X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/dab3ca1324288a1abeb32590e1caec8848efe3e0..f35283ae4398fef78d72204142554689979a7bb6:/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch?ds=sidebyside diff --git a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch index 76e90584d..966382ad4 100644 --- a/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch +++ b/target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch @@ -1,44 +1,44 @@ -diff -urN linux.old/arch/mips/kernel/genex.S linux.dev/arch/mips/kernel/genex.S ---- linux.old/arch/mips/kernel/genex.S 2005-12-04 06:10:42.000000000 +0100 -+++ linux.dev/arch/mips/kernel/genex.S 2005-12-18 05:30:48.564937750 +0100 -@@ -72,6 +72,10 @@ +diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kernel/genex.S +--- linux-2.6.17/arch/mips/kernel/genex.S 2006-06-18 03:49:35.000000000 +0200 ++++ linux-2.6.17-owrt/arch/mips/kernel/genex.S 2006-06-18 15:36:58.000000000 +0200 +@@ -73,6 +73,10 @@ .set push .set mips3 .set noat -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + nop + nop +#endif mfc0 k1, CP0_CAUSE li k0, 31<<2 andi k1, k1, 0x7c -diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c ---- linux.old/arch/mips/mm/c-r4k.c 2005-12-04 06:10:42.000000000 +0100 -+++ linux.dev/arch/mips/mm/c-r4k.c 2005-12-18 06:08:19.112437750 +0100 +diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k.c +--- linux-2.6.17/arch/mips/mm/c-r4k.c 2006-06-18 03:49:35.000000000 +0200 ++++ linux-2.6.17-owrt/arch/mips/mm/c-r4k.c 2006-06-18 15:36:58.000000000 +0200 @@ -14,6 +14,12 @@ #include #include -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +#include "../bcm947xx/include/typedefs.h" +#include "../bcm947xx/include/sbconfig.h" ++#include "../bcm947xx/include/mipsinc.h" +#include +#endif -+ #include #include #include -@@ -29,6 +35,9 @@ - #include +@@ -30,6 +36,9 @@ #include /* for run_uncached() */ + +/* For enabling BCM4710 cache workarounds */ +int bcm4710 = 0; + /* - * Must die. - */ -@@ -73,7 +82,9 @@ + * Special Variant of smp_call_function for use by cache functions: + * +@@ -94,7 +103,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); @@ -49,7 +49,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c r4k_blast_dcache_page = blast_dcache16_page; else if (dc_lsize == 32) r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; -@@ -85,7 +96,9 @@ +@@ -106,7 +117,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); @@ -60,7 +60,7 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; else if (dc_lsize == 32) r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; -@@ -97,7 +110,9 @@ +@@ -118,7 +131,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); @@ -71,52 +71,20 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c r4k_blast_dcache = blast_dcache16; else if (dc_lsize == 32) r4k_blast_dcache = blast_dcache32; -@@ -486,6 +501,9 @@ - addr = start & ~(dc_lsize - 1); - aend = (end - 1) & ~(dc_lsize - 1); - -+ BCM4710_PROTECTED_FILL_TLB(addr); -+ BCM4710_PROTECTED_FILL_TLB(aend); -+ - while (1) { - /* Hit_Writeback_Inv_D */ - protected_writeback_dcache_line(addr); -@@ -657,6 +675,10 @@ - R4600_HIT_CACHEOP_WAR_IMPL; - a = addr & ~(dc_lsize - 1); - end = (addr + size - 1) & ~(dc_lsize - 1); -+ -+ BCM4710_FILL_TLB(a); -+ BCM4710_FILL_TLB(end); -+ - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) -@@ -702,6 +724,10 @@ - R4600_HIT_CACHEOP_WAR_IMPL; - a = addr & ~(dc_lsize - 1); - end = (addr + size - 1) & ~(dc_lsize - 1); -+ -+ BCM4710_FILL_TLB(a); -+ BCM4710_FILL_TLB(end); -+ - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) -@@ -727,6 +753,8 @@ +@@ -683,6 +698,8 @@ unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; + BCM4710_PROTECTED_FILL_TLB(addr); + BCM4710_PROTECTED_FILL_TLB(addr + 4); protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - if (!cpu_icache_snoops_remote_store) + if (!cpu_icache_snoops_remote_store && scache_size) protected_writeback_scache_line(addr & ~(sc_lsize - 1)); -@@ -1202,6 +1230,16 @@ +@@ -1189,6 +1206,16 @@ static inline void coherency_setup(void) { change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); -+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365) ++#ifdef CONFIG_BCM947XX + if (BCM330X(current_cpu_data.processor_id)) { + __u32 cm = read_c0_diag(); + /* Enable icache */ @@ -129,13 +97,13 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c /* * c0_status.cu=0 specifies that updates by the sc instruction use -@@ -1231,6 +1269,15 @@ +@@ -1227,6 +1254,15 @@ /* Default cache error handler for R4000 and R5000 family */ set_uncached_handler (0x100, &except_vec2_generic, 0x80); + + /* Check if special workarounds are required */ -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) { + printk("Enabling BCM4710A0 cache workarounds.\n"); + bcm4710 = 1; @@ -145,25 +113,25 @@ diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c probe_pcache(); setup_scache(); -diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c ---- linux.old/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100 -+++ linux.dev/arch/mips/mm/tlbex.c 2005-12-18 06:06:17.916863500 +0100 -@@ -28,6 +28,10 @@ +diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c +--- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 15:34:19.000000000 +0200 ++++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 15:36:58.000000000 +0200 +@@ -38,6 +38,10 @@ /* #define DEBUG_TLB */ -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +extern int bcm4710; +#endif + static __init int __attribute__((unused)) r45k_bvahwbug(void) { /* XXX: We should probe for the presence of this bug, but we don't. */ -@@ -1152,6 +1156,12 @@ +@@ -1184,6 +1188,12 @@ memset(relocs, 0, sizeof(relocs)); memset(final_handler, 0, sizeof(final_handler)); -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + if (bcm4710) { + i_nop(&p); + } @@ -172,14 +140,14 @@ diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c /* * create the plain linear handler */ -diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h ---- linux.old/include/asm-mips/r4kcache.h 2005-12-17 22:39:19.281320000 +0100 -+++ linux.dev/include/asm-mips/r4kcache.h 2005-12-18 05:22:06.020280750 +0100 -@@ -15,6 +15,18 @@ - #include - #include +diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm-mips/r4kcache.h +--- linux-2.6.17/include/asm-mips/r4kcache.h 2006-06-18 03:49:35.000000000 +0200 ++++ linux-2.6.17-owrt/include/asm-mips/r4kcache.h 2006-06-18 15:56:57.000000000 +0200 +@@ -17,6 +17,18 @@ + #include + #include -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate) + +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) @@ -194,37 +162,47 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca /* * This macro return a properly sign-extended address suitable as base address * for indexed cache operations. Two issues here: -@@ -45,6 +57,7 @@ - +@@ -150,6 +162,7 @@ static inline void flush_dcache_line_indexed(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Index_Writeback_Inv_D, addr); + __dflush_epilogue } - -@@ -60,11 +73,13 @@ - +@@ -169,6 +182,7 @@ static inline void flush_dcache_line(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Hit_Writeback_Inv_D, addr); + __dflush_epilogue } - +@@ -176,6 +190,7 @@ static inline void invalidate_dcache_line(unsigned long addr) { + __dflush_prologue + BCM4710_DUMMY_RREG(); cache_op(Hit_Invalidate_D, addr); + __dflush_epilogue + } +@@ -208,6 +223,7 @@ + */ + static inline void protected_flush_icache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + protected_cache_op(Hit_Invalidate_I, addr); } -@@ -104,6 +119,7 @@ +@@ -219,6 +235,7 @@ */ static inline void protected_writeback_dcache_line(unsigned long addr) { + BCM4710_DUMMY_RREG(); - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" -@@ -166,6 +182,49 @@ + protected_cache_op(Hit_Writeback_Inv_D, addr); + } + +@@ -339,8 +356,52 @@ : "r" (base), \ "i" (op)); @@ -271,43 +249,103 @@ diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kca + } +} + - static inline void blast_dcache16(void) - { - unsigned long start = INDEX_BASE; -@@ -213,7 +272,8 @@ - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; -- -+ -+ BCM4710_FILL_TLB(start); - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -@@ -357,6 +417,7 @@ - current_cpu_data.icache.waybit; - unsigned long ws, addr; ++ + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ ++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \ + static inline void blast_##pfx##cache##lsize(void) \ + { \ + unsigned long start = INDEX_BASE; \ +@@ -352,6 +413,7 @@ + \ + __##pfx##flush_prologue \ + \ ++ war \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws,indexop); \ +@@ -366,6 +428,7 @@ + \ + __##pfx##flush_prologue \ + \ ++ war \ + do { \ + cache##lsize##_unroll32(start,hitop); \ + start += lsize * 32; \ +@@ -384,6 +447,8 @@ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ ++ war \ ++ \ + __##pfx##flush_prologue \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ +@@ -393,24 +458,25 @@ + __##pfx##flush_epilogue \ + } -+ BCM4710_FILL_TLB(start); - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -@@ -471,6 +532,7 @@ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) -+ BCM4710_FILL_TLB(start); - do { - cache64_unroll32(start,Hit_Invalidate_I); - start += 0x800; -diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h ---- linux.old/include/asm-mips/stackframe.h 2005-12-04 06:10:42.000000000 +0100 -+++ linux.dev/include/asm-mips/stackframe.h 2005-12-18 05:33:02.405302250 +0100 -@@ -285,6 +285,10 @@ + /* build blast_xxx_range, protected_blast_xxx_range */ +-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ ++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war) \ + static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ + { \ + unsigned long lsize = cpu_##desc##_line_size(); \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ ++ war \ + \ + __##pfx##flush_prologue \ + \ +@@ -424,13 +490,13 @@ + __##pfx##flush_epilogue \ + } + +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) + /* blast_inv_dcache_range */ +-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) +-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) ++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) ++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) + + #endif /* _ASM_R4KCACHE_H */ +diff -Nur linux-2.6.17/include/asm-mips/stackframe.h linux-2.6.17-owrt/include/asm-mips/stackframe.h +--- linux-2.6.17/include/asm-mips/stackframe.h 2006-06-18 03:49:35.000000000 +0200 ++++ linux-2.6.17-owrt/include/asm-mips/stackframe.h 2006-06-18 15:36:58.000000000 +0200 +@@ -361,6 +361,10 @@ .macro RESTORE_SP_AND_RET LONG_L sp, PT_R29(sp) .set mips3 -+#ifdef CONFIG_BCM4710 ++#ifdef CONFIG_BCM947XX + nop + nop +#endif