X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/dc54bc58f3a3368dc6735c7263560eaee700bb53..98a41238633bc693110f1a93fa71cc0b950f574e:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index a9f288b27..46629327c 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -32,6 +32,8 @@
 #define AR71XX_EHCI_SIZE	0x01000000
 #define AR71XX_OHCI_BASE	0x1c000000
 #define AR71XX_OHCI_SIZE	0x01000000
+#define AR7240_OHCI_BASE	0x1b000000
+#define AR7240_OHCI_SIZE	0x01000000
 #define AR71XX_SPI_BASE		0x1f000000
 #define AR71XX_SPI_SIZE		0x01000000
 
@@ -253,7 +255,25 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
 
 #define AR71XX_GPIO_COUNT	16
 
-#define AR724X_GPIO_COUNT	16
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)
+
+#define AR724X_GPIO_COUNT	18
 
 #define AR91XX_GPIO_FUNC_WMAC_LED_EN	BIT(22)
 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN	BIT(21)
@@ -302,6 +322,8 @@ void ar71xx_gpio_function_disable(u32 mask);
 
 #define AR724X_DDR_REG_FLUSH_GE0	0x7c
 #define AR724X_DDR_REG_FLUSH_GE1	0x80
+#define AR724X_DDR_REG_FLUSH_USB	0x84
+#define AR724X_DDR_REG_FLUSH_PCIE	0x88
 
 #define AR91XX_DDR_REG_FLUSH_GE0	0x7c
 #define AR91XX_DDR_REG_FLUSH_GE1	0x80
@@ -448,6 +470,7 @@ static inline u32 ar724x_pci_rr(unsigned reg)
 #define RESET_MODULE_USB_OHCI_DLL	BIT(6)
 #define RESET_MODULE_USB_HOST		BIT(5)
 #define RESET_MODULE_USB_PHY		BIT(4)
+#define RESET_MODULE_USB_OHCI_DLL_7240	BIT(3)
 #define RESET_MODULE_PCI_BUS		BIT(1)
 #define RESET_MODULE_PCI_CORE		BIT(0)