X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/dc79249b1b34785a26444c60e5515608330817ec..9959eb47d18f7715b8159ca3f401ea9f657e5b74:/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index 6a922436c..0b150db87 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -24,6 +24,11 @@
 					CKCTL_6338_SAR_EN |		\
 					CKCTL_6338_SPI_EN)
 
+#define CKCTL_6345_CPU_EN		(1 << 0)
+#define CKCTL_6345_UART_EN		(1 << 3)
+#define CKCTL_6345_ENET_EN		(1 << 7)
+#define CKCTL_6345_USBH_EN		(1 << 8)
+
 #define CKCTL_6348_ADSLPHY_EN		(1 << 0)
 #define CKCTL_6348_MPI_EN		(1 << 1)
 #define CKCTL_6348_SDRAM_EN		(1 << 2)
@@ -757,7 +762,7 @@
  *************************************************************************/
 
 /* BCM 6338 SPI core */
-#define SPI_BCM_6338_SPI_CMD		0x00
+#define SPI_BCM_6338_SPI_CMD		0x00	/* 16-bits register */
 #define SPI_BCM_6338_SPI_INT_STATUS	0x02
 #define SPI_BCM_6338_SPI_MASK_INT_ST	0x03
 #define SPI_BCM_6338_SPI_INT_MASK	0x04
@@ -773,24 +778,31 @@
 #define SPI_BCM_6338_SPI_RX_DATA_SIZE	0x3f
 
 /* BCM 6348 SPI core */
-#define SPI_BCM_6348_SPI_CMD1		0x00
-#define SPI_BCM_6348_SPI_CMD2		0x04
-#define SPI_BCM_6348_SPI_TAIL		0x08
+#define SPI_BCM_6348_SPI_MASK_INT_ST	0x00
+#define SPI_BCM_6348_SPI_INT_STATUS	0x01
+#define SPI_BCM_6348_SPI_CMD		0x02	/* 16-bits register */
+#define SPI_BCM_6348_SPI_FILL_BYTE	0x04
+#define SPI_BCM_6348_SPI_CLK_CFG	0x05
+#define SPI_BCM_6348_SPI_ST		0x06
+#define SPI_BCM_6348_SPI_INT_MASK	0x07
+#define SPI_BCM_6348_SPI_RX_TAIL	0x08
+#define SPI_BCM_6348_SPI_MSG_TAIL	0x10
 #define SPI_BCM_6348_SPI_MSG_DATA	0x40
+#define SPI_BCM_6348_SPI_MSG_CTL	0x42
 #define SPI_BCM_6348_SPI_MSG_DATA_SIZE	0x3f
 #define SPI_BCM_6348_SPI_RX_DATA	0x80
 #define SPI_BCM_6348_SPI_RX_DATA_SIZE	0x3f
 
 /* BCM 6358 SPI core */
-#define SPI_BCM_6358_MSG_CTL		0x00
+#define SPI_BCM_6358_MSG_CTL		0x00	/* 16-bits register */
 
 #define SPI_BCM_6358_SPI_MSG_DATA	0x02
 #define SPI_BCM_6358_SPI_MSG_DATA_SIZE	0x21e
 
-#define SPI_BCM_6358_SPI_RX_FIFO	0x400
-#define SPI_BCM_6358_SPI_RX_FIFO_SIZE	0x220
+#define SPI_BCM_6358_SPI_RX_DATA	0x400
+#define SPI_BCM_6358_SPI_RX_DATA_SIZE	0x220
 
-#define SPI_BCM_6358_SPI_CMD		0x700
+#define SPI_BCM_6358_SPI_CMD		0x700	/* 16-bits register */
 
 #define SPI_BCM_6358_SPI_INT_STATUS	0x702
 #define SPI_BCM_6358_SPI_MASK_INT_ST	0x703
@@ -808,16 +820,17 @@
 /* Shared SPI definitions */
 
 /* Message configuration */
-#define SPI_FD_RW			0
-#define SPI_HD_W			1
-#define SPI_HD_R			2
+#define SPI_FD_RW			0x00
+#define SPI_HD_W			0x01
+#define SPI_HD_R			0x02
+#define SPI_BYTE_CNT_SHIFT		0
 #define SPI_MSG_TYPE_SHIFT		14
 
 /* Command */
-#define SPI_CMD_NOOP			0
-#define SPI_CMD_SOFT_RESET		1
-#define SPI_CMD_HARD_RESET		2
-#define SPI_CMD_START_IMMEDIATE		3
+#define SPI_CMD_NOOP			0x01
+#define SPI_CMD_SOFT_RESET		0x02
+#define SPI_CMD_HARD_RESET		0x04
+#define SPI_CMD_START_IMMEDIATE		0x08
 #define SPI_CMD_COMMAND_SHIFT		0
 #define SPI_CMD_COMMAND_MASK		0x000f
 #define SPI_CMD_DEVICE_ID_SHIFT		4
@@ -843,12 +856,14 @@
 #define SPI_SERIAL_BUSY			0x08
 
 /* Clock configuration */
-#define SPI_CLK_0_391MHZ		1
-#define SPI_CLK_0_781MHZ		2 /* default */
-#define SPI_CLK_1_563MHZ		3
-#define SPI_CLK_3_125MHZ		4
-#define SPI_CLK_6_250MHZ		5
-#define SPI_CLK_12_50MHZ		6
+#define SPI_CLK_20MHZ			0x00
+#define SPI_CLK_0_391MHZ		0x01
+#define SPI_CLK_0_781MHZ		0x02 /* default */
+#define SPI_CLK_1_563MHZ		0x03
+#define SPI_CLK_3_125MHZ		0x04
+#define SPI_CLK_6_250MHZ		0x05
+#define SPI_CLK_12_50MHZ		0x06
+#define SPI_CLK_25MHZ			0x07
 #define SPI_CLK_MASK			0x07
 #define SPI_SSOFFTIME_MASK		0x38
 #define SPI_SSOFFTIME_SHIFT		3