X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/e2b1c817e6a9e2cfb26f27467ca85ac43b194862..1ff112ddd2ee9f48859bf09e96289acb20bd6ac1:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 00e7cbc4b..c6a5a4099 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -79,8 +79,7 @@
 #define AR71XX_PCI_IRQ_BASE     48
 #define AR71XX_PCI_IRQ_COUNT	8
 
-#define AR71XX_CPU_IRQ_PCI	(AR71XX_CPU_IRQ_BASE + 2)
-#define AR71XX_CPU_IRQ_WMAC	(AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_IP2	(AR71XX_CPU_IRQ_BASE + 2)
 #define AR71XX_CPU_IRQ_USB	(AR71XX_CPU_IRQ_BASE + 3)
 #define AR71XX_CPU_IRQ_GE0	(AR71XX_CPU_IRQ_BASE + 4)
 #define AR71XX_CPU_IRQ_GE1	(AR71XX_CPU_IRQ_BASE + 5)
@@ -113,6 +112,8 @@ enum ar71xx_soc_type {
 	AR71XX_SOC_AR7141,
 	AR71XX_SOC_AR7161,
 	AR71XX_SOC_AR7240,
+	AR71XX_SOC_AR7241,
+	AR71XX_SOC_AR7242,
 	AR71XX_SOC_AR9130,
 	AR71XX_SOC_AR9132
 };
@@ -269,6 +270,7 @@ static inline u32 ar71xx_gpio_rr(unsigned reg)
 void ar71xx_gpio_init(void) __init;
 void ar71xx_gpio_function_enable(u32 mask);
 void ar71xx_gpio_function_disable(u32 mask);
+void ar71xx_gpio_function_setup(u32 set, u32 clear);
 
 /*
  * DDR_CTRL block
@@ -353,37 +355,10 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR724X_PCI_REG_INT_MASK		0x50
 
 #define AR724X_PCI_APP_LTSSM_ENABLE	BIT(0)
+#define AR724X_PCI_RESET_LINK_UP	BIT(0)
 
 #define AR724X_PCI_INT_DEV0		BIT(14)
 
-static inline void ar724x_pci_wr(unsigned reg, u32 val)
-{
-	void __iomem *base;
-
-	base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
-	__raw_writel(val, base + reg);
-	iounmap(base);
-}
-
-static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
-{
-	void __iomem *base;
-
-	base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
-	iounmap(base);
-}
-
-static inline u32 ar724x_pci_rr(unsigned reg)
-{
-	void __iomem *base;
-	u32 ret;
-
-	base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
-	ret = __raw_readl(base + reg);
-	iounmap(base);
-	return ret;
-}
-
 /*
  * RESET block
  */
@@ -452,14 +427,18 @@ static inline u32 ar724x_pci_rr(unsigned reg)
 #define RESET_MODULE_PCI_BUS		BIT(1)
 #define RESET_MODULE_PCI_CORE		BIT(0)
 
+#define AR724X_RESET_GE1_MDIO		BIT(23)
+#define AR724X_RESET_GE0_MDIO		BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
 #define AR724X_RESET_PCIE_PHY		BIT(7)
 #define AR724X_RESET_PCIE		BIT(6)
 
-#define REV_ID_MAJOR_MASK	0xf0
-#define REV_ID_MAJOR_AR71XX	0xa0
-#define REV_ID_MAJOR_AR913X	0xb0
-#define REV_ID_MAJOR_AR724X	0xc0
+#define REV_ID_MAJOR_MASK	0xfff0
+#define REV_ID_MAJOR_AR71XX	0x00a0
+#define REV_ID_MAJOR_AR913X	0x00b0
+#define REV_ID_MAJOR_AR7240	0x00c0
+#define REV_ID_MAJOR_AR7241	0x0100
+#define REV_ID_MAJOR_AR7242	0x1100
 
 #define AR71XX_REV_ID_MINOR_MASK	0x3
 #define AR71XX_REV_ID_MINOR_AR7130	0x0