X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/e2b1c817e6a9e2cfb26f27467ca85ac43b194862..2fb031808cacd96ffda49e84987899e8e95502de:/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 00e7cbc4b..97ac835dc 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -1,10 +1,12 @@ /* * Atheros AR71xx SoC specific definitions * + * Copyright (C) 2010-2011 Jaiganesh Narayanan * Copyright (C) 2008-2009 Gabor Juhos * Copyright (C) 2008 Imre Kaloz * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -68,19 +70,28 @@ #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) #define AR91XX_WMAC_SIZE 0x30000 +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 + +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 + #define AR71XX_MEM_SIZE_MIN 0x0200000 #define AR71XX_MEM_SIZE_MAX 0x10000000 #define AR71XX_CPU_IRQ_BASE 0 #define AR71XX_MISC_IRQ_BASE 8 -#define AR71XX_MISC_IRQ_COUNT 8 -#define AR71XX_GPIO_IRQ_BASE 16 +#define AR71XX_MISC_IRQ_COUNT 32 +#define AR71XX_GPIO_IRQ_BASE 40 #define AR71XX_GPIO_IRQ_COUNT 32 -#define AR71XX_PCI_IRQ_BASE 48 +#define AR71XX_PCI_IRQ_BASE 72 #define AR71XX_PCI_IRQ_COUNT 8 -#define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2) -#define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2) +#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) @@ -95,6 +106,11 @@ #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) +#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) +#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) +#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) +#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) +#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) @@ -106,6 +122,7 @@ extern u32 ar71xx_ahb_freq; extern u32 ar71xx_cpu_freq; extern u32 ar71xx_ddr_freq; +extern u32 ar71xx_ref_freq; enum ar71xx_soc_type { AR71XX_SOC_UNKNOWN, @@ -113,9 +130,17 @@ enum ar71xx_soc_type { AR71XX_SOC_AR7141, AR71XX_SOC_AR7161, AR71XX_SOC_AR7240, + AR71XX_SOC_AR7241, + AR71XX_SOC_AR7242, AR71XX_SOC_AR9130, - AR71XX_SOC_AR9132 + AR71XX_SOC_AR9132, + AR71XX_SOC_AR9330, + AR71XX_SOC_AR9331, + AR71XX_SOC_AR9341, + AR71XX_SOC_AR9342, + AR71XX_SOC_AR9344, }; +extern u32 ar71xx_soc_rev; extern enum ar71xx_soc_type ar71xx_soc; @@ -151,6 +176,8 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR724X_DDR_DIV_SHIFT 22 #define AR724X_DDR_DIV_MASK 0x3 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + #define AR91XX_PLL_REG_CPU_CONFIG 0x00 #define AR91XX_PLL_REG_ETH_CONFIG 0x04 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 @@ -166,6 +193,185 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR91XX_ETH0_PLL_SHIFT 20 #define AR91XX_ETH1_PLL_SHIFT 22 +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_REG_CPU_CONFIG 0x00 +#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 + +#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 +#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19 +#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000 + +#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \ + AR934X_CPU_PLL_CFG_OUTDIV_LSB) + +#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25 +#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23 +#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000 + +#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \ + AR934X_DDR_PLL_CFG_OUTDIV_LSB) + +#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \ + AR934X_DDR_PLL_CFG_OUTDIV_MASK) + +#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16 +#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12 +#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000 + +#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \ + AR934X_CPU_PLL_CFG_REFDIV_LSB) + +#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \ + AR934X_CPU_PLL_CFG_REFDIV_MASK) + +#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2 + +#define AR934X_CPU_PLL_CFG_NINT_MSB 11 +#define AR934X_CPU_PLL_CFG_NINT_LSB 6 +#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0 + +#define AR934X_CPU_PLL_CFG_NINT_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \ + AR934X_CPU_PLL_CFG_NINT_LSB) + +#define AR934X_CPU_PLL_CFG_NINT_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \ + AR934X_CPU_PLL_CFG_NINT_MASK) + +#define AR934X_CPU_PLL_CFG_NINT_RESET 20 + +#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5 +#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0 +#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f + +#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \ + (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \ + AR934X_CPU_PLL_CFG_NFRAC_LSB) + +#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \ + (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \ + AR934X_CPU_PLL_CFG_NFRAC_MASK) + +#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20 +#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16 +#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000 + +#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \ + AR934X_DDR_PLL_CFG_REFDIV_LSB) + +#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \ + AR934X_DDR_PLL_CFG_REFDIV_MASK) + +#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2 + +#define AR934X_DDR_PLL_CFG_NINT_MSB 15 +#define AR934X_DDR_PLL_CFG_NINT_LSB 10 +#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00 + +#define AR934X_DDR_PLL_CFG_NINT_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \ + AR934X_DDR_PLL_CFG_NINT_LSB) + +#define AR934X_DDR_PLL_CFG_NINT_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \ + AR934X_DDR_PLL_CFG_NINT_MASK) + +#define AR934X_DDR_PLL_CFG_NINT_RESET 20 + +#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9 +#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0 +#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff + +#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \ + (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \ + AR934X_DDR_PLL_CFG_NFRAC_LSB) + +#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \ + (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \ + AR934X_DDR_PLL_CFG_NFRAC_MASK) + +#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512 + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19 +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15 +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000 + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14 +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10 +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00 + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9 +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5 +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0 + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0 + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24 +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24 +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \ + (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \ + AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \ + (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \ + AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) + +#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 + extern void __iomem *ar71xx_pll_base; static inline void ar71xx_pll_wr(unsigned reg, u32 val) @@ -254,6 +460,14 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) #define AR91XX_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 + +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) + +#define AR934X_GPIO_COUNT 32 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) + extern void __iomem *ar71xx_gpio_base; static inline void ar71xx_gpio_wr(unsigned reg, u32 value) @@ -269,6 +483,7 @@ static inline u32 ar71xx_gpio_rr(unsigned reg) void ar71xx_gpio_init(void) __init; void ar71xx_gpio_function_enable(u32 mask); void ar71xx_gpio_function_disable(u32 mask); +void ar71xx_gpio_function_setup(u32 set, u32 clear); /* * DDR_CTRL block @@ -296,6 +511,17 @@ void ar71xx_gpio_function_disable(u32 mask); #define AR91XX_DDR_REG_FLUSH_USB 0x84 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 + + #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 #define PCI_WIN2_OFFS 0x12000000 @@ -353,37 +579,10 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_PCI_REG_INT_MASK 0x50 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) +#define AR724X_PCI_RESET_LINK_UP BIT(0) #define AR724X_PCI_INT_DEV0 BIT(14) -static inline void ar724x_pci_wr(unsigned reg, u32 val) -{ - void __iomem *base; - - base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); - __raw_writel(val, base + reg); - iounmap(base); -} - -static inline void ar724x_pci_wr_nf(unsigned reg, u32 val) -{ - void __iomem *base; - - base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); - iounmap(base); -} - -static inline u32 ar724x_pci_rr(unsigned reg) -{ - void __iomem *base; - u32 ret; - - base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE); - ret = __raw_readl(base + reg); - iounmap(base); - return ret; -} - /* * RESET block */ @@ -410,6 +609,16 @@ static inline u32 ar724x_pci_rr(unsigned reg) #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +/* 0 - 25MHz 1 - 40 MHz */ +#define AR934X_REF_CLK_40 (1 << 4) + #define WDOG_CTRL_LAST_RESET BIT(31) #define WDOG_CTRL_ACTION_MASK 3 #define WDOG_CTRL_ACTION_NONE 0 /* no action */ @@ -417,6 +626,11 @@ static inline u32 ar724x_pci_rr(unsigned reg) #define WDOG_CTRL_ACTION_NMI 2 /* NMI */ #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ +#define MISC_INT_ENET_LINK BIT(12) +#define MISC_INT_DDR_PERF BIT(11) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) #define MISC_INT_DMA BIT(7) #define MISC_INT_OHCI BIT(6) #define MISC_INT_PERFC BIT(5) @@ -452,14 +666,35 @@ static inline u32 ar724x_pci_rr(unsigned reg) #define RESET_MODULE_PCI_BUS BIT(1) #define RESET_MODULE_PCI_CORE BIT(0) +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) #define AR724X_RESET_PCIE_PHY BIT(7) #define AR724X_RESET_PCIE BIT(6) - -#define REV_ID_MAJOR_MASK 0xf0 -#define REV_ID_MAJOR_AR71XX 0xa0 -#define REV_ID_MAJOR_AR913X 0xb0 -#define REV_ID_MAJOR_AR724X 0xc0 +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 @@ -476,6 +711,10 @@ static inline u32 ar724x_pci_rr(unsigned reg) #define AR724X_REV_ID_REVISION_MASK 0x3 +#define AR933X_REV_ID_REVISION_MASK 0xf + +#define AR934X_REV_ID_REVISION_MASK 0xf + extern void __iomem *ar71xx_reset_base; static inline void ar71xx_reset_wr(unsigned reg, u32 val) @@ -490,6 +729,7 @@ static inline u32 ar71xx_reset_rr(unsigned reg) void ar71xx_device_stop(u32 mask); void ar71xx_device_start(u32 mask); +void ar71xx_device_reset_rmw(u32 clear, u32 set); int ar71xx_device_stopped(u32 mask); /* @@ -530,6 +770,23 @@ void ar71xx_flash_release(void); #define MII1_CTRL_IF_RGMII 0 #define MII1_CTRL_IF_RMII 1 +/* + * AR933X GMAC + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + #endif /* __ASSEMBLER__ */ #endif /* __ASM_MACH_AR71XX_H */