X-Git-Url: https://git.rohieb.name/openwrt.git/blobdiff_plain/eeab7aa026971e3db3dcb17ba0366937466f1934..3a065a453ff58430b6915b58cf542e81d143ae3e:/target/linux/rdc-2.6/files/drivers/net/r6040.c

diff --git a/target/linux/rdc-2.6/files/drivers/net/r6040.c b/target/linux/rdc-2.6/files/drivers/net/r6040.c
index de58e657b..376b6ecfe 100644
--- a/target/linux/rdc-2.6/files/drivers/net/r6040.c
+++ b/target/linux/rdc-2.6/files/drivers/net/r6040.c
@@ -617,9 +617,6 @@ r6040_close(struct net_device *dev)
 	return 0;
 }
 
-#define DMZ_GPIO	1
-#define RDC3210_CFGREG_ADDR	0x0CF8
-#define RDC3210_CFGREG_DATA	0x0CFC
 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct r6040_private *lp = dev->priv;
@@ -641,27 +638,8 @@ static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
 		if(args[0]&(1<<27))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x2000));	/* port 2 */
 		if(args[0]&(1<<25))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x0020));	/* port 3 */
 
-		/* DMZ LED */
-		val = 0x80000000 | (7 << 11) | ((0x48));
-		outl(val, RDC3210_CFGREG_ADDR);
-		udelay(10);
-		val = inl(RDC3210_CFGREG_DATA);
-
-		val |= (0x1 << DMZ_GPIO);
-		outl(val, RDC3210_CFGREG_DATA);
-		udelay(10);
-
-		val = 0x80000000 | (7 << 11) | ((0x4C));
-		outl(val, RDC3210_CFGREG_ADDR);
-		udelay(10);
-		val = inl(RDC3210_CFGREG_DATA);
-		if(args[0]&(1<<23))	/* DMZ enabled */
-			val &= ~(0x1 << DMZ_GPIO);	/* low activated */
-		else val |= (0x1 << DMZ_GPIO);
-		outl(val, RDC3210_CFGREG_DATA);
-		udelay(10);
-	}
-	return 0;
+	} 
+	return -EOPNOTSUPP;
 }
 
 /**
@@ -861,18 +839,19 @@ for (i = 0; i < RX_DCNT; i++) {
 	outw(MAX_BUF_SIZE, ioaddr+0x18);
 
 	if ((lp->switch_sig = phy_read(ioaddr, 0, 2)) == 0x0243)	// ICPlus IP175C Signature
-{
-	phy_write(ioaddr, 29,31, 0x175C);	//Enable registers
-	lp->phy_mode = 0x8000;
-} else {
-	/* PHY Mode Check */
-	phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
-	phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
-
-	if (PHY_MODE == 0x3100) 
-		lp->phy_mode = phy_mode_chk(dev);
-	else lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
-}
+	{
+		phy_write(ioaddr, 29,31, 0x175C);	//Enable registers
+		lp->phy_mode = 0x8000;
+	} else {
+		/* PHY Mode Check */
+		phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
+		phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
+
+		if (PHY_MODE == 0x3100)
+			lp->phy_mode = phy_mode_chk(dev);
+		else
+			lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
+	}
 	/* MAC Bus Control Register */
 	outw(MBCR_DEFAULT, ioaddr+0x8);
 
@@ -880,6 +859,16 @@ for (i = 0; i < RX_DCNT; i++) {
 	lp->mcr0 |= lp->phy_mode;
 	outw(lp->mcr0, ioaddr);
 
+	/* set interrupt waiting time and packet numbers */
+	outw(0x0802, ioaddr + 0x0C);
+	outw(0x0802, ioaddr + 0x10);
+
+	/* upgrade performance (by RDC guys) */
+	phy_write(ioaddr,30,17,(phy_read(ioaddr,30,17)|0x4000));        //bit 14=1
+	phy_write(ioaddr,30,17,~((~phy_read(ioaddr,30,17))|0x2000));    //bit 13=0
+	phy_write(ioaddr,0,19,0x0000);
+	phy_write(ioaddr,0,30,0x01F0);
+
 	/* Interrupt Mask Register */
 	outw(R6040_INT_MASK, ioaddr + 0x40);
 }