removed volatile register derefs from amazon setup code

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8334 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c b/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c
index 4cd3b9b..a96b565 100644 (file)
--- a/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c
+++ b/target/linux/amazon-2.6/files/arch/mips/amazon/setup.c
@@ -18,6 +18,7 @@
  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  *
  */
  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  *
  */

+

 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/module.h>


@@ -44,7 +45,7 @@ unsigned int amazon_get_cpu_hz(void)
        /*-----------------------------------*/
        /**CGU CPU Clock Reduction Register***/ 
        /*-----------------------------------*/
        /*-----------------------------------*/
        /**CGU CPU Clock Reduction Register***/ 
        /*-----------------------------------*/

-       switch((*AMAZON_CGU_CPUCRD) & 0x3){
+       switch(amazon_readl(AMAZON_CGU_CPUCRD) & 0x3){

                case 0:
                        /*divider ration 1/1, 235 MHz clock */
                        return 235000000;
                case 0:
                        /*divider ration 1/1, 235 MHz clock */
                        return 235000000;


@@ -69,7 +70,7 @@ unsigned int amazon_get_fpi_hz(void)
        /*-------------------------------------*/
        /***CGU Clock Divider Select Register***/
        /*-------------------------------------*/
        /*-------------------------------------*/
        /***CGU Clock Divider Select Register***/
        /*-------------------------------------*/

-       switch ((*AMAZON_CGU_DIV) & 0x3)
+       switch (amazon_readl(AMAZON_CGU_DIV) & 0x3)

        {
                case 1:
                        return clkCPU >> 1;
        {
                case 1:
                        return clkCPU >> 1;


@@ -81,20 +82,19 @@ unsigned int amazon_get_fpi_hz(void)
        }
 }
 
        }
 }
 

-/* get the CPU version number  - based on sysLib.c from VxWorks sources */

 /* this doesn't really belong here, but it's a convenient location */
 unsigned int amazon_get_cpu_ver(void)
 {
        static unsigned int cpu_ver = 0;
        if (cpu_ver == 0)
 /* this doesn't really belong here, but it's a convenient location */
 unsigned int amazon_get_cpu_ver(void)
 {
        static unsigned int cpu_ver = 0;
        if (cpu_ver == 0)

-               cpu_ver = *AMAZON_MCD_CHIPID & 0xFFFFF000;
+               cpu_ver = amazon_readl(AMAZON_MCD_CHIPID) & 0xFFFFF000;

        return cpu_ver;
 }
 
 void amazon_time_init(void)
 {
        mips_hpt_frequency = amazon_get_cpu_hz()/2;
        return cpu_ver;
 }
 
 void amazon_time_init(void)
 {
        mips_hpt_frequency = amazon_get_cpu_hz()/2;

-       printk("mips_hpt_frequency:%d\n",mips_hpt_frequency);
+       printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);

 }
 
 extern int hr_time_resolution;
 }
 
 extern int hr_time_resolution;


@@ -121,43 +121,13 @@ void __init plat_timer_setup(struct irqaction *irq)
        /* cpu counter for timer interrupts */
        setup_irq(MIPS_CPU_TIMER_IRQ, irq);
 
        /* cpu counter for timer interrupts */
        setup_irq(MIPS_CPU_TIMER_IRQ, irq);
 

-#if 0
-       /* to generate the first CPU timer interrupt */
-       write_c0_compare(read_c0_count() + amazon_get_cpu_hz()/(2*HZ));
-#endif
-

        /* enable the timer in the PMU */
        /* enable the timer in the PMU */

-       *(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;
-       /* setup the GPTU for timer tick  f_fpi == f_gptu*/
-       *(AMAZON_GPTU_CLC) = 0x100;
-
-       *(AMAZON_GPTU_CAPREL) = 0xffff;
-       *(AMAZON_GPTU_T6CON) = 0x80C0;
-       //setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
-
-#if 0
-#ifdef CONFIG_HIGH_RES_TIMERS
-       /* GPTU timer 6 */
-       int retval;
-       if ( hr_time_resolution > 200000000 || hr_time_resolution < 40) {
-               prom_printf("hr_time_resolution is out of range, HIGH_RES_TIMER is diabled.\n");
-               return;
-       }
+       amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR);

        
        

-       /* enable the timer in the PMU */
-        *(AMAZON_PMU_PWDCR) = (*(AMAZON_PMU_PWDCR))| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI;

        /* setup the GPTU for timer tick  f_fpi == f_gptu*/
        /* setup the GPTU for timer tick  f_fpi == f_gptu*/

-       *(AMAZON_GPTU_CLC) = 0x100;
-
-       *(AMAZON_GPTU_CAPREL) = 0xffff;
-       *(AMAZON_GPTU_T6CON) = 0x80C0;
-       
-       retval = setup_irq(AMAZON_TIMER6_INT,&hrt_irqaction);
-       if (retval){
-               prom_printf("reqeust_irq failed %d. HIGH_RES_TIMER is diabled\n",AMAZON_TIMER6_INT);            
-       }
-#endif //CONFIG_HIGH_RES_TIMERS                
-#endif
+       amazon_writel(0x0100, AMAZON_GPTU_CLC);
+       amazon_writel(0xffff, AMAZON_GPTU_CAPREL);
+       amazon_writel(0x80C0, AMAZON_GPTU_T6CON);

 }
 
 void __init plat_mem_setup(void)
 }
 
 void __init plat_mem_setup(void)


@@ -165,7 +135,7 @@ void __init plat_mem_setup(void)
        u32 chipid = 0;
        u32 part_no = 0;
        
        u32 chipid = 0;
        u32 part_no = 0;
        

-       chipid = *(AMAZON_MCD_CHIPID);
+       chipid = amazon_readl(AMAZON_MCD_CHIPID);

        part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
        
        if(part_no == AMAZON_CHIPID_YANGTSE){
        part_no = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
        
        if(part_no == AMAZON_CHIPID_YANGTSE){


@@ -180,17 +150,17 @@ void __init plat_mem_setup(void)
        board_time_init = amazon_time_init;
 
        //stop reset TPE and DFE
        board_time_init = amazon_time_init;
 
        //stop reset TPE and DFE

-       *(AMAZON_RST_REQ) = 0x0;
+       amazon_writel(0, AMAZON_RST_REQ);

        //clock
        //clock

-       *(AMAZON_PMU_PWDCR) = 0x3fff;
+       amazon_writel(0x3fff, AMAZON_PMU_PWDCR);

        //reenable trace capability
        //reenable trace capability

-       part_no = *(AMAZON_BCU_ECON);
+       part_no = readl(AMAZON_BCU_ECON);

 }
 
 static void amazon_machine_restart(char *command)
 {
     local_irq_disable();
 }
 
 static void amazon_machine_restart(char *command)
 {
     local_irq_disable();

-    *AMAZON_RST_REQ = AMAZON_RST_ALL;
+    amazon_writel(AMAZON_RST_ALL, AMAZON_RST_REQ);

     for (;;) ;
 }
 
     for (;;) ;
 }
 

diff --git a/target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon.h b/target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon.h
index 79e495a..3f74f60 100644 (file)
--- a/target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon.h
+++ b/target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon.h
@@ -129,39 +129,27 @@
 /***********************************************************************/   
 
 /***CGU Clock Divider Select Register***/
 /***********************************************************************/   
 
 /***CGU Clock Divider Select Register***/

-#define AMAZON_CGU_DIV                         ((volatile u32*)(AMAZON_CGU+ 0x0000))                   
-
+#define AMAZON_CGU_DIV                                                 (AMAZON_CGU + 0x0000)                   

 /***CGU PLL0 Status Register***/ 
 /***CGU PLL0 Status Register***/ 

-#define AMAZON_CGU_PLL0SR                      ((volatile u32*)(AMAZON_CGU+ 0x0004))
-      
+#define AMAZON_CGU_PLL0SR                                              (AMAZON_CGU + 0x0004)

 /***CGU PLL1 Status Register***/ 
 /***CGU PLL1 Status Register***/ 

-#define AMAZON_CGU_PLL1SR                      ((volatile u32*)(AMAZON_CGU+ 0x0008))
-      
+#define AMAZON_CGU_PLL1SR                                              (AMAZON_CGU + 0x0008)

 /***CGU Interface Clock Control Register***/ 
 /***CGU Interface Clock Control Register***/ 

-#define AMAZON_CGU_IFCCR                       ((volatile u32*)(AMAZON_CGU+ 0x000c))
-      
+#define AMAZON_CGU_IFCCR                                               (AMAZON_CGU + 0x000c)

 /***CGU Oscillator Control Register***/ 
 /***CGU Oscillator Control Register***/ 

-#define AMAZON_CGU_OSCCR                       ((volatile u32*)(AMAZON_CGU+ 0x0010))
-      
+#define AMAZON_CGU_OSCCR                                               (AMAZON_CGU + 0x0010)

 /***CGU Memory Clock Delay Register***/ 
 /***CGU Memory Clock Delay Register***/ 

-#define AMAZON_CGU_MCDEL                       ((volatile u32*)(AMAZON_CGU+ 0x0014))
-      
+#define AMAZON_CGU_MCDEL                                               (AMAZON_CGU + 0x0014)

 /***CGU CPU Clock Reduction Register***/ 
 /***CGU CPU Clock Reduction Register***/ 

-#define AMAZON_CGU_CPUCRD                      ((volatile u32*)(AMAZON_CGU+ 0x0018))
-
-/* 165001:henryhsu:20050603:Source Add by Bing Tao */
-
+#define AMAZON_CGU_CPUCRD                                              (AMAZON_CGU + 0x0018)

 /***CGU Test Register**/
 /***CGU Test Register**/

-#define AMAZON_CGU_TST                          ((volatile u32*)(AMAZON_CGU+ 0x003c))
-
-/* 165001 */
-
+#define AMAZON_CGU_TST                                                 (AMAZON_CGU + 0x003c)

 
 /***********************************************************************/
 /*  Module      :  PMU register address and bits                       */
 /***********************************************************************/
          
 
 /***********************************************************************/
 /*  Module      :  PMU register address and bits                       */
 /***********************************************************************/
          

-#define AMAZON_PMU                          AMAZON_CGU
+#define AMAZON_PMU                                                             AMAZON_CGU

 /***********************************************************************/   
 
       
 /***********************************************************************/