From 8e777a33d87738a9f197df05c8ed312c050ea26f Mon Sep 17 00:00:00 2001
From: juhosg <juhosg@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Wed, 18 Feb 2009 19:58:43 +0000
Subject: [PATCH] [ar71xx] add a workaround for fixing the bad performance of
 the Ubiquiti RouterStation/LS-SR71 boards, until they fix their bootloader.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14556 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 .../asm/mach-ar71xx/kernel-entry-init.h       | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h
new file mode 100644
index 000000000..948d28034
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h
@@ -0,0 +1,32 @@
+/*
+ *  Atheros AR71xx specific kernel entry setup
+ *
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H
+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H
+
+	/*
+	 * Some bootloaders set the 'Kseg0 coherency algorithm' to
+	 * 'Cacheable, noncoherent, write-through, no write allocate'
+	 * and this cause performance issues. Let's go and change it to
+	 * 'Cacheable, noncoherent, write-back, write allocate'
+	 */
+	.macro	kernel_entry_setup
+	mfc0	t0, CP0_CONFIG
+	li	t1, ~CONF_CM_CMASK
+	and	t0, t1
+	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	nop
+	.endm
+
+	.macro	smp_slave_setup
+	.endm
+
+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */
-- 
2.20.1