lpc1xxx/LPC11xx_handlers.c

   1 /*
   2  * Software License Agreement (BSD License)
   3  *
   4  * Copyright (c) 2010, Roel Verdult
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  * notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  * notice, this list of conditions and the following disclaimer in the
  13  * documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the copyright holders nor the
  15  * names of its contributors may be used to endorse or promote products
  16  * derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
  19  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  20  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  21  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY
  22  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  23  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  24  *  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  27  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  */
  30
  31 // The GCC compiler defines the current architecture derived from the -mcpu argument.
  32 // When target cpu is the cortex-m0, it automatically defines __ARM_ARCH_6M__
  33 #ifndef __ARM_ARCH_6M__
  34   #error "The target ARM cpu must be Cortex-M0 compatible (-mcpu=cortex-m0)"
  35 #endif
  36
  37 // Declare a weak alias macro as described in the GCC manual[1][2]
  38 #define WEAK_ALIAS(f) __attribute__ ((weak, alias (#f)));
  39 #define SECTION(s) __attribute__ ((section(s)))
  40
  41 /******************************************************************************
  42  * Forward undefined IRQ handlers to an infinite loop function. The Handlers
  43  * are weakly aliased which means that (re)definitions will overide these.
  44  *****************************************************************************/
  45
  46 void irq_undefined() {
  47   // Do nothing when occured interrupt is not defined, just keep looping
  48   while(1);
  49 }
  50
  51 void CAN_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  52 void SSP1_IRQHandler(void)      WEAK_ALIAS(irq_undefined);
  53 void I2C_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  54 void TIMER16_0_IRQHandler(void) WEAK_ALIAS(irq_undefined);
  55 void TIMER16_1_IRQHandler(void) WEAK_ALIAS(irq_undefined);
  56 void TIMER32_0_IRQHandler(void) WEAK_ALIAS(irq_undefined);
  57 void TIMER32_1_IRQHandler(void) WEAK_ALIAS(irq_undefined);
  58 void SSP0_IRQHandler(void)      WEAK_ALIAS(irq_undefined);
  59 void UART_IRQHandler(void)      WEAK_ALIAS(irq_undefined);
  60 void USB_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  61 void USB_FIQHandler(void)       WEAK_ALIAS(irq_undefined);
  62 void ADC_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  63 void WDT_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  64 void BOD_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  65 void FMC_IRQHandler(void)       WEAK_ALIAS(irq_undefined);
  66 void PIOINT3_IRQHandler(void)   WEAK_ALIAS(irq_undefined);
  67 void PIOINT2_IRQHandler(void)   WEAK_ALIAS(irq_undefined);
  68 void PIOINT1_IRQHandler(void)   WEAK_ALIAS(irq_undefined);
  69 void PIOINT0_IRQHandler(void)   WEAK_ALIAS(irq_undefined);
  70 void WAKEUP_IRQHandler(void)    WEAK_ALIAS(irq_undefined);
  71
  72 /*****************************************************************************
  73  * Forward undefined fault handlers to an infinite loop function. The Handlers
  74  * are weakly aliased which means that (re)definitions will overide these.
  75  ****************************************************************************/
  76
  77 void fault_undefined() {
  78   // Do nothing when occured interrupt is not defined, just keep looping
  79   while(1);
  80 }
  81
  82 void NMI_Handler(void)          WEAK_ALIAS(fault_undefined);
  83 void HardFault_Handler(void)    WEAK_ALIAS(fault_undefined);
  84 void MemManage_Handler(void)    WEAK_ALIAS(fault_undefined);
  85 void BusFault_Handler(void)     WEAK_ALIAS(fault_undefined);
  86 void UsageFault_Handler(void)   WEAK_ALIAS(fault_undefined);
  87 void SVCall_Handler(void)       WEAK_ALIAS(fault_undefined);
  88 void DebugMon_Handler(void)     WEAK_ALIAS(fault_undefined);
  89 void PendSV_Handler(void)       WEAK_ALIAS(fault_undefined);
  90 void SysTick_Handler(void)      WEAK_ALIAS(fault_undefined);
  91
  92 /******************************************************************************
  93  * Forward undefined IRQ handlers to an infinite loop function. The Handlers
  94  * are weakly aliased which means that (re)definitions will overide these.
  95  *****************************************************************************/
  96
  97 // Prototype the entry values, which are handled by the linker script
  98 extern void* stack_entry;
  99 extern void boot_entry(void);
 100
 101 // Defined irq vectors using simple c code following the description in a white
 102 // paper from ARM[3] and code example from Simonsson Fun Technologies[4].
 103 // These vectors are placed at the memory location defined in the linker script
 104 const void *vectors[] SECTION(".irq_vectors") =
 105 {
 106   // Stack and program reset entry point
 107   &stack_entry,          // The initial stack pointer
 108   boot_entry,            // The reset handler
 109
 110   // Various fault handlers
 111   NMI_Handler,           // The NMI handler
 112   HardFault_Handler,     // The hard fault handler
 113   MemManage_Handler,     // MemManage_Handler
 114   BusFault_Handler,      // BusFault_Handler
 115   UsageFault_Handler,    // UsageFault_Handler
 116   0,                     // Reserved
 117   0,                     // Reserved
 118   0,                     // Reserved
 119   0,                     // Reserved
 120   SVCall_Handler,        // SVCall handler
 121   DebugMon_Handler,      // DebugMon_Handler
 122   0,                     // Reserved
 123   PendSV_Handler,        // The PendSV handler
 124   SysTick_Handler,       // The SysTick handler
 125
 126   // Wakeup I/O pins handlers
 127   WAKEUP_IRQHandler,     // PIO0_0  Wakeup
 128   WAKEUP_IRQHandler,     // PIO0_1  Wakeup
 129   WAKEUP_IRQHandler,     // PIO0_2  Wakeup
 130   WAKEUP_IRQHandler,     // PIO0_3  Wakeup
 131   WAKEUP_IRQHandler,     // PIO0_4  Wakeup
 132   WAKEUP_IRQHandler,     // PIO0_5  Wakeup
 133   WAKEUP_IRQHandler,     // PIO0_6  Wakeup
 134   WAKEUP_IRQHandler,     // PIO0_7  Wakeup
 135   WAKEUP_IRQHandler,     // PIO0_8  Wakeup
 136   WAKEUP_IRQHandler,     // PIO0_9  Wakeup
 137   WAKEUP_IRQHandler,     // PIO0_10 Wakeup
 138   WAKEUP_IRQHandler,     // PIO0_11 Wakeup
 139   WAKEUP_IRQHandler,     // PIO1_0  Wakeup
 140
 141   // Specific peripheral irq handlers
 142   CAN_IRQHandler,        // CAN
 143   SSP1_IRQHandler,       // SSP1
 144   I2C_IRQHandler,        // I2C0
 145   TIMER16_0_IRQHandler,  // CT16B0 (16-bit Timer 0)
 146   TIMER16_1_IRQHandler,  // CT16B1 (16-bit Timer 1)
 147   TIMER32_0_IRQHandler,  // CT32B0 (32-bit Timer 0)
 148   TIMER32_1_IRQHandler,  // CT32B1 (32-bit Timer 1)
 149   SSP0_IRQHandler,       // SSP0
 150   UART_IRQHandler,       // UART0
 151   USB_IRQHandler,        // USB IRQ
 152   USB_FIQHandler,        // USB FIQ
 153   ADC_IRQHandler,        // ADC (A/D Converter)
 154   WDT_IRQHandler,        // WDT (Watchdog Timer)
 155   BOD_IRQHandler,        // BOD (Brownout Detect)
 156   FMC_IRQHandler,        // Flash (IP2111 Flash Memory Controller)
 157   PIOINT3_IRQHandler,    // PIO INT3
 158   PIOINT2_IRQHandler,    // PIO INT2
 159   PIOINT1_IRQHandler,    // PIO INT1
 160   PIOINT0_IRQHandler,    // PIO INT0
 161 };
 162
 163 /******************************************************************************
 164  * References
 165  *  [1] http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
 166  *  [2] http://gcc.gnu.org/onlinedocs/gcc/Variable-Attributes.html
 167  *  [3] http://www.arm.com/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf
 168  *  [4] http://fun-tech.se/stm32/OlimexBlinky/mini.php
 169  *****************************************************************************/
 170