1 diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
2 index 4de432e..c4c810b 100644
3 --- a/arch/arm/kernel/setup.c
4 +++ b/arch/arm/kernel/setup.c
5 @@ -61,6 +61,7 @@ extern int root_mountflags;
6 extern void _stext, _text, _etext, __data_start, _edata, _end;
8 unsigned int processor_id;
9 +EXPORT_SYMBOL(processor_id);
10 unsigned int __machine_arch_type;
11 EXPORT_SYMBOL(__machine_arch_type);
13 diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
14 index 61b2dfc..e774447 100644
15 --- a/arch/arm/mach-ixp4xx/Kconfig
16 +++ b/arch/arm/mach-ixp4xx/Kconfig
17 @@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI
18 need to use the indirect method instead. If you don't know
19 what you need, leave this option unselected.
22 + tristate "IXP4xx Queue Manager support"
24 + This driver supports IXP4xx built-in hardware queue manager
25 + and is automatically selected by Ethernet and HSS drivers.
28 + tristate "IXP4xx Network Processor Engine support"
32 + This driver supports IXP4xx built-in network coprocessors
33 + and is automatically selected by Ethernet and HSS drivers.
38 diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
39 index 77e00ad..4bb97e1 100644
40 --- a/arch/arm/mach-ixp4xx/Makefile
41 +++ b/arch/arm/mach-ixp4xx/Makefile
42 @@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
43 obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
45 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
46 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
47 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
48 diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
49 index d5008d8..10b41c6 100644
50 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
51 +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
52 @@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = {
53 .resource = ixdp425_uart_resources
56 +/* Built-in 10/100 Ethernet MAC interfaces */
57 +static struct eth_plat_info ixdp425_plat_eth[] = {
69 +static struct platform_device ixdp425_eth[] = {
71 + .name = "ixp4xx_eth",
72 + .id = IXP4XX_ETH_NPEB,
73 + .dev.platform_data = ixdp425_plat_eth,
75 + .name = "ixp4xx_eth",
76 + .id = IXP4XX_ETH_NPEC,
77 + .dev.platform_data = ixdp425_plat_eth + 1,
81 static struct platform_device *ixdp425_devices[] __initdata = {
82 &ixdp425_i2c_controller,
84 @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = {
85 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
94 static void __init ixdp425_init(void)
95 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
97 index 0000000..83c137e
99 +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
102 + * Intel IXP4xx Network Processor Engine driver for Linux
104 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
106 + * This program is free software; you can redistribute it and/or modify it
107 + * under the terms of version 2 of the GNU General Public License
108 + * as published by the Free Software Foundation.
110 + * The code is based on publicly available information:
111 + * - Intel IXP4xx Developer's Manual and other e-papers
112 + * - Intel IXP400 Access Library Software (BSD license)
113 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
114 + * Thanks, Christian.
117 +#include <linux/delay.h>
118 +#include <linux/dma-mapping.h>
119 +#include <linux/firmware.h>
120 +#include <linux/io.h>
121 +#include <linux/kernel.h>
122 +#include <linux/module.h>
123 +#include <linux/slab.h>
124 +#include <asm/arch/npe.h>
130 +#define MAX_RETRIES 1000 /* microseconds */
131 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
132 +#define NPE_46X_DATA_SIZE 0x1000
133 +#define NPE_A_42X_INSTR_SIZE 0x1000
134 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
135 +#define NPE_46X_INSTR_SIZE 0x1000
136 +#define REGS_SIZE 0x1000
138 +#define NPE_PHYS_REG 32
140 +#define FW_MAGIC 0xFEEDF00D
141 +#define FW_BLOCK_TYPE_INSTR 0x0
142 +#define FW_BLOCK_TYPE_DATA 0x1
143 +#define FW_BLOCK_TYPE_EOF 0xF
145 +/* NPE exec status (read) and command (write) */
146 +#define CMD_NPE_STEP 0x01
147 +#define CMD_NPE_START 0x02
148 +#define CMD_NPE_STOP 0x03
149 +#define CMD_NPE_CLR_PIPE 0x04
150 +#define CMD_CLR_PROFILE_CNT 0x0C
151 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
152 +#define CMD_WR_INS_MEM 0x11
153 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
154 +#define CMD_WR_DATA_MEM 0x13
155 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
156 +#define CMD_WR_ECS_REG 0x15
158 +#define STAT_RUN 0x80000000
159 +#define STAT_STOP 0x40000000
160 +#define STAT_CLEAR 0x20000000
161 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
163 +#define NPE_STEVT 0x1B
164 +#define NPE_STARTPC 0x1C
165 +#define NPE_REGMAP 0x1E
166 +#define NPE_CINDEX 0x1F
168 +#define INSTR_WR_REG_SHORT 0x0000C000
169 +#define INSTR_WR_REG_BYTE 0x00004000
170 +#define INSTR_RD_FIFO 0x0F888220
171 +#define INSTR_RESET_MBOX 0x0FAC8210
173 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
174 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
175 +#define ECS_BG_CTXT_REG_2 0x02
176 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
177 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
178 +#define ECS_PRI_1_CTXT_REG_2 0x06
179 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
180 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
181 +#define ECS_PRI_2_CTXT_REG_2 0x0A
182 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
183 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
184 +#define ECS_DBG_CTXT_REG_2 0x0E
185 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
187 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
188 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
189 +#define ECS_REG_0_LDUR_BITS 8
190 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
191 +#define ECS_REG_1_CCTXT_BITS 16
192 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
193 +#define ECS_REG_1_SELCTXT_BITS 0
194 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
195 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
196 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
198 +/* NPE watchpoint_fifo register bit */
199 +#define WFIFO_VALID 0x80000000
201 +/* NPE messaging_status register bit definitions */
202 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
203 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
204 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
205 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
206 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
207 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
208 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
209 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
211 +/* NPE messaging_control register bit definitions */
212 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
213 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
214 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
215 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
217 +/* NPE mailbox_status value for reset */
218 +#define RESET_MBOX_STAT 0x0000F0F0
220 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
222 +#define print_npe(pri, npe, fmt, ...) \
223 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
226 +#define debug_msg(npe, fmt, ...) \
227 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
229 +#define debug_msg(npe, fmt, ...)
235 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
236 + { ECS_BG_CTXT_REG_1, 0x01000000 },
237 + { ECS_BG_CTXT_REG_2, 0x00008000 },
238 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
239 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
240 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
241 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
242 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
243 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
244 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
245 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
246 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
247 + { ECS_INSTRUCT_REG, 0x1003C00F },
250 +static struct npe npe_tab[NPE_COUNT] = {
253 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
254 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
257 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
258 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
261 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
262 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
266 +int npe_running(struct npe *npe)
268 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
271 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
273 + __raw_writel(data, &npe->regs->exec_data);
274 + __raw_writel(addr, &npe->regs->exec_addr);
275 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
278 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
280 + __raw_writel(addr, &npe->regs->exec_addr);
281 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
282 + /* Iintroduce extra read cycles after issuing read command to NPE
283 + so that we read the register after the NPE has updated it.
284 + This is to overcome race condition between XScale and NPE */
285 + __raw_readl(&npe->regs->exec_data);
286 + __raw_readl(&npe->regs->exec_data);
287 + return __raw_readl(&npe->regs->exec_data);
290 +static void npe_clear_active(struct npe *npe, u32 reg)
292 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
293 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
296 +static void npe_start(struct npe *npe)
298 + /* ensure only Background Context Stack Level is active */
299 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
300 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
301 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
303 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
304 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
307 +static void npe_stop(struct npe *npe)
309 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
310 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
313 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
319 + /* set the Active bit, and the LDUR, in the debug level */
320 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
321 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
323 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
324 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
325 + which context store to access.
326 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
328 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
329 + (ctx << ECS_REG_1_CCTXT_BITS) |
330 + (ctx << ECS_REG_1_SELCTXT_BITS));
332 + /* clear the pipeline */
333 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
335 + /* load NPE instruction into the instruction register */
336 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
338 + /* we need this value later to wait for completion of NPE execution
340 + wc = __raw_readl(&npe->regs->watch_count);
342 + /* issue a Step One command via the Execution Control register */
343 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
345 + /* Watch Count register increments when NPE completes an instruction */
346 + for (i = 0; i < MAX_RETRIES; i++) {
347 + if (wc != __raw_readl(&npe->regs->watch_count))
352 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
356 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
359 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
360 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
361 + addr << 9 | /* base Operand */
362 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
363 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
364 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
367 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
370 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
371 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
372 + addr << 9 | /* base Operand */
373 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
374 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
375 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
378 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
381 + /* write in 16 bit steps first the high and then the low value */
382 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
384 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
387 +static int npe_reset(struct npe *npe)
389 + u32 val, ctl, exec_count, ctx_reg2;
392 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
395 + /* disable parity interrupt */
396 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
398 + /* pre exec - debug instruction */
399 + /* turn off the halt bit by clearing Execution Count register. */
400 + exec_count = __raw_readl(&npe->regs->exec_count);
401 + __raw_writel(0, &npe->regs->exec_count);
402 + /* ensure that IF and IE are on (temporarily), so that we don't end up
403 + stepping forever */
404 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
405 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
406 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
408 + /* clear the FIFOs */
409 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
411 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
412 + /* read from the outFIFO until empty */
413 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
414 + __raw_readl(&npe->regs->in_out_fifo));
416 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
417 + /* step execution of the NPE intruction to read inFIFO using
418 + the Debug Executing Context stack */
419 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
422 + /* reset the mailbox reg from the XScale side */
423 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
424 + /* from NPE side */
425 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
428 + /* Reset the physical registers in the NPE register file */
429 + for (val = 0; val < NPE_PHYS_REG; val++) {
430 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
432 + /* address is either 0 or 4 */
433 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
437 + /* Reset the context store = each context's Context Store registers */
439 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
440 + for Background ECS, to set where NPE starts executing code */
441 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
442 + val &= ~ECS_REG_0_NEXTPC_MASK;
443 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
444 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
446 + for (i = 0; i < 16; i++) {
447 + if (i) { /* Context 0 has no STEVT nor STARTPC */
448 + /* STEVT = off, 0x80 */
449 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
451 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
454 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
455 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
457 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
462 + /* clear active bit in debug level */
463 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
464 + /* clear the pipeline */
465 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
466 + /* restore previous values */
467 + __raw_writel(exec_count, &npe->regs->exec_count);
468 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
470 + /* write reset values to Execution Context Stack registers */
471 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
472 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
473 + ecs_reset[val].val);
475 + /* clear the profile counter */
476 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
478 + __raw_writel(0, &npe->regs->exec_count);
479 + __raw_writel(0, &npe->regs->action_points[0]);
480 + __raw_writel(0, &npe->regs->action_points[1]);
481 + __raw_writel(0, &npe->regs->action_points[2]);
482 + __raw_writel(0, &npe->regs->action_points[3]);
483 + __raw_writel(0, &npe->regs->watch_count);
485 + val = ixp4xx_read_feature_bits();
486 + /* reset the NPE */
487 + ixp4xx_write_feature_bits(val &
488 + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
489 + for (i = 0; i < MAX_RETRIES; i++) {
490 + if (!(ixp4xx_read_feature_bits() &
491 + (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
492 + break; /* reset completed */
495 + if (i == MAX_RETRIES)
498 + /* deassert reset */
499 + ixp4xx_write_feature_bits(val |
500 + (IXP4XX_FEATURE_RESET_NPEA << npe->id));
501 + for (i = 0; i < MAX_RETRIES; i++) {
502 + if (ixp4xx_read_feature_bits() &
503 + (IXP4XX_FEATURE_RESET_NPEA << npe->id))
504 + break; /* NPE is back alive */
507 + if (i == MAX_RETRIES)
512 + /* restore NPE configuration bus Control Register - parity settings */
513 + __raw_writel(ctl, &npe->regs->messaging_control);
518 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
520 + const u32 *send = msg;
523 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
524 + what, send[0], send[1]);
526 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
527 + debug_msg(npe, "NPE input FIFO not empty\n");
531 + __raw_writel(send[0], &npe->regs->in_out_fifo);
533 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
534 + debug_msg(npe, "NPE input FIFO full\n");
538 + __raw_writel(send[1], &npe->regs->in_out_fifo);
540 + while ((cycles < MAX_RETRIES) &&
541 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
546 + if (cycles == MAX_RETRIES) {
547 + debug_msg(npe, "Timeout sending message\n");
551 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
555 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
558 + int cycles = 0, cnt = 0;
560 + debug_msg(npe, "Trying to receive message %s\n", what);
562 + while (cycles < MAX_RETRIES) {
563 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
564 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
575 + debug_msg(npe, "Received [%08X]\n", recv[0]);
578 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
582 + if (cycles == MAX_RETRIES) {
583 + debug_msg(npe, "Timeout waiting for message\n");
587 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
591 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
594 + u32 *send = msg, recv[2];
596 + if ((result = npe_send_message(npe, msg, what)) != 0)
598 + if ((result = npe_recv_message(npe, recv, what)) != 0)
601 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
602 + debug_msg(npe, "Message %s: unexpected message received\n",
610 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
612 + const struct firmware *fw_entry;
625 + struct dl_block blocks[0];
629 + struct dl_codeblock {
635 + int i, j, err, data_size, instr_size, blocks, table_end;
638 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
642 + if (fw_entry->size < sizeof(struct dl_image)) {
643 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
646 + image = (struct dl_image*)fw_entry->data;
649 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
650 + image->magic, image->id, image->size, image->size * 4);
653 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
654 + image->id = swab32(image->id);
655 + image->size = swab32(image->size);
656 + } else if (image->magic != FW_MAGIC) {
657 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
661 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
662 + print_npe(KERN_ERR, npe,
663 + "inconsistent size of firmware file\n");
666 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
667 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
670 + if (image->magic == swab32(FW_MAGIC))
671 + for (i = 0; i < image->size; i++)
672 + image->data[i] = swab32(image->data[i]);
674 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
675 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
680 + if (npe_running(npe)) {
681 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
682 + "already running\n");
691 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
692 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
693 + (image->id >> 8) & 0xFF, image->id & 0xFF);
695 + if (!cpu_is_ixp46x()) {
697 + instr_size = NPE_A_42X_INSTR_SIZE;
699 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
700 + data_size = NPE_42X_DATA_SIZE;
702 + instr_size = NPE_46X_INSTR_SIZE;
703 + data_size = NPE_46X_DATA_SIZE;
706 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
708 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
710 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
711 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
717 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
720 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
721 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
722 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
723 + || blk->offset < table_end) {
724 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
725 + "firmware block #%i\n", blk->offset, i);
729 + cb = (struct dl_codeblock*)&image->data[blk->offset];
730 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
731 + if (cb->npe_addr + cb->size > instr_size)
733 + cmd = CMD_WR_INS_MEM;
734 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
735 + if (cb->npe_addr + cb->size > data_size)
737 + cmd = CMD_WR_DATA_MEM;
739 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
740 + "type 0x%X\n", i, blk->type);
743 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
744 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
745 + "fit in firmware image: type %c, start 0x%X,"
746 + " length 0x%X\n", i,
747 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
748 + cb->npe_addr, cb->size);
752 + for (j = 0; j < cb->size; j++)
753 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
757 + if (!npe_running(npe))
758 + print_npe(KERN_ERR, npe, "unable to start\n");
759 + release_firmware(fw_entry);
763 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
764 + "memory: type %c, start 0x%X, length 0x%X\n", i,
765 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
766 + cb->npe_addr, cb->size);
768 + release_firmware(fw_entry);
773 +struct npe *npe_request(int id)
775 + if (id < NPE_COUNT)
776 + if (npe_tab[id].valid)
777 + if (try_module_get(THIS_MODULE))
778 + return &npe_tab[id];
782 +void npe_release(struct npe *npe)
784 + module_put(THIS_MODULE);
788 +static int __init npe_init_module(void)
793 + for (i = 0; i < NPE_COUNT; i++) {
794 + struct npe *npe = &npe_tab[i];
795 + if (!(ixp4xx_read_feature_bits() &
796 + (IXP4XX_FEATURE_RESET_NPEA << i)))
797 + continue; /* NPE already disabled or not present */
798 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
801 + print_npe(KERN_ERR, npe,
802 + "failed to request memory region\n");
806 + if (npe_reset(npe))
817 +static void __exit npe_cleanup_module(void)
821 + for (i = 0; i < NPE_COUNT; i++)
822 + if (npe_tab[i].mem_res) {
823 + npe_reset(&npe_tab[i]);
824 + release_resource(npe_tab[i].mem_res);
828 +module_init(npe_init_module);
829 +module_exit(npe_cleanup_module);
831 +MODULE_AUTHOR("Krzysztof Halasa");
832 +MODULE_LICENSE("GPL v2");
834 +EXPORT_SYMBOL(npe_names);
835 +EXPORT_SYMBOL(npe_running);
836 +EXPORT_SYMBOL(npe_request);
837 +EXPORT_SYMBOL(npe_release);
838 +EXPORT_SYMBOL(npe_load_firmware);
839 +EXPORT_SYMBOL(npe_send_message);
840 +EXPORT_SYMBOL(npe_recv_message);
841 +EXPORT_SYMBOL(npe_send_recv_message);
842 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
844 index 0000000..e833013
846 +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
849 + * Intel IXP4xx Queue Manager driver for Linux
851 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
853 + * This program is free software; you can redistribute it and/or modify it
854 + * under the terms of version 2 of the GNU General Public License
855 + * as published by the Free Software Foundation.
858 +#include <linux/ioport.h>
859 +#include <linux/interrupt.h>
860 +#include <linux/kernel.h>
861 +#include <linux/module.h>
862 +#include <asm/arch/qmgr.h>
866 +struct qmgr_regs __iomem *qmgr_regs;
867 +static struct resource *mem_res;
868 +static spinlock_t qmgr_lock;
869 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
870 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
871 +static void *irq_pdevs[HALF_QUEUES];
873 +void qmgr_set_irq(unsigned int queue, int src,
874 + void (*handler)(void *pdev), void *pdev)
876 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
877 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
878 + unsigned long flags;
881 + spin_lock_irqsave(&qmgr_lock, flags);
882 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
883 + irq_handlers[queue] = handler;
884 + irq_pdevs[queue] = pdev;
885 + spin_unlock_irqrestore(&qmgr_lock, flags);
889 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
892 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
893 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
895 + for (i = 0; i < HALF_QUEUES; i++)
896 + if (val & (1 << i))
897 + irq_handlers[i](irq_pdevs[i]);
899 + return val ? IRQ_HANDLED : 0;
903 +void qmgr_enable_irq(unsigned int queue)
905 + unsigned long flags;
907 + spin_lock_irqsave(&qmgr_lock, flags);
908 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
909 + &qmgr_regs->irqen[0]);
910 + spin_unlock_irqrestore(&qmgr_lock, flags);
913 +void qmgr_disable_irq(unsigned int queue)
915 + unsigned long flags;
917 + spin_lock_irqsave(&qmgr_lock, flags);
918 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
919 + &qmgr_regs->irqen[0]);
920 + spin_unlock_irqrestore(&qmgr_lock, flags);
923 +static inline void shift_mask(u32 *mask)
925 + mask[3] = mask[3] << 1 | mask[2] >> 31;
926 + mask[2] = mask[2] << 1 | mask[1] >> 31;
927 + mask[1] = mask[1] << 1 | mask[0] >> 31;
931 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
932 + unsigned int nearly_empty_watermark,
933 + unsigned int nearly_full_watermark)
935 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
938 + if (queue >= HALF_QUEUES)
941 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
965 + cfg |= nearly_empty_watermark << 26;
966 + cfg |= nearly_full_watermark << 29;
967 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
968 + mask[1] = mask[2] = mask[3] = 0;
970 + if (!try_module_get(THIS_MODULE))
973 + spin_lock_irq(&qmgr_lock);
974 + if (__raw_readl(&qmgr_regs->sram[queue])) {
980 + if (!(used_sram_bitmap[0] & mask[0]) &&
981 + !(used_sram_bitmap[1] & mask[1]) &&
982 + !(used_sram_bitmap[2] & mask[2]) &&
983 + !(used_sram_bitmap[3] & mask[3]))
984 + break; /* found free space */
988 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
989 + printk(KERN_ERR "qmgr: no free SRAM space for"
990 + " queue %i\n", queue);
996 + used_sram_bitmap[0] |= mask[0];
997 + used_sram_bitmap[1] |= mask[1];
998 + used_sram_bitmap[2] |= mask[2];
999 + used_sram_bitmap[3] |= mask[3];
1000 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
1001 + spin_unlock_irq(&qmgr_lock);
1004 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
1010 + spin_unlock_irq(&qmgr_lock);
1011 + module_put(THIS_MODULE);
1015 +void qmgr_release_queue(unsigned int queue)
1017 + u32 cfg, addr, mask[4];
1019 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
1021 + spin_lock_irq(&qmgr_lock);
1022 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
1023 + addr = (cfg >> 14) & 0xFF;
1025 + BUG_ON(!addr); /* not requested */
1027 + switch ((cfg >> 24) & 3) {
1028 + case 0: mask[0] = 0x1; break;
1029 + case 1: mask[0] = 0x3; break;
1030 + case 2: mask[0] = 0xF; break;
1031 + case 3: mask[0] = 0xFF; break;
1037 + __raw_writel(0, &qmgr_regs->sram[queue]);
1039 + used_sram_bitmap[0] &= ~mask[0];
1040 + used_sram_bitmap[1] &= ~mask[1];
1041 + used_sram_bitmap[2] &= ~mask[2];
1042 + used_sram_bitmap[3] &= ~mask[3];
1043 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
1044 + spin_unlock_irq(&qmgr_lock);
1046 + module_put(THIS_MODULE);
1048 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
1052 +static int qmgr_init(void)
1055 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
1056 + IXP4XX_QMGR_REGION_SIZE,
1057 + "IXP4xx Queue Manager");
1058 + if (mem_res == NULL)
1061 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1062 + if (qmgr_regs == NULL) {
1067 + /* reset qmgr registers */
1068 + for (i = 0; i < 4; i++) {
1069 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
1070 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
1072 + for (i = 0; i < 2; i++) {
1073 + __raw_writel(0, &qmgr_regs->stat2[i]);
1074 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
1075 + __raw_writel(0, &qmgr_regs->irqen[i]);
1078 + for (i = 0; i < QUEUES; i++)
1079 + __raw_writel(0, &qmgr_regs->sram[i]);
1081 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
1082 + "IXP4xx Queue Manager", NULL);
1084 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
1089 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
1090 + spin_lock_init(&qmgr_lock);
1092 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
1096 + iounmap(qmgr_regs);
1098 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1102 +static void qmgr_remove(void)
1104 + free_irq(IRQ_IXP4XX_QM1, NULL);
1105 + synchronize_irq(IRQ_IXP4XX_QM1);
1106 + iounmap(qmgr_regs);
1107 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1110 +module_init(qmgr_init);
1111 +module_exit(qmgr_remove);
1113 +MODULE_LICENSE("GPL v2");
1114 +MODULE_AUTHOR("Krzysztof Halasa");
1116 +EXPORT_SYMBOL(qmgr_regs);
1117 +EXPORT_SYMBOL(qmgr_set_irq);
1118 +EXPORT_SYMBOL(qmgr_enable_irq);
1119 +EXPORT_SYMBOL(qmgr_disable_irq);
1120 +EXPORT_SYMBOL(qmgr_request_queue);
1121 +EXPORT_SYMBOL(qmgr_release_queue);
1122 diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
1123 index f9cc2b6..9274d3f 100644
1124 --- a/drivers/net/arm/Kconfig
1125 +++ b/drivers/net/arm/Kconfig
1126 @@ -47,3 +47,13 @@ config EP93XX_ETH
1128 This is a driver for the ethernet hardware included in EP93xx CPUs.
1129 Say Y if you are building a kernel for EP93xx based devices.
1132 + tristate "IXP4xx Ethernet support"
1133 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
1135 + select IXP4XX_QMGR
1138 + Say Y here if you want to use built-in Ethernet ports
1139 + on IXP4xx processor.
1140 diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
1141 index a4c8682..7c812ac 100644
1142 --- a/drivers/net/arm/Makefile
1143 +++ b/drivers/net/arm/Makefile
1144 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
1145 obj-$(CONFIG_ARM_ETHER1) += ether1.o
1146 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
1147 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
1148 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
1149 diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
1150 new file mode 100644
1151 index 0000000..2c23f50
1153 +++ b/drivers/net/arm/ixp4xx_eth.c
1156 + * Intel IXP4xx Ethernet driver for Linux
1158 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1160 + * This program is free software; you can redistribute it and/or modify it
1161 + * under the terms of version 2 of the GNU General Public License
1162 + * as published by the Free Software Foundation.
1164 + * Ethernet port config (0x00 is not present on IXP42X):
1166 + * logical port 0x00 0x10 0x20
1167 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
1168 + * physical PortId 2 0 1
1169 + * TX queue 23 24 25
1170 + * RX-free queue 26 27 28
1171 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
1175 + * bits 0 -> 1 - NPE ID (RX and TX-done)
1176 + * bits 0 -> 2 - priority (TX, per 802.1D)
1177 + * bits 3 -> 4 - port ID (user-set?)
1178 + * bits 5 -> 31 - physical descriptor address
1181 +#include <linux/delay.h>
1182 +#include <linux/dma-mapping.h>
1183 +#include <linux/dmapool.h>
1184 +#include <linux/etherdevice.h>
1185 +#include <linux/io.h>
1186 +#include <linux/kernel.h>
1187 +#include <linux/mii.h>
1188 +#include <linux/platform_device.h>
1189 +#include <asm/arch/npe.h>
1190 +#include <asm/arch/qmgr.h>
1192 +#define DEBUG_QUEUES 0
1193 +#define DEBUG_DESC 0
1196 +#define DEBUG_PKT_BYTES 0
1197 +#define DEBUG_MDIO 0
1198 +#define DEBUG_CLOSE 0
1200 +#define DRV_NAME "ixp4xx_eth"
1204 +#define RX_DESCS 64 /* also length of all RX queues */
1205 +#define TX_DESCS 16 /* also length of all TX queues */
1206 +#define TXDONE_QUEUE_LEN 64 /* dwords */
1208 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1209 +#define REGS_SIZE 0x1000
1210 +#define MAX_MRU 1536 /* 0x600 */
1212 +#define MDIO_INTERVAL (3 * HZ)
1213 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
1214 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
1215 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
1217 +#define NPE_ID(port_id) ((port_id) >> 4)
1218 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
1219 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
1220 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
1221 +#define TXDONE_QUEUE 31
1223 +/* TX Control Registers */
1224 +#define TX_CNTRL0_TX_EN 0x01
1225 +#define TX_CNTRL0_HALFDUPLEX 0x02
1226 +#define TX_CNTRL0_RETRY 0x04
1227 +#define TX_CNTRL0_PAD_EN 0x08
1228 +#define TX_CNTRL0_APPEND_FCS 0x10
1229 +#define TX_CNTRL0_2DEFER 0x20
1230 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
1231 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
1233 +/* RX Control Registers */
1234 +#define RX_CNTRL0_RX_EN 0x01
1235 +#define RX_CNTRL0_PADSTRIP_EN 0x02
1236 +#define RX_CNTRL0_SEND_FCS 0x04
1237 +#define RX_CNTRL0_PAUSE_EN 0x08
1238 +#define RX_CNTRL0_LOOP_EN 0x10
1239 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
1240 +#define RX_CNTRL0_RX_RUNT_EN 0x40
1241 +#define RX_CNTRL0_BCAST_DIS 0x80
1242 +#define RX_CNTRL1_DEFER_EN 0x01
1244 +/* Core Control Register */
1245 +#define CORE_RESET 0x01
1246 +#define CORE_RX_FIFO_FLUSH 0x02
1247 +#define CORE_TX_FIFO_FLUSH 0x04
1248 +#define CORE_SEND_JAM 0x08
1249 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
1251 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
1252 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
1254 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
1255 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
1258 +/* NPE message codes */
1259 +#define NPE_GETSTATUS 0x00
1260 +#define NPE_EDB_SETPORTADDRESS 0x01
1261 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
1262 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
1263 +#define NPE_GETSTATS 0x04
1264 +#define NPE_RESETSTATS 0x05
1265 +#define NPE_SETMAXFRAMELENGTHS 0x06
1266 +#define NPE_VLAN_SETRXTAGMODE 0x07
1267 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
1268 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
1269 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
1270 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
1271 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
1272 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
1273 +#define NPE_FW_SETFIREWALLMODE 0x0E
1274 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
1275 +#define NPE_PC_SETAPMACTABLE 0x11
1276 +#define NPE_SETLOOPBACK_MODE 0x12
1277 +#define NPE_PC_SETBSSIDTABLE 0x13
1278 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
1279 +#define NPE_APPENDFCSCONFIG 0x15
1280 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
1281 +#define NPE_MAC_RECOVERY_START 0x17
1285 +typedef struct sk_buff buffer_t;
1286 +#define free_buffer dev_kfree_skb
1287 +#define free_buffer_irq dev_kfree_skb_irq
1289 +typedef void buffer_t;
1290 +#define free_buffer kfree
1291 +#define free_buffer_irq kfree
1295 + u32 tx_control[2], __res1[2]; /* 000 */
1296 + u32 rx_control[2], __res2[2]; /* 010 */
1297 + u32 random_seed, __res3[3]; /* 020 */
1298 + u32 partial_empty_threshold, __res4; /* 030 */
1299 + u32 partial_full_threshold, __res5; /* 038 */
1300 + u32 tx_start_bytes, __res6[3]; /* 040 */
1301 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
1302 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
1303 + u32 slot_time, __res9[3]; /* 070 */
1304 + u32 mdio_command[4]; /* 080 */
1305 + u32 mdio_status[4]; /* 090 */
1306 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
1307 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
1308 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
1309 + u32 hw_addr[6], __res13[61]; /* 0F0 */
1310 + u32 core_control; /* 1FC */
1314 + struct resource *mem_res;
1315 + struct eth_regs __iomem *regs;
1317 + struct net_device *netdev;
1318 + struct net_device_stats stat;
1319 + struct mii_if_info mii;
1320 + struct delayed_work mdio_thread;
1321 + struct eth_plat_info *plat;
1322 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1323 + struct desc *desc_tab; /* coherent */
1324 + u32 desc_tab_phys;
1325 + int id; /* logical port ID */
1329 +/* NPE message structure */
1332 + u8 cmd, eth_id, byte2, byte3;
1333 + u8 byte4, byte5, byte6, byte7;
1335 + u8 byte3, byte2, eth_id, cmd;
1336 + u8 byte7, byte6, byte5, byte4;
1340 +/* Ethernet packet descriptor */
1342 + u32 next; /* pointer to next buffer, unused */
1345 + u16 buf_len; /* buffer length */
1346 + u16 pkt_len; /* packet length */
1347 + u32 data; /* pointer to data buffer in RAM */
1355 + u16 pkt_len; /* packet length */
1356 + u16 buf_len; /* buffer length */
1357 + u32 data; /* pointer to data buffer in RAM */
1367 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
1368 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
1369 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
1371 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
1372 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
1373 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
1378 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1379 + (n) * sizeof(struct desc))
1380 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1382 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1383 + ((n) + RX_DESCS) * sizeof(struct desc))
1384 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1387 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1390 + for (i = 0; i < cnt; i++)
1391 + dest[i] = swab32(src[i]);
1395 +static spinlock_t mdio_lock;
1396 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
1397 +static int ports_open;
1398 +static struct port *npe_port_tab[MAX_NPES];
1399 +static struct dma_pool *dma_pool;
1402 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
1403 + int write, u16 cmd)
1407 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
1408 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
1413 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
1414 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
1416 + __raw_writel(((phy_id << 5) | location) & 0xFF,
1417 + &mdio_regs->mdio_command[2]);
1418 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
1419 + &mdio_regs->mdio_command[3]);
1421 + while ((cycles < MAX_MDIO_RETRIES) &&
1422 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
1427 + if (cycles == MAX_MDIO_RETRIES) {
1428 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
1433 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
1440 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
1441 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
1445 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
1446 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
1449 +static int mdio_read(struct net_device *dev, int phy_id, int location)
1451 + unsigned long flags;
1454 + spin_lock_irqsave(&mdio_lock, flags);
1455 + val = mdio_cmd(dev, phy_id, location, 0, 0);
1456 + spin_unlock_irqrestore(&mdio_lock, flags);
1460 +static void mdio_write(struct net_device *dev, int phy_id, int location,
1463 + unsigned long flags;
1465 + spin_lock_irqsave(&mdio_lock, flags);
1466 + mdio_cmd(dev, phy_id, location, 1, val);
1467 + spin_unlock_irqrestore(&mdio_lock, flags);
1470 +static void phy_reset(struct net_device *dev, int phy_id)
1472 + struct port *port = netdev_priv(dev);
1475 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
1477 + while (cycles < MAX_MII_RESET_RETRIES) {
1478 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
1480 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
1481 + dev->name, cycles);
1489 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
1492 +static void eth_set_duplex(struct port *port)
1494 + if (port->mii.full_duplex)
1495 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
1496 + &port->regs->tx_control[0]);
1498 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
1499 + &port->regs->tx_control[0]);
1503 +static void phy_check_media(struct port *port, int init)
1505 + if (mii_check_media(&port->mii, 1, init))
1506 + eth_set_duplex(port);
1507 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
1508 + struct net_device *dev = port->netdev;
1509 + int cur_link = mii_link_ok(&port->mii);
1510 + int prev_link = netif_carrier_ok(dev);
1512 + if (!prev_link && cur_link) {
1513 + printk(KERN_INFO "%s: link up\n", dev->name);
1514 + netif_carrier_on(dev);
1515 + } else if (prev_link && !cur_link) {
1516 + printk(KERN_INFO "%s: link down\n", dev->name);
1517 + netif_carrier_off(dev);
1523 +static void mdio_thread(struct work_struct *work)
1525 + struct port *port = container_of(work, struct port, mdio_thread.work);
1527 + phy_check_media(port, 0);
1528 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1532 +static inline void debug_pkt(struct net_device *dev, const char *func,
1533 + u8 *data, int len)
1535 +#if DEBUG_PKT_BYTES
1538 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1539 + for (i = 0; i < len; i++) {
1540 + if (i >= DEBUG_PKT_BYTES)
1543 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
1551 +static inline void debug_desc(u32 phys, struct desc *desc)
1554 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
1555 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
1556 + phys, desc->next, desc->buf_len, desc->pkt_len,
1557 + desc->data, desc->dest_id, desc->src_id, desc->flags,
1558 + desc->qos, desc->padlen, desc->vlan_tci,
1559 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
1560 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
1561 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
1562 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
1566 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1573 + { TX_QUEUE(0x10), "TX#0 " },
1574 + { TX_QUEUE(0x20), "TX#1 " },
1575 + { TX_QUEUE(0x00), "TX#2 " },
1576 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
1577 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
1578 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
1579 + { TXDONE_QUEUE, "TX-done " },
1583 + for (i = 0; i < ARRAY_SIZE(names); i++)
1584 + if (names[i].queue == queue)
1587 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1588 + i < ARRAY_SIZE(names) ? names[i].name : "",
1589 + is_get ? "->" : "<-", phys);
1593 +static inline u32 queue_get_entry(unsigned int queue)
1595 + u32 phys = qmgr_get_entry(queue);
1596 + debug_queue(queue, 1, phys);
1600 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1603 + u32 phys, tab_phys, n_desc;
1606 + if (!(phys = queue_get_entry(queue)))
1609 + phys &= ~0x1F; /* mask out non-address bits */
1610 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1611 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1612 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1613 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1614 + debug_desc(phys, &tab[n_desc]);
1615 + BUG_ON(tab[n_desc].next);
1619 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1620 + struct desc *desc)
1622 + debug_queue(queue, 0, phys);
1623 + debug_desc(phys, desc);
1624 + BUG_ON(phys & 0x1F);
1625 + qmgr_put_entry(queue, phys);
1626 + BUG_ON(qmgr_stat_overflow(queue));
1630 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1633 + dma_unmap_single(&port->netdev->dev, desc->data,
1634 + desc->buf_len, DMA_TO_DEVICE);
1636 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1637 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1643 +static void eth_rx_irq(void *pdev)
1645 + struct net_device *dev = pdev;
1646 + struct port *port = netdev_priv(dev);
1649 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
1651 + qmgr_disable_irq(port->plat->rxq);
1652 + netif_rx_schedule(dev);
1655 +static int eth_poll(struct net_device *dev, int *budget)
1657 + struct port *port = netdev_priv(dev);
1658 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
1659 + int quota = dev->quota, received = 0;
1662 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
1666 + struct sk_buff *skb;
1667 + struct desc *desc;
1670 + struct sk_buff *temp;
1674 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1675 + dev->quota -= received; /* No packet received */
1676 + *budget -= received;
1679 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
1682 + netif_rx_complete(dev);
1683 + qmgr_enable_irq(rxq);
1684 + if (!qmgr_stat_empty(rxq) &&
1685 + netif_rx_reschedule(dev, 0)) {
1687 + printk(KERN_DEBUG "%s: eth_poll"
1688 + " netif_rx_reschedule successed\n",
1691 + qmgr_disable_irq(rxq);
1695 + printk(KERN_DEBUG "%s: eth_poll all done\n",
1698 + return 0; /* all work done */
1701 + desc = rx_desc_ptr(port, n);
1704 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
1705 + phys = dma_map_single(&dev->dev, skb->data,
1706 + MAX_MRU, DMA_FROM_DEVICE);
1707 + if (dma_mapping_error(phys)) {
1708 + dev_kfree_skb(skb);
1713 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1717 + port->stat.rx_dropped++;
1718 + /* put the desc back on RX-ready queue */
1719 + desc->buf_len = MAX_MRU;
1720 + desc->pkt_len = 0;
1721 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1725 + /* process received frame */
1728 + skb = port->rx_buff_tab[n];
1729 + dma_unmap_single(&dev->dev, desc->data,
1730 + MAX_MRU, DMA_FROM_DEVICE);
1732 + dma_sync_single(&dev->dev, desc->data,
1733 + MAX_MRU, DMA_FROM_DEVICE);
1734 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1735 + ALIGN(desc->pkt_len, 4) / 4);
1737 + skb_put(skb, desc->pkt_len);
1739 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
1741 + skb->protocol = eth_type_trans(skb, dev);
1742 + dev->last_rx = jiffies;
1743 + port->stat.rx_packets++;
1744 + port->stat.rx_bytes += skb->len;
1745 + netif_receive_skb(skb);
1747 + /* put the new buffer on RX-free queue */
1749 + port->rx_buff_tab[n] = temp;
1750 + desc->data = phys;
1752 + desc->buf_len = MAX_MRU;
1753 + desc->pkt_len = 0;
1754 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1758 + dev->quota -= received;
1759 + *budget -= received;
1761 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
1763 + return 1; /* not all work done */
1767 +static void eth_txdone_irq(void *unused)
1772 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
1774 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
1775 + u32 npe_id, n_desc;
1776 + struct port *port;
1777 + struct desc *desc;
1780 + npe_id = phys & 3;
1781 + BUG_ON(npe_id >= MAX_NPES);
1782 + port = npe_port_tab[npe_id];
1784 + phys &= ~0x1F; /* mask out non-address bits */
1785 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
1786 + BUG_ON(n_desc >= TX_DESCS);
1787 + desc = tx_desc_ptr(port, n_desc);
1788 + debug_desc(phys, desc);
1790 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
1791 + port->stat.tx_packets++;
1792 + port->stat.tx_bytes += desc->pkt_len;
1794 + dma_unmap_tx(port, desc);
1796 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
1797 + port->netdev->name, port->tx_buff_tab[n_desc]);
1799 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1800 + port->tx_buff_tab[n_desc] = NULL;
1803 + start = qmgr_stat_empty(port->plat->txreadyq);
1804 + queue_put_desc(port->plat->txreadyq, phys, desc);
1807 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
1808 + port->netdev->name);
1810 + netif_wake_queue(port->netdev);
1815 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
1817 + struct port *port = netdev_priv(dev);
1818 + unsigned int txreadyq = port->plat->txreadyq;
1819 + int len, offset, bytes, n;
1822 + struct desc *desc;
1825 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
1828 + if (unlikely(skb->len > MAX_MRU)) {
1829 + dev_kfree_skb(skb);
1830 + port->stat.tx_errors++;
1831 + return NETDEV_TX_OK;
1834 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
1838 + offset = 0; /* no need to keep alignment */
1842 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
1843 + bytes = ALIGN(offset + len, 4);
1844 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1845 + dev_kfree_skb(skb);
1846 + port->stat.tx_dropped++;
1847 + return NETDEV_TX_OK;
1849 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1850 + dev_kfree_skb(skb);
1853 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1854 + if (dma_mapping_error(phys)) {
1856 + dev_kfree_skb(skb);
1860 + port->stat.tx_dropped++;
1861 + return NETDEV_TX_OK;
1864 + n = queue_get_desc(txreadyq, port, 1);
1866 + desc = tx_desc_ptr(port, n);
1869 + port->tx_buff_tab[n] = skb;
1871 + port->tx_buff_tab[n] = mem;
1873 + desc->data = phys + offset;
1874 + desc->buf_len = desc->pkt_len = len;
1876 + /* NPE firmware pads short frames with zeros internally */
1878 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
1879 + dev->trans_start = jiffies;
1881 + if (qmgr_stat_empty(txreadyq)) {
1883 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
1885 + netif_stop_queue(dev);
1886 + /* we could miss TX ready interrupt */
1887 + if (!qmgr_stat_empty(txreadyq)) {
1889 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
1892 + netif_wake_queue(dev);
1897 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
1899 + return NETDEV_TX_OK;
1903 +static struct net_device_stats *eth_stats(struct net_device *dev)
1905 + struct port *port = netdev_priv(dev);
1906 + return &port->stat;
1909 +static void eth_set_mcast_list(struct net_device *dev)
1911 + struct port *port = netdev_priv(dev);
1912 + struct dev_mc_list *mclist = dev->mc_list;
1913 + u8 diffs[ETH_ALEN], *addr;
1914 + int cnt = dev->mc_count, i;
1916 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
1917 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
1918 + &port->regs->rx_control[0]);
1922 + memset(diffs, 0, ETH_ALEN);
1923 + addr = mclist->dmi_addr; /* first MAC address */
1925 + while (--cnt && (mclist = mclist->next))
1926 + for (i = 0; i < ETH_ALEN; i++)
1927 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
1929 + for (i = 0; i < ETH_ALEN; i++) {
1930 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
1931 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
1934 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
1935 + &port->regs->rx_control[0]);
1939 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1941 + struct port *port = netdev_priv(dev);
1942 + unsigned int duplex_chg;
1945 + if (!netif_running(dev))
1947 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
1949 + eth_set_duplex(port);
1954 +static int request_queues(struct port *port)
1958 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
1962 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
1966 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
1970 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1974 + /* TX-done queue handles skbs sent out by the NPEs */
1975 + if (!ports_open) {
1976 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
1983 + qmgr_release_queue(port->plat->txreadyq);
1985 + qmgr_release_queue(TX_QUEUE(port->id));
1987 + qmgr_release_queue(port->plat->rxq);
1989 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1990 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1991 + port->netdev->name);
1995 +static void release_queues(struct port *port)
1997 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1998 + qmgr_release_queue(port->plat->rxq);
1999 + qmgr_release_queue(TX_QUEUE(port->id));
2000 + qmgr_release_queue(port->plat->txreadyq);
2003 + qmgr_release_queue(TXDONE_QUEUE);
2006 +static int init_queues(struct port *port)
2011 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
2012 + POOL_ALLOC_SIZE, 32, 0)))
2015 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
2016 + &port->desc_tab_phys)))
2018 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2019 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2020 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2022 + /* Setup RX buffers */
2023 + for (i = 0; i < RX_DESCS; i++) {
2024 + struct desc *desc = rx_desc_ptr(port, i);
2028 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
2030 + data = buff->data;
2032 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
2036 + desc->buf_len = MAX_MRU;
2037 + desc->data = dma_map_single(&port->netdev->dev, data,
2038 + MAX_MRU, DMA_FROM_DEVICE);
2039 + if (dma_mapping_error(desc->data)) {
2040 + free_buffer(buff);
2043 + port->rx_buff_tab[i] = buff;
2049 +static void destroy_queues(struct port *port)
2053 + if (port->desc_tab) {
2054 + for (i = 0; i < RX_DESCS; i++) {
2055 + struct desc *desc = rx_desc_ptr(port, i);
2056 + buffer_t *buff = port->rx_buff_tab[i];
2058 + dma_unmap_single(&port->netdev->dev,
2059 + desc->data, MAX_MRU,
2061 + free_buffer(buff);
2064 + for (i = 0; i < TX_DESCS; i++) {
2065 + struct desc *desc = tx_desc_ptr(port, i);
2066 + buffer_t *buff = port->tx_buff_tab[i];
2068 + dma_unmap_tx(port, desc);
2069 + free_buffer(buff);
2072 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2073 + port->desc_tab = NULL;
2076 + if (!ports_open && dma_pool) {
2077 + dma_pool_destroy(dma_pool);
2082 +static int eth_open(struct net_device *dev)
2084 + struct port *port = netdev_priv(dev);
2085 + struct npe *npe = port->npe;
2089 + if (!npe_running(npe)) {
2090 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2094 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
2095 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
2101 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
2103 + memset(&msg, 0, sizeof(msg));
2104 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
2105 + msg.eth_id = port->id;
2106 + msg.byte5 = port->plat->rxq | 0x80;
2107 + msg.byte7 = port->plat->rxq << 4;
2108 + for (i = 0; i < 8; i++) {
2110 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
2114 + msg.cmd = NPE_EDB_SETPORTADDRESS;
2115 + msg.eth_id = PHYSICAL_ID(port->id);
2116 + msg.byte2 = dev->dev_addr[0];
2117 + msg.byte3 = dev->dev_addr[1];
2118 + msg.byte4 = dev->dev_addr[2];
2119 + msg.byte5 = dev->dev_addr[3];
2120 + msg.byte6 = dev->dev_addr[4];
2121 + msg.byte7 = dev->dev_addr[5];
2122 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
2125 + memset(&msg, 0, sizeof(msg));
2126 + msg.cmd = NPE_FW_SETFIREWALLMODE;
2127 + msg.eth_id = port->id;
2128 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
2131 + if ((err = request_queues(port)) != 0)
2134 + if ((err = init_queues(port)) != 0) {
2135 + destroy_queues(port);
2136 + release_queues(port);
2140 + for (i = 0; i < ETH_ALEN; i++)
2141 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
2142 + __raw_writel(0x08, &port->regs->random_seed);
2143 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
2144 + __raw_writel(0x30, &port->regs->partial_full_threshold);
2145 + __raw_writel(0x08, &port->regs->tx_start_bytes);
2146 + __raw_writel(0x15, &port->regs->tx_deferral);
2147 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
2148 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
2149 + __raw_writel(0x80, &port->regs->slot_time);
2150 + __raw_writel(0x01, &port->regs->int_clock_threshold);
2152 + /* Populate queues with buffers, no failure after this point */
2153 + for (i = 0; i < TX_DESCS; i++)
2154 + queue_put_desc(port->plat->txreadyq,
2155 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2157 + for (i = 0; i < RX_DESCS; i++)
2158 + queue_put_desc(RXFREE_QUEUE(port->id),
2159 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2161 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
2162 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
2163 + __raw_writel(0, &port->regs->rx_control[1]);
2164 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
2166 + phy_check_media(port, 1);
2167 + eth_set_mcast_list(dev);
2168 + netif_start_queue(dev);
2169 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
2171 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
2173 + if (!ports_open) {
2174 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
2175 + eth_txdone_irq, NULL);
2176 + qmgr_enable_irq(TXDONE_QUEUE);
2179 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2183 +static int eth_close(struct net_device *dev)
2185 + struct port *port = netdev_priv(dev);
2187 + int buffs = RX_DESCS; /* allocated RX buffers */
2191 + qmgr_disable_irq(port->plat->rxq);
2192 + netif_stop_queue(dev);
2194 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
2197 + memset(&msg, 0, sizeof(msg));
2198 + msg.cmd = NPE_SETLOOPBACK_MODE;
2199 + msg.eth_id = port->id;
2201 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
2202 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
2205 + do { /* drain RX buffers */
2206 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
2210 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
2211 + /* we have to inject some packet */
2212 + struct desc *desc;
2214 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
2216 + desc = tx_desc_ptr(port, n);
2217 + phys = tx_desc_phys(port, n);
2218 + desc->buf_len = desc->pkt_len = 1;
2220 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
2223 + } while (++i < MAX_CLOSE_WAIT);
2226 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2227 + " left in NPE\n", dev->name, buffs);
2230 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
2234 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
2235 + buffs--; /* cancel TX */
2239 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2243 + } while (++i < MAX_CLOSE_WAIT);
2246 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2247 + "left in NPE\n", dev->name, buffs);
2250 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2254 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
2255 + printk(KERN_CRIT "%s: unable to disable loopback\n",
2258 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
2259 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
2260 + mdio_write(dev, port->plat->phy, MII_BMCR,
2261 + port->mii_bmcr | BMCR_PDOWN);
2264 + qmgr_disable_irq(TXDONE_QUEUE);
2265 + cancel_rearming_delayed_work(&port->mdio_thread);
2266 + destroy_queues(port);
2267 + release_queues(port);
2271 +static int __devinit eth_init_one(struct platform_device *pdev)
2273 + struct port *port;
2274 + struct net_device *dev;
2275 + struct eth_plat_info *plat = pdev->dev.platform_data;
2279 + if (!(dev = alloc_etherdev(sizeof(struct port))))
2282 + SET_MODULE_OWNER(dev);
2283 + SET_NETDEV_DEV(dev, &pdev->dev);
2284 + port = netdev_priv(dev);
2285 + port->netdev = dev;
2286 + port->id = pdev->id;
2288 + switch (port->id) {
2289 + case IXP4XX_ETH_NPEA:
2290 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
2291 + regs_phys = IXP4XX_EthA_BASE_PHYS;
2293 + case IXP4XX_ETH_NPEB:
2294 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2295 + regs_phys = IXP4XX_EthB_BASE_PHYS;
2297 + case IXP4XX_ETH_NPEC:
2298 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
2299 + regs_phys = IXP4XX_EthC_BASE_PHYS;
2306 + dev->open = eth_open;
2307 + dev->hard_start_xmit = eth_xmit;
2308 + dev->poll = eth_poll;
2309 + dev->stop = eth_close;
2310 + dev->get_stats = eth_stats;
2311 + dev->do_ioctl = eth_ioctl;
2312 + dev->set_multicast_list = eth_set_mcast_list;
2314 + dev->tx_queue_len = 100;
2316 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
2321 + if (register_netdev(dev)) {
2326 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
2327 + if (!port->mem_res) {
2332 + port->plat = plat;
2333 + npe_port_tab[NPE_ID(port->id)] = port;
2334 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
2336 + platform_set_drvdata(pdev, dev);
2338 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
2339 + &port->regs->core_control);
2341 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
2344 + port->mii.dev = dev;
2345 + port->mii.mdio_read = mdio_read;
2346 + port->mii.mdio_write = mdio_write;
2347 + port->mii.phy_id = plat->phy;
2348 + port->mii.phy_id_mask = 0x1F;
2349 + port->mii.reg_num_mask = 0x1F;
2351 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
2352 + npe_name(port->npe));
2354 + phy_reset(dev, plat->phy);
2355 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
2356 + ~(BMCR_RESET | BMCR_PDOWN);
2357 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
2359 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
2363 + unregister_netdev(dev);
2365 + npe_release(port->npe);
2371 +static int __devexit eth_remove_one(struct platform_device *pdev)
2373 + struct net_device *dev = platform_get_drvdata(pdev);
2374 + struct port *port = netdev_priv(dev);
2376 + unregister_netdev(dev);
2377 + npe_port_tab[NPE_ID(port->id)] = NULL;
2378 + platform_set_drvdata(pdev, NULL);
2379 + npe_release(port->npe);
2380 + release_resource(port->mem_res);
2385 +static struct platform_driver drv = {
2386 + .driver.name = DRV_NAME,
2387 + .probe = eth_init_one,
2388 + .remove = eth_remove_one,
2391 +static int __init eth_init_module(void)
2393 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
2396 + /* All MII PHY accesses use NPE-B Ethernet registers */
2397 + spin_lock_init(&mdio_lock);
2398 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2399 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
2401 + return platform_driver_register(&drv);
2404 +static void __exit eth_cleanup_module(void)
2406 + platform_driver_unregister(&drv);
2409 +MODULE_AUTHOR("Krzysztof Halasa");
2410 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
2411 +MODULE_LICENSE("GPL v2");
2412 +module_init(eth_init_module);
2413 +module_exit(eth_cleanup_module);
2414 diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
2415 index a3df09e..94e7aa7 100644
2416 --- a/drivers/net/wan/Kconfig
2417 +++ b/drivers/net/wan/Kconfig
2418 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
2420 Say Y if your card supports this feature.
2423 + tristate "IXP4xx HSS (synchronous serial port) support"
2424 + depends on HDLC && ARM && ARCH_IXP4XX
2426 + select IXP4XX_QMGR
2428 + Say Y here if you want to use built-in HSS ports
2429 + on IXP4xx processor.
2432 tristate "Frame Relay DLCI support"
2434 diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
2435 index d61fef3..1b1d116 100644
2436 --- a/drivers/net/wan/Makefile
2437 +++ b/drivers/net/wan/Makefile
2438 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
2439 obj-$(CONFIG_WANXL) += wanxl.o
2440 obj-$(CONFIG_PCI200SYN) += pci200syn.o
2441 obj-$(CONFIG_PC300TOO) += pc300too.o
2442 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
2444 clean-files := wanxlfw.inc
2445 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
2446 diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
2447 new file mode 100644
2448 index 0000000..c4cdace
2450 +++ b/drivers/net/wan/ixp4xx_hss.c
2453 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
2455 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2457 + * This program is free software; you can redistribute it and/or modify it
2458 + * under the terms of version 2 of the GNU General Public License
2459 + * as published by the Free Software Foundation.
2462 +#include <linux/dma-mapping.h>
2463 +#include <linux/dmapool.h>
2464 +#include <linux/io.h>
2465 +#include <linux/kernel.h>
2466 +#include <linux/hdlc.h>
2467 +#include <linux/platform_device.h>
2468 +#include <asm/arch/npe.h>
2469 +#include <asm/arch/qmgr.h>
2471 +#define DEBUG_QUEUES 0
2472 +#define DEBUG_DESC 0
2475 +#define DEBUG_PKT_BYTES 0
2476 +#define DEBUG_CLOSE 0
2478 +#define DRV_NAME "ixp4xx_hss"
2480 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
2481 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
2482 +#define FRAME_SYNC_SIZE 1024
2483 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
2484 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
2486 +#define RX_DESCS 16 /* also length of all RX queues */
2487 +#define TX_DESCS 16 /* also length of all TX queues */
2489 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
2490 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
2491 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
2494 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
2495 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
2496 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
2497 +#define HSS0_PKT_TX1_QUEUE 15
2498 +#define HSS0_PKT_TX2_QUEUE 16
2499 +#define HSS0_PKT_TX3_QUEUE 17
2500 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
2501 +#define HSS0_PKT_RXFREE1_QUEUE 19
2502 +#define HSS0_PKT_RXFREE2_QUEUE 20
2503 +#define HSS0_PKT_RXFREE3_QUEUE 21
2504 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
2506 +#define HSS1_CHL_RXTRIG_QUEUE 10
2507 +#define HSS1_PKT_RX_QUEUE 0
2508 +#define HSS1_PKT_TX0_QUEUE 5
2509 +#define HSS1_PKT_TX1_QUEUE 6
2510 +#define HSS1_PKT_TX2_QUEUE 7
2511 +#define HSS1_PKT_TX3_QUEUE 8
2512 +#define HSS1_PKT_RXFREE0_QUEUE 1
2513 +#define HSS1_PKT_RXFREE1_QUEUE 2
2514 +#define HSS1_PKT_RXFREE2_QUEUE 3
2515 +#define HSS1_PKT_RXFREE3_QUEUE 4
2516 +#define HSS1_PKT_TXDONE_QUEUE 9
2518 +#define NPE_PKT_MODE_HDLC 0
2519 +#define NPE_PKT_MODE_RAW 1
2520 +#define NPE_PKT_MODE_56KMODE 2
2521 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
2523 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
2524 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
2525 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
2526 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
2529 +/* hss_config, PCRs */
2530 +/* Frame sync sampling, default = active low */
2531 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
2532 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
2533 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
2535 +/* Frame sync pin: input (default) or output generated off a given clk edge */
2536 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
2537 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
2539 +/* Frame and data clock sampling on edge, default = falling */
2540 +#define PCR_FCLK_EDGE_RISING 0x08000000
2541 +#define PCR_DCLK_EDGE_RISING 0x04000000
2543 +/* Clock direction, default = input */
2544 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
2546 +/* Generate/Receive frame pulses, default = enabled */
2547 +#define PCR_FRM_PULSE_DISABLED 0x01000000
2549 + /* Data rate is full (default) or half the configured clk speed */
2550 +#define PCR_HALF_CLK_RATE 0x00200000
2552 +/* Invert data between NPE and HSS FIFOs? (default = no) */
2553 +#define PCR_DATA_POLARITY_INVERT 0x00100000
2555 +/* TX/RX endianness, default = LSB */
2556 +#define PCR_MSB_ENDIAN 0x00080000
2558 +/* Normal (default) / open drain mode (TX only) */
2559 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
2561 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
2562 +#define PCR_SOF_NO_FBIT 0x00020000
2564 +/* Drive data pins? */
2565 +#define PCR_TX_DATA_ENABLE 0x00010000
2567 +/* Voice 56k type: drive the data pins low (default), high, high Z */
2568 +#define PCR_TX_V56K_HIGH 0x00002000
2569 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
2571 +/* Unassigned type: drive the data pins low (default), high, high Z */
2572 +#define PCR_TX_UNASS_HIGH 0x00000800
2573 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
2575 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
2576 +#define PCR_TX_FB_HIGH_IMP 0x00000400
2578 +/* 56k data endiannes - which bit unused: high (default) or low */
2579 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
2581 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
2582 +#define PCR_TX_56KS_56K_DATA 0x00000100
2584 +/* hss_config, cCR */
2585 +/* Number of packetized clients, default = 1 */
2586 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
2587 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
2589 +/* default = no loopback */
2590 +#define CCR_LOOPBACK 0x02000000
2592 +/* HSS number, default = 0 (first) */
2593 +#define CCR_SECOND_HSS 0x01000000
2596 +/* hss_config, clkCR: main:10, num:10, denom:12 */
2597 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
2599 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
2600 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
2601 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
2602 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
2603 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
2604 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
2606 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
2607 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
2608 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
2609 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
2610 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
2611 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
2614 +/* hss_config, LUT entries */
2615 +#define TDMMAP_UNASSIGNED 0
2616 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
2617 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
2618 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
2620 +#define TIMESLOTS 128
2623 +/* offsets into HSS config */
2624 +#define HSS_CONFIG_TX_PCR 0x00
2625 +#define HSS_CONFIG_RX_PCR 0x04
2626 +#define HSS_CONFIG_CORE_CR 0x08
2627 +#define HSS_CONFIG_CLOCK_CR 0x0C
2628 +#define HSS_CONFIG_TX_FCR 0x10
2629 +#define HSS_CONFIG_RX_FCR 0x14
2630 +#define HSS_CONFIG_TX_LUT 0x18
2631 +#define HSS_CONFIG_RX_LUT 0x38
2634 +/* NPE command codes */
2635 +/* writes the ConfigWord value to the location specified by offset */
2636 +#define PORT_CONFIG_WRITE 0x40
2638 +/* triggers the NPE to load the contents of the configuration table */
2639 +#define PORT_CONFIG_LOAD 0x41
2641 +/* triggers the NPE to return an HssErrorReadResponse message */
2642 +#define PORT_ERROR_READ 0x42
2644 +/* reset NPE internal status and enable the HssChannelized operation */
2645 +#define CHAN_FLOW_ENABLE 0x43
2646 +#define CHAN_FLOW_DISABLE 0x44
2647 +#define CHAN_IDLE_PATTERN_WRITE 0x45
2648 +#define CHAN_NUM_CHANS_WRITE 0x46
2649 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
2650 +#define CHAN_RX_BUF_CFG_WRITE 0x48
2651 +#define CHAN_TX_BLK_CFG_WRITE 0x49
2652 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
2653 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
2654 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
2655 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
2657 +/* downloads the gainWord value for a timeslot switching channel associated
2659 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
2661 +/* triggers the NPE to reset internal status and enable the HssPacketized
2662 + operation for the flow specified by pPipe */
2663 +#define PKT_PIPE_FLOW_ENABLE 0x50
2664 +#define PKT_PIPE_FLOW_DISABLE 0x51
2665 +#define PKT_NUM_PIPES_WRITE 0x52
2666 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
2667 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
2668 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
2669 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
2670 +#define PKT_PIPE_MODE_WRITE 0x57
2672 +/* HDLC packet status values - desc->status */
2673 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
2674 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
2675 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
2676 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
2677 + this packet (if buf_len < pkt_len) */
2678 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
2679 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
2680 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
2684 +typedef struct sk_buff buffer_t;
2685 +#define free_buffer dev_kfree_skb
2686 +#define free_buffer_irq dev_kfree_skb_irq
2688 +typedef void buffer_t;
2689 +#define free_buffer kfree
2690 +#define free_buffer_irq kfree
2695 + struct net_device *netdev;
2696 + struct hss_plat_info *plat;
2697 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
2698 + struct desc *desc_tab; /* coherent */
2699 + u32 desc_tab_phys;
2701 + unsigned int clock_type, clock_rate, loopback;
2705 +/* NPE message structure */
2708 + u8 cmd, unused, hss_port, index;
2710 + struct { u8 data8a, data8b, data8c, data8d; };
2711 + struct { u16 data16a, data16b; };
2712 + struct { u32 data32; };
2715 + u8 index, hss_port, unused, cmd;
2717 + struct { u8 data8d, data8c, data8b, data8a; };
2718 + struct { u16 data16b, data16a; };
2719 + struct { u32 data32; };
2724 +/* HDLC packet descriptor */
2726 + u32 next; /* pointer to next buffer, unused */
2729 + u16 buf_len; /* buffer length */
2730 + u16 pkt_len; /* packet length */
2731 + u32 data; /* pointer to data buffer in RAM */
2736 + u16 pkt_len; /* packet length */
2737 + u16 buf_len; /* buffer length */
2738 + u32 data; /* pointer to data buffer in RAM */
2743 + u32 __reserved1[4];
2747 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2748 + (n) * sizeof(struct desc))
2749 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2751 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2752 + ((n) + RX_DESCS) * sizeof(struct desc))
2753 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2755 +/*****************************************************************************
2756 + * global variables
2757 + ****************************************************************************/
2759 +static int ports_open;
2760 +static struct dma_pool *dma_pool;
2762 +static const struct {
2763 + int tx, txdone, rx, rxfree;
2764 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
2765 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
2766 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
2767 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
2770 +/*****************************************************************************
2771 + * utility functions
2772 + ****************************************************************************/
2774 +static inline struct port* dev_to_port(struct net_device *dev)
2776 + return dev_to_hdlc(dev)->priv;
2780 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
2783 + for (i = 0; i < cnt; i++)
2784 + dest[i] = swab32(src[i]);
2788 +static inline void debug_pkt(struct net_device *dev, const char *func,
2789 + u8 *data, int len)
2791 +#if DEBUG_PKT_BYTES
2794 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
2795 + for (i = 0; i < len; i++) {
2796 + if (i >= DEBUG_PKT_BYTES)
2798 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
2805 +static inline void debug_desc(u32 phys, struct desc *desc)
2808 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
2809 + phys, desc->next, desc->buf_len, desc->pkt_len,
2810 + desc->data, desc->status, desc->error_count);
2814 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
2821 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
2822 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
2823 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
2824 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
2825 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
2826 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
2827 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
2828 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
2832 + for (i = 0; i < ARRAY_SIZE(names); i++)
2833 + if (names[i].queue == queue)
2836 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
2837 + i < ARRAY_SIZE(names) ? names[i].name : "",
2838 + is_get ? "->" : "<-", phys);
2842 +static inline u32 queue_get_entry(unsigned int queue)
2844 + u32 phys = qmgr_get_entry(queue);
2845 + debug_queue(queue, 1, phys);
2849 +static inline int queue_get_desc(unsigned int queue, struct port *port,
2852 + u32 phys, tab_phys, n_desc;
2855 + if (!(phys = queue_get_entry(queue)))
2858 + BUG_ON(phys & 0x1F);
2859 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
2860 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
2861 + n_desc = (phys - tab_phys) / sizeof(struct desc);
2862 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
2863 + debug_desc(phys, &tab[n_desc]);
2864 + BUG_ON(tab[n_desc].next);
2868 +static inline void queue_put_desc(unsigned int queue, u32 phys,
2869 + struct desc *desc)
2871 + debug_queue(queue, 0, phys);
2872 + debug_desc(phys, desc);
2873 + BUG_ON(phys & 0x1F);
2874 + qmgr_put_entry(queue, phys);
2875 + BUG_ON(qmgr_stat_overflow(queue));
2879 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
2882 + dma_unmap_single(&port->netdev->dev, desc->data,
2883 + desc->buf_len, DMA_TO_DEVICE);
2885 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
2886 + ALIGN((desc->data & 3) + desc->buf_len, 4),
2892 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
2894 + struct net_device *dev = pdev;
2896 + netif_carrier_on(dev);
2898 + netif_carrier_off(dev);
2901 +static void hss_hdlc_rx_irq(void *pdev)
2903 + struct net_device *dev = pdev;
2904 + struct port *port = dev_to_port(dev);
2907 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
2909 + qmgr_disable_irq(queue_ids[port->id].rx);
2910 + netif_rx_schedule(dev);
2913 +static int hss_hdlc_poll(struct net_device *dev, int *budget)
2915 + struct port *port = dev_to_port(dev);
2916 + unsigned int rxq = queue_ids[port->id].rx;
2917 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
2918 + struct net_device_stats *stats = hdlc_stats(dev);
2919 + int quota = dev->quota, received = 0;
2922 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
2926 + struct sk_buff *skb;
2927 + struct desc *desc;
2930 + struct sk_buff *temp;
2934 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
2935 + dev->quota -= received; /* No packet received */
2936 + *budget -= received;
2939 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2940 + " netif_rx_complete\n", dev->name);
2942 + netif_rx_complete(dev);
2943 + qmgr_enable_irq(rxq);
2944 + if (!qmgr_stat_empty(rxq) &&
2945 + netif_rx_reschedule(dev, 0)) {
2947 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2948 + " netif_rx_reschedule successed\n",
2951 + qmgr_disable_irq(rxq);
2955 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
2958 + return 0; /* all work done */
2961 + desc = rx_desc_ptr(port, n);
2963 + if (desc->error_count) /* FIXME - remove printk */
2964 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
2965 + " errors %u\n", dev->name, desc->status,
2966 + desc->error_count);
2969 + switch (desc->status) {
2972 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
2973 + phys = dma_map_single(&dev->dev, skb->data,
2976 + if (dma_mapping_error(phys)) {
2977 + dev_kfree_skb(skb);
2982 + skb = netdev_alloc_skb(dev, desc->pkt_len);
2985 + stats->rx_dropped++;
2987 + case ERR_HDLC_ALIGN:
2988 + case ERR_HDLC_ABORT:
2989 + stats->rx_frame_errors++;
2990 + stats->rx_errors++;
2992 + case ERR_HDLC_FCS:
2993 + stats->rx_crc_errors++;
2994 + stats->rx_errors++;
2996 + case ERR_HDLC_TOO_LONG:
2997 + stats->rx_length_errors++;
2998 + stats->rx_errors++;
3000 + default: /* FIXME - remove printk */
3001 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
3002 + " errors %u\n", dev->name, desc->status,
3003 + desc->error_count);
3004 + stats->rx_errors++;
3008 + /* put the desc back on RX-ready queue */
3009 + desc->buf_len = RX_SIZE;
3010 + desc->pkt_len = desc->status = 0;
3011 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3015 + /* process received frame */
3018 + skb = port->rx_buff_tab[n];
3019 + dma_unmap_single(&dev->dev, desc->data,
3020 + RX_SIZE, DMA_FROM_DEVICE);
3022 + dma_sync_single(&dev->dev, desc->data,
3023 + RX_SIZE, DMA_FROM_DEVICE);
3024 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
3025 + ALIGN(desc->pkt_len, 4) / 4);
3027 + skb_put(skb, desc->pkt_len);
3029 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
3031 + skb->protocol = hdlc_type_trans(skb, dev);
3032 + dev->last_rx = jiffies;
3033 + stats->rx_packets++;
3034 + stats->rx_bytes += skb->len;
3035 + netif_receive_skb(skb);
3037 + /* put the new buffer on RX-free queue */
3039 + port->rx_buff_tab[n] = temp;
3040 + desc->data = phys;
3042 + desc->buf_len = RX_SIZE;
3043 + desc->pkt_len = 0;
3044 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3048 + dev->quota -= received;
3049 + *budget -= received;
3051 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
3053 + return 1; /* not all work done */
3057 +static void hss_hdlc_txdone_irq(void *pdev)
3059 + struct net_device *dev = pdev;
3060 + struct port *port = dev_to_port(dev);
3061 + struct net_device_stats *stats = hdlc_stats(dev);
3065 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
3067 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
3069 + struct desc *desc;
3072 + desc = tx_desc_ptr(port, n_desc);
3074 + stats->tx_packets++;
3075 + stats->tx_bytes += desc->pkt_len;
3077 + dma_unmap_tx(port, desc);
3079 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
3080 + port->netdev->name, port->tx_buff_tab[n_desc]);
3082 + free_buffer_irq(port->tx_buff_tab[n_desc]);
3083 + port->tx_buff_tab[n_desc] = NULL;
3085 + start = qmgr_stat_empty(port->plat->txreadyq);
3086 + queue_put_desc(port->plat->txreadyq,
3087 + tx_desc_phys(port, n_desc), desc);
3090 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
3091 + " ready\n", port->netdev->name);
3093 + netif_wake_queue(port->netdev);
3098 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
3100 + struct port *port = dev_to_port(dev);
3101 + struct net_device_stats *stats = hdlc_stats(dev);
3102 + unsigned int txreadyq = port->plat->txreadyq;
3103 + int len, offset, bytes, n;
3106 + struct desc *desc;
3109 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
3112 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
3113 + dev_kfree_skb(skb);
3114 + stats->tx_errors++;
3115 + return NETDEV_TX_OK;
3118 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
3122 + offset = 0; /* no need to keep alignment */
3126 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
3127 + bytes = ALIGN(offset + len, 4);
3128 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
3129 + dev_kfree_skb(skb);
3130 + stats->tx_dropped++;
3131 + return NETDEV_TX_OK;
3133 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
3134 + dev_kfree_skb(skb);
3137 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
3138 + if (dma_mapping_error(phys)) {
3140 + dev_kfree_skb(skb);
3144 + stats->tx_dropped++;
3145 + return NETDEV_TX_OK;
3148 + n = queue_get_desc(txreadyq, port, 1);
3150 + desc = tx_desc_ptr(port, n);
3153 + port->tx_buff_tab[n] = skb;
3155 + port->tx_buff_tab[n] = mem;
3157 + desc->data = phys + offset;
3158 + desc->buf_len = desc->pkt_len = len;
3161 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
3162 + dev->trans_start = jiffies;
3164 + if (qmgr_stat_empty(txreadyq)) {
3166 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
3168 + netif_stop_queue(dev);
3169 + /* we could miss TX ready interrupt */
3170 + if (!qmgr_stat_empty(txreadyq)) {
3172 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
3175 + netif_wake_queue(dev);
3180 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
3182 + return NETDEV_TX_OK;
3186 +static int request_hdlc_queues(struct port *port)
3190 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
3194 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
3198 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
3202 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
3206 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
3212 + qmgr_release_queue(port->plat->txreadyq);
3214 + qmgr_release_queue(queue_ids[port->id].tx);
3216 + qmgr_release_queue(queue_ids[port->id].rx);
3218 + qmgr_release_queue(queue_ids[port->id].rxfree);
3219 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
3220 + port->netdev->name);
3224 +static void release_hdlc_queues(struct port *port)
3226 + qmgr_release_queue(queue_ids[port->id].rxfree);
3227 + qmgr_release_queue(queue_ids[port->id].rx);
3228 + qmgr_release_queue(queue_ids[port->id].txdone);
3229 + qmgr_release_queue(queue_ids[port->id].tx);
3230 + qmgr_release_queue(port->plat->txreadyq);
3233 +static int init_hdlc_queues(struct port *port)
3238 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
3239 + POOL_ALLOC_SIZE, 32, 0)))
3242 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
3243 + &port->desc_tab_phys)))
3245 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
3246 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
3247 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
3249 + /* Setup RX buffers */
3250 + for (i = 0; i < RX_DESCS; i++) {
3251 + struct desc *desc = rx_desc_ptr(port, i);
3255 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
3257 + data = buff->data;
3259 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
3263 + desc->buf_len = RX_SIZE;
3264 + desc->data = dma_map_single(&port->netdev->dev, data,
3265 + RX_SIZE, DMA_FROM_DEVICE);
3266 + if (dma_mapping_error(desc->data)) {
3267 + free_buffer(buff);
3270 + port->rx_buff_tab[i] = buff;
3276 +static void destroy_hdlc_queues(struct port *port)
3280 + if (port->desc_tab) {
3281 + for (i = 0; i < RX_DESCS; i++) {
3282 + struct desc *desc = rx_desc_ptr(port, i);
3283 + buffer_t *buff = port->rx_buff_tab[i];
3285 + dma_unmap_single(&port->netdev->dev,
3286 + desc->data, RX_SIZE,
3288 + free_buffer(buff);
3291 + for (i = 0; i < TX_DESCS; i++) {
3292 + struct desc *desc = tx_desc_ptr(port, i);
3293 + buffer_t *buff = port->tx_buff_tab[i];
3295 + dma_unmap_tx(port, desc);
3296 + free_buffer(buff);
3299 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
3300 + port->desc_tab = NULL;
3303 + if (!ports_open && dma_pool) {
3304 + dma_pool_destroy(dma_pool);
3309 +static int hss_hdlc_open(struct net_device *dev)
3311 + struct port *port = dev_to_port(dev);
3312 + struct npe *npe = port->npe;
3316 + if (!npe_running(npe)) {
3317 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
3322 + if ((err = hdlc_open(dev)) != 0)
3325 + if (port->plat->open)
3326 + if ((err = port->plat->open(port->id, port->netdev,
3327 + hss_hdlc_set_carrier)) != 0)
3328 + goto err_hdlc_close;
3330 + /* HSS main configuration */
3331 + memset(&msg, 0, sizeof(msg));
3332 + msg.cmd = PORT_CONFIG_WRITE;
3333 + msg.hss_port = port->id;
3334 + msg.index = 0; /* offset in HSS config */
3336 + msg.data32 = PCR_FRM_PULSE_DISABLED |
3339 + PCR_TX_DATA_ENABLE;
3341 + if (port->clock_type == CLOCK_INT)
3342 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
3344 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
3345 + goto err_plat_close; /* 0: TX PCR */
3348 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
3349 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
3350 + goto err_plat_close; /* 4: RX PCR */
3353 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
3354 + (port->id ? CCR_SECOND_HSS : 0);
3355 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
3356 + goto err_plat_close; /* 8: Core CR */
3359 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
3360 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
3361 + goto err_plat_close; /* 12: CLK CR */
3363 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
3365 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
3366 + goto err_plat_close; /* 16: TX FCR */
3369 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
3370 + goto err_plat_close; /* 20: RX FCR */
3372 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
3373 + for (i = 0; i < 32 / LUT_BITS; i++)
3374 + msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i);
3376 + for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) {
3377 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
3378 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
3379 + goto err_plat_close;
3382 + /* HDLC mode configuration */
3383 + memset(&msg, 0, sizeof(msg));
3384 + msg.cmd = PKT_NUM_PIPES_WRITE;
3385 + msg.hss_port = port->id;
3386 + msg.data8a = PKT_NUM_PIPES;
3387 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
3388 + goto err_plat_close;
3390 + memset(&msg, 0, sizeof(msg));
3391 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
3392 + msg.hss_port = port->id;
3393 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
3394 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
3395 + goto err_plat_close;
3397 + memset(&msg, 0, sizeof(msg));
3398 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
3399 + msg.hss_port = port->id;
3400 + msg.data32 = 0x7F7F7F7F;
3401 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
3402 + goto err_plat_close;
3404 + memset(&msg, 0, sizeof(msg));
3405 + msg.cmd = PORT_CONFIG_LOAD;
3406 + msg.hss_port = port->id;
3407 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3408 + goto err_plat_close;
3409 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3410 + goto err_plat_close;
3412 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
3413 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
3414 + printk(KERN_DEBUG "%s: unexpected message received in"
3415 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
3417 + goto err_plat_close;
3420 + memset(&msg, 0, sizeof(msg));
3421 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
3422 + msg.hss_port = port->id;
3423 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
3424 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
3425 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
3426 + goto err_plat_close;
3428 + memset(&msg, 0, sizeof(msg));
3429 + msg.cmd = PKT_PIPE_MODE_WRITE;
3430 + msg.hss_port = port->id;
3431 + msg.data8a = NPE_PKT_MODE_HDLC;
3432 + /* msg.data8b = inv_mask */
3433 + /* msg.data8c = or_mask */
3434 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
3435 + goto err_plat_close;
3437 + memset(&msg, 0, sizeof(msg));
3438 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
3439 + msg.hss_port = port->id;
3440 + msg.data16a = HDLC_MAX_MRU;
3441 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
3442 + goto err_plat_close;
3444 + if ((err = request_hdlc_queues(port)) != 0)
3445 + goto err_plat_close;
3447 + if ((err = init_hdlc_queues(port)) != 0)
3448 + goto err_destroy_queues;
3450 + memset(&msg, 0, sizeof(msg));
3451 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
3452 + msg.hss_port = port->id;
3453 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
3454 + goto err_destroy_queues;
3456 + /* Populate queues with buffers, no failure after this point */
3457 + for (i = 0; i < TX_DESCS; i++)
3458 + queue_put_desc(port->plat->txreadyq,
3459 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
3461 + for (i = 0; i < RX_DESCS; i++)
3462 + queue_put_desc(queue_ids[port->id].rxfree,
3463 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
3465 + netif_start_queue(dev);
3467 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
3468 + hss_hdlc_rx_irq, dev);
3470 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
3471 + hss_hdlc_txdone_irq, dev);
3472 + qmgr_enable_irq(queue_ids[port->id].txdone);
3475 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
3478 +err_destroy_queues:
3479 + destroy_hdlc_queues(port);
3480 + release_hdlc_queues(port);
3482 + if (port->plat->close)
3483 + port->plat->close(port->id, port->netdev);
3489 +static int hss_hdlc_close(struct net_device *dev)
3491 + struct port *port = dev_to_port(dev);
3492 + struct npe *npe = port->npe;
3494 + int buffs = RX_DESCS; /* allocated RX buffers */
3498 + qmgr_disable_irq(queue_ids[port->id].rx);
3499 + netif_stop_queue(dev);
3501 + memset(&msg, 0, sizeof(msg));
3502 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
3503 + msg.hss_port = port->id;
3504 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
3505 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
3507 + /* The upper level would ignore the error anyway */
3510 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
3512 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
3516 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
3517 + " left in NPE\n", dev->name, buffs);
3520 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
3521 + buffs--; /* cancel TX */
3525 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
3529 + } while (++i < MAX_CLOSE_WAIT);
3532 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
3533 + "left in NPE\n", dev->name, buffs);
3536 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
3538 + qmgr_disable_irq(queue_ids[port->id].txdone);
3539 + destroy_hdlc_queues(port);
3540 + release_hdlc_queues(port);
3542 + if (port->plat->close)
3543 + port->plat->close(port->id, port->netdev);
3549 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
3550 + unsigned short parity)
3552 + struct port *port = dev_to_port(dev);
3554 + if (encoding != ENCODING_NRZ)
3558 + case PARITY_CRC16_PR1_CCITT:
3559 + port->hdlc_cfg = 0;
3562 + case PARITY_CRC32_PR1_CCITT:
3563 + port->hdlc_cfg = PKT_HDLC_CRC_32;
3572 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3574 + const size_t size = sizeof(sync_serial_settings);
3575 + sync_serial_settings new_line;
3577 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
3578 + struct port *port = dev_to_port(dev);
3580 + if (cmd != SIOCWANDEV)
3581 + return hdlc_ioctl(dev, ifr, cmd);
3583 + switch(ifr->ifr_settings.type) {
3584 + case IF_GET_IFACE:
3585 + ifr->ifr_settings.type = IF_IFACE_V35;
3586 + if (ifr->ifr_settings.size < size) {
3587 + ifr->ifr_settings.size = size; /* data size wanted */
3590 + memset(&new_line, 0, sizeof(new_line));
3591 + new_line.clock_type = port->clock_type;
3592 + new_line.clock_rate = port->clock_rate;
3593 + new_line.loopback = port->loopback;
3594 + if (copy_to_user(line, &new_line, size))
3598 + case IF_IFACE_SYNC_SERIAL:
3599 + case IF_IFACE_V35:
3600 + if(!capable(CAP_NET_ADMIN))
3602 + if (dev->flags & IFF_UP)
3603 + return -EBUSY; /* Cannot change parameters when open */
3605 + if (copy_from_user(&new_line, line, size))
3608 + clk = new_line.clock_type;
3609 + if (port->plat->set_clock)
3610 + clk = port->plat->set_clock(port->id, clk);
3612 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
3613 + return -EINVAL; /* No such clock setting */
3615 + if (new_line.loopback != 0 && new_line.loopback != 1)
3618 + port->clock_type = clk; /* Update settings */
3619 + port->clock_rate = new_line.clock_rate;
3620 + port->loopback = new_line.loopback;
3624 + return hdlc_ioctl(dev, ifr, cmd);
3629 +static int __devinit hss_init_one(struct platform_device *pdev)
3631 + struct port *port;
3632 + struct net_device *dev;
3633 + hdlc_device *hdlc;
3636 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
3638 + platform_set_drvdata(pdev, port);
3639 + port->id = pdev->id;
3641 + if ((port->npe = npe_request(0)) == NULL) {
3646 + port->plat = pdev->dev.platform_data;
3647 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
3652 + SET_MODULE_OWNER(net);
3653 + SET_NETDEV_DEV(dev, &pdev->dev);
3654 + hdlc = dev_to_hdlc(dev);
3655 + hdlc->attach = hss_hdlc_attach;
3656 + hdlc->xmit = hss_hdlc_xmit;
3657 + dev->open = hss_hdlc_open;
3658 + dev->poll = hss_hdlc_poll;
3659 + dev->stop = hss_hdlc_close;
3660 + dev->do_ioctl = hss_hdlc_ioctl;
3662 + dev->tx_queue_len = 100;
3663 + port->clock_type = CLOCK_EXT;
3664 + port->clock_rate = 2048000;
3666 + if (register_hdlc_device(dev)) {
3667 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
3670 + goto err_free_netdev;
3672 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
3678 + npe_release(port->npe);
3679 + platform_set_drvdata(pdev, NULL);
3685 +static int __devexit hss_remove_one(struct platform_device *pdev)
3687 + struct port *port = platform_get_drvdata(pdev);
3689 + unregister_hdlc_device(port->netdev);
3690 + free_netdev(port->netdev);
3691 + npe_release(port->npe);
3692 + platform_set_drvdata(pdev, NULL);
3697 +static struct platform_driver drv = {
3698 + .driver.name = DRV_NAME,
3699 + .probe = hss_init_one,
3700 + .remove = hss_remove_one,
3703 +static int __init hss_init_module(void)
3705 + if ((ixp4xx_read_feature_bits() &
3706 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
3707 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
3709 + return platform_driver_register(&drv);
3712 +static void __exit hss_cleanup_module(void)
3714 + platform_driver_unregister(&drv);
3717 +MODULE_AUTHOR("Krzysztof Halasa");
3718 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
3719 +MODULE_LICENSE("GPL v2");
3720 +module_init(hss_init_module);
3721 +module_exit(hss_cleanup_module);
3722 diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
3723 index d2523b3..2fa3d6b 100644
3724 --- a/include/asm-arm/arch-ixp4xx/cpu.h
3725 +++ b/include/asm-arm/arch-ixp4xx/cpu.h
3726 @@ -28,4 +28,19 @@ extern unsigned int processor_id;
3727 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
3728 IXP465_PROCESSOR_ID_VALUE)
3730 +static inline u32 ixp4xx_read_feature_bits(void)
3732 + unsigned int val = ~*IXP4XX_EXP_CFG2;
3733 + val &= ~IXP4XX_FEATURE_RESERVED;
3734 + if (!cpu_is_ixp46x())
3735 + val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
3740 +static inline void ixp4xx_write_feature_bits(u32 value)
3742 + *IXP4XX_EXP_CFG2 = ~value;
3745 #endif /* _ASM_ARCH_CPU_H */
3746 diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
3747 index 297ceda..73e8dc3 100644
3748 --- a/include/asm-arm/arch-ixp4xx/hardware.h
3749 +++ b/include/asm-arm/arch-ixp4xx/hardware.h
3752 #define pcibios_assign_all_busses() 1
3754 +/* Register locations and bits */
3755 +#include "ixp4xx-regs.h"
3757 #ifndef __ASSEMBLER__
3758 #include <asm/arch/cpu.h>
3761 -/* Register locations and bits */
3762 -#include "ixp4xx-regs.h"
3764 /* Platform helper functions and definitions */
3765 #include "platform.h"
3767 diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3768 index 5d949d7..c704fe8 100644
3769 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3770 +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3775 -#ifndef __ASM_ARCH_HARDWARE_H__
3776 -#error "Do not include this directly, instead #include <asm/hardware.h>"
3779 #ifndef _ASM_ARM_IXP4XX_H_
3780 #define _ASM_ARM_IXP4XX_H_
3782 @@ -607,4 +603,36 @@
3784 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
3786 +/* "fuse" bits of IXP_EXP_CFG2 */
3787 +#define IXP4XX_FEATURE_RCOMP (1 << 0)
3788 +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
3789 +#define IXP4XX_FEATURE_HASH (1 << 2)
3790 +#define IXP4XX_FEATURE_AES (1 << 3)
3791 +#define IXP4XX_FEATURE_DES (1 << 4)
3792 +#define IXP4XX_FEATURE_HDLC (1 << 5)
3793 +#define IXP4XX_FEATURE_AAL (1 << 6)
3794 +#define IXP4XX_FEATURE_HSS (1 << 7)
3795 +#define IXP4XX_FEATURE_UTOPIA (1 << 8)
3796 +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
3797 +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
3798 +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
3799 +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
3800 +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
3801 +#define IXP4XX_FEATURE_PCI (1 << 14)
3802 +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
3803 +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
3804 +#define IXP4XX_FEATURE_USB_HOST (1 << 18)
3805 +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
3806 +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
3807 +#define IXP4XX_FEATURE_RSA (1 << 21)
3808 +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
3809 +#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
3811 +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
3812 + IXP4XX_FEATURE_USB_HOST | \
3813 + IXP4XX_FEATURE_NPEA_ETH | \
3814 + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
3815 + IXP4XX_FEATURE_RSA | \
3816 + IXP4XX_FEATURE_XSCALE_MAX_FREQ)
3819 diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h
3820 new file mode 100644
3821 index 0000000..37d0511
3823 +++ b/include/asm-arm/arch-ixp4xx/npe.h
3825 +#ifndef __IXP4XX_NPE_H
3826 +#define __IXP4XX_NPE_H
3828 +#include <linux/kernel.h>
3830 +extern const char *npe_names[];
3833 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
3834 + u32 action_points[4];
3835 + u32 watchpoint_fifo, watch_count;
3836 + u32 profile_count;
3837 + u32 messaging_status, messaging_control;
3838 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
3842 + struct resource *mem_res;
3843 + struct npe_regs __iomem *regs;
3850 +static inline const char *npe_name(struct npe *npe)
3852 + return npe_names[npe->id];
3855 +int npe_running(struct npe *npe);
3856 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
3857 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
3858 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
3859 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
3860 +struct npe *npe_request(int id);
3861 +void npe_release(struct npe *npe);
3863 +#endif /* __IXP4XX_NPE_H */
3864 diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
3865 index 2a44d3d..695b9c4 100644
3866 --- a/include/asm-arm/arch-ixp4xx/platform.h
3867 +++ b/include/asm-arm/arch-ixp4xx/platform.h
3868 @@ -77,8 +77,7 @@ extern unsigned long ixp4xx_exp_bus_size;
3871 * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
3873 - * Used as platform_data to provide GPIO pin information to the ixp42x
3874 + * used as platform_data to provide GPIO pin information to the ixp42x
3877 struct ixp4xx_i2c_pins {
3878 @@ -86,6 +85,27 @@ struct ixp4xx_i2c_pins {
3879 unsigned long scl_pin;
3882 +#define IXP4XX_ETH_NPEA 0x00
3883 +#define IXP4XX_ETH_NPEB 0x10
3884 +#define IXP4XX_ETH_NPEC 0x20
3886 +/* Information about built-in Ethernet MAC interfaces */
3887 +struct eth_plat_info {
3888 + u8 phy; /* MII PHY ID, 0 - 31 */
3889 + u8 rxq; /* configurable, currently 0 - 31 only */
3894 +/* Information about built-in HSS (synchronous serial) interfaces */
3895 +struct hss_plat_info {
3896 + int (*set_clock)(int port, unsigned int clock_type);
3897 + int (*open)(int port, void *pdev,
3898 + void (*set_carrier_cb)(void *pdev, int carrier));
3899 + void (*close)(int port, void *pdev);
3904 * This structure provide a means for the board setup code
3905 * to give information to th pata_ixp4xx driver. It is
3906 diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h
3907 new file mode 100644
3908 index 0000000..1e52b95
3910 +++ b/include/asm-arm/arch-ixp4xx/qmgr.h
3913 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3915 + * This program is free software; you can redistribute it and/or modify it
3916 + * under the terms of version 2 of the GNU General Public License
3917 + * as published by the Free Software Foundation.
3920 +#ifndef IXP4XX_QMGR_H
3921 +#define IXP4XX_QMGR_H
3923 +#include <linux/io.h>
3924 +#include <linux/kernel.h>
3926 +#define HALF_QUEUES 32
3927 +#define QUEUES 64 /* only 32 lower queues currently supported */
3928 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
3930 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
3931 +#define QUEUE_STAT1_NEARLY_EMPTY 2
3932 +#define QUEUE_STAT1_NEARLY_FULL 4
3933 +#define QUEUE_STAT1_FULL 8
3934 +#define QUEUE_STAT2_UNDERFLOW 1
3935 +#define QUEUE_STAT2_OVERFLOW 2
3937 +#define QUEUE_WATERMARK_0_ENTRIES 0
3938 +#define QUEUE_WATERMARK_1_ENTRY 1
3939 +#define QUEUE_WATERMARK_2_ENTRIES 2
3940 +#define QUEUE_WATERMARK_4_ENTRIES 3
3941 +#define QUEUE_WATERMARK_8_ENTRIES 4
3942 +#define QUEUE_WATERMARK_16_ENTRIES 5
3943 +#define QUEUE_WATERMARK_32_ENTRIES 6
3944 +#define QUEUE_WATERMARK_64_ENTRIES 7
3946 +/* queue interrupt request conditions */
3947 +#define QUEUE_IRQ_SRC_EMPTY 0
3948 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
3949 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
3950 +#define QUEUE_IRQ_SRC_FULL 3
3951 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
3952 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
3953 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
3954 +#define QUEUE_IRQ_SRC_NOT_FULL 7
3957 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
3958 + u32 stat1[4]; /* 0x400 - 0x40F */
3959 + u32 stat2[2]; /* 0x410 - 0x417 */
3960 + u32 statne_h; /* 0x418 - queue nearly empty */
3961 + u32 statf_h; /* 0x41C - queue full */
3962 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
3963 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
3964 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
3965 + u32 reserved[1776];
3966 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
3969 +void qmgr_set_irq(unsigned int queue, int src,
3970 + void (*handler)(void *pdev), void *pdev);
3971 +void qmgr_enable_irq(unsigned int queue);
3972 +void qmgr_disable_irq(unsigned int queue);
3974 +/* request_ and release_queue() must be called from non-IRQ context */
3975 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3976 + unsigned int nearly_empty_watermark,
3977 + unsigned int nearly_full_watermark);
3978 +void qmgr_release_queue(unsigned int queue);
3981 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
3983 + extern struct qmgr_regs __iomem *qmgr_regs;
3984 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
3987 +static inline u32 qmgr_get_entry(unsigned int queue)
3989 + extern struct qmgr_regs __iomem *qmgr_regs;
3990 + return __raw_readl(&qmgr_regs->acc[queue][0]);
3993 +static inline int qmgr_get_stat1(unsigned int queue)
3995 + extern struct qmgr_regs __iomem *qmgr_regs;
3996 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
3997 + >> ((queue & 7) << 2)) & 0xF;
4000 +static inline int qmgr_get_stat2(unsigned int queue)
4002 + extern struct qmgr_regs __iomem *qmgr_regs;
4003 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
4004 + >> ((queue & 0xF) << 1)) & 0x3;
4007 +static inline int qmgr_stat_empty(unsigned int queue)
4009 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
4012 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
4014 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
4017 +static inline int qmgr_stat_nearly_full(unsigned int queue)
4019 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
4022 +static inline int qmgr_stat_full(unsigned int queue)
4024 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
4027 +static inline int qmgr_stat_underflow(unsigned int queue)
4029 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
4032 +static inline int qmgr_stat_overflow(unsigned int queue)
4034 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
4038 diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
4039 index f7a35b7..34ef48f 100644
4040 --- a/include/asm-arm/arch-ixp4xx/uncompress.h
4041 +++ b/include/asm-arm/arch-ixp4xx/uncompress.h
4043 #ifndef _ARCH_UNCOMPRESS_H_
4044 #define _ARCH_UNCOMPRESS_H_
4046 -#include <asm/hardware.h>
4047 +#include "ixp4xx-regs.h"
4048 #include <asm/mach-types.h>
4049 #include <linux/serial_reg.h>