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fix networking
[openwrt.git] / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.15/arch/mips/aruba/flash_lock.c linux-2.6.15-openwrt/arch/mips/aruba/flash_lock.c
2 --- linux-2.6.15/arch/mips/aruba/flash_lock.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.15-openwrt/arch/mips/aruba/flash_lock.c 2006-01-10 00:32:32.000000000 +0100
4 @@ -0,0 +1,27 @@
5 +#include <linux/module.h>
6 +#include <linux/types.h>
7 +#include <asm/bootinfo.h>
8 +
9 +#define AP70_PROT_ADDR 0xb8010008
10 +#define AP70_PROT_DATA 0x8
11 +#define AP60_PROT_ADDR 0xB8400000
12 +#define AP60_PROT_DATA 0x04000000
13 +
14 +void unlock_ap60_70_flash(void)
15 +{
16 + volatile __u32 val;
17 + switch (mips_machtype) {
18 + case MACH_ARUBA_AP70:
19 + val = *(volatile __u32 *)AP70_PROT_ADDR;
20 + val &= ~(AP70_PROT_DATA);
21 + *(volatile __u32 *)AP70_PROT_ADDR = val;
22 + break;
23 + case MACH_ARUBA_AP65:
24 + case MACH_ARUBA_AP60:
25 + default:
26 + val = *(volatile __u32 *)AP60_PROT_ADDR;
27 + val &= ~(AP60_PROT_DATA);
28 + *(volatile __u32 *)AP60_PROT_ADDR = val;
29 + break;
30 + }
31 +}
32 diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S
33 --- linux-2.6.15/arch/mips/aruba/idtIRQ.S 1970-01-01 01:00:00.000000000 +0100
34 +++ linux-2.6.15-openwrt/arch/mips/aruba/idtIRQ.S 2006-01-10 00:32:32.000000000 +0100
35 @@ -0,0 +1,87 @@
36 +/**************************************************************************
37 + *
38 + * BRIEF MODULE DESCRIPTION
39 + * Intterrupt dispatcher code for IDT boards
40 + *
41 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
42 + *
43 + * This program is free software; you can redistribute it and/or modify it
44 + * under the terms of the GNU General Public License as published by the
45 + * Free Software Foundation; either version 2 of the License, or (at your
46 + * option) any later version.
47 + *
48 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
49 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
50 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
51 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
54 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
55 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 + *
59 + * You should have received a copy of the GNU General Public License along
60 + * with this program; if not, write to the Free Software Foundation, Inc.,
61 + * 675 Mass Ave, Cambridge, MA 02139, USA.
62 + *
63 + *
64 + **************************************************************************
65 + * May 2004 rkt, neb
66 + *
67 + * Initial Release
68 + *
69 + *
70 + *
71 + **************************************************************************
72 + */
73 +
74 +
75 +#include <asm/asm.h>
76 +#include <asm/mipsregs.h>
77 +#include <asm/regdef.h>
78 +#include <asm/stackframe.h>
79 +
80 + .text
81 + .set noreorder
82 + .set noat
83 + .align 5
84 + NESTED(idtIRQ, PT_SIZE, sp)
85 + .set noat
86 + SAVE_ALL
87 + CLI
88 +
89 + .set at
90 + .set noreorder
91 +
92 + /* Get the pending interrupts */
93 + mfc0 t0, CP0_CAUSE
94 + nop
95 +
96 + /* Isolate the allowed ones by anding the irq mask */
97 + mfc0 t2, CP0_STATUS
98 + move a1, sp /* need a nop here, hence we anticipate */
99 + andi t0, CAUSEF_IP
100 + and t0, t2
101 +
102 + /* check for r4k counter/timer IRQ. */
103 +
104 + andi t1, t0, CAUSEF_IP7
105 + beqz t1, 1f
106 + nop
107 +
108 + jal aruba_timer_interrupt
109 +
110 + li a0, 7
111 +
112 + j ret_from_irq
113 + nop
114 +1:
115 + jal aruba_irqdispatch
116 + move a0, t0
117 + j ret_from_irq
118 + nop
119 +
120 + END(idtIRQ)
121 +
122 +
123 diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
124 --- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
125 +++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
126 @@ -0,0 +1,394 @@
127 +/**************************************************************************
128 + *
129 + * BRIEF MODULE DESCRIPTION
130 + * Interrupt routines for IDT EB434 boards
131 + *
132 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
133 + *
134 + * This program is free software; you can redistribute it and/or modify it
135 + * under the terms of the GNU General Public License as published by the
136 + * Free Software Foundation; either version 2 of the License, or (at your
137 + * option) any later version.
138 + *
139 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
140 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
141 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
142 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
143 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
144 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
145 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
146 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
147 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
148 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
149 + *
150 + * You should have received a copy of the GNU General Public License along
151 + * with this program; if not, write to the Free Software Foundation, Inc.,
152 + * 675 Mass Ave, Cambridge, MA 02139, USA.
153 + *
154 + *
155 + **************************************************************************
156 + * May 2004 rkt, neb
157 + *
158 + * Initial Release
159 + *
160 + *
161 + *
162 + **************************************************************************
163 + */
164 +
165 +#include <linux/errno.h>
166 +#include <linux/init.h>
167 +#include <linux/kernel_stat.h>
168 +#include <linux/module.h>
169 +#include <linux/signal.h>
170 +#include <linux/sched.h>
171 +#include <linux/types.h>
172 +#include <linux/interrupt.h>
173 +#include <linux/ioport.h>
174 +#include <linux/timex.h>
175 +#include <linux/slab.h>
176 +#include <linux/random.h>
177 +#include <linux/delay.h>
178 +
179 +#include <asm/bitops.h>
180 +#include <asm/bootinfo.h>
181 +#include <asm/io.h>
182 +#include <asm/mipsregs.h>
183 +#include <asm/system.h>
184 +#include <asm/idt-boards/rc32434/rc32434.h>
185 +#include <asm/idt-boards/rc32434/rc32434_gpio.h>
186 +
187 +#include <asm/irq.h>
188 +
189 +#undef DEBUG_IRQ
190 +#ifdef DEBUG_IRQ
191 +/* note: prints function name for you */
192 +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
193 +#else
194 +#define DPRINTK(fmt, args...)
195 +#endif
196 +
197 +extern asmlinkage void idtIRQ(void);
198 +static unsigned int startup_irq(unsigned int irq);
199 +static void end_irq(unsigned int irq_nr);
200 +static void mask_and_ack_irq(unsigned int irq_nr);
201 +static void aruba_enable_irq(unsigned int irq_nr);
202 +static void aruba_disable_irq(unsigned int irq_nr);
203 +
204 +extern void __init init_generic_irq(void);
205 +
206 +typedef struct {
207 + u32 mask;
208 + volatile u32 *base_addr;
209 +} intr_group_t;
210 +
211 +static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
212 + {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
213 +};
214 +
215 +#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
216 +#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003010 + 4)))
217 +#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)((0xbc003010) + 4))) = (val))
218 +
219 +static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
220 + {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
221 + {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
222 + {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
223 + {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
224 + {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
225 +};
226 +
227 +#define READ_PEND_MUSCAT(base) (*(base))
228 +#define READ_MASK_MUSCAT(base) (*(base + 2))
229 +#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
230 +
231 +static inline int irq_to_group(unsigned int irq_nr)
232 +{
233 + switch (mips_machtype) {
234 + case MACH_ARUBA_AP70:
235 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
236 + case MACH_ARUBA_AP65:
237 + case MACH_ARUBA_AP60:
238 + default:
239 + return 0;
240 + }
241 +}
242 +
243 +static inline int group_to_ip(unsigned int group)
244 +{
245 + switch (mips_machtype) {
246 + case MACH_ARUBA_AP70:
247 + return group + 2;
248 + case MACH_ARUBA_AP65:
249 + case MACH_ARUBA_AP60:
250 + default:
251 + return 6;
252 + }
253 +}
254 +
255 +static inline void enable_local_irq(unsigned int ip)
256 +{
257 + int ipnum = 0x100 << ip;
258 + clear_c0_cause(ipnum);
259 + set_c0_status(ipnum);
260 +}
261 +
262 +static inline void disable_local_irq(unsigned int ip)
263 +{
264 + int ipnum = 0x100 << ip;
265 + clear_c0_status(ipnum);
266 +}
267 +
268 +static inline void ack_local_irq(unsigned int ip)
269 +{
270 + int ipnum = 0x100 << ip;
271 + clear_c0_cause(ipnum);
272 +}
273 +
274 +static void aruba_enable_irq(unsigned int irq_nr)
275 +{
276 + int ip = irq_nr - GROUP0_IRQ_BASE;
277 + unsigned int group, intr_bit;
278 + volatile unsigned int *addr;
279 + if (ip < 0) {
280 + enable_local_irq(irq_nr);
281 + } else {
282 + // calculate group
283 + switch (mips_machtype) {
284 + case MACH_ARUBA_AP70:
285 + group = ip >> 5;
286 + break;
287 + case MACH_ARUBA_AP65:
288 + case MACH_ARUBA_AP60:
289 + default:
290 + group = 0;
291 + break;
292 + }
293 +
294 + // calc interrupt bit within group
295 + ip -= (group << 5);
296 + intr_bit = 1 << ip;
297 +
298 + // first enable the IP mapped to this IRQ
299 + enable_local_irq(group_to_ip(group));
300 +
301 + switch (mips_machtype) {
302 + case MACH_ARUBA_AP70:
303 + addr = intr_group_muscat[group].base_addr;
304 + // unmask intr within group
305 + WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
306 + break;
307 + case MACH_ARUBA_AP65:
308 + case MACH_ARUBA_AP60:
309 + default:
310 + addr = intr_group_merlot[group].base_addr;
311 + WRITE_MASK_MERLOT(addr, (READ_MASK_MERLOT(addr) | intr_bit));
312 + break;
313 + }
314 + }
315 +}
316 +
317 +static void aruba_disable_irq(unsigned int irq_nr)
318 +{
319 + int ip = irq_nr - GROUP0_IRQ_BASE;
320 + unsigned int group, intr_bit, mask;
321 + volatile unsigned int *addr;
322 +
323 + // calculate group
324 + switch (mips_machtype) {
325 + case MACH_ARUBA_AP70:
326 + group = ip >> 5;
327 + break;
328 + case MACH_ARUBA_AP65:
329 + case MACH_ARUBA_AP60:
330 + default:
331 + group = 0;
332 + break;
333 + }
334 +
335 + // calc interrupt bit within group
336 + ip -= group << 5;
337 + intr_bit = 1 << ip;
338 +
339 + switch (mips_machtype) {
340 + case MACH_ARUBA_AP70:
341 + addr = intr_group_muscat[group].base_addr;
342 + // mask intr within group
343 + mask = READ_MASK_MUSCAT(addr);
344 + mask |= intr_bit;
345 + WRITE_MASK_MUSCAT(addr, mask);
346 +
347 + /*
348 + if there are no more interrupts enabled in this
349 + group, disable corresponding IP
350 + */
351 + if (mask == intr_group_muscat[group].mask)
352 + disable_local_irq(group_to_ip(group));
353 + break;
354 + case MACH_ARUBA_AP65:
355 + case MACH_ARUBA_AP60:
356 + default:
357 + addr = intr_group_merlot[group].base_addr;
358 + addr = intr_group_merlot[group].base_addr;
359 + // mask intr within group
360 + WRITE_MASK_MERLOT(addr, (READ_MASK_MERLOT(addr) & ~intr_bit));
361 + if (READ_MASK_MERLOT(addr))
362 + disable_local_irq(group_to_ip(group));
363 + break;
364 + }
365 +}
366 +
367 +static unsigned int startup_irq(unsigned int irq_nr)
368 +{
369 + aruba_enable_irq(irq_nr);
370 + return 0;
371 +}
372 +
373 +static void shutdown_irq(unsigned int irq_nr)
374 +{
375 + aruba_disable_irq(irq_nr);
376 + return;
377 +}
378 +
379 +static void mask_and_ack_irq(unsigned int irq_nr)
380 +{
381 + aruba_disable_irq(irq_nr);
382 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
383 +}
384 +
385 +static void end_irq(unsigned int irq_nr)
386 +{
387 +
388 + int ip = irq_nr - GROUP0_IRQ_BASE;
389 + unsigned int intr_bit, group;
390 + volatile unsigned int *addr;
391 +
392 + if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
393 + printk("warning: end_irq %d did not enable (%x)\n",
394 + irq_nr, irq_desc[irq_nr].status);
395 + }
396 +
397 + switch (mips_machtype) {
398 + case MACH_ARUBA_AP70:
399 + if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
400 + else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
401 + else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
402 + else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
403 +
404 + group = ip >> 5;
405 +
406 + // calc interrupt bit within group
407 + ip -= (group << 5);
408 + intr_bit = 1 << ip;
409 +
410 + // first enable the IP mapped to this IRQ
411 + enable_local_irq(group_to_ip(group));
412 +
413 + addr = intr_group_muscat[group].base_addr;
414 + // unmask intr within group
415 + WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
416 + break;
417 + case MACH_ARUBA_AP65:
418 + case MACH_ARUBA_AP60:
419 + group = 0;
420 + // calc interrupt bit within group
421 + intr_bit = 1 << ip;
422 + // first enable the IP mapped to this IRQ
423 + enable_local_irq(group_to_ip(group));
424 + addr = intr_group_merlot[group].base_addr;
425 + // unmask intr within group
426 + WRITE_MASK_MERLOT(addr, (READ_MASK_MERLOT(addr) | intr_bit));
427 + break;
428 + }
429 +}
430 +
431 +static struct hw_interrupt_type aruba_irq_type = {
432 + .typename = "IDT434",
433 + .startup = startup_irq,
434 + .shutdown = shutdown_irq,
435 + .enable = aruba_enable_irq,
436 + .disable = aruba_disable_irq,
437 + .ack = mask_and_ack_irq,
438 + .end = end_irq,
439 +};
440 +
441 +void __init arch_init_irq(void)
442 +{
443 + int i;
444 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
445 + memset(irq_desc, 0, sizeof(irq_desc));
446 + set_except_vector(0, idtIRQ);
447 +
448 + for (i = 0; i < RC32434_NR_IRQS; i++) {
449 + irq_desc[i].status = IRQ_DISABLED;
450 + irq_desc[i].action = NULL;
451 + irq_desc[i].depth = 1;
452 + irq_desc[i].handler = &aruba_irq_type;
453 + spin_lock_init(&irq_desc[i].lock);
454 + }
455 +
456 + switch (mips_machtype) {
457 + case MACH_ARUBA_AP70:
458 + break;
459 + case MACH_ARUBA_AP65:
460 + case MACH_ARUBA_AP60:
461 + default:
462 + WRITE_MASK_MERLOT(intr_group_merlot[0].base_addr, 0);
463 + *((volatile unsigned long *)0xbc003014) = 0x10;
464 + break;
465 + }
466 +}
467 +
468 +/* Main Interrupt dispatcher */
469 +void aruba_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
470 +{
471 + unsigned int pend, group, ip;
472 + volatile unsigned int *addr;
473 + switch (mips_machtype) {
474 + case MACH_ARUBA_AP70:
475 + if ((ip = (cp0_cause & 0x7c00))) {
476 + group = 21 - rc32434_clz(ip);
477 +
478 + addr = intr_group_muscat[group].base_addr;
479 +
480 + pend = READ_PEND_MUSCAT(addr);
481 + pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
482 + pend = 39 - rc32434_clz(pend);
483 + do_IRQ((group << 5) + pend, regs);
484 + }
485 + break;
486 + case MACH_ARUBA_AP65:
487 + case MACH_ARUBA_AP60:
488 + default:
489 + #define MERLOT_WLAN1_IRQ 2 // bit 10 in CP0_status register
490 + #define MERLOT_ENET_IRQ 3 // bit 11 in CP0_status register
491 + #define MERLOT_WLAN_IRQ 5 // bit 13 in CP0_status register
492 + #define MERLOT_MISC_IRQ 6 // bit 14 in CP0_status register = GROUP 0
493 +
494 + if (cp0_cause & (1 << (8 + MERLOT_MISC_IRQ))) {
495 + // Misc Interrupt
496 + group = 0;
497 + addr = intr_group_merlot[group].base_addr;
498 + pend = READ_PEND_MERLOT(addr);
499 + pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
500 + /* handle one misc interrupt at a time */
501 + while (pend) {
502 + unsigned int intr_bit, irq_nr;
503 + intr_bit = pend ^ (pend - 1);
504 + irq_nr = ((31 - rc32434_clz(pend)) + GROUP0_IRQ_BASE);
505 + do_IRQ(irq_nr, regs);
506 + do_IRQ(irq_nr, regs);
507 + pend &= ~intr_bit;
508 + }
509 + }
510 +
511 + if (cp0_cause & (1 << (8 + MERLOT_WLAN_IRQ))) {
512 + do_IRQ(MERLOT_WLAN_IRQ, regs);
513 + }
514 +
515 + if (cp0_cause & (1 << (8 + MERLOT_ENET_IRQ))) {
516 + do_IRQ(MERLOT_ENET_IRQ, regs);
517 + }
518 + break;
519 + }
520 +}
521 diff -Nur linux-2.6.15/arch/mips/aruba/Makefile linux-2.6.15-openwrt/arch/mips/aruba/Makefile
522 --- linux-2.6.15/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
523 +++ linux-2.6.15-openwrt/arch/mips/aruba/Makefile 2006-01-10 00:32:32.000000000 +0100
524 @@ -0,0 +1,49 @@
525 +###############################################################################
526 +#
527 +# BRIEF MODULE DESCRIPTION
528 +# Makefile for IDT EB434 BSP
529 +#
530 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
531 +#
532 +# This program is free software; you can redistribute it and/or modify it
533 +# under the terms of the GNU General Public License as published by the
534 +# Free Software Foundation; either version 2 of the License, or (at your
535 +# option) any later version.
536 +#
537 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
538 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
539 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
540 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
541 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
542 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
543 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
544 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
545 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
546 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
547 +#
548 +# You should have received a copy of the GNU General Public License along
549 +# with this program; if not, write to the Free Software Foundation, Inc.,
550 +# 675 Mass Ave, Cambridge, MA 02139, USA.
551 +#
552 +#
553 +###############################################################################
554 +# May 2004 rkt, neb
555 +#
556 +# Initial Release
557 +#
558 +#
559 +#
560 +###############################################################################
561 +
562 +
563 +# .S.s:
564 +# $(CPP) $(CFLAGS) $< -o $*.s
565 +# .S.o:
566 +# $(CC) $(CFLAGS) -c $< -o $*.o
567 +
568 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o wdt_merlot.o
569 +obj-$(CONFIG_SERIAL_8250) += serial.o
570 +
571 +subdir-y += nvram
572 +obj-y += nvram/built-in.o
573 +
574 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/Makefile linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile
575 --- linux-2.6.15/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
576 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/Makefile 2006-01-10 00:32:32.000000000 +0100
577 @@ -0,0 +1,46 @@
578 +###############################################################################
579 +#
580 +# BRIEF MODULE DESCRIPTION
581 +# Makefile for IDT EB434 nvram access routines
582 +#
583 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
584 +#
585 +# This program is free software; you can redistribute it and/or modify it
586 +# under the terms of the GNU General Public License as published by the
587 +# Free Software Foundation; either version 2 of the License, or (at your
588 +# option) any later version.
589 +#
590 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
591 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
592 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
593 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
594 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
595 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
596 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
597 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
598 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
599 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
600 +#
601 +# You should have received a copy of the GNU General Public License along
602 +# with this program; if not, write to the Free Software Foundation, Inc.,
603 +# 675 Mass Ave, Cambridge, MA 02139, USA.
604 +#
605 +#
606 +###############################################################################
607 +# May 2004 rkt, neb
608 +#
609 +# Initial Release
610 +#
611 +#
612 +#
613 +###############################################################################
614 +
615 +obj-y := nvram434.o
616 +obj-m := $(O_TARGET)
617 +
618 +
619 +
620 +
621 +
622 +
623 +
624 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.c linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c
625 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
626 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.c 2006-01-10 00:32:32.000000000 +0100
627 @@ -0,0 +1,392 @@
628 +/**************************************************************************
629 + *
630 + * BRIEF MODULE DESCRIPTION
631 + * nvram interface routines.
632 + *
633 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
634 + *
635 + * This program is free software; you can redistribute it and/or modify it
636 + * under the terms of the GNU General Public License as published by the
637 + * Free Software Foundation; either version 2 of the License, or (at your
638 + * option) any later version.
639 + *
640 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
641 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
642 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
643 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
644 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
645 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
646 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
647 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
648 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
649 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
650 + *
651 + * You should have received a copy of the GNU General Public License along
652 + * with this program; if not, write to the Free Software Foundation, Inc.,
653 + * 675 Mass Ave, Cambridge, MA 02139, USA.
654 + *
655 + *
656 + **************************************************************************
657 + * May 2004 rkt, neb
658 + *
659 + * Initial Release
660 + *
661 + *
662 + *
663 + **************************************************************************
664 + */
665 +
666 +#include <linux/ctype.h>
667 +#include <linux/string.h>
668 +
669 +//#include <asm/ds1553rtc.h>
670 +#include "nvram434.h"
671 +#define NVRAM_BASE 0xbfff8000
672 +
673 +extern void setenv (char *e, char *v, int rewrite);
674 +extern void unsetenv (char *e);
675 +extern void mapenv (int (*func)(char *, char *));
676 +extern char *getenv (char *s);
677 +extern void purgeenv(void);
678 +
679 +static void nvram_initenv(void);
680 +
681 +static unsigned char
682 +nvram_getbyte(int offs)
683 +{
684 + return(*((unsigned char*)(NVRAM_BASE + offs)));
685 +}
686 +
687 +static void
688 +nvram_setbyte(int offs, unsigned char val)
689 +{
690 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
691 +
692 + *nvramDataPointer = val;
693 +}
694 +
695 +/*
696 + * BigEndian!
697 + */
698 +static unsigned short
699 +nvram_getshort(int offs)
700 +{
701 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
702 +}
703 +
704 +static void
705 +nvram_setshort(int offs, unsigned short val)
706 +{
707 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
708 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
709 +}
710 +#if 0
711 +static unsigned int
712 +nvram_getint(int offs)
713 +{
714 + unsigned int val;
715 + val = nvram_getbyte(offs) << 24;
716 + val |= nvram_getbyte(offs + 1) << 16;
717 + val |= nvram_getbyte(offs + 2) << 8;
718 + val |= nvram_getbyte(offs + 3);
719 + return(val);
720 +}
721 +
722 +static void
723 +nvram_setint(int offs, unsigned int val)
724 +{
725 + nvram_setbyte(offs, val >> 24);
726 + nvram_setbyte(offs + 1, val >> 16);
727 + nvram_setbyte(offs + 2, val >> 8);
728 + nvram_setbyte(offs + 3, val);
729 +}
730 +#endif
731 +/*
732 + * calculate NVRAM checksum
733 + */
734 +static unsigned short
735 +nvram_calcsum(void)
736 +{
737 + unsigned short sum = NV_MAGIC;
738 + int i;
739 +
740 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
741 + sum += nvram_getshort(i);
742 + return(sum);
743 +}
744 +
745 +/*
746 + * update the nvram checksum
747 + */
748 +static void
749 +nvram_updatesum (void)
750 +{
751 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
752 +}
753 +
754 +/*
755 + * test validity of nvram by checksumming it
756 + */
757 +static int
758 +nvram_isvalid(void)
759 +{
760 + static int is_valid;
761 +
762 + if (is_valid)
763 + return(1);
764 +
765 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
766 + printk("nvram_isvalid FAILED\n");
767 + //nvram_initenv();
768 + }
769 + is_valid = 1;
770 + return(1);
771 +}
772 +
773 +/* return nvram address of environment string */
774 +static int
775 +nvram_matchenv(char *s)
776 +{
777 + int envsize, envp, n, i, varsize;
778 + char *var;
779 +
780 + envsize = nvram_getshort(NVOFF_ENVSIZE);
781 +
782 + if (envsize > ENV_AVAIL)
783 + return(0); /* sanity */
784 +
785 + envp = ENV_BASE;
786 +
787 + if ((n = strlen (s)) > 255)
788 + return(0);
789 +
790 + while (envsize > 0) {
791 + varsize = nvram_getbyte(envp);
792 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
793 + return(0); /* sanity */
794 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
795 + char c1 = nvram_getbyte(i);
796 + char c2 = *var;
797 + if (islower(c1))
798 + c1 = toupper(c1);
799 + if (islower(c2))
800 + c2 = toupper(c2);
801 + if (c1 != c2)
802 + break;
803 + }
804 + if (i > envp + n) { /* match so far */
805 + if (n == varsize - 1) /* match on boolean */
806 + return(envp);
807 + if (nvram_getbyte(i) == '=') /* exact match on variable */
808 + return(envp);
809 + }
810 + envsize -= varsize;
811 + envp += varsize;
812 + }
813 + return(0);
814 +}
815 +
816 +static void nvram_initenv(void)
817 +{
818 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
819 + nvram_setshort(NVOFF_ENVSIZE, 0);
820 +
821 + nvram_updatesum();
822 +}
823 +
824 +static void
825 +nvram_delenv(char *s)
826 +{
827 + int nenvp, envp, envsize, nbytes;
828 +
829 + envp = nvram_matchenv(s);
830 + if (envp == 0)
831 + return;
832 +
833 + nenvp = envp + nvram_getbyte(envp);
834 + envsize = nvram_getshort(NVOFF_ENVSIZE);
835 + nbytes = envsize - (nenvp - ENV_BASE);
836 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
837 + while (nbytes--) {
838 + nvram_setbyte(envp, nvram_getbyte(nenvp));
839 + envp++;
840 + nenvp++;
841 + }
842 + nvram_updatesum();
843 +}
844 +
845 +static int
846 +nvram_setenv(char *s, char *v)
847 +{
848 + int ns, nv, total;
849 + int envp;
850 +
851 + if (!nvram_isvalid())
852 + return(-1);
853 +
854 + nvram_delenv(s);
855 + ns = strlen(s);
856 + if (ns == 0)
857 + return (-1);
858 + if (v && *v) {
859 + nv = strlen(v);
860 + total = ns + nv + 2;
861 + }
862 + else {
863 + nv = 0;
864 + total = ns + 1;
865 + }
866 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
867 + return(-1);
868 +
869 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
870 +
871 + nvram_setbyte(envp, (unsigned char) total);
872 + envp++;
873 +
874 + while (ns--) {
875 + nvram_setbyte(envp, *s);
876 + envp++;
877 + s++;
878 + }
879 +
880 + if (nv) {
881 + nvram_setbyte(envp, '=');
882 + envp++;
883 + while (nv--) {
884 + nvram_setbyte(envp, *v);
885 + envp++;
886 + v++;
887 + }
888 + }
889 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
890 + nvram_updatesum();
891 + return 0;
892 +}
893 +
894 +static char *
895 +nvram_getenv(char *s)
896 +{
897 + static char buf[256]; /* FIXME: this cannot be static */
898 + int envp, ns, nbytes, i;
899 +
900 + if (!nvram_isvalid())
901 + return "INVALID NVRAM"; //((char *)0);
902 +
903 + envp = nvram_matchenv(s);
904 + if (envp == 0)
905 + return "NOT FOUND"; //((char *)0);
906 + ns = strlen(s);
907 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
908 + buf[0] = '\0';
909 + else {
910 + nbytes = nvram_getbyte(envp) - (ns + 2);
911 + envp += ns + 2;
912 + for (i = 0; i < nbytes; i++)
913 + buf[i] = nvram_getbyte(envp++);
914 + buf[i] = '\0';
915 + }
916 + return(buf);
917 +}
918 +
919 +static void
920 +nvram_unsetenv(char *s)
921 +{
922 + if (!nvram_isvalid())
923 + return;
924 +
925 + nvram_delenv(s);
926 +}
927 +
928 +/*
929 + * apply func to each string in environment
930 + */
931 +static void
932 +nvram_mapenv(int (*func)(char *, char *))
933 +{
934 + int envsize, envp, n, i, seeneql;
935 + char name[256], value[256];
936 + char c, *s;
937 +
938 + if (!nvram_isvalid())
939 + return;
940 +
941 + envsize = nvram_getshort(NVOFF_ENVSIZE);
942 + envp = ENV_BASE;
943 +
944 + while (envsize > 0) {
945 + value[0] = '\0';
946 + seeneql = 0;
947 + s = name;
948 + n = nvram_getbyte(envp);
949 + for (i = envp + 1; i < envp + n; i++) {
950 + c = nvram_getbyte(i);
951 + if ((c == '=') && !seeneql) {
952 + *s = '\0';
953 + s = value;
954 + seeneql = 1;
955 + continue;
956 + }
957 + *s++ = c;
958 + }
959 + *s = '\0';
960 + (*func)(name, value);
961 + envsize -= n;
962 + envp += n;
963 + }
964 +}
965 +#if 0
966 +static unsigned int
967 +digit(char c)
968 +{
969 + if ('0' <= c && c <= '9')
970 + return (c - '0');
971 + if ('A' <= c && c <= 'Z')
972 + return (10 + c - 'A');
973 + if ('a' <= c && c <= 'z')
974 + return (10 + c - 'a');
975 + return (~0);
976 +}
977 +#endif
978 +/*
979 + * Wrappers to allow 'special' environment variables to get processed
980 + */
981 +void
982 +setenv(char *e, char *v, int rewrite)
983 +{
984 + if (nvram_getenv(e) && !rewrite)
985 + return;
986 +
987 + nvram_setenv(e, v);
988 +}
989 +
990 +char *
991 +getenv(char *e)
992 +{
993 + return(nvram_getenv(e));
994 +}
995 +
996 +void
997 +unsetenv(char *e)
998 +{
999 + nvram_unsetenv(e);
1000 +}
1001 +
1002 +void
1003 +purgeenv()
1004 +{
1005 + int i;
1006 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
1007 +
1008 + for (i = ENV_BASE; i < ENV_TOP; i++)
1009 + *nvramDataPointer++ = 0;
1010 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
1011 + nvram_setshort(NVOFF_ENVSIZE, 0);
1012 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
1013 +}
1014 +
1015 +void
1016 +mapenv(int (*func)(char *, char *))
1017 +{
1018 + nvram_mapenv(func);
1019 +}
1020 diff -Nur linux-2.6.15/arch/mips/aruba/nvram/nvram434.h linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h
1021 --- linux-2.6.15/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
1022 +++ linux-2.6.15-openwrt/arch/mips/aruba/nvram/nvram434.h 2006-01-10 00:32:32.000000000 +0100
1023 @@ -0,0 +1,66 @@
1024 +/**************************************************************************
1025 + *
1026 + * BRIEF MODULE DESCRIPTION
1027 + * nvram definitions.
1028 + *
1029 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1030 + *
1031 + * This program is free software; you can redistribute it and/or modify it
1032 + * under the terms of the GNU General Public License as published by the
1033 + * Free Software Foundation; either version 2 of the License, or (at your
1034 + * option) any later version.
1035 + *
1036 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1037 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1038 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1039 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1040 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1041 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1042 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1043 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1044 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1045 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1046 + *
1047 + * You should have received a copy of the GNU General Public License along
1048 + * with this program; if not, write to the Free Software Foundation, Inc.,
1049 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1050 + *
1051 + *
1052 + **************************************************************************
1053 + * May 2004 rkt, neb
1054 + *
1055 + * Initial Release
1056 + *
1057 + *
1058 + *
1059 + **************************************************************************
1060 + */
1061 +
1062 +
1063 +#ifndef _NVRAM_
1064 +#define _NVRAM_
1065 +#define NVOFFSET 0 /* use all of NVRAM */
1066 +
1067 +/* Offsets to reserved locations */
1068 + /* size description */
1069 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
1070 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
1071 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
1072 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
1073 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
1074 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
1075 +
1076 +#define NV_MAGIC 0xdeaf /* nvram magic number */
1077 +#define NV_RESERVED 6 /* number of reserved bytes */
1078 +
1079 +#undef NVOFF_ETHADDR
1080 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
1081 +
1082 +/* number of bytes available for environment */
1083 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
1084 +#define ENV_TOP 0x2000
1085 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
1086 +
1087 +#endif /* _NVRAM_ */
1088 +
1089 +
1090 diff -Nur linux-2.6.15/arch/mips/aruba/prom.c linux-2.6.15-openwrt/arch/mips/aruba/prom.c
1091 --- linux-2.6.15/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
1092 +++ linux-2.6.15-openwrt/arch/mips/aruba/prom.c 2006-01-10 00:32:32.000000000 +0100
1093 @@ -0,0 +1,111 @@
1094 +/**************************************************************************
1095 + *
1096 + * BRIEF MODULE DESCRIPTION
1097 + * prom interface routines
1098 + *
1099 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1100 + *
1101 + * This program is free software; you can redistribute it and/or modify it
1102 + * under the terms of the GNU General Public License as published by the
1103 + * Free Software Foundation; either version 2 of the License, or (at your
1104 + * option) any later version.
1105 + *
1106 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1107 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1108 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1109 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1110 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1111 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1112 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1113 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1114 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1115 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1116 + *
1117 + * You should have received a copy of the GNU General Public License along
1118 + * with this program; if not, write to the Free Software Foundation, Inc.,
1119 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1120 + *
1121 + *
1122 + **************************************************************************
1123 + * May 2004 rkt, neb
1124 + *
1125 + * Initial Release
1126 + *
1127 + *
1128 + *
1129 + **************************************************************************
1130 + */
1131 +
1132 +#include <linux/config.h>
1133 +#include <linux/init.h>
1134 +#include <linux/mm.h>
1135 +#include <linux/module.h>
1136 +#include <linux/string.h>
1137 +#include <linux/console.h>
1138 +#include <asm/bootinfo.h>
1139 +#include <linux/bootmem.h>
1140 +#include <linux/ioport.h>
1141 +#include <linux/serial.h>
1142 +#include <linux/serialP.h>
1143 +#include <asm/serial.h>
1144 +#include <linux/ioport.h>
1145 +
1146 +unsigned int idt_cpu_freq;
1147 +EXPORT_SYMBOL(idt_cpu_freq);
1148 +
1149 +unsigned int arch_has_pci=0;
1150 +
1151 +/* Kernel Boot parameters */
1152 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
1153 +
1154 +extern unsigned long mips_machgroup;
1155 +extern unsigned long mips_machtype;
1156 +
1157 +extern void setup_serial_port(void);
1158 +extern char * getenv(char *e);
1159 +
1160 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
1161 +#define RAM_SIZE 32*1024*1024
1162 +
1163 +char *__init prom_getcmdline(void)
1164 +{
1165 + return &(arcs_cmdline[0]);
1166 +}
1167 +
1168 +void __init prom_init(void)
1169 +{
1170 + char *boardname;
1171 + sprintf(arcs_cmdline, "%s", bootparm);
1172 +
1173 + /* set our arch type */
1174 + mips_machgroup = MACH_GROUP_ARUBA;
1175 + mips_machtype = MACH_ARUBA_UNKNOWN;
1176 +
1177 + boardname=getenv("boardname");
1178 +
1179 + if (!strcmp(boardname,"Muscat")) {
1180 + mips_machtype = MACH_ARUBA_AP70;
1181 + idt_cpu_freq = 133000000;
1182 + arch_has_pci=1;
1183 + } else if (!strcmp(boardname,"Mataro")) {
1184 + mips_machtype = MACH_ARUBA_AP65;
1185 + idt_cpu_freq = 110000000;
1186 + } else if (!strcmp(boardname,"Merlot")) {
1187 + mips_machtype = MACH_ARUBA_AP60;
1188 + idt_cpu_freq = 90000000;
1189 + }
1190 +
1191 + /* turn on the console */
1192 + setup_serial_port();
1193 +
1194 + /*
1195 + * give all RAM to boot allocator,
1196 + * except where the kernel was loaded
1197 + */
1198 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
1199 +}
1200 +
1201 +void prom_free_prom_memory(void)
1202 +{
1203 + printk("stubbed prom_free_prom_memory()\n");
1204 +}
1205 diff -Nur linux-2.6.15/arch/mips/aruba/serial.c linux-2.6.15-openwrt/arch/mips/aruba/serial.c
1206 --- linux-2.6.15/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
1207 +++ linux-2.6.15-openwrt/arch/mips/aruba/serial.c 2006-01-10 00:32:32.000000000 +0100
1208 @@ -0,0 +1,94 @@
1209 +/**************************************************************************
1210 + *
1211 + * BRIEF MODULE DESCRIPTION
1212 + * Serial port initialisation.
1213 + *
1214 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1215 + *
1216 + * This program is free software; you can redistribute it and/or modify it
1217 + * under the terms of the GNU General Public License as published by the
1218 + * Free Software Foundation; either version 2 of the License, or (at your
1219 + * option) any later version.
1220 + *
1221 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1222 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1223 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1224 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1225 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1226 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1227 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1228 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1229 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1230 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1231 + *
1232 + * You should have received a copy of the GNU General Public License along
1233 + * with this program; if not, write to the Free Software Foundation, Inc.,
1234 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1235 + *
1236 + *
1237 + **************************************************************************
1238 + * May 2004 rkt, neb
1239 + *
1240 + * Initial Release
1241 + *
1242 + *
1243 + *
1244 + **************************************************************************
1245 + */
1246 +
1247 +
1248 +#include <linux/config.h>
1249 +#include <linux/init.h>
1250 +#include <linux/sched.h>
1251 +#include <linux/pci.h>
1252 +#include <linux/interrupt.h>
1253 +#include <linux/tty.h>
1254 +#include <linux/serial.h>
1255 +#include <linux/serial_core.h>
1256 +
1257 +#include <asm/time.h>
1258 +#include <asm/cpu.h>
1259 +#include <asm/bootinfo.h>
1260 +#include <asm/irq.h>
1261 +#include <asm/serial.h>
1262 +
1263 +#include <asm/idt-boards/rc32434/rc32434.h>
1264 +
1265 +extern int __init early_serial_setup(struct uart_port *port);
1266 +
1267 +#define BASE_BAUD (1843200 / 16)
1268 +
1269 +extern unsigned int idt_cpu_freq;
1270 +
1271 +extern int __init setup_serial_port(void)
1272 +{
1273 + static struct uart_port serial_req[2];
1274 +
1275 + memset(serial_req, 0, sizeof(serial_req));
1276 + serial_req[0].type = PORT_16550A;
1277 + serial_req[0].line = 0;
1278 + serial_req[0].flags = STD_COM_FLAGS;
1279 + serial_req[0].iotype = SERIAL_IO_MEM;
1280 + serial_req[0].regshift = 2;
1281 +
1282 + switch (mips_machtype) {
1283 + case MACH_ARUBA_AP70:
1284 + serial_req[0].irq = 104;
1285 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
1286 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
1287 + serial_req[0].uartclk = idt_cpu_freq;
1288 + break;
1289 + case MACH_ARUBA_AP65:
1290 + case MACH_ARUBA_AP60:
1291 + default:
1292 + serial_req[0].irq = 12;
1293 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
1294 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
1295 + serial_req[0].uartclk = idt_cpu_freq / 2;
1296 + break;
1297 + }
1298 +
1299 + early_serial_setup(&serial_req[0]);
1300 +
1301 + return(0);
1302 +}
1303 diff -Nur linux-2.6.15/arch/mips/aruba/setup.c linux-2.6.15-openwrt/arch/mips/aruba/setup.c
1304 --- linux-2.6.15/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
1305 +++ linux-2.6.15-openwrt/arch/mips/aruba/setup.c 2006-01-10 00:32:32.000000000 +0100
1306 @@ -0,0 +1,124 @@
1307 +/**************************************************************************
1308 + *
1309 + * BRIEF MODULE DESCRIPTION
1310 + * setup routines for IDT EB434 boards
1311 + *
1312 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1313 + *
1314 + * This program is free software; you can redistribute it and/or modify it
1315 + * under the terms of the GNU General Public License as published by the
1316 + * Free Software Foundation; either version 2 of the License, or (at your
1317 + * option) any later version.
1318 + *
1319 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1320 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1321 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1322 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1323 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1324 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1325 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1326 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1327 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1328 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1329 + *
1330 + * You should have received a copy of the GNU General Public License along
1331 + * with this program; if not, write to the Free Software Foundation, Inc.,
1332 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1333 + *
1334 + *
1335 + **************************************************************************
1336 + * May 2004 rkt, neb
1337 + *
1338 + * Initial Release
1339 + *
1340 + *
1341 + *
1342 + **************************************************************************
1343 + */
1344 +
1345 +#include <linux/init.h>
1346 +#include <linux/mm.h>
1347 +#include <linux/sched.h>
1348 +#include <linux/irq.h>
1349 +#include <asm/bootinfo.h>
1350 +#include <asm/io.h>
1351 +#include <linux/ioport.h>
1352 +#include <asm/mipsregs.h>
1353 +#include <asm/pgtable.h>
1354 +#include <asm/reboot.h>
1355 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1356 +#include <asm/idt-boards/rc32434/rc32434.h>
1357 +
1358 +extern char *__init prom_getcmdline(void);
1359 +
1360 +extern void (*board_time_init) (void);
1361 +extern void (*board_timer_setup) (struct irqaction * irq);
1362 +extern void aruba_time_init(void);
1363 +extern void aruba_timer_setup(struct irqaction *irq);
1364 +extern void aruba_reset(void);
1365 +
1366 +#define epldMask ((volatile unsigned char *)0xB900000d)
1367 +
1368 +static void aruba_machine_restart(char *command)
1369 +{
1370 + switch (mips_machtype) {
1371 + case MACH_ARUBA_AP70:
1372 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
1373 + break;
1374 + case MACH_ARUBA_AP65:
1375 + case MACH_ARUBA_AP60:
1376 + default:
1377 + /* Reset*/
1378 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
1379 + udelay(100);
1380 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
1381 + udelay(100);
1382 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
1383 + break;
1384 + }
1385 +}
1386 +
1387 +static void aruba_machine_halt(void)
1388 +{
1389 + for (;;) continue;
1390 +}
1391 +
1392 +extern char * getenv(char *e);
1393 +extern void unlock_ap60_70_flash(void);
1394 +extern void wdt_merlot_disable(void);
1395 +
1396 +void __init plat_setup(void)
1397 +{
1398 + board_time_init = aruba_time_init;
1399 +
1400 + board_timer_setup = aruba_timer_setup;
1401 +
1402 + _machine_restart = aruba_machine_restart;
1403 + _machine_halt = aruba_machine_halt;
1404 + _machine_power_off = aruba_machine_halt;
1405 +
1406 + set_io_port_base(KSEG1);
1407 +
1408 + /* Enable PCI interrupts in EPLD Mask register */
1409 + *epldMask = 0x0;
1410 + *(epldMask + 1) = 0x0;
1411 +
1412 + write_c0_wired(0);
1413 + unlock_ap60_70_flash();
1414 +
1415 + printk("BOARD - %s\n",getenv("boardname"));
1416 +
1417 + wdt_merlot_disable();
1418 +
1419 + return 0;
1420 +}
1421 +
1422 +int page_is_ram(unsigned long pagenr)
1423 +{
1424 + return 1;
1425 +}
1426 +
1427 +const char *get_system_type(void)
1428 +{
1429 + return "MIPS IDT32434 - ARUBA";
1430 +}
1431 diff -Nur linux-2.6.15/arch/mips/aruba/time.c linux-2.6.15-openwrt/arch/mips/aruba/time.c
1432 --- linux-2.6.15/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
1433 +++ linux-2.6.15-openwrt/arch/mips/aruba/time.c 2006-01-10 00:32:32.000000000 +0100
1434 @@ -0,0 +1,108 @@
1435 +/**************************************************************************
1436 + *
1437 + * BRIEF MODULE DESCRIPTION
1438 + * timer routines for IDT EB434 boards
1439 + *
1440 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1441 + *
1442 + * This program is free software; you can redistribute it and/or modify it
1443 + * under the terms of the GNU General Public License as published by the
1444 + * Free Software Foundation; either version 2 of the License, or (at your
1445 + * option) any later version.
1446 + *
1447 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1448 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1449 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1450 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1451 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1452 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1453 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1454 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1455 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1456 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1457 + *
1458 + * You should have received a copy of the GNU General Public License along
1459 + * with this program; if not, write to the Free Software Foundation, Inc.,
1460 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1461 + *
1462 + *
1463 + **************************************************************************
1464 + * May 2004 rkt, neb
1465 + *
1466 + * Initial Release
1467 + *
1468 + *
1469 + *
1470 + **************************************************************************
1471 + */
1472 +
1473 +#include <linux/config.h>
1474 +#include <linux/init.h>
1475 +#include <linux/kernel_stat.h>
1476 +#include <linux/sched.h>
1477 +#include <linux/spinlock.h>
1478 +#include <linux/mc146818rtc.h>
1479 +#include <linux/irq.h>
1480 +#include <linux/timex.h>
1481 +
1482 +#include <linux/param.h>
1483 +#include <asm/mipsregs.h>
1484 +#include <asm/ptrace.h>
1485 +#include <asm/time.h>
1486 +#include <asm/hardirq.h>
1487 +
1488 +#include <asm/mipsregs.h>
1489 +#include <asm/ptrace.h>
1490 +#include <asm/debug.h>
1491 +#include <asm/time.h>
1492 +
1493 +#include <asm/idt-boards/rc32434/rc32434.h>
1494 +
1495 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1496 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1497 +
1498 +extern unsigned int idt_cpu_freq;
1499 +
1500 +static unsigned long __init cal_r4koff(void)
1501 +{
1502 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1503 + return (mips_hpt_frequency / HZ);
1504 +}
1505 +
1506 +void __init aruba_time_init(void)
1507 +{
1508 + unsigned int est_freq, flags;
1509 + local_irq_save(flags);
1510 +
1511 + printk("calculating r4koff... ");
1512 + r4k_offset = cal_r4koff();
1513 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1514 +
1515 + est_freq = 2 * r4k_offset * HZ;
1516 + est_freq += 5000; /* round */
1517 + est_freq -= est_freq % 10000;
1518 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1519 + (est_freq % 1000000) * 100 / 1000000);
1520 + local_irq_restore(flags);
1521 +
1522 +}
1523 +
1524 +void __init aruba_timer_setup(struct irqaction *irq)
1525 +{
1526 + /* we are using the cpu counter for timer interrupts */
1527 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1528 +
1529 + /* to generate the first timer interrupt */
1530 + r4k_cur = (read_c0_count() + r4k_offset);
1531 + write_c0_compare(r4k_cur);
1532 +
1533 +}
1534 +
1535 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1536 +{
1537 + irq_enter();
1538 + kstat_this_cpu.irqs[irq]++;
1539 +
1540 + timer_interrupt(irq, NULL, regs);
1541 + irq_exit();
1542 +}
1543 diff -Nur linux-2.6.15/arch/mips/aruba/wdt_merlot.c linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c
1544 --- linux-2.6.15/arch/mips/aruba/wdt_merlot.c 1970-01-01 01:00:00.000000000 +0100
1545 +++ linux-2.6.15-openwrt/arch/mips/aruba/wdt_merlot.c 2006-01-10 00:32:32.000000000 +0100
1546 @@ -0,0 +1,30 @@
1547 +#include <linux/config.h>
1548 +#include <linux/kernel.h>
1549 +#include <asm/bootinfo.h>
1550 +
1551 +void wdt_merlot_disable()
1552 +{
1553 + volatile __u32 *wdt_errcs;
1554 + volatile __u32 *wdt_wtc;
1555 + volatile __u32 *wdt_ctl;
1556 + volatile __u32 val;
1557 +
1558 + switch (mips_machtype) {
1559 + case MACH_ARUBA_AP70:
1560 + wdt_errcs = (__u32 *) 0xb8030030;
1561 + wdt_wtc = (__u32 *) 0xb803003c;
1562 + val = *wdt_errcs;
1563 + val &= ~0x201;
1564 + *wdt_errcs = val;
1565 + val = *wdt_wtc;
1566 + val &= ~0x1;
1567 + *wdt_wtc = val;
1568 + break;
1569 + case MACH_ARUBA_AP65:
1570 + case MACH_ARUBA_AP60:
1571 + default:
1572 + wdt_ctl = (__u32 *) 0xbc003008;
1573 + *wdt_ctl = 0;
1574 + break;
1575 + }
1576 +}
1577 diff -Nur linux-2.6.15/arch/mips/Kconfig linux-2.6.15-openwrt/arch/mips/Kconfig
1578 --- linux-2.6.15/arch/mips/Kconfig 2006-01-03 04:21:10.000000000 +0100
1579 +++ linux-2.6.15-openwrt/arch/mips/Kconfig 2006-01-10 00:32:32.000000000 +0100
1580 @@ -227,6 +227,18 @@
1581 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1582 a kernel for this platform.
1583
1584 +config MACH_ARUBA
1585 + bool "Support for the ARUBA product line"
1586 + select DMA_NONCOHERENT
1587 + select IRQ_CPU
1588 + select CPU_HAS_PREFETCH
1589 + select HW_HAS_PCI
1590 + select SWAP_IO_SPACE
1591 + select SYS_SUPPORTS_32BIT_KERNEL
1592 + select SYS_HAS_CPU_MIPS32_R1
1593 + select SYS_SUPPORTS_BIG_ENDIAN
1594 +
1595 +
1596 config MACH_JAZZ
1597 bool "Support for the Jazz family of machines"
1598 select ARC
1599 diff -Nur linux-2.6.15/arch/mips/Makefile linux-2.6.15-openwrt/arch/mips/Makefile
1600 --- linux-2.6.15/arch/mips/Makefile 2006-01-03 04:21:10.000000000 +0100
1601 +++ linux-2.6.15-openwrt/arch/mips/Makefile 2006-01-10 00:32:32.000000000 +0100
1602 @@ -258,6 +258,14 @@
1603 #
1604
1605 #
1606 +# Aruba
1607 +#
1608 +
1609 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1610 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1611 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1612 +
1613 +#
1614 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1615 #
1616 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1617 diff -Nur linux-2.6.15/arch/mips/mm/tlbex.c linux-2.6.15-openwrt/arch/mips/mm/tlbex.c
1618 --- linux-2.6.15/arch/mips/mm/tlbex.c 2006-01-03 04:21:10.000000000 +0100
1619 +++ linux-2.6.15-openwrt/arch/mips/mm/tlbex.c 2006-01-10 00:32:32.000000000 +0100
1620 @@ -852,7 +852,6 @@
1621
1622 case CPU_R10000:
1623 case CPU_R12000:
1624 - case CPU_4KC:
1625 case CPU_SB1:
1626 case CPU_SB1A:
1627 case CPU_4KSC:
1628 @@ -880,6 +879,7 @@
1629 tlbw(p);
1630 break;
1631
1632 + case CPU_4KC:
1633 case CPU_4KEC:
1634 case CPU_24K:
1635 case CPU_34K:
1636 diff -Nur linux-2.6.15/arch/mips/pci/fixup-aruba.c linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c
1637 --- linux-2.6.15/arch/mips/pci/fixup-aruba.c 1970-01-01 01:00:00.000000000 +0100
1638 +++ linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c 2006-01-10 00:34:41.000000000 +0100
1639 @@ -0,0 +1,115 @@
1640 +/**************************************************************************
1641 + *
1642 + * BRIEF MODULE DESCRIPTION
1643 + * PCI fixups for IDT EB434 board
1644 + *
1645 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1646 + *
1647 + * This program is free software; you can redistribute it and/or modify it
1648 + * under the terms of the GNU General Public License as published by the
1649 + * Free Software Foundation; either version 2 of the License, or (at your
1650 + * option) any later version.
1651 + *
1652 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1653 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1654 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1655 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1656 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1657 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1658 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1659 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1660 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1661 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1662 + *
1663 + * You should have received a copy of the GNU General Public License along
1664 + * with this program; if not, write to the Free Software Foundation, Inc.,
1665 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1666 + *
1667 + *
1668 + **************************************************************************
1669 + * May 2004 rkt, neb
1670 + *
1671 + * Initial Release
1672 + *
1673 + *
1674 + *
1675 + **************************************************************************
1676 + */
1677 +
1678 +#include <linux/config.h>
1679 +#include <linux/types.h>
1680 +#include <linux/pci.h>
1681 +#include <linux/kernel.h>
1682 +#include <linux/init.h>
1683 +#include <asm/idt-boards/rc32434/rc32434.h>
1684 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
1685 +
1686 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
1687 +{
1688 +
1689 + if (dev->bus->number != 0) {
1690 + return 0;
1691 + }
1692 +
1693 + slot = PCI_SLOT(dev->devfn);
1694 + dev->irq = 0;
1695 +
1696 + if (slot > 0 && slot <= 15) {
1697 +#if 1
1698 + if(slot == 10) {
1699 + if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 9; // intA
1700 + } else if(slot == 11) {
1701 + if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 10; // intA
1702 + if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 10; // intA
1703 + if(pin == 3) dev->irq = GROUP4_IRQ_BASE + 10; // intA
1704 + } else if(slot == 12) {
1705 + if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 11; // intA
1706 + if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 12; // intB
1707 + } else if (slot == 13) {
1708 + if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 12; // intA
1709 + if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 11; // intB
1710 + } else {
1711 + dev->irq = GROUP4_IRQ_BASE + 11;
1712 + }
1713 +#else
1714 + switch (pin) {
1715 + case 1: /* INTA*/
1716 + dev->irq = GROUP4_IRQ_BASE + 11;
1717 + break;
1718 + case 2: /* INTB */
1719 + dev->irq = GROUP4_IRQ_BASE + 11;
1720 + break;
1721 + case 3: /* INTC */
1722 + dev->irq = GROUP4_IRQ_BASE + 11;
1723 + break;
1724 + case 4: /* INTD */
1725 + dev->irq = GROUP4_IRQ_BASE + 11;
1726 + break;
1727 + default:
1728 + dev->irq = 0xff;
1729 + break;
1730 + }
1731 +#endif
1732 +#ifdef DEBUG
1733 + printk("irq fixup: slot %d, pin %d, irq %d\n",
1734 + slot, pin, dev->irq);
1735 +#endif
1736 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
1737 + }
1738 + return (dev->irq);
1739 +}
1740 +
1741 +struct pci_fixup pcibios_fixups[] = {
1742 + {0}
1743 +};
1744 +
1745 +
1746 +
1747 +
1748 +
1749 +
1750 +
1751 +
1752 +
1753 +
1754 +
1755 diff -Nur linux-2.6.15/arch/mips/pci/Makefile linux-2.6.15-openwrt/arch/mips/pci/Makefile
1756 --- linux-2.6.15/arch/mips/pci/Makefile 2006-01-03 04:21:10.000000000 +0100
1757 +++ linux-2.6.15-openwrt/arch/mips/pci/Makefile 2006-01-10 00:32:32.000000000 +0100
1758 @@ -56,3 +56,4 @@
1759 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
1760 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
1761 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
1762 +obj-$(CONFIG_MACH_ARUBA) += fixup-aruba.o ops-aruba.o pci-aruba.o
1763 diff -Nur linux-2.6.15/arch/mips/pci/ops-aruba.c linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c
1764 --- linux-2.6.15/arch/mips/pci/ops-aruba.c 1970-01-01 01:00:00.000000000 +0100
1765 +++ linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c 2006-01-10 00:32:32.000000000 +0100
1766 @@ -0,0 +1,204 @@
1767 +/**************************************************************************
1768 + *
1769 + * BRIEF MODULE DESCRIPTION
1770 + * pci_ops for IDT EB434 board
1771 + *
1772 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1773 + *
1774 + * This program is free software; you can redistribute it and/or modify it
1775 + * under the terms of the GNU General Public License as published by the
1776 + * Free Software Foundation; either version 2 of the License, or (at your
1777 + * option) any later version.
1778 + *
1779 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1780 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1781 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1782 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1783 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1784 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1785 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1786 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1787 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1788 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1789 + *
1790 + * You should have received a copy of the GNU General Public License along
1791 + * with this program; if not, write to the Free Software Foundation, Inc.,
1792 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1793 + *
1794 + *
1795 + **************************************************************************
1796 + * May 2004 rkt, neb
1797 + *
1798 + * Initial Release
1799 + *
1800 + *
1801 + *
1802 + **************************************************************************
1803 + */
1804 +
1805 +#include <linux/config.h>
1806 +#include <linux/init.h>
1807 +#include <linux/pci.h>
1808 +#include <linux/types.h>
1809 +#include <linux/delay.h>
1810 +
1811 +#include <asm/cpu.h>
1812 +#include <asm/io.h>
1813 +
1814 +#include <asm/idt-boards/rc32434/rc32434.h>
1815 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
1816 +
1817 +#define PCI_ACCESS_READ 0
1818 +#define PCI_ACCESS_WRITE 1
1819 +
1820 +
1821 +#define PCI_CFG_SET(slot,func,off) \
1822 + (rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
1823 + ((func)<<8) | (off)))
1824 +
1825 +static int config_access(unsigned char access_type, struct pci_bus *bus,
1826 + unsigned int devfn, unsigned char where,
1827 + u32 * data)
1828 +{
1829 + /*
1830 + * config cycles are on 4 byte boundary only
1831 + */
1832 + unsigned int slot = PCI_SLOT(devfn);
1833 + u8 func = PCI_FUNC(devfn);
1834 +
1835 + if (slot < 2 || slot > 15) {
1836 + *data = 0xFFFFFFFF;
1837 + return -1;
1838 + }
1839 + /* Setup address */
1840 + PCI_CFG_SET(slot, func, where);
1841 + rc32434_sync();
1842 +
1843 + if (access_type == PCI_ACCESS_WRITE) {
1844 + rc32434_sync();
1845 + rc32434_pci->pcicfgd = *data;
1846 + } else {
1847 + rc32434_sync();
1848 + *data = rc32434_pci->pcicfgd;
1849 + }
1850 +
1851 + rc32434_sync();
1852 +
1853 + return 0;
1854 +}
1855 +
1856 +
1857 +/*
1858 + * We can't address 8 and 16 bit words directly. Instead we have to
1859 + * read/write a 32bit word and mask/modify the data we actually want.
1860 + */
1861 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
1862 + int where, u8 * val)
1863 +{
1864 + u32 data;
1865 + int ret;
1866 +
1867 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
1868 + *val = (data >> ((where & 3) << 3)) & 0xff;
1869 + return ret;
1870 +}
1871 +
1872 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
1873 + int where, u16 * val)
1874 +{
1875 + u32 data;
1876 + int ret;
1877 +
1878 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
1879 + *val = (data >> ((where & 3) << 3)) & 0xffff;
1880 + return ret;
1881 +}
1882 +
1883 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
1884 + int where, u32 * val)
1885 +{
1886 + int ret;
1887 +
1888 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
1889 + return ret;
1890 +}
1891 +
1892 +static int
1893 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
1894 + u8 val)
1895 +{
1896 + u32 data = 0;
1897 +
1898 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
1899 + return -1;
1900 +
1901 + data = (data & ~(0xff << ((where & 3) << 3))) |
1902 + (val << ((where & 3) << 3));
1903 +
1904 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
1905 + return -1;
1906 +
1907 + return PCIBIOS_SUCCESSFUL;
1908 +}
1909 +
1910 +
1911 +static int
1912 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
1913 + u16 val)
1914 +{
1915 + u32 data = 0;
1916 +
1917 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
1918 + return -1;
1919 +
1920 + data = (data & ~(0xffff << ((where & 3) << 3))) |
1921 + (val << ((where & 3) << 3));
1922 +
1923 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
1924 + return -1;
1925 +
1926 +
1927 + return PCIBIOS_SUCCESSFUL;
1928 +}
1929 +
1930 +
1931 +static int
1932 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
1933 + u32 val)
1934 +{
1935 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
1936 + return -1;
1937 +
1938 + return PCIBIOS_SUCCESSFUL;
1939 +}
1940 +
1941 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
1942 + int where, int size, u32 * val)
1943 +{
1944 + switch (size) {
1945 + case 1:
1946 + return read_config_byte(bus, devfn, where, (u8 *) val);
1947 + case 2:
1948 + return read_config_word(bus, devfn, where, (u16 *) val);
1949 + default:
1950 + return read_config_dword(bus, devfn, where, val);
1951 + }
1952 +}
1953 +
1954 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
1955 + int where, int size, u32 val)
1956 +{
1957 + switch (size) {
1958 + case 1:
1959 + return write_config_byte(bus, devfn, where, (u8) val);
1960 + case 2:
1961 + return write_config_word(bus, devfn, where, (u16) val);
1962 + default:
1963 + return write_config_dword(bus, devfn, where, val);
1964 + }
1965 +}
1966 +
1967 +struct pci_ops rc32434_pci_ops = {
1968 + .read = pci_config_read,
1969 + .write = pci_config_write,
1970 +};
1971 diff -Nur linux-2.6.15/arch/mips/pci/pci-aruba.c linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c
1972 --- linux-2.6.15/arch/mips/pci/pci-aruba.c 1970-01-01 01:00:00.000000000 +0100
1973 +++ linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c 2006-01-10 00:32:32.000000000 +0100
1974 @@ -0,0 +1,235 @@
1975 +/**************************************************************************
1976 + *
1977 + * BRIEF MODULE DESCRIPTION
1978 + * PCI initialization for IDT EB434 board
1979 + *
1980 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1981 + *
1982 + * This program is free software; you can redistribute it and/or modify it
1983 + * under the terms of the GNU General Public License as published by the
1984 + * Free Software Foundation; either version 2 of the License, or (at your
1985 + * option) any later version.
1986 + *
1987 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1988 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1989 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1990 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1991 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1992 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1993 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1994 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1995 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1996 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1997 + *
1998 + * You should have received a copy of the GNU General Public License along
1999 + * with this program; if not, write to the Free Software Foundation, Inc.,
2000 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2001 + *
2002 + *
2003 + **************************************************************************
2004 + * May 2004 rkt, neb
2005 + *
2006 + * Initial Release
2007 + *
2008 + *
2009 + *
2010 + **************************************************************************
2011 + */
2012 +
2013 +#include <linux/config.h>
2014 +#include <linux/types.h>
2015 +#include <linux/pci.h>
2016 +#include <linux/kernel.h>
2017 +#include <linux/init.h>
2018 +#include <asm/idt-boards/rc32434/rc32434.h>
2019 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
2020 +
2021 +#define PCI_ACCESS_READ 0
2022 +#define PCI_ACCESS_WRITE 1
2023 +
2024 +#undef DEBUG
2025 +#ifdef DEBUG
2026 +#define DBG(x...) printk(x)
2027 +#else
2028 +#define DBG(x...)
2029 +#endif
2030 +/* define an unsigned array for the PCI registers */
2031 +unsigned int korinaCnfgRegs[25] = {
2032 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
2033 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
2034 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
2035 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
2036 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
2037 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
2038 +};
2039 +
2040 +static struct resource rc32434_res_pci_mem2;
2041 +
2042 +static struct resource rc32434_res_pci_mem1 = {
2043 + .name = "PCI MEM1",
2044 + .start = 0x50000000,
2045 + .end = 0x5FFFFFFF,
2046 + .flags = IORESOURCE_MEM,
2047 + .child = &rc32434_res_pci_mem2,
2048 +};
2049 +static struct resource rc32434_res_pci_mem2 = {
2050 + .name = "PCI MEM2",
2051 + .start = 0x60000000,
2052 + .end = 0x6FFFFFFF,
2053 + .flags = IORESOURCE_MEM,
2054 + .parent = &rc32434_res_pci_mem1,
2055 +};
2056 +static struct resource rc32434_res_pci_io1 = {
2057 + .name = "PCI I/O1",
2058 + .start = 0x18800000,
2059 + .end = 0x188FFFFF,
2060 + .flags = IORESOURCE_IO,
2061 +};
2062 +
2063 +extern struct pci_ops rc32434_pci_ops;
2064 +
2065 +struct pci_controller rc32434_controller = {
2066 + .pci_ops = &rc32434_pci_ops,
2067 + .mem_resource = &rc32434_res_pci_mem1,
2068 + .io_resource = &rc32434_res_pci_io1,
2069 + .mem_offset = 0x00000000UL,
2070 + .io_offset = 0x00000000UL,
2071 +};
2072 +
2073 +extern unsigned int arch_has_pci;
2074 +
2075 +static int __init rc32434_pcibridge_init(void)
2076 +{
2077 +
2078 + unsigned int pciConfigAddr = 0;/*used for writing pci config values */
2079 + int loopCount=0 ;/*used for the loop */
2080 +
2081 + unsigned int pcicValue, pcicData=0;
2082 + unsigned int dummyRead, pciCntlVal = 0;
2083 +
2084 + if (!arch_has_pci) return 0;
2085 +
2086 + printk("PCI: Initializing PCI\n");
2087 +
2088 + /* Disable the IP bus error for PCI scaning */
2089 + pciCntlVal=rc32434_pci->pcic;
2090 + pciCntlVal &= 0xFFFFFF7;
2091 + rc32434_pci->pcic = pciCntlVal;
2092 +
2093 + ioport_resource.start = rc32434_res_pci_io1.start;
2094 + ioport_resource.end = rc32434_res_pci_io1.end;
2095 +/*
2096 + iomem_resource.start = rc32434_res_pci_mem1.start;
2097 + iomem_resource.end = rc32434_res_pci_mem1.end;
2098 +*/
2099 +
2100 + pcicValue = rc32434_pci->pcic;
2101 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
2102 + if (!((pcicValue == PCIM_H_EA) ||
2103 + (pcicValue == PCIM_H_IA_FIX) ||
2104 + (pcicValue == PCIM_H_IA_RR))) {
2105 + /* Not in Host Mode, return ERROR */
2106 + return -1;
2107 + }
2108 +
2109 + /* Enables the Idle Grant mode, Arbiter Parking */
2110 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
2111 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
2112 + /* Zero out the PCI status & PCI Status Mask */
2113 + for(;;) {
2114 + pcicData = rc32434_pci->pcis;
2115 + if (!(pcicData & PCIS_rip_m))
2116 + break;
2117 + }
2118 +
2119 + rc32434_pci->pcis = 0;
2120 + rc32434_pci->pcism = 0xFFFFFFFF;
2121 + /* Zero out the PCI decoupled registers */
2122 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
2123 + rc32434_pci->pcidas=0; /* clear the status */
2124 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
2125 + /* Mask PCI Messaging Interrupts */
2126 + rc32434_pci_msg->pciiic = 0;
2127 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
2128 + rc32434_pci_msg->pciioic = 0;
2129 + rc32434_pci_msg->pciioim = 0;
2130 +
2131 + /* Setup PCILB0 as Memory Window */
2132 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
2133 +
2134 + /* setup the PCI map address as same as the local address */
2135 +
2136 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
2137 +
2138 + /* Setup PCILBA1 as MEM */
2139 +#ifdef __MIPSEB__
2140 + rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
2141 +#else
2142 + rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
2143 +#endif
2144 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
2145 +
2146 + rc32434_pci->pcilba[1].a = 0x60000000;
2147 +
2148 + rc32434_pci->pcilba[1].m = 0x60000000;
2149 + /* setup PCILBA2 as IO Window*/
2150 +#ifdef __MIPSEB__
2151 + rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
2152 +#else
2153 + rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
2154 +#endif
2155 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
2156 + rc32434_pci->pcilba[2].a = 0x18C00000;
2157 +
2158 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
2159 + /* setup PCILBA2 as IO Window*/
2160 +#ifdef __MIPSEB__
2161 + rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
2162 +#else
2163 + rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
2164 +#endif
2165 +
2166 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
2167 +
2168 +
2169 + rc32434_pci->pcilba[3].a = 0x18800000;
2170 +
2171 + rc32434_pci->pcilba[3].m = 0x18800000;
2172 + /* Setup PCILBA3 as IO Window */
2173 +
2174 +#ifdef __MIPSEB__
2175 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCILBAC_sb_m);
2176 +#else
2177 + rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
2178 +#endif
2179 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
2180 +
2181 + pciConfigAddr = (unsigned int)(0x80000004);
2182 + for(loopCount = 0; loopCount < 24; loopCount++){
2183 + rc32434_pci->pcicfga = pciConfigAddr;
2184 + dummyRead = rc32434_pci->pcicfga;
2185 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
2186 + dummyRead=rc32434_pci->pcicfgd;
2187 + pciConfigAddr += 4;
2188 + }
2189 + rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
2190 + ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
2191 +
2192 + pciCntlVal = rc32434_pci->pcic;
2193 + pciCntlVal &= ~(PCIC_tnr_m);
2194 + rc32434_pci->pcic = pciCntlVal;
2195 + pciCntlVal = rc32434_pci->pcic;
2196 +
2197 + register_pci_controller(&rc32434_controller);
2198 +
2199 + rc32434_sync();
2200 + return 0;
2201 +}
2202 +
2203 +arch_initcall(rc32434_pcibridge_init);
2204 +
2205 +/* Do platform specific device initialization at pci_enable_device() time */
2206 +int pcibios_plat_dev_init(struct pci_dev *dev)
2207 +{
2208 + return 0;
2209 +}
2210 diff -Nur linux-2.6.15/drivers/mtd/chips/cfi_probe.c linux-2.6.15-openwrt/drivers/mtd/chips/cfi_probe.c
2211 --- linux-2.6.15/drivers/mtd/chips/cfi_probe.c 2006-01-03 04:21:10.000000000 +0100
2212 +++ linux-2.6.15-openwrt/drivers/mtd/chips/cfi_probe.c 2006-01-10 00:32:32.000000000 +0100
2213 @@ -26,6 +26,74 @@
2214 static void print_cfi_ident(struct cfi_ident *);
2215 #endif
2216
2217 +#if 1
2218 +
2219 +#define AMD_AUTOSEL_OFF1 0xAAA
2220 +#define AMD_AUTOSEL_OFF2 0x555
2221 +#define AMD_MANUF_ID 0x1
2222 +#define AMD_DEVICE_ID1 0xF6 /* T */
2223 +#define AMD_DEVICE_ID2 0xF9 /* B */
2224 +/* Foll. are definitions for Macronix Flash Part */
2225 +#define MCX_MANUF_ID 0xC2
2226 +#define MCX_DEVICE_ID1 0xA7
2227 +#define MCX_DEVICE_ID2 0xA8
2228 +/* Foll. common to both AMD and Macronix */
2229 +#define FACTORY_LOCKED 0x99
2230 +#define USER_LOCKED 0x19
2231 +
2232 +/* NOTE: AP-70/6x use BYTE mode flash access. Therefore the
2233 + * lowest Addr. pin in the flash is not A0 but A-1 (A minus 1).
2234 + * CPU's A0 is tied to Flash's A-1, A1 to A0 and so on. This
2235 + * gives 4MB of byte-addressable mem. In byte mode, all addr
2236 + * need to be multiplied by 2 (i.e compared to word mode).
2237 + * NOTE: AMD_AUTOSEL_OFF1 and OFF2 are already mult. by 2
2238 + * Just blindly use the addr offsets suggested in the manual
2239 + * for byte mode and you'll be OK. Offs. in Table 6 need to
2240 + * be mult by 2 (for getting autosel params)
2241 + */
2242 +void
2243 +flash_detect(struct map_info *map, __u32 base, struct cfi_private *cfi)
2244 +{
2245 + map_word val[3];
2246 + int osf = cfi->interleave * cfi->device_type; // =2 for AP70/6x
2247 + char *manuf, *part, *lock ;
2248 +
2249 + if (osf != 1) return ;
2250 +
2251 + cfi_send_gen_cmd(0xAA, AMD_AUTOSEL_OFF1, base, map, cfi, cfi->device_type, NULL);
2252 + cfi_send_gen_cmd(0x55, AMD_AUTOSEL_OFF2, base, map, cfi, cfi->device_type, NULL);
2253 + cfi_send_gen_cmd(0x90, AMD_AUTOSEL_OFF1, base, map, cfi, cfi->device_type, NULL);
2254 + val[0] = map_read(map, base) ; // manuf ID
2255 + val[1] = map_read(map, base+2) ; // device ID
2256 + val[2] = map_read(map, base+6) ; // lock indicator
2257 +#if 0
2258 +printk("v1=0x%x v2=0x%x v3=0x%x\n", val[0], val[1], val[2]) ;
2259 +#endif
2260 + if (val[0].x[0] == AMD_MANUF_ID) {
2261 + manuf = "AMD Flash" ;
2262 + if (val[1].x[0] == AMD_DEVICE_ID1)
2263 + part = "AM29LV320D (Top)" ;
2264 + else if (val[1].x[0] == AMD_DEVICE_ID2)
2265 + part = "AM29LV320D (Bot)" ;
2266 + else part = "Unknown" ;
2267 + } else if (val[0].x[0] == MCX_MANUF_ID) {
2268 + manuf = "Macronix Flash" ;
2269 + if (val[1].x[0] == MCX_DEVICE_ID1)
2270 + part = "MX29LV320A (Top)" ;
2271 + else if (val[1].x[0] == MCX_DEVICE_ID2)
2272 + part = "MX29LV320A (Bot)" ;
2273 + else part = "Unknown" ;
2274 + } else
2275 + return ;
2276 + if (val[2].x[0] == FACTORY_LOCKED)
2277 + lock = "Factory Locked" ;
2278 + else if (val[2].x[0] == USER_LOCKED)
2279 + lock = "User Locked" ;
2280 + else lock = "Unknown locking" ;
2281 + printk("%s %s (%s)\n", manuf, part, lock) ;
2282 +}
2283 +#endif
2284 +
2285 static int cfi_probe_chip(struct map_info *map, __u32 base,
2286 unsigned long *chip_map, struct cfi_private *cfi);
2287 static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
2288 @@ -118,6 +186,10 @@
2289 }
2290
2291 xip_disable();
2292 +#if 1
2293 + //cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
2294 + flash_detect(map, base, cfi) ;
2295 +#endif
2296 cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
2297 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
2298 cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL);
2299 diff -Nur linux-2.6.15/drivers/mtd/maps/physmap.c linux-2.6.15-openwrt/drivers/mtd/maps/physmap.c
2300 --- linux-2.6.15/drivers/mtd/maps/physmap.c 2006-01-03 04:21:10.000000000 +0100
2301 +++ linux-2.6.15-openwrt/drivers/mtd/maps/physmap.c 2006-01-10 00:32:32.000000000 +0100
2302 @@ -34,15 +34,31 @@
2303 static struct mtd_partition *mtd_parts;
2304 static int mtd_parts_nb;
2305
2306 -static int num_physmap_partitions;
2307 -static struct mtd_partition *physmap_partitions;
2308 +static int num_physmap_partitions = 3;
2309 +static struct mtd_partition physmap_partitions[] = {
2310 + {
2311 + name: "zImage",
2312 + size: 0x3f0000-0x80000,
2313 + offset: 0x80000,
2314 + },
2315 + {
2316 + name: "JFFS2",
2317 + size: 0x3f0000-0x120000,
2318 + offset: 0x120000,
2319 + },
2320 + {
2321 + name: "NVRAM",
2322 + size: 0x2000,
2323 + offset: 0x3f8000,
2324 + }
2325 +};
2326
2327 static const char *part_probes[] __initdata = {"cmdlinepart", "RedBoot", NULL};
2328
2329 void physmap_set_partitions(struct mtd_partition *parts, int num_parts)
2330 {
2331 - physmap_partitions=parts;
2332 - num_physmap_partitions=num_parts;
2333 +// physmap_partitions=parts;
2334 +// num_physmap_partitions=num_parts;
2335 }
2336 #endif /* CONFIG_MTD_PARTITIONS */
2337
2338 diff -Nur linux-2.6.15/drivers/net/Kconfig linux-2.6.15-openwrt/drivers/net/Kconfig
2339 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 04:21:10.000000000 +0100
2340 +++ linux-2.6.15-openwrt/drivers/net/Kconfig 2006-01-10 00:32:32.000000000 +0100
2341 @@ -176,6 +176,13 @@
2342
2343 source "drivers/net/arm/Kconfig"
2344
2345 +config IDT_RC32434_ETH
2346 + tristate "IDT RC32434 Local Ethernet support"
2347 + depends on NET_ETHERNET
2348 + help
2349 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
2350 + To compile this driver as a module, choose M here.
2351 +
2352 config MACE
2353 tristate "MACE (Power Mac ethernet) support"
2354 depends on NET_ETHERNET && PPC_PMAC && PPC32
2355 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
2356 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 04:21:10.000000000 +0100
2357 +++ linux-2.6.15-openwrt/drivers/net/Makefile 2006-01-10 00:32:33.000000000 +0100
2358 @@ -190,6 +190,7 @@
2359 obj-$(CONFIG_SMC91X) += smc91x.o
2360 obj-$(CONFIG_DM9000) += dm9000.o
2361 obj-$(CONFIG_FEC_8XX) += fec_8xx/
2362 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
2363
2364 obj-$(CONFIG_ARM) += arm/
2365 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
2366 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.c linux-2.6.15-openwrt/drivers/net/rc32434_eth.c
2367 --- linux-2.6.15/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
2368 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.c 2006-01-10 00:32:33.000000000 +0100
2369 @@ -0,0 +1,1268 @@
2370 +/**************************************************************************
2371 + *
2372 + * BRIEF MODULE DESCRIPTION
2373 + * Driver for the IDT RC32434 on-chip ethernet controller.
2374 + *
2375 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2376 + *
2377 + * This program is free software; you can redistribute it and/or modify it
2378 + * under the terms of the GNU General Public License as published by the
2379 + * Free Software Foundation; either version 2 of the License, or (at your
2380 + * option) any later version.
2381 + *
2382 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2383 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2384 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2385 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2386 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2387 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2388 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2389 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2390 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2391 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2392 + *
2393 + * You should have received a copy of the GNU General Public License along
2394 + * with this program; if not, write to the Free Software Foundation, Inc.,
2395 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2396 + *
2397 + *
2398 + **************************************************************************
2399 + * May 2004 rkt, neb
2400 + *
2401 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
2402 + *
2403 + * Aug 2004 Sadik
2404 + *
2405 + * Added NAPI
2406 + *
2407 + **************************************************************************
2408 + */
2409 +
2410 +#include <linux/config.h>
2411 +#include <linux/module.h>
2412 +#include <linux/kernel.h>
2413 +#include <linux/moduleparam.h>
2414 +#include <linux/sched.h>
2415 +#include <linux/ctype.h>
2416 +#include <linux/types.h>
2417 +#include <linux/fcntl.h>
2418 +#include <linux/interrupt.h>
2419 +#include <linux/ptrace.h>
2420 +#include <linux/init.h>
2421 +#include <linux/ioport.h>
2422 +#include <linux/proc_fs.h>
2423 +#include <linux/in.h>
2424 +#include <linux/slab.h>
2425 +#include <linux/string.h>
2426 +#include <linux/delay.h>
2427 +#include <linux/netdevice.h>
2428 +#include <linux/etherdevice.h>
2429 +#include <linux/skbuff.h>
2430 +#include <linux/errno.h>
2431 +#include <asm/bootinfo.h>
2432 +#include <asm/system.h>
2433 +#include <asm/bitops.h>
2434 +#include <asm/pgtable.h>
2435 +#include <asm/segment.h>
2436 +#include <asm/io.h>
2437 +#include <asm/dma.h>
2438 +
2439 +#include "rc32434_eth.h"
2440 +
2441 +#define DRIVER_VERSION "(mar2904)"
2442 +
2443 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
2444 +
2445 +
2446 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
2447 + ((dev)->dev_addr[1]))
2448 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
2449 + ((dev)->dev_addr[3] << 16) | \
2450 + ((dev)->dev_addr[4] << 8) | \
2451 + ((dev)->dev_addr[5]))
2452 +
2453 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
2454 +static char mac0[18] = "08:00:06:05:40:01";
2455 +
2456 +MODULE_PARM(mac0, "c18");
2457 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
2458 +
2459 +static struct rc32434_if_t {
2460 + char *name;
2461 + struct net_device *dev;
2462 + char* mac_str;
2463 + int weight;
2464 + u32 iobase;
2465 + u32 rxdmabase;
2466 + u32 txdmabase;
2467 + int rx_dma_irq;
2468 + int tx_dma_irq;
2469 + int rx_ovr_irq;
2470 + int tx_und_irq;
2471 +} rc32434_iflist[] =
2472 +{
2473 + {
2474 + "rc32434_eth0", NULL, mac0,
2475 + 64,
2476 + ETH0_PhysicalAddress,
2477 + ETH0_RX_DMA_ADDR,
2478 + ETH0_TX_DMA_ADDR,
2479 + ETH0_DMA_RX_IRQ,
2480 + ETH0_DMA_TX_IRQ,
2481 + ETH0_RX_OVR_IRQ,
2482 + ETH0_TX_UND_IRQ
2483 + }
2484 +};
2485 +
2486 +
2487 +static int parse_mac_addr(struct net_device *dev, char* macstr)
2488 +{
2489 + int i, j;
2490 + unsigned char result, value;
2491 +
2492 + for (i=0; i<6; i++) {
2493 + result = 0;
2494 + if (i != 5 && *(macstr+2) != ':') {
2495 + ERR("invalid mac address format: %d %c\n",
2496 + i, *(macstr+2));
2497 + return -EINVAL;
2498 + }
2499 + for (j=0; j<2; j++) {
2500 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
2501 + toupper(*macstr)-'A'+10) < 16) {
2502 + result = result*16 + value;
2503 + macstr++;
2504 + }
2505 + else {
2506 + ERR("invalid mac address "
2507 + "character: %c\n", *macstr);
2508 + return -EINVAL;
2509 + }
2510 + }
2511 +
2512 + macstr++;
2513 + dev->dev_addr[i] = result;
2514 + }
2515 +
2516 + return 0;
2517 +}
2518 +
2519 +
2520 +
2521 +static inline void rc32434_abort_tx(struct net_device *dev)
2522 +{
2523 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2524 + rc32434_abort_dma(dev, lp->tx_dma_regs);
2525 +
2526 +}
2527 +
2528 +static inline void rc32434_abort_rx(struct net_device *dev)
2529 +{
2530 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2531 + rc32434_abort_dma(dev, lp->rx_dma_regs);
2532 +
2533 +}
2534 +
2535 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
2536 +{
2537 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
2538 +}
2539 +
2540 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
2541 +{
2542 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
2543 +}
2544 +
2545 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
2546 +{
2547 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
2548 +}
2549 +
2550 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
2551 +{
2552 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
2553 +}
2554 +
2555 +#ifdef RC32434_PROC_DEBUG
2556 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
2557 + int length, int *eof, void *data)
2558 +{
2559 + struct net_device *dev = (struct net_device *)data;
2560 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2561 + int len = 0;
2562 +
2563 + /* print out header */
2564 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
2565 + len += sprintf (buf + len,
2566 + "DMA halt count = %10d, DMA run count = %10d\n",
2567 + lp->dma_halt_cnt, lp->dma_run_cnt);
2568 +
2569 + if (fpos >= len) {
2570 + *start = buf;
2571 + *eof = 1;
2572 + return 0;
2573 + }
2574 + *start = buf + fpos;
2575 +
2576 + if ((len -= fpos) > length)
2577 + return length;
2578 + *eof = 1;
2579 +
2580 + return len;
2581 +
2582 +}
2583 +#endif
2584 +
2585 +
2586 +/*
2587 + * Restart the RC32434 ethernet controller.
2588 + */
2589 +static int rc32434_restart(struct net_device *dev)
2590 +{
2591 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2592 +
2593 + /*
2594 + * Disable interrupts
2595 + */
2596 + disable_irq(lp->rx_irq);
2597 + disable_irq(lp->tx_irq);
2598 +#ifdef RC32434_REVISION
2599 + disable_irq(lp->ovr_irq);
2600 +#endif
2601 + disable_irq(lp->und_irq);
2602 +
2603 + /* Mask F E bit in Tx DMA */
2604 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
2605 + /* Mask D H E bit in Rx DMA */
2606 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
2607 +
2608 + rc32434_init(dev);
2609 + rc32434_multicast_list(dev);
2610 +
2611 + enable_irq(lp->und_irq);
2612 +#ifdef RC32434_REVISION
2613 + enable_irq(lp->ovr_irq);
2614 +#endif
2615 + enable_irq(lp->tx_irq);
2616 + enable_irq(lp->rx_irq);
2617 +
2618 + return 0;
2619 +}
2620 +
2621 +int rc32434_init_module(void)
2622 +{
2623 +#ifdef CONFIG_MACH_ARUBA
2624 + if (mips_machtype != MACH_ARUBA_AP70)
2625 + return 1;
2626 +#endif
2627 +
2628 + printk(KERN_INFO DRIVER_NAME " \n");
2629 + return rc32434_probe(0);
2630 +}
2631 +
2632 +static int rc32434_probe(int port_num)
2633 +{
2634 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
2635 + struct rc32434_local *lp = NULL;
2636 + struct net_device *dev = NULL;
2637 + int i, retval,err;
2638 +
2639 + dev = alloc_etherdev(sizeof(struct rc32434_local));
2640 + if(!dev) {
2641 + ERR("rc32434_eth: alloc_etherdev failed\n");
2642 + return -1;
2643 + }
2644 +
2645 + SET_MODULE_OWNER(dev);
2646 + bif->dev = dev;
2647 +
2648 +#ifdef CONFIG_MACH_ARUBA
2649 + {
2650 + extern char * getenv(char *e);
2651 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
2652 + }
2653 +#endif
2654 +
2655 + printk("mac: %s\n", bif->mac_str);
2656 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
2657 + ERR("MAC address parse failed\n");
2658 + free_netdev(dev);
2659 + return -1;
2660 + }
2661 +
2662 +
2663 + /* Initialize the device structure. */
2664 + if (dev->priv == NULL) {
2665 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
2666 + memset(lp, 0, sizeof(struct rc32434_local));
2667 + }
2668 + else {
2669 + lp = (struct rc32434_local *)dev->priv;
2670 + }
2671 +
2672 + lp->rx_irq = bif->rx_dma_irq;
2673 + lp->tx_irq = bif->tx_dma_irq;
2674 + lp->ovr_irq = bif->rx_ovr_irq;
2675 + lp->und_irq = bif->tx_und_irq;
2676 +
2677 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
2678 +
2679 + if (!lp->eth_regs) {
2680 + ERR("Can't remap eth registers\n");
2681 + retval = -ENXIO;
2682 + goto probe_err_out;
2683 + }
2684 +
2685 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
2686 +
2687 + if (!lp->rx_dma_regs) {
2688 + ERR("Can't remap Rx DMA registers\n");
2689 + retval = -ENXIO;
2690 + goto probe_err_out;
2691 + }
2692 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
2693 +
2694 + if (!lp->tx_dma_regs) {
2695 + ERR("Can't remap Tx DMA registers\n");
2696 + retval = -ENXIO;
2697 + goto probe_err_out;
2698 + }
2699 +
2700 +#ifdef RC32434_PROC_DEBUG
2701 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
2702 + rc32434_read_proc, dev);
2703 +#endif
2704 +
2705 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
2706 + if (!lp->td_ring) {
2707 + ERR("Can't allocate descriptors\n");
2708 + retval = -ENOMEM;
2709 + goto probe_err_out;
2710 + }
2711 +
2712 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
2713 +
2714 + /* now convert TD_RING pointer to KSEG1 */
2715 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
2716 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
2717 +
2718 +
2719 + spin_lock_init(&lp->lock);
2720 +
2721 + dev->base_addr = bif->iobase;
2722 + /* just use the rx dma irq */
2723 + dev->irq = bif->rx_dma_irq;
2724 +
2725 + dev->priv = lp;
2726 +
2727 + dev->open = rc32434_open;
2728 + dev->stop = rc32434_close;
2729 + dev->hard_start_xmit = rc32434_send_packet;
2730 + dev->get_stats = rc32434_get_stats;
2731 + dev->set_multicast_list = &rc32434_multicast_list;
2732 + dev->tx_timeout = rc32434_tx_timeout;
2733 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
2734 +
2735 +#ifdef CONFIG_IDT_USE_NAPI
2736 + dev->poll = rc32434_poll;
2737 + dev->weight = bif->weight;
2738 + printk("Using NAPI with weight %d\n",dev->weight);
2739 +#else
2740 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
2741 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
2742 +#endif
2743 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
2744 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
2745 +
2746 + if ((err = register_netdev(dev))) {
2747 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
2748 + free_netdev(dev);
2749 + retval = -EINVAL;
2750 + goto probe_err_out;
2751 + }
2752 +
2753 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
2754 + for (i = 0; i < 6; i++) {
2755 + printk("%2.2x", dev->dev_addr[i]);
2756 + if (i<5)
2757 + printk(":");
2758 + }
2759 + printk("\n");
2760 +
2761 + return 0;
2762 +
2763 + probe_err_out:
2764 + rc32434_cleanup_module();
2765 + ERR(" failed. Returns %d\n", retval);
2766 + return retval;
2767 +
2768 +}
2769 +
2770 +
2771 +static void rc32434_cleanup_module(void)
2772 +{
2773 + int i;
2774 +
2775 + for (i = 0; rc32434_iflist[i].iobase; i++) {
2776 + struct rc32434_if_t * bif = &rc32434_iflist[i];
2777 + if (bif->dev != NULL) {
2778 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
2779 + if (lp != NULL) {
2780 + if (lp->eth_regs)
2781 + iounmap((void*)lp->eth_regs);
2782 + if (lp->rx_dma_regs)
2783 + iounmap((void*)lp->rx_dma_regs);
2784 + if (lp->tx_dma_regs)
2785 + iounmap((void*)lp->tx_dma_regs);
2786 + if (lp->td_ring)
2787 + kfree((void*)KSEG0ADDR(lp->td_ring));
2788 +
2789 +#ifdef RC32434_PROC_DEBUG
2790 + if (lp->ps) {
2791 + remove_proc_entry(bif->name, proc_net);
2792 + }
2793 +#endif
2794 + kfree(lp);
2795 + }
2796 +
2797 + unregister_netdev(bif->dev);
2798 + free_netdev(bif->dev);
2799 + kfree(bif->dev);
2800 + }
2801 + }
2802 +}
2803 +
2804 +
2805 +
2806 +static int rc32434_open(struct net_device *dev)
2807 +{
2808 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2809 +
2810 + /* Initialize */
2811 + if (rc32434_init(dev)) {
2812 + ERR("Error: cannot open the Ethernet device\n");
2813 + return -EAGAIN;
2814 + }
2815 +
2816 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
2817 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
2818 + SA_SHIRQ | SA_INTERRUPT,
2819 + "rc32434 ethernet Rx", dev)) {
2820 + ERR(": unable to get Rx DMA IRQ %d\n",
2821 + lp->rx_irq);
2822 + return -EAGAIN;
2823 + }
2824 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
2825 + SA_SHIRQ | SA_INTERRUPT,
2826 + "rc32434 ethernet Tx", dev)) {
2827 + ERR(": unable to get Tx DMA IRQ %d\n",
2828 + lp->tx_irq);
2829 + free_irq(lp->rx_irq, dev);
2830 + return -EAGAIN;
2831 + }
2832 +
2833 +#ifdef RC32434_REVISION
2834 + /* Install handler for overrun error. */
2835 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
2836 + SA_SHIRQ | SA_INTERRUPT,
2837 + "Ethernet Overflow", dev)) {
2838 + ERR(": unable to get OVR IRQ %d\n",
2839 + lp->ovr_irq);
2840 + free_irq(lp->rx_irq, dev);
2841 + free_irq(lp->tx_irq, dev);
2842 + return -EAGAIN;
2843 + }
2844 +#endif
2845 +
2846 + /* Install handler for underflow error. */
2847 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
2848 + SA_SHIRQ | SA_INTERRUPT,
2849 + "Ethernet Underflow", dev)) {
2850 + ERR(": unable to get UND IRQ %d\n",
2851 + lp->und_irq);
2852 + free_irq(lp->rx_irq, dev);
2853 + free_irq(lp->tx_irq, dev);
2854 +#ifdef RC32434_REVISION
2855 + free_irq(lp->ovr_irq, dev);
2856 +#endif
2857 + return -EAGAIN;
2858 + }
2859 +
2860 +
2861 + return 0;
2862 +}
2863 +
2864 +
2865 +
2866 +
2867 +static int rc32434_close(struct net_device *dev)
2868 +{
2869 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2870 + u32 tmp;
2871 +
2872 + /* Disable interrupts */
2873 + disable_irq(lp->rx_irq);
2874 + disable_irq(lp->tx_irq);
2875 +#ifdef RC32434_REVISION
2876 + disable_irq(lp->ovr_irq);
2877 +#endif
2878 + disable_irq(lp->und_irq);
2879 +
2880 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
2881 + tmp = tmp | DMASM_f_m | DMASM_e_m;
2882 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
2883 +
2884 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
2885 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
2886 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
2887 +
2888 + free_irq(lp->rx_irq, dev);
2889 + free_irq(lp->tx_irq, dev);
2890 +#ifdef RC32434_REVISION
2891 + free_irq(lp->ovr_irq, dev);
2892 +#endif
2893 + free_irq(lp->und_irq, dev);
2894 + return 0;
2895 +}
2896 +
2897 +
2898 +/* transmit packet */
2899 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
2900 +{
2901 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2902 + unsigned long flags;
2903 + u32 length;
2904 + DMAD_t td;
2905 +
2906 +
2907 + spin_lock_irqsave(&lp->lock, flags);
2908 +
2909 + td = &lp->td_ring[lp->tx_chain_tail];
2910 +
2911 + /* stop queue when full, drop pkts if queue already full */
2912 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
2913 + lp->tx_full = 1;
2914 +
2915 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
2916 + netif_stop_queue(dev);
2917 + }
2918 + else {
2919 + lp->stats.tx_dropped++;
2920 + dev_kfree_skb_any(skb);
2921 + spin_unlock_irqrestore(&lp->lock, flags);
2922 + return 1;
2923 + }
2924 + }
2925 +
2926 + lp->tx_count ++;
2927 +
2928 + lp->tx_skb[lp->tx_chain_tail] = skb;
2929 +
2930 + length = skb->len;
2931 +
2932 + /* Setup the transmit descriptor. */
2933 + td->ca = CPHYSADDR(skb->data);
2934 +
2935 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
2936 + if( lp->tx_chain_status == empty ) {
2937 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
2938 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
2939 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
2940 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
2941 + }
2942 + else {
2943 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
2944 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
2945 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
2946 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
2947 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
2948 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
2949 + lp->tx_chain_status = empty;
2950 + }
2951 + }
2952 + else {
2953 + if( lp->tx_chain_status == empty ) {
2954 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
2955 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
2956 + lp->tx_chain_status = filled;
2957 + }
2958 + else {
2959 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
2960 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
2961 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
2962 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
2963 + }
2964 + }
2965 +
2966 + dev->trans_start = jiffies;
2967 +
2968 + spin_unlock_irqrestore(&lp->lock, flags);
2969 +
2970 + return 0;
2971 +}
2972 +
2973 +
2974 +/* Ethernet MII-PHY Handler */
2975 +static void rc32434_mii_handler(unsigned long data)
2976 +{
2977 + struct net_device *dev = (struct net_device *)data;
2978 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2979 + unsigned long flags;
2980 + unsigned long duplex_status;
2981 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
2982 +
2983 + spin_lock_irqsave(&lp->lock, flags);
2984 +
2985 + /* Two ports are using the same MII, the difference is the PHY address */
2986 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
2987 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
2988 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
2989 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
2990 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
2991 +
2992 + ERR("irq:%x port_addr:%x RDD:%x\n",
2993 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
2994 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
2995 + if(duplex_status != lp->duplex_mode) {
2996 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
2997 + lp->duplex_mode = duplex_status;
2998 + rc32434_restart(dev);
2999 + }
3000 +
3001 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
3002 + add_timer(&lp->mii_phy_timer);
3003 +
3004 + spin_unlock_irqrestore(&lp->lock, flags);
3005 +
3006 +}
3007 +
3008 +#ifdef RC32434_REVISION
3009 +/* Ethernet Rx Overflow interrupt */
3010 +static irqreturn_t
3011 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
3012 +{
3013 + struct net_device *dev = (struct net_device *)dev_id;
3014 + struct rc32434_local *lp;
3015 + unsigned int ovr;
3016 + irqreturn_t retval = IRQ_NONE;
3017 +
3018 + ASSERT(dev != NULL);
3019 +
3020 + lp = (struct rc32434_local *)dev->priv;
3021 + spin_lock(&lp->lock);
3022 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
3023 +
3024 + if(ovr & ETHINTFC_ovr_m) {
3025 + netif_stop_queue(dev);
3026 +
3027 + /* clear OVR bit */
3028 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
3029 +
3030 + /* Restart interface */
3031 + rc32434_restart(dev);
3032 + retval = IRQ_HANDLED;
3033 + }
3034 + spin_unlock(&lp->lock);
3035 +
3036 + return retval;
3037 +}
3038 +
3039 +#endif
3040 +
3041 +
3042 +/* Ethernet Tx Underflow interrupt */
3043 +static irqreturn_t
3044 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
3045 +{
3046 + struct net_device *dev = (struct net_device *)dev_id;
3047 + struct rc32434_local *lp;
3048 + unsigned int und;
3049 + irqreturn_t retval = IRQ_NONE;
3050 +
3051 + ASSERT(dev != NULL);
3052 +
3053 + lp = (struct rc32434_local *)dev->priv;
3054 +
3055 + spin_lock(&lp->lock);
3056 +
3057 + und = rc32434_readl(&lp->eth_regs->ethintfc);
3058 +
3059 + if(und & ETHINTFC_und_m) {
3060 + netif_stop_queue(dev);
3061 +
3062 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
3063 +
3064 + /* Restart interface */
3065 + rc32434_restart(dev);
3066 + retval = IRQ_HANDLED;
3067 + }
3068 +
3069 + spin_unlock(&lp->lock);
3070 +
3071 + return retval;
3072 +}
3073 +
3074 +
3075 +/* Ethernet Rx DMA interrupt */
3076 +static irqreturn_t
3077 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
3078 +{
3079 + struct net_device *dev = (struct net_device *)dev_id;
3080 + struct rc32434_local* lp;
3081 + volatile u32 dmas,dmasm;
3082 + irqreturn_t retval;
3083 +
3084 + ASSERT(dev != NULL);
3085 +
3086 + lp = (struct rc32434_local *)dev->priv;
3087 +
3088 + spin_lock(&lp->lock);
3089 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
3090 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
3091 + /* Mask D H E bit in Rx DMA */
3092 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
3093 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
3094 +#ifdef CONFIG_IDT_USE_NAPI
3095 + if(netif_rx_schedule_prep(dev))
3096 + __netif_rx_schedule(dev);
3097 +#else
3098 + tasklet_hi_schedule(lp->rx_tasklet);
3099 +#endif
3100 +
3101 + if (dmas & DMAS_e_m)
3102 + ERR(": DMA error\n");
3103 +
3104 + retval = IRQ_HANDLED;
3105 + }
3106 + else
3107 + retval = IRQ_NONE;
3108 +
3109 + spin_unlock(&lp->lock);
3110 + return retval;
3111 +}
3112 +
3113 +#ifdef CONFIG_IDT_USE_NAPI
3114 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
3115 +#else
3116 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
3117 +#endif
3118 +{
3119 + struct net_device *dev = (struct net_device *)rx_data_dev;
3120 + struct rc32434_local* lp = netdev_priv(dev);
3121 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
3122 + struct sk_buff *skb, *skb_new;
3123 + u8* pkt_buf;
3124 + u32 devcs, count, pkt_len, pktuncrc_len;
3125 + volatile u32 dmas;
3126 +#ifdef CONFIG_IDT_USE_NAPI
3127 + u32 received = 0;
3128 + int rx_work_limit = min(*budget,dev->quota);
3129 +#else
3130 + unsigned long flags;
3131 + spin_lock_irqsave(&lp->lock, flags);
3132 +#endif
3133 +
3134 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
3135 +#ifdef CONFIG_IDT_USE_NAPI
3136 + if(--rx_work_limit <0)
3137 + {
3138 + break;
3139 + }
3140 +#endif
3141 + /* init the var. used for the later operations within the while loop */
3142 + skb_new = NULL;
3143 + devcs = rd->devcs;
3144 + pkt_len = RCVPKT_LENGTH(devcs);
3145 + skb = lp->rx_skb[lp->rx_next_done];
3146 +
3147 + if (count < 64) {
3148 + lp->stats.rx_errors++;
3149 + lp->stats.rx_dropped++;
3150 + }
3151 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
3152 + /* check that this is a whole packet */
3153 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
3154 + lp->stats.rx_errors++;
3155 + lp->stats.rx_dropped++;
3156 + }
3157 + else if ( (devcs & ETHRX_rok_m) ) {
3158 +
3159 + {
3160 + /* must be the (first and) last descriptor then */
3161 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
3162 +
3163 + pktuncrc_len = pkt_len - 4;
3164 + /* invalidate the cache */
3165 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
3166 +
3167 + /* Malloc up new buffer. */
3168 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
3169 +
3170 + if (skb_new != NULL){
3171 + /* Make room */
3172 + skb_put(skb, pktuncrc_len);
3173 +
3174 + skb->protocol = eth_type_trans(skb, dev);
3175 +
3176 + /* pass the packet to upper layers */
3177 +#ifdef CONFIG_IDT_USE_NAPI
3178 + netif_receive_skb(skb);
3179 +#else
3180 + netif_rx(skb);
3181 +#endif
3182 +
3183 + dev->last_rx = jiffies;
3184 + lp->stats.rx_packets++;
3185 + lp->stats.rx_bytes += pktuncrc_len;
3186 +
3187 + if (IS_RCV_MP(devcs))
3188 + lp->stats.multicast++;
3189 +
3190 + /* 16 bit align */
3191 + skb_reserve(skb_new, 2);
3192 +
3193 + skb_new->dev = dev;
3194 + lp->rx_skb[lp->rx_next_done] = skb_new;
3195 + }
3196 + else {
3197 + ERR("no memory, dropping rx packet.\n");
3198 + lp->stats.rx_errors++;
3199 + lp->stats.rx_dropped++;
3200 + }
3201 + }
3202 +
3203 + }
3204 + else {
3205 + /* This should only happen if we enable accepting broken packets */
3206 + lp->stats.rx_errors++;
3207 + lp->stats.rx_dropped++;
3208 +
3209 + /* add statistics counters */
3210 + if (IS_RCV_CRC_ERR(devcs)) {
3211 + DBG(2, "RX CRC error\n");
3212 + lp->stats.rx_crc_errors++;
3213 + }
3214 + else if (IS_RCV_LOR_ERR(devcs)) {
3215 + DBG(2, "RX LOR error\n");
3216 + lp->stats.rx_length_errors++;
3217 + }
3218 + else if (IS_RCV_LE_ERR(devcs)) {
3219 + DBG(2, "RX LE error\n");
3220 + lp->stats.rx_length_errors++;
3221 + }
3222 + else if (IS_RCV_OVR_ERR(devcs)) {
3223 + lp->stats.rx_over_errors++;
3224 + }
3225 + else if (IS_RCV_CV_ERR(devcs)) {
3226 + /* code violation */
3227 + DBG(2, "RX CV error\n");
3228 + lp->stats.rx_frame_errors++;
3229 + }
3230 + else if (IS_RCV_CES_ERR(devcs)) {
3231 + DBG(2, "RX Preamble error\n");
3232 + }
3233 + }
3234 +
3235 + rd->devcs = 0;
3236 +
3237 + /* restore descriptor's curr_addr */
3238 + if(skb_new)
3239 + rd->ca = CPHYSADDR(skb_new->data);
3240 + else
3241 + rd->ca = CPHYSADDR(skb->data);
3242 +
3243 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
3244 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
3245 +
3246 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
3247 + rd = &lp->rd_ring[lp->rx_next_done];
3248 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
3249 + }
3250 +#ifdef CONFIG_IDT_USE_NAPI
3251 + dev->quota -= received;
3252 + *budget =- received;
3253 + if(rx_work_limit < 0)
3254 + goto not_done;
3255 +#endif
3256 +
3257 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
3258 +
3259 + if(dmas & DMAS_h_m) {
3260 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
3261 +#ifdef RC32434_PROC_DEBUG
3262 + lp->dma_halt_cnt++;
3263 +#endif
3264 + rd->devcs = 0;
3265 + skb = lp->rx_skb[lp->rx_next_done];
3266 + rd->ca = CPHYSADDR(skb->data);
3267 + rc32434_chain_rx(lp,rd);
3268 + }
3269 +
3270 +#ifdef CONFIG_IDT_USE_NAPI
3271 + netif_rx_complete(dev);
3272 +#endif
3273 + /* Enable D H E bit in Rx DMA */
3274 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
3275 +#ifdef CONFIG_IDT_USE_NAPI
3276 + return 0;
3277 + not_done:
3278 + return 1;
3279 +#else
3280 + spin_unlock_irqrestore(&lp->lock, flags);
3281 + return;
3282 +#endif
3283 +
3284 +
3285 +}
3286 +
3287 +
3288 +
3289 +/* Ethernet Tx DMA interrupt */
3290 +static irqreturn_t
3291 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
3292 +{
3293 + struct net_device *dev = (struct net_device *)dev_id;
3294 + struct rc32434_local *lp;
3295 + volatile u32 dmas,dmasm;
3296 + irqreturn_t retval;
3297 +
3298 + ASSERT(dev != NULL);
3299 +
3300 + lp = (struct rc32434_local *)dev->priv;
3301 +
3302 + spin_lock(&lp->lock);
3303 +
3304 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
3305 +
3306 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
3307 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
3308 + /* Mask F E bit in Tx DMA */
3309 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
3310 +
3311 + tasklet_hi_schedule(lp->tx_tasklet);
3312 +
3313 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
3314 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
3315 + lp->tx_chain_status = empty;
3316 + lp->tx_chain_head = lp->tx_chain_tail;
3317 + dev->trans_start = jiffies;
3318 + }
3319 +
3320 + if (dmas & DMAS_e_m)
3321 + ERR(": DMA error\n");
3322 +
3323 + retval = IRQ_HANDLED;
3324 + }
3325 + else
3326 + retval = IRQ_NONE;
3327 +
3328 + spin_unlock(&lp->lock);
3329 +
3330 + return retval;
3331 +}
3332 +
3333 +
3334 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
3335 +{
3336 + struct net_device *dev = (struct net_device *)tx_data_dev;
3337 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
3338 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
3339 + u32 devcs;
3340 + unsigned long flags;
3341 + volatile u32 dmas;
3342 +
3343 + spin_lock_irqsave(&lp->lock, flags);
3344 +
3345 + /* process all desc that are done */
3346 + while(IS_DMA_FINISHED(td->control)) {
3347 + if(lp->tx_full == 1) {
3348 + netif_wake_queue(dev);
3349 + lp->tx_full = 0;
3350 + }
3351 +
3352 + devcs = lp->td_ring[lp->tx_next_done].devcs;
3353 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
3354 + lp->stats.tx_errors++;
3355 + lp->stats.tx_dropped++;
3356 +
3357 + /* should never happen */
3358 + DBG(1, __FUNCTION__ ": split tx ignored\n");
3359 + }
3360 + else if (IS_TX_TOK(devcs)) {
3361 + lp->stats.tx_packets++;
3362 + }
3363 + else {
3364 + lp->stats.tx_errors++;
3365 + lp->stats.tx_dropped++;
3366 +
3367 + /* underflow */
3368 + if (IS_TX_UND_ERR(devcs))
3369 + lp->stats.tx_fifo_errors++;
3370 +
3371 + /* oversized frame */
3372 + if (IS_TX_OF_ERR(devcs))
3373 + lp->stats.tx_aborted_errors++;
3374 +
3375 + /* excessive deferrals */
3376 + if (IS_TX_ED_ERR(devcs))
3377 + lp->stats.tx_carrier_errors++;
3378 +
3379 + /* collisions: medium busy */
3380 + if (IS_TX_EC_ERR(devcs))
3381 + lp->stats.collisions++;
3382 +
3383 + /* late collision */
3384 + if (IS_TX_LC_ERR(devcs))
3385 + lp->stats.tx_window_errors++;
3386 +
3387 + }
3388 +
3389 + /* We must always free the original skb */
3390 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
3391 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
3392 + lp->tx_skb[lp->tx_next_done] = NULL;
3393 + }
3394 +
3395 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
3396 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
3397 + lp->td_ring[lp->tx_next_done].link = 0;
3398 + lp->td_ring[lp->tx_next_done].ca = 0;
3399 + lp->tx_count --;
3400 +
3401 + /* go on to next transmission */
3402 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
3403 + td = &lp->td_ring[lp->tx_next_done];
3404 +
3405 + }
3406 +
3407 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
3408 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
3409 +
3410 + /* Enable F E bit in Tx DMA */
3411 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
3412 + spin_unlock_irqrestore(&lp->lock, flags);
3413 +
3414 +}
3415 +
3416 +
3417 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
3418 +{
3419 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
3420 + return &lp->stats;
3421 +}
3422 +
3423 +
3424 +/*
3425 + * Set or clear the multicast filter for this adaptor.
3426 + */
3427 +static void rc32434_multicast_list(struct net_device *dev)
3428 +{
3429 + /* listen to broadcasts always and to treat */
3430 + /* IFF bits independantly */
3431 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
3432 + unsigned long flags;
3433 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
3434 +
3435 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
3436 + recognise |= ETHARC_pro_m;
3437 +
3438 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
3439 + recognise |= ETHARC_am_m; /* all multicast & bcast */
3440 + else if (dev->mc_count > 0) {
3441 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
3442 + recognise |= ETHARC_am_m; /* for the time being */
3443 + }
3444 +
3445 + spin_lock_irqsave(&lp->lock, flags);
3446 + rc32434_writel(recognise, &lp->eth_regs->etharc);
3447 + spin_unlock_irqrestore(&lp->lock, flags);
3448 +}
3449 +
3450 +
3451 +static void rc32434_tx_timeout(struct net_device *dev)
3452 +{
3453 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
3454 + unsigned long flags;
3455 +
3456 + spin_lock_irqsave(&lp->lock, flags);
3457 + rc32434_restart(dev);
3458 + spin_unlock_irqrestore(&lp->lock, flags);
3459 +
3460 +}
3461 +
3462 +
3463 +/*
3464 + * Initialize the RC32434 ethernet controller.
3465 + */
3466 +static int rc32434_init(struct net_device *dev)
3467 +{
3468 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
3469 + int i, j;
3470 +
3471 + /* Disable DMA */
3472 + rc32434_abort_tx(dev);
3473 + rc32434_abort_rx(dev);
3474 +
3475 + /* reset ethernet logic */
3476 + rc32434_writel(0, &lp->eth_regs->ethintfc);
3477 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
3478 + dev->trans_start = jiffies;
3479 +
3480 + /* Enable Ethernet Interface */
3481 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
3482 +
3483 +#ifndef CONFIG_IDT_USE_NAPI
3484 + tasklet_disable(lp->rx_tasklet);
3485 +#endif
3486 + tasklet_disable(lp->tx_tasklet);
3487 +
3488 + /* Initialize the transmit Descriptors */
3489 + for (i = 0; i < RC32434_NUM_TDS; i++) {
3490 + lp->td_ring[i].control = DMAD_iof_m;
3491 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
3492 + lp->td_ring[i].ca = 0;
3493 + lp->td_ring[i].link = 0;
3494 + if (lp->tx_skb[i] != NULL) {
3495 + dev_kfree_skb_any(lp->tx_skb[i]);
3496 + lp->tx_skb[i] = NULL;
3497 + }
3498 + }
3499 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
3500 + lp-> tx_chain_status = empty;
3501 +
3502 + /*
3503 + * Initialize the receive descriptors so that they
3504 + * become a circular linked list, ie. let the last
3505 + * descriptor point to the first again.
3506 + */
3507 + for (i=0; i<RC32434_NUM_RDS; i++) {
3508 + struct sk_buff *skb = lp->rx_skb[i];
3509 +
3510 + if (lp->rx_skb[i] == NULL) {
3511 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
3512 + if (skb == NULL) {
3513 + ERR("No memory in the system\n");
3514 + for (j = 0; j < RC32434_NUM_RDS; j ++)
3515 + if (lp->rx_skb[j] != NULL)
3516 + dev_kfree_skb_any(lp->rx_skb[j]);
3517 +
3518 + return 1;
3519 + }
3520 + else {
3521 + skb->dev = dev;
3522 + skb_reserve(skb, 2);
3523 + lp->rx_skb[i] = skb;
3524 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
3525 +
3526 + }
3527 + }
3528 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
3529 + lp->rd_ring[i].devcs = 0;
3530 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
3531 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
3532 +
3533 + }
3534 + /* loop back */
3535 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
3536 + lp->rx_next_done = 0;
3537 +
3538 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
3539 + lp->rx_chain_head = 0;
3540 + lp->rx_chain_tail = 0;
3541 + lp->rx_chain_status = empty;
3542 +
3543 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
3544 + /* Start Rx DMA */
3545 + rc32434_start_rx(lp, &lp->rd_ring[0]);
3546 +
3547 + /* Enable F E bit in Tx DMA */
3548 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
3549 + /* Enable D H E bit in Rx DMA */
3550 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
3551 +
3552 + /* Accept only packets destined for this Ethernet device address */
3553 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
3554 +
3555 + /* Set all Ether station address registers to their initial values */
3556 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
3557 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
3558 +
3559 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
3560 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
3561 +
3562 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
3563 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
3564 +
3565 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
3566 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
3567 +
3568 +
3569 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
3570 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
3571 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
3572 +
3573 + /* Back to back inter-packet-gap */
3574 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
3575 + /* Non - Back to back inter-packet-gap */
3576 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
3577 +
3578 + /* Management Clock Prescaler Divisor */
3579 + /* Clock independent setting */
3580 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
3581 + &lp->eth_regs->ethmcp);
3582 +
3583 + /* don't transmit until fifo contains 48b */
3584 + rc32434_writel(48, &lp->eth_regs->ethfifott);
3585 +
3586 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
3587 +
3588 +#ifndef CONFIG_IDT_USE_NAPI
3589 + tasklet_enable(lp->rx_tasklet);
3590 +#endif
3591 + tasklet_enable(lp->tx_tasklet);
3592 +
3593 + netif_start_queue(dev);
3594 +
3595 +
3596 + return 0;
3597 +
3598 +}
3599 +
3600 +
3601 +#ifndef MODULE
3602 +
3603 +static int __init rc32434_setup(char *options)
3604 +{
3605 + /* no options yet */
3606 + return 1;
3607 +}
3608 +
3609 +static int __init rc32434_setup_ethaddr0(char *options)
3610 +{
3611 + memcpy(mac0, options, 17);
3612 + mac0[17]= '\0';
3613 + return 1;
3614 +}
3615 +
3616 +__setup("rc32434eth=", rc32434_setup);
3617 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
3618 +
3619 +
3620 +#endif /* MODULE */
3621 +
3622 +module_init(rc32434_init_module);
3623 +module_exit(rc32434_cleanup_module);
3624 +
3625 +
3626 +
3627 +
3628 +
3629 +
3630 +
3631 +
3632 +
3633 +
3634 +
3635 +
3636 +
3637 +
3638 diff -Nur linux-2.6.15/drivers/net/rc32434_eth.h linux-2.6.15-openwrt/drivers/net/rc32434_eth.h
3639 --- linux-2.6.15/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
3640 +++ linux-2.6.15-openwrt/drivers/net/rc32434_eth.h 2006-01-10 00:32:33.000000000 +0100
3641 @@ -0,0 +1,187 @@
3642 +/**************************************************************************
3643 + *
3644 + * BRIEF MODULE DESCRIPTION
3645 + * Definitions for IDT RC32434 on-chip ethernet controller.
3646 + *
3647 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3648 + *
3649 + * This program is free software; you can redistribute it and/or modify it
3650 + * under the terms of the GNU General Public License as published by the
3651 + * Free Software Foundation; either version 2 of the License, or (at your
3652 + * option) any later version.
3653 + *
3654 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3655 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3656 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3657 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3658 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3659 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3660 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3661 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3662 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3663 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3664 + *
3665 + * You should have received a copy of the GNU General Public License along
3666 + * with this program; if not, write to the Free Software Foundation, Inc.,
3667 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3668 + *
3669 + *
3670 + **************************************************************************
3671 + * May 2004 rkt, neb
3672 + *
3673 + * Initial Release
3674 + *
3675 + * Aug 2004
3676 + *
3677 + * Added NAPI
3678 + *
3679 + **************************************************************************
3680 + */
3681 +
3682 +
3683 +#include <asm/idt-boards/rc32434/rc32434.h>
3684 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
3685 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
3686 +
3687 +#define RC32434_DEBUG 2
3688 +//#define RC32434_PROC_DEBUG
3689 +#undef RC32434_DEBUG
3690 +
3691 +#ifdef RC32434_DEBUG
3692 +
3693 +/* use 0 for production, 1 for verification, >2 for debug */
3694 +static int rc32434_debug = RC32434_DEBUG;
3695 +#define ASSERT(expr) \
3696 + if(!(expr)) { \
3697 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
3698 + #expr,__FILE__,__FUNCTION__,__LINE__); }
3699 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
3700 +#else
3701 +#define ASSERT(expr) do {} while (0)
3702 +#define DBG(lvl, format, arg...) do {} while (0)
3703 +#endif
3704 +
3705 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
3706 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
3707 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
3708 +
3709 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
3710 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
3711 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
3712 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
3713 +
3714 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
3715 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
3716 +
3717 +/* the following must be powers of two */
3718 +#ifdef CONFIG_IDT_USE_NAPI
3719 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
3720 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
3721 +#else
3722 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
3723 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
3724 +#endif
3725 +
3726 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
3727 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
3728 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
3729 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
3730 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
3731 +
3732 +#define RC32434_TX_TIMEOUT HZ * 100
3733 +
3734 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
3735 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
3736 +
3737 +enum status { filled, empty};
3738 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
3739 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
3740 +
3741 +
3742 +/* Information that need to be kept for each board. */
3743 +struct rc32434_local {
3744 + ETH_t eth_regs;
3745 + DMA_Chan_t rx_dma_regs;
3746 + DMA_Chan_t tx_dma_regs;
3747 + volatile DMAD_t td_ring; /* transmit descriptor ring */
3748 + volatile DMAD_t rd_ring; /* receive descriptor ring */
3749 +
3750 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
3751 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
3752 +
3753 +#ifndef CONFIG_IDT_USE_NAPI
3754 + struct tasklet_struct * rx_tasklet;
3755 +#endif
3756 + struct tasklet_struct * tx_tasklet;
3757 +
3758 + int rx_next_done;
3759 + int rx_chain_head;
3760 + int rx_chain_tail;
3761 + enum status rx_chain_status;
3762 +
3763 + int tx_next_done;
3764 + int tx_chain_head;
3765 + int tx_chain_tail;
3766 + enum status tx_chain_status;
3767 + int tx_count;
3768 + int tx_full;
3769 +
3770 + struct timer_list mii_phy_timer;
3771 + unsigned long duplex_mode;
3772 +
3773 + int rx_irq;
3774 + int tx_irq;
3775 + int ovr_irq;
3776 + int und_irq;
3777 +
3778 + struct net_device_stats stats;
3779 + spinlock_t lock;
3780 +
3781 + /* debug /proc entry */
3782 + struct proc_dir_entry *ps;
3783 + int dma_halt_cnt; int dma_run_cnt;
3784 +};
3785 +
3786 +extern unsigned int idt_cpu_freq;
3787 +
3788 +/* Index to functions, as function prototypes. */
3789 +static int rc32434_open(struct net_device *dev);
3790 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
3791 +static void rc32434_mii_handler(unsigned long data);
3792 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
3793 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
3794 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
3795 +#ifdef RC32434_REVISION
3796 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
3797 +#endif
3798 +static int rc32434_close(struct net_device *dev);
3799 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
3800 +static void rc32434_multicast_list(struct net_device *dev);
3801 +static int rc32434_init(struct net_device *dev);
3802 +static void rc32434_tx_timeout(struct net_device *dev);
3803 +
3804 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
3805 +#ifdef CONFIG_IDT_USE_NAPI
3806 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
3807 +#else
3808 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
3809 +#endif
3810 +static void rc32434_cleanup_module(void);
3811 +static int rc32434_probe(int port_num);
3812 +int rc32434_init_module(void);
3813 +
3814 +
3815 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
3816 +{
3817 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
3818 + rc32434_writel(0x10, &ch->dmac);
3819 +
3820 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
3821 + dev->trans_start = jiffies;
3822 +
3823 + rc32434_writel(0, &ch->dmas);
3824 + }
3825 +
3826 + rc32434_writel(0, &ch->dmadptr);
3827 + rc32434_writel(0, &ch->dmandptr);
3828 +}
3829 diff -Nur linux-2.6.15/drivers/pci/access.c linux-2.6.15-openwrt/drivers/pci/access.c
3830 --- linux-2.6.15/drivers/pci/access.c 2006-01-03 04:21:10.000000000 +0100
3831 +++ linux-2.6.15-openwrt/drivers/pci/access.c 2006-01-10 00:43:10.000000000 +0100
3832 @@ -21,6 +21,7 @@
3833 #define PCI_word_BAD (pos & 1)
3834 #define PCI_dword_BAD (pos & 3)
3835
3836 +#ifdef __MIPSEB__
3837 #define PCI_OP_READ(size,type,len) \
3838 int pci_bus_read_config_##size \
3839 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
3840 @@ -31,11 +32,32 @@
3841 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
3842 spin_lock_irqsave(&pci_lock, flags); \
3843 res = bus->ops->read(bus, devfn, pos, len, &data); \
3844 + if (len == 1) \
3845 + *value = (type)((data >> 24) & 0xff); \
3846 + else if (len == 2) \
3847 + *value = (type)((data >> 16) & 0xffff); \
3848 + else \
3849 *value = (type)data; \
3850 spin_unlock_irqrestore(&pci_lock, flags); \
3851 return res; \
3852 }
3853 +#else
3854
3855 +#define PCI_OP_READ(size,type,len) \
3856 +int pci_bus_read_config_##size \
3857 + (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
3858 +{ \
3859 + int res; \
3860 + unsigned long flags; \
3861 + u32 data = 0; \
3862 + if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
3863 + spin_lock_irqsave(&pci_lock, flags); \
3864 + res = bus->ops->read(bus, devfn, pos, len, &data); \
3865 + *value = (type)data; \
3866 + spin_unlock_irqrestore(&pci_lock, flags); \
3867 + return res; \
3868 +}
3869 +#endif
3870 #define PCI_OP_WRITE(size,type,len) \
3871 int pci_bus_write_config_##size \
3872 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
3873 diff -Nur linux-2.6.15/include/asm-mips/bootinfo.h linux-2.6.15-openwrt/include/asm-mips/bootinfo.h
3874 --- linux-2.6.15/include/asm-mips/bootinfo.h 2006-01-03 04:21:10.000000000 +0100
3875 +++ linux-2.6.15-openwrt/include/asm-mips/bootinfo.h 2006-01-10 00:32:33.000000000 +0100
3876 @@ -218,6 +218,16 @@
3877 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
3878 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
3879
3880 +
3881 +/*
3882 + * Valid machtype for group ARUBA
3883 + */
3884 +#define MACH_GROUP_ARUBA 23
3885 +#define MACH_ARUBA_UNKNOWN 0
3886 +#define MACH_ARUBA_AP60 1
3887 +#define MACH_ARUBA_AP65 2
3888 +#define MACH_ARUBA_AP70 3
3889 +
3890 #define CL_SIZE COMMAND_LINE_SIZE
3891
3892 const char *get_system_type(void);
3893 diff -Nur linux-2.6.15/include/asm-mips/cpu.h linux-2.6.15-openwrt/include/asm-mips/cpu.h
3894 --- linux-2.6.15/include/asm-mips/cpu.h 2006-01-03 04:21:10.000000000 +0100
3895 +++ linux-2.6.15-openwrt/include/asm-mips/cpu.h 2006-01-10 00:32:33.000000000 +0100
3896 @@ -53,6 +53,9 @@
3897 #define PRID_IMP_R12000 0x0e00
3898 #define PRID_IMP_R8000 0x1000
3899 #define PRID_IMP_PR4450 0x1200
3900 +#define PRID_IMP_RC32334 0x1800
3901 +#define PRID_IMP_RC32355 0x1900
3902 +#define PRID_IMP_RC32365 0x1900
3903 #define PRID_IMP_R4600 0x2000
3904 #define PRID_IMP_R4700 0x2100
3905 #define PRID_IMP_TX39 0x2200
3906 @@ -196,7 +199,8 @@
3907 #define CPU_34K 60
3908 #define CPU_PR4450 61
3909 #define CPU_SB1A 62
3910 -#define CPU_LAST 62
3911 +#define CPU_RC32300 63
3912 +#define CPU_LAST 63
3913
3914 /*
3915 * ISA Level encodings
3916 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h
3917 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
3918 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-01-10 00:32:33.000000000 +0100
3919 @@ -0,0 +1,142 @@
3920 +/**************************************************************************
3921 + *
3922 + * BRIEF MODULE DESCRIPTION
3923 + * RC32300 helper routines
3924 + *
3925 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3926 + *
3927 + * This program is free software; you can redistribute it and/or modify it
3928 + * under the terms of the GNU General Public License as published by the
3929 + * Free Software Foundation; either version 2 of the License, or (at your
3930 + * option) any later version.
3931 + *
3932 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3933 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3934 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3935 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3936 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3937 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3938 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3939 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3940 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3941 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3942 + *
3943 + * You should have received a copy of the GNU General Public License along
3944 + * with this program; if not, write to the Free Software Foundation, Inc.,
3945 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3946 + *
3947 + *
3948 + **************************************************************************
3949 + * May 2004 P. Sadik.
3950 + *
3951 + * Initial Release
3952 + *
3953 + *
3954 + *
3955 + **************************************************************************
3956 + */
3957 +
3958 +#ifndef __IDT_RC32300_H__
3959 +#define __IDT_RC32300_H__
3960 +
3961 +#include <linux/delay.h>
3962 +#include <asm/io.h>
3963 +
3964 +
3965 +/* cpu pipeline flush */
3966 +static inline void rc32300_sync(void)
3967 +{
3968 + __asm__ volatile ("sync");
3969 +}
3970 +
3971 +static inline void rc32300_sync_udelay(int us)
3972 +{
3973 + __asm__ volatile ("sync");
3974 + udelay(us);
3975 +}
3976 +
3977 +static inline void rc32300_sync_delay(int ms)
3978 +{
3979 + __asm__ volatile ("sync");
3980 + mdelay(ms);
3981 +}
3982 +
3983 +/*
3984 + * Macros to access internal RC32300 registers. No byte
3985 + * swapping should be done when accessing the internal
3986 + * registers.
3987 + */
3988 +
3989 +static inline u8 rc32300_readb(unsigned long pa)
3990 +{
3991 + return *((volatile u8 *)KSEG1ADDR(pa));
3992 +}
3993 +static inline u16 rc32300_readw(unsigned long pa)
3994 +{
3995 + return *((volatile u16 *)KSEG1ADDR(pa));
3996 +}
3997 +static inline u32 rc32300_readl(unsigned long pa)
3998 +{
3999 + return *((volatile u32 *)KSEG1ADDR(pa));
4000 +}
4001 +static inline void rc32300_writeb(u8 val, unsigned long pa)
4002 +{
4003 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
4004 +}
4005 +static inline void rc32300_writew(u16 val, unsigned long pa)
4006 +{
4007 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
4008 +}
4009 +static inline void rc32300_writel(u32 val, unsigned long pa)
4010 +{
4011 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
4012 +}
4013 +
4014 +
4015 +#define local_readb __raw_readb
4016 +#define local_readw __raw_readw
4017 +#define local_readl __raw_readl
4018 +
4019 +#define local_writeb __raw_writeb
4020 +#define local_writew __raw_writew
4021 +#define local_writel __raw_writel
4022 +
4023 +
4024 +/*
4025 + * C access to CLZ and CLO instructions
4026 + * (count leading zeroes/ones).
4027 + */
4028 +static inline int rc32300_clz(unsigned long val)
4029 +{
4030 + int ret;
4031 + __asm__ volatile (
4032 + ".set\tnoreorder\n\t"
4033 + ".set\tnoat\n\t"
4034 + ".set\tmips32\n\t"
4035 + "clz\t%0,%1\n\t"
4036 + ".set\tmips0\n\t"
4037 + ".set\tat\n\t"
4038 + ".set\treorder"
4039 + : "=r" (ret)
4040 + : "r" (val));
4041 +
4042 + return ret;
4043 +}
4044 +static inline int rc32300_clo(unsigned long val)
4045 +{
4046 + int ret;
4047 + __asm__ volatile (
4048 + ".set\tnoreorder\n\t"
4049 + ".set\tnoat\n\t"
4050 + ".set\tmips32\n\t"
4051 + "clo\t%0,%1\n\t"
4052 + ".set\tmips0\n\t"
4053 + ".set\tat\n\t"
4054 + ".set\treorder"
4055 + : "=r" (ret)
4056 + : "r" (val));
4057 +
4058 + return ret;
4059 +}
4060 +
4061 +#endif // __IDT_RC32300_H__
4062 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h
4063 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
4064 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-01-10 00:32:33.000000000 +0100
4065 @@ -0,0 +1,207 @@
4066 +/**************************************************************************
4067 + *
4068 + * BRIEF MODULE DESCRIPTION
4069 + * Definitions for IDT RC32334 CPU.
4070 + *
4071 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4072 + *
4073 + * This program is free software; you can redistribute it and/or modify it
4074 + * under the terms of the GNU General Public License as published by the
4075 + * Free Software Foundation; either version 2 of the License, or (at your
4076 + * option) any later version.
4077 + *
4078 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4079 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4080 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4081 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4082 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4083 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4084 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4085 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4086 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4087 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4088 + *
4089 + * You should have received a copy of the GNU General Public License along
4090 + * with this program; if not, write to the Free Software Foundation, Inc.,
4091 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4092 + *
4093 + *
4094 + **************************************************************************
4095 + * May 2004 P. Sadik.
4096 + *
4097 + * Initial Release
4098 + *
4099 + *
4100 + *
4101 + **************************************************************************
4102 + */
4103 +
4104 +
4105 +#ifndef __IDT_RC32334_H__
4106 +#define __IDT_RC32334_H__
4107 +
4108 +#include <linux/delay.h>
4109 +#include <asm/io.h>
4110 +
4111 +/* Base address of internal registers */
4112 +#define RC32334_REG_BASE 0x18000000
4113 +
4114 +/* CPU and IP Bus Control */
4115 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
4116 +#define CPU_BTA 0xffffe204 // virtual!
4117 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
4118 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
4119 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
4120 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
4121 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
4122 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
4123 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
4124 +
4125 +/* Memory Controller */
4126 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
4127 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
4128 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
4129 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
4130 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
4131 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
4132 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
4133 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
4134 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
4135 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
4136 +
4137 +/* PCI Controller */
4138 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
4139 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
4140 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
4141 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
4142 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
4143 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
4144 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
4145 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
4146 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
4147 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
4148 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
4149 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
4150 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
4151 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
4152 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
4153 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
4154 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
4155 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
4156 +
4157 +/* Timers */
4158 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
4159 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
4160 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
4161 +#define TIMER_REG_OFFSET 0x10
4162 +
4163 +/* Programmable I/O */
4164 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
4165 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
4166 +
4167 +/*
4168 + * DMA
4169 + *
4170 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
4171 + *
4172 + * DMA0: 18001400
4173 + * DMA1: 18001440
4174 + * DMA2: 18001900
4175 + * DMA3: 18001940
4176 + * NB: dma number must be immediate value or variable.
4177 + * It MUST NOT be a function since it would get called twice!
4178 + */
4179 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
4180 +
4181 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
4182 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
4183 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
4184 +
4185 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
4186 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
4187 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
4188 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
4189 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
4190 +
4191 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
4192 +
4193 +/* Expansion Interrupt Controller */
4194 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
4195 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
4196 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
4197 +#define IC_GROUP_OFFSET 0x10
4198 +
4199 +#define NUM_INTR_GROUPS 15
4200 +/*
4201 + * The IRQ mapping is as follows:
4202 + *
4203 + * IRQ Mapped To
4204 + * --- -------------------
4205 + * 0 SW0 (IP0) SW0 intr
4206 + * 1 SW1 (IP1) SW1 intr
4207 + * 2 Int0 (IP2) board-specific
4208 + * 3 Int1 (IP3) board-specific
4209 + * 4 Int2 (IP4) board-specific
4210 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
4211 + * 6 Int4 (IP6) board-specific
4212 + * 7 Int5 (IP7) CP0 Timer
4213 + *
4214 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
4215 + * internally on the RC32334 is routed to the Expansion
4216 + * Interrupt Controller.
4217 + */
4218 +#define MIPS_CPU_TIMER_IRQ 7
4219 +
4220 +#define GROUP1_IRQ_BASE 8 // bus error
4221 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
4222 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
4223 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
4224 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
4225 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
4226 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
4227 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
4228 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
4229 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
4230 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
4231 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
4232 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
4233 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
4234 +
4235 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
4236 +
4237 +/* 16550 UARTs */
4238 +#ifdef __MIPSEB__
4239 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
4240 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
4241 +#else
4242 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
4243 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
4244 +#endif
4245 +
4246 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
4247 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
4248 +
4249 +#define IDT_CLOCK_MULT 2
4250 +
4251 +/* NVRAM */
4252 +#define NVRAM_BASE 0x12000000
4253 +#define NVRAM_ENVSIZE_OFF 4
4254 +#define NVRAM_ENVSTART_OFF 0x40
4255 +
4256 +/* LCD 4-digit display */
4257 +#define LCD_CLEAR 0x14000400
4258 +#define LCD_DIGIT0 0x1400000f
4259 +#define LCD_DIGIT1 0x14000008
4260 +#define LCD_DIGIT2 0x14000007
4261 +#define LCD_DIGIT3 0x14000003
4262 +
4263 +/* Interrupts routed on 79S334A board (see rc32334.h) */
4264 +#define RC32334_SCC8530_IRQ 2
4265 +#define RC32334_PCI_INTA_IRQ 3
4266 +#define RC32334_PCI_INTB_IRQ 4
4267 +#define RC32334_PCI_INTC_IRQ 6
4268 +#define RC32334_PCI_INTD_IRQ 7
4269 +
4270 +#define RAM_SIZE (32*1024*1024)
4271 +
4272 +#endif // __IDT_RC32334_H__
4273 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
4274 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
4275 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-01-10 00:32:33.000000000 +0100
4276 @@ -0,0 +1,206 @@
4277 +/**************************************************************************
4278 + *
4279 + * BRIEF MODULE DESCRIPTION
4280 + * DMA controller defines on IDT RC32355
4281 + *
4282 + * Copyright 2004 IDT Inc.
4283 + * Author: Integrated Device Technology Inc. rischelp@idt.com
4284 + *
4285 + *
4286 + * This program is free software; you can redistribute it and/or modify it
4287 + * under the terms of the GNU General Public License as published by the
4288 + * Free Software Foundation; either version 2 of the License, or (at your
4289 + * option) any later version.
4290 + *
4291 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4292 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4293 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4294 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4295 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4296 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4297 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4298 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4299 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4300 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4301 + *
4302 + * You should have received a copy of the GNU General Public License along
4303 + * with this program; if not, write to the Free Software Foundation, Inc.,
4304 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4305 + *
4306 + *
4307 + * May 2004 rkt
4308 + * Initial Release
4309 + *
4310 + **************************************************************************
4311 + */
4312 +
4313 +#ifndef BANYAN_DMA_H
4314 +#define BANYAN_DMA_H
4315 +#include <asm/idt-boards/rc32300/rc32300.h>
4316 +
4317 +/*
4318 + * An image of one RC32355 dma channel registers
4319 + */
4320 +typedef struct {
4321 + u32 dmac;
4322 + u32 dmas;
4323 + u32 dmasm;
4324 + u32 dmadptr;
4325 + u32 dmandptr;
4326 +} rc32355_dma_ch_t;
4327 +
4328 +/*
4329 + * An image of all RC32355 dma channel registers
4330 + */
4331 +typedef struct {
4332 + rc32355_dma_ch_t ch[16];
4333 +} rc32355_dma_regs_t;
4334 +
4335 +
4336 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
4337 +
4338 +
4339 +/* DMAC register layout */
4340 +
4341 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
4342 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
4343 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
4344 +
4345 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
4346 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
4347 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
4348 +
4349 +/* DMAS and DMASM register layout */
4350 +
4351 +#define DMAS_F 0x01 /* Finished */
4352 +#define DMAS_D 0x02 /* Done */
4353 +#define DMAS_C 0x04 /* Chain */
4354 +#define DMAS_E 0x08 /* Error */
4355 +#define DMAS_H 0x10 /* Halt */
4356 +
4357 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
4358 +#define DMA_HALT_TIMEOUT 500
4359 +
4360 +
4361 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
4362 +{
4363 + int timeout=1;
4364 +
4365 + if (local_readl(&ch->dmac) & DMAC_RUN) {
4366 + local_writel(0, &ch->dmac);
4367 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4368 + if (local_readl(&ch->dmas) & DMAS_H) {
4369 + local_writel(0, &ch->dmas);
4370 + break;
4371 + }
4372 + }
4373 + }
4374 +
4375 + return timeout ? 0 : 1;
4376 +}
4377 +
4378 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
4379 +{
4380 + local_writel(0, &ch->dmandptr);
4381 + local_writel(dma_addr, &ch->dmadptr);
4382 +}
4383 +
4384 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
4385 +{
4386 + local_writel(dma_addr, &ch->dmandptr);
4387 +}
4388 +
4389 +
4390 +/* The following can be used to describe DMA channels 0 to 15, and the */
4391 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
4392 +
4393 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
4394 +
4395 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
4396 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
4397 +
4398 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
4399 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
4400 +
4401 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
4402 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
4403 +
4404 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
4405 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
4406 +
4407 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
4408 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
4409 +#define DMA_DEV_ATMVCC(entry) 0
4410 +
4411 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
4412 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
4413 +
4414 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
4415 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
4416 +
4417 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
4418 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
4419 +
4420 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
4421 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
4422 +
4423 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
4424 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
4425 +
4426 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
4427 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
4428 +
4429 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
4430 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
4431 +
4432 +#define DMA_CHAN_USBIN 13 /* USB input */
4433 +#define DMA_DEV_USBIN 0 /* USB input */
4434 +
4435 +#define DMA_CHAN_USBOUT 14 /* USB output */
4436 +#define DMA_DEV_USBOUT 0 /* USB output */
4437 +
4438 +#define DMA_CHAN_EXTERN 15 /* External DMA */
4439 +#define DMA_DEV_EXTERN 0 /* External DMA */
4440 +
4441 +/*
4442 + * An RC32355 dma descriptor in system memory
4443 + */
4444 +typedef struct {
4445 + u32 cmdstat; /* control and status */
4446 + u32 curr_addr; /* current address of data */
4447 + u32 devcs; /* peripheral-specific control and status */
4448 + u32 link; /* link to next descriptor */
4449 +} rc32355_dma_desc_t;
4450 +
4451 +/* Values for the descriptor cmdstat word */
4452 +
4453 +#define DMADESC_F 0x80000000u /* Finished bit */
4454 +#define DMADESC_D 0x40000000u /* Done bit */
4455 +#define DMADESC_T 0x20000000u /* Terminated bit */
4456 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
4457 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
4458 +#define DMADESC_COD 0x04000000u /* Chain On Done */
4459 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
4460 +
4461 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
4462 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
4463 +
4464 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
4465 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
4466 +
4467 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
4468 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
4469 +
4470 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
4471 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
4472 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
4473 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
4474 +
4475 +#define DMA_DEVCMD(devcmd) \
4476 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
4477 +#define DMA_DS(ds) \
4478 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
4479 +#define DMA_COUNT(count) \
4480 + ((count) & DMADESC_COUNT_MASK)
4481 +
4482 +#endif /* RC32355_DMA_H */
4483 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
4484 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
4485 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-01-10 00:32:33.000000000 +0100
4486 @@ -0,0 +1,442 @@
4487 +/**************************************************************************
4488 + *
4489 + * BRIEF MODULE DESCRIPTION
4490 + * Ethernet registers on IDT RC32355
4491 + *
4492 + * Copyright 2004 IDT Inc.
4493 + * Author: Integrated Device Technology Inc. rischelp@idt.com
4494 + *
4495 + *
4496 + * This program is free software; you can redistribute it and/or modify it
4497 + * under the terms of the GNU General Public License as published by the
4498 + * Free Software Foundation; either version 2 of the License, or (at your
4499 + * option) any later version.
4500 + *
4501 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4502 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4503 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4504 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4505 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4506 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4507 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4508 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4509 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4510 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4511 + *
4512 + * You should have received a copy of the GNU General Public License along
4513 + * with this program; if not, write to the Free Software Foundation, Inc.,
4514 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4515 + *
4516 + *
4517 + * May 2004 rkt
4518 + * Initial Release
4519 + *
4520 + **************************************************************************
4521 + */
4522 +
4523 +
4524 +#ifndef RC32355_ETHER_H
4525 +#define RC32355_ETHER_H
4526 +
4527 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
4528 +
4529 +/*
4530 + * A partial image of the RC32355 ethernet registers
4531 + */
4532 +typedef struct {
4533 + u32 ethintfc;
4534 + u32 ethfifott;
4535 + u32 etharc;
4536 + u32 ethhash0;
4537 + u32 ethhash1;
4538 + u32 ethfifost;
4539 + u32 ethfifos;
4540 + u32 ethodeops;
4541 + u32 ethis;
4542 + u32 ethos;
4543 + u32 ethmcp;
4544 + u32 _u1;
4545 + u32 ethid;
4546 + u32 _u2;
4547 + u32 _u3;
4548 + u32 _u4;
4549 + u32 ethod;
4550 + u32 _u5;
4551 + u32 _u6;
4552 + u32 _u7;
4553 + u32 ethodeop;
4554 + u32 _u8[43];
4555 + u32 ethsal0;
4556 + u32 ethsah0;
4557 + u32 ethsal1;
4558 + u32 ethsah1;
4559 + u32 ethsal2;
4560 + u32 ethsah2;
4561 + u32 ethsal3;
4562 + u32 ethsah3;
4563 + u32 ethrbc;
4564 + u32 ethrpc;
4565 + u32 ethrupc;
4566 + u32 ethrfc;
4567 + u32 ethtbc;
4568 + u32 ethgpf;
4569 + u32 _u9[50];
4570 + u32 ethmac1;
4571 + u32 ethmac2;
4572 + u32 ethipgt;
4573 + u32 ethipgr;
4574 + u32 ethclrt;
4575 + u32 ethmaxf;
4576 + u32 _u10;
4577 + u32 ethmtest;
4578 + u32 miimcfg;
4579 + u32 miimcmd;
4580 + u32 miimaddr;
4581 + u32 miimwtd;
4582 + u32 miimrdd;
4583 + u32 miimind;
4584 + u32 _u11;
4585 + u32 _u12;
4586 + u32 ethcfsa0;
4587 + u32 ethcfsa1;
4588 + u32 ethcfsa2;
4589 +} rc32355_eth_regs_t;
4590 +
4591 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
4592 +
4593 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
4594 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
4595 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
4596 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
4597 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
4598 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
4599 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
4600 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
4601 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
4602 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
4603 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
4604 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
4605 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
4606 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
4607 +
4608 +/* for n in { 0, 1, 2, 3 } */
4609 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
4610 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
4611 +
4612 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
4613 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
4614 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
4615 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
4616 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
4617 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
4618 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
4619 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
4620 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
4621 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
4622 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
4623 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
4624 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
4625 +
4626 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
4627 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
4628 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
4629 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
4630 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
4631 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
4632 +
4633 +/* for n in { 0, 1, 2 } */
4634 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
4635 +
4636 +
4637 +/*
4638 + * Register Interpretations follow
4639 + */
4640 +
4641 +/******************************************************************************
4642 + * ETHINTFC register
4643 + *****************************************************************************/
4644 +
4645 +#define ETHERINTFC_EN (1<<0)
4646 +#define ETHERINTFC_ITS (1<<1)
4647 +#define ETHERINTFC_RES (1<<2)
4648 +#define ETHERINTFC_RIP (1<<2)
4649 +#define ETHERINTFC_JAM (1<<3)
4650 +
4651 +/******************************************************************************
4652 + * ETHFIFOTT register
4653 + *****************************************************************************/
4654 +
4655 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
4656 +
4657 +/******************************************************************************
4658 + * ETHARC register
4659 + *****************************************************************************/
4660 +
4661 +#define ETHERARC_PRO (1<<0)
4662 +#define ETHERARC_AM (1<<1)
4663 +#define ETHERARC_AFM (1<<2)
4664 +#define ETHERARC_AB (1<<3)
4665 +
4666 +/******************************************************************************
4667 + * ETHHASH registers
4668 + *****************************************************************************/
4669 +
4670 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
4671 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
4672 +
4673 +/******************************************************************************
4674 + * ETHSA registers
4675 + *****************************************************************************/
4676 +
4677 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
4678 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
4679 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
4680 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
4681 +#define ETHERSAH0(v) (((v)&0xff)<<0)
4682 +#define ETHERSAH1(v) (((v)&0xff)<<0)
4683 +#define ETHERSAH2(v) (((v)&0xff)<<0)
4684 +#define ETHERSAH3(v) (((v)&0xff)<<0)
4685 +
4686 +/******************************************************************************
4687 + * ETHFIFOST register
4688 + *****************************************************************************/
4689 +
4690 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
4691 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
4692 +
4693 +/******************************************************************************
4694 + * ETHFIFOS register
4695 + *****************************************************************************/
4696 +
4697 +#define ETHERFIFOS_IR (1<<0)
4698 +#define ETHERFIFOS_OR (1<<1)
4699 +#define ETHERFIFOS_OVR (1<<2)
4700 +#define ETHERFIFOS_UND (1<<3)
4701 +
4702 +/******************************************************************************
4703 + * DATA registers
4704 + *****************************************************************************/
4705 +
4706 +#define ETHERID(v) (((v)&0xffff)<<0)
4707 +#define ETHEROD(v) (((v)&0xffff)<<0)
4708 +
4709 +/******************************************************************************
4710 + * ETHODEOPS register
4711 + *****************************************************************************/
4712 +
4713 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
4714 +
4715 +/******************************************************************************
4716 + * ETHODEOP register
4717 + *****************************************************************************/
4718 +
4719 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
4720 +
4721 +/******************************************************************************
4722 + * ETHIS register
4723 + *****************************************************************************/
4724 +
4725 +#define ETHERIS_EOP (1<<0)
4726 +#define ETHERIS_ROK (1<<2)
4727 +#define ETHERIS_FM (1<<3)
4728 +#define ETHERIS_MP (1<<4)
4729 +#define ETHERIS_BP (1<<5)
4730 +#define ETHERIS_VLT (1<<6)
4731 +#define ETHERIS_CF (1<<7)
4732 +#define ETHERIS_OVR (1<<8)
4733 +#define ETHERIS_CRC (1<<9)
4734 +#define ETHERIS_CV (1<<10)
4735 +#define ETHERIS_DB (1<<11)
4736 +#define ETHERIS_LE (1<<12)
4737 +#define ETHERIS_LOR (1<<13)
4738 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
4739 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
4740 +
4741 +/******************************************************************************
4742 + * ETHOS register
4743 + *****************************************************************************/
4744 +
4745 +#define ETHEROS_T (1<<0)
4746 +#define ETHEROS_TOK (1<<6)
4747 +#define ETHEROS_MP (1<<7)
4748 +#define ETHEROS_BP (1<<8)
4749 +#define ETHEROS_UND (1<<9)
4750 +#define ETHEROS_OF (1<<10)
4751 +#define ETHEROS_ED (1<<11)
4752 +#define ETHEROS_EC (1<<12)
4753 +#define ETHEROS_LC (1<<13)
4754 +#define ETHEROS_TD (1<<14)
4755 +#define ETHEROS_CRC (1<<15)
4756 +#define ETHEROS_LE (1<<16)
4757 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
4758 +#define ETHEROS_PFD (1<<21)
4759 +
4760 +/******************************************************************************
4761 + * Statistics registers
4762 + *****************************************************************************/
4763 +
4764 +#define ETHERRBC(v) (((v)&0xffff)<<0)
4765 +#define ETHERRPC(v) (((v)&0xffff)<<0)
4766 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
4767 +#define ETHERRFC(v) (((v)&0xffff)<<0)
4768 +#define ETHERTBC(v) (((v)&0xffff)<<0)
4769 +
4770 +/******************************************************************************
4771 + * ETHGPF register
4772 + *****************************************************************************/
4773 +
4774 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
4775 +
4776 +/******************************************************************************
4777 + * MAC registers
4778 + *****************************************************************************/
4779 +//ETHMAC1
4780 +#define ETHERMAC1_RE (1<<0)
4781 +#define ETHERMAC1_PAF (1<<1)
4782 +#define ETHERMAC1_RFC (1<<2)
4783 +#define ETHERMAC1_TFC (1<<3)
4784 +#define ETHERMAC1_LB (1<<4)
4785 +#define ETHERMAC1_MR (1<<15)
4786 +
4787 +//ETHMAC2
4788 +#define ETHERMAC2_FD (1<<0)
4789 +#define ETHERMAC2_FLC (1<<1)
4790 +#define ETHERMAC2_HFE (1<<2)
4791 +#define ETHERMAC2_DC (1<<3)
4792 +#define ETHERMAC2_CEN (1<<4)
4793 +#define ETHERMAC2_PE (1<<5)
4794 +#define ETHERMAC2_VPE (1<<6)
4795 +#define ETHERMAC2_APE (1<<7)
4796 +#define ETHERMAC2_PPE (1<<8)
4797 +#define ETHERMAC2_LPE (1<<9)
4798 +#define ETHERMAC2_NB (1<<12)
4799 +#define ETHERMAC2_BP (1<<13)
4800 +#define ETHERMAC2_ED (1<<14)
4801 +
4802 +//ETHIPGT
4803 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
4804 +
4805 +//ETHIPGR
4806 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
4807 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
4808 +
4809 +//ETHCLRT
4810 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
4811 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
4812 +
4813 +//ETHMAXF
4814 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
4815 +
4816 +//ETHMTEST
4817 +#define ETHERMTEST_TB (1<<2)
4818 +
4819 +//ETHMCP
4820 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
4821 +
4822 +//MIIMCFG
4823 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
4824 +#define ETHERMIIMCFG_R (1<<15)
4825 +
4826 +//MIIMCMD
4827 +#define ETHERMIIMCMD_RD (1<<0)
4828 +#define ETHERMIIMCMD_SCN (1<<1)
4829 +
4830 +//MIIMADDR
4831 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
4832 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
4833 +
4834 +//MIIMWTD
4835 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
4836 +
4837 +//MIIMRDD
4838 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
4839 +
4840 +//MIIMIND
4841 +#define ETHERMIIMIND_BSY (1<<0)
4842 +#define ETHERMIIMIND_SCN (1<<1)
4843 +#define ETHERMIIMIND_NV (1<<2)
4844 +
4845 +//DMA DEVCS IN
4846 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
4847 +#define ETHERDMA_IN_CES (1<<14)
4848 +#define ETHERDMA_IN_LOR (1<<13)
4849 +#define ETHERDMA_IN_LE (1<<12)
4850 +#define ETHERDMA_IN_DB (1<<11)
4851 +#define ETHERDMA_IN_CV (1<<10)
4852 +#define ETHERDMA_IN_CRC (1<<9)
4853 +#define ETHERDMA_IN_OVR (1<<8)
4854 +#define ETHERDMA_IN_CF (1<<7)
4855 +#define ETHERDMA_IN_VLT (1<<6)
4856 +#define ETHERDMA_IN_BP (1<<5)
4857 +#define ETHERDMA_IN_MP (1<<4)
4858 +#define ETHERDMA_IN_FM (1<<3)
4859 +#define ETHERDMA_IN_ROK (1<<2)
4860 +#define ETHERDMA_IN_LD (1<<1)
4861 +#define ETHERDMA_IN_FD (1<<0)
4862 +
4863 +//DMA DEVCS OUT
4864 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
4865 +#define ETHERDMA_OUT_CNT 0x001e0000
4866 +#define ETHERDMA_OUT_SHFT 17
4867 +#define ETHERDMA_OUT_LE (1<<16)
4868 +
4869 +#define ETHERDMA_OUT_CRC (1<<15)
4870 +#define ETHERDMA_OUT_TD (1<<14)
4871 +#define ETHERDMA_OUT_LC (1<<13)
4872 +#define ETHERDMA_OUT_EC (1<<12)
4873 +#define ETHERDMA_OUT_ED (1<<11)
4874 +#define ETHERDMA_OUT_OF (1<<10)
4875 +#define ETHERDMA_OUT_UND (1<<9)
4876 +#define ETHERDMA_OUT_BP (1<<8)
4877 +#define ETHERDMA_OUT_MP (1<<7)
4878 +#define ETHERDMA_OUT_TOK (1<<6)
4879 +#define ETHERDMA_OUT_HEN (1<<5)
4880 +#define ETHERDMA_OUT_CEN (1<<4)
4881 +#define ETHERDMA_OUT_PEN (1<<3)
4882 +#define ETHERDMA_OUT_OEN (1<<2)
4883 +#define ETHERDMA_OUT_LD (1<<1)
4884 +#define ETHERDMA_OUT_FD (1<<0)
4885 +
4886 +#define RCV_ERRS \
4887 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
4888 +#define TX_ERRS \
4889 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
4890 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
4891 +
4892 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
4893 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
4894 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
4895 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
4896 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
4897 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
4898 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
4899 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
4900 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
4901 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
4902 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
4903 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
4904 + Range */
4905 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
4906 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
4907 + received packet */
4908 +
4909 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
4910 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
4911 +
4912 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
4913 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
4914 + Underflow */
4915 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
4916 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
4917 + deferral */
4918 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
4919 + collisions */
4920 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
4921 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
4922 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
4923 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
4924 +
4925 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
4926 +
4927 +#endif /* RC32355_ETHER_H */
4928 +
4929 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h
4930 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
4931 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-01-10 00:32:33.000000000 +0100
4932 @@ -0,0 +1,177 @@
4933 +/**************************************************************************
4934 + *
4935 + * BRIEF MODULE DESCRIPTION
4936 + * Definitions for IDT RC32355 CPU.
4937 + *
4938 + * Copyright 2004 IDT Inc.
4939 + * Author: Integrated Device Technology Inc. rischelp@idt.com
4940 + *
4941 + *
4942 + * This program is free software; you can redistribute it and/or modify it
4943 + * under the terms of the GNU General Public License as published by the
4944 + * Free Software Foundation; either version 2 of the License, or (at your
4945 + * option) any later version.
4946 + *
4947 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4948 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4949 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4950 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4951 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4952 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4953 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4954 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4955 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4956 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4957 + *
4958 + * You should have received a copy of the GNU General Public License along
4959 + * with this program; if not, write to the Free Software Foundation, Inc.,
4960 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4961 + *
4962 + *
4963 + * May 2004 rkt
4964 + * Initial Release
4965 + *
4966 + **************************************************************************
4967 + */
4968 +
4969 +
4970 +#ifndef _RC32355_H_
4971 +#define _RC32355_H_
4972 +
4973 +#include <linux/delay.h>
4974 +#include <asm/io.h>
4975 +
4976 +/* Base address of internal registers */
4977 +#define RC32355_REG_BASE 0x18000000
4978 +
4979 +/* System ID Registers */
4980 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
4981 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
4982 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
4983 +
4984 +/* Reset Controller */
4985 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
4986 +
4987 +/* Device Controller */
4988 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
4989 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
4990 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
4991 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
4992 +#define DEV_REG_OFFSET 0x10
4993 +
4994 +/* SDRAM Controller */
4995 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
4996 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
4997 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
4998 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
4999 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
5000 +
5001 +/* Bus Arbiter */
5002 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
5003 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
5004 +
5005 +/* Counters/Timers */
5006 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
5007 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
5008 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
5009 +#define TIMER_REG_OFFSET 0x0C
5010 +
5011 +/* System Integrity */
5012 +
5013 +/* Interrupt Controller */
5014 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
5015 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
5016 +#define IC_GROUP_OFFSET 0x08
5017 +
5018 +#define NUM_INTR_GROUPS 5
5019 +/*
5020 + * The IRQ mapping is as follows:
5021 + *
5022 + * IRQ Mapped To
5023 + * --- -------------------
5024 + * 0 SW0 (IP0) SW0 intr
5025 + * 1 SW1 (IP1) SW1 intr
5026 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5027 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5028 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5029 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5030 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5031 + * 7 Int5 (IP7) CP0 Timer
5032 + *
5033 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5034 + * internally on the RC32355 is routed to the Expansion
5035 + * Interrupt Controller.
5036 + */
5037 +#define MIPS_CPU_TIMER_IRQ 7
5038 +
5039 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5040 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5041 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
5042 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
5043 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5044 +
5045 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
5046 +
5047 +/* DMA - see rc32355_dma.h for full list of registers */
5048 +
5049 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
5050 +#define DMA_CHAN_OFFSET 0x14
5051 +
5052 +/* GPIO Controller */
5053 +
5054 +/* TDM Bus */
5055 +
5056 +/* 16550 UARTs */
5057 +#ifdef __MIPSEB__
5058 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
5059 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
5060 +#else
5061 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
5062 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
5063 +#endif
5064 +
5065 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
5066 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
5067 +
5068 +/* ATM */
5069 +
5070 +/* Ethernet - see rc32355_eth.h for full list of registers */
5071 +
5072 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
5073 +
5074 +
5075 +#define IDT_CLOCK_MULT 2
5076 +
5077 +/* Memory map of 79EB355 board */
5078 +
5079 +/* DRAM */
5080 +#define RAM_BASE 0x00000000
5081 +#define RAM_SIZE (32*1024*1024)
5082 +
5083 +/* SRAM (device 1) */
5084 +#define SRAM_BASE 0x02000000
5085 +#define SRAM_SIZE 0x00100000
5086 +
5087 +/* FLASH (device 2) */
5088 +#define FLASH_BASE 0x0C000000
5089 +#define FLASH_SIZE 0x00C00000
5090 +
5091 +/* ATM PHY (device 4) */
5092 +#define ATM_PHY_BASE 0x14000000
5093 +
5094 +/* TDM switch (device 3) */
5095 +#define TDM_BASE 0x1A000000
5096 +
5097 +/* LCD panel (device 3) */
5098 +#define LCD_BASE 0x1A002000
5099 +
5100 +/* RTC (DS1511W) (device 3) */
5101 +#define RTC_BASE 0x1A004000
5102 +
5103 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
5104 +#define NVRAM_ADDR RTC_BASE + 0x10
5105 +#define NVRAM_DATA RTC_BASE + 0x13
5106 +#define NVRAM_ENVSIZE_OFF 4
5107 +#define NVRAM_ENVSTART_OFF 32
5108 +
5109 +#endif /* _RC32355_H_ */
5110 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
5111 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
5112 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-01-10 00:32:33.000000000 +0100
5113 @@ -0,0 +1,226 @@
5114 +/**************************************************************************
5115 + *
5116 + * BRIEF MODULE DESCRIPTION
5117 + * RC32365/336 DMA hardware abstraction.
5118 + *
5119 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5120 + *
5121 + * This program is free software; you can redistribute it and/or modify it
5122 + * under the terms of the GNU General Public License as published by the
5123 + * Free Software Foundation; either version 2 of the License, or (at your
5124 + * option) any later version.
5125 + *
5126 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5127 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5128 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5129 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5130 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5131 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5132 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5133 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5134 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5135 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5136 + *
5137 + * You should have received a copy of the GNU General Public License along
5138 + * with this program; if not, write to the Free Software Foundation, Inc.,
5139 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5140 + *
5141 + *
5142 + **************************************************************************
5143 + * May 2004 P. Sadik.
5144 + *
5145 + * Initial Release
5146 + *
5147 + *
5148 + *
5149 + **************************************************************************
5150 + */
5151 +
5152 +#ifndef __IDT_RC32365_DMA_H__
5153 +#define __IDT_RC32365_DMA_H__
5154 +
5155 +enum
5156 +{
5157 + DMA0_PhysicalAddress = 0x18038000,
5158 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5159 +
5160 + DMA0_VirtualAddress = 0xb8038000,
5161 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5162 +} ;
5163 +
5164 +/*
5165 + * DMA descriptor (in physical memory).
5166 + */
5167 +
5168 +typedef struct DMAD_s
5169 +{
5170 + u32 control ; // Control. use DMAD_*
5171 + u32 ca ; // Current Address.
5172 + u32 devcs ; // Device control and status.
5173 + u32 link ; // Next descriptor in chain.
5174 +} volatile *DMAD_t ;
5175 +
5176 +enum
5177 +{
5178 + DMAD_size = sizeof (struct DMAD_s),
5179 + DMAD_count_b = 0, // in DMAD_t -> control
5180 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5181 + DMAD_ds_b = 20, // in DMAD_t -> control
5182 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5183 + DMAD_ds_extToMem0_v = 0,
5184 + DMAD_ds_memToExt0_v = 1,
5185 + DMAD_ds_extToMem1_v = 0,
5186 + DMAD_ds_memToExt1_v = 1,
5187 + DMAD_ds_ethRcv0_v = 0,
5188 + DMAD_ds_ethXmt0_v = 0,
5189 + DMAD_ds_ethRcv1_v = 0,
5190 + DMAD_ds_ethXmt2_v = 0,
5191 + DMAD_ds_memToFifo_v = 0,
5192 + DMAD_ds_fifoToMem_v = 0,
5193 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
5194 + DMAD_ds_pciToMem_v = 0,
5195 + DMAD_ds_memToPci_v = 0,
5196 + DMAD_ds_securityInput_v = 0,
5197 + DMAD_ds_securityOutput_v = 0,
5198 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
5199 +
5200 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5201 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5202 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5203 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5204 + DMAD_devcmd_word_v = 2, //memory-to-memory
5205 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5206 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5207 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5208 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5209 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5210 + DMAD_cof_b = 25, // chain on finished
5211 + DMAD_cof_m = 0x02000000, //
5212 + DMAD_cod_b = 26, // chain on done
5213 + DMAD_cod_m = 0x04000000, //
5214 + DMAD_iof_b = 27, // interrupt on finished
5215 + DMAD_iof_m = 0x08000000, //
5216 + DMAD_iod_b = 28, // interrupt on done
5217 + DMAD_iod_m = 0x10000000, //
5218 + DMAD_t_b = 29, // terminated
5219 + DMAD_t_m = 0x20000000, //
5220 + DMAD_d_b = 30, // done
5221 + DMAD_d_m = 0x40000000, //
5222 + DMAD_f_b = 31, // finished
5223 + DMAD_f_m = 0x80000000, //
5224 +} ;
5225 +
5226 +/*
5227 + * DMA register (within Internal Register Map).
5228 + */
5229 +
5230 +struct DMA_Chan_s
5231 +{
5232 + u32 dmac ; // Control.
5233 + u32 dmas ; // Status.
5234 + u32 dmasm ; // Mask.
5235 + u32 dmadptr ; // Descriptor pointer.
5236 + u32 dmandptr ; // Next descriptor pointer.
5237 +};
5238 +
5239 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5240 +
5241 +//DMA_Channels use DMACH_count instead
5242 +
5243 +enum
5244 +{
5245 + DMAC_run_b = 0, //
5246 + DMAC_run_m = 0x00000001, //
5247 + DMAC_dm_b = 1, // done mask
5248 + DMAC_dm_m = 0x00000002, //
5249 + DMAC_mode_b = 2, //
5250 + DMAC_mode_m = 0x0000000c, //
5251 + DMAC_mode_auto_v = 0,
5252 + DMAC_mode_burst_v = 1,
5253 + DMAC_mode_transfer_v = 2, //usually used
5254 + DMAC_mode_reserved_v = 3,
5255 + DMAC_a_b = 4, //
5256 + DMAC_a_m = 0x00000010, //
5257 +
5258 + DMAS_f_b = 0, // finished (sticky)
5259 + DMAS_f_m = 0x00000001, //
5260 + DMAS_d_b = 1, // done (sticky)
5261 + DMAS_d_m = 0x00000002, //
5262 + DMAS_c_b = 2, // chain (sticky)
5263 + DMAS_c_m = 0x00000004, //
5264 + DMAS_e_b = 3, // error (sticky)
5265 + DMAS_e_m = 0x00000008, //
5266 + DMAS_h_b = 4, // halt (sticky)
5267 + DMAS_h_m = 0x00000010, //
5268 +
5269 + DMASM_f_b = 0, // finished (1=mask)
5270 + DMASM_f_m = 0x00000001, //
5271 + DMASM_d_b = 1, // done (1=mask)
5272 + DMASM_d_m = 0x00000002, //
5273 + DMASM_c_b = 2, // chain (1=mask)
5274 + DMASM_c_m = 0x00000004, //
5275 + DMASM_e_b = 3, // error (1=mask)
5276 + DMASM_e_m = 0x00000008, //
5277 + DMASM_h_b = 4, // halt (1=mask)
5278 + DMASM_h_m = 0x00000010, //
5279 +} ;
5280 +
5281 +/*
5282 + * DMA channel definitions
5283 + */
5284 +
5285 +enum
5286 +{
5287 + DMACH_ethRcv0 = 0,
5288 + DMACH_ethXmt0 = 1,
5289 + DMACH_ethRcv1 = 2,
5290 + DMACH_ethXmt2 = 3,
5291 + DMACH_pciToMem = 4,
5292 + DMACH_memToPci = 5,
5293 + DMACH_securityInput = 6,
5294 + DMACH_securityOutput = 7,
5295 + DMACH_rng = 8,
5296 +
5297 + DMACH_count //must be last
5298 +};
5299 +
5300 +
5301 +typedef struct DMAC_s
5302 +{
5303 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
5304 +} volatile *DMA_t ;
5305 +
5306 +
5307 +/*
5308 + * External DMA parameters
5309 +*/
5310 +
5311 +enum
5312 +{
5313 + DMADEVCMD_ts_b = 0, // ts field in devcmd
5314 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
5315 + DMADEVCMD_ts_byte_v = 0,
5316 + DMADEVCMD_ts_halfword_v = 1,
5317 + DMADEVCMD_ts_word_v = 2,
5318 + DMADEVCMD_ts_2word_v = 3,
5319 + DMADEVCMD_ts_4word_v = 4,
5320 + DMADEVCMD_ts_6word_v = 5,
5321 + DMADEVCMD_ts_8word_v = 6,
5322 + DMADEVCMD_ts_16word_v = 7
5323 +};
5324 +
5325 +
5326 +#if 1 // aws - Compatibility.
5327 +# define EXTDMA_ts_b DMADEVCMD_ts_b
5328 +# define EXTDMA_ts_m DMADEVCMD_ts_m
5329 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
5330 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
5331 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
5332 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
5333 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
5334 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
5335 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
5336 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
5337 +#endif // aws - Compatibility.
5338 +
5339 +#endif // __IDT_RC32365_DMA_H__
5340 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
5341 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
5342 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-01-10 00:32:33.000000000 +0100
5343 @@ -0,0 +1,86 @@
5344 +/**************************************************************************
5345 + *
5346 + * BRIEF MODULE DESCRIPTION
5347 + * RC32365/336 DMA interface routines.
5348 + *
5349 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5350 + *
5351 + * This program is free software; you can redistribute it and/or modify it
5352 + * under the terms of the GNU General Public License as published by the
5353 + * Free Software Foundation; either version 2 of the License, or (at your
5354 + * option) any later version.
5355 + *
5356 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5357 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5358 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5359 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5360 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5361 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5362 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5363 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5364 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5365 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5366 + *
5367 + * You should have received a copy of the GNU General Public License along
5368 + * with this program; if not, write to the Free Software Foundation, Inc.,
5369 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5370 + *
5371 + *
5372 + **************************************************************************
5373 + * May 2004 P. Sadik.
5374 + *
5375 + * Initial Release
5376 + *
5377 + *
5378 + *
5379 + **************************************************************************
5380 + */
5381 +
5382 +#ifndef __IDT_RC32365_DMA_V_H__
5383 +#define __IDT_RC32365_DMA_V_H__
5384 +
5385 +
5386 +#include <asm/idt-boards/rc32300/rc32300.h>
5387 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
5388 +#include <asm/idt-boards/rc32300/rc32365.h>
5389 +
5390 +#define DMA_CHAN_OFFSET 0x14
5391 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
5392 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
5393 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
5394 +
5395 +#define DMA_COUNT(count) \
5396 + ((count) & DMAD_count_m)
5397 +
5398 +#define DMA_HALT_TIMEOUT 500
5399 +
5400 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
5401 +{
5402 + int timeout=1;
5403 + if (local_readl(&ch->dmac) & DMAC_run_m) {
5404 + local_writel(0, &ch->dmac);
5405 +
5406 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
5407 + if (local_readl(&ch->dmas) & DMAS_h_m) {
5408 + local_writel(0, &ch->dmas);
5409 + break;
5410 + }
5411 + }
5412 +
5413 + }
5414 +
5415 + return timeout ? 0 : 1;
5416 +}
5417 +
5418 +
5419 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
5420 +{
5421 + local_writel(0, &ch->dmandptr);
5422 + local_writel(dma_addr, &ch->dmadptr);
5423 +}
5424 +
5425 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
5426 +{
5427 + local_writel(dma_addr, &ch->dmandptr);
5428 +}
5429 +#endif //__IDT_RC32365_DMA_V_H__
5430 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
5431 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
5432 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-01-10 00:32:33.000000000 +0100
5433 @@ -0,0 +1,344 @@
5434 +/**************************************************************************
5435 + *
5436 + * BRIEF MODULE DESCRIPTION
5437 + * RC32365/336 Ethernet hardware abstraction.
5438 + *
5439 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5440 + *
5441 + * This program is free software; you can redistribute it and/or modify it
5442 + * under the terms of the GNU General Public License as published by the
5443 + * Free Software Foundation; either version 2 of the License, or (at your
5444 + * option) any later version.
5445 + *
5446 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5447 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5448 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5449 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5450 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5451 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5452 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5453 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5454 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5455 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5456 + *
5457 + * You should have received a copy of the GNU General Public License along
5458 + * with this program; if not, write to the Free Software Foundation, Inc.,
5459 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5460 + *
5461 + *
5462 + **************************************************************************
5463 + * May 2004 P. Sadik.
5464 + *
5465 + * Initial Release
5466 + *
5467 + *
5468 + *
5469 + **************************************************************************
5470 + */
5471 +
5472 +#ifndef __IDT_RC32365_ETH_H__
5473 +#define __IDT_RC32365_ETH_H__
5474 +
5475 +enum
5476 +{
5477 + ETH0_PhysicalAddress = 0x18058000,
5478 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
5479 + ETH0_VirtualAddress = 0xb8058000,
5480 +
5481 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
5482 +
5483 + ETH1_PhysicalAddress = 0x18060000,
5484 + ETH1_VirtualAddress = 0xb8060000, // Default
5485 +} ;
5486 +
5487 +typedef struct
5488 +{
5489 + u32 ethintfc ;
5490 + u32 ethfifott ;
5491 + u32 etharc ;
5492 + u32 ethhash0 ;
5493 + u32 ethhash1 ;
5494 + u32 ethu0 [4] ; // Reserved.
5495 + u32 ethpfs ;
5496 + u32 ethmcp ;
5497 + u32 eth_u1 [10] ; // Reserved.
5498 + u32 ethspare ;
5499 + u32 eth_u2 [42] ; // Reserved.
5500 + u32 ethsal0 ;
5501 + u32 ethsah0 ;
5502 + u32 ethsal1 ;
5503 + u32 ethsah1 ;
5504 + u32 ethsal2 ;
5505 + u32 ethsah2 ;
5506 + u32 ethsal3 ;
5507 + u32 ethsah3 ;
5508 + u32 ethrbc ;
5509 + u32 ethrpc ;
5510 + u32 ethrupc ;
5511 + u32 ethrfc ;
5512 + u32 ethtbc ;
5513 + u32 ethgpf ;
5514 + u32 eth_u9 [50] ; // Reserved.
5515 + u32 ethmac1 ;
5516 + u32 ethmac2 ;
5517 + u32 ethipgt ;
5518 + u32 ethipgr ;
5519 + u32 ethclrt ;
5520 + u32 ethmaxf ;
5521 + u32 eth_u10 ; // Reserved.
5522 + u32 ethmtest ;
5523 + u32 miimcfg ;
5524 + u32 miimcmd ;
5525 + u32 miimaddr ;
5526 + u32 miimwtd ;
5527 + u32 miimrdd ;
5528 + u32 miimind ;
5529 + u32 eth_u11 ; // Reserved.
5530 + u32 eth_u12 ; // Reserved.
5531 + u32 ethcfsa0 ;
5532 + u32 ethcfsa1 ;
5533 + u32 ethcfsa2 ;
5534 +} volatile *ETH_t;
5535 +
5536 +enum
5537 +{
5538 + ETHINTFC_en_b = 0,
5539 + ETHINTFC_en_m = 0x00000001,
5540 + ETHINTFC_its_b = 1,
5541 + ETHINTFC_its_m = 0x00000002,
5542 + ETHINTFC_rip_b = 2,
5543 + ETHINTFC_rip_m = 0x00000004,
5544 + ETHINTFC_jam_b = 3,
5545 + ETHINTFC_jam_m = 0x00000008,
5546 + ETHINTFC_ovr_b = 4,
5547 + ETHINTFC_ovr_m = 0x00000010,
5548 + ETHINTFC_und_b = 5,
5549 + ETHINTFC_und_m = 0x00000020,
5550 +
5551 + ETHFIFOTT_tth_b = 0,
5552 + ETHFIFOTT_tth_m = 0x0000007f,
5553 +
5554 + ETHARC_pro_b = 0,
5555 + ETHARC_pro_m = 0x00000001,
5556 + ETHARC_am_b = 1,
5557 + ETHARC_am_m = 0x00000002,
5558 + ETHARC_afm_b = 2,
5559 + ETHARC_afm_m = 0x00000004,
5560 + ETHARC_ab_b = 3,
5561 + ETHARC_ab_m = 0x00000008,
5562 +
5563 + ETHSAL_byte5_b = 0,
5564 + ETHSAL_byte5_m = 0x000000ff,
5565 + ETHSAL_byte4_b = 8,
5566 + ETHSAL_byte4_m = 0x0000ff00,
5567 + ETHSAL_byte3_b = 16,
5568 + ETHSAL_byte3_m = 0x00ff0000,
5569 + ETHSAL_byte2_b = 24,
5570 + ETHSAL_byte2_m = 0xff000000,
5571 +
5572 + ETHSAH_byte1_b = 0,
5573 + ETHSAH_byte1_m = 0x000000ff,
5574 + ETHSAH_byte0_b = 8,
5575 + ETHSAH_byte0_m = 0x0000ff00,
5576 +
5577 + ETHGPF_ptv_b = 0,
5578 + ETHGPF_ptv_m = 0x0000ffff,
5579 +
5580 + ETHPFS_pfd_b = 0,
5581 + ETHPFS_pfd_m = 0x00000001,
5582 +
5583 + ETHCFSA0_cfsa4_b = 0,
5584 + ETHCFSA0_cfsa4_m = 0x000000ff,
5585 + ETHCFSA0_cfsa5_b = 8,
5586 + ETHCFSA0_cfsa5_m = 0x0000ff00,
5587 +
5588 + ETHCFSA1_cfsa2_b = 0,
5589 + ETHCFSA1_cfsa2_m = 0x000000ff,
5590 + ETHCFSA1_cfsa3_b = 8,
5591 + ETHCFSA1_cfsa3_m = 0x0000ff00,
5592 +
5593 + ETHCFSA2_cfsa0_b = 0,
5594 + ETHCFSA2_cfsa0_m = 0x000000ff,
5595 + ETHCFSA2_cfsa1_b = 8,
5596 + ETHCFSA2_cfsa1_m = 0x0000ff00,
5597 +
5598 + ETHMAC1_re_b = 0,
5599 + ETHMAC1_re_m = 0x00000001,
5600 + ETHMAC1_paf_b = 1,
5601 + ETHMAC1_paf_m = 0x00000002,
5602 + ETHMAC1_rfc_b = 2,
5603 + ETHMAC1_rfc_m = 0x00000004,
5604 + ETHMAC1_tfc_b = 3,
5605 + ETHMAC1_tfc_m = 0x00000008,
5606 + ETHMAC1_lb_b = 4,
5607 + ETHMAC1_lb_m = 0x00000010,
5608 + ETHMAC1_mr_b = 31,
5609 + ETHMAC1_mr_m = 0x80000000,
5610 +
5611 + ETHMAC2_fd_b = 0,
5612 + ETHMAC2_fd_m = 0x00000001,
5613 + ETHMAC2_flc_b = 1,
5614 + ETHMAC2_flc_m = 0x00000002,
5615 + ETHMAC2_hfe_b = 2,
5616 + ETHMAC2_hfe_m = 0x00000004,
5617 + ETHMAC2_dc_b = 3,
5618 + ETHMAC2_dc_m = 0x00000008,
5619 + ETHMAC2_cen_b = 4,
5620 + ETHMAC2_cen_m = 0x00000010,
5621 + ETHMAC2_pe_b = 5,
5622 + ETHMAC2_pe_m = 0x00000020,
5623 + ETHMAC2_vpe_b = 6,
5624 + ETHMAC2_vpe_m = 0x00000040,
5625 + ETHMAC2_ape_b = 7,
5626 + ETHMAC2_ape_m = 0x00000080,
5627 + ETHMAC2_ppe_b = 8,
5628 + ETHMAC2_ppe_m = 0x00000100,
5629 + ETHMAC2_lpe_b = 9,
5630 + ETHMAC2_lpe_m = 0x00000200,
5631 + ETHMAC2_nb_b = 12,
5632 + ETHMAC2_nb_m = 0x00001000,
5633 + ETHMAC2_bp_b = 13,
5634 + ETHMAC2_bp_m = 0x00002000,
5635 + ETHMAC2_ed_b = 14,
5636 + ETHMAC2_ed_m = 0x00004000,
5637 +
5638 + ETHIPGT_ipgt_b = 0,
5639 + ETHIPGT_ipgt_m = 0x0000007f,
5640 +
5641 + ETHIPGR_ipgr2_b = 0,
5642 + ETHIPGR_ipgr2_m = 0x0000007f,
5643 + ETHIPGR_ipgr1_b = 8,
5644 + ETHIPGR_ipgr1_m = 0x00007f00,
5645 +
5646 + ETHCLRT_maxret_b = 0,
5647 + ETHCLRT_maxret_m = 0x0000000f,
5648 + ETHCLRT_colwin_b = 8,
5649 + ETHCLRT_colwin_m = 0x00003f00,
5650 +
5651 + ETHMAXF_maxf_b = 0,
5652 + ETHMAXF_maxf_m = 0x0000ffff,
5653 +
5654 + ETHMTEST_tb_b = 2,
5655 + ETHMTEST_tb_m = 0x00000004,
5656 +
5657 + ETHMCP_div_b = 0,
5658 + ETHMCP_div_m = 0x000000ff,
5659 +
5660 + MIIMCFG_rsv_b = 0,
5661 + MIIMCFG_rsv_m = 0x0000000c,
5662 +
5663 + MIIMCMD_rd_b = 0,
5664 + MIIMCMD_rd_m = 0x00000001,
5665 + MIIMCMD_scn_b = 1,
5666 + MIIMCMD_scn_m = 0x00000002,
5667 +
5668 + MIIMADDR_regaddr_b = 0,
5669 + MIIMADDR_regaddr_m = 0x0000001f,
5670 + MIIMADDR_phyaddr_b = 8,
5671 + MIIMADDR_phyaddr_m = 0x00001f00,
5672 +
5673 + MIIMWTD_wdata_b = 0,
5674 + MIIMWTD_wdata_m = 0x0000ffff,
5675 +
5676 + MIIMRDD_rdata_b = 0,
5677 + MIIMRDD_rdata_m = 0x0000ffff,
5678 +
5679 + MIIMIND_bsy_b = 0,
5680 + MIIMIND_bsy_m = 0x00000001,
5681 + MIIMIND_scn_b = 1,
5682 + MIIMIND_scn_m = 0x00000002,
5683 + MIIMIND_nv_b = 2,
5684 + MIIMIND_nv_m = 0x00000004,
5685 +
5686 +} ;
5687 +
5688 +/*
5689 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
5690 + */
5691 +enum
5692 +{
5693 + ETHRX_fd_b = 0,
5694 + ETHRX_fd_m = 0x00000001,
5695 + ETHRX_ld_b = 1,
5696 + ETHRX_ld_m = 0x00000002,
5697 + ETHRX_rok_b = 2,
5698 + ETHRX_rok_m = 0x00000004,
5699 + ETHRX_fm_b = 3,
5700 + ETHRX_fm_m = 0x00000008,
5701 + ETHRX_mp_b = 4,
5702 + ETHRX_mp_m = 0x00000010,
5703 + ETHRX_bp_b = 5,
5704 + ETHRX_bp_m = 0x00000020,
5705 + ETHRX_vlt_b = 6,
5706 + ETHRX_vlt_m = 0x00000040,
5707 + ETHRX_cf_b = 7,
5708 + ETHRX_cf_m = 0x00000080,
5709 + ETHRX_ovr_b = 8,
5710 + ETHRX_ovr_m = 0x00000100,
5711 + ETHRX_crc_b = 9,
5712 + ETHRX_crc_m = 0x00000200,
5713 + ETHRX_cv_b = 10,
5714 + ETHRX_cv_m = 0x00000400,
5715 + ETHRX_db_b = 11,
5716 + ETHRX_db_m = 0x00000800,
5717 + ETHRX_le_b = 12,
5718 + ETHRX_le_m = 0x00001000,
5719 + ETHRX_lor_b = 13,
5720 + ETHRX_lor_m = 0x00002000,
5721 + ETHRX_ces_b = 14,
5722 + ETHRX_ces_m = 0x00004000,
5723 + ETHRX_length_b = 16,
5724 + ETHRX_length_m = 0xffff0000,
5725 +
5726 + ETHTX_fd_b = 0,
5727 + ETHTX_fd_m = 0x00000001,
5728 + ETHTX_ld_b = 1,
5729 + ETHTX_ld_m = 0x00000002,
5730 + ETHTX_oen_b = 2,
5731 + ETHTX_oen_m = 0x00000004,
5732 + ETHTX_pen_b = 3,
5733 + ETHTX_pen_m = 0x00000008,
5734 + ETHTX_cen_b = 4,
5735 + ETHTX_cen_m = 0x00000010,
5736 + ETHTX_hen_b = 5,
5737 + ETHTX_hen_m = 0x00000020,
5738 + ETHTX_tok_b = 6,
5739 + ETHTX_tok_m = 0x00000040,
5740 + ETHTX_mp_b = 7,
5741 + ETHTX_mp_m = 0x00000080,
5742 + ETHTX_bp_b = 8,
5743 + ETHTX_bp_m = 0x00000100,
5744 + ETHTX_und_b = 9,
5745 + ETHTX_und_m = 0x00000200,
5746 + ETHTX_of_b = 10,
5747 + ETHTX_of_m = 0x00000400,
5748 + ETHTX_ed_b = 11,
5749 + ETHTX_ed_m = 0x00000800,
5750 + ETHTX_ec_b = 12,
5751 + ETHTX_ec_m = 0x00001000,
5752 + ETHTX_lc_b = 13,
5753 + ETHTX_lc_m = 0x00002000,
5754 + ETHTX_td_b = 14,
5755 + ETHTX_td_m = 0x00004000,
5756 + ETHTX_crc_b = 15,
5757 + ETHTX_crc_m = 0x00008000,
5758 + ETHTX_le_b = 16,
5759 + ETHTX_le_m = 0x00010000,
5760 + ETHTX_cc_b = 17,
5761 + ETHTX_cc_m = 0x001E0000,
5762 +} ;
5763 +
5764 +enum
5765 +{
5766 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
5767 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
5768 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
5769 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
5770 +} ;
5771 +
5772 +typedef struct
5773 +{
5774 + u32 ipabmcrx ;
5775 + u32 ipabmctx ;
5776 +}volatile *IPABM_ETH_t;
5777 +#endif //__IDT_RC32365_ETH_H__
5778 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
5779 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
5780 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-01-10 00:32:33.000000000 +0100
5781 @@ -0,0 +1,72 @@
5782 +/**************************************************************************
5783 + *
5784 + * BRIEF MODULE DESCRIPTION
5785 + * RC32365/336 Ethernet status checking.
5786 + *
5787 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5788 + *
5789 + * This program is free software; you can redistribute it and/or modify it
5790 + * under the terms of the GNU General Public License as published by the
5791 + * Free Software Foundation; either version 2 of the License, or (at your
5792 + * option) any later version.
5793 + *
5794 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5795 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5796 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5797 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5798 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5799 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5800 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5801 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5802 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5803 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5804 + *
5805 + * You should have received a copy of the GNU General Public License along
5806 + * with this program; if not, write to the Free Software Foundation, Inc.,
5807 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5808 + *
5809 + *
5810 + **************************************************************************
5811 + * May 2004 P. Sadik.
5812 + *
5813 + * Initial Release
5814 + *
5815 + *
5816 + *
5817 + **************************************************************************
5818 + */
5819 +
5820 +#ifndef __IDT_RC32365_ETH_V_H__
5821 +#define __IDT_RC32365_ETH_V_H__
5822 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
5823 +
5824 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
5825 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
5826 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
5827 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
5828 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
5829 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
5830 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
5831 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
5832 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
5833 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
5834 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
5835 +
5836 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
5837 +
5838 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
5839 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
5840 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
5841 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
5842 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
5843 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
5844 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
5845 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
5846 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
5847 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
5848 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
5849 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
5850 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
5851 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
5852 +
5853 +#endif //__IDT_RC32365_ETH_V_H__
5854 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
5855 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
5856 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-01-10 00:32:33.000000000 +0100
5857 @@ -0,0 +1,181 @@
5858 +/**************************************************************************
5859 + *
5860 + * BRIEF MODULE DESCRIPTION
5861 + * RC32365/336 GPIO hardware abstraction.
5862 + *
5863 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5864 + *
5865 + * This program is free software; you can redistribute it and/or modify it
5866 + * under the terms of the GNU General Public License as published by the
5867 + * Free Software Foundation; either version 2 of the License, or (at your
5868 + * option) any later version.
5869 + *
5870 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5871 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5872 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5873 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5874 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5875 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5876 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5877 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5878 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5879 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5880 + *
5881 + * You should have received a copy of the GNU General Public License along
5882 + * with this program; if not, write to the Free Software Foundation, Inc.,
5883 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5884 + *
5885 + *
5886 + **************************************************************************
5887 + * May 2004 P. Sadik.
5888 + *
5889 + * Initial Release
5890 + *
5891 + *
5892 + *
5893 + **************************************************************************
5894 + */
5895 +
5896 +#ifndef __IDT_RC32365_GPIO_H__
5897 +#define __IDT_RC32365_GPIO_H__
5898 +
5899 +enum
5900 +{
5901 + GPIO0_PhysicalAddress = 0x18048000,
5902 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
5903 +
5904 + GPIO0_VirtualAddress = 0xb8048000,
5905 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
5906 +} ;
5907 +
5908 +typedef struct
5909 +{
5910 + u32 gpiofunc; /* GPIO Function Register
5911 + * gpiofunc[x]==0 bit = gpio
5912 + * func[x]==1 bit = altfunc
5913 + */
5914 + u32 gpiocfg; /* GPIO Configuration Register
5915 + * gpiocfg[x]==0 bit = input
5916 + * gpiocfg[x]==1 bit = output
5917 + */
5918 + u32 gpiod; /* GPIO Data Register
5919 + * gpiod[x] read/write gpio pinX status
5920 + */
5921 + u32 gpioilevel; /* GPIO Interrupt Status Register
5922 + * interrupt level (see gpioistat)
5923 + */
5924 + u32 gpioistat; /* Gpio Interrupt Status Register
5925 + * istat[x] = (gpiod[x] == level[x])
5926 + * cleared in ISR (STICKY bits)
5927 + */
5928 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
5929 +} volatile * GPIO_t ;
5930 +
5931 +typedef enum
5932 +{
5933 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
5934 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
5935 + GPIO_input_v = 0, // gpiocfg use pin as input.
5936 + GPIO_output_v = 1, // gpiocfg use pin as output.
5937 + GPIO_pin0_b = 0,
5938 + GPIO_pin0_m = 0x00000001,
5939 + GPIO_pin1_b = 1,
5940 + GPIO_pin1_m = 0x00000002,
5941 + GPIO_pin2_b = 2,
5942 + GPIO_pin2_m = 0x00000004,
5943 + GPIO_pin3_b = 3,
5944 + GPIO_pin3_m = 0x00000008,
5945 + GPIO_pin4_b = 4,
5946 + GPIO_pin4_m = 0x00000010,
5947 + GPIO_pin5_b = 5,
5948 + GPIO_pin5_m = 0x00000020,
5949 + GPIO_pin6_b = 6,
5950 + GPIO_pin6_m = 0x00000040,
5951 + GPIO_pin7_b = 7,
5952 + GPIO_pin7_m = 0x00000080,
5953 + GPIO_pin8_b = 8,
5954 + GPIO_pin8_m = 0x00000100,
5955 + GPIO_pin9_b = 9,
5956 + GPIO_pin9_m = 0x00000200,
5957 + GPIO_pin10_b = 10,
5958 + GPIO_pin10_m = 0x00000400,
5959 + GPIO_pin11_b = 11,
5960 + GPIO_pin11_m = 0x00000800,
5961 + GPIO_pin12_b = 12,
5962 + GPIO_pin12_m = 0x00001000,
5963 + GPIO_pin13_b = 13,
5964 + GPIO_pin13_m = 0x00002000,
5965 + GPIO_pin14_b = 14,
5966 + GPIO_pin14_m = 0x00004000,
5967 + GPIO_pin15_b = 15,
5968 + GPIO_pin15_m = 0x00008000,
5969 +
5970 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
5971 +
5972 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
5973 + GPIO_u0sout_m = GPIO_pin0_m,
5974 + GPIO_u0sout_cfg_v = GPIO_output_v,
5975 +
5976 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
5977 + GPIO_u0sinp_m = GPIO_pin1_m,
5978 + GPIO_u0sinp_cfg_v = GPIO_input_v,
5979 +
5980 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
5981 + GPIO_maddr22_m = GPIO_pin2_m,
5982 + GPIO_maddr22_cfg_v = GPIO_output_v,
5983 +
5984 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
5985 + GPIO_maddr23_m = GPIO_pin3_m,
5986 + GPIO_maddr23_cfg_v = GPIO_output_v,
5987 +
5988 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
5989 + GPIO_maddr24_m = GPIO_pin4_m,
5990 + GPIO_maddr24_cfg_v = GPIO_output_v,
5991 +
5992 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
5993 + GPIO_maddr25_m = GPIO_pin5_m,
5994 + GPIO_maddr25_cfg_v = GPIO_output_v,
5995 +
5996 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
5997 + GPIO_rngclk_m = GPIO_pin6_m,
5998 + GPIO_rngclk_cfg_v = GPIO_input_v,
5999 +
6000 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
6001 + GPIO_sdckenp_m = GPIO_pin7_m,
6002 + GPIO_sdckenp_cfg_v = GPIO_output_v,
6003 +
6004 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
6005 + GPIO_cen1_m = GPIO_pin8_m,
6006 + GPIO_cen1_cfg_v = GPIO_output_v,
6007 +
6008 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
6009 + GPIO_cen2_m = GPIO_pin9_m,
6010 + GPIO_cen2_cfg_v = GPIO_output_v,
6011 +
6012 + GPIO_regn_b = GPIO_pin10_b, // reserved.
6013 + GPIO_regn_m = GPIO_pin10_m,
6014 + GPIO_regn_cfg_v = GPIO_output_v,
6015 +
6016 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
6017 + GPIO_iordn_m = GPIO_pin11_m,
6018 + GPIO_iordn_cfg_v = GPIO_output_v,
6019 +
6020 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
6021 + GPIO_iowrn_m = GPIO_pin12_m,
6022 + GPIO_iowrn_cfg_v = GPIO_output_v,
6023 +
6024 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
6025 + GPIO_pcireqn2_m = GPIO_pin13_m,
6026 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
6027 +
6028 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
6029 + GPIO_pcigntn2_m = GPIO_pin14_m,
6030 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
6031 +
6032 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
6033 + GPIO_pcimuintn_m = GPIO_pin15_m,
6034 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
6035 +
6036 +} GPIO_DEFS_t;
6037 +
6038 +#endif //__IDT_RC32365_GPIO_H__
6039 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
6040 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
6041 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-01-10 00:32:33.000000000 +0100
6042 @@ -0,0 +1,91 @@
6043 +/**************************************************************************
6044 + *
6045 + * BRIEF MODULE DESCRIPTION
6046 + * Routines to set/clear/toggle GPIO on RC32365
6047 + *
6048 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6049 + *
6050 + * This program is free software; you can redistribute it and/or modify it
6051 + * under the terms of the GNU General Public License as published by the
6052 + * Free Software Foundation; either version 2 of the License, or (at your
6053 + * option) any later version.
6054 + *
6055 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6056 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6057 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6058 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6059 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6060 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6061 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6062 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6063 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6064 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6065 + *
6066 + * You should have received a copy of the GNU General Public License along
6067 + * with this program; if not, write to the Free Software Foundation, Inc.,
6068 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6069 + *
6070 + *
6071 + **************************************************************************
6072 + * May 2004 P. Sadik.
6073 + *
6074 + * Initial Release
6075 + *
6076 + *
6077 + *
6078 + **************************************************************************
6079 + */
6080 +#ifndef __IDT_RC32365_GPIO_V_H__
6081 +#define __IDT_RC32365_GPIO_V_H__
6082 +
6083 +
6084 +#ifdef _LANGUAGE_ASSEMBLY
6085 +#define SET_GPIO(pin) \
6086 + lui t5,0xb804 ; \
6087 + ori t5,t5,0x8000 ; \
6088 + lw t4,8(t5) ; \
6089 + ori t4,t4,pin ; \
6090 + sw t4,8(t5) ;
6091 +
6092 +#define CLEAR_GPIO(pin) \
6093 + lui t5,0xb804 ; \
6094 + ori t5,t5,0x8000 ; \
6095 + lw t4,8(t5) ; \
6096 + lui t6,0xFFFF; \
6097 + ori t6,t6,0xFFFF; \
6098 + xori t6,t6,pin ; \
6099 + and t4,t6 ; \
6100 + sw t4,8(t5) ;
6101 +
6102 +#define TOGGLE_GPIO(pin) \
6103 + lui t5,0xb804 ; \
6104 + ori t5,t5,0x8000 ; \
6105 + lw t4,8(t5) ; \
6106 + xori t4,t4,pin ; \
6107 + sw t4,8(t5) ;
6108 +
6109 +#else // !_LANGUAGE_ASSEMBLY
6110 +#include <asm/rc32300/types.h>
6111 +#include <asm/rc32300/rc32365_gpio.h>
6112 +#include <asm/rc32300/rc32365.h>
6113 +
6114 +static inline void set_gpio(unsigned long pin)
6115 +{
6116 + idt_gpio->gpiod |= pin;
6117 +}
6118 +
6119 +static inline void clear_gpio(unsigned long pin)
6120 +{
6121 + idt_gpio->gpiod &= ~pin;
6122 +}
6123 +static inline void toggle_gpio(unsigned long pin)
6124 +{
6125 + idt_gpio->gpiod ^= pin;
6126 +}
6127 +#define SET_GPIO(pin) set_gpio(pin)
6128 +#define CLEAR_GPIO(pin) clear_gpio(pin)
6129 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
6130 +#endif // _LANGUAGE_ASSEMBLY
6131 +
6132 +#endif //__IDT_RC32365_GPIO_V_H__
6133 +
6134 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h
6135 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
6136 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-01-10 00:32:33.000000000 +0100
6137 @@ -0,0 +1,160 @@
6138 +/**************************************************************************
6139 + *
6140 + * BRIEF MODULE DESCRIPTION
6141 + * Definitions for IDT RC32365 CPU.
6142 + *
6143 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6144 + *
6145 + * This program is free software; you can redistribute it and/or modify it
6146 + * under the terms of the GNU General Public License as published by the
6147 + * Free Software Foundation; either version 2 of the License, or (at your
6148 + * option) any later version.
6149 + *
6150 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6151 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6152 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6153 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6154 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6155 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6156 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6157 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6158 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6159 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6160 + *
6161 + * You should have received a copy of the GNU General Public License along
6162 + * with this program; if not, write to the Free Software Foundation, Inc.,
6163 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6164 + *
6165 + *
6166 + **************************************************************************
6167 + * May 2004 P. Sadik.
6168 + *
6169 + * Initial Release
6170 + *
6171 + *
6172 + *
6173 + **************************************************************************
6174 + */
6175 +
6176 +#ifndef __IDT_RC32365_H__
6177 +#define __IDT_RC32365_H__
6178 +
6179 +extern unsigned int cedar_za;
6180 +
6181 +/* Base address of internal registers */
6182 +#define RC32365_REG_BASE 0x18000000
6183 +
6184 +/* System ID Registers */
6185 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
6186 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
6187 +
6188 +/* Reset Controller */
6189 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
6190 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
6191 +
6192 +/* Device Controller */
6193 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
6194 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
6195 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
6196 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
6197 +#define DEV_REG_OFFSET 0x10
6198 +
6199 +/* SDRAM Controller */
6200 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
6201 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
6202 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
6203 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
6204 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
6205 +
6206 +/* Counters/Timers */
6207 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
6208 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
6209 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
6210 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
6211 +#define TIMER_REG_OFFSET 0x10
6212 +
6213 +/* System Integrity */
6214 +
6215 +/* Interrupt Controller */
6216 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
6217 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
6218 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
6219 +#define IC_GROUP_OFFSET 0x0c
6220 +
6221 +#define NUM_INTR_GROUPS 5
6222 +/*
6223 + * The IRQ mapping is as follows:
6224 + *
6225 + * IRQ Mapped To
6226 + * --- -------------------
6227 + * 0 SW0 (IP0) SW0 intr
6228 + * 1 SW1 (IP1) SW1 intr
6229 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
6230 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
6231 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
6232 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
6233 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
6234 + * 7 Int5 (IP7) CP0 Timer
6235 + *
6236 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
6237 + * internally on the RC32365 is routed to the Expansion
6238 + * Interrupt Controller.
6239 + */
6240 +#define MIPS_CPU_TIMER_IRQ 7
6241 +
6242 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
6243 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
6244 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
6245 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
6246 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
6247 +
6248 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
6249 +
6250 +/* DMA - see rc32365_dma.h for full list of registers */
6251 +
6252 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
6253 +#define DMA_CHAN_OFFSET 0x14
6254 +
6255 +/* GPIO Controller */
6256 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6257 +
6258 +/* 16550 UARTs */
6259 +#ifdef __MIPSEB__
6260 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
6261 +#else
6262 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
6263 +#endif
6264 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
6265 +
6266 +/* Ethernet - see rc32365_eth.h for full list of registers */
6267 +
6268 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
6269 +
6270 +#define IDT_CLOCK_MULT 2
6271 +
6272 +/* FLASH (device 1) */
6273 +#define FLASH_BASE 0x08000000
6274 +#define FLASH_SIZE 0x00800000
6275 +
6276 +/* LCD 4-digit display (device 2) */
6277 +#define LCD_DIGIT0 0x0C000003
6278 +#define LCD_DIGIT1 0x0C000002
6279 +#define LCD_DIGIT2 0x0C000001
6280 +#define LCD_DIGIT3 0x0C000000
6281 +
6282 +/* RTC (DS1553) (device 2) */
6283 +#define RTC_BASE 0x0c800000
6284 +/* NVRAM */
6285 +#define NVRAM_BASE RTC_BASE
6286 +#define NVRAM_ENVSIZE_OFF 4
6287 +#define NVRAM_ENVSTART_OFF 32
6288 +
6289 +/* Interrupts routed on 79EB365 board */
6290 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
6291 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
6292 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
6293 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
6294 +
6295 +#define RAM_SIZE (32 * 1024 * 1024)
6296 +
6297 +#endif //__IDT_RC32365_H__
6298 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
6299 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
6300 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-01-10 00:32:33.000000000 +0100
6301 @@ -0,0 +1,515 @@
6302 +/**************************************************************************
6303 + *
6304 + * BRIEF MODULE DESCRIPTION
6305 + * Datatype declaration for IDT 79EB365/336 PCI
6306 + *
6307 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6308 + *
6309 + * This program is free software; you can redistribute it and/or modify it
6310 + * under the terms of the GNU General Public License as published by the
6311 + * Free Software Foundation; either version 2 of the License, or (at your
6312 + * option) any later version.
6313 + *
6314 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6315 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6316 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6317 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6318 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6319 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6320 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6321 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6322 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6323 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6324 + *
6325 + * You should have received a copy of the GNU General Public License along
6326 + * with this program; if not, write to the Free Software Foundation, Inc.,
6327 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6328 + *
6329 + *
6330 + **************************************************************************
6331 + * May 2004 P. Sadik.
6332 + *
6333 + * Initial Release
6334 + *
6335 + *
6336 + *
6337 + **************************************************************************
6338 + */
6339 +
6340 +#ifndef __IDT_RC32365_PCI_H__
6341 +#define __IDT_RC32365_PCI_H__
6342 +
6343 +enum
6344 +{
6345 + PCI0_PhysicalAddress = 0x18068000,
6346 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
6347 +
6348 + PCI0_VirtualAddress = 0xb8068000,
6349 + PCI_VirtualAddress = PCI0_VirtualAddress,
6350 +} ;
6351 +
6352 +enum
6353 +{
6354 + PCI_LbaCount = 4, // Local base addresses.
6355 +} ;
6356 +
6357 +typedef struct
6358 +{
6359 + u32 a ; // Address.
6360 + u32 c ; // Control.
6361 + u32 m ; // mapping.
6362 +} PCI_Map_s ;
6363 +
6364 +typedef struct
6365 +{
6366 + u32 pcic ;
6367 + u32 pcis ;
6368 + u32 pcism ;
6369 + u32 pcicfga ;
6370 + u32 pcicfgd ;
6371 + PCI_Map_s pcilba [PCI_LbaCount] ;
6372 + u32 pcidac ;
6373 + u32 pcidas ;
6374 + u32 pcidasm ;
6375 + u32 pcidad ;
6376 + u32 pcidma8c ;
6377 + u32 pcidma9c ;
6378 + u32 pcitc ;
6379 +} volatile *PCI_t ;
6380 +
6381 +// PCI messaging unit.
6382 +enum
6383 +{
6384 + PCIM_Count = 2,
6385 +} ;
6386 +typedef struct
6387 +{
6388 + u32 pciim [PCIM_Count] ;
6389 + u32 pciom [PCIM_Count] ;
6390 + u32 pciid ;
6391 + u32 pciiic ;
6392 + u32 pciiim ;
6393 + u32 pciiod ;
6394 + u32 pciioic ;
6395 + u32 pciioim ;
6396 +} volatile *PCIM_t ;
6397 +
6398 +/*******************************************************************************
6399 + *
6400 + * PCI Control Register
6401 + *
6402 + ******************************************************************************/
6403 +enum
6404 +{
6405 + PCIC_en_b = 0,
6406 + PCIC_en_m = 0x00000001,
6407 + PCIC_tnr_b = 1,
6408 + PCIC_tnr_m = 0x00000002,
6409 + PCIC_sce_b = 2,
6410 + PCIC_sce_m = 0x00000004,
6411 + PCIC_ien_b = 3,
6412 + PCIC_ien_m = 0x00000008,
6413 + PCIC_aaa_b = 4,
6414 + PCIC_aaa_m = 0x00000010,
6415 + PCIC_eap_b = 5,
6416 + PCIC_eap_m = 0x00000020,
6417 + PCIC_pcim_b = 6,
6418 + PCIC_pcim_m = 0x000001c0,
6419 + PCIC_pcim_disabled_v = 0,
6420 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
6421 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
6422 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
6423 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
6424 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
6425 + PCIC_pcim_reserved6_v = 6,
6426 + PCIC_pcim_reserved7_v = 7,
6427 + PCIC_igm_b = 9,
6428 + PCIC_igm_m = 0x00000200,
6429 +} ;
6430 +
6431 +/*******************************************************************************
6432 + *
6433 + * PCI Status Register
6434 + *
6435 + ******************************************************************************/
6436 +enum {
6437 + PCIS_eed_b = 0,
6438 + PCIS_eed_m = 0x00000001,
6439 + PCIS_wr_b = 1,
6440 + PCIS_wr_m = 0x00000002,
6441 + PCIS_nmi_b = 2,
6442 + PCIS_nmi_m = 0x00000004,
6443 + PCIS_ii_b = 3,
6444 + PCIS_ii_m = 0x00000008,
6445 + PCIS_cwe_b = 4,
6446 + PCIS_cwe_m = 0x00000010,
6447 + PCIS_cre_b = 5,
6448 + PCIS_cre_m = 0x00000020,
6449 + PCIS_mdpe_b = 6,
6450 + PCIS_mdpe_m = 0x00000040,
6451 + PCIS_sta_b = 7,
6452 + PCIS_sta_m = 0x00000080,
6453 + PCIS_rta_b = 8,
6454 + PCIS_rta_m = 0x00000100,
6455 + PCIS_rma_b = 9,
6456 + PCIS_rma_m = 0x00000200,
6457 + PCIS_sse_b = 10,
6458 + PCIS_sse_m = 0x00000400,
6459 + PCIS_ose_b = 11,
6460 + PCIS_ose_m = 0x00000800,
6461 + PCIS_pe_b = 12,
6462 + PCIS_pe_m = 0x00001000,
6463 + PCIS_tae_b = 13,
6464 + PCIS_tae_m = 0x00002000,
6465 + PCIS_rle_b = 14,
6466 + PCIS_rle_m = 0x00004000,
6467 + PCIS_bme_b = 15,
6468 + PCIS_bme_m = 0x00008000,
6469 + PCIS_prd_b = 16,
6470 + PCIS_prd_m = 0x00010000,
6471 + PCIS_rip_b = 17,
6472 + PCIS_rip_m = 0x00020000,
6473 +} ;
6474 +
6475 +/*******************************************************************************
6476 + *
6477 + * PCI Status Mask Register
6478 + *
6479 + ******************************************************************************/
6480 +enum {
6481 + PCISM_eed_b = 0,
6482 + PCISM_eed_m = 0x00000001,
6483 + PCISM_wr_b = 1,
6484 + PCISM_wr_m = 0x00000002,
6485 + PCISM_nmi_b = 2,
6486 + PCISM_nmi_m = 0x00000004,
6487 + PCISM_ii_b = 3,
6488 + PCISM_ii_m = 0x00000008,
6489 + PCISM_cwe_b = 4,
6490 + PCISM_cwe_m = 0x00000010,
6491 + PCISM_cre_b = 5,
6492 + PCISM_cre_m = 0x00000020,
6493 + PCISM_mdpe_b = 6,
6494 + PCISM_mdpe_m = 0x00000040,
6495 + PCISM_sta_b = 7,
6496 + PCISM_sta_m = 0x00000080,
6497 + PCISM_rta_b = 8,
6498 + PCISM_rta_m = 0x00000100,
6499 + PCISM_rma_b = 9,
6500 + PCISM_rma_m = 0x00000200,
6501 + PCISM_sse_b = 10,
6502 + PCISM_sse_m = 0x00000400,
6503 + PCISM_ose_b = 11,
6504 + PCISM_ose_m = 0x00000800,
6505 + PCISM_pe_b = 12,
6506 + PCISM_pe_m = 0x00001000,
6507 + PCISM_tae_b = 13,
6508 + PCISM_tae_m = 0x00002000,
6509 + PCISM_rle_b = 14,
6510 + PCISM_rle_m = 0x00004000,
6511 + PCISM_bme_b = 15,
6512 + PCISM_bme_m = 0x00008000,
6513 + PCISM_prd_b = 16,
6514 + PCISM_prd_m = 0x00010000,
6515 + PCISM_rip_b = 17,
6516 + PCISM_rip_m = 0x00020000,
6517 +} ;
6518 +
6519 +/*******************************************************************************
6520 + *
6521 + * PCI Configuration Address Register
6522 + *
6523 + ******************************************************************************/
6524 +enum {
6525 + PCICFGA_reg_b = 2,
6526 + PCICFGA_reg_m = 0x000000fc,
6527 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
6528 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
6529 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
6530 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
6531 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
6532 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
6533 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
6534 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
6535 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
6536 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
6537 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
6538 + PCICFGA_reg_pba0m_v = 0x48>>2,
6539 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
6540 + PCICFGA_reg_pba1m_v = 0x50>>2,
6541 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
6542 + PCICFGA_reg_pba2m_v = 0x58>>2,
6543 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
6544 + PCICFGA_reg_pba3m_v = 0x60>>2,
6545 + PCICFGA_reg_pmgt_v = 0x64>>2,
6546 + PCICFGA_func_b = 8,
6547 + PCICFGA_func_m = 0x00000700,
6548 + PCICFGA_dev_b = 11,
6549 + PCICFGA_dev_m = 0x0000f800,
6550 + PCICFGA_dev_internal_v = 0,
6551 + PCICFGA_bus_b = 16,
6552 + PCICFGA_bus_m = 0x00ff0000,
6553 + PCICFGA_bus_type0_v = 0, //local bus
6554 + PCICFGA_en_b = 31, // read only
6555 + PCICFGA_en_m = 0x80000000,
6556 +} ;
6557 +
6558 +enum {
6559 + PCFGID_vendor_b = 0,
6560 + PCFGID_vendor_m = 0x0000ffff,
6561 + PCFGID_vendor_IDT_v = 0x111d,
6562 + PCFGID_device_b = 16,
6563 + PCFGID_device_m = 0xffff0000,
6564 + PCFGID_device_Acaciade_v = 0x0207,
6565 +
6566 + PCFG04_command_ioena_b = 1,
6567 + PCFG04_command_ioena_m = 0x00000001,
6568 + PCFG04_command_memena_b = 2,
6569 + PCFG04_command_memena_m = 0x00000002,
6570 + PCFG04_command_bmena_b = 3,
6571 + PCFG04_command_bmena_m = 0x00000004,
6572 + PCFG04_command_mwinv_b = 5,
6573 + PCFG04_command_mwinv_m = 0x00000010,
6574 + PCFG04_command_parena_b = 7,
6575 + PCFG04_command_parena_m = 0x00000040,
6576 + PCFG04_command_serrena_b = 9,
6577 + PCFG04_command_serrena_m = 0x00000100,
6578 + PCFG04_command_fastbbena_b = 10,
6579 + PCFG04_command_fastbbena_m = 0x00000200,
6580 + PCFG04_status_b = 16,
6581 + PCFG04_status_m = 0xffff0000,
6582 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
6583 + PCFG04_status_66MHz_m = 0x00200000,
6584 + PCFG04_status_fbb_b = 23,
6585 + PCFG04_status_fbb_m = 0x00800000,
6586 + PCFG04_status_mdpe_b = 24,
6587 + PCFG04_status_mdpe_m = 0x01000000,
6588 + PCFG04_status_dst_b = 25,
6589 + PCFG04_status_dst_m = 0x06000000,
6590 + PCFG04_status_sta_b = 27,
6591 + PCFG04_status_sta_m = 0x08000000,
6592 + PCFG04_status_rta_b = 28,
6593 + PCFG04_status_rta_m = 0x10000000,
6594 + PCFG04_status_rma_b = 29,
6595 + PCFG04_status_rma_m = 0x20000000,
6596 + PCFG04_status_sse_b = 30,
6597 + PCFG04_status_sse_m = 0x40000000,
6598 + PCFG04_status_pe_b = 31,
6599 + PCFG04_status_pe_m = 0x40000000,
6600 +
6601 + PCFG08_revId_b = 0,
6602 + PCFG08_revId_m = 0x000000ff,
6603 + PCFG08_classCode_b = 0,
6604 + PCFG08_classCode_m = 0xffffff00,
6605 + PCFG08_classCode_bridge_v = 06,
6606 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
6607 + PCFG0C_cacheline_b = 0,
6608 + PCFG0C_cacheline_m = 0x000000ff,
6609 + PCFG0C_masterLatency_b = 8,
6610 + PCFG0C_masterLatency_m = 0x0000ff00,
6611 + PCFG0C_headerType_b = 16,
6612 + PCFG0C_headerType_m = 0x00ff0000,
6613 + PCFG0C_bist_b = 24,
6614 + PCFG0C_bist_m = 0xff000000,
6615 +
6616 + PCIPBA_msi_b = 0,
6617 + PCIPBA_msi_m = 0x00000001,
6618 + PCIPBA_p_b = 3,
6619 + PCIPBA_p_m = 0x00000004,
6620 + PCIPBA_baddr_b = 8,
6621 + PCIPBA_baddr_m = 0xffffff00,
6622 +
6623 + PCFGSS_vendorId_b = 0,
6624 + PCFGSS_vendorId_m = 0x0000ffff,
6625 + PCFGSS_id_b = 16,
6626 + PCFGSS_id_m = 0xffff0000,
6627 +
6628 + PCFG3C_interruptLine_b = 0,
6629 + PCFG3C_interruptLine_m = 0x000000ff,
6630 + PCFG3C_interruptPin_b = 8,
6631 + PCFG3C_interruptPin_m = 0x0000ff00,
6632 + PCFG3C_minGrant_b = 16,
6633 + PCFG3C_minGrant_m = 0x00ff0000,
6634 + PCFG3C_maxLat_b = 24,
6635 + PCFG3C_maxLat_m = 0xff000000,
6636 +
6637 + PCIPBAC_msi_b = 0,
6638 + PCIPBAC_msi_m = 0x00000001,
6639 + PCIPBAC_p_b = 1,
6640 + PCIPBAC_p_m = 0x00000002,
6641 + PCIPBAC_size_b = 2,
6642 + PCIPBAC_size_m = 0x0000007c,
6643 + PCIPBAC_sb_b = 7,
6644 + PCIPBAC_sb_m = 0x00000080,
6645 + PCIPBAC_pp_b = 8,
6646 + PCIPBAC_pp_m = 0x00000100,
6647 + PCIPBAC_mr_b = 9,
6648 + PCIPBAC_mr_m = 0x00000600,
6649 + PCIPBAC_mr_read_v =0, //no prefetching
6650 + PCIPBAC_mr_readLine_v =1,
6651 + PCIPBAC_mr_readMult_v =2,
6652 + PCIPBAC_mrl_b = 11,
6653 + PCIPBAC_mrl_m = 0x00000800,
6654 + PCIPBAC_mrm_b = 12,
6655 + PCIPBAC_mrm_m = 0x00001000,
6656 + PCIPBAC_trp_b = 13,
6657 + PCIPBAC_trp_m = 0x00002000,
6658 +
6659 + PCFG40_trdyTimeout_b = 0,
6660 + PCFG40_trdyTimeout_m = 0x000000ff,
6661 + PCFG40_retryLim_b = 8,
6662 + PCFG40_retryLim_m = 0x0000ff00,
6663 +};
6664 +
6665 +/*******************************************************************************
6666 + *
6667 + * PCI Local Base Address [0|1|2|3] Register
6668 + *
6669 + ******************************************************************************/
6670 +enum {
6671 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
6672 + PCILBA_baddr_m = 0xffffff00,
6673 +} ;
6674 +/*******************************************************************************
6675 + *
6676 + * PCI Local Base Address Control Register
6677 + *
6678 + ******************************************************************************/
6679 +enum {
6680 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
6681 + PCILBAC_msi_m = 0x00000001,
6682 + PCILBAC_msi_mem_v = 0,
6683 + PCILBAC_msi_io_v = 1,
6684 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
6685 + PCILBAC_size_m = 0x0000007c,
6686 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
6687 + PCILBAC_sb_m = 0x00000080,
6688 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
6689 + PCILBAC_rt_m = 0x00000100,
6690 + PCILBAC_rt_noprefetch_v = 0, // mem read
6691 + PCILBAC_rt_prefetch_v = 1, // mem readline
6692 +} ;
6693 +
6694 +/*******************************************************************************
6695 + *
6696 + * PCI Local Base Address [0|1|2|3] Mapping Register
6697 + *
6698 + ******************************************************************************/
6699 +enum {
6700 + PCILBAM_maddr_b = 8,
6701 + PCILBAM_maddr_m = 0xffffff00,
6702 +} ;
6703 +
6704 +/*******************************************************************************
6705 + *
6706 + * PCI Decoupled Access Control Register
6707 + *
6708 + ******************************************************************************/
6709 +enum {
6710 + PCIDAC_den_b = 0,
6711 + PCIDAC_den_m = 0x00000001,
6712 +} ;
6713 +
6714 +/*******************************************************************************
6715 + *
6716 + * PCI Decoupled Access Status Register
6717 + *
6718 + ******************************************************************************/
6719 +enum {
6720 + PCIDAS_d_b = 0,
6721 + PCIDAS_d_m = 0x00000001,
6722 + PCIDAS_b_b = 1,
6723 + PCIDAS_b_m = 0x00000002,
6724 + PCIDAS_e_b = 2,
6725 + PCIDAS_e_m = 0x00000004,
6726 + PCIDAS_ofe_b = 3,
6727 + PCIDAS_ofe_m = 0x00000008,
6728 + PCIDAS_off_b = 4,
6729 + PCIDAS_off_m = 0x00000010,
6730 + PCIDAS_ife_b = 5,
6731 + PCIDAS_ife_m = 0x00000020,
6732 + PCIDAS_iff_b = 6,
6733 + PCIDAS_iff_m = 0x00000040,
6734 +} ;
6735 +
6736 +/*******************************************************************************
6737 + *
6738 + * PCI DMA Channel 8 Configuration Register
6739 + *
6740 + ******************************************************************************/
6741 +enum
6742 +{
6743 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
6744 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
6745 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
6746 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
6747 +} ;
6748 +
6749 +/*******************************************************************************
6750 + *
6751 + * PCI DMA Channel 9 Configuration Register
6752 + *
6753 + ******************************************************************************/
6754 +enum
6755 +{
6756 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
6757 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
6758 +} ;
6759 +
6760 +/*******************************************************************************
6761 + *
6762 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
6763 + *
6764 + ******************************************************************************/
6765 +enum {
6766 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
6767 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
6768 + // These are for reads (DMA channel 8)
6769 + PCIDMAD_devcmd_mr_v = 0, //memory read
6770 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
6771 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
6772 + PCIDMAD_devcmd_ior_v = 3, //I/O read
6773 + // These are for writes (DMA channel 9)
6774 + PCIDMAD_devcmd_mw_v = 0, //memory write
6775 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
6776 + PCIDMAD_devcmd_iow_v = 3, //I/O write
6777 +
6778 + // Swap byte field applies to both DMA channel 8 and 9
6779 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
6780 + PCIDMAD_sb_m = 0x01000000, // swap byte field
6781 +} ;
6782 +
6783 +
6784 +/*******************************************************************************
6785 + *
6786 + * PCI Target Control Register
6787 + *
6788 + ******************************************************************************/
6789 +enum
6790 +{
6791 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
6792 + PCITC_rtimer_m = 0x000000ff,
6793 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
6794 + PCITC_dtimer_m = 0x0000ff00,
6795 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
6796 + PCITC_rdr_m = 0x00040000,
6797 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
6798 + PCITC_ddt_m = 0x00080000,
6799 +} ;
6800 +/*******************************************************************************
6801 + *
6802 + * PCI messaging unit [applies to both inbound and outbound registers ]
6803 + *
6804 + ******************************************************************************/
6805 +enum
6806 +{
6807 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
6808 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
6809 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
6810 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
6811 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
6812 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
6813 +};
6814 +
6815 +
6816 +#endif // __IDT_RC32365_PCI_H__
6817 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
6818 --- linux-2.6.15/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
6819 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-01-10 00:32:33.000000000 +0100
6820 @@ -0,0 +1,217 @@
6821 +/**************************************************************************
6822 + *
6823 + * BRIEF MODULE DESCRIPTION
6824 + * PCI header values for IDT 79EB365/336
6825 + *
6826 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6827 + *
6828 + * This program is free software; you can redistribute it and/or modify it
6829 + * under the terms of the GNU General Public License as published by the
6830 + * Free Software Foundation; either version 2 of the License, or (at your
6831 + * option) any later version.
6832 + *
6833 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6834 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6835 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6836 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6837 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6838 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6839 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6840 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6841 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6842 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6843 + *
6844 + * You should have received a copy of the GNU General Public License along
6845 + * with this program; if not, write to the Free Software Foundation, Inc.,
6846 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6847 + *
6848 + *
6849 + **************************************************************************
6850 + * May 2004 P. Sadik.
6851 + *
6852 + * Initial Release
6853 + *
6854 + *
6855 + *
6856 + **************************************************************************
6857 + */
6858 +
6859 +#ifndef __IDT_RC32365_PCI_V_H__
6860 +#define __IDT_RC32365_PCI_V_H__
6861 +
6862 +
6863 +#define PCI_MSG_VirtualAddress 0xB806C010
6864 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
6865 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
6866 +
6867 +#define PCIM_SHFT 0x6
6868 +#define PCIM_BIT_LEN 0x7
6869 +#define PCIM_H_EA 0x3
6870 +#define PCIM_H_IA_FIX 0x4
6871 +#define PCIM_H_IA_RR 0x5
6872 +
6873 +#define PCI_ADDR_START 0x50000000
6874 +
6875 +#define CPUTOPCI_MEM_WIN 0x02000000
6876 +#define CPUTOPCI_IO_WIN 0x00100000
6877 +#define PCILBA_SIZE_SHFT 2
6878 +#define PCILBA_SIZE_MASK 0x1F
6879 +#define SIZE_256MB 0x1C
6880 +#define SIZE_128MB 0x1B
6881 +#define SIZE_64MB 0x1A
6882 +#define SIZE_32MB 0x19
6883 +#define SIZE_16MB 0x18
6884 +#define SIZE_4MB 0x16
6885 +#define SIZE_2MB 0x15
6886 +#define SIZE_1MB 0x14
6887 +#define CEDAR_CONFIG0_ADDR 0x80000000
6888 +#define CEDAR_CONFIG1_ADDR 0x80000004
6889 +#define CEDAR_CONFIG2_ADDR 0x80000008
6890 +#define CEDAR_CONFIG3_ADDR 0x8000000C
6891 +#define CEDAR_CONFIG4_ADDR 0x80000010
6892 +#define CEDAR_CONFIG5_ADDR 0x80000014
6893 +#define CEDAR_CONFIG6_ADDR 0x80000018
6894 +#define CEDAR_CONFIG7_ADDR 0x8000001C
6895 +#define CEDAR_CONFIG8_ADDR 0x80000020
6896 +#define CEDAR_CONFIG9_ADDR 0x80000024
6897 +#define CEDAR_CONFIG10_ADDR 0x80000028
6898 +#define CEDAR_CONFIG11_ADDR 0x8000002C
6899 +#define CEDAR_CONFIG12_ADDR 0x80000030
6900 +#define CEDAR_CONFIG13_ADDR 0x80000034
6901 +#define CEDAR_CONFIG14_ADDR 0x80000038
6902 +#define CEDAR_CONFIG15_ADDR 0x8000003C
6903 +#define CEDAR_CONFIG16_ADDR 0x80000040
6904 +#define CEDAR_CONFIG17_ADDR 0x80000044
6905 +#define CEDAR_CONFIG18_ADDR 0x80000048
6906 +#define CEDAR_CONFIG19_ADDR 0x8000004C
6907 +#define CEDAR_CONFIG20_ADDR 0x80000050
6908 +#define CEDAR_CONFIG21_ADDR 0x80000054
6909 +#define CEDAR_CONFIG22_ADDR 0x80000058
6910 +#define CEDAR_CONFIG23_ADDR 0x8000005C
6911 +#define CEDAR_CONFIG24_ADDR 0x80000060
6912 +#define CEDAR_CONFIG25_ADDR 0x80000064
6913 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
6914 + PCFG04_command_memena_m | \
6915 + PCFG04_command_bmena_m | \
6916 + PCFG04_command_mwinv_m | \
6917 + PCFG04_command_parena_m | \
6918 + PCFG04_command_serrena_m )
6919 +
6920 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
6921 + PCFG04_status_sta_m | \
6922 + PCFG04_status_rta_m | \
6923 + PCFG04_status_rma_m | \
6924 + PCFG04_status_sse_m | \
6925 + PCFG04_status_pe_m)
6926 +
6927 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
6928 + CEDAR_CMD)
6929 +
6930 +#define CEDAR_REVID 0
6931 +#define CEDAR_CLASS_CODE 0
6932 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
6933 + CEDAR_REVID)
6934 +
6935 +#define CEDAR_CACHE_LINE_SIZE 4
6936 +#define CEDAR_MASTER_LAT 0x3c
6937 +#define CEDAR_HEADER_TYPE 0
6938 +#define CEDAR_BIST 0
6939 +
6940 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
6941 + (CEDAR_HEADER_TYPE << 16) | \
6942 + (CEDAR_MASTER_LAT << 8) | \
6943 + CEDAR_CACHE_LINE_SIZE)
6944 +
6945 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
6946 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
6947 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
6948 + internal Registers */
6949 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
6950 +
6951 +#define CEDAR_CNFG4 CEDAR_BAR0
6952 +#define CEDAR_CNFG5 CEDAR_BAR1
6953 +#define CEDAR_CNFG6 CEDAR_BAR2
6954 +#define CEDAR_CNFG7 CEDAR_BAR3
6955 +
6956 +#define CEDAR_SUBSYS_VENDOR_ID 0
6957 +#define CEDAR_SUBSYSTEM_ID 0
6958 +#define CEDAR_CNFG8 0
6959 +#define CEDAR_CNFG9 0
6960 +#define CEDAR_CNFG10 0
6961 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
6962 + CEDAR_SUBSYSTEM_ID)
6963 +#define CEDAR_INT_LINE 1
6964 +#define CEDAR_INT_PIN 1
6965 +#define CEDAR_MIN_GNT 8
6966 +#define CEDAR_MAX_LAT 0x38
6967 +#define CEDAR_CNFG12 0
6968 +#define CEDAR_CNFG13 0
6969 +#define CEDAR_CNFG14 0
6970 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
6971 + (CEDAR_MIN_GNT << 16) | \
6972 + (CEDAR_INT_PIN << 8) | \
6973 + CEDAR_INT_LINE)
6974 +#define CEDAR_RETRY_LIMIT 0x80
6975 +#define CEDAR_TRDY_LIMIT 0x80
6976 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
6977 + CEDAR_TRDY_LIMIT)
6978 +#define PCI_PBAxC_R 0x0
6979 +#define PCI_PBAxC_RL 0x1
6980 +#define PCI_PBAxC_RM 0x2
6981 +#define SIZE_SHFT 2
6982 +#ifdef __MIPSEB__
6983 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
6984 + PCIPBAC_pp_m | \
6985 + PCIPBAC_sb_m | \
6986 + (SIZE_128MB << SIZE_SHFT) | \
6987 + PCIPBAC_p_m)
6988 +#else
6989 +
6990 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
6991 + PCIPBAC_pp_m | \
6992 + (SIZE_128MB << SIZE_SHFT) | \
6993 + PCIPBAC_p_m)
6994 +#endif
6995 +#define CEDAR_CNFG17 CEDAR_PBA0C
6996 +#define CEDAR_PBA0M 0x0
6997 +#define CEDAR_CNFG18 CEDAR_PBA0M
6998 +
6999 +#ifdef __MIPSEB__
7000 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
7001 + PCIPBAC_sb_m | \
7002 + PCIPBAC_msi_m)
7003 +#else
7004 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
7005 + PCIPBAC_msi_m)
7006 +#endif
7007 +#define CEDAR_CNFG19 CEDAR_PBA1C
7008 +#define CEDAR_PBA1M 0x0
7009 +#define CEDAR_CNFG20 CEDAR_PBA1M
7010 +
7011 +#ifdef __MIPSEB__
7012 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
7013 + PCIPBAC_sb_m | \
7014 + PCIPBAC_msi_m)
7015 +#else
7016 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
7017 + PCIPBAC_msi_m)
7018 +#endif
7019 +
7020 +#define CEDAR_CNFG21 CEDAR_PBA2C
7021 +#define CEDAR_PBA2M 0x18000000
7022 +#define CEDAR_CNFG22 CEDAR_PBA2M
7023 +
7024 +#ifdef __MIPSEB__
7025 +#define CEDAR_PBA3C PCIPBAC_sb_m
7026 +#else
7027 +#define CEDAR_PBA3C 0
7028 +#endif
7029 +
7030 +#define CEDAR_CNFG23 CEDAR_PBA3C
7031 +#define CEDAR_PBA3M 0
7032 +#define CEDAR_CNFG24 CEDAR_PBA3M
7033 +
7034 +#define PCITC_DTIMER_VAL 8
7035 +#define PCITC_RTIMER_VAL 0x10
7036 +
7037 +#endif //__IDT_RC32365_PCI_V_H__
7038 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
7039 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
7040 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-01-10 00:32:33.000000000 +0100
7041 @@ -0,0 +1,205 @@
7042 +/**************************************************************************
7043 + *
7044 + * BRIEF MODULE DESCRIPTION
7045 + * DMA register definition
7046 + *
7047 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7048 + *
7049 + * This program is free software; you can redistribute it and/or modify it
7050 + * under the terms of the GNU General Public License as published by the
7051 + * Free Software Foundation; either version 2 of the License, or (at your
7052 + * option) any later version.
7053 + *
7054 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7055 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7056 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7057 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7058 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7059 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7060 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7061 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7062 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7063 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7064 + *
7065 + * You should have received a copy of the GNU General Public License along
7066 + * with this program; if not, write to the Free Software Foundation, Inc.,
7067 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7068 + *
7069 + *
7070 + **************************************************************************
7071 + * May 2004 rkt, neb
7072 + *
7073 + * Initial Release
7074 + *
7075 + *
7076 + *
7077 + **************************************************************************
7078 + */
7079 +
7080 +#ifndef __IDT_DMA_H__
7081 +#define __IDT_DMA_H__
7082 +
7083 +enum
7084 +{
7085 + DMA0_PhysicalAddress = 0x18040000,
7086 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
7087 +
7088 + DMA0_VirtualAddress = 0xb8040000,
7089 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
7090 +} ;
7091 +
7092 +/*
7093 + * DMA descriptor (in physical memory).
7094 + */
7095 +
7096 +typedef struct DMAD_s
7097 +{
7098 + u32 control ; // Control. use DMAD_*
7099 + u32 ca ; // Current Address.
7100 + u32 devcs ; // Device control and status.
7101 + u32 link ; // Next descriptor in chain.
7102 +} volatile *DMAD_t ;
7103 +
7104 +enum
7105 +{
7106 + DMAD_size = sizeof (struct DMAD_s),
7107 + DMAD_count_b = 0, // in DMAD_t -> control
7108 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
7109 + DMAD_ds_b = 20, // in DMAD_t -> control
7110 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
7111 + DMAD_ds_ethRcv0_v = 0,
7112 + DMAD_ds_ethXmt0_v = 0,
7113 + DMAD_ds_memToFifo_v = 0,
7114 + DMAD_ds_fifoToMem_v = 0,
7115 + DMAD_ds_pciToMem_v = 0,
7116 + DMAD_ds_memToPci_v = 0,
7117 +
7118 + DMAD_devcmd_b = 22, // in DMAD_t -> control
7119 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
7120 + DMAD_devcmd_byte_v = 0, //memory-to-memory
7121 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
7122 + DMAD_devcmd_word_v = 2, //memory-to-memory
7123 + DMAD_devcmd_2words_v = 3, //memory-to-memory
7124 + DMAD_devcmd_4words_v = 4, //memory-to-memory
7125 + DMAD_devcmd_6words_v = 5, //memory-to-memory
7126 + DMAD_devcmd_8words_v = 6, //memory-to-memory
7127 + DMAD_devcmd_16words_v = 7, //memory-to-memory
7128 + DMAD_cof_b = 25, // chain on finished
7129 + DMAD_cof_m = 0x02000000, //
7130 + DMAD_cod_b = 26, // chain on done
7131 + DMAD_cod_m = 0x04000000, //
7132 + DMAD_iof_b = 27, // interrupt on finished
7133 + DMAD_iof_m = 0x08000000, //
7134 + DMAD_iod_b = 28, // interrupt on done
7135 + DMAD_iod_m = 0x10000000, //
7136 + DMAD_t_b = 29, // terminated
7137 + DMAD_t_m = 0x20000000, //
7138 + DMAD_d_b = 30, // done
7139 + DMAD_d_m = 0x40000000, //
7140 + DMAD_f_b = 31, // finished
7141 + DMAD_f_m = 0x80000000, //
7142 +} ;
7143 +
7144 +/*
7145 + * DMA register (within Internal Register Map).
7146 + */
7147 +
7148 +struct DMA_Chan_s
7149 +{
7150 + u32 dmac ; // Control.
7151 + u32 dmas ; // Status.
7152 + u32 dmasm ; // Mask.
7153 + u32 dmadptr ; // Descriptor pointer.
7154 + u32 dmandptr ; // Next descriptor pointer.
7155 +};
7156 +
7157 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
7158 +
7159 +//DMA_Channels use DMACH_count instead
7160 +
7161 +enum
7162 +{
7163 + DMAC_run_b = 0, //
7164 + DMAC_run_m = 0x00000001, //
7165 + DMAC_dm_b = 1, // done mask
7166 + DMAC_dm_m = 0x00000002, //
7167 + DMAC_mode_b = 2, //
7168 + DMAC_mode_m = 0x0000000c, //
7169 + DMAC_mode_auto_v = 0,
7170 + DMAC_mode_burst_v = 1,
7171 + DMAC_mode_transfer_v = 2, //usually used
7172 + DMAC_mode_reserved_v = 3,
7173 + DMAC_a_b = 4, //
7174 + DMAC_a_m = 0x00000010, //
7175 +
7176 + DMAS_f_b = 0, // finished (sticky)
7177 + DMAS_f_m = 0x00000001, //
7178 + DMAS_d_b = 1, // done (sticky)
7179 + DMAS_d_m = 0x00000002, //
7180 + DMAS_c_b = 2, // chain (sticky)
7181 + DMAS_c_m = 0x00000004, //
7182 + DMAS_e_b = 3, // error (sticky)
7183 + DMAS_e_m = 0x00000008, //
7184 + DMAS_h_b = 4, // halt (sticky)
7185 + DMAS_h_m = 0x00000010, //
7186 +
7187 + DMASM_f_b = 0, // finished (1=mask)
7188 + DMASM_f_m = 0x00000001, //
7189 + DMASM_d_b = 1, // done (1=mask)
7190 + DMASM_d_m = 0x00000002, //
7191 + DMASM_c_b = 2, // chain (1=mask)
7192 + DMASM_c_m = 0x00000004, //
7193 + DMASM_e_b = 3, // error (1=mask)
7194 + DMASM_e_m = 0x00000008, //
7195 + DMASM_h_b = 4, // halt (1=mask)
7196 + DMASM_h_m = 0x00000010, //
7197 +} ;
7198 +
7199 +/*
7200 + * DMA channel definitions
7201 + */
7202 +
7203 +enum
7204 +{
7205 + DMACH_ethRcv0 = 0,
7206 + DMACH_ethXmt0 = 1,
7207 + DMACH_memToFifo = 2,
7208 + DMACH_fifoToMem = 3,
7209 + DMACH_pciToMem = 4,
7210 + DMACH_memToPci = 5,
7211 +
7212 + DMACH_count //must be last
7213 +};
7214 +
7215 +
7216 +typedef struct DMAC_s
7217 +{
7218 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
7219 +} volatile *DMA_t ;
7220 +
7221 +
7222 +/*
7223 + * External DMA parameters
7224 +*/
7225 +
7226 +enum
7227 +{
7228 + DMADEVCMD_ts_b = 0, // ts field in devcmd
7229 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
7230 + DMADEVCMD_ts_byte_v = 0,
7231 + DMADEVCMD_ts_halfword_v = 1,
7232 + DMADEVCMD_ts_word_v = 2,
7233 + DMADEVCMD_ts_2word_v = 3,
7234 + DMADEVCMD_ts_4word_v = 4,
7235 + DMADEVCMD_ts_6word_v = 5,
7236 + DMADEVCMD_ts_8word_v = 6,
7237 + DMADEVCMD_ts_16word_v = 7
7238 +};
7239 +
7240 +
7241 +#endif // __IDT_DMA_H__
7242 +
7243 +
7244 +
7245 +
7246 +
7247 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
7248 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
7249 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-01-10 00:32:33.000000000 +0100
7250 @@ -0,0 +1,89 @@
7251 +/**************************************************************************
7252 + *
7253 + * BRIEF MODULE DESCRIPTION
7254 + * Definitions for DMA controller.
7255 + *
7256 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7257 + *
7258 + * This program is free software; you can redistribute it and/or modify it
7259 + * under the terms of the GNU General Public License as published by the
7260 + * Free Software Foundation; either version 2 of the License, or (at your
7261 + * option) any later version.
7262 + *
7263 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7264 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7265 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7266 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7267 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7268 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7269 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7270 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7271 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7272 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7273 + *
7274 + * You should have received a copy of the GNU General Public License along
7275 + * with this program; if not, write to the Free Software Foundation, Inc.,
7276 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7277 + *
7278 + *
7279 + **************************************************************************
7280 + * May 2004 rkt, neb.
7281 + *
7282 + * Initial Release
7283 + *
7284 + *
7285 + *
7286 + **************************************************************************
7287 + */
7288 +
7289 +#ifndef __IDT_DMA_V_H__
7290 +#define __IDT_DMA_V_H__
7291 +
7292 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
7293 +#include <asm/idt-boards/rc32434/rc32434.h>
7294 +
7295 +#define DMA_CHAN_OFFSET 0x14
7296 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
7297 +#define DMA_COUNT(count) \
7298 + ((count) & DMAD_count_m)
7299 +
7300 +#define DMA_HALT_TIMEOUT 500
7301 +
7302 +
7303 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
7304 +{
7305 + int timeout=1;
7306 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
7307 + rc32434_writel(0, &ch->dmac);
7308 +
7309 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
7310 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
7311 + rc32434_writel(0, &ch->dmas);
7312 + break;
7313 + }
7314 + }
7315 +
7316 + }
7317 +
7318 + return timeout ? 0 : 1;
7319 +}
7320 +
7321 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
7322 +{
7323 + rc32434_writel(0, &ch->dmandptr);
7324 + rc32434_writel(dma_addr, &ch->dmadptr);
7325 +}
7326 +
7327 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
7328 +{
7329 + rc32434_writel(dma_addr, &ch->dmandptr);
7330 +}
7331 +
7332 +#endif // __IDT_DMA_V_H__
7333 +
7334 +
7335 +
7336 +
7337 +
7338 +
7339 +
7340 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
7341 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
7342 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-01-10 00:32:33.000000000 +0100
7343 @@ -0,0 +1,333 @@
7344 +/**************************************************************************
7345 + *
7346 + * BRIEF MODULE DESCRIPTION
7347 + * Ethernet register definition
7348 + *
7349 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7350 + *
7351 + * This program is free software; you can redistribute it and/or modify it
7352 + * under the terms of the GNU General Public License as published by the
7353 + * Free Software Foundation; either version 2 of the License, or (at your
7354 + * option) any later version.
7355 + *
7356 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7357 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7358 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7359 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7360 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7361 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7362 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7363 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7364 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7365 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7366 + *
7367 + * You should have received a copy of the GNU General Public License along
7368 + * with this program; if not, write to the Free Software Foundation, Inc.,
7369 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7370 + *
7371 + *
7372 + **************************************************************************
7373 + * May 2004 rkt, neb.
7374 + *
7375 + * Initial Release
7376 + *
7377 + *
7378 + *
7379 + **************************************************************************
7380 + */
7381 +
7382 +#ifndef __IDT_ETH_H__
7383 +#define __IDT_ETH_H__
7384 +
7385 +
7386 +enum
7387 +{
7388 + ETH0_PhysicalAddress = 0x18060000,
7389 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
7390 +
7391 + ETH0_VirtualAddress = 0xb8060000,
7392 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
7393 +} ;
7394 +
7395 +typedef struct
7396 +{
7397 + u32 ethintfc ;
7398 + u32 ethfifott ;
7399 + u32 etharc ;
7400 + u32 ethhash0 ;
7401 + u32 ethhash1 ;
7402 + u32 ethu0 [4] ; // Reserved.
7403 + u32 ethpfs ;
7404 + u32 ethmcp ;
7405 + u32 eth_u1 [10] ; // Reserved.
7406 + u32 ethspare ;
7407 + u32 eth_u2 [42] ; // Reserved.
7408 + u32 ethsal0 ;
7409 + u32 ethsah0 ;
7410 + u32 ethsal1 ;
7411 + u32 ethsah1 ;
7412 + u32 ethsal2 ;
7413 + u32 ethsah2 ;
7414 + u32 ethsal3 ;
7415 + u32 ethsah3 ;
7416 + u32 ethrbc ;
7417 + u32 ethrpc ;
7418 + u32 ethrupc ;
7419 + u32 ethrfc ;
7420 + u32 ethtbc ;
7421 + u32 ethgpf ;
7422 + u32 eth_u9 [50] ; // Reserved.
7423 + u32 ethmac1 ;
7424 + u32 ethmac2 ;
7425 + u32 ethipgt ;
7426 + u32 ethipgr ;
7427 + u32 ethclrt ;
7428 + u32 ethmaxf ;
7429 + u32 eth_u10 ; // Reserved.
7430 + u32 ethmtest ;
7431 + u32 miimcfg ;
7432 + u32 miimcmd ;
7433 + u32 miimaddr ;
7434 + u32 miimwtd ;
7435 + u32 miimrdd ;
7436 + u32 miimind ;
7437 + u32 eth_u11 ; // Reserved.
7438 + u32 eth_u12 ; // Reserved.
7439 + u32 ethcfsa0 ;
7440 + u32 ethcfsa1 ;
7441 + u32 ethcfsa2 ;
7442 +} volatile *ETH_t;
7443 +
7444 +enum
7445 +{
7446 + ETHINTFC_en_b = 0,
7447 + ETHINTFC_en_m = 0x00000001,
7448 + ETHINTFC_its_b = 1,
7449 + ETHINTFC_its_m = 0x00000002,
7450 + ETHINTFC_rip_b = 2,
7451 + ETHINTFC_rip_m = 0x00000004,
7452 + ETHINTFC_jam_b = 3,
7453 + ETHINTFC_jam_m = 0x00000008,
7454 + ETHINTFC_ovr_b = 4,
7455 + ETHINTFC_ovr_m = 0x00000010,
7456 + ETHINTFC_und_b = 5,
7457 + ETHINTFC_und_m = 0x00000020,
7458 +
7459 + ETHFIFOTT_tth_b = 0,
7460 + ETHFIFOTT_tth_m = 0x0000007f,
7461 +
7462 + ETHARC_pro_b = 0,
7463 + ETHARC_pro_m = 0x00000001,
7464 + ETHARC_am_b = 1,
7465 + ETHARC_am_m = 0x00000002,
7466 + ETHARC_afm_b = 2,
7467 + ETHARC_afm_m = 0x00000004,
7468 + ETHARC_ab_b = 3,
7469 + ETHARC_ab_m = 0x00000008,
7470 +
7471 + ETHSAL_byte5_b = 0,
7472 + ETHSAL_byte5_m = 0x000000ff,
7473 + ETHSAL_byte4_b = 8,
7474 + ETHSAL_byte4_m = 0x0000ff00,
7475 + ETHSAL_byte3_b = 16,
7476 + ETHSAL_byte3_m = 0x00ff0000,
7477 + ETHSAL_byte2_b = 24,
7478 + ETHSAL_byte2_m = 0xff000000,
7479 +
7480 + ETHSAH_byte1_b = 0,
7481 + ETHSAH_byte1_m = 0x000000ff,
7482 + ETHSAH_byte0_b = 8,
7483 + ETHSAH_byte0_m = 0x0000ff00,
7484 +
7485 + ETHGPF_ptv_b = 0,
7486 + ETHGPF_ptv_m = 0x0000ffff,
7487 +
7488 + ETHPFS_pfd_b = 0,
7489 + ETHPFS_pfd_m = 0x00000001,
7490 +
7491 + ETHCFSA0_cfsa4_b = 0,
7492 + ETHCFSA0_cfsa4_m = 0x000000ff,
7493 + ETHCFSA0_cfsa5_b = 8,
7494 + ETHCFSA0_cfsa5_m = 0x0000ff00,
7495 +
7496 + ETHCFSA1_cfsa2_b = 0,
7497 + ETHCFSA1_cfsa2_m = 0x000000ff,
7498 + ETHCFSA1_cfsa3_b = 8,
7499 + ETHCFSA1_cfsa3_m = 0x0000ff00,
7500 +
7501 + ETHCFSA2_cfsa0_b = 0,
7502 + ETHCFSA2_cfsa0_m = 0x000000ff,
7503 + ETHCFSA2_cfsa1_b = 8,
7504 + ETHCFSA2_cfsa1_m = 0x0000ff00,
7505 +
7506 + ETHMAC1_re_b = 0,
7507 + ETHMAC1_re_m = 0x00000001,
7508 + ETHMAC1_paf_b = 1,
7509 + ETHMAC1_paf_m = 0x00000002,
7510 + ETHMAC1_rfc_b = 2,
7511 + ETHMAC1_rfc_m = 0x00000004,
7512 + ETHMAC1_tfc_b = 3,
7513 + ETHMAC1_tfc_m = 0x00000008,
7514 + ETHMAC1_lb_b = 4,
7515 + ETHMAC1_lb_m = 0x00000010,
7516 + ETHMAC1_mr_b = 31,
7517 + ETHMAC1_mr_m = 0x80000000,
7518 +
7519 + ETHMAC2_fd_b = 0,
7520 + ETHMAC2_fd_m = 0x00000001,
7521 + ETHMAC2_flc_b = 1,
7522 + ETHMAC2_flc_m = 0x00000002,
7523 + ETHMAC2_hfe_b = 2,
7524 + ETHMAC2_hfe_m = 0x00000004,
7525 + ETHMAC2_dc_b = 3,
7526 + ETHMAC2_dc_m = 0x00000008,
7527 + ETHMAC2_cen_b = 4,
7528 + ETHMAC2_cen_m = 0x00000010,
7529 + ETHMAC2_pe_b = 5,
7530 + ETHMAC2_pe_m = 0x00000020,
7531 + ETHMAC2_vpe_b = 6,
7532 + ETHMAC2_vpe_m = 0x00000040,
7533 + ETHMAC2_ape_b = 7,
7534 + ETHMAC2_ape_m = 0x00000080,
7535 + ETHMAC2_ppe_b = 8,
7536 + ETHMAC2_ppe_m = 0x00000100,
7537 + ETHMAC2_lpe_b = 9,
7538 + ETHMAC2_lpe_m = 0x00000200,
7539 + ETHMAC2_nb_b = 12,
7540 + ETHMAC2_nb_m = 0x00001000,
7541 + ETHMAC2_bp_b = 13,
7542 + ETHMAC2_bp_m = 0x00002000,
7543 + ETHMAC2_ed_b = 14,
7544 + ETHMAC2_ed_m = 0x00004000,
7545 +
7546 + ETHIPGT_ipgt_b = 0,
7547 + ETHIPGT_ipgt_m = 0x0000007f,
7548 +
7549 + ETHIPGR_ipgr2_b = 0,
7550 + ETHIPGR_ipgr2_m = 0x0000007f,
7551 + ETHIPGR_ipgr1_b = 8,
7552 + ETHIPGR_ipgr1_m = 0x00007f00,
7553 +
7554 + ETHCLRT_maxret_b = 0,
7555 + ETHCLRT_maxret_m = 0x0000000f,
7556 + ETHCLRT_colwin_b = 8,
7557 + ETHCLRT_colwin_m = 0x00003f00,
7558 +
7559 + ETHMAXF_maxf_b = 0,
7560 + ETHMAXF_maxf_m = 0x0000ffff,
7561 +
7562 + ETHMTEST_tb_b = 2,
7563 + ETHMTEST_tb_m = 0x00000004,
7564 +
7565 + ETHMCP_div_b = 0,
7566 + ETHMCP_div_m = 0x000000ff,
7567 +
7568 + MIIMCFG_rsv_b = 0,
7569 + MIIMCFG_rsv_m = 0x0000000c,
7570 +
7571 + MIIMCMD_rd_b = 0,
7572 + MIIMCMD_rd_m = 0x00000001,
7573 + MIIMCMD_scn_b = 1,
7574 + MIIMCMD_scn_m = 0x00000002,
7575 +
7576 + MIIMADDR_regaddr_b = 0,
7577 + MIIMADDR_regaddr_m = 0x0000001f,
7578 + MIIMADDR_phyaddr_b = 8,
7579 + MIIMADDR_phyaddr_m = 0x00001f00,
7580 +
7581 + MIIMWTD_wdata_b = 0,
7582 + MIIMWTD_wdata_m = 0x0000ffff,
7583 +
7584 + MIIMRDD_rdata_b = 0,
7585 + MIIMRDD_rdata_m = 0x0000ffff,
7586 +
7587 + MIIMIND_bsy_b = 0,
7588 + MIIMIND_bsy_m = 0x00000001,
7589 + MIIMIND_scn_b = 1,
7590 + MIIMIND_scn_m = 0x00000002,
7591 + MIIMIND_nv_b = 2,
7592 + MIIMIND_nv_m = 0x00000004,
7593 +
7594 +} ;
7595 +
7596 +/*
7597 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
7598 + */
7599 +enum
7600 +{
7601 + ETHRX_fd_b = 0,
7602 + ETHRX_fd_m = 0x00000001,
7603 + ETHRX_ld_b = 1,
7604 + ETHRX_ld_m = 0x00000002,
7605 + ETHRX_rok_b = 2,
7606 + ETHRX_rok_m = 0x00000004,
7607 + ETHRX_fm_b = 3,
7608 + ETHRX_fm_m = 0x00000008,
7609 + ETHRX_mp_b = 4,
7610 + ETHRX_mp_m = 0x00000010,
7611 + ETHRX_bp_b = 5,
7612 + ETHRX_bp_m = 0x00000020,
7613 + ETHRX_vlt_b = 6,
7614 + ETHRX_vlt_m = 0x00000040,
7615 + ETHRX_cf_b = 7,
7616 + ETHRX_cf_m = 0x00000080,
7617 + ETHRX_ovr_b = 8,
7618 + ETHRX_ovr_m = 0x00000100,
7619 + ETHRX_crc_b = 9,
7620 + ETHRX_crc_m = 0x00000200,
7621 + ETHRX_cv_b = 10,
7622 + ETHRX_cv_m = 0x00000400,
7623 + ETHRX_db_b = 11,
7624 + ETHRX_db_m = 0x00000800,
7625 + ETHRX_le_b = 12,
7626 + ETHRX_le_m = 0x00001000,
7627 + ETHRX_lor_b = 13,
7628 + ETHRX_lor_m = 0x00002000,
7629 + ETHRX_ces_b = 14,
7630 + ETHRX_ces_m = 0x00004000,
7631 + ETHRX_length_b = 16,
7632 + ETHRX_length_m = 0xffff0000,
7633 +
7634 + ETHTX_fd_b = 0,
7635 + ETHTX_fd_m = 0x00000001,
7636 + ETHTX_ld_b = 1,
7637 + ETHTX_ld_m = 0x00000002,
7638 + ETHTX_oen_b = 2,
7639 + ETHTX_oen_m = 0x00000004,
7640 + ETHTX_pen_b = 3,
7641 + ETHTX_pen_m = 0x00000008,
7642 + ETHTX_cen_b = 4,
7643 + ETHTX_cen_m = 0x00000010,
7644 + ETHTX_hen_b = 5,
7645 + ETHTX_hen_m = 0x00000020,
7646 + ETHTX_tok_b = 6,
7647 + ETHTX_tok_m = 0x00000040,
7648 + ETHTX_mp_b = 7,
7649 + ETHTX_mp_m = 0x00000080,
7650 + ETHTX_bp_b = 8,
7651 + ETHTX_bp_m = 0x00000100,
7652 + ETHTX_und_b = 9,
7653 + ETHTX_und_m = 0x00000200,
7654 + ETHTX_of_b = 10,
7655 + ETHTX_of_m = 0x00000400,
7656 + ETHTX_ed_b = 11,
7657 + ETHTX_ed_m = 0x00000800,
7658 + ETHTX_ec_b = 12,
7659 + ETHTX_ec_m = 0x00001000,
7660 + ETHTX_lc_b = 13,
7661 + ETHTX_lc_m = 0x00002000,
7662 + ETHTX_td_b = 14,
7663 + ETHTX_td_m = 0x00004000,
7664 + ETHTX_crc_b = 15,
7665 + ETHTX_crc_m = 0x00008000,
7666 + ETHTX_le_b = 16,
7667 + ETHTX_le_m = 0x00010000,
7668 + ETHTX_cc_b = 17,
7669 + ETHTX_cc_m = 0x001E0000,
7670 +} ;
7671 +
7672 +#endif // __IDT_ETH_H__
7673 +
7674 +
7675 +
7676 +
7677 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
7678 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
7679 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-01-10 00:32:33.000000000 +0100
7680 @@ -0,0 +1,77 @@
7681 +/**************************************************************************
7682 + *
7683 + * BRIEF MODULE DESCRIPTION
7684 + * Ethernet register definition
7685 + *
7686 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7687 + *
7688 + * This program is free software; you can redistribute it and/or modify it
7689 + * under the terms of the GNU General Public License as published by the
7690 + * Free Software Foundation; either version 2 of the License, or (at your
7691 + * option) any later version.
7692 + *
7693 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7694 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7695 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7696 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7697 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7698 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7699 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7700 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7701 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7702 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7703 + *
7704 + * You should have received a copy of the GNU General Public License along
7705 + * with this program; if not, write to the Free Software Foundation, Inc.,
7706 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7707 + *
7708 + *
7709 + **************************************************************************
7710 + * May 2004 rkt, neb.
7711 + *
7712 + * Initial Release
7713 + *
7714 + *
7715 + *
7716 + **************************************************************************
7717 + */
7718 +
7719 +#ifndef __IDT_ETH_V_H__
7720 +#define __IDT_ETH_V_H__
7721 +
7722 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
7723 +
7724 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
7725 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
7726 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
7727 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
7728 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
7729 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
7730 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
7731 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
7732 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
7733 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
7734 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
7735 +
7736 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
7737 +
7738 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
7739 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
7740 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
7741 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
7742 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
7743 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
7744 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
7745 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
7746 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
7747 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
7748 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
7749 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
7750 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
7751 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
7752 +#endif // __IDT_ETH_V_H__
7753 +
7754 +
7755 +
7756 +
7757 +
7758 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
7759 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
7760 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-01-10 00:32:33.000000000 +0100
7761 @@ -0,0 +1,167 @@
7762 +/**************************************************************************
7763 + *
7764 + * BRIEF MODULE DESCRIPTION
7765 + * GPIO register definition
7766 + *
7767 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7768 + *
7769 + * This program is free software; you can redistribute it and/or modify it
7770 + * under the terms of the GNU General Public License as published by the
7771 + * Free Software Foundation; either version 2 of the License, or (at your
7772 + * option) any later version.
7773 + *
7774 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7775 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7776 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7777 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7778 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7779 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7780 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7781 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7782 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7783 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7784 + *
7785 + * You should have received a copy of the GNU General Public License along
7786 + * with this program; if not, write to the Free Software Foundation, Inc.,
7787 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7788 + *
7789 + *
7790 + **************************************************************************
7791 + * May 2004 rkt, neb.
7792 + *
7793 + * Initial Release
7794 + *
7795 + *
7796 + *
7797 + **************************************************************************
7798 + */
7799 +
7800 +#ifndef __IDT_GPIO_H__
7801 +#define __IDT_GPIO_H__
7802 +
7803 +enum
7804 +{
7805 + GPIO0_PhysicalAddress = 0x18050000,
7806 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
7807 +
7808 + GPIO0_VirtualAddress = 0xb8050000,
7809 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
7810 +} ;
7811 +
7812 +typedef struct
7813 +{
7814 + u32 gpiofunc; /* GPIO Function Register
7815 + * gpiofunc[x]==0 bit = gpio
7816 + * func[x]==1 bit = altfunc
7817 + */
7818 + u32 gpiocfg; /* GPIO Configuration Register
7819 + * gpiocfg[x]==0 bit = input
7820 + * gpiocfg[x]==1 bit = output
7821 + */
7822 + u32 gpiod; /* GPIO Data Register
7823 + * gpiod[x] read/write gpio pinX status
7824 + */
7825 + u32 gpioilevel; /* GPIO Interrupt Status Register
7826 + * interrupt level (see gpioistat)
7827 + */
7828 + u32 gpioistat; /* Gpio Interrupt Status Register
7829 + * istat[x] = (gpiod[x] == level[x])
7830 + * cleared in ISR (STICKY bits)
7831 + */
7832 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
7833 +} volatile * GPIO_t ;
7834 +
7835 +typedef enum
7836 +{
7837 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
7838 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
7839 + GPIO_input_v = 0, // gpiocfg use pin as input.
7840 + GPIO_output_v = 1, // gpiocfg use pin as output.
7841 + GPIO_pin0_b = 0,
7842 + GPIO_pin0_m = 0x00000001,
7843 + GPIO_pin1_b = 1,
7844 + GPIO_pin1_m = 0x00000002,
7845 + GPIO_pin2_b = 2,
7846 + GPIO_pin2_m = 0x00000004,
7847 + GPIO_pin3_b = 3,
7848 + GPIO_pin3_m = 0x00000008,
7849 + GPIO_pin4_b = 4,
7850 + GPIO_pin4_m = 0x00000010,
7851 + GPIO_pin5_b = 5,
7852 + GPIO_pin5_m = 0x00000020,
7853 + GPIO_pin6_b = 6,
7854 + GPIO_pin6_m = 0x00000040,
7855 + GPIO_pin7_b = 7,
7856 + GPIO_pin7_m = 0x00000080,
7857 + GPIO_pin8_b = 8,
7858 + GPIO_pin8_m = 0x00000100,
7859 + GPIO_pin9_b = 9,
7860 + GPIO_pin9_m = 0x00000200,
7861 + GPIO_pin10_b = 10,
7862 + GPIO_pin10_m = 0x00000400,
7863 + GPIO_pin11_b = 11,
7864 + GPIO_pin11_m = 0x00000800,
7865 + GPIO_pin12_b = 12,
7866 + GPIO_pin12_m = 0x00001000,
7867 + GPIO_pin13_b = 13,
7868 + GPIO_pin13_m = 0x00002000,
7869 +
7870 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
7871 +
7872 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
7873 + GPIO_u0sout_m = GPIO_pin0_m,
7874 + GPIO_u0sout_cfg_v = GPIO_output_v,
7875 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
7876 + GPIO_u0sinp_m = GPIO_pin1_m,
7877 + GPIO_u0sinp_cfg_v = GPIO_input_v,
7878 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
7879 + GPIO_u0rtsn_m = GPIO_pin2_m,
7880 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
7881 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
7882 + GPIO_u0ctsn_m = GPIO_pin3_m,
7883 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
7884 +
7885 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
7886 + GPIO_maddr22_m = GPIO_pin4_m,
7887 + GPIO_maddr22_cfg_v = GPIO_output_v,
7888 +
7889 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
7890 + GPIO_maddr23_m = GPIO_pin5_m,
7891 + GPIO_maddr23_cfg_v = GPIO_output_v,
7892 +
7893 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
7894 + GPIO_maddr24_m = GPIO_pin6_m,
7895 + GPIO_maddr24_cfg_v = GPIO_output_v,
7896 +
7897 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
7898 + GPIO_maddr25_m = GPIO_pin7_m,
7899 + GPIO_maddr25_cfg_v = GPIO_output_v,
7900 +
7901 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
7902 + GPIO_cpudmadebug_m = GPIO_pin8_m,
7903 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
7904 +
7905 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
7906 + GPIO_pcireq4_m = GPIO_pin9_m,
7907 + GPIO_pcireq4_cfg_v = GPIO_input_v,
7908 +
7909 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
7910 + GPIO_pcigrant4_m = GPIO_pin10_m,
7911 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
7912 +
7913 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
7914 + GPIO_pcireq5_m = GPIO_pin11_m,
7915 + GPIO_pcireq5_cfg_v = GPIO_input_v,
7916 +
7917 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
7918 + GPIO_pcigrant5_m = GPIO_pin12_m,
7919 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
7920 +
7921 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
7922 + GPIO_pcimuintn_m = GPIO_pin13_m,
7923 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
7924 +
7925 +} GPIO_DEFS_t;
7926 +
7927 +#endif // __IDT_GPIO_H__
7928 +
7929 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h
7930 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
7931 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-01-10 00:32:33.000000000 +0100
7932 @@ -0,0 +1,199 @@
7933 + /**************************************************************************
7934 + *
7935 + * BRIEF MODULE DESCRIPTION
7936 + * Definitions for IDT RC32434 CPU
7937 + *
7938 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7939 + *
7940 + * This program is free software; you can redistribute it and/or modify it
7941 + * under the terms of the GNU General Public License as published by the
7942 + * Free Software Foundation; either version 2 of the License, or (at your
7943 + * option) any later version.
7944 + *
7945 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7946 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7947 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7948 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7949 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7950 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7951 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7952 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7953 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7954 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7955 + *
7956 + * You should have received a copy of the GNU General Public License along
7957 + * with this program; if not, write to the Free Software Foundation, Inc.,
7958 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7959 + *
7960 + *
7961 + **************************************************************************
7962 + * May 2004 rkt, neb.
7963 + *
7964 + * Initial Release
7965 + *
7966 + *
7967 + *
7968 + **************************************************************************
7969 + */
7970 +
7971 +#ifndef _RC32434_H_
7972 +#define _RC32434_H_
7973 +
7974 +#include <linux/config.h>
7975 +#include <linux/delay.h>
7976 +#include <asm/io.h>
7977 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
7978 +
7979 +#define RC32434_REG_BASE 0x18000000
7980 +
7981 +
7982 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
7983 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
7984 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
7985 +
7986 +#define IDT_CLOCK_MULT 2
7987 +#define MIPS_CPU_TIMER_IRQ 7
7988 +/* Interrupt Controller */
7989 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
7990 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
7991 +#define IC_GROUP_OFFSET 0x0C
7992 +#define RTC_BASE 0xBA001FF0
7993 +
7994 +#define NUM_INTR_GROUPS 5
7995 +/* 16550 UARTs */
7996 +
7997 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
7998 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
7999 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
8000 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
8001 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
8002 +
8003 +#ifdef __MIPSEB__
8004 +
8005 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
8006 +#define EB434_UART1_BASE (0x19800003)
8007 +
8008 +#else
8009 +
8010 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
8011 +#define EB434_UART1_BASE (0x19800000)
8012 +
8013 +#endif
8014 +
8015 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
8016 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
8017 +
8018 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
8019 +
8020 +/* cpu pipeline flush */
8021 +static inline void rc32434_sync(void)
8022 +{
8023 + __asm__ volatile ("sync");
8024 +}
8025 +
8026 +static inline void rc32434_sync_udelay(int us)
8027 +{
8028 + __asm__ volatile ("sync");
8029 + udelay(us);
8030 +}
8031 +
8032 +static inline void rc32434_sync_delay(int ms)
8033 +{
8034 + __asm__ volatile ("sync");
8035 + mdelay(ms);
8036 +}
8037 +
8038 +
8039 +
8040 +/*
8041 + * Macros to access internal RC32434 registers. No byte
8042 + * swapping should be done when accessing the internal
8043 + * registers.
8044 + */
8045 +
8046 +#define rc32434_readb __raw_readb
8047 +#define rc32434_readw __raw_readw
8048 +#define rc32434_readl __raw_readl
8049 +
8050 +#define rc32434_writeb __raw_writeb
8051 +#define rc32434_writew __raw_writew
8052 +#define rc32434_writel __raw_writel
8053 +
8054 +#if 0
8055 +static inline u8 rc32434_readb(unsigned long pa)
8056 +{
8057 + return *((volatile u8 *)KSEG1ADDR(pa));
8058 +}
8059 +static inline u16 rc32434_readw(unsigned long pa)
8060 +{
8061 + return *((volatile u16 *)KSEG1ADDR(pa));
8062 +}
8063 +static inline u32 rc32434_readl(unsigned long pa)
8064 +{
8065 + return *((volatile u32 *)KSEG1ADDR(pa));
8066 +}
8067 +static inline void rc32434_writeb(u8 val, unsigned long pa)
8068 +{
8069 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
8070 +}
8071 +static inline void rc32434_writew(u16 val, unsigned long pa)
8072 +{
8073 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
8074 +}
8075 +static inline void rc32434_writel(u32 val, unsigned long pa)
8076 +{
8077 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
8078 +}
8079 +
8080 +#endif
8081 +
8082 +
8083 +/*
8084 + * C access to CLZ and CLO instructions
8085 + * (count leading zeroes/ones).
8086 + */
8087 +static inline int rc32434_clz(unsigned long val)
8088 +{
8089 + int ret;
8090 + __asm__ volatile (
8091 + ".set\tnoreorder\n\t"
8092 + ".set\tnoat\n\t"
8093 + ".set\tmips32\n\t"
8094 + "clz\t%0,%1\n\t"
8095 + ".set\tmips0\n\t"
8096 + ".set\tat\n\t"
8097 + ".set\treorder"
8098 + : "=r" (ret)
8099 + : "r" (val));
8100 +
8101 + return ret;
8102 +}
8103 +static inline int rc32434_clo(unsigned long val)
8104 +{
8105 + int ret;
8106 + __asm__ volatile (
8107 + ".set\tnoreorder\n\t"
8108 + ".set\tnoat\n\t"
8109 + ".set\tmips32\n\t"
8110 + "clo\t%0,%1\n\t"
8111 + ".set\tmips0\n\t"
8112 + ".set\tat\n\t"
8113 + ".set\treorder"
8114 + : "=r" (ret)
8115 + : "r" (val));
8116 +
8117 + return ret;
8118 +}
8119 +#endif /* _RC32434_H_ */
8120 +
8121 +
8122 +
8123 +
8124 +
8125 +
8126 +
8127 +
8128 +
8129 +
8130 +
8131 +
8132 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
8133 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
8134 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-01-10 00:32:33.000000000 +0100
8135 @@ -0,0 +1,90 @@
8136 +/**************************************************************************
8137 + *
8138 + * BRIEF MODULE DESCRIPTION
8139 + * System Integrity register definition
8140 + *
8141 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8142 + *
8143 + * This program is free software; you can redistribute it and/or modify it
8144 + * under the terms of the GNU General Public License as published by the
8145 + * Free Software Foundation; either version 2 of the License, or (at your
8146 + * option) any later version.
8147 + *
8148 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8149 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8150 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8151 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8152 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8153 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8154 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8155 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8156 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8157 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8158 + *
8159 + * You should have received a copy of the GNU General Public License along
8160 + * with this program; if not, write to the Free Software Foundation, Inc.,
8161 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8162 + *
8163 + *
8164 + **************************************************************************
8165 + * May 2004 rkt, neb
8166 + *
8167 + * Initial Release
8168 + *
8169 + *
8170 + *
8171 + **************************************************************************
8172 + */
8173 +
8174 +#ifndef __IDT_INTEG_H__
8175 +#define __IDT_INTEG_H__
8176 +
8177 +enum
8178 +{
8179 + INTEG0_PhysicalAddress = 0x18030000,
8180 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
8181 +
8182 + INTEG0_VirtualAddress = 0xB8030000,
8183 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
8184 +} ;
8185 +
8186 +// if you are looking for CEA, try rst.h
8187 +typedef struct
8188 +{
8189 + u32 filler [0xc] ; // 0x30 bytes unused.
8190 + u32 errcs ; // sticky use ERRCS_
8191 + u32 wtcount ; // Watchdog timer count reg.
8192 + u32 wtcompare ; // Watchdog timer timeout value.
8193 + u32 wtc ; // Watchdog timer control. use WTC_
8194 +} volatile *INTEG_t ;
8195 +
8196 +enum
8197 +{
8198 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
8199 + ERRCS_wto_m = 0x00000001,
8200 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
8201 + ERRCS_wne_m = 0x00000002,
8202 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
8203 + ERRCS_ucw_m = 0x00000004,
8204 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
8205 + ERRCS_ucr_m = 0x00000008,
8206 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
8207 + ERRCS_upw_m = 0x00000010,
8208 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
8209 + ERRCS_upr_m = 0x00000020,
8210 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
8211 + ERRCS_udw_m = 0x00000040,
8212 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
8213 + ERRCS_udr_m = 0x00000080,
8214 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
8215 + ERRCS_sae_m = 0x00000100,
8216 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
8217 + ERRCS_wre_m = 0x00000200,
8218 +
8219 + WTC_en_b = 0, // In INTEG_t -> wtc
8220 + WTC_en_m = 0x00000001,
8221 + WTC_to_b = 1, // In INTEG_t -> wtc
8222 + WTC_to_m = 0x00000002,
8223 +} ;
8224 +
8225 +#endif // __IDT_INTEG_H__
8226 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
8227 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
8228 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-01-10 00:32:33.000000000 +0100
8229 @@ -0,0 +1,174 @@
8230 +/**************************************************************************
8231 + *
8232 + * BRIEF MODULE DESCRIPTION
8233 + * Interrupt Controller register definition.
8234 + *
8235 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8236 + *
8237 + * This program is free software; you can redistribute it and/or modify it
8238 + * under the terms of the GNU General Public License as published by the
8239 + * Free Software Foundation; either version 2 of the License, or (at your
8240 + * option) any later version.
8241 + *
8242 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8243 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8244 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8245 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8246 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8247 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8248 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8249 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8250 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8251 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8252 + *
8253 + * You should have received a copy of the GNU General Public License along
8254 + * with this program; if not, write to the Free Software Foundation, Inc.,
8255 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8256 + *
8257 + *
8258 + **************************************************************************
8259 + * May 2004 rkt, neb.
8260 + *
8261 + * Initial Release
8262 + *
8263 + *
8264 + *
8265 + **************************************************************************
8266 + */
8267 +
8268 +#ifndef __IDT_INT_H__
8269 +#define __IDT_INT_H__
8270 +
8271 +enum
8272 +{
8273 + INT0_PhysicalAddress = 0x18038000,
8274 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
8275 +
8276 + INT0_VirtualAddress = 0xB8038000,
8277 + INT_VirtualAddress = INT0_VirtualAddress, // Default
8278 +} ;
8279 +
8280 +struct INT_s
8281 +{
8282 + u32 ipend ; //Pending interrupts. use INT?_
8283 + u32 itest ; //Test bits. use INT?_
8284 + u32 imask ; //Interrupt disabled when set. use INT?_
8285 +} ;
8286 +
8287 +enum
8288 +{
8289 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
8290 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
8291 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
8292 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
8293 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
8294 +
8295 + IPEND_count, // must be last (used in loops)
8296 + IPEND_min = IPEND2 // min IPEND (used in loops)
8297 +};
8298 +
8299 +typedef struct INTC_s
8300 +{
8301 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
8302 + u32 nmips ; // use NMIPS_
8303 +} volatile *INT_t ;
8304 +
8305 +enum
8306 +{
8307 + INT2_timer0_b = 0,
8308 + INT2_timer0_m = 0x00000001,
8309 + INT2_timer1_b = 1,
8310 + INT2_timer1_m = 0x00000002,
8311 + INT2_timer2_b = 2,
8312 + INT2_timer2_m = 0x00000004,
8313 + INT2_refresh_b = 3,
8314 + INT2_refresh_m = 0x00000008,
8315 + INT2_watchdogTimeout_b = 4,
8316 + INT2_watchdogTimeout_m = 0x00000010,
8317 + INT2_undecodedCpuWrite_b = 5,
8318 + INT2_undecodedCpuWrite_m = 0x00000020,
8319 + INT2_undecodedCpuRead_b = 6,
8320 + INT2_undecodedCpuRead_m = 0x00000040,
8321 + INT2_undecodedPciWrite_b = 7,
8322 + INT2_undecodedPciWrite_m = 0x00000080,
8323 + INT2_undecodedPciRead_b = 8,
8324 + INT2_undecodedPciRead_m = 0x00000100,
8325 + INT2_undecodedDmaWrite_b = 9,
8326 + INT2_undecodedDmaWrite_m = 0x00000200,
8327 + INT2_undecodedDmaRead_b = 10,
8328 + INT2_undecodedDmaRead_m = 0x00000400,
8329 + INT2_ipBusSlaveAckError_b = 11,
8330 + INT2_ipBusSlaveAckError_m = 0x00000800,
8331 +
8332 + INT3_dmaChannel0_b = 0,
8333 + INT3_dmaChannel0_m = 0x00000001,
8334 + INT3_dmaChannel1_b = 1,
8335 + INT3_dmaChannel1_m = 0x00000002,
8336 + INT3_dmaChannel2_b = 2,
8337 + INT3_dmaChannel2_m = 0x00000004,
8338 + INT3_dmaChannel3_b = 3,
8339 + INT3_dmaChannel3_m = 0x00000008,
8340 + INT3_dmaChannel4_b = 4,
8341 + INT3_dmaChannel4_m = 0x00000010,
8342 + INT3_dmaChannel5_b = 5,
8343 + INT3_dmaChannel5_m = 0x00000020,
8344 +
8345 + INT5_uartGeneral0_b = 0,
8346 + INT5_uartGeneral0_m = 0x00000001,
8347 + INT5_uartTxrdy0_b = 1,
8348 + INT5_uartTxrdy0_m = 0x00000002,
8349 + INT5_uartRxrdy0_b = 2,
8350 + INT5_uartRxrdy0_m = 0x00000004,
8351 + INT5_pci_b = 3,
8352 + INT5_pci_m = 0x00000008,
8353 + INT5_pciDecoupled_b = 4,
8354 + INT5_pciDecoupled_m = 0x00000010,
8355 + INT5_spi_b = 5,
8356 + INT5_spi_m = 0x00000020,
8357 + INT5_deviceDecoupled_b = 6,
8358 + INT5_deviceDecoupled_m = 0x00000040,
8359 + INT5_eth0Ovr_b = 9,
8360 + INT5_eth0Ovr_m = 0x00000200,
8361 + INT5_eth0Und_b = 10,
8362 + INT5_eth0Und_m = 0x00000400,
8363 + INT5_eth0Pfd_b = 11,
8364 + INT5_eth0Pfd_m = 0x00000800,
8365 + INT5_nvram_b = 12,
8366 + INT5_nvram_m = 0x00001000,
8367 +
8368 + INT6_gpio0_b = 0,
8369 + INT6_gpio0_m = 0x00000001,
8370 + INT6_gpio1_b = 1,
8371 + INT6_gpio1_m = 0x00000002,
8372 + INT6_gpio2_b = 2,
8373 + INT6_gpio2_m = 0x00000004,
8374 + INT6_gpio3_b = 3,
8375 + INT6_gpio3_m = 0x00000008,
8376 + INT6_gpio4_b = 4,
8377 + INT6_gpio4_m = 0x00000010,
8378 + INT6_gpio5_b = 5,
8379 + INT6_gpio5_m = 0x00000020,
8380 + INT6_gpio6_b = 6,
8381 + INT6_gpio6_m = 0x00000040,
8382 + INT6_gpio7_b = 7,
8383 + INT6_gpio7_m = 0x00000080,
8384 + INT6_gpio8_b = 8,
8385 + INT6_gpio8_m = 0x00000100,
8386 + INT6_gpio9_b = 9,
8387 + INT6_gpio9_m = 0x00000200,
8388 + INT6_gpio10_b = 10,
8389 + INT6_gpio10_m = 0x00000400,
8390 + INT6_gpio11_b = 11,
8391 + INT6_gpio11_m = 0x00000800,
8392 + INT6_gpio12_b = 12,
8393 + INT6_gpio12_m = 0x00001000,
8394 + INT6_gpio13_b = 13,
8395 + INT6_gpio13_m = 0x00002000,
8396 +
8397 + NMIPS_gpio_b = 0,
8398 + NMIPS_gpio_m = 0x00000001,
8399 +} ;
8400 +
8401 +#endif // __IDT_INT_H__
8402 +
8403 +
8404 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
8405 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
8406 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-01-10 00:32:33.000000000 +0100
8407 @@ -0,0 +1,111 @@
8408 +/**************************************************************************
8409 + *
8410 + * BRIEF MODULE DESCRIPTION
8411 + * IP Arbiter register definitions
8412 + *
8413 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8414 + *
8415 + * This program is free software; you can redistribute it and/or modify it
8416 + * under the terms of the GNU General Public License as published by the
8417 + * Free Software Foundation; either version 2 of the License, or (at your
8418 + * option) any later version.
8419 + *
8420 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8421 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8422 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8423 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8424 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8425 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8426 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8427 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8428 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8429 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8430 + *
8431 + * You should have received a copy of the GNU General Public License along
8432 + * with this program; if not, write to the Free Software Foundation, Inc.,
8433 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8434 + *
8435 + *
8436 + **************************************************************************
8437 + * May 2004 rkt,neb
8438 + *
8439 + * Initial Release
8440 + *
8441 + *
8442 + *
8443 + **************************************************************************
8444 + */
8445 +
8446 +#ifndef __IDT_IPARB_H__
8447 +#define __IDT_IPARB_H__
8448 +
8449 +enum
8450 +{
8451 + IPARB0_PhysicalAddress = 0x18048000,
8452 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
8453 +
8454 + IPARB0_VirtualAddress = 0xB8048000,
8455 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
8456 +} ;
8457 +
8458 +enum
8459 +{
8460 + IPABMXC_ethernet0Receive = 0,
8461 + IPABMXC_ethernet0Transmit = 1,
8462 + IPABMXC_memoryToHoldFifo = 2,
8463 + IPABMXC_holdFifoToMemory = 3,
8464 + IPABMXC_pciToMemory = 4,
8465 + IPABMXC_memoryToPci = 5,
8466 + IPABMXC_pciTarget = 6,
8467 + IPABMXC_pciTargetStart = 7,
8468 + IPABMXC_cpuToIpBus = 8,
8469 +
8470 + IPABMXC_Count, // Must be last in list !
8471 + IPABMXC_Min = IPABMXC_ethernet0Receive,
8472 +
8473 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
8474 +} ;
8475 +
8476 +typedef struct
8477 +{
8478 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
8479 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
8480 + u32 ipac ; // use IPAC_
8481 + u32 ipaitcc; // use IPAITCC_
8482 + u32 ipaspare ;
8483 +} volatile * IPARB_t ;
8484 +
8485 +enum
8486 +{
8487 + IPAC_dp_b = 0,
8488 + IPAC_dp_m = 0x00000001,
8489 + IPAC_dep_b = 1,
8490 + IPAC_dep_m = 0x00000002,
8491 + IPAC_drm_b = 2,
8492 + IPAC_drm_m = 0x00000004,
8493 + IPAC_dwm_b = 3,
8494 + IPAC_dwm_m = 0x00000008,
8495 + IPAC_msk_b = 4,
8496 + IPAC_msk_m = 0x00000010,
8497 +
8498 + IPAPC_ptc_b = 0,
8499 + IPAPC_ptc_m = 0x00003fff,
8500 + IPAPC_mf_b = 14,
8501 + IPAPC_mf_m = 0x00004000,
8502 + IPAPC_cptc_b = 16,
8503 + IPAPC_cptc_m = 0x3fff0000,
8504 +
8505 + IPAITCC_itcc = 0,
8506 + IPAITCC_itcc, = 0x000001ff,
8507 +
8508 + IPABMC_mtc_b = 0,
8509 + IPABMC_mtc_m = 0x00000fff,
8510 + IPABMC_p_b = 12,
8511 + IPABMC_p_m = 0x00003000,
8512 + IPABMC_msk_b = 14,
8513 + IPABMC_msk_m = 0x00004000,
8514 + IPABMC_cmtc_b = 16,
8515 + IPABMC_cmtc_m = 0x0fff0000,
8516 +};
8517 +
8518 +#endif // __IDT_IPARB_H__
8519 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
8520 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
8521 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-01-10 00:32:33.000000000 +0100
8522 @@ -0,0 +1,695 @@
8523 +/**************************************************************************
8524 + *
8525 + * BRIEF MODULE DESCRIPTION
8526 + * PCI register definitio
8527 + *
8528 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8529 + *
8530 + * This program is free software; you can redistribute it and/or modify it
8531 + * under the terms of the GNU General Public License as published by the
8532 + * Free Software Foundation; either version 2 of the License, or (at your
8533 + * option) any later version.
8534 + *
8535 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8536 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8537 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8538 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8539 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8540 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8541 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8542 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8543 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8544 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8545 + *
8546 + * You should have received a copy of the GNU General Public License along
8547 + * with this program; if not, write to the Free Software Foundation, Inc.,
8548 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8549 + *
8550 + *
8551 + **************************************************************************
8552 + * May 2004 rkt, neb.
8553 + *
8554 + * Initial Release
8555 + *
8556 + *
8557 + *
8558 + **************************************************************************
8559 + */
8560 +
8561 +#ifndef __IDT_PCI_H__
8562 +#define __IDT_PCI_H__
8563 +
8564 +enum
8565 +{
8566 + PCI0_PhysicalAddress = 0x18080000,
8567 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
8568 +
8569 + PCI0_VirtualAddress = 0xB8080000,
8570 + PCI_VirtualAddress = PCI0_VirtualAddress,
8571 +} ;
8572 +
8573 +enum
8574 +{
8575 + PCI_LbaCount = 4, // Local base addresses.
8576 +} ;
8577 +
8578 +typedef struct
8579 +{
8580 + u32 a ; // Address.
8581 + u32 c ; // Control.
8582 + u32 m ; // mapping.
8583 +} PCI_Map_s ;
8584 +
8585 +typedef struct
8586 +{
8587 + u32 pcic ;
8588 + u32 pcis ;
8589 + u32 pcism ;
8590 + u32 pcicfga ;
8591 + u32 pcicfgd ;
8592 + PCI_Map_s pcilba [PCI_LbaCount] ;
8593 + u32 pcidac ;
8594 + u32 pcidas ;
8595 + u32 pcidasm ;
8596 + u32 pcidad ;
8597 + u32 pcidma8c ;
8598 + u32 pcidma9c ;
8599 + u32 pcitc ;
8600 +} volatile *PCI_t ;
8601 +
8602 +// PCI messaging unit.
8603 +enum
8604 +{
8605 + PCIM_Count = 2,
8606 +} ;
8607 +typedef struct
8608 +{
8609 + u32 pciim [PCIM_Count] ;
8610 + u32 pciom [PCIM_Count] ;
8611 + u32 pciid ;
8612 + u32 pciiic ;
8613 + u32 pciiim ;
8614 + u32 pciiod ;
8615 + u32 pciioic ;
8616 + u32 pciioim ;
8617 +} volatile *PCIM_t ;
8618 +
8619 +/*******************************************************************************
8620 + *
8621 + * PCI Control Register
8622 + *
8623 + ******************************************************************************/
8624 +enum
8625 +{
8626 + PCIC_en_b = 0,
8627 + PCIC_en_m = 0x00000001,
8628 + PCIC_tnr_b = 1,
8629 + PCIC_tnr_m = 0x00000002,
8630 + PCIC_sce_b = 2,
8631 + PCIC_sce_m = 0x00000004,
8632 + PCIC_ien_b = 3,
8633 + PCIC_ien_m = 0x00000008,
8634 + PCIC_aaa_b = 4,
8635 + PCIC_aaa_m = 0x00000010,
8636 + PCIC_eap_b = 5,
8637 + PCIC_eap_m = 0x00000020,
8638 + PCIC_pcim_b = 6,
8639 + PCIC_pcim_m = 0x000001c0,
8640 + PCIC_pcim_disabled_v = 0,
8641 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
8642 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
8643 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
8644 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
8645 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
8646 + PCIC_pcim_reserved6_v = 6,
8647 + PCIC_pcim_reserved7_v = 7,
8648 + PCIC_igm_b = 9,
8649 + PCIC_igm_m = 0x00000200,
8650 +} ;
8651 +
8652 +/*******************************************************************************
8653 + *
8654 + * PCI Status Register
8655 + *
8656 + ******************************************************************************/
8657 +enum {
8658 + PCIS_eed_b = 0,
8659 + PCIS_eed_m = 0x00000001,
8660 + PCIS_wr_b = 1,
8661 + PCIS_wr_m = 0x00000002,
8662 + PCIS_nmi_b = 2,
8663 + PCIS_nmi_m = 0x00000004,
8664 + PCIS_ii_b = 3,
8665 + PCIS_ii_m = 0x00000008,
8666 + PCIS_cwe_b = 4,
8667 + PCIS_cwe_m = 0x00000010,
8668 + PCIS_cre_b = 5,
8669 + PCIS_cre_m = 0x00000020,
8670 + PCIS_mdpe_b = 6,
8671 + PCIS_mdpe_m = 0x00000040,
8672 + PCIS_sta_b = 7,
8673 + PCIS_sta_m = 0x00000080,
8674 + PCIS_rta_b = 8,
8675 + PCIS_rta_m = 0x00000100,
8676 + PCIS_rma_b = 9,
8677 + PCIS_rma_m = 0x00000200,
8678 + PCIS_sse_b = 10,
8679 + PCIS_sse_m = 0x00000400,
8680 + PCIS_ose_b = 11,
8681 + PCIS_ose_m = 0x00000800,
8682 + PCIS_pe_b = 12,
8683 + PCIS_pe_m = 0x00001000,
8684 + PCIS_tae_b = 13,
8685 + PCIS_tae_m = 0x00002000,
8686 + PCIS_rle_b = 14,
8687 + PCIS_rle_m = 0x00004000,
8688 + PCIS_bme_b = 15,
8689 + PCIS_bme_m = 0x00008000,
8690 + PCIS_prd_b = 16,
8691 + PCIS_prd_m = 0x00010000,
8692 + PCIS_rip_b = 17,
8693 + PCIS_rip_m = 0x00020000,
8694 +} ;
8695 +
8696 +/*******************************************************************************
8697 + *
8698 + * PCI Status Mask Register
8699 + *
8700 + ******************************************************************************/
8701 +enum {
8702 + PCISM_eed_b = 0,
8703 + PCISM_eed_m = 0x00000001,
8704 + PCISM_wr_b = 1,
8705 + PCISM_wr_m = 0x00000002,
8706 + PCISM_nmi_b = 2,
8707 + PCISM_nmi_m = 0x00000004,
8708 + PCISM_ii_b = 3,
8709 + PCISM_ii_m = 0x00000008,
8710 + PCISM_cwe_b = 4,
8711 + PCISM_cwe_m = 0x00000010,
8712 + PCISM_cre_b = 5,
8713 + PCISM_cre_m = 0x00000020,
8714 + PCISM_mdpe_b = 6,
8715 + PCISM_mdpe_m = 0x00000040,
8716 + PCISM_sta_b = 7,
8717 + PCISM_sta_m = 0x00000080,
8718 + PCISM_rta_b = 8,
8719 + PCISM_rta_m = 0x00000100,
8720 + PCISM_rma_b = 9,
8721 + PCISM_rma_m = 0x00000200,
8722 + PCISM_sse_b = 10,
8723 + PCISM_sse_m = 0x00000400,
8724 + PCISM_ose_b = 11,
8725 + PCISM_ose_m = 0x00000800,
8726 + PCISM_pe_b = 12,
8727 + PCISM_pe_m = 0x00001000,
8728 + PCISM_tae_b = 13,
8729 + PCISM_tae_m = 0x00002000,
8730 + PCISM_rle_b = 14,
8731 + PCISM_rle_m = 0x00004000,
8732 + PCISM_bme_b = 15,
8733 + PCISM_bme_m = 0x00008000,
8734 + PCISM_prd_b = 16,
8735 + PCISM_prd_m = 0x00010000,
8736 + PCISM_rip_b = 17,
8737 + PCISM_rip_m = 0x00020000,
8738 +} ;
8739 +
8740 +/*******************************************************************************
8741 + *
8742 + * PCI Configuration Address Register
8743 + *
8744 + ******************************************************************************/
8745 +enum {
8746 + PCICFGA_reg_b = 2,
8747 + PCICFGA_reg_m = 0x000000fc,
8748 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
8749 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
8750 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
8751 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
8752 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
8753 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
8754 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
8755 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
8756 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
8757 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
8758 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
8759 + PCICFGA_reg_pba0m_v = 0x48>>2,
8760 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
8761 + PCICFGA_reg_pba1m_v = 0x50>>2,
8762 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
8763 + PCICFGA_reg_pba2m_v = 0x58>>2,
8764 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
8765 + PCICFGA_reg_pba3m_v = 0x60>>2,
8766 + PCICFGA_reg_pmgt_v = 0x64>>2,
8767 + PCICFGA_func_b = 8,
8768 + PCICFGA_func_m = 0x00000700,
8769 + PCICFGA_dev_b = 11,
8770 + PCICFGA_dev_m = 0x0000f800,
8771 + PCICFGA_dev_internal_v = 0,
8772 + PCICFGA_bus_b = 16,
8773 + PCICFGA_bus_m = 0x00ff0000,
8774 + PCICFGA_bus_type0_v = 0, //local bus
8775 + PCICFGA_en_b = 31, // read only
8776 + PCICFGA_en_m = 0x80000000,
8777 +} ;
8778 +
8779 +enum {
8780 + PCFGID_vendor_b = 0,
8781 + PCFGID_vendor_m = 0x0000ffff,
8782 + PCFGID_vendor_IDT_v = 0x111d,
8783 + PCFGID_device_b = 16,
8784 + PCFGID_device_m = 0xffff0000,
8785 + PCFGID_device_Korinade_v = 0x0214,
8786 +
8787 + PCFG04_command_ioena_b = 1,
8788 + PCFG04_command_ioena_m = 0x00000001,
8789 + PCFG04_command_memena_b = 2,
8790 + PCFG04_command_memena_m = 0x00000002,
8791 + PCFG04_command_bmena_b = 3,
8792 + PCFG04_command_bmena_m = 0x00000004,
8793 + PCFG04_command_mwinv_b = 5,
8794 + PCFG04_command_mwinv_m = 0x00000010,
8795 + PCFG04_command_parena_b = 7,
8796 + PCFG04_command_parena_m = 0x00000040,
8797 + PCFG04_command_serrena_b = 9,
8798 + PCFG04_command_serrena_m = 0x00000100,
8799 + PCFG04_command_fastbbena_b = 10,
8800 + PCFG04_command_fastbbena_m = 0x00000200,
8801 + PCFG04_status_b = 16,
8802 + PCFG04_status_m = 0xffff0000,
8803 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
8804 + PCFG04_status_66MHz_m = 0x00200000,
8805 + PCFG04_status_fbb_b = 23,
8806 + PCFG04_status_fbb_m = 0x00800000,
8807 + PCFG04_status_mdpe_b = 24,
8808 + PCFG04_status_mdpe_m = 0x01000000,
8809 + PCFG04_status_dst_b = 25,
8810 + PCFG04_status_dst_m = 0x06000000,
8811 + PCFG04_status_sta_b = 27,
8812 + PCFG04_status_sta_m = 0x08000000,
8813 + PCFG04_status_rta_b = 28,
8814 + PCFG04_status_rta_m = 0x10000000,
8815 + PCFG04_status_rma_b = 29,
8816 + PCFG04_status_rma_m = 0x20000000,
8817 + PCFG04_status_sse_b = 30,
8818 + PCFG04_status_sse_m = 0x40000000,
8819 + PCFG04_status_pe_b = 31,
8820 + PCFG04_status_pe_m = 0x40000000,
8821 +
8822 + PCFG08_revId_b = 0,
8823 + PCFG08_revId_m = 0x000000ff,
8824 + PCFG08_classCode_b = 0,
8825 + PCFG08_classCode_m = 0xffffff00,
8826 + PCFG08_classCode_bridge_v = 06,
8827 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
8828 + PCFG0C_cacheline_b = 0,
8829 + PCFG0C_cacheline_m = 0x000000ff,
8830 + PCFG0C_masterLatency_b = 8,
8831 + PCFG0C_masterLatency_m = 0x0000ff00,
8832 + PCFG0C_headerType_b = 16,
8833 + PCFG0C_headerType_m = 0x00ff0000,
8834 + PCFG0C_bist_b = 24,
8835 + PCFG0C_bist_m = 0xff000000,
8836 +
8837 + PCIPBA_msi_b = 0,
8838 + PCIPBA_msi_m = 0x00000001,
8839 + PCIPBA_p_b = 3,
8840 + PCIPBA_p_m = 0x00000004,
8841 + PCIPBA_baddr_b = 8,
8842 + PCIPBA_baddr_m = 0xffffff00,
8843 +
8844 + PCFGSS_vendorId_b = 0,
8845 + PCFGSS_vendorId_m = 0x0000ffff,
8846 + PCFGSS_id_b = 16,
8847 + PCFGSS_id_m = 0xffff0000,
8848 +
8849 + PCFG3C_interruptLine_b = 0,
8850 + PCFG3C_interruptLine_m = 0x000000ff,
8851 + PCFG3C_interruptPin_b = 8,
8852 + PCFG3C_interruptPin_m = 0x0000ff00,
8853 + PCFG3C_minGrant_b = 16,
8854 + PCFG3C_minGrant_m = 0x00ff0000,
8855 + PCFG3C_maxLat_b = 24,
8856 + PCFG3C_maxLat_m = 0xff000000,
8857 +
8858 + PCIPBAC_msi_b = 0,
8859 + PCIPBAC_msi_m = 0x00000001,
8860 + PCIPBAC_p_b = 1,
8861 + PCIPBAC_p_m = 0x00000002,
8862 + PCIPBAC_size_b = 2,
8863 + PCIPBAC_size_m = 0x0000007c,
8864 + PCIPBAC_sb_b = 7,
8865 + PCIPBAC_sb_m = 0x00000080,
8866 + PCIPBAC_pp_b = 8,
8867 + PCIPBAC_pp_m = 0x00000100,
8868 + PCIPBAC_mr_b = 9,
8869 + PCIPBAC_mr_m = 0x00000600,
8870 + PCIPBAC_mr_read_v =0, //no prefetching
8871 + PCIPBAC_mr_readLine_v =1,
8872 + PCIPBAC_mr_readMult_v =2,
8873 + PCIPBAC_mrl_b = 11,
8874 + PCIPBAC_mrl_m = 0x00000800,
8875 + PCIPBAC_mrm_b = 12,
8876 + PCIPBAC_mrm_m = 0x00001000,
8877 + PCIPBAC_trp_b = 13,
8878 + PCIPBAC_trp_m = 0x00002000,
8879 +
8880 + PCFG40_trdyTimeout_b = 0,
8881 + PCFG40_trdyTimeout_m = 0x000000ff,
8882 + PCFG40_retryLim_b = 8,
8883 + PCFG40_retryLim_m = 0x0000ff00,
8884 +};
8885 +
8886 +/*******************************************************************************
8887 + *
8888 + * PCI Local Base Address [0|1|2|3] Register
8889 + *
8890 + ******************************************************************************/
8891 +enum {
8892 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
8893 + PCILBA_baddr_m = 0xffffff00,
8894 +} ;
8895 +/*******************************************************************************
8896 + *
8897 + * PCI Local Base Address Control Register
8898 + *
8899 + ******************************************************************************/
8900 +enum {
8901 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
8902 + PCILBAC_msi_m = 0x00000001,
8903 + PCILBAC_msi_mem_v = 0,
8904 + PCILBAC_msi_io_v = 1,
8905 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
8906 + PCILBAC_size_m = 0x0000007c,
8907 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
8908 + PCILBAC_sb_m = 0x00000080,
8909 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
8910 + PCILBAC_rt_m = 0x00000100,
8911 + PCILBAC_rt_noprefetch_v = 0, // mem read
8912 + PCILBAC_rt_prefetch_v = 1, // mem readline
8913 +} ;
8914 +
8915 +/*******************************************************************************
8916 + *
8917 + * PCI Local Base Address [0|1|2|3] Mapping Register
8918 + *
8919 + ******************************************************************************/
8920 +enum {
8921 + PCILBAM_maddr_b = 8,
8922 + PCILBAM_maddr_m = 0xffffff00,
8923 +} ;
8924 +
8925 +/*******************************************************************************
8926 + *
8927 + * PCI Decoupled Access Control Register
8928 + *
8929 + ******************************************************************************/
8930 +enum {
8931 + PCIDAC_den_b = 0,
8932 + PCIDAC_den_m = 0x00000001,
8933 +} ;
8934 +
8935 +/*******************************************************************************
8936 + *
8937 + * PCI Decoupled Access Status Register
8938 + *
8939 + ******************************************************************************/
8940 +enum {
8941 + PCIDAS_d_b = 0,
8942 + PCIDAS_d_m = 0x00000001,
8943 + PCIDAS_b_b = 1,
8944 + PCIDAS_b_m = 0x00000002,
8945 + PCIDAS_e_b = 2,
8946 + PCIDAS_e_m = 0x00000004,
8947 + PCIDAS_ofe_b = 3,
8948 + PCIDAS_ofe_m = 0x00000008,
8949 + PCIDAS_off_b = 4,
8950 + PCIDAS_off_m = 0x00000010,
8951 + PCIDAS_ife_b = 5,
8952 + PCIDAS_ife_m = 0x00000020,
8953 + PCIDAS_iff_b = 6,
8954 + PCIDAS_iff_m = 0x00000040,
8955 +} ;
8956 +
8957 +/*******************************************************************************
8958 + *
8959 + * PCI DMA Channel 8 Configuration Register
8960 + *
8961 + ******************************************************************************/
8962 +enum
8963 +{
8964 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
8965 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
8966 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
8967 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
8968 +} ;
8969 +
8970 +/*******************************************************************************
8971 + *
8972 + * PCI DMA Channel 9 Configuration Register
8973 + *
8974 + ******************************************************************************/
8975 +enum
8976 +{
8977 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
8978 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
8979 +} ;
8980 +
8981 +/*******************************************************************************
8982 + *
8983 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
8984 + *
8985 + ******************************************************************************/
8986 +enum {
8987 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
8988 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
8989 + // These are for reads (DMA channel 8)
8990 + PCIDMAD_devcmd_mr_v = 0, //memory read
8991 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
8992 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
8993 + PCIDMAD_devcmd_ior_v = 3, //I/O read
8994 + // These are for writes (DMA channel 9)
8995 + PCIDMAD_devcmd_mw_v = 0, //memory write
8996 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
8997 + PCIDMAD_devcmd_iow_v = 3, //I/O write
8998 +
8999 + // Swap byte field applies to both DMA channel 8 and 9
9000 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
9001 + PCIDMAD_sb_m = 0x01000000, // swap byte field
9002 +} ;
9003 +
9004 +
9005 +/*******************************************************************************
9006 + *
9007 + * PCI Target Control Register
9008 + *
9009 + ******************************************************************************/
9010 +enum
9011 +{
9012 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
9013 + PCITC_rtimer_m = 0x000000ff,
9014 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
9015 + PCITC_dtimer_m = 0x0000ff00,
9016 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
9017 + PCITC_rdr_m = 0x00040000,
9018 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
9019 + PCITC_ddt_m = 0x00080000,
9020 +} ;
9021 +/*******************************************************************************
9022 + *
9023 + * PCI messaging unit [applies to both inbound and outbound registers ]
9024 + *
9025 + ******************************************************************************/
9026 +enum
9027 +{
9028 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
9029 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
9030 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
9031 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
9032 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
9033 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
9034 +};
9035 +
9036 +
9037 +
9038 +
9039 +
9040 +
9041 +#define PCI_MSG_VirtualAddress 0xB8088010
9042 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
9043 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
9044 +
9045 +#define PCIM_SHFT 0x6
9046 +#define PCIM_BIT_LEN 0x7
9047 +#define PCIM_H_EA 0x3
9048 +#define PCIM_H_IA_FIX 0x4
9049 +#define PCIM_H_IA_RR 0x5
9050 +#if 0
9051 +#define PCI_ADDR_START 0x13000000
9052 +#endif
9053 +
9054 +#define PCI_ADDR_START 0x50000000
9055 +
9056 +#define CPUTOPCI_MEM_WIN 0x02000000
9057 +#define CPUTOPCI_IO_WIN 0x00100000
9058 +#define PCILBA_SIZE_SHFT 2
9059 +#define PCILBA_SIZE_MASK 0x1F
9060 +#define SIZE_256MB 0x1C
9061 +#define SIZE_128MB 0x1B
9062 +#define SIZE_64MB 0x1A
9063 +#define SIZE_32MB 0x19
9064 +#define SIZE_16MB 0x18
9065 +#define SIZE_4MB 0x16
9066 +#define SIZE_2MB 0x15
9067 +#define SIZE_1MB 0x14
9068 +#define KORINA_CONFIG0_ADDR 0x80000000
9069 +#define KORINA_CONFIG1_ADDR 0x80000004
9070 +#define KORINA_CONFIG2_ADDR 0x80000008
9071 +#define KORINA_CONFIG3_ADDR 0x8000000C
9072 +#define KORINA_CONFIG4_ADDR 0x80000010
9073 +#define KORINA_CONFIG5_ADDR 0x80000014
9074 +#define KORINA_CONFIG6_ADDR 0x80000018
9075 +#define KORINA_CONFIG7_ADDR 0x8000001C
9076 +#define KORINA_CONFIG8_ADDR 0x80000020
9077 +#define KORINA_CONFIG9_ADDR 0x80000024
9078 +#define KORINA_CONFIG10_ADDR 0x80000028
9079 +#define KORINA_CONFIG11_ADDR 0x8000002C
9080 +#define KORINA_CONFIG12_ADDR 0x80000030
9081 +#define KORINA_CONFIG13_ADDR 0x80000034
9082 +#define KORINA_CONFIG14_ADDR 0x80000038
9083 +#define KORINA_CONFIG15_ADDR 0x8000003C
9084 +#define KORINA_CONFIG16_ADDR 0x80000040
9085 +#define KORINA_CONFIG17_ADDR 0x80000044
9086 +#define KORINA_CONFIG18_ADDR 0x80000048
9087 +#define KORINA_CONFIG19_ADDR 0x8000004C
9088 +#define KORINA_CONFIG20_ADDR 0x80000050
9089 +#define KORINA_CONFIG21_ADDR 0x80000054
9090 +#define KORINA_CONFIG22_ADDR 0x80000058
9091 +#define KORINA_CONFIG23_ADDR 0x8000005C
9092 +#define KORINA_CONFIG24_ADDR 0x80000060
9093 +#define KORINA_CONFIG25_ADDR 0x80000064
9094 +#define KORINA_CMD (PCFG04_command_ioena_m | \
9095 + PCFG04_command_memena_m | \
9096 + PCFG04_command_bmena_m | \
9097 + PCFG04_command_mwinv_m | \
9098 + PCFG04_command_parena_m | \
9099 + PCFG04_command_serrena_m )
9100 +
9101 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
9102 + PCFG04_status_sta_m | \
9103 + PCFG04_status_rta_m | \
9104 + PCFG04_status_rma_m | \
9105 + PCFG04_status_sse_m | \
9106 + PCFG04_status_pe_m)
9107 +
9108 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
9109 +
9110 +#define KORINA_REVID 0
9111 +#define KORINA_CLASS_CODE 0
9112 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
9113 + KORINA_REVID)
9114 +
9115 +#define KORINA_CACHE_LINE_SIZE 4
9116 +#define KORINA_MASTER_LAT 0x3c
9117 +#define KORINA_HEADER_TYPE 0
9118 +#define KORINA_BIST 0
9119 +
9120 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
9121 + (KORINA_HEADER_TYPE<<16) | \
9122 + (KORINA_MASTER_LAT<<8) | \
9123 + KORINA_CACHE_LINE_SIZE )
9124 +
9125 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
9126 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
9127 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
9128 + internal Registers */
9129 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
9130 +
9131 +#define KORINA_CNFG4 KORINA_BAR0
9132 +#define KORINA_CNFG5 KORINA_BAR1
9133 +#define KORINA_CNFG6 KORINA_BAR2
9134 +#define KORINA_CNFG7 KORINA_BAR3
9135 +
9136 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
9137 +#define KORINA_SUBSYSTEM_ID 0x0214
9138 +#define KORINA_CNFG8 0
9139 +#define KORINA_CNFG9 0
9140 +#define KORINA_CNFG10 0
9141 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
9142 + KORINA_SUBSYSTEM_ID)
9143 +#define KORINA_INT_LINE 1
9144 +#define KORINA_INT_PIN 1
9145 +#define KORINA_MIN_GNT 8
9146 +#define KORINA_MAX_LAT 0x38
9147 +#define KORINA_CNFG12 0
9148 +#define KORINA_CNFG13 0
9149 +#define KORINA_CNFG14 0
9150 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
9151 + (KORINA_MIN_GNT<<16) | \
9152 + (KORINA_INT_PIN<<8) | \
9153 + KORINA_INT_LINE)
9154 +#define KORINA_RETRY_LIMIT 0x80
9155 +#define KORINA_TRDY_LIMIT 0x80
9156 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
9157 + KORINA_TRDY_LIMIT)
9158 +#define PCI_PBAxC_R 0x0
9159 +#define PCI_PBAxC_RL 0x1
9160 +#define PCI_PBAxC_RM 0x2
9161 +#define SIZE_SHFT 2
9162 +
9163 +#if defined(__MIPSEB__)
9164 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
9165 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
9166 + PCIPBAC_pp_m | \
9167 + (SIZE_128MB<<SIZE_SHFT) | \
9168 + PCIPBAC_p_m)
9169 +#else
9170 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
9171 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
9172 + PCIPBAC_pp_m | \
9173 + (SIZE_128MB<<SIZE_SHFT) | \
9174 + PCIPBAC_p_m)
9175 +#endif
9176 +#define KORINA_CNFG17 KORINA_PBA0C
9177 +#define KORINA_PBA0M 0x0
9178 +#define KORINA_CNFG18 KORINA_PBA0M
9179 +
9180 +#if defined(__MIPSEB__)
9181 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
9182 + PCIPBAC_msi_m)
9183 +#else
9184 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
9185 + PCIPBAC_msi_m)
9186 +#endif
9187 +#define KORINA_CNFG19 KORINA_PBA1C
9188 +#define KORINA_PBA1M 0x0
9189 +#define KORINA_CNFG20 KORINA_PBA1M
9190 +
9191 +#if defined(__MIPSEB__)
9192 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
9193 + PCIPBAC_msi_m)
9194 +#else
9195 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
9196 + PCIPBAC_msi_m)
9197 +#endif
9198 +#define KORINA_CNFG21 KORINA_PBA2C
9199 +#define KORINA_PBA2M 0x18000000
9200 +#define KORINA_CNFG22 KORINA_PBA2M
9201 +#define KORINA_PBA3C 0
9202 +#define KORINA_CNFG23 KORINA_PBA3C
9203 +#define KORINA_PBA3M 0
9204 +#define KORINA_CNFG24 KORINA_PBA3M
9205 +
9206 +
9207 +
9208 +#define PCITC_DTIMER_VAL 8
9209 +#define PCITC_RTIMER_VAL 0x10
9210 +
9211 +
9212 +
9213 +
9214 +#endif // __IDT_PCI_H__
9215 +
9216 +
9217 +
9218 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
9219 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
9220 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-01-10 00:32:33.000000000 +0100
9221 @@ -0,0 +1,119 @@
9222 +/**************************************************************************
9223 + *
9224 + * BRIEF MODULE DESCRIPTION
9225 + * Reset register definitions.
9226 + *
9227 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9228 + *
9229 + * This program is free software; you can redistribute it and/or modify it
9230 + * under the terms of the GNU General Public License as published by the
9231 + * Free Software Foundation; either version 2 of the License, or (at your
9232 + * option) any later version.
9233 + *
9234 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9235 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9236 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9237 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9238 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9239 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9240 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9241 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9242 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9243 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9244 + *
9245 + * You should have received a copy of the GNU General Public License along
9246 + * with this program; if not, write to the Free Software Foundation, Inc.,
9247 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9248 + *
9249 + *
9250 + **************************************************************************
9251 + * May 2004 rkt, neb.
9252 + *
9253 + * Initial Release
9254 + *
9255 + *
9256 + *
9257 + **************************************************************************
9258 + */
9259 +
9260 +#ifndef __IDT_RST_H__
9261 +#define __IDT_RST_H__
9262 +
9263 +enum
9264 +{
9265 + RST0_PhysicalAddress = 0x18000000,
9266 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
9267 +
9268 + RST0_VirtualAddress = 0xb8000000,
9269 + RST_VirtualAddress = RST0_VirtualAddress, // Default
9270 +} ;
9271 +
9272 +typedef struct RST_s
9273 +{
9274 + u32 filler [0x0006] ;
9275 + u32 sysid ;
9276 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
9277 + u32 reset ;
9278 + u32 bcv ;
9279 + u32 cea ;
9280 +} volatile * RST_t ;
9281 +
9282 +enum
9283 +{
9284 + SYSID_rev_b = 0,
9285 + SYSID_rev_m = 0x000000ff,
9286 + SYSID_imp_b = 8,
9287 + SYSID_imp_m = 0x000fff00,
9288 + SYSID_vendor_b = 8,
9289 + SYSID_vendor_m = 0xfff00000,
9290 +
9291 + BCV_pll_b = 0,
9292 + BCV_pll_m = 0x0000000f,
9293 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
9294 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
9295 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
9296 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
9297 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
9298 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
9299 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
9300 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
9301 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
9302 + BCV_pll_Res9_v = 0x9,
9303 + BCV_pll_Res10_v = 0xa,
9304 + BCV_pll_Res11_v = 0xb,
9305 + BCV_pll_Res12_v = 0xc,
9306 + BCV_pll_Res13_v = 0xd,
9307 + BCV_pll_Res14_v = 0xe,
9308 + BCV_pll_Res15_v = 0xf,
9309 + BCV_clkDiv_b = 4,
9310 + BCV_clkDiv_m = 0x00000030,
9311 + BCV_clkDiv_Div1_v = 0x0,
9312 + BCV_clkDiv_Div2_v = 0x1,
9313 + BCV_clkDiv_Div4_v = 0x2,
9314 + BCV_clkDiv_Res3_v = 0x3,
9315 + BCV_bigEndian_b = 6,
9316 + BCV_bigEndian_m = 0x00000040,
9317 + BCV_resetFast_b = 7,
9318 + BCV_resetFast_m = 0x00000080,
9319 + BCV_pciMode_b = 8,
9320 + BCV_pciMode_m = 0x00000700,
9321 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
9322 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
9323 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
9324 + BCV_pciMode_external_v = 3, // host, external arbiter.
9325 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
9326 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
9327 + BCV_pciMode_res6_v = 6,
9328 + BCV_pciMode_res7_v = 7,
9329 + BCV_watchDisable_b = 11,
9330 + BCV_watchDisable_m = 0x00000800,
9331 + BCV_res12_b = 12,
9332 + BCV_res12_m = 0x00001000,
9333 + BCV_res13_b = 13,
9334 + BCV_res13_m = 0x00002000,
9335 + BCV_res14_b = 14,
9336 + BCV_res14_m = 0x00004000,
9337 + BCV_res15_b = 15,
9338 + BCV_res15_m = 0x00008000,
9339 +} ;
9340 +#endif // __IDT_RST_H__
9341 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
9342 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
9343 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-01-10 00:32:33.000000000 +0100
9344 @@ -0,0 +1,120 @@
9345 +/**************************************************************************
9346 + *
9347 + * BRIEF MODULE DESCRIPTION
9348 + * Serial Peripheral Interface register definitions.
9349 + *
9350 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9351 + *
9352 + * This program is free software; you can redistribute it and/or modify it
9353 + * under the terms of the GNU General Public License as published by the
9354 + * Free Software Foundation; either version 2 of the License, or (at your
9355 + * option) any later version.
9356 + *
9357 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9358 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9359 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9360 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9361 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9362 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9363 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9364 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9365 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9366 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9367 + *
9368 + * You should have received a copy of the GNU General Public License along
9369 + * with this program; if not, write to the Free Software Foundation, Inc.,
9370 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9371 + *
9372 + *
9373 + **************************************************************************
9374 + * May 2004 rkt, neb.
9375 + *
9376 + * Initial Release
9377 + *
9378 + *
9379 + *
9380 + **************************************************************************
9381 + */
9382 +
9383 +#ifndef __IDT_SPI_H__
9384 +#define __IDT_SPI_H__
9385 +
9386 +enum
9387 +{
9388 + SPI0_PhysicalAddress = 0x18070000,
9389 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
9390 +
9391 + SPI0_VirtualAddress = 0xB8070000,
9392 + SPI_VirtualAddress = SPI0_VirtualAddress,
9393 +} ;
9394 +
9395 +typedef struct
9396 +{
9397 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
9398 + u32 spc ; // spi control reg use SPC_
9399 + u32 sps ; // spi status reg use SPS_
9400 + u32 spd ; // spi data reg use SPD_
9401 + u32 siofunc ; // serial IO function use SIOFUNC_
9402 + u32 siocfg ; // serial IO config use SIOCFG_
9403 + u32 siod; // serial IO data use SIOD_
9404 +} volatile *SPI_t ;
9405 +
9406 +enum
9407 +{
9408 + SPCP_div_b = 0,
9409 + SPCP_div_m = 0x000000ff,
9410 + SPC_spr_b = 0,
9411 + SPC_spr_m = 0x00000003,
9412 + SPC_spr_div2_v = 0,
9413 + SPC_spr_div4_v = 1,
9414 + SPC_spr_div16_v = 2,
9415 + SPC_spr_div32_v = 3,
9416 + SPC_cpha_b = 2,
9417 + SPC_cpha_m = 0x00000004,
9418 + SPC_cpol_b = 3,
9419 + SPC_cpol_m = 0x00000008,
9420 + SPC_mstr_b = 4,
9421 + SPC_mstr_m = 0x00000010,
9422 + SPC_spe_b = 6,
9423 + SPC_spe_m = 0x00000040,
9424 + SPC_spie_b = 7,
9425 + SPC_spie_m = 0x00000080,
9426 +
9427 + SPS_modf_b = 4,
9428 + SPS_modf_m = 0x00000010,
9429 + SPS_wcol_b = 6,
9430 + SPS_wcol_m = 0x00000040,
9431 + SPS_spif_b = 7,
9432 + SPS_spif_m = 0x00000070,
9433 +
9434 + SPD_data_b = 0,
9435 + SPD_data_m = 0x000000ff,
9436 +
9437 + SIOFUNC_sdo_b = 0,
9438 + SIOFUNC_sdo_m = 0x00000001,
9439 + SIOFUNC_sdi_b = 1,
9440 + SIOFUNC_sdi_m = 0x00000002,
9441 + SIOFUNC_sck_b = 2,
9442 + SIOFUNC_sck_m = 0x00000004,
9443 + SIOFUNC_pci_b = 3,
9444 + SIOFUNC_pci_m = 0x00000008,
9445 +
9446 + SIOCFG_sdo_b = 0,
9447 + SIOCFG_sdo_m = 0x00000001,
9448 + SIOCFG_sdi_b = 1,
9449 + SIOCFG_sdi_m = 0x00000002,
9450 + SIOCFG_sck_b = 2,
9451 + SIOCFG_sck_m = 0x00000004,
9452 + SIOCFG_pci_b = 3,
9453 + SIOCFG_pci_m = 0x00000008,
9454 +
9455 + SIOD_sdo_b = 0,
9456 + SIOD_sdo_m = 0x00000001,
9457 + SIOD_sdi_b = 1,
9458 + SIOD_sdi_m = 0x00000002,
9459 + SIOD_sck_b = 2,
9460 + SIOD_sck_m = 0x00000004,
9461 + SIOD_pci_b = 3,
9462 + SIOD_pci_m = 0x00000008,
9463 +} ;
9464 +#endif // __IDT_SPI_H__
9465 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
9466 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
9467 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-01-10 00:32:33.000000000 +0100
9468 @@ -0,0 +1,91 @@
9469 +/**************************************************************************
9470 + *
9471 + * BRIEF MODULE DESCRIPTION
9472 + * Definitions for timer registers
9473 + *
9474 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9475 + *
9476 + * This program is free software; you can redistribute it and/or modify it
9477 + * under the terms of the GNU General Public License as published by the
9478 + * Free Software Foundation; either version 2 of the License, or (at your
9479 + * option) any later version.
9480 + *
9481 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9482 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9483 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9484 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9485 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9486 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9487 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9488 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9489 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9490 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9491 + *
9492 + * You should have received a copy of the GNU General Public License along
9493 + * with this program; if not, write to the Free Software Foundation, Inc.,
9494 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9495 + *
9496 + *
9497 + **************************************************************************
9498 + * May 2004 rkt,neb.
9499 + *
9500 + * Initial Release
9501 + *
9502 + *
9503 + *
9504 + **************************************************************************
9505 + */
9506 +
9507 +#ifndef __IDT_TIM_H__
9508 +#define __IDT_TIM_H__
9509 +
9510 +enum
9511 +{
9512 + TIM0_PhysicalAddress = 0x18028000,
9513 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
9514 +
9515 + TIM0_VirtualAddress = 0xb8028000,
9516 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
9517 +} ;
9518 +
9519 +enum
9520 +{
9521 + TIM_Count = 3,
9522 +} ;
9523 +
9524 +struct TIM_CNTR_s
9525 +{
9526 + u32 count ;
9527 + u32 compare ;
9528 + u32 ctc ; //use CTC_
9529 +} ;
9530 +
9531 +typedef struct TIM_s
9532 +{
9533 + struct TIM_CNTR_s tim [TIM_Count] ;
9534 + u32 rcount ; //use RCOUNT_
9535 + u32 rcompare ; //use RCOMPARE_
9536 + u32 rtc ; //use RTC_
9537 +} volatile * TIM_t ;
9538 +
9539 +enum
9540 +{
9541 + CTC_en_b = 0,
9542 + CTC_en_m = 0x00000001,
9543 + CTC_to_b = 1,
9544 + CTC_to_m = 0x00000002,
9545 +
9546 + RCOUNT_count_b = 0,
9547 + RCOUNT_count_m = 0x0000ffff,
9548 + RCOMPARE_compare_b = 0,
9549 + RCOMPARE_compare_m = 0x0000ffff,
9550 + RTC_ce_b = 0,
9551 + RTC_ce_m = 0x00000001,
9552 + RTC_to_b = 1,
9553 + RTC_to_m = 0x00000002,
9554 + RTC_rqe_b = 2,
9555 + RTC_rqe_m = 0x00000004,
9556 +
9557 +} ;
9558 +#endif // __IDT_TIM_H__
9559 +
9560 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
9561 --- linux-2.6.15/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
9562 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-01-10 00:32:33.000000000 +0100
9563 @@ -0,0 +1,189 @@
9564 +/**************************************************************************
9565 + *
9566 + * BRIEF MODULE DESCRIPTION
9567 + * UART register definitions
9568 + *
9569 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9570 + *
9571 + * This program is free software; you can redistribute it and/or modify it
9572 + * under the terms of the GNU General Public License as published by the
9573 + * Free Software Foundation; either version 2 of the License, or (at your
9574 + * option) any later version.
9575 + *
9576 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9577 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9578 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9579 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9580 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9581 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9582 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9583 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9584 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9585 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9586 + *
9587 + * You should have received a copy of the GNU General Public License along
9588 + * with this program; if not, write to the Free Software Foundation, Inc.,
9589 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9590 + *
9591 + *
9592 + **************************************************************************
9593 + * May 2004 rkt, neb.
9594 + *
9595 + * Initial Release
9596 + *
9597 + *
9598 + *
9599 + **************************************************************************
9600 + */
9601 +
9602 +#ifndef __IDT_UART_H__
9603 +#define __IDT_UART_H__
9604 +
9605 +enum
9606 +{
9607 + UART0_PhysicalAddress = 0x1c000000,
9608 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
9609 +
9610 + UART0_VirtualAddress = 0xbc000000,
9611 + UART_VirtualAddress = UART0_VirtualAddress, // Default
9612 +} ;
9613 +
9614 +/*
9615 + * Register definitions are in bytes so we can handle endian problems.
9616 + */
9617 +
9618 +typedef struct UART_s
9619 +{
9620 + union
9621 + {
9622 + u32 const uartrb ; // 0x00 - DLAB=0, read.
9623 + u32 uartth ; // 0x00 - DLAB=0, write.
9624 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
9625 + } ;
9626 +
9627 + union
9628 + {
9629 + u32 uartie ; // 0x04 - DLAB=0, read/write.
9630 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
9631 + } ;
9632 + union
9633 + {
9634 + u32 const uartii ; // 0x08 - DLAB=0, read.
9635 + u32 uartfc ; // 0x08 - DLAB=0, write.
9636 + } ;
9637 +
9638 + u32 uartlc ; // 0x0c
9639 + u32 uartmc ; // 0x10
9640 + u32 uartls ; // 0x14
9641 + u32 uartms ; // 0x18
9642 + u32 uarts ; // 0x1c
9643 +} volatile *UART_t ;
9644 +
9645 +// Reset registers.
9646 +typedef u32 volatile *UARTRR_t ;
9647 +
9648 +enum
9649 +{
9650 + UARTIE_rda_b = 0,
9651 + UARTIE_rda_m = 0x00000001,
9652 + UARTIE_the_b = 1,
9653 + UARTIE_the_m = 0x00000002,
9654 + UARTIE_rls_b = 2,
9655 + UARTIE_rls_m = 0x00000004,
9656 + UARTIE_ems_b = 3,
9657 + UARTIE_ems_m = 0x00000008,
9658 +
9659 + UARTII_pi_b = 0,
9660 + UARTII_pi_m = 0x00000001,
9661 + UARTII_iid_b = 1,
9662 + UARTII_iid_m = 0x0000000e,
9663 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
9664 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
9665 + UARTII_iid_rda_v = 2, // Receive data available
9666 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
9667 + UARTII_iid_res4_v = 4, // reserved.
9668 + UARTII_iid_res5_v = 5, // reserved.
9669 + UARTII_iid_cto_v = 6, // Character timeout.
9670 + UARTII_iid_res7_v = 7, // reserved.
9671 +
9672 + UARTFC_en_b = 0,
9673 + UARTFC_en_m = 0x00000001,
9674 + UARTFC_rr_b = 1,
9675 + UARTFC_rr_m = 0x00000002,
9676 + UARTFC_tr_b = 2,
9677 + UARTFC_tr_m = 0x00000004,
9678 + UARTFC_dms_b = 3,
9679 + UARTFC_dms_m = 0x00000008,
9680 + UARTFC_rt_b = 6,
9681 + UARTFC_rt_m = 0x000000c0,
9682 + UARTFC_rt_1Byte_v = 0,
9683 + UARTFC_rt_4Byte_v = 1,
9684 + UARTFC_rt_8Byte_v = 2,
9685 + UARTFC_rt_14Byte_v = 3,
9686 +
9687 + UARTLC_wls_b = 0,
9688 + UARTLC_wls_m = 0x00000003,
9689 + UARTLC_wls_5Bits_v = 0,
9690 + UARTLC_wls_6Bits_v = 1,
9691 + UARTLC_wls_7Bits_v = 2,
9692 + UARTLC_wls_8Bits_v = 3,
9693 + UARTLC_stb_b = 2,
9694 + UARTLC_stb_m = 0x00000004,
9695 + UARTLC_pen_b = 3,
9696 + UARTLC_pen_m = 0x00000008,
9697 + UARTLC_eps_b = 4,
9698 + UARTLC_eps_m = 0x00000010,
9699 + UARTLC_sp_b = 5,
9700 + UARTLC_sp_m = 0x00000020,
9701 + UARTLC_sb_b = 6,
9702 + UARTLC_sb_m = 0x00000040,
9703 + UARTLC_dlab_b = 7,
9704 + UARTLC_dlab_m = 0x00000080,
9705 +
9706 + UARTMC_dtr_b = 0,
9707 + UARTMC_dtr_m = 0x00000001,
9708 + UARTMC_rts_b = 1,
9709 + UARTMC_rts_m = 0x00000002,
9710 + UARTMC_o1_b = 2,
9711 + UARTMC_o1_m = 0x00000004,
9712 + UARTMC_o2_b = 3,
9713 + UARTMC_o2_m = 0x00000008,
9714 + UARTMC_lp_b = 4,
9715 + UARTMC_lp_m = 0x00000010,
9716 +
9717 + UARTLS_dr_b = 0,
9718 + UARTLS_dr_m = 0x00000001,
9719 + UARTLS_oe_b = 1,
9720 + UARTLS_oe_m = 0x00000002,
9721 + UARTLS_pe_b = 2,
9722 + UARTLS_pe_m = 0x00000004,
9723 + UARTLS_fe_b = 3,
9724 + UARTLS_fe_m = 0x00000008,
9725 + UARTLS_bi_b = 4,
9726 + UARTLS_bi_m = 0x00000010,
9727 + UARTLS_thr_b = 5,
9728 + UARTLS_thr_m = 0x00000020,
9729 + UARTLS_te_b = 6,
9730 + UARTLS_te_m = 0x00000040,
9731 + UARTLS_rfe_b = 7,
9732 + UARTLS_rfe_m = 0x00000080,
9733 +
9734 + UARTMS_dcts_b = 0,
9735 + UARTMS_dcts_m = 0x00000001,
9736 + UARTMS_ddsr_b = 1,
9737 + UARTMS_ddsr_m = 0x00000002,
9738 + UARTMS_teri_b = 2,
9739 + UARTMS_teri_m = 0x00000004,
9740 + UARTMS_ddcd_b = 3,
9741 + UARTMS_ddcd_m = 0x00000008,
9742 + UARTMS_cts_b = 4,
9743 + UARTMS_cts_m = 0x00000010,
9744 + UARTMS_dsr_b = 5,
9745 + UARTMS_dsr_m = 0x00000020,
9746 + UARTMS_ri_b = 6,
9747 + UARTMS_ri_m = 0x00000040,
9748 + UARTMS_dcd_b = 7,
9749 + UARTMS_dcd_m = 0x00000080,
9750 +} ;
9751 +
9752 +#endif // __IDT_UART_H__
9753 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
9754 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
9755 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-01-10 00:32:33.000000000 +0100
9756 @@ -0,0 +1,231 @@
9757 +/**************************************************************************
9758 + *
9759 + * BRIEF MODULE DESCRIPTION
9760 + * Register definitions for IDT RC32438 DMA.
9761 + *
9762 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9763 + *
9764 + * This program is free software; you can redistribute it and/or modify it
9765 + * under the terms of the GNU General Public License as published by the
9766 + * Free Software Foundation; either version 2 of the License, or (at your
9767 + * option) any later version.
9768 + *
9769 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9770 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9771 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9772 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9773 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9774 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9775 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9776 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9777 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9778 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9779 + *
9780 + * You should have received a copy of the GNU General Public License along
9781 + * with this program; if not, write to the Free Software Foundation, Inc.,
9782 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9783 + *
9784 + *
9785 + **************************************************************************
9786 + * May 2004 P. Sadik.
9787 + *
9788 + * Initial Release
9789 + *
9790 + *
9791 + *
9792 + **************************************************************************
9793 + */
9794 +#ifndef __IDT_RC32438_DMA_H__
9795 +#define __IDT_RC32438_DMA_H__
9796 +enum
9797 +{
9798 + DMA0_PhysicalAddress = 0x18040000,
9799 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
9800 +
9801 + DMA0_VirtualAddress = 0xb8040000,
9802 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
9803 +} ;
9804 +
9805 +/*
9806 + * DMA descriptor (in physical memory).
9807 + */
9808 +
9809 +typedef struct DMAD_s
9810 +{
9811 + u32 control ; // Control. use DMAD_*
9812 + u32 ca ; // Current Address.
9813 + u32 devcs ; // Device control and status.
9814 + u32 link ; // Next descriptor in chain.
9815 +} volatile *DMAD_t ;
9816 +
9817 +enum
9818 +{
9819 + DMAD_size = sizeof (struct DMAD_s),
9820 + DMAD_count_b = 0, // in DMAD_t -> control
9821 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
9822 + DMAD_ds_b = 20, // in DMAD_t -> control
9823 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
9824 + DMAD_ds_extToMem0_v = 0,
9825 + DMAD_ds_memToExt0_v = 1,
9826 + DMAD_ds_extToMem1_v = 0,
9827 + DMAD_ds_memToExt1_v = 1,
9828 + DMAD_ds_ethRcv0_v = 0,
9829 + DMAD_ds_ethXmt0_v = 0,
9830 + DMAD_ds_ethRcv1_v = 0,
9831 + DMAD_ds_ethXmt2_v = 0,
9832 + DMAD_ds_memToFifo_v = 0,
9833 + DMAD_ds_fifoToMem_v = 0,
9834 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
9835 + DMAD_ds_pciToMem_v = 0,
9836 + DMAD_ds_memToPci_v = 0,
9837 + DMAD_ds_securityInput_v = 0,
9838 + DMAD_ds_securityOutput_v = 0,
9839 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
9840 +
9841 + DMAD_devcmd_b = 22, // in DMAD_t -> control
9842 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
9843 + DMAD_devcmd_byte_v = 0, //memory-to-memory
9844 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
9845 + DMAD_devcmd_word_v = 2, //memory-to-memory
9846 + DMAD_devcmd_2words_v = 3, //memory-to-memory
9847 + DMAD_devcmd_4words_v = 4, //memory-to-memory
9848 + DMAD_devcmd_6words_v = 5, //memory-to-memory
9849 + DMAD_devcmd_8words_v = 6, //memory-to-memory
9850 + DMAD_devcmd_16words_v = 7, //memory-to-memory
9851 + DMAD_cof_b = 25, // chain on finished
9852 + DMAD_cof_m = 0x02000000, //
9853 + DMAD_cod_b = 26, // chain on done
9854 + DMAD_cod_m = 0x04000000, //
9855 + DMAD_iof_b = 27, // interrupt on finished
9856 + DMAD_iof_m = 0x08000000, //
9857 + DMAD_iod_b = 28, // interrupt on done
9858 + DMAD_iod_m = 0x10000000, //
9859 + DMAD_t_b = 29, // terminated
9860 + DMAD_t_m = 0x20000000, //
9861 + DMAD_d_b = 30, // done
9862 + DMAD_d_m = 0x40000000, //
9863 + DMAD_f_b = 31, // finished
9864 + DMAD_f_m = 0x80000000, //
9865 +} ;
9866 +
9867 +/*
9868 + * DMA register (within Internal Register Map).
9869 + */
9870 +
9871 +struct DMA_Chan_s
9872 +{
9873 + u32 dmac ; // Control.
9874 + u32 dmas ; // Status.
9875 + u32 dmasm ; // Mask.
9876 + u32 dmadptr ; // Descriptor pointer.
9877 + u32 dmandptr ; // Next descriptor pointer.
9878 +};
9879 +
9880 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
9881 +
9882 +//DMA_Channels use DMACH_count instead
9883 +
9884 +enum
9885 +{
9886 + DMAC_run_b = 0, //
9887 + DMAC_run_m = 0x00000001, //
9888 + DMAC_dm_b = 1, // done mask
9889 + DMAC_dm_m = 0x00000002, //
9890 + DMAC_mode_b = 2, //
9891 + DMAC_mode_m = 0x0000000c, //
9892 + DMAC_mode_auto_v = 0,
9893 + DMAC_mode_burst_v = 1,
9894 + DMAC_mode_transfer_v = 2, //usually used
9895 + DMAC_mode_reserved_v = 3,
9896 + DMAC_a_b = 4, //
9897 + DMAC_a_m = 0x00000010, //
9898 +
9899 + DMAS_f_b = 0, // finished (sticky)
9900 + DMAS_f_m = 0x00000001, //
9901 + DMAS_d_b = 1, // done (sticky)
9902 + DMAS_d_m = 0x00000002, //
9903 + DMAS_c_b = 2, // chain (sticky)
9904 + DMAS_c_m = 0x00000004, //
9905 + DMAS_e_b = 3, // error (sticky)
9906 + DMAS_e_m = 0x00000008, //
9907 + DMAS_h_b = 4, // halt (sticky)
9908 + DMAS_h_m = 0x00000010, //
9909 +
9910 + DMASM_f_b = 0, // finished (1=mask)
9911 + DMASM_f_m = 0x00000001, //
9912 + DMASM_d_b = 1, // done (1=mask)
9913 + DMASM_d_m = 0x00000002, //
9914 + DMASM_c_b = 2, // chain (1=mask)
9915 + DMASM_c_m = 0x00000004, //
9916 + DMASM_e_b = 3, // error (1=mask)
9917 + DMASM_e_m = 0x00000008, //
9918 + DMASM_h_b = 4, // halt (1=mask)
9919 + DMASM_h_m = 0x00000010, //
9920 +} ;
9921 +
9922 +/*
9923 + * DMA channel definitions
9924 + */
9925 +
9926 +enum
9927 +{
9928 + DMACH_extToMem0 = 0,
9929 + DMACH_memToExt0 = 0,
9930 + DMACH_extToMem1 = 1,
9931 + DMACH_memToExt1 = 1,
9932 + DMACH_ethRcv0 = 2,
9933 + DMACH_ethXmt0 = 3,
9934 + DMACH_ethRcv1 = 4,
9935 + DMACH_ethXmt2 = 5,
9936 + DMACH_memToFifo = 6,
9937 + DMACH_fifoToMem = 7,
9938 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
9939 + DMACH_pciToMem = 8,
9940 + DMACH_memToPci = 9,
9941 + DMACH_securityInput = 10,
9942 + DMACH_securityOutput = 11,
9943 + DMACH_rng_se = 12, //randomNumberGenerator on SE
9944 +
9945 + DMACH_count //must be last
9946 +};
9947 +
9948 +
9949 +typedef struct DMAC_s
9950 +{
9951 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
9952 +} volatile *DMA_t ;
9953 +
9954 +
9955 +/*
9956 + * External DMA parameters
9957 +*/
9958 +
9959 +enum
9960 +{
9961 + DMADEVCMD_ts_b = 0, // ts field in devcmd
9962 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
9963 + DMADEVCMD_ts_byte_v = 0,
9964 + DMADEVCMD_ts_halfword_v = 1,
9965 + DMADEVCMD_ts_word_v = 2,
9966 + DMADEVCMD_ts_2word_v = 3,
9967 + DMADEVCMD_ts_4word_v = 4,
9968 + DMADEVCMD_ts_6word_v = 5,
9969 + DMADEVCMD_ts_8word_v = 6,
9970 + DMADEVCMD_ts_16word_v = 7
9971 +};
9972 +
9973 +
9974 +#if 1 // aws - Compatibility.
9975 +# define EXTDMA_ts_b DMADEVCMD_ts_b
9976 +# define EXTDMA_ts_m DMADEVCMD_ts_m
9977 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
9978 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
9979 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
9980 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
9981 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
9982 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
9983 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
9984 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
9985 +#endif // aws - Compatibility.
9986 +
9987 +#endif //__IDT_RC32438_DMA_H__
9988 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
9989 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
9990 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-01-10 00:32:33.000000000 +0100
9991 @@ -0,0 +1,82 @@
9992 +/**************************************************************************
9993 + *
9994 + * BRIEF MODULE DESCRIPTION
9995 + * DMA operations for IDT RC32438.
9996 + *
9997 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9998 + *
9999 + * This program is free software; you can redistribute it and/or modify it
10000 + * under the terms of the GNU General Public License as published by the
10001 + * Free Software Foundation; either version 2 of the License, or (at your
10002 + * option) any later version.
10003 + *
10004 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10005 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10006 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10007 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10008 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10009 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10010 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10011 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10012 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10013 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10014 + *
10015 + * You should have received a copy of the GNU General Public License along
10016 + * with this program; if not, write to the Free Software Foundation, Inc.,
10017 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10018 + *
10019 + *
10020 + **************************************************************************
10021 + * May 2004 P. Sadik.
10022 + *
10023 + * Initial Release
10024 + *
10025 + *
10026 + *
10027 + **************************************************************************
10028 + */
10029 +
10030 +#ifndef __IDT_RC32438_DMA_V_H__
10031 +#define __IDT_RC32438_DMA_V_H__
10032 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
10033 +
10034 +#define DMA_CHAN_OFFSET 0x14
10035 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
10036 +#define DMA_COUNT(count) \
10037 + ((count) & DMAD_count_m)
10038 +
10039 +#define DMA_HALT_TIMEOUT 500
10040 +
10041 +
10042 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
10043 +{
10044 + int timeout=1;
10045 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
10046 + rc32438_writel(0, &ch->dmac);
10047 +
10048 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
10049 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
10050 + rc32438_writel(0, &ch->dmas);
10051 + break;
10052 + }
10053 + }
10054 +
10055 + }
10056 +
10057 + return timeout ? 0 : 1;
10058 +}
10059 +
10060 +
10061 +
10062 +
10063 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
10064 +{
10065 + rc32438_writel(0, &ch->dmandptr);
10066 + rc32438_writel(dma_addr, &ch->dmadptr);
10067 +}
10068 +
10069 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
10070 +{
10071 + rc32438_writel(dma_addr, &ch->dmandptr);
10072 +}
10073 +#endif //__IDT_RC32438_DMA_V_H__
10074 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
10075 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
10076 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-01-10 00:32:33.000000000 +0100
10077 @@ -0,0 +1,328 @@
10078 +/**************************************************************************
10079 + *
10080 + * BRIEF MODULE DESCRIPTION
10081 + * Definitions for IDT EB438 ethernet
10082 + *
10083 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10084 + *
10085 + * This program is free software; you can redistribute it and/or modify it
10086 + * under the terms of the GNU General Public License as published by the
10087 + * Free Software Foundation; either version 2 of the License, or (at your
10088 + * option) any later version.
10089 + *
10090 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10091 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10092 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10093 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10094 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10095 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10096 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10097 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10098 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10099 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10100 + *
10101 + * You should have received a copy of the GNU General Public License along
10102 + * with this program; if not, write to the Free Software Foundation, Inc.,
10103 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10104 + *
10105 + *
10106 + **************************************************************************
10107 + * May 2004 P. Sadik.
10108 + *
10109 + * Initial Release
10110 + *
10111 + *
10112 + *
10113 + **************************************************************************
10114 + */
10115 +
10116 +#ifndef __IDT_RC32438_ETH_H__
10117 +#define __IDT_RC32438_ETH_H__
10118 +enum
10119 +{
10120 + ETH0_PhysicalAddress = 0x18058000,
10121 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
10122 +
10123 + ETH0_VirtualAddress = 0xb8058000,
10124 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
10125 + ETH1_PhysicalAddress = 0x18060000,
10126 + ETH1_VirtualAddress = 0xb8060000, // Default
10127 +} ;
10128 +
10129 +typedef struct
10130 +{
10131 + u32 ethintfc ;
10132 + u32 ethfifott ;
10133 + u32 etharc ;
10134 + u32 ethhash0 ;
10135 + u32 ethhash1 ;
10136 + u32 ethu0 [4] ; // Reserved.
10137 + u32 ethpfs ;
10138 + u32 ethmcp ;
10139 + u32 eth_u1 [10] ; // Reserved.
10140 + u32 ethspare ;
10141 + u32 eth_u2 [42] ; // Reserved.
10142 + u32 ethsal0 ;
10143 + u32 ethsah0 ;
10144 + u32 ethsal1 ;
10145 + u32 ethsah1 ;
10146 + u32 ethsal2 ;
10147 + u32 ethsah2 ;
10148 + u32 ethsal3 ;
10149 + u32 ethsah3 ;
10150 + u32 ethrbc ;
10151 + u32 ethrpc ;
10152 + u32 ethrupc ;
10153 + u32 ethrfc ;
10154 + u32 ethtbc ;
10155 + u32 ethgpf ;
10156 + u32 eth_u9 [50] ; // Reserved.
10157 + u32 ethmac1 ;
10158 + u32 ethmac2 ;
10159 + u32 ethipgt ;
10160 + u32 ethipgr ;
10161 + u32 ethclrt ;
10162 + u32 ethmaxf ;
10163 + u32 eth_u10 ; // Reserved.
10164 + u32 ethmtest ;
10165 + u32 miimcfg ;
10166 + u32 miimcmd ;
10167 + u32 miimaddr ;
10168 + u32 miimwtd ;
10169 + u32 miimrdd ;
10170 + u32 miimind ;
10171 + u32 eth_u11 ; // Reserved.
10172 + u32 eth_u12 ; // Reserved.
10173 + u32 ethcfsa0 ;
10174 + u32 ethcfsa1 ;
10175 + u32 ethcfsa2 ;
10176 +} volatile *ETH_t;
10177 +
10178 +enum
10179 +{
10180 + ETHINTFC_en_b = 0,
10181 + ETHINTFC_en_m = 0x00000001,
10182 + ETHINTFC_its_b = 1,
10183 + ETHINTFC_its_m = 0x00000002,
10184 + ETHINTFC_rip_b = 2,
10185 + ETHINTFC_rip_m = 0x00000004,
10186 + ETHINTFC_jam_b = 3,
10187 + ETHINTFC_jam_m = 0x00000008,
10188 + ETHINTFC_ovr_b = 4,
10189 + ETHINTFC_ovr_m = 0x00000010,
10190 + ETHINTFC_und_b = 5,
10191 + ETHINTFC_und_m = 0x00000020,
10192 +
10193 + ETHFIFOTT_tth_b = 0,
10194 + ETHFIFOTT_tth_m = 0x0000007f,
10195 +
10196 + ETHARC_pro_b = 0,
10197 + ETHARC_pro_m = 0x00000001,
10198 + ETHARC_am_b = 1,
10199 + ETHARC_am_m = 0x00000002,
10200 + ETHARC_afm_b = 2,
10201 + ETHARC_afm_m = 0x00000004,
10202 + ETHARC_ab_b = 3,
10203 + ETHARC_ab_m = 0x00000008,
10204 +
10205 + ETHSAL_byte5_b = 0,
10206 + ETHSAL_byte5_m = 0x000000ff,
10207 + ETHSAL_byte4_b = 8,
10208 + ETHSAL_byte4_m = 0x0000ff00,
10209 + ETHSAL_byte3_b = 16,
10210 + ETHSAL_byte3_m = 0x00ff0000,
10211 + ETHSAL_byte2_b = 24,
10212 + ETHSAL_byte2_m = 0xff000000,
10213 +
10214 + ETHSAH_byte1_b = 0,
10215 + ETHSAH_byte1_m = 0x000000ff,
10216 + ETHSAH_byte0_b = 8,
10217 + ETHSAH_byte0_m = 0x0000ff00,
10218 +
10219 + ETHGPF_ptv_b = 0,
10220 + ETHGPF_ptv_m = 0x0000ffff,
10221 +
10222 + ETHPFS_pfd_b = 0,
10223 + ETHPFS_pfd_m = 0x00000001,
10224 +
10225 + ETHCFSA0_cfsa4_b = 0,
10226 + ETHCFSA0_cfsa4_m = 0x000000ff,
10227 + ETHCFSA0_cfsa5_b = 8,
10228 + ETHCFSA0_cfsa5_m = 0x0000ff00,
10229 +
10230 + ETHCFSA1_cfsa2_b = 0,
10231 + ETHCFSA1_cfsa2_m = 0x000000ff,
10232 + ETHCFSA1_cfsa3_b = 8,
10233 + ETHCFSA1_cfsa3_m = 0x0000ff00,
10234 +
10235 + ETHCFSA2_cfsa0_b = 0,
10236 + ETHCFSA2_cfsa0_m = 0x000000ff,
10237 + ETHCFSA2_cfsa1_b = 8,
10238 + ETHCFSA2_cfsa1_m = 0x0000ff00,
10239 +
10240 + ETHMAC1_re_b = 0,
10241 + ETHMAC1_re_m = 0x00000001,
10242 + ETHMAC1_paf_b = 1,
10243 + ETHMAC1_paf_m = 0x00000002,
10244 + ETHMAC1_rfc_b = 2,
10245 + ETHMAC1_rfc_m = 0x00000004,
10246 + ETHMAC1_tfc_b = 3,
10247 + ETHMAC1_tfc_m = 0x00000008,
10248 + ETHMAC1_lb_b = 4,
10249 + ETHMAC1_lb_m = 0x00000010,
10250 + ETHMAC1_mr_b = 31,
10251 + ETHMAC1_mr_m = 0x80000000,
10252 +
10253 + ETHMAC2_fd_b = 0,
10254 + ETHMAC2_fd_m = 0x00000001,
10255 + ETHMAC2_flc_b = 1,
10256 + ETHMAC2_flc_m = 0x00000002,
10257 + ETHMAC2_hfe_b = 2,
10258 + ETHMAC2_hfe_m = 0x00000004,
10259 + ETHMAC2_dc_b = 3,
10260 + ETHMAC2_dc_m = 0x00000008,
10261 + ETHMAC2_cen_b = 4,
10262 + ETHMAC2_cen_m = 0x00000010,
10263 + ETHMAC2_pe_b = 5,
10264 + ETHMAC2_pe_m = 0x00000020,
10265 + ETHMAC2_vpe_b = 6,
10266 + ETHMAC2_vpe_m = 0x00000040,
10267 + ETHMAC2_ape_b = 7,
10268 + ETHMAC2_ape_m = 0x00000080,
10269 + ETHMAC2_ppe_b = 8,
10270 + ETHMAC2_ppe_m = 0x00000100,
10271 + ETHMAC2_lpe_b = 9,
10272 + ETHMAC2_lpe_m = 0x00000200,
10273 + ETHMAC2_nb_b = 12,
10274 + ETHMAC2_nb_m = 0x00001000,
10275 + ETHMAC2_bp_b = 13,
10276 + ETHMAC2_bp_m = 0x00002000,
10277 + ETHMAC2_ed_b = 14,
10278 + ETHMAC2_ed_m = 0x00004000,
10279 +
10280 + ETHIPGT_ipgt_b = 0,
10281 + ETHIPGT_ipgt_m = 0x0000007f,
10282 +
10283 + ETHIPGR_ipgr2_b = 0,
10284 + ETHIPGR_ipgr2_m = 0x0000007f,
10285 + ETHIPGR_ipgr1_b = 8,
10286 + ETHIPGR_ipgr1_m = 0x00007f00,
10287 +
10288 + ETHCLRT_maxret_b = 0,
10289 + ETHCLRT_maxret_m = 0x0000000f,
10290 + ETHCLRT_colwin_b = 8,
10291 + ETHCLRT_colwin_m = 0x00003f00,
10292 +
10293 + ETHMAXF_maxf_b = 0,
10294 + ETHMAXF_maxf_m = 0x0000ffff,
10295 +
10296 + ETHMTEST_tb_b = 2,
10297 + ETHMTEST_tb_m = 0x00000004,
10298 +
10299 + ETHMCP_div_b = 0,
10300 + ETHMCP_div_m = 0x000000ff,
10301 +
10302 + MIIMCFG_rsv_b = 0,
10303 + MIIMCFG_rsv_m = 0x0000000c,
10304 +
10305 + MIIMCMD_rd_b = 0,
10306 + MIIMCMD_rd_m = 0x00000001,
10307 + MIIMCMD_scn_b = 1,
10308 + MIIMCMD_scn_m = 0x00000002,
10309 +
10310 + MIIMADDR_regaddr_b = 0,
10311 + MIIMADDR_regaddr_m = 0x0000001f,
10312 + MIIMADDR_phyaddr_b = 8,
10313 + MIIMADDR_phyaddr_m = 0x00001f00,
10314 +
10315 + MIIMWTD_wdata_b = 0,
10316 + MIIMWTD_wdata_m = 0x0000ffff,
10317 +
10318 + MIIMRDD_rdata_b = 0,
10319 + MIIMRDD_rdata_m = 0x0000ffff,
10320 +
10321 + MIIMIND_bsy_b = 0,
10322 + MIIMIND_bsy_m = 0x00000001,
10323 + MIIMIND_scn_b = 1,
10324 + MIIMIND_scn_m = 0x00000002,
10325 + MIIMIND_nv_b = 2,
10326 + MIIMIND_nv_m = 0x00000004,
10327 +
10328 +} ;
10329 +
10330 +/*
10331 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
10332 + */
10333 +enum
10334 +{
10335 + ETHRX_fd_b = 0,
10336 + ETHRX_fd_m = 0x00000001,
10337 + ETHRX_ld_b = 1,
10338 + ETHRX_ld_m = 0x00000002,
10339 + ETHRX_rok_b = 2,
10340 + ETHRX_rok_m = 0x00000004,
10341 + ETHRX_fm_b = 3,
10342 + ETHRX_fm_m = 0x00000008,
10343 + ETHRX_mp_b = 4,
10344 + ETHRX_mp_m = 0x00000010,
10345 + ETHRX_bp_b = 5,
10346 + ETHRX_bp_m = 0x00000020,
10347 + ETHRX_vlt_b = 6,
10348 + ETHRX_vlt_m = 0x00000040,
10349 + ETHRX_cf_b = 7,
10350 + ETHRX_cf_m = 0x00000080,
10351 + ETHRX_ovr_b = 8,
10352 + ETHRX_ovr_m = 0x00000100,
10353 + ETHRX_crc_b = 9,
10354 + ETHRX_crc_m = 0x00000200,
10355 + ETHRX_cv_b = 10,
10356 + ETHRX_cv_m = 0x00000400,
10357 + ETHRX_db_b = 11,
10358 + ETHRX_db_m = 0x00000800,
10359 + ETHRX_le_b = 12,
10360 + ETHRX_le_m = 0x00001000,
10361 + ETHRX_lor_b = 13,
10362 + ETHRX_lor_m = 0x00002000,
10363 + ETHRX_ces_b = 14,
10364 + ETHRX_ces_m = 0x00004000,
10365 + ETHRX_length_b = 16,
10366 + ETHRX_length_m = 0xffff0000,
10367 +
10368 + ETHTX_fd_b = 0,
10369 + ETHTX_fd_m = 0x00000001,
10370 + ETHTX_ld_b = 1,
10371 + ETHTX_ld_m = 0x00000002,
10372 + ETHTX_oen_b = 2,
10373 + ETHTX_oen_m = 0x00000004,
10374 + ETHTX_pen_b = 3,
10375 + ETHTX_pen_m = 0x00000008,
10376 + ETHTX_cen_b = 4,
10377 + ETHTX_cen_m = 0x00000010,
10378 + ETHTX_hen_b = 5,
10379 + ETHTX_hen_m = 0x00000020,
10380 + ETHTX_tok_b = 6,
10381 + ETHTX_tok_m = 0x00000040,
10382 + ETHTX_mp_b = 7,
10383 + ETHTX_mp_m = 0x00000080,
10384 + ETHTX_bp_b = 8,
10385 + ETHTX_bp_m = 0x00000100,
10386 + ETHTX_und_b = 9,
10387 + ETHTX_und_m = 0x00000200,
10388 + ETHTX_of_b = 10,
10389 + ETHTX_of_m = 0x00000400,
10390 + ETHTX_ed_b = 11,
10391 + ETHTX_ed_m = 0x00000800,
10392 + ETHTX_ec_b = 12,
10393 + ETHTX_ec_m = 0x00001000,
10394 + ETHTX_lc_b = 13,
10395 + ETHTX_lc_m = 0x00002000,
10396 + ETHTX_td_b = 14,
10397 + ETHTX_td_m = 0x00004000,
10398 + ETHTX_crc_b = 15,
10399 + ETHTX_crc_m = 0x00008000,
10400 + ETHTX_le_b = 16,
10401 + ETHTX_le_m = 0x00010000,
10402 + ETHTX_cc_b = 17,
10403 + ETHTX_cc_m = 0x001E0000,
10404 +} ;
10405 +#endif //__IDT_RC32438_ETH_H__
10406 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
10407 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
10408 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-01-10 00:32:33.000000000 +0100
10409 @@ -0,0 +1,72 @@
10410 +/**************************************************************************
10411 + *
10412 + * BRIEF MODULE DESCRIPTION
10413 + * macros for IDT EB438 ethernet
10414 + *
10415 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10416 + *
10417 + * This program is free software; you can redistribute it and/or modify it
10418 + * under the terms of the GNU General Public License as published by the
10419 + * Free Software Foundation; either version 2 of the License, or (at your
10420 + * option) any later version.
10421 + *
10422 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10423 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10424 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10425 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10426 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10427 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10428 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10429 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10430 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10431 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10432 + *
10433 + * You should have received a copy of the GNU General Public License along
10434 + * with this program; if not, write to the Free Software Foundation, Inc.,
10435 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10436 + *
10437 + *
10438 + **************************************************************************
10439 + * May 2004 P. Sadik.
10440 + *
10441 + * Initial Release
10442 + *
10443 + *
10444 + *
10445 + **************************************************************************
10446 + */
10447 +
10448 +#ifndef __IDT_RC32438_ETH_V_H__
10449 +#define __IDT_RC32438_ETH_V_H__
10450 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
10451 +
10452 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
10453 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
10454 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
10455 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
10456 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
10457 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
10458 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
10459 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
10460 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
10461 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
10462 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
10463 +
10464 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
10465 +
10466 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
10467 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
10468 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
10469 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
10470 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
10471 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
10472 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
10473 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
10474 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
10475 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
10476 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
10477 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
10478 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
10479 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
10480 +
10481 +#endif //__IDT_RC32438_ETH_V_H__
10482 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
10483 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
10484 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-01-10 00:32:33.000000000 +0100
10485 @@ -0,0 +1,257 @@
10486 +/**************************************************************************
10487 + *
10488 + * BRIEF MODULE DESCRIPTION
10489 + * Definitions for IDT RC32438 GPIO.
10490 + *
10491 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10492 + *
10493 + * This program is free software; you can redistribute it and/or modify it
10494 + * under the terms of the GNU General Public License as published by the
10495 + * Free Software Foundation; either version 2 of the License, or (at your
10496 + * option) any later version.
10497 + *
10498 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10499 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10500 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10501 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10502 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10503 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10504 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10505 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10506 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10507 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10508 + *
10509 + * You should have received a copy of the GNU General Public License along
10510 + * with this program; if not, write to the Free Software Foundation, Inc.,
10511 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10512 + *
10513 + *
10514 + **************************************************************************
10515 + * May 2004 P. Sadik.
10516 + *
10517 + * Initial Release
10518 + *
10519 + *
10520 + *
10521 + **************************************************************************
10522 + */
10523 +#ifndef __IDT_RC32438_GPIO_H__
10524 +#define __IDT_RC32438_GPIO_H__
10525 +enum
10526 +{
10527 + GPIO0_PhysicalAddress = 0x18048000,
10528 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
10529 +
10530 + GPIO0_VirtualAddress = 0xb8048000,
10531 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
10532 +} ;
10533 +
10534 +typedef struct
10535 +{
10536 + u32 gpiofunc; /* GPIO Function Register
10537 + * gpiofunc[x]==0 bit = gpio
10538 + * func[x]==1 bit = altfunc
10539 + */
10540 + u32 gpiocfg; /* GPIO Configuration Register
10541 + * gpiocfg[x]==0 bit = input
10542 + * gpiocfg[x]==1 bit = output
10543 + */
10544 + u32 gpiod; /* GPIO Data Register
10545 + * gpiod[x] read/write gpio pinX status
10546 + */
10547 + u32 gpioilevel; /* GPIO Interrupt Status Register
10548 + * interrupt level (see gpioistat)
10549 + */
10550 + u32 gpioistat; /* Gpio Interrupt Status Register
10551 + * istat[x] = (gpiod[x] == level[x])
10552 + * cleared in ISR (STICKY bits)
10553 + */
10554 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
10555 +} volatile * GPIO_t ;
10556 +
10557 +typedef enum
10558 +{
10559 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
10560 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
10561 + GPIO_input_v = 0, // gpiocfg use pin as input.
10562 + GPIO_output_v = 1, // gpiocfg use pin as output.
10563 + GPIO_pin0_b = 0,
10564 + GPIO_pin0_m = 0x00000001,
10565 + GPIO_pin1_b = 1,
10566 + GPIO_pin1_m = 0x00000002,
10567 + GPIO_pin2_b = 2,
10568 + GPIO_pin2_m = 0x00000004,
10569 + GPIO_pin3_b = 3,
10570 + GPIO_pin3_m = 0x00000008,
10571 + GPIO_pin4_b = 4,
10572 + GPIO_pin4_m = 0x00000010,
10573 + GPIO_pin5_b = 5,
10574 + GPIO_pin5_m = 0x00000020,
10575 + GPIO_pin6_b = 6,
10576 + GPIO_pin6_m = 0x00000040,
10577 + GPIO_pin7_b = 7,
10578 + GPIO_pin7_m = 0x00000080,
10579 + GPIO_pin8_b = 8,
10580 + GPIO_pin8_m = 0x00000100,
10581 + GPIO_pin9_b = 9,
10582 + GPIO_pin9_m = 0x00000200,
10583 + GPIO_pin10_b = 10,
10584 + GPIO_pin10_m = 0x00000400,
10585 + GPIO_pin11_b = 11,
10586 + GPIO_pin11_m = 0x00000800,
10587 + GPIO_pin12_b = 12,
10588 + GPIO_pin12_m = 0x00001000,
10589 + GPIO_pin13_b = 13,
10590 + GPIO_pin13_m = 0x00002000,
10591 + GPIO_pin14_b = 14,
10592 + GPIO_pin14_m = 0x00004000,
10593 + GPIO_pin15_b = 15,
10594 + GPIO_pin15_m = 0x00008000,
10595 + GPIO_pin16_b = 16,
10596 + GPIO_pin16_m = 0x00010000,
10597 + GPIO_pin17_b = 17,
10598 + GPIO_pin17_m = 0x00020000,
10599 + GPIO_pin18_b = 18,
10600 + GPIO_pin18_m = 0x00040000,
10601 + GPIO_pin19_b = 19,
10602 + GPIO_pin19_m = 0x00080000,
10603 + GPIO_pin20_b = 20,
10604 + GPIO_pin20_m = 0x00100000,
10605 + GPIO_pin21_b = 21,
10606 + GPIO_pin21_m = 0x00200000,
10607 + GPIO_pin22_b = 22,
10608 + GPIO_pin22_m = 0x00400000,
10609 + GPIO_pin23_b = 23,
10610 + GPIO_pin23_m = 0x00800000,
10611 + GPIO_pin24_b = 24,
10612 + GPIO_pin24_m = 0x01000000,
10613 + GPIO_pin25_b = 25,
10614 + GPIO_pin25_m = 0x02000000,
10615 + GPIO_pin26_b = 26,
10616 + GPIO_pin26_m = 0x04000000,
10617 + GPIO_pin27_b = 27,
10618 + GPIO_pin27_m = 0x08000000,
10619 + GPIO_pin28_b = 28,
10620 + GPIO_pin28_m = 0x10000000,
10621 + GPIO_pin29_b = 29,
10622 + GPIO_pin29_m = 0x20000000,
10623 + GPIO_pin30_b = 30,
10624 + GPIO_pin30_m = 0x40000000,
10625 + GPIO_pin31_b = 31,
10626 + GPIO_pin31_m = 0x80000000,
10627 +
10628 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
10629 +
10630 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
10631 + GPIO_u0sout_m = GPIO_pin0_m,
10632 + GPIO_u0sout_cfg_v = GPIO_output_v,
10633 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
10634 + GPIO_u0sinp_m = GPIO_pin1_m,
10635 + GPIO_u0sinp_cfg_v = GPIO_input_v,
10636 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
10637 + GPIO_u0rin_m = GPIO_pin2_m,
10638 + GPIO_u0rin_cfg_v = GPIO_input_v,
10639 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
10640 + GPIO_u0dcdn_m = GPIO_pin3_m,
10641 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
10642 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
10643 + GPIO_u0dtrn_m = GPIO_pin4_m,
10644 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
10645 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
10646 + GPIO_u0dsrn_m = GPIO_pin5_m,
10647 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
10648 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
10649 + GPIO_u0rtsn_m = GPIO_pin6_m,
10650 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
10651 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
10652 + GPIO_u0ctsn_m = GPIO_pin7_m,
10653 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
10654 +
10655 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
10656 + GPIO_u1sout_m = GPIO_pin8_m,
10657 + GPIO_u1sout_cfg_v = GPIO_output_v,
10658 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
10659 + GPIO_u1sinp_m = GPIO_pin9_m,
10660 + GPIO_u1sinp_cfg_v = GPIO_input_v,
10661 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
10662 + GPIO_u1dtrn_m = GPIO_pin10_m,
10663 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
10664 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
10665 + GPIO_u1dsrn_m = GPIO_pin11_m,
10666 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
10667 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
10668 + GPIO_u1rtsn_m = GPIO_pin12_m,
10669 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
10670 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
10671 + GPIO_u1ctsn_m = GPIO_pin13_m,
10672 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
10673 +
10674 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
10675 + GPIO_dmareqn0_m = GPIO_pin14_m,
10676 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
10677 +
10678 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
10679 + GPIO_dmareqn1_m = GPIO_pin15_m,
10680 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
10681 +
10682 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
10683 + GPIO_dmadonen0_m = GPIO_pin16_m,
10684 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
10685 +
10686 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
10687 + GPIO_dmadonen1_m = GPIO_pin17_m,
10688 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
10689 +
10690 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
10691 + GPIO_dmafinn0_m = GPIO_pin18_m,
10692 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
10693 +
10694 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
10695 + GPIO_dmafinn1_m = GPIO_pin19_m,
10696 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
10697 +
10698 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
10699 + GPIO_maddr22_m = GPIO_pin20_m,
10700 + GPIO_maddr22_cfg_v = GPIO_output_v,
10701 +
10702 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
10703 + GPIO_maddr23_m = GPIO_pin21_m,
10704 + GPIO_maddr23_cfg_v = GPIO_output_v,
10705 +
10706 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
10707 + GPIO_maddr24_m = GPIO_pin22_m,
10708 + GPIO_maddr24_cfg_v = GPIO_output_v,
10709 +
10710 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
10711 + GPIO_maddr25_m = GPIO_pin23_m,
10712 + GPIO_maddr25_cfg_v = GPIO_output_v,
10713 +
10714 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
10715 + GPIO_afspare6_m = GPIO_pin24_m,
10716 + GPIO_afspare6_cfg_v = GPIO_input_v,
10717 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
10718 + GPIO_afspare5_m = GPIO_pin25_m,
10719 + GPIO_afspare5_cfg_v = GPIO_input_v,
10720 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
10721 + GPIO_afspare4_m = GPIO_pin26_m,
10722 + GPIO_afspare4_cfg_v = GPIO_input_v,
10723 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
10724 + GPIO_afspare3_m = GPIO_pin27_m,
10725 + GPIO_afspare3_cfg_v = GPIO_input_v,
10726 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
10727 + GPIO_afspare2_m = GPIO_pin28_m,
10728 + GPIO_afspare2_cfg_v = GPIO_input_v,
10729 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
10730 + GPIO_afspare1_m = GPIO_pin29_m,
10731 + GPIO_afspare1_cfg_v = GPIO_input_v,
10732 +
10733 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
10734 + GPIO_pcimuintn_m = GPIO_pin30_m,
10735 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
10736 +
10737 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
10738 + GPIO_rngclk_m = GPIO_pin31_m,
10739 + GPIO_rncclk_cfg_v = GPIO_input_v,
10740 +} GPIO_DEFS_t;
10741 +
10742 +#endif //__IDT_RC32438_GPIO_H__
10743 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h
10744 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
10745 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-01-10 00:32:33.000000000 +0100
10746 @@ -0,0 +1,152 @@
10747 +/**************************************************************************
10748 + *
10749 + * BRIEF MODULE DESCRIPTION
10750 + * Definitions for IDT RC32438 CPU.
10751 + *
10752 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10753 + *
10754 + * This program is free software; you can redistribute it and/or modify it
10755 + * under the terms of the GNU General Public License as published by the
10756 + * Free Software Foundation; either version 2 of the License, or (at your
10757 + * option) any later version.
10758 + *
10759 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10760 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10761 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10762 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10763 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10764 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10765 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10766 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10767 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10768 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10769 + *
10770 + * You should have received a copy of the GNU General Public License along
10771 + * with this program; if not, write to the Free Software Foundation, Inc.,
10772 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10773 + *
10774 + *
10775 + **************************************************************************
10776 + * May 2004 P. Sadik.
10777 + *
10778 + * Initial Release
10779 + *
10780 + *
10781 + *
10782 + **************************************************************************
10783 + */
10784 +
10785 +#ifndef __IDT_RC32438_H__
10786 +#define __IDT_RC32438_H__
10787 +#include <linux/config.h>
10788 +#include <linux/delay.h>
10789 +#include <asm/io.h>
10790 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
10791 +
10792 +#define RC32438_REG_BASE 0x18000000
10793 +
10794 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
10795 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
10796 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
10797 +
10798 +#define IDT_CLOCK_MULT 2
10799 +#define MIPS_CPU_TIMER_IRQ 7
10800 +/* Interrupt Controller */
10801 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
10802 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
10803 +#define IC_GROUP_OFFSET 0x0C
10804 +#define RTC_BASE 0xAC0801FF0
10805 +
10806 +#define NUM_INTR_GROUPS 5
10807 +/* 16550 UARTs */
10808 +
10809 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
10810 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
10811 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
10812 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
10813 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
10814 +
10815 +#ifdef __MIPSEB__
10816 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
10817 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
10818 +#else
10819 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
10820 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
10821 +#endif
10822 +
10823 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
10824 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
10825 +
10826 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
10827 +
10828 +
10829 +
10830 +/* cpu pipeline flush */
10831 +static inline void rc32438_sync(void)
10832 +{
10833 + __asm__ volatile ("sync");
10834 +}
10835 +
10836 +static inline void rc32438_sync_udelay(int us)
10837 +{
10838 + __asm__ volatile ("sync");
10839 + udelay(us);
10840 +}
10841 +
10842 +static inline void rc32438_sync_delay(int ms)
10843 +{
10844 + __asm__ volatile ("sync");
10845 + mdelay(ms);
10846 +}
10847 +
10848 +/*
10849 + * Macros to access internal RC32438 registers. No byte
10850 + * swapping should be done when accessing the internal
10851 + * registers.
10852 + */
10853 +
10854 +#define rc32438_readb __raw_readb
10855 +#define rc32438_readw __raw_readw
10856 +#define rc32438_readl __raw_readl
10857 +
10858 +#define rc32438_writeb __raw_writeb
10859 +#define rc32438_writew __raw_writew
10860 +#define rc32438_writel __raw_writel
10861 +
10862 +/*
10863 + * C access to CLZ and CLO instructions
10864 + * (count leading zeroes/ones).
10865 + */
10866 +static inline int rc32438_clz(unsigned long val)
10867 +{
10868 + int ret;
10869 + __asm__ volatile (
10870 + ".set\tnoreorder\n\t"
10871 + ".set\tnoat\n\t"
10872 + ".set\tmips32\n\t"
10873 + "clz\t%0,%1\n\t"
10874 + ".set\tmips0\n\t"
10875 + ".set\tat\n\t"
10876 + ".set\treorder"
10877 + : "=r" (ret)
10878 + : "r" (val));
10879 +
10880 + return ret;
10881 +}
10882 +static inline int rc32438_clo(unsigned long val)
10883 +{
10884 + int ret;
10885 + __asm__ volatile (
10886 + ".set\tnoreorder\n\t"
10887 + ".set\tnoat\n\t"
10888 + ".set\tmips32\n\t"
10889 + "clo\t%0,%1\n\t"
10890 + ".set\tmips0\n\t"
10891 + ".set\tat\n\t"
10892 + ".set\treorder"
10893 + : "=r" (ret)
10894 + : "r" (val));
10895 +
10896 + return ret;
10897 +}
10898 +#endif //__IDT_RC32438_H__
10899 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
10900 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
10901 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-01-10 00:32:33.000000000 +0100
10902 @@ -0,0 +1,510 @@
10903 +/**************************************************************************
10904 + *
10905 + * BRIEF MODULE DESCRIPTION
10906 + * Definitions for IDT RC32438 PCI.
10907 + *
10908 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10909 + *
10910 + * This program is free software; you can redistribute it and/or modify it
10911 + * under the terms of the GNU General Public License as published by the
10912 + * Free Software Foundation; either version 2 of the License, or (at your
10913 + * option) any later version.
10914 + *
10915 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10916 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10917 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10918 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10919 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10920 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10921 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10922 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10923 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10924 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10925 + *
10926 + * You should have received a copy of the GNU General Public License along
10927 + * with this program; if not, write to the Free Software Foundation, Inc.,
10928 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10929 + *
10930 + *
10931 + **************************************************************************
10932 + * May 2004 P. Sadik
10933 + *
10934 + * Initial Release
10935 + *
10936 + *
10937 + *
10938 + **************************************************************************
10939 + */
10940 +
10941 +enum
10942 +{
10943 + PCI0_PhysicalAddress = 0x18080000,
10944 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
10945 +
10946 + PCI0_VirtualAddress = 0xb8080000,
10947 + PCI_VirtualAddress = PCI0_VirtualAddress,
10948 +} ;
10949 +
10950 +enum
10951 +{
10952 + PCI_LbaCount = 4, // Local base addresses.
10953 +} ;
10954 +
10955 +typedef struct
10956 +{
10957 + u32 a ; // Address.
10958 + u32 c ; // Control.
10959 + u32 m ; // mapping.
10960 +} PCI_Map_s ;
10961 +
10962 +typedef struct
10963 +{
10964 + u32 pcic ;
10965 + u32 pcis ;
10966 + u32 pcism ;
10967 + u32 pcicfga ;
10968 + u32 pcicfgd ;
10969 + PCI_Map_s pcilba [PCI_LbaCount] ;
10970 + u32 pcidac ;
10971 + u32 pcidas ;
10972 + u32 pcidasm ;
10973 + u32 pcidad ;
10974 + u32 pcidma8c ;
10975 + u32 pcidma9c ;
10976 + u32 pcitc ;
10977 +} volatile *PCI_t ;
10978 +
10979 +// PCI messaging unit.
10980 +enum
10981 +{
10982 + PCIM_Count = 2,
10983 +} ;
10984 +typedef struct
10985 +{
10986 + u32 pciim [PCIM_Count] ;
10987 + u32 pciom [PCIM_Count] ;
10988 + u32 pciid ;
10989 + u32 pciiic ;
10990 + u32 pciiim ;
10991 + u32 pciiod ;
10992 + u32 pciioic ;
10993 + u32 pciioim ;
10994 +} volatile *PCIM_t ;
10995 +
10996 +/*******************************************************************************
10997 + *
10998 + * PCI Control Register
10999 + *
11000 + ******************************************************************************/
11001 +enum
11002 +{
11003 + PCIC_en_b = 0,
11004 + PCIC_en_m = 0x00000001,
11005 + PCIC_tnr_b = 1,
11006 + PCIC_tnr_m = 0x00000002,
11007 + PCIC_sce_b = 2,
11008 + PCIC_sce_m = 0x00000004,
11009 + PCIC_ien_b = 3,
11010 + PCIC_ien_m = 0x00000008,
11011 + PCIC_aaa_b = 4,
11012 + PCIC_aaa_m = 0x00000010,
11013 + PCIC_eap_b = 5,
11014 + PCIC_eap_m = 0x00000020,
11015 + PCIC_pcim_b = 6,
11016 + PCIC_pcim_m = 0x000001c0,
11017 + PCIC_pcim_disabled_v = 0,
11018 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
11019 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
11020 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
11021 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
11022 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
11023 + PCIC_pcim_reserved6_v = 6,
11024 + PCIC_pcim_reserved7_v = 7,
11025 + PCIC_igm_b = 9,
11026 + PCIC_igm_m = 0x00000200,
11027 +} ;
11028 +
11029 +/*******************************************************************************
11030 + *
11031 + * PCI Status Register
11032 + *
11033 + ******************************************************************************/
11034 +enum {
11035 + PCIS_eed_b = 0,
11036 + PCIS_eed_m = 0x00000001,
11037 + PCIS_wr_b = 1,
11038 + PCIS_wr_m = 0x00000002,
11039 + PCIS_nmi_b = 2,
11040 + PCIS_nmi_m = 0x00000004,
11041 + PCIS_ii_b = 3,
11042 + PCIS_ii_m = 0x00000008,
11043 + PCIS_cwe_b = 4,
11044 + PCIS_cwe_m = 0x00000010,
11045 + PCIS_cre_b = 5,
11046 + PCIS_cre_m = 0x00000020,
11047 + PCIS_mdpe_b = 6,
11048 + PCIS_mdpe_m = 0x00000040,
11049 + PCIS_sta_b = 7,
11050 + PCIS_sta_m = 0x00000080,
11051 + PCIS_rta_b = 8,
11052 + PCIS_rta_m = 0x00000100,
11053 + PCIS_rma_b = 9,
11054 + PCIS_rma_m = 0x00000200,
11055 + PCIS_sse_b = 10,
11056 + PCIS_sse_m = 0x00000400,
11057 + PCIS_ose_b = 11,
11058 + PCIS_ose_m = 0x00000800,
11059 + PCIS_pe_b = 12,
11060 + PCIS_pe_m = 0x00001000,
11061 + PCIS_tae_b = 13,
11062 + PCIS_tae_m = 0x00002000,
11063 + PCIS_rle_b = 14,
11064 + PCIS_rle_m = 0x00004000,
11065 + PCIS_bme_b = 15,
11066 + PCIS_bme_m = 0x00008000,
11067 + PCIS_prd_b = 16,
11068 + PCIS_prd_m = 0x00010000,
11069 + PCIS_rip_b = 17,
11070 + PCIS_rip_m = 0x00020000,
11071 +} ;
11072 +
11073 +/*******************************************************************************
11074 + *
11075 + * PCI Status Mask Register
11076 + *
11077 + ******************************************************************************/
11078 +enum {
11079 + PCISM_eed_b = 0,
11080 + PCISM_eed_m = 0x00000001,
11081 + PCISM_wr_b = 1,
11082 + PCISM_wr_m = 0x00000002,
11083 + PCISM_nmi_b = 2,
11084 + PCISM_nmi_m = 0x00000004,
11085 + PCISM_ii_b = 3,
11086 + PCISM_ii_m = 0x00000008,
11087 + PCISM_cwe_b = 4,
11088 + PCISM_cwe_m = 0x00000010,
11089 + PCISM_cre_b = 5,
11090 + PCISM_cre_m = 0x00000020,
11091 + PCISM_mdpe_b = 6,
11092 + PCISM_mdpe_m = 0x00000040,
11093 + PCISM_sta_b = 7,
11094 + PCISM_sta_m = 0x00000080,
11095 + PCISM_rta_b = 8,
11096 + PCISM_rta_m = 0x00000100,
11097 + PCISM_rma_b = 9,
11098 + PCISM_rma_m = 0x00000200,
11099 + PCISM_sse_b = 10,
11100 + PCISM_sse_m = 0x00000400,
11101 + PCISM_ose_b = 11,
11102 + PCISM_ose_m = 0x00000800,
11103 + PCISM_pe_b = 12,
11104 + PCISM_pe_m = 0x00001000,
11105 + PCISM_tae_b = 13,
11106 + PCISM_tae_m = 0x00002000,
11107 + PCISM_rle_b = 14,
11108 + PCISM_rle_m = 0x00004000,
11109 + PCISM_bme_b = 15,
11110 + PCISM_bme_m = 0x00008000,
11111 + PCISM_prd_b = 16,
11112 + PCISM_prd_m = 0x00010000,
11113 + PCISM_rip_b = 17,
11114 + PCISM_rip_m = 0x00020000,
11115 +} ;
11116 +
11117 +/*******************************************************************************
11118 + *
11119 + * PCI Configuration Address Register
11120 + *
11121 + ******************************************************************************/
11122 +enum {
11123 + PCICFGA_reg_b = 2,
11124 + PCICFGA_reg_m = 0x000000fc,
11125 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
11126 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
11127 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
11128 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
11129 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
11130 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
11131 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
11132 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
11133 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
11134 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
11135 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
11136 + PCICFGA_reg_pba0m_v = 0x48>>2,
11137 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
11138 + PCICFGA_reg_pba1m_v = 0x50>>2,
11139 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
11140 + PCICFGA_reg_pba2m_v = 0x58>>2,
11141 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
11142 + PCICFGA_reg_pba3m_v = 0x60>>2,
11143 + PCICFGA_reg_pmgt_v = 0x64>>2,
11144 + PCICFGA_func_b = 8,
11145 + PCICFGA_func_m = 0x00000700,
11146 + PCICFGA_dev_b = 11,
11147 + PCICFGA_dev_m = 0x0000f800,
11148 + PCICFGA_dev_internal_v = 0,
11149 + PCICFGA_bus_b = 16,
11150 + PCICFGA_bus_m = 0x00ff0000,
11151 + PCICFGA_bus_type0_v = 0, //local bus
11152 + PCICFGA_en_b = 31, // read only
11153 + PCICFGA_en_m = 0x80000000,
11154 +} ;
11155 +
11156 +enum {
11157 + PCFGID_vendor_b = 0,
11158 + PCFGID_vendor_m = 0x0000ffff,
11159 + PCFGID_vendor_IDT_v = 0x111d,
11160 + PCFGID_device_b = 16,
11161 + PCFGID_device_m = 0xffff0000,
11162 + PCFGID_device_Acaciade_v = 0x0207,
11163 +
11164 + PCFG04_command_ioena_b = 1,
11165 + PCFG04_command_ioena_m = 0x00000001,
11166 + PCFG04_command_memena_b = 2,
11167 + PCFG04_command_memena_m = 0x00000002,
11168 + PCFG04_command_bmena_b = 3,
11169 + PCFG04_command_bmena_m = 0x00000004,
11170 + PCFG04_command_mwinv_b = 5,
11171 + PCFG04_command_mwinv_m = 0x00000010,
11172 + PCFG04_command_parena_b = 7,
11173 + PCFG04_command_parena_m = 0x00000040,
11174 + PCFG04_command_serrena_b = 9,
11175 + PCFG04_command_serrena_m = 0x00000100,
11176 + PCFG04_command_fastbbena_b = 10,
11177 + PCFG04_command_fastbbena_m = 0x00000200,
11178 + PCFG04_status_b = 16,
11179 + PCFG04_status_m = 0xffff0000,
11180 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
11181 + PCFG04_status_66MHz_m = 0x00200000,
11182 + PCFG04_status_fbb_b = 23,
11183 + PCFG04_status_fbb_m = 0x00800000,
11184 + PCFG04_status_mdpe_b = 24,
11185 + PCFG04_status_mdpe_m = 0x01000000,
11186 + PCFG04_status_dst_b = 25,
11187 + PCFG04_status_dst_m = 0x06000000,
11188 + PCFG04_status_sta_b = 27,
11189 + PCFG04_status_sta_m = 0x08000000,
11190 + PCFG04_status_rta_b = 28,
11191 + PCFG04_status_rta_m = 0x10000000,
11192 + PCFG04_status_rma_b = 29,
11193 + PCFG04_status_rma_m = 0x20000000,
11194 + PCFG04_status_sse_b = 30,
11195 + PCFG04_status_sse_m = 0x40000000,
11196 + PCFG04_status_pe_b = 31,
11197 + PCFG04_status_pe_m = 0x40000000,
11198 +
11199 + PCFG08_revId_b = 0,
11200 + PCFG08_revId_m = 0x000000ff,
11201 + PCFG08_classCode_b = 0,
11202 + PCFG08_classCode_m = 0xffffff00,
11203 + PCFG08_classCode_bridge_v = 06,
11204 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
11205 + PCFG0C_cacheline_b = 0,
11206 + PCFG0C_cacheline_m = 0x000000ff,
11207 + PCFG0C_masterLatency_b = 8,
11208 + PCFG0C_masterLatency_m = 0x0000ff00,
11209 + PCFG0C_headerType_b = 16,
11210 + PCFG0C_headerType_m = 0x00ff0000,
11211 + PCFG0C_bist_b = 24,
11212 + PCFG0C_bist_m = 0xff000000,
11213 +
11214 + PCIPBA_msi_b = 0,
11215 + PCIPBA_msi_m = 0x00000001,
11216 + PCIPBA_p_b = 3,
11217 + PCIPBA_p_m = 0x00000004,
11218 + PCIPBA_baddr_b = 8,
11219 + PCIPBA_baddr_m = 0xffffff00,
11220 +
11221 + PCFGSS_vendorId_b = 0,
11222 + PCFGSS_vendorId_m = 0x0000ffff,
11223 + PCFGSS_id_b = 16,
11224 + PCFGSS_id_m = 0xffff0000,
11225 +
11226 + PCFG3C_interruptLine_b = 0,
11227 + PCFG3C_interruptLine_m = 0x000000ff,
11228 + PCFG3C_interruptPin_b = 8,
11229 + PCFG3C_interruptPin_m = 0x0000ff00,
11230 + PCFG3C_minGrant_b = 16,
11231 + PCFG3C_minGrant_m = 0x00ff0000,
11232 + PCFG3C_maxLat_b = 24,
11233 + PCFG3C_maxLat_m = 0xff000000,
11234 +
11235 + PCIPBAC_msi_b = 0,
11236 + PCIPBAC_msi_m = 0x00000001,
11237 + PCIPBAC_p_b = 1,
11238 + PCIPBAC_p_m = 0x00000002,
11239 + PCIPBAC_size_b = 2,
11240 + PCIPBAC_size_m = 0x0000007c,
11241 + PCIPBAC_sb_b = 7,
11242 + PCIPBAC_sb_m = 0x00000080,
11243 + PCIPBAC_pp_b = 8,
11244 + PCIPBAC_pp_m = 0x00000100,
11245 + PCIPBAC_mr_b = 9,
11246 + PCIPBAC_mr_m = 0x00000600,
11247 + PCIPBAC_mr_read_v =0, //no prefetching
11248 + PCIPBAC_mr_readLine_v =1,
11249 + PCIPBAC_mr_readMult_v =2,
11250 + PCIPBAC_mrl_b = 11,
11251 + PCIPBAC_mrl_m = 0x00000800,
11252 + PCIPBAC_mrm_b = 12,
11253 + PCIPBAC_mrm_m = 0x00001000,
11254 + PCIPBAC_trp_b = 13,
11255 + PCIPBAC_trp_m = 0x00002000,
11256 +
11257 + PCFG40_trdyTimeout_b = 0,
11258 + PCFG40_trdyTimeout_m = 0x000000ff,
11259 + PCFG40_retryLim_b = 8,
11260 + PCFG40_retryLim_m = 0x0000ff00,
11261 +};
11262 +
11263 +/*******************************************************************************
11264 + *
11265 + * PCI Local Base Address [0|1|2|3] Register
11266 + *
11267 + ******************************************************************************/
11268 +enum {
11269 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
11270 + PCILBA_baddr_m = 0xffffff00,
11271 +} ;
11272 +/*******************************************************************************
11273 + *
11274 + * PCI Local Base Address Control Register
11275 + *
11276 + ******************************************************************************/
11277 +enum {
11278 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
11279 + PCILBAC_msi_m = 0x00000001,
11280 + PCILBAC_msi_mem_v = 0,
11281 + PCILBAC_msi_io_v = 1,
11282 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
11283 + PCILBAC_size_m = 0x0000007c,
11284 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
11285 + PCILBAC_sb_m = 0x00000080,
11286 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
11287 + PCILBAC_rt_m = 0x00000100,
11288 + PCILBAC_rt_noprefetch_v = 0, // mem read
11289 + PCILBAC_rt_prefetch_v = 1, // mem readline
11290 +} ;
11291 +
11292 +/*******************************************************************************
11293 + *
11294 + * PCI Local Base Address [0|1|2|3] Mapping Register
11295 + *
11296 + ******************************************************************************/
11297 +enum {
11298 + PCILBAM_maddr_b = 8,
11299 + PCILBAM_maddr_m = 0xffffff00,
11300 +} ;
11301 +
11302 +/*******************************************************************************
11303 + *
11304 + * PCI Decoupled Access Control Register
11305 + *
11306 + ******************************************************************************/
11307 +enum {
11308 + PCIDAC_den_b = 0,
11309 + PCIDAC_den_m = 0x00000001,
11310 +} ;
11311 +
11312 +/*******************************************************************************
11313 + *
11314 + * PCI Decoupled Access Status Register
11315 + *
11316 + ******************************************************************************/
11317 +enum {
11318 + PCIDAS_d_b = 0,
11319 + PCIDAS_d_m = 0x00000001,
11320 + PCIDAS_b_b = 1,
11321 + PCIDAS_b_m = 0x00000002,
11322 + PCIDAS_e_b = 2,
11323 + PCIDAS_e_m = 0x00000004,
11324 + PCIDAS_ofe_b = 3,
11325 + PCIDAS_ofe_m = 0x00000008,
11326 + PCIDAS_off_b = 4,
11327 + PCIDAS_off_m = 0x00000010,
11328 + PCIDAS_ife_b = 5,
11329 + PCIDAS_ife_m = 0x00000020,
11330 + PCIDAS_iff_b = 6,
11331 + PCIDAS_iff_m = 0x00000040,
11332 +} ;
11333 +
11334 +/*******************************************************************************
11335 + *
11336 + * PCI DMA Channel 8 Configuration Register
11337 + *
11338 + ******************************************************************************/
11339 +enum
11340 +{
11341 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
11342 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
11343 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
11344 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
11345 +} ;
11346 +
11347 +/*******************************************************************************
11348 + *
11349 + * PCI DMA Channel 9 Configuration Register
11350 + *
11351 + ******************************************************************************/
11352 +enum
11353 +{
11354 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
11355 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
11356 +} ;
11357 +
11358 +/*******************************************************************************
11359 + *
11360 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
11361 + *
11362 + ******************************************************************************/
11363 +enum {
11364 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
11365 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
11366 + // These are for reads (DMA channel 8)
11367 + PCIDMAD_devcmd_mr_v = 0, //memory read
11368 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
11369 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
11370 + PCIDMAD_devcmd_ior_v = 3, //I/O read
11371 + // These are for writes (DMA channel 9)
11372 + PCIDMAD_devcmd_mw_v = 0, //memory write
11373 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
11374 + PCIDMAD_devcmd_iow_v = 3, //I/O write
11375 +
11376 + // Swap byte field applies to both DMA channel 8 and 9
11377 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
11378 + PCIDMAD_sb_m = 0x01000000, // swap byte field
11379 +} ;
11380 +
11381 +
11382 +/*******************************************************************************
11383 + *
11384 + * PCI Target Control Register
11385 + *
11386 + ******************************************************************************/
11387 +enum
11388 +{
11389 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
11390 + PCITC_rtimer_m = 0x000000ff,
11391 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
11392 + PCITC_dtimer_m = 0x0000ff00,
11393 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
11394 + PCITC_rdr_m = 0x00040000,
11395 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
11396 + PCITC_ddt_m = 0x00080000,
11397 +} ;
11398 +/*******************************************************************************
11399 + *
11400 + * PCI messaging unit [applies to both inbound and outbound registers ]
11401 + *
11402 + ******************************************************************************/
11403 +enum
11404 +{
11405 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
11406 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
11407 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
11408 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
11409 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
11410 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
11411 +};
11412 +
11413 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
11414 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
11415 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-01-10 00:32:33.000000000 +0100
11416 @@ -0,0 +1,190 @@
11417 +/**************************************************************************
11418 + *
11419 + * BRIEF MODULE DESCRIPTION
11420 + * Definitions for IDT RC32438 PCI setup.
11421 + *
11422 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
11423 + *
11424 + * This program is free software; you can redistribute it and/or modify it
11425 + * under the terms of the GNU General Public License as published by the
11426 + * Free Software Foundation; either version 2 of the License, or (at your
11427 + * option) any later version.
11428 + *
11429 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11430 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11431 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11432 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11433 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11434 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11435 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11436 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11437 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11438 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11439 + *
11440 + * You should have received a copy of the GNU General Public License along
11441 + * with this program; if not, write to the Free Software Foundation, Inc.,
11442 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11443 + *
11444 + *
11445 + **************************************************************************
11446 + * May 2004 P. Sadik
11447 + *
11448 + * Initial Release
11449 + *
11450 + *
11451 + *
11452 + **************************************************************************
11453 + */
11454 +
11455 +#define PCI_MSG_VirtualAddress 0xB8088010
11456 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
11457 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
11458 +
11459 +#define PCIM_SHFT 0x6
11460 +#define PCIM_BIT_LEN 0x7
11461 +#define PCIM_H_EA 0x3
11462 +#define PCIM_H_IA_FIX 0x4
11463 +#define PCIM_H_IA_RR 0x5
11464 +
11465 +#define PCI_ADDR_START 0x50000000
11466 +
11467 +#define CPUTOPCI_MEM_WIN 0x02000000
11468 +#define CPUTOPCI_IO_WIN 0x00100000
11469 +#define PCILBA_SIZE_SHFT 2
11470 +#define PCILBA_SIZE_MASK 0x1F
11471 +#define SIZE_256MB 0x1C
11472 +#define SIZE_128MB 0x1B
11473 +#define SIZE_64MB 0x1A
11474 +#define SIZE_32MB 0x19
11475 +#define SIZE_16MB 0x18
11476 +#define SIZE_4MB 0x16
11477 +#define SIZE_2MB 0x15
11478 +#define SIZE_1MB 0x14
11479 +#define ACACIA_CONFIG0_ADDR 0x80000000
11480 +#define ACACIA_CONFIG1_ADDR 0x80000004
11481 +#define ACACIA_CONFIG2_ADDR 0x80000008
11482 +#define ACACIA_CONFIG3_ADDR 0x8000000C
11483 +#define ACACIA_CONFIG4_ADDR 0x80000010
11484 +#define ACACIA_CONFIG5_ADDR 0x80000014
11485 +#define ACACIA_CONFIG6_ADDR 0x80000018
11486 +#define ACACIA_CONFIG7_ADDR 0x8000001C
11487 +#define ACACIA_CONFIG8_ADDR 0x80000020
11488 +#define ACACIA_CONFIG9_ADDR 0x80000024
11489 +#define ACACIA_CONFIG10_ADDR 0x80000028
11490 +#define ACACIA_CONFIG11_ADDR 0x8000002C
11491 +#define ACACIA_CONFIG12_ADDR 0x80000030
11492 +#define ACACIA_CONFIG13_ADDR 0x80000034
11493 +#define ACACIA_CONFIG14_ADDR 0x80000038
11494 +#define ACACIA_CONFIG15_ADDR 0x8000003C
11495 +#define ACACIA_CONFIG16_ADDR 0x80000040
11496 +#define ACACIA_CONFIG17_ADDR 0x80000044
11497 +#define ACACIA_CONFIG18_ADDR 0x80000048
11498 +#define ACACIA_CONFIG19_ADDR 0x8000004C
11499 +#define ACACIA_CONFIG20_ADDR 0x80000050
11500 +#define ACACIA_CONFIG21_ADDR 0x80000054
11501 +#define ACACIA_CONFIG22_ADDR 0x80000058
11502 +#define ACACIA_CONFIG23_ADDR 0x8000005C
11503 +#define ACACIA_CONFIG24_ADDR 0x80000060
11504 +#define ACACIA_CONFIG25_ADDR 0x80000064
11505 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
11506 + PCFG04_command_memena_m | \
11507 + PCFG04_command_bmena_m | \
11508 + PCFG04_command_mwinv_m | \
11509 + PCFG04_command_parena_m | \
11510 + PCFG04_command_serrena_m )
11511 +
11512 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
11513 + PCFG04_status_sta_m | \
11514 + PCFG04_status_rta_m | \
11515 + PCFG04_status_rma_m | \
11516 + PCFG04_status_sse_m | \
11517 + PCFG04_status_pe_m)
11518 +
11519 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
11520 +
11521 +#define ACACIA_REVID 0
11522 +#define ACACIA_CLASS_CODE 0
11523 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
11524 + ACACIA_REVID)
11525 +
11526 +#define ACACIA_CACHE_LINE_SIZE 4
11527 +#define ACACIA_MASTER_LAT 0x3c
11528 +#define ACACIA_HEADER_TYPE 0
11529 +#define ACACIA_BIST 0
11530 +
11531 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
11532 + (ACACIA_HEADER_TYPE<<16) | \
11533 + (ACACIA_MASTER_LAT<<8) | \
11534 + ACACIA_CACHE_LINE_SIZE )
11535 +
11536 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
11537 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
11538 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
11539 + internal Registers */
11540 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
11541 +
11542 +#define ACACIA_CNFG4 ACACIA_BAR0
11543 +#define ACACIA_CNFG5 ACACIA_BAR1
11544 +#define ACACIA_CNFG6 ACACIA_BAR2
11545 +#define ACACIA_CNFG7 ACACIA_BAR3
11546 +
11547 +#define ACACIA_SUBSYS_VENDOR_ID 0
11548 +#define ACACIA_SUBSYSTEM_ID 0
11549 +#define ACACIA_CNFG8 0
11550 +#define ACACIA_CNFG9 0
11551 +#define ACACIA_CNFG10 0
11552 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
11553 + ACACIA_SUBSYSTEM_ID)
11554 +#define ACACIA_INT_LINE 1
11555 +#define ACACIA_INT_PIN 1
11556 +#define ACACIA_MIN_GNT 8
11557 +#define ACACIA_MAX_LAT 0x38
11558 +#define ACACIA_CNFG12 0
11559 +#define ACACIA_CNFG13 0
11560 +#define ACACIA_CNFG14 0
11561 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
11562 + (ACACIA_MIN_GNT<<16) | \
11563 + (ACACIA_INT_PIN<<8) | \
11564 + ACACIA_INT_LINE)
11565 +#define ACACIA_RETRY_LIMIT 0x80
11566 +#define ACACIA_TRDY_LIMIT 0x80
11567 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
11568 + ACACIA_TRDY_LIMIT)
11569 +#define PCI_PBAxC_R 0x0
11570 +#define PCI_PBAxC_RL 0x1
11571 +#define PCI_PBAxC_RM 0x2
11572 +#define SIZE_SHFT 2
11573 +
11574 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
11575 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
11576 + PCIPBAC_pp_m | \
11577 + (SIZE_128MB<<SIZE_SHFT) | \
11578 + PCIPBAC_p_m)
11579 +
11580 +#define ACACIA_CNFG17 ACACIA_PBA0C
11581 +#define ACACIA_PBA0M 0x0
11582 +#define ACACIA_CNFG18 ACACIA_PBA0M
11583 +
11584 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
11585 + PCIPBAC_msi_m)
11586 +
11587 +#define ACACIA_CNFG19 ACACIA_PBA1C
11588 +#define ACACIA_PBA1M 0x0
11589 +#define ACACIA_CNFG20 ACACIA_PBA1M
11590 +
11591 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
11592 + PCIPBAC_msi_m)
11593 +
11594 +#define ACACIA_CNFG21 ACACIA_PBA2C
11595 +#define ACACIA_PBA2M 0x18000000
11596 +#define ACACIA_CNFG22 ACACIA_PBA2M
11597 +#define ACACIA_PBA3C 0
11598 +#define ACACIA_CNFG23 ACACIA_PBA3C
11599 +#define ACACIA_PBA3M 0
11600 +#define ACACIA_CNFG24 ACACIA_PBA3M
11601 +
11602 +
11603 +
11604 +#define PCITC_DTIMER_VAL 8
11605 +#define PCITC_RTIMER_VAL 0x10
11606 +
11607 diff -Nur linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
11608 --- linux-2.6.15/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
11609 +++ linux-2.6.15-openwrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-01-10 00:32:33.000000000 +0100
11610 @@ -0,0 +1,91 @@
11611 +/**************************************************************************
11612 + *
11613 + * BRIEF MODULE DESCRIPTION
11614 + * Timer register definition IDT RC32438 CPU.
11615 + *
11616 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
11617 + *
11618 + * This program is free software; you can redistribute it and/or modify it
11619 + * under the terms of the GNU General Public License as published by the
11620 + * Free Software Foundation; either version 2 of the License, or (at your
11621 + * option) any later version.
11622 + *
11623 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11624 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11625 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11626 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11627 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11628 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11629 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11630 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11631 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11632 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11633 + *
11634 + * You should have received a copy of the GNU General Public License along
11635 + * with this program; if not, write to the Free Software Foundation, Inc.,
11636 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11637 + *
11638 + *
11639 + **************************************************************************
11640 + * May 2004 P. Sadik.
11641 + *
11642 + * Initial Release
11643 + *
11644 + *
11645 + *
11646 + **************************************************************************
11647 + */
11648 +
11649 +#ifndef __IDT_RC32438_TIM_H__
11650 +#define __IDT_RC32438_TIM_H__
11651 +
11652 +enum
11653 +{
11654 + TIM0_PhysicalAddress = 0x18028000,
11655 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
11656 +
11657 + TIM0_VirtualAddress = 0xb8028000,
11658 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
11659 +} ;
11660 +
11661 +enum
11662 +{
11663 + TIM_Count = 3,
11664 +} ;
11665 +
11666 +struct TIM_CNTR_s
11667 +{
11668 + u32 count ;
11669 + u32 compare ;
11670 + u32 ctc ; //use CTC_
11671 +} ;
11672 +
11673 +typedef struct TIM_s
11674 +{
11675 + struct TIM_CNTR_s tim [TIM_Count] ;
11676 + u32 rcount ; //use RCOUNT_
11677 + u32 rcompare ; //use RCOMPARE_
11678 + u32 rtc ; //use RTC_
11679 +} volatile * TIM_t ;
11680 +
11681 +enum
11682 +{
11683 + CTC_en_b = 0,
11684 + CTC_en_m = 0x00000001,
11685 + CTC_to_b = 1,
11686 + CTC_to_m = 0x00000002,
11687 +
11688 + RCOUNT_count_b = 0,
11689 + RCOUNT_count_m = 0x0000ffff,
11690 + RCOMPARE_compare_b = 0,
11691 + RCOMPARE_compare_m = 0x0000ffff,
11692 + RTC_ce_b = 0,
11693 + RTC_ce_m = 0x00000001,
11694 + RTC_to_b = 1,
11695 + RTC_to_m = 0x00000002,
11696 + RTC_rqe_b = 2,
11697 + RTC_rqe_m = 0x00000004,
11698 +
11699 +} ;
11700 +#endif //__IDT_RC32438_TIM_H__
11701 +
11702 diff -Nur linux-2.6.15/include/asm-mips/mach-generic/irq.h linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h
11703 --- linux-2.6.15/include/asm-mips/mach-generic/irq.h 2006-01-03 04:21:10.000000000 +0100
11704 +++ linux-2.6.15-openwrt/include/asm-mips/mach-generic/irq.h 2006-01-10 00:32:33.000000000 +0100
11705 @@ -8,6 +8,6 @@
11706 #ifndef __ASM_MACH_GENERIC_IRQ_H
11707 #define __ASM_MACH_GENERIC_IRQ_H
11708
11709 -#define NR_IRQS 128
11710 +#define NR_IRQS 256
11711
11712 #endif /* __ASM_MACH_GENERIC_IRQ_H */
11713 diff -Nur linux-2.6.15/include/linux/init.h linux-2.6.15-openwrt/include/linux/init.h
11714 --- linux-2.6.15/include/linux/init.h 2006-01-03 04:21:10.000000000 +0100
11715 +++ linux-2.6.15-openwrt/include/linux/init.h 2006-01-10 00:32:33.000000000 +0100
11716 @@ -86,6 +86,8 @@
11717 static initcall_t __initcall_##fn __attribute_used__ \
11718 __attribute__((__section__(".initcall" level ".init"))) = fn
11719
11720 +#define early_initcall(fn) __define_initcall(".early1",fn)
11721 +
11722 #define core_initcall(fn) __define_initcall("1",fn)
11723 #define postcore_initcall(fn) __define_initcall("2",fn)
11724 #define arch_initcall(fn) __define_initcall("3",fn)
11725 diff -Nur linux-2.6.15/include/linux/kernel.h linux-2.6.15-openwrt/include/linux/kernel.h
11726 --- linux-2.6.15/include/linux/kernel.h 2006-01-03 04:21:10.000000000 +0100
11727 +++ linux-2.6.15-openwrt/include/linux/kernel.h 2006-01-10 00:32:33.000000000 +0100
11728 @@ -307,6 +307,7 @@
11729 };
11730
11731 /* Force a compilation error if condition is true */
11732 +extern void BUILD_BUG(void);
11733 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
11734
11735 #ifdef CONFIG_SYSCTL
11736 diff -Nur linux-2.6.15/Makefile linux-2.6.15-openwrt/Makefile
11737 --- linux-2.6.15/Makefile 2006-01-03 04:21:10.000000000 +0100
11738 +++ linux-2.6.15-openwrt/Makefile 2006-01-10 00:32:33.000000000 +0100
11739 @@ -166,10 +166,7 @@
11740 # then ARCH is assigned, getting whatever value it gets normally, and
11741 # SUBARCH is subsequently ignored.
11742
11743 -SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
11744 - -e s/arm.*/arm/ -e s/sa110/arm/ \
11745 - -e s/s390x/s390/ -e s/parisc64/parisc/ \
11746 - -e s/ppc64/powerpc/ )
11747 +SUBARCH := mips
11748
11749 # Cross compiling and selecting different set of gcc/bin-utils
11750 # ---------------------------------------------------------------------------
11751 diff -Nur linux-2.6.15/drivers/net/natsemi.c linux-2.6.15-openwrt/drivers/net/natsemi.c
11752 --- linux-2.6.15/drivers/net/natsemi.c 2006-01-02 19:21:10.000000000 -0800
11753 +++ linux-2.6.15-openwrt/drivers/net/natsemi.c 2006-01-10 07:29:49.581994000 -0800
11754 @@ -771,6 +771,49 @@
11755 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
11756 static struct ethtool_ops ethtool_ops;
11757
11758 +#ifdef CONFIG_MACH_ARUBA
11759 +
11760 +#include <linux/ctype.h>
11761 +
11762 +#ifndef ERR
11763 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
11764 +#endif
11765 +
11766 +static int parse_mac_addr(struct net_device *dev, char* macstr)
11767 +{
11768 + int i, j;
11769 + unsigned char result, value;
11770 +
11771 + for (i=0; i<6; i++) {
11772 + result = 0;
11773 + if (i != 5 && *(macstr+2) != ':') {
11774 + ERR("invalid mac address format: %d %c\n",
11775 + i, *(macstr+2));
11776 + return -EINVAL;
11777 + }
11778 + for (j=0; j<2; j++) {
11779 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
11780 + toupper(*macstr)-'A'+10) < 16) {
11781 + result = result*16 + value;
11782 + macstr++;
11783 + }
11784 + else {
11785 + ERR("invalid mac address "
11786 + "character: %c\n", *macstr);
11787 + return -EINVAL;
11788 + }
11789 + }
11790 +
11791 + macstr++;
11792 + dev->dev_addr[i] = result;
11793 + }
11794 +
11795 + dev->dev_addr[5]++;
11796 + return 0;
11797 +}
11798 +
11799 +#endif
11800 +
11801 static inline void __iomem *ns_ioaddr(struct net_device *dev)
11802 {
11803 return (void __iomem *) dev->base_addr;
11804 @@ -859,6 +902,7 @@
11805 goto err_ioremap;
11806 }
11807
11808 +#ifndef CONFIG_MACH_ARUBA
11809 /* Work around the dropped serial bit. */
11810 prev_eedata = eeprom_read(ioaddr, 6);
11811 for (i = 0; i < 3; i++) {
11812 @@ -867,6 +911,19 @@
11813 dev->dev_addr[i*2+1] = eedata >> 7;
11814 prev_eedata = eedata;
11815 }
11816 +#else
11817 + {
11818 + char mac[32];
11819 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
11820 + extern char *getenv(char *e);
11821 + memset(mac, 0, 32);
11822 + memcpy(mac, getenv("ethaddr"), 17);
11823 + if (parse_mac_addr(dev, mac)){
11824 + printk("%s: MAC address not found\n", __func__);
11825 + memcpy(dev->dev_addr, def_mac, 6);
11826 + }
11827 + }
11828 +#endif
11829
11830 dev->base_addr = (unsigned long __force) ioaddr;
11831 dev->irq = irq;
11832 diff -Nur linux-2.6.15/drivers/net/Makefile linux-2.6.15-openwrt/drivers/net/Makefile
11833 --- linux-2.6.15/drivers/net/Makefile 2006-01-13 09:19:55.000000000 -0800
11834 +++ linux-2.6.15-openwrt/drivers/net/Makefile 2006-01-09 20:44:10.378339000 -0800
11835 @@ -35,6 +35,7 @@
11836
11837 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
11838
11839 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
11840 obj-$(CONFIG_DGRS) += dgrs.o
11841 obj-$(CONFIG_VORTEX) += 3c59x.o
11842 obj-$(CONFIG_TYPHOON) += typhoon.o
11843 @@ -190,7 +189,6 @@
11844 obj-$(CONFIG_SMC91X) += smc91x.o
11845 obj-$(CONFIG_DM9000) += dm9000.o
11846 obj-$(CONFIG_FEC_8XX) += fec_8xx/
11847 -obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
11848
11849 obj-$(CONFIG_ARM) += arm/
11850 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
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