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ar71xx: build image for the Hornet-UB board
[openwrt.git] / target / linux / generic / patches-2.6.39 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
4 if (!ccdev)
5 return;
6 bus = ccdev->bus;
7 +
8 + /* We support SLOW only on 6..9 */
9 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
10 + mode = SSB_CLKMODE_DYNAMIC;
11 +
12 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
13 + return; /* PMU controls clockmode, separated function needed */
14 + SSB_WARN_ON(ccdev->id.revision >= 20);
15 +
16 /* chipcommon cores prior to rev6 don't support dynamic clock control */
17 if (ccdev->id.revision < 6)
18 return;
19 - /* chipcommon cores rev10 are a whole new ball game */
20 +
21 + /* ChipCommon cores rev10+ need testing */
22 if (ccdev->id.revision >= 10)
23 return;
24 +
25 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
26 return;
27
28 switch (mode) {
29 - case SSB_CLKMODE_SLOW:
30 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
31 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
32 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
33 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
34 break;
35 case SSB_CLKMODE_FAST:
36 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
37 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
38 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
39 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
40 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
41 + if (ccdev->id.revision < 10) {
42 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
43 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
44 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
45 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
46 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
47 + } else {
48 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
49 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
50 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
51 + /* udelay(150); TODO: not available in early init */
52 + }
53 break;
54 case SSB_CLKMODE_DYNAMIC:
55 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
56 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
57 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
58 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
59 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
60 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
61 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
62 -
63 - /* for dynamic control, we have to release our xtal_pu "force on" */
64 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
65 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
66 + if (ccdev->id.revision < 10) {
67 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
68 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
69 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
70 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
71 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
72 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
73 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
74 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
75 +
76 + /* For dynamic control, we have to release our xtal_pu
77 + * "force on" */
78 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
79 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
80 + } else {
81 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
82 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
83 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
84 + }
85 break;
86 default:
87 SSB_WARN_ON(1);
88 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
89 if (cc->dev->id.revision >= 11)
90 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
91 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
92 +
93 + if (cc->dev->id.revision >= 20) {
94 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
95 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
96 + }
97 +
98 ssb_pmu_init(cc);
99 chipco_powercontrol_init(cc);
100 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
101 --- a/drivers/ssb/driver_chipcommon_pmu.c
102 +++ b/drivers/ssb/driver_chipcommon_pmu.c
103 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
104 u32 min_msk = 0, max_msk = 0;
105 unsigned int i;
106 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
107 - unsigned int updown_tab_size;
108 + unsigned int updown_tab_size = 0;
109 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
110 - unsigned int depend_tab_size;
111 + unsigned int depend_tab_size = 0;
112
113 switch (bus->chip_id) {
114 case 0x4312:
115 + min_msk = 0xCBB;
116 + break;
117 case 0x4322:
118 /* We keep the default settings:
119 * min_msk = 0xCBB
120 --- a/drivers/ssb/driver_gige.c
121 +++ b/drivers/ssb/driver_gige.c
122 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
123 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
124 }
125
126 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
127 - int reg, int size, u32 *val)
128 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
129 + unsigned int devfn, int reg,
130 + int size, u32 *val)
131 {
132 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
133 unsigned long flags;
134 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
135 return PCIBIOS_SUCCESSFUL;
136 }
137
138 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
139 - int reg, int size, u32 val)
140 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
141 + unsigned int devfn, int reg,
142 + int size, u32 val)
143 {
144 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
145 unsigned long flags;
146 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
147 return PCIBIOS_SUCCESSFUL;
148 }
149
150 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
151 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
152 + const struct ssb_device_id *id)
153 {
154 struct ssb_gige *dev;
155 u32 base, tmslow, tmshigh;
156 --- a/drivers/ssb/driver_pcicore.c
157 +++ b/drivers/ssb/driver_pcicore.c
158 @@ -15,6 +15,11 @@
159
160 #include "ssb_private.h"
161
162 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
163 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
164 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
165 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
166 + u8 address, u16 data);
167
168 static inline
169 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
170 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
171 return ssb_mips_irq(extpci_core->dev) + 2;
172 }
173
174 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
175 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
176 {
177 u32 val;
178
179 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
180 register_pci_controller(&ssb_pcicore_controller);
181 }
182
183 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
184 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
185 {
186 struct ssb_bus *bus = pc->dev->bus;
187 u16 chipid_top;
188 @@ -403,25 +408,133 @@ static int pcicore_is_in_hostmode(struct
189 }
190 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
191
192 +/**************************************************
193 + * Workarounds.
194 + **************************************************/
195 +
196 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
197 +{
198 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
199 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
200 + tmp &= ~0xF000;
201 + tmp |= (pc->dev->core_index << 12);
202 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
203 + }
204 +}
205 +
206 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
207 +{
208 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
209 +}
210 +
211 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
212 +{
213 + const u8 serdes_pll_device = 0x1D;
214 + const u8 serdes_rx_device = 0x1F;
215 + u16 tmp;
216 +
217 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
218 + ssb_pcicore_polarity_workaround(pc));
219 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
220 + if (tmp & 0x4000)
221 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
222 +}
223 +
224 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
225 +{
226 + struct ssb_device *pdev = pc->dev;
227 + struct ssb_bus *bus = pdev->bus;
228 + u32 tmp;
229 +
230 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
231 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
232 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
233 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
234 +
235 + if (pdev->id.revision < 5) {
236 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
237 + tmp &= ~SSB_IMCFGLO_SERTO;
238 + tmp |= 2;
239 + tmp &= ~SSB_IMCFGLO_REQTO;
240 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
241 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
242 + ssb_commit_settings(bus);
243 + } else if (pdev->id.revision >= 11) {
244 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
245 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
246 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
247 + }
248 +}
249 +
250 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
251 +{
252 + u32 tmp;
253 + u8 rev = pc->dev->id.revision;
254 +
255 + if (rev == 0 || rev == 1) {
256 + /* TLP Workaround register. */
257 + tmp = ssb_pcie_read(pc, 0x4);
258 + tmp |= 0x8;
259 + ssb_pcie_write(pc, 0x4, tmp);
260 + }
261 + if (rev == 1) {
262 + /* DLLP Link Control register. */
263 + tmp = ssb_pcie_read(pc, 0x100);
264 + tmp |= 0x40;
265 + ssb_pcie_write(pc, 0x100, tmp);
266 + }
267 +
268 + if (rev == 0) {
269 + const u8 serdes_rx_device = 0x1F;
270 +
271 + ssb_pcie_mdio_write(pc, serdes_rx_device,
272 + 2 /* Timer */, 0x8128);
273 + ssb_pcie_mdio_write(pc, serdes_rx_device,
274 + 6 /* CDR */, 0x0100);
275 + ssb_pcie_mdio_write(pc, serdes_rx_device,
276 + 7 /* CDR BW */, 0x1466);
277 + } else if (rev == 3 || rev == 4 || rev == 5) {
278 + /* TODO: DLLP Power Management Threshold */
279 + ssb_pcicore_serdes_workaround(pc);
280 + /* TODO: ASPM */
281 + } else if (rev == 7) {
282 + /* TODO: No PLL down */
283 + }
284 +
285 + if (rev >= 6) {
286 + /* Miscellaneous Configuration Fixup */
287 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
288 + if (!(tmp & 0x8000))
289 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
290 + tmp | 0x8000);
291 + }
292 +}
293
294 /**************************************************
295 * Generic and Clientmode operation code.
296 **************************************************/
297
298 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
299 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
300 {
301 + ssb_pcicore_fix_sprom_core_index(pc);
302 +
303 /* Disable PCI interrupts. */
304 ssb_write32(pc->dev, SSB_INTVEC, 0);
305 +
306 + /* Additional PCIe always once-executed workarounds */
307 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
308 + ssb_pcicore_serdes_workaround(pc);
309 + /* TODO: ASPM */
310 + /* TODO: Clock Request Update */
311 + }
312 }
313
314 -void ssb_pcicore_init(struct ssb_pcicore *pc)
315 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
316 {
317 struct ssb_device *dev = pc->dev;
318 - struct ssb_bus *bus;
319
320 if (!dev)
321 return;
322 - bus = dev->bus;
323 if (!ssb_device_is_enabled(dev))
324 ssb_device_enable(dev, 0);
325
326 @@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pc
327 pcicore_write32(pc, 0x134, data);
328 }
329
330 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
331 - u8 address, u16 data)
332 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
333 +{
334 + const u16 mdio_control = 0x128;
335 + const u16 mdio_data = 0x12C;
336 + u32 v;
337 + int i;
338 +
339 + v = (1 << 30); /* Start of Transaction */
340 + v |= (1 << 28); /* Write Transaction */
341 + v |= (1 << 17); /* Turnaround */
342 + v |= (0x1F << 18);
343 + v |= (phy << 4);
344 + pcicore_write32(pc, mdio_data, v);
345 +
346 + udelay(10);
347 + for (i = 0; i < 200; i++) {
348 + v = pcicore_read32(pc, mdio_control);
349 + if (v & 0x100 /* Trans complete */)
350 + break;
351 + msleep(1);
352 + }
353 +}
354 +
355 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
356 {
357 const u16 mdio_control = 0x128;
358 const u16 mdio_data = 0x12C;
359 + int max_retries = 10;
360 + u16 ret = 0;
361 u32 v;
362 int i;
363
364 @@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct s
365 v |= 0x2; /* MDIO Clock Divisor */
366 pcicore_write32(pc, mdio_control, v);
367
368 + if (pc->dev->id.revision >= 10) {
369 + max_retries = 200;
370 + ssb_pcie_mdio_set_phy(pc, device);
371 + }
372 +
373 v = (1 << 30); /* Start of Transaction */
374 - v |= (1 << 28); /* Write Transaction */
375 + v |= (1 << 29); /* Read Transaction */
376 v |= (1 << 17); /* Turnaround */
377 - v |= (u32)device << 22;
378 + if (pc->dev->id.revision < 10)
379 + v |= (u32)device << 22;
380 v |= (u32)address << 18;
381 - v |= data;
382 pcicore_write32(pc, mdio_data, v);
383 /* Wait for the device to complete the transaction */
384 udelay(10);
385 - for (i = 0; i < 10; i++) {
386 + for (i = 0; i < max_retries; i++) {
387 v = pcicore_read32(pc, mdio_control);
388 - if (v & 0x100 /* Trans complete */)
389 + if (v & 0x100 /* Trans complete */) {
390 + udelay(10);
391 + ret = pcicore_read32(pc, mdio_data);
392 break;
393 + }
394 msleep(1);
395 }
396 pcicore_write32(pc, mdio_control, 0);
397 + return ret;
398 }
399
400 -static void ssb_broadcast_value(struct ssb_device *dev,
401 - u32 address, u32 data)
402 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
403 + u8 address, u16 data)
404 {
405 - /* This is used for both, PCI and ChipCommon core, so be careful. */
406 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
407 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
408 + const u16 mdio_control = 0x128;
409 + const u16 mdio_data = 0x12C;
410 + int max_retries = 10;
411 + u32 v;
412 + int i;
413
414 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
415 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
416 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
417 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
418 -}
419 + v = 0x80; /* Enable Preamble Sequence */
420 + v |= 0x2; /* MDIO Clock Divisor */
421 + pcicore_write32(pc, mdio_control, v);
422
423 -static void ssb_commit_settings(struct ssb_bus *bus)
424 -{
425 - struct ssb_device *dev;
426 + if (pc->dev->id.revision >= 10) {
427 + max_retries = 200;
428 + ssb_pcie_mdio_set_phy(pc, device);
429 + }
430
431 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
432 - if (WARN_ON(!dev))
433 - return;
434 - /* This forces an update of the cached registers. */
435 - ssb_broadcast_value(dev, 0xFD8, 0);
436 + v = (1 << 30); /* Start of Transaction */
437 + v |= (1 << 28); /* Write Transaction */
438 + v |= (1 << 17); /* Turnaround */
439 + if (pc->dev->id.revision < 10)
440 + v |= (u32)device << 22;
441 + v |= (u32)address << 18;
442 + v |= data;
443 + pcicore_write32(pc, mdio_data, v);
444 + /* Wait for the device to complete the transaction */
445 + udelay(10);
446 + for (i = 0; i < max_retries; i++) {
447 + v = pcicore_read32(pc, mdio_control);
448 + if (v & 0x100 /* Trans complete */)
449 + break;
450 + msleep(1);
451 + }
452 + pcicore_write32(pc, mdio_control, 0);
453 }
454
455 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
456 @@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
457 if (pc->setup_done)
458 goto out;
459 if (pdev->id.coreid == SSB_DEV_PCI) {
460 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
461 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
462 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
463 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
464 -
465 - if (pdev->id.revision < 5) {
466 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
467 - tmp &= ~SSB_IMCFGLO_SERTO;
468 - tmp |= 2;
469 - tmp &= ~SSB_IMCFGLO_REQTO;
470 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
471 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
472 - ssb_commit_settings(bus);
473 - } else if (pdev->id.revision >= 11) {
474 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
475 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
476 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
477 - }
478 + ssb_pcicore_pci_setup_workarounds(pc);
479 } else {
480 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
481 - //TODO: Better make defines for all these magic PCIE values.
482 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
483 - /* TLP Workaround register. */
484 - tmp = ssb_pcie_read(pc, 0x4);
485 - tmp |= 0x8;
486 - ssb_pcie_write(pc, 0x4, tmp);
487 - }
488 - if (pdev->id.revision == 0) {
489 - const u8 serdes_rx_device = 0x1F;
490 -
491 - ssb_pcie_mdio_write(pc, serdes_rx_device,
492 - 2 /* Timer */, 0x8128);
493 - ssb_pcie_mdio_write(pc, serdes_rx_device,
494 - 6 /* CDR */, 0x0100);
495 - ssb_pcie_mdio_write(pc, serdes_rx_device,
496 - 7 /* CDR BW */, 0x1466);
497 - } else if (pdev->id.revision == 1) {
498 - /* DLLP Link Control register. */
499 - tmp = ssb_pcie_read(pc, 0x100);
500 - tmp |= 0x40;
501 - ssb_pcie_write(pc, 0x100, tmp);
502 - }
503 + ssb_pcicore_pcie_setup_workarounds(pc);
504 }
505 pc->setup_done = 1;
506 out:
507 --- a/drivers/ssb/main.c
508 +++ b/drivers/ssb/main.c
509 @@ -557,7 +557,7 @@ error:
510 }
511
512 /* Needs ssb_buses_lock() */
513 -static int ssb_attach_queued_buses(void)
514 +static int __devinit ssb_attach_queued_buses(void)
515 {
516 struct ssb_bus *bus, *n;
517 int err = 0;
518 @@ -768,9 +768,9 @@ out:
519 return err;
520 }
521
522 -static int ssb_bus_register(struct ssb_bus *bus,
523 - ssb_invariants_func_t get_invariants,
524 - unsigned long baseaddr)
525 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
526 + ssb_invariants_func_t get_invariants,
527 + unsigned long baseaddr)
528 {
529 int err;
530
531 @@ -851,8 +851,8 @@ err_disable_xtal:
532 }
533
534 #ifdef CONFIG_SSB_PCIHOST
535 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
536 - struct pci_dev *host_pci)
537 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
538 + struct pci_dev *host_pci)
539 {
540 int err;
541
542 @@ -875,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
543 #endif /* CONFIG_SSB_PCIHOST */
544
545 #ifdef CONFIG_SSB_PCMCIAHOST
546 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
547 - struct pcmcia_device *pcmcia_dev,
548 - unsigned long baseaddr)
549 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
550 + struct pcmcia_device *pcmcia_dev,
551 + unsigned long baseaddr)
552 {
553 int err;
554
555 @@ -897,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
556 #endif /* CONFIG_SSB_PCMCIAHOST */
557
558 #ifdef CONFIG_SSB_SDIOHOST
559 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
560 - unsigned int quirks)
561 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
562 + struct sdio_func *func,
563 + unsigned int quirks)
564 {
565 int err;
566
567 @@ -918,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_
568 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
569 #endif /* CONFIG_SSB_PCMCIAHOST */
570
571 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
572 - unsigned long baseaddr,
573 - ssb_invariants_func_t get_invariants)
574 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
575 + unsigned long baseaddr,
576 + ssb_invariants_func_t get_invariants)
577 {
578 int err;
579
580 @@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
581 switch (plltype) {
582 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
583 if (m & SSB_CHIPCO_CLK_T6_MMASK)
584 - return SSB_CHIPCO_CLK_T6_M0;
585 - return SSB_CHIPCO_CLK_T6_M1;
586 + return SSB_CHIPCO_CLK_T6_M1;
587 + return SSB_CHIPCO_CLK_T6_M0;
588 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
589 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
590 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
591 @@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(str
592 {
593 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
594
595 - /* The REJECT bit changed position in TMSLOW between
596 - * Backplane revisions. */
597 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
598 switch (rev) {
599 case SSB_IDLOW_SSBREV_22:
600 - return SSB_TMSLOW_REJECT_22;
601 + case SSB_IDLOW_SSBREV_24:
602 + case SSB_IDLOW_SSBREV_26:
603 + return SSB_TMSLOW_REJECT;
604 case SSB_IDLOW_SSBREV_23:
605 return SSB_TMSLOW_REJECT_23;
606 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
607 - case SSB_IDLOW_SSBREV_25: /* same here */
608 - case SSB_IDLOW_SSBREV_26: /* same here */
609 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
610 case SSB_IDLOW_SSBREV_27: /* same here */
611 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
612 + return SSB_TMSLOW_REJECT; /* this is a guess */
613 default:
614 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
615 WARN_ON(1);
616 }
617 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
618 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
619 }
620
621 int ssb_device_is_enabled(struct ssb_device *dev)
622 @@ -1266,7 +1266,10 @@ u32 ssb_dma_translation(struct ssb_devic
623 case SSB_BUSTYPE_SSB:
624 return 0;
625 case SSB_BUSTYPE_PCI:
626 - return SSB_PCI_DMA;
627 + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
628 + return SSB_PCIE_DMA_H32;
629 + else
630 + return SSB_PCI_DMA;
631 default:
632 __ssb_dma_not_implemented(dev);
633 }
634 @@ -1309,20 +1312,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
635
636 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
637 {
638 - struct ssb_chipcommon *cc;
639 int err;
640 enum ssb_clkmode mode;
641
642 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
643 if (err)
644 goto error;
645 - cc = &bus->chipco;
646 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
647 - ssb_chipco_set_clockmode(cc, mode);
648
649 #ifdef CONFIG_SSB_DEBUG
650 bus->powered_up = 1;
651 #endif
652 +
653 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
654 + ssb_chipco_set_clockmode(&bus->chipco, mode);
655 +
656 return 0;
657 error:
658 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
659 @@ -1330,6 +1333,37 @@ error:
660 }
661 EXPORT_SYMBOL(ssb_bus_powerup);
662
663 +static void ssb_broadcast_value(struct ssb_device *dev,
664 + u32 address, u32 data)
665 +{
666 +#ifdef CONFIG_SSB_DRIVER_PCICORE
667 + /* This is used for both, PCI and ChipCommon core, so be careful. */
668 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
669 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
670 +#endif
671 +
672 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
673 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
674 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
675 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
676 +}
677 +
678 +void ssb_commit_settings(struct ssb_bus *bus)
679 +{
680 + struct ssb_device *dev;
681 +
682 +#ifdef CONFIG_SSB_DRIVER_PCICORE
683 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
684 +#else
685 + dev = bus->chipco.dev;
686 +#endif
687 + if (WARN_ON(!dev))
688 + return;
689 + /* This forces an update of the cached registers. */
690 + ssb_broadcast_value(dev, 0xFD8, 0);
691 +}
692 +EXPORT_SYMBOL(ssb_commit_settings);
693 +
694 u32 ssb_admatch_base(u32 adm)
695 {
696 u32 base = 0;
697 --- a/drivers/ssb/pci.c
698 +++ b/drivers/ssb/pci.c
699 @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus
700 static int ssb_pci_sprom_get(struct ssb_bus *bus,
701 struct ssb_sprom *sprom)
702 {
703 - const struct ssb_sprom *fallback;
704 int err;
705 u16 *buf;
706
707 @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_
708 if (err) {
709 /* All CRC attempts failed.
710 * Maybe there is no SPROM on the device?
711 - * If we have a fallback, use that. */
712 - fallback = ssb_get_fallback_sprom();
713 - if (fallback) {
714 - memcpy(sprom, fallback, sizeof(*sprom));
715 + * Now we ask the arch code if there is some sprom
716 + * available for this device in some other storage */
717 + err = ssb_fill_sprom_with_fallback(bus, sprom);
718 + if (err) {
719 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
720 + " fallback SPROM failed (err %d)\n",
721 + err);
722 + } else {
723 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
724 + " revision %d provided by"
725 + " platform.\n", sprom->revision);
726 err = 0;
727 goto out_free;
728 }
729 @@ -728,12 +734,9 @@ out_free:
730 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
731 struct ssb_boardinfo *bi)
732 {
733 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
734 - &bi->vendor);
735 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
736 - &bi->type);
737 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
738 - &bi->rev);
739 + bi->vendor = bus->host_pci->subsystem_vendor;
740 + bi->type = bus->host_pci->subsystem_device;
741 + bi->rev = bus->host_pci->revision;
742 }
743
744 int ssb_pci_get_invariants(struct ssb_bus *bus,
745 --- a/drivers/ssb/pcihost_wrapper.c
746 +++ b/drivers/ssb/pcihost_wrapper.c
747 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
748 # define ssb_pcihost_resume NULL
749 #endif /* CONFIG_PM */
750
751 -static int ssb_pcihost_probe(struct pci_dev *dev,
752 - const struct pci_device_id *id)
753 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
754 + const struct pci_device_id *id)
755 {
756 struct ssb_bus *ssb;
757 int err = -ENOMEM;
758 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
759 pci_set_drvdata(dev, NULL);
760 }
761
762 -int ssb_pcihost_register(struct pci_driver *driver)
763 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
764 {
765 driver->probe = ssb_pcihost_probe;
766 driver->remove = ssb_pcihost_remove;
767 --- a/drivers/ssb/scan.c
768 +++ b/drivers/ssb/scan.c
769 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
770 #ifdef CONFIG_SSB_PCIHOST
771 if (bus->bustype == SSB_BUSTYPE_PCI) {
772 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
773 - bus->host_pci->device == 0x4324)
774 + ((bus->host_pci->device == 0x4313) ||
775 + (bus->host_pci->device == 0x431A) ||
776 + (bus->host_pci->device == 0x4321) ||
777 + (bus->host_pci->device == 0x4324)))
778 return 1;
779 }
780 #endif /* CONFIG_SSB_PCIHOST */
781 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
782 } else {
783 if (bus->bustype == SSB_BUSTYPE_PCI) {
784 bus->chip_id = pcidev_to_chipid(bus->host_pci);
785 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
786 - &bus->chip_rev);
787 + bus->chip_rev = bus->host_pci->revision;
788 bus->chip_package = 0;
789 } else {
790 bus->chip_id = 0x4710;
791 --- a/drivers/ssb/sprom.c
792 +++ b/drivers/ssb/sprom.c
793 @@ -17,7 +17,7 @@
794 #include <linux/slab.h>
795
796
797 -static const struct ssb_sprom *fallback_sprom;
798 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
799
800
801 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
802 @@ -145,36 +145,43 @@ out:
803 }
804
805 /**
806 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
807 + * ssb_arch_register_fallback_sprom - Registers a method providing a
808 + * fallback SPROM if no SPROM is found.
809 *
810 - * @sprom: The SPROM data structure to register.
811 + * @sprom_callback: The callback function.
812 *
813 - * With this function the architecture implementation may register a fallback
814 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
815 - * where no valid SPROM can be found in the shadow registers.
816 + * With this function the architecture implementation may register a
817 + * callback handler which fills the SPROM data structure. The fallback is
818 + * only used for PCI based SSB devices, where no valid SPROM can be found
819 + * in the shadow registers.
820 *
821 - * This function is useful for weird architectures that have a half-assed SSB device
822 - * hardwired to their PCI bus.
823 + * This function is useful for weird architectures that have a half-assed
824 + * SSB device hardwired to their PCI bus.
825 *
826 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
827 - * don't use this fallback.
828 - * Architectures must provide the SPROM for native SSB devices anyway,
829 - * so the fallback also isn't used for native devices.
830 + * Note that it does only work with PCI attached SSB devices. PCMCIA
831 + * devices currently don't use this fallback.
832 + * Architectures must provide the SPROM for native SSB devices anyway, so
833 + * the fallback also isn't used for native devices.
834 *
835 - * This function is available for architecture code, only. So it is not exported.
836 + * This function is available for architecture code, only. So it is not
837 + * exported.
838 */
839 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
840 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
841 + struct ssb_sprom *out))
842 {
843 - if (fallback_sprom)
844 + if (get_fallback_sprom)
845 return -EEXIST;
846 - fallback_sprom = sprom;
847 + get_fallback_sprom = sprom_callback;
848
849 return 0;
850 }
851
852 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
853 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
854 {
855 - return fallback_sprom;
856 + if (!get_fallback_sprom)
857 + return -ENOENT;
858 +
859 + return get_fallback_sprom(bus, out);
860 }
861
862 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
863 --- a/drivers/ssb/ssb_private.h
864 +++ b/drivers/ssb/ssb_private.h
865 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
866 const char *buf, size_t count,
867 int (*sprom_check_crc)(const u16 *sprom, size_t size),
868 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
869 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
870 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
871 + struct ssb_sprom *out);
872
873
874 /* core.c */
875 --- a/include/linux/ssb/ssb.h
876 +++ b/include/linux/ssb/ssb.h
877 @@ -27,6 +27,8 @@ struct ssb_sprom {
878 u8 et1mdcport; /* MDIO for enet1 */
879 u8 board_rev; /* Board revision number from SPROM. */
880 u8 country_code; /* Country Code */
881 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
882 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
883 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
884 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
885 u16 pa0b0;
886 @@ -99,7 +101,7 @@ struct ssb_sprom {
887 struct ssb_boardinfo {
888 u16 vendor;
889 u16 type;
890 - u16 rev;
891 + u8 rev;
892 };
893
894
895 @@ -308,7 +310,7 @@ struct ssb_bus {
896
897 /* ID information about the Chip. */
898 u16 chip_id;
899 - u16 chip_rev;
900 + u8 chip_rev;
901 u16 sprom_offset;
902 u16 sprom_size; /* number of words in sprom */
903 u8 chip_package;
904 @@ -404,7 +406,9 @@ extern bool ssb_is_sprom_available(struc
905
906 /* Set a fallback SPROM.
907 * See kdoc at the function definition for complete documentation. */
908 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
909 +extern int ssb_arch_register_fallback_sprom(
910 + int (*sprom_callback)(struct ssb_bus *bus,
911 + struct ssb_sprom *out));
912
913 /* Suspend a SSB bus.
914 * Call this from the parent bus suspend routine. */
915 @@ -518,6 +522,7 @@ extern int ssb_bus_may_powerdown(struct
916 * Otherwise static always-on powercontrol will be used. */
917 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
918
919 +extern void ssb_commit_settings(struct ssb_bus *bus);
920
921 /* Various helper functions */
922 extern u32 ssb_admatch_base(u32 adm);
923 --- a/include/linux/ssb/ssb_driver_chipcommon.h
924 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
925 @@ -123,6 +123,8 @@
926 #define SSB_CHIPCO_FLASHDATA 0x0048
927 #define SSB_CHIPCO_BCAST_ADDR 0x0050
928 #define SSB_CHIPCO_BCAST_DATA 0x0054
929 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
930 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
931 #define SSB_CHIPCO_GPIOIN 0x0060
932 #define SSB_CHIPCO_GPIOOUT 0x0064
933 #define SSB_CHIPCO_GPIOOUTEN 0x0068
934 @@ -131,6 +133,9 @@
935 #define SSB_CHIPCO_GPIOIRQ 0x0074
936 #define SSB_CHIPCO_WATCHDOG 0x0080
937 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
938 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
939 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
940 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
941 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
942 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
943 #define SSB_CHIPCO_CLOCK_N 0x0090
944 @@ -189,8 +194,10 @@
945 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
946 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
947 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
948 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
949 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
950 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
951 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
952 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
953 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
954 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
955 #define SSB_CHIPCO_UART0_DATA 0x0300
956 #define SSB_CHIPCO_UART0_IMR 0x0304
957 --- a/include/linux/ssb/ssb_regs.h
958 +++ b/include/linux/ssb/ssb_regs.h
959 @@ -97,7 +97,7 @@
960 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
961 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
962 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
963 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
964 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
965 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
966 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
967 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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