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add my 2.6.15-rc5 port (yay) with devfs. The PCI subsystem is broken on Broadcom...
[openwrt.git] / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2005-11-07 23:12:50.582887000 +0100
3 +++ linux.dev/arch/mips/Makefile 2005-11-07 21:57:08.537629000 +0100
4 @@ -727,6 +727,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -779,6 +793,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-11-08 00:55:04.392074500 +0100
35 @@ -0,0 +1,15 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := nvram_linux.o setup.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o
48 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
52 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-11-07 21:57:07.841585500 +0100
54 @@ -0,0 +1,33 @@
55 +#
56 +# Makefile for Broadcom BCM947XX boards
57 +#
58 +# Copyright 2001-2003, Broadcom Corporation
59 +# All Rights Reserved.
60 +#
61 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
62 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
63 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
64 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
65 +#
66 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
67 +#
68 +
69 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
70 +SYSTEM ?= $(TOPDIR)/vmlinux
71 +
72 +all: vmlinuz
73 +
74 +# Don't build dependencies, this may die if $(CC) isn't gcc
75 +dep:
76 +
77 +# Create a gzipped version named vmlinuz for compatibility
78 +vmlinuz: piggy
79 + gzip -c9 $< > $@
80 +
81 +piggy: $(SYSTEM)
82 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
83 +
84 +mrproper: clean
85 +
86 +clean:
87 + rm -f vmlinuz piggy
88 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
89 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
90 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-11-07 21:57:07.841585500 +0100
91 @@ -0,0 +1,15 @@
92 +#
93 +# Makefile for the BCM947xx specific kernel interface routines
94 +# under Linux.
95 +#
96 +
97 +.S.s:
98 + $(CPP) $(AFLAGS) $< -o $*.s
99 +.S.o:
100 + $(CC) $(AFLAGS) -c $< -o $*.o
101 +
102 +O_TARGET := brcm.o
103 +
104 +obj-y := int-handler.o irq.o
105 +
106 +include $(TOPDIR)/Rules.make
107 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
108 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
109 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-11-07 21:57:07.841585500 +0100
110 @@ -0,0 +1,51 @@
111 +/*
112 + * Generic interrupt handler for Broadcom MIPS boards
113 + *
114 + * Copyright 2004, Broadcom Corporation
115 + * All Rights Reserved.
116 + *
117 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
118 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
119 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
120 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
121 + *
122 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
123 + */
124 +
125 +#include <linux/config.h>
126 +
127 +#include <asm/asm.h>
128 +#include <asm/mipsregs.h>
129 +#include <asm/regdef.h>
130 +#include <asm/stackframe.h>
131 +
132 +/*
133 + * MIPS IRQ Source
134 + * -------- ------
135 + * 0 Software (ignored)
136 + * 1 Software (ignored)
137 + * 2 Combined hardware interrupt (hw0)
138 + * 3 Hardware
139 + * 4 Hardware
140 + * 5 Hardware
141 + * 6 Hardware
142 + * 7 R4k timer
143 + */
144 +
145 + .text
146 + .set noreorder
147 + .set noat
148 + .align 5
149 + NESTED(brcmIRQ, PT_SIZE, sp)
150 + SAVE_ALL
151 + CLI
152 + .set at
153 + .set noreorder
154 +
155 + jal brcm_irq_dispatch
156 + move a0, sp
157 +
158 + j ret_from_irq
159 + nop
160 +
161 + END(brcmIRQ)
162 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
163 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
164 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-11-07 21:57:07.841585500 +0100
165 @@ -0,0 +1,130 @@
166 +/*
167 + * Generic interrupt control functions for Broadcom MIPS boards
168 + *
169 + * Copyright 2004, Broadcom Corporation
170 + * All Rights Reserved.
171 + *
172 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
173 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
174 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
175 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
176 + *
177 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
178 + */
179 +
180 +#include <linux/config.h>
181 +#include <linux/init.h>
182 +#include <linux/kernel.h>
183 +#include <linux/types.h>
184 +#include <linux/interrupt.h>
185 +#include <linux/irq.h>
186 +
187 +#include <asm/irq.h>
188 +#include <asm/mipsregs.h>
189 +#include <asm/gdb-stub.h>
190 +
191 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
192 +
193 +extern asmlinkage void brcmIRQ(void);
194 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
195 +
196 +void
197 +brcm_irq_dispatch(struct pt_regs *regs)
198 +{
199 + u32 cause;
200 +
201 + cause = read_c0_cause() &
202 + read_c0_status() &
203 + CAUSEF_IP;
204 +
205 +#ifdef CONFIG_KERNPROF
206 + change_c0_status(cause | 1, 1);
207 +#else
208 + clear_c0_status(cause);
209 +#endif
210 +
211 + if (cause & CAUSEF_IP7)
212 + do_IRQ(7, regs);
213 + if (cause & CAUSEF_IP2)
214 + do_IRQ(2, regs);
215 + if (cause & CAUSEF_IP3)
216 + do_IRQ(3, regs);
217 + if (cause & CAUSEF_IP4)
218 + do_IRQ(4, regs);
219 + if (cause & CAUSEF_IP5)
220 + do_IRQ(5, regs);
221 + if (cause & CAUSEF_IP6)
222 + do_IRQ(6, regs);
223 +}
224 +
225 +static void
226 +enable_brcm_irq(unsigned int irq)
227 +{
228 + if (irq < 8)
229 + set_c0_status(1 << (irq + 8));
230 + else
231 + set_c0_status(IE_IRQ0);
232 +}
233 +
234 +static void
235 +disable_brcm_irq(unsigned int irq)
236 +{
237 + if (irq < 8)
238 + clear_c0_status(1 << (irq + 8));
239 + else
240 + clear_c0_status(IE_IRQ0);
241 +}
242 +
243 +static void
244 +ack_brcm_irq(unsigned int irq)
245 +{
246 + /* Already done in brcm_irq_dispatch */
247 +}
248 +
249 +static unsigned int
250 +startup_brcm_irq(unsigned int irq)
251 +{
252 + enable_brcm_irq(irq);
253 +
254 + return 0; /* never anything pending */
255 +}
256 +
257 +static void
258 +end_brcm_irq(unsigned int irq)
259 +{
260 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
261 + enable_brcm_irq(irq);
262 +}
263 +
264 +static struct hw_interrupt_type brcm_irq_type = {
265 + typename: "MIPS",
266 + startup: startup_brcm_irq,
267 + shutdown: disable_brcm_irq,
268 + enable: enable_brcm_irq,
269 + disable: disable_brcm_irq,
270 + ack: ack_brcm_irq,
271 + end: end_brcm_irq,
272 + NULL
273 +};
274 +
275 +void __init
276 +init_IRQ(void)
277 +{
278 + int i;
279 +
280 + for (i = 0; i < NR_IRQS; i++) {
281 + irq_desc[i].status = IRQ_DISABLED;
282 + irq_desc[i].action = 0;
283 + irq_desc[i].depth = 1;
284 + irq_desc[i].handler = &brcm_irq_type;
285 + }
286 +
287 + set_except_vector(0, brcmIRQ);
288 + change_c0_status(ST0_IM, ALLINTS);
289 +
290 +#ifdef CONFIG_REMOTE_DEBUG
291 + printk("Breaking into debugger...\n");
292 + set_debug_traps();
293 + breakpoint();
294 +#endif
295 +}
296 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
297 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
298 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-11-07 23:58:34.968754500 +0100
299 @@ -0,0 +1,158 @@
300 +/*
301 + * GPIO char driver
302 + *
303 + * Copyright 2005, Broadcom Corporation
304 + * All Rights Reserved.
305 + *
306 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
307 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
308 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
309 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
310 + *
311 + * $Id$
312 + */
313 +
314 +#include <linux/module.h>
315 +#include <linux/init.h>
316 +#include <linux/fs.h>
317 +#include <linux/miscdevice.h>
318 +#include <asm/uaccess.h>
319 +
320 +#include <typedefs.h>
321 +#include <bcmutils.h>
322 +#include <sbutils.h>
323 +#include <bcmdevs.h>
324 +
325 +static sb_t *gpio_sbh;
326 +static int gpio_major;
327 +static devfs_handle_t gpio_dir;
328 +static struct {
329 + char *name;
330 + devfs_handle_t handle;
331 +} gpio_file[] = {
332 + { "in", NULL },
333 + { "out", NULL },
334 + { "outen", NULL },
335 + { "control", NULL }
336 +};
337 +
338 +static int
339 +gpio_open(struct inode *inode, struct file * file)
340 +{
341 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
342 + return -ENODEV;
343 +
344 + MOD_INC_USE_COUNT;
345 + return 0;
346 +}
347 +
348 +static int
349 +gpio_release(struct inode *inode, struct file * file)
350 +{
351 + MOD_DEC_USE_COUNT;
352 + return 0;
353 +}
354 +
355 +static ssize_t
356 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
357 +{
358 + u32 val;
359 +
360 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
361 + case 0:
362 + val = sb_gpioin(gpio_sbh);
363 + break;
364 + case 1:
365 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
366 + break;
367 + case 2:
368 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
369 + break;
370 + case 3:
371 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
372 + break;
373 + default:
374 + return -ENODEV;
375 + }
376 +
377 + if (put_user(val, (u32 *) buf))
378 + return -EFAULT;
379 +
380 + return sizeof(val);
381 +}
382 +
383 +static ssize_t
384 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
385 +{
386 + u32 val;
387 +
388 + if (get_user(val, (u32 *) buf))
389 + return -EFAULT;
390 +
391 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
392 + case 0:
393 + return -EACCES;
394 + case 1:
395 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
396 + break;
397 + case 2:
398 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
399 + break;
400 + case 3:
401 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
402 + break;
403 + default:
404 + return -ENODEV;
405 + }
406 +
407 + return sizeof(val);
408 +}
409 +
410 +static struct file_operations gpio_fops = {
411 + owner: THIS_MODULE,
412 + open: gpio_open,
413 + release: gpio_release,
414 + read: gpio_read,
415 + write: gpio_write,
416 +};
417 +
418 +static int __init
419 +gpio_init(void)
420 +{
421 + int i;
422 +
423 + if (!(gpio_sbh = sb_kattach()))
424 + return -ENODEV;
425 +
426 + sb_gpiosetcore(gpio_sbh);
427 +
428 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
429 + return gpio_major;
430 +
431 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
432 +
433 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
434 + gpio_file[i].handle = devfs_register(gpio_dir,
435 + gpio_file[i].name,
436 + DEVFS_FL_DEFAULT, gpio_major, i,
437 + S_IFCHR | S_IRUGO | S_IWUGO,
438 + &gpio_fops, NULL);
439 + }
440 +
441 + return 0;
442 +}
443 +
444 +static void __exit
445 +gpio_exit(void)
446 +{
447 + int i;
448 +
449 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
450 + devfs_unregister(gpio_file[i].handle);
451 + devfs_unregister(gpio_dir);
452 + devfs_unregister_chrdev(gpio_major, "gpio");
453 + sb_detach(gpio_sbh);
454 +}
455 +
456 +module_init(gpio_init);
457 +module_exit(gpio_exit);
458 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
459 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
460 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-11-07 22:51:38.772725750 +0100
461 @@ -0,0 +1,391 @@
462 +/*
463 + * Broadcom device-specific manifest constants.
464 + *
465 + * Copyright 2005, Broadcom Corporation
466 + * All Rights Reserved.
467 + *
468 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
469 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
470 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
471 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
472 + * $Id$
473 + */
474 +
475 +#ifndef _BCMDEVS_H
476 +#define _BCMDEVS_H
477 +
478 +
479 +/* Known PCI vendor Id's */
480 +#define VENDOR_EPIGRAM 0xfeda
481 +#define VENDOR_BROADCOM 0x14e4
482 +#define VENDOR_3COM 0x10b7
483 +#define VENDOR_NETGEAR 0x1385
484 +#define VENDOR_DIAMOND 0x1092
485 +#define VENDOR_DELL 0x1028
486 +#define VENDOR_HP 0x0e11
487 +#define VENDOR_APPLE 0x106b
488 +
489 +/* PCI Device Id's */
490 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
491 +#define BCM4211_DEVICE_ID 0x4211
492 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
493 +#define BCM4231_DEVICE_ID 0x4231
494 +
495 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
496 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
497 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
498 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
499 +
500 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
501 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
502 +
503 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
504 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
505 +
506 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
507 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
508 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
509 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
510 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
511 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
512 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
513 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
514 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
515 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
516 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
517 +
518 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
519 +
520 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
521 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
522 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
523 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
524 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
525 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
526 +
527 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
528 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
529 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
530 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
531 +
532 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
533 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
534 +
535 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
536 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
537 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
538 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
539 +
540 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
541 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
542 +#define BCM4306_D11G_ID2 0x4325
543 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
544 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
545 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
546 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
547 +
548 +#define BCM4309_PKG_ID 1 /* 4309 package id */
549 +
550 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
551 +#define BCM4303_PKG_ID 2 /* 4303 package id */
552 +
553 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
554 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
555 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
556 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
557 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
558 +
559 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
560 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
561 +
562 +
563 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
564 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
565 +
566 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
567 +
568 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
569 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
570 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
571 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
572 +
573 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
574 +
575 +/* Address map */
576 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
577 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
578 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
579 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
580 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
581 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
582 +
583 +/* Core register space */
584 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
585 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
586 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
587 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
588 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
589 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
590 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
591 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
592 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
593 +
594 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
595 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
596 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
597 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
598 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
599 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
600 +
601 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
602 +
603 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
604 +
605 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
606 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
607 +
608 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
609 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
610 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
611 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
612 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
613 +
614 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
615 +
616 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
617 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
618 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
619 +
620 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
621 +
622 +/* PCMCIA vendor Id's */
623 +
624 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
625 +
626 +/* SDIO vendor Id's */
627 +#define VENDOR_BROADCOM_SDIO 0x00BF
628 +
629 +
630 +/* boardflags */
631 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
632 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
633 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
634 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
635 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
636 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
637 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
638 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
639 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
640 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
641 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
642 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
643 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
644 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
645 +
646 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
647 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
648 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
649 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
650 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
651 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
652 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
653 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
654 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
655 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
656 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
657 +
658 +/* Bus types */
659 +#define SB_BUS 0 /* Silicon Backplane */
660 +#define PCI_BUS 1 /* PCI target */
661 +#define PCMCIA_BUS 2 /* PCMCIA target */
662 +#define SDIO_BUS 3 /* SDIO target */
663 +#define JTAG_BUS 4 /* JTAG */
664 +
665 +/* Allows optimization for single-bus support */
666 +#ifdef BCMBUSTYPE
667 +#define BUSTYPE(bus) (BCMBUSTYPE)
668 +#else
669 +#define BUSTYPE(bus) (bus)
670 +#endif
671 +
672 +/* power control defines */
673 +#define PLL_DELAY 150 /* us pll on delay */
674 +#define FREF_DELAY 200 /* us fref change delay */
675 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
676 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
677 +
678 +/* Reference Board Types */
679 +
680 +#define BU4710_BOARD 0x0400
681 +#define VSIM4710_BOARD 0x0401
682 +#define QT4710_BOARD 0x0402
683 +
684 +#define BU4610_BOARD 0x0403
685 +#define VSIM4610_BOARD 0x0404
686 +
687 +#define BU4307_BOARD 0x0405
688 +#define BCM94301CB_BOARD 0x0406
689 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
690 +#define BCM94301MP_BOARD 0x0407
691 +#define BCM94307MP_BOARD 0x0408
692 +#define BCMAP4307_BOARD 0x0409
693 +
694 +#define BU4309_BOARD 0x040a
695 +#define BCM94309CB_BOARD 0x040b
696 +#define BCM94309MP_BOARD 0x040c
697 +#define BCM4309AP_BOARD 0x040d
698 +
699 +#define BCM94302MP_BOARD 0x040e
700 +
701 +#define VSIM4310_BOARD 0x040f
702 +#define BU4711_BOARD 0x0410
703 +#define BCM94310U_BOARD 0x0411
704 +#define BCM94310AP_BOARD 0x0412
705 +#define BCM94310MP_BOARD 0x0414
706 +
707 +#define BU4306_BOARD 0x0416
708 +#define BCM94306CB_BOARD 0x0417
709 +#define BCM94306MP_BOARD 0x0418
710 +
711 +#define BCM94710D_BOARD 0x041a
712 +#define BCM94710R1_BOARD 0x041b
713 +#define BCM94710R4_BOARD 0x041c
714 +#define BCM94710AP_BOARD 0x041d
715 +
716 +
717 +#define BU2050_BOARD 0x041f
718 +
719 +
720 +#define BCM94309G_BOARD 0x0421
721 +
722 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
723 +
724 +#define BU4704_BOARD 0x0423
725 +#define BU4702_BOARD 0x0424
726 +
727 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
728 +
729 +#define BU4317_BOARD 0x0426
730 +
731 +
732 +#define BCM94702MN_BOARD 0x0428
733 +
734 +/* BCM4702 1U CompactPCI Board */
735 +#define BCM94702CPCI_BOARD 0x0429
736 +
737 +/* BCM4702 with BCM95380 VLAN Router */
738 +#define BCM95380RR_BOARD 0x042a
739 +
740 +/* cb4306 with SiGe PA */
741 +#define BCM94306CBSG_BOARD 0x042b
742 +
743 +/* mp4301 with 2050 radio */
744 +#define BCM94301MPL_BOARD 0x042c
745 +
746 +/* cb4306 with SiGe PA */
747 +#define PCSG94306_BOARD 0x042d
748 +
749 +/* bu4704 with sdram */
750 +#define BU4704SD_BOARD 0x042e
751 +
752 +/* Dual 11a/11g Router */
753 +#define BCM94704AGR_BOARD 0x042f
754 +
755 +/* 11a-only minipci */
756 +#define BCM94308MP_BOARD 0x0430
757 +
758 +
759 +
760 +/* BCM94317 boards */
761 +#define BCM94317CB_BOARD 0x0440
762 +#define BCM94317MP_BOARD 0x0441
763 +#define BCM94317PCMCIA_BOARD 0x0442
764 +#define BCM94317SDIO_BOARD 0x0443
765 +
766 +#define BU4712_BOARD 0x0444
767 +#define BU4712SD_BOARD 0x045d
768 +#define BU4712L_BOARD 0x045f
769 +
770 +/* BCM4712 boards */
771 +#define BCM94712AP_BOARD 0x0445
772 +#define BCM94712P_BOARD 0x0446
773 +
774 +/* BCM4318 boards */
775 +#define BU4318_BOARD 0x0447
776 +#define CB4318_BOARD 0x0448
777 +#define MPG4318_BOARD 0x0449
778 +#define MP4318_BOARD 0x044a
779 +#define SD4318_BOARD 0x044b
780 +
781 +/* BCM63XX boards */
782 +#define BCM96338_BOARD 0x6338
783 +#define BCM96345_BOARD 0x6345
784 +#define BCM96348_BOARD 0x6348
785 +
786 +/* Another mp4306 with SiGe */
787 +#define BCM94306P_BOARD 0x044c
788 +
789 +/* CF-like 4317 modules */
790 +#define BCM94317CF_BOARD 0x044d
791 +
792 +/* mp4303 */
793 +#define BCM94303MP_BOARD 0x044e
794 +
795 +/* mpsgh4306 */
796 +#define BCM94306MPSGH_BOARD 0x044f
797 +
798 +/* BRCM 4306 w/ Front End Modules */
799 +#define BCM94306MPM 0x0450
800 +#define BCM94306MPL 0x0453
801 +
802 +/* 4712agr */
803 +#define BCM94712AGR_BOARD 0x0451
804 +
805 +/* The real CF 4317 board */
806 +#define CFI4317_BOARD 0x0452
807 +
808 +/* pcmcia 4303 */
809 +#define PC4303_BOARD 0x0454
810 +
811 +/* 5350K */
812 +#define BCM95350K_BOARD 0x0455
813 +
814 +/* 5350R */
815 +#define BCM95350R_BOARD 0x0456
816 +
817 +/* 4306mplna */
818 +#define BCM94306MPLNA_BOARD 0x0457
819 +
820 +/* 4320 boards */
821 +#define BU4320_BOARD 0x0458
822 +#define BU4320S_BOARD 0x0459
823 +#define BCM94320PH_BOARD 0x045a
824 +
825 +/* 4306mph */
826 +#define BCM94306MPH_BOARD 0x045b
827 +
828 +/* 4306pciv */
829 +#define BCM94306PCIV_BOARD 0x045c
830 +
831 +#define BU4712SD_BOARD 0x045d
832 +
833 +#define BCM94320PFLSH_BOARD 0x045e
834 +
835 +#define BU4712L_BOARD 0x045f
836 +#define BCM94712LGR_BOARD 0x0460
837 +#define BCM94320R_BOARD 0x0461
838 +
839 +#define BU5352_BOARD 0x0462
840 +
841 +#define BCM94318MPGH_BOARD 0x0463
842 +
843 +
844 +#define BCM95352GR_BOARD 0x0467
845 +
846 +/* bcm95351agr */
847 +#define BCM95351AGR_BOARD 0x0470
848 +
849 +/* # of GPIO pins */
850 +#define GPIO_NUMPINS 16
851 +
852 +#endif /* _BCMDEVS_H */
853 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
854 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
855 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-11-07 22:51:38.772725750 +0100
856 @@ -0,0 +1,152 @@
857 +/*
858 + * local version of endian.h - byte order defines
859 + *
860 + * Copyright 2005, Broadcom Corporation
861 + * All Rights Reserved.
862 + *
863 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
864 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
865 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
866 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
867 + *
868 + * $Id$
869 +*/
870 +
871 +#ifndef _BCMENDIAN_H_
872 +#define _BCMENDIAN_H_
873 +
874 +#include <typedefs.h>
875 +
876 +/* Byte swap a 16 bit value */
877 +#define BCMSWAP16(val) \
878 + ((uint16)( \
879 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
880 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
881 +
882 +/* Byte swap a 32 bit value */
883 +#define BCMSWAP32(val) \
884 + ((uint32)( \
885 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
886 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
887 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
888 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
889 +
890 +/* 2 Byte swap a 32 bit value */
891 +#define BCMSWAP32BY16(val) \
892 + ((uint32)( \
893 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
894 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
895 +
896 +
897 +static INLINE uint16
898 +bcmswap16(uint16 val)
899 +{
900 + return BCMSWAP16(val);
901 +}
902 +
903 +static INLINE uint32
904 +bcmswap32(uint32 val)
905 +{
906 + return BCMSWAP32(val);
907 +}
908 +
909 +static INLINE uint32
910 +bcmswap32by16(uint32 val)
911 +{
912 + return BCMSWAP32BY16(val);
913 +}
914 +
915 +/* buf - start of buffer of shorts to swap */
916 +/* len - byte length of buffer */
917 +static INLINE void
918 +bcmswap16_buf(uint16 *buf, uint len)
919 +{
920 + len = len/2;
921 +
922 + while(len--){
923 + *buf = bcmswap16(*buf);
924 + buf++;
925 + }
926 +}
927 +
928 +#ifndef hton16
929 +#ifndef IL_BIGENDIAN
930 +#define HTON16(i) BCMSWAP16(i)
931 +#define hton16(i) bcmswap16(i)
932 +#define hton32(i) bcmswap32(i)
933 +#define ntoh16(i) bcmswap16(i)
934 +#define ntoh32(i) bcmswap32(i)
935 +#define ltoh16(i) (i)
936 +#define ltoh32(i) (i)
937 +#define htol16(i) (i)
938 +#define htol32(i) (i)
939 +#else
940 +#define HTON16(i) (i)
941 +#define hton16(i) (i)
942 +#define hton32(i) (i)
943 +#define ntoh16(i) (i)
944 +#define ntoh32(i) (i)
945 +#define ltoh16(i) bcmswap16(i)
946 +#define ltoh32(i) bcmswap32(i)
947 +#define htol16(i) bcmswap16(i)
948 +#define htol32(i) bcmswap32(i)
949 +#endif
950 +#endif
951 +
952 +#ifndef IL_BIGENDIAN
953 +#define ltoh16_buf(buf, i)
954 +#define htol16_buf(buf, i)
955 +#else
956 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
957 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
958 +#endif
959 +
960 +/*
961 +* load 16-bit value from unaligned little endian byte array.
962 +*/
963 +static INLINE uint16
964 +ltoh16_ua(uint8 *bytes)
965 +{
966 + return (bytes[1]<<8)+bytes[0];
967 +}
968 +
969 +/*
970 +* load 32-bit value from unaligned little endian byte array.
971 +*/
972 +static INLINE uint32
973 +ltoh32_ua(uint8 *bytes)
974 +{
975 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
976 +}
977 +
978 +/*
979 +* load 16-bit value from unaligned big(network) endian byte array.
980 +*/
981 +static INLINE uint16
982 +ntoh16_ua(uint8 *bytes)
983 +{
984 + return (bytes[0]<<8)+bytes[1];
985 +}
986 +
987 +/*
988 +* load 32-bit value from unaligned big(network) endian byte array.
989 +*/
990 +static INLINE uint32
991 +ntoh32_ua(uint8 *bytes)
992 +{
993 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
994 +}
995 +
996 +#define ltoh_ua(ptr) ( \
997 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
998 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
999 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1000 +)
1001 +
1002 +#define ntoh_ua(ptr) ( \
1003 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1004 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1005 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1006 +)
1007 +
1008 +#endif /* _BCMENDIAN_H_ */
1009 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
1010 --- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1011 +++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-11-07 22:51:38.772725750 +0100
1012 @@ -0,0 +1,229 @@
1013 +/*
1014 + * Hardware-specific definitions for
1015 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1016 + *
1017 + * Copyright 2005, Broadcom Corporation
1018 + * All Rights Reserved.
1019 + *
1020 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1021 + * the contents of this file may not be disclosed to third parties, copied
1022 + * or duplicated in any form, in whole or in part, without the prior
1023 + * written permission of Broadcom Corporation.
1024 + * $Id$
1025 + */
1026 +
1027 +#ifndef _bcmenet_47xx_h_
1028 +#define _bcmenet_47xx_h_
1029 +
1030 +#include <bcmenetmib.h>
1031 +#include <bcmenetrxh.h>
1032 +#include <bcmenetphy.h>
1033 +
1034 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1035 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1036 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1037 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1038 +
1039 +/* power management event wakeup pattern constants */
1040 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1041 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1042 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1043 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1044 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1045 +
1046 +/* cpp contortions to concatenate w/arg prescan */
1047 +#ifndef PAD
1048 +#define _PADLINE(line) pad ## line
1049 +#define _XSTR(line) _PADLINE(line)
1050 +#define PAD _XSTR(__LINE__)
1051 +#endif /* PAD */
1052 +
1053 +/*
1054 + * Host Interface Registers
1055 + */
1056 +typedef volatile struct _bcmenettregs {
1057 + /* Device and Power Control */
1058 + uint32 devcontrol;
1059 + uint32 PAD[2];
1060 + uint32 biststatus;
1061 + uint32 wakeuplength;
1062 + uint32 PAD[3];
1063 +
1064 + /* Interrupt Control */
1065 + uint32 intstatus;
1066 + uint32 intmask;
1067 + uint32 gptimer;
1068 + uint32 PAD[23];
1069 +
1070 + /* Ethernet MAC Address Filtering Control */
1071 + uint32 PAD[2];
1072 + uint32 enetftaddr;
1073 + uint32 enetftdata;
1074 + uint32 PAD[2];
1075 +
1076 + /* Ethernet MAC Control */
1077 + uint32 emactxmaxburstlen;
1078 + uint32 emacrxmaxburstlen;
1079 + uint32 emaccontrol;
1080 + uint32 emacflowcontrol;
1081 +
1082 + uint32 PAD[20];
1083 +
1084 + /* DMA Lazy Interrupt Control */
1085 + uint32 intrecvlazy;
1086 + uint32 PAD[63];
1087 +
1088 + /* DMA engine */
1089 + dma32regp_t dmaregs;
1090 + dma32diag_t dmafifo;
1091 + uint32 PAD[116];
1092 +
1093 + /* EMAC Registers */
1094 + uint32 rxconfig;
1095 + uint32 rxmaxlength;
1096 + uint32 txmaxlength;
1097 + uint32 PAD;
1098 + uint32 mdiocontrol;
1099 + uint32 mdiodata;
1100 + uint32 emacintmask;
1101 + uint32 emacintstatus;
1102 + uint32 camdatalo;
1103 + uint32 camdatahi;
1104 + uint32 camcontrol;
1105 + uint32 enetcontrol;
1106 + uint32 txcontrol;
1107 + uint32 txwatermark;
1108 + uint32 mibcontrol;
1109 + uint32 PAD[49];
1110 +
1111 + /* EMAC MIB counters */
1112 + bcmenetmib_t mib;
1113 +
1114 + uint32 PAD[585];
1115 +
1116 + /* Sonics SiliconBackplane config registers */
1117 + sbconfig_t sbconfig;
1118 +} bcmenetregs_t;
1119 +
1120 +/* device control */
1121 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1122 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1123 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1124 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1125 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1126 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1127 +#define DC_PA_SHIFT 18
1128 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1129 +#define DC_FS_SHIFT 23
1130 +#define DC_FS_4K 0 /* 4Kbytes */
1131 +#define DC_FS_512 1 /* 512bytes */
1132 +
1133 +/* wakeup length */
1134 +#define WL_P0_MASK 0x7f /* pattern 0 */
1135 +#define WL_D0 ((uint32)1 << 7)
1136 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1137 +#define WL_P1_SHIFT 8
1138 +#define WL_D1 ((uint32)1 << 15)
1139 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1140 +#define WL_P2_SHIFT 16
1141 +#define WL_D2 ((uint32)1 << 23)
1142 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1143 +#define WL_P3_SHIFT 24
1144 +#define WL_D3 ((uint32)1 << 31)
1145 +
1146 +/* intstatus and intmask */
1147 +#define I_PME ((uint32)1 << 6) /* power management event */
1148 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1149 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1150 +#define I_PD ((uint32)1 << 11) /* data error */
1151 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1152 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1153 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1154 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1155 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1156 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1157 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1158 +#define I_MW ((uint32)1 << 27) /* mii write */
1159 +#define I_MR ((uint32)1 << 28) /* mii read */
1160 +
1161 +/* emaccontrol */
1162 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1163 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1164 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1165 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1166 +#define EMC_LC_SHIFT 5
1167 +
1168 +/* emacflowcontrol */
1169 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1170 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1171 +
1172 +/* interrupt receive lazy */
1173 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1174 +#define IRL_FC_MASK 0xff000000 /* frame count */
1175 +#define IRL_FC_SHIFT 24 /* frame count */
1176 +
1177 +/* emac receive config */
1178 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1179 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1180 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1181 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1182 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1183 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1184 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1185 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1186 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1187 +
1188 +/* emac mdio control */
1189 +#define MC_MF_MASK 0x7f /* mdc frequency */
1190 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1191 +
1192 +/* emac mdio data */
1193 +#define MD_DATA_MASK 0xffff /* r/w data */
1194 +#define MD_TA_MASK 0x30000 /* turnaround value */
1195 +#define MD_TA_SHIFT 16
1196 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1197 +#define MD_RA_MASK 0x7c0000 /* register address */
1198 +#define MD_RA_SHIFT 18
1199 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1200 +#define MD_PMD_SHIFT 23
1201 +#define MD_OP_MASK 0x30000000 /* opcode */
1202 +#define MD_OP_SHIFT 28
1203 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1204 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1205 +#define MD_SB_MASK 0xc0000000 /* start bits */
1206 +#define MD_SB_SHIFT 30
1207 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1208 +
1209 +/* emac intstatus and intmask */
1210 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1211 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1212 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1213 +
1214 +/* emac cam data high */
1215 +#define CD_V ((uint32)1 << 16) /* valid bit */
1216 +
1217 +/* emac cam control */
1218 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1219 +#define CC_MS ((uint32)1 << 1) /* mask select */
1220 +#define CC_RD ((uint32)1 << 2) /* read */
1221 +#define CC_WR ((uint32)1 << 3) /* write */
1222 +#define CC_INDEX_MASK 0x3f0000 /* index */
1223 +#define CC_INDEX_SHIFT 16
1224 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1225 +
1226 +/* emac ethernet control */
1227 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1228 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1229 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1230 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1231 +
1232 +/* emac transmit control */
1233 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1234 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1235 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1236 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1237 +
1238 +/* emac mib control */
1239 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1240 +
1241 +#endif /* _bcmenet_47xx_h_ */
1242 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
1243 --- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1244 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-11-07 21:57:07.845585750 +0100
1245 @@ -0,0 +1,81 @@
1246 +/*
1247 + * Hardware-specific MIB definition for
1248 + * Broadcom Home Networking Division
1249 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1250 + *
1251 + * Copyright 2005, Broadcom Corporation
1252 + * All Rights Reserved.
1253 + *
1254 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1255 + * the contents of this file may not be disclosed to third parties, copied
1256 + * or duplicated in any form, in whole or in part, without the prior
1257 + * written permission of Broadcom Corporation.
1258 + * $Id$
1259 + */
1260 +
1261 +#ifndef _bcmenetmib_h_
1262 +#define _bcmenetmib_h_
1263 +
1264 +/* cpp contortions to concatenate w/arg prescan */
1265 +#ifndef PAD
1266 +#define _PADLINE(line) pad ## line
1267 +#define _XSTR(line) _PADLINE(line)
1268 +#define PAD _XSTR(__LINE__)
1269 +#endif /* PAD */
1270 +
1271 +/*
1272 + * EMAC MIB Registers
1273 + */
1274 +typedef volatile struct {
1275 + uint32 tx_good_octets;
1276 + uint32 tx_good_pkts;
1277 + uint32 tx_octets;
1278 + uint32 tx_pkts;
1279 + uint32 tx_broadcast_pkts;
1280 + uint32 tx_multicast_pkts;
1281 + uint32 tx_len_64;
1282 + uint32 tx_len_65_to_127;
1283 + uint32 tx_len_128_to_255;
1284 + uint32 tx_len_256_to_511;
1285 + uint32 tx_len_512_to_1023;
1286 + uint32 tx_len_1024_to_max;
1287 + uint32 tx_jabber_pkts;
1288 + uint32 tx_oversize_pkts;
1289 + uint32 tx_fragment_pkts;
1290 + uint32 tx_underruns;
1291 + uint32 tx_total_cols;
1292 + uint32 tx_single_cols;
1293 + uint32 tx_multiple_cols;
1294 + uint32 tx_excessive_cols;
1295 + uint32 tx_late_cols;
1296 + uint32 tx_defered;
1297 + uint32 tx_carrier_lost;
1298 + uint32 tx_pause_pkts;
1299 + uint32 PAD[8];
1300 +
1301 + uint32 rx_good_octets;
1302 + uint32 rx_good_pkts;
1303 + uint32 rx_octets;
1304 + uint32 rx_pkts;
1305 + uint32 rx_broadcast_pkts;
1306 + uint32 rx_multicast_pkts;
1307 + uint32 rx_len_64;
1308 + uint32 rx_len_65_to_127;
1309 + uint32 rx_len_128_to_255;
1310 + uint32 rx_len_256_to_511;
1311 + uint32 rx_len_512_to_1023;
1312 + uint32 rx_len_1024_to_max;
1313 + uint32 rx_jabber_pkts;
1314 + uint32 rx_oversize_pkts;
1315 + uint32 rx_fragment_pkts;
1316 + uint32 rx_missed_pkts;
1317 + uint32 rx_crc_align_errs;
1318 + uint32 rx_undersize;
1319 + uint32 rx_crc_errs;
1320 + uint32 rx_align_errs;
1321 + uint32 rx_symbol_errs;
1322 + uint32 rx_pause_pkts;
1323 + uint32 rx_nonpause_pkts;
1324 +} bcmenetmib_t;
1325 +
1326 +#endif /* _bcmenetmib_h_ */
1327 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
1328 --- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1329 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-11-07 21:57:07.845585750 +0100
1330 @@ -0,0 +1,58 @@
1331 +/*
1332 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1333 + *
1334 + * Copyright 2005, Broadcom Corporation
1335 + * All Rights Reserved.
1336 + *
1337 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1338 + * the contents of this file may not be disclosed to third parties, copied
1339 + * or duplicated in any form, in whole or in part, without the prior
1340 + * written permission of Broadcom Corporation.
1341 + * $Id$
1342 + */
1343 +
1344 +#ifndef _bcmenetphy_h_
1345 +#define _bcmenetphy_h_
1346 +
1347 +/* phy address */
1348 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1349 +#define EPHY_MASK 0x1f
1350 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1351 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1352 +
1353 +/* just a few phy registers */
1354 +#define CTL_RESET (1 << 15) /* reset */
1355 +#define CTL_LOOP (1 << 14) /* loopback */
1356 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1357 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1358 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1359 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1360 +
1361 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1362 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1363 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1364 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1365 +
1366 +/* link partner ability register */
1367 +#define LPA_SLCT 0x001f /* same as advertise selector */
1368 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1369 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1370 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1371 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1372 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1373 +#define LPA_RESV 0x1c00 /* unused */
1374 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1375 +#define LPA_LPACK 0x4000 /* link partner acked us */
1376 +#define LPA_NPAGE 0x8000 /* next page bit */
1377 +
1378 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1379 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1380 +
1381 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1382 +#define STAT_LINK (1 << 2) /* link status */
1383 +#define STAT_JAB (1 << 1) /* jabber detected */
1384 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1385 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1386 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1387 +
1388 +#endif /* _bcmenetphy_h_ */
1389 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
1390 --- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1391 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-11-07 21:57:07.845585750 +0100
1392 @@ -0,0 +1,43 @@
1393 +/*
1394 + * Hardware-specific Receive Data Header for the
1395 + * Broadcom Home Networking Division
1396 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1397 + *
1398 + * Copyright 2005, Broadcom Corporation
1399 + * All Rights Reserved.
1400 + *
1401 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1402 + * the contents of this file may not be disclosed to third parties, copied
1403 + * or duplicated in any form, in whole or in part, without the prior
1404 + * written permission of Broadcom Corporation.
1405 + * $Id$
1406 + */
1407 +
1408 +#ifndef _bcmenetrxh_h_
1409 +#define _bcmenetrxh_h_
1410 +
1411 +/*
1412 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1413 + * with every frame consisting of
1414 + * 16bits of frame length, followed by
1415 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1416 + */
1417 +typedef volatile struct {
1418 + uint16 len;
1419 + uint16 flags;
1420 + uint16 pad[12];
1421 +} bcmenetrxh_t;
1422 +
1423 +#define RXHDR_LEN 28
1424 +
1425 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1426 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1427 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1428 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1429 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1430 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1431 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1432 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1433 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1434 +
1435 +#endif /* _bcmenetrxh_h_ */
1436 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1437 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1438 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-11-07 22:51:38.772725750 +0100
1439 @@ -0,0 +1,141 @@
1440 +/*
1441 + * NVRAM variable manipulation
1442 + *
1443 + * Copyright 2005, Broadcom Corporation
1444 + * All Rights Reserved.
1445 + *
1446 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1447 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1448 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1449 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1450 + *
1451 + * $Id$
1452 + */
1453 +
1454 +#ifndef _bcmnvram_h_
1455 +#define _bcmnvram_h_
1456 +
1457 +#ifndef _LANGUAGE_ASSEMBLY
1458 +
1459 +#include <typedefs.h>
1460 +
1461 +struct nvram_header {
1462 + uint32 magic;
1463 + uint32 len;
1464 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1465 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1466 + uint32 config_ncdl; /* ncdl values for memc */
1467 +};
1468 +
1469 +struct nvram_tuple {
1470 + char *name;
1471 + char *value;
1472 + struct nvram_tuple *next;
1473 +};
1474 +
1475 +/*
1476 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1477 + * platforms.
1478 + */
1479 +extern int BCMINIT(nvram_init)(void *sbh);
1480 +
1481 +/*
1482 + * Disable NVRAM access. May be unnecessary or undefined on certain
1483 + * platforms.
1484 + */
1485 +extern void BCMINIT(nvram_exit)(void *sbh);
1486 +
1487 +/*
1488 + * Get the value of an NVRAM variable. The pointer returned may be
1489 + * invalid after a set.
1490 + * @param name name of variable to get
1491 + * @return value of variable or NULL if undefined
1492 + */
1493 +extern char * BCMINIT(nvram_get)(const char *name);
1494 +
1495 +/*
1496 + * Read the reset GPIO value from the nvram and set the GPIO
1497 + * as input
1498 + */
1499 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1500 +
1501 +/*
1502 + * Get the value of an NVRAM variable.
1503 + * @param name name of variable to get
1504 + * @return value of variable or NUL if undefined
1505 + */
1506 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1507 +
1508 +/*
1509 + * Match an NVRAM variable.
1510 + * @param name name of variable to match
1511 + * @param match value to compare against value of variable
1512 + * @return TRUE if variable is defined and its value is string equal
1513 + * to match or FALSE otherwise
1514 + */
1515 +static INLINE int
1516 +nvram_match(char *name, char *match) {
1517 + const char *value = BCMINIT(nvram_get)(name);
1518 + return (value && !strcmp(value, match));
1519 +}
1520 +
1521 +/*
1522 + * Inversely match an NVRAM variable.
1523 + * @param name name of variable to match
1524 + * @param match value to compare against value of variable
1525 + * @return TRUE if variable is defined and its value is not string
1526 + * equal to invmatch or FALSE otherwise
1527 + */
1528 +static INLINE int
1529 +nvram_invmatch(char *name, char *invmatch) {
1530 + const char *value = BCMINIT(nvram_get)(name);
1531 + return (value && strcmp(value, invmatch));
1532 +}
1533 +
1534 +/*
1535 + * Set the value of an NVRAM variable. The name and value strings are
1536 + * copied into private storage. Pointers to previously set values
1537 + * may become invalid. The new value may be immediately
1538 + * retrieved but will not be permanently stored until a commit.
1539 + * @param name name of variable to set
1540 + * @param value value of variable
1541 + * @return 0 on success and errno on failure
1542 + */
1543 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1544 +
1545 +/*
1546 + * Unset an NVRAM variable. Pointers to previously set values
1547 + * remain valid until a set.
1548 + * @param name name of variable to unset
1549 + * @return 0 on success and errno on failure
1550 + * NOTE: use nvram_commit to commit this change to flash.
1551 + */
1552 +extern int BCMINIT(nvram_unset)(const char *name);
1553 +
1554 +/*
1555 + * Commit NVRAM variables to permanent storage. All pointers to values
1556 + * may be invalid after a commit.
1557 + * NVRAM values are undefined after a commit.
1558 + * @return 0 on success and errno on failure
1559 + */
1560 +extern int BCMINIT(nvram_commit)(void);
1561 +
1562 +/*
1563 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1564 + * @param buf buffer to store variables
1565 + * @param count size of buffer in bytes
1566 + * @return 0 on success and errno on failure
1567 + */
1568 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1569 +
1570 +#endif /* _LANGUAGE_ASSEMBLY */
1571 +
1572 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1573 +#define NVRAM_VERSION 1
1574 +#define NVRAM_HEADER_SIZE 20
1575 +#define NVRAM_SPACE 0x8000
1576 +
1577 +#define NVRAM_MAX_VALUE_LEN 255
1578 +#define NVRAM_MAX_PARAM_LEN 64
1579 +
1580 +#endif /* _bcmnvram_h_ */
1581 diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
1582 --- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1583 +++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-11-07 22:51:38.776726000 +0100
1584 @@ -0,0 +1,25 @@
1585 +/*
1586 + * Misc system wide parameters.
1587 + *
1588 + * Copyright 2005, Broadcom Corporation
1589 + * All Rights Reserved.
1590 + *
1591 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1592 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1593 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1594 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1595 + * $Id$
1596 + */
1597 +
1598 +#ifndef _bcmparams_h_
1599 +#define _bcmparams_h_
1600 +
1601 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1602 +
1603 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1604 +
1605 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1606 +
1607 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1608 +
1609 +#endif
1610 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1611 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1612 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-11-07 22:51:38.776726000 +0100
1613 @@ -0,0 +1,23 @@
1614 +/*
1615 + * Misc useful routines to access NIC local SROM/OTP .
1616 + *
1617 + * Copyright 2005, Broadcom Corporation
1618 + * All Rights Reserved.
1619 + *
1620 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1621 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1622 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1623 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1624 + *
1625 + * $Id$
1626 + */
1627 +
1628 +#ifndef _bcmsrom_h_
1629 +#define _bcmsrom_h_
1630 +
1631 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1632 +
1633 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1634 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1635 +
1636 +#endif /* _bcmsrom_h_ */
1637 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1638 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1639 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-11-07 22:51:38.776726000 +0100
1640 @@ -0,0 +1,313 @@
1641 +/*
1642 + * Misc useful os-independent macros and functions.
1643 + *
1644 + * Copyright 2005, Broadcom Corporation
1645 + * All Rights Reserved.
1646 + *
1647 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1648 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1649 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1650 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1651 + * $Id$
1652 + */
1653 +
1654 +#ifndef _bcmutils_h_
1655 +#define _bcmutils_h_
1656 +
1657 +/*** driver-only section ***/
1658 +#ifdef BCMDRIVER
1659 +#include <osl.h>
1660 +
1661 +#define _BCM_U 0x01 /* upper */
1662 +#define _BCM_L 0x02 /* lower */
1663 +#define _BCM_D 0x04 /* digit */
1664 +#define _BCM_C 0x08 /* cntrl */
1665 +#define _BCM_P 0x10 /* punct */
1666 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1667 +#define _BCM_X 0x40 /* hex digit */
1668 +#define _BCM_SP 0x80 /* hard space (0x20) */
1669 +
1670 +#define GPIO_PIN_NOTDEFINED 0x20
1671 +
1672 +extern unsigned char bcm_ctype[];
1673 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1674 +
1675 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1676 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1677 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1678 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1679 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1680 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1681 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1682 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1683 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1684 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1685 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1686 +
1687 +/*
1688 + * Spin at most 'us' microseconds while 'exp' is true.
1689 + * Caller should explicitly test 'exp' when this completes
1690 + * and take appropriate error action if 'exp' is still true.
1691 + */
1692 +#define SPINWAIT(exp, us) { \
1693 + uint countdown = (us) + 9; \
1694 + while ((exp) && (countdown >= 10)) {\
1695 + OSL_DELAY(10); \
1696 + countdown -= 10; \
1697 + } \
1698 +}
1699 +
1700 +/* generic osl packet queue */
1701 +struct pktq {
1702 + void *head; /* first packet to dequeue */
1703 + void *tail; /* last packet to dequeue */
1704 + uint len; /* number of queued packets */
1705 + uint maxlen; /* maximum number of queued packets */
1706 + bool priority; /* enqueue by packet priority */
1707 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1708 +};
1709 +#define DEFAULT_QLEN 128
1710 +
1711 +#define pktq_len(q) ((q)->len)
1712 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1713 +#define pktq_head(q) ((q)->head)
1714 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1715 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1716 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1717 +
1718 +/* externs */
1719 +/* packet */
1720 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1721 +extern uint pkttotlen(osl_t *osh, void *);
1722 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1723 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1724 +extern void *pktdeq(struct pktq *q);
1725 +extern void *pktdeqtail(struct pktq *q);
1726 +/* string */
1727 +extern uint bcm_atoi(char *s);
1728 +extern uchar bcm_toupper(uchar c);
1729 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1730 +extern char *bcmstrstr(char *haystack, char *needle);
1731 +extern char *bcmstrcat(char *dest, const char *src);
1732 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1733 +/* ethernet address */
1734 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1735 +extern int bcm_ether_atoe(char *p, char *ea);
1736 +/* delay */
1737 +extern void bcm_mdelay(uint ms);
1738 +/* variable access */
1739 +extern char *getvar(char *vars, char *name);
1740 +extern int getintvar(char *vars, char *name);
1741 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1742 +#define bcmlog(fmt, a1, a2)
1743 +#define bcmdumplog(buf, size) *buf = '\0'
1744 +#define bcmdumplogent(buf, idx) -1
1745 +
1746 +#endif /* #ifdef BCMDRIVER */
1747 +
1748 +/*** driver/apps-shared section ***/
1749 +
1750 +#define BCME_STRLEN 64
1751 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1752 +
1753 +
1754 +/*
1755 + * error codes could be added but the defined ones shouldn't be changed/deleted
1756 + * these error codes are exposed to the user code
1757 + * when ever a new error code is added to this list
1758 + * please update errorstring table with the related error string and
1759 + * update osl files with os specific errorcode map
1760 +*/
1761 +
1762 +#define BCME_ERROR -1 /* Error generic */
1763 +#define BCME_BADARG -2 /* Bad Argument */
1764 +#define BCME_BADOPTION -3 /* Bad option */
1765 +#define BCME_NOTUP -4 /* Not up */
1766 +#define BCME_NOTDOWN -5 /* Not down */
1767 +#define BCME_NOTAP -6 /* Not AP */
1768 +#define BCME_NOTSTA -7 /* Not STA */
1769 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1770 +#define BCME_RADIOOFF -9 /* Radio Off */
1771 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1772 +#define BCME_NOCLK -11 /* No Clock*/
1773 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1774 +#define BCME_BADBAND -13 /* BAD Band */
1775 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1776 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1777 +#define BCME_BUSY -16 /* Busy*/
1778 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1779 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1780 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1781 +#define BCME_BADCHAN -20 /* BAD Channel */
1782 +#define BCME_BADADDR -21 /* BAD Address*/
1783 +#define BCME_NORESOURCE -22 /* No resources*/
1784 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1785 +#define BCME_BADLEN -24 /* Bad Length*/
1786 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1787 +#define BCME_EPERM -26 /* Not Permitted */
1788 +#define BCME_NOMEM -27 /* No Memory */
1789 +#define BCME_ASSOCIATED -28 /* Associated */
1790 +#define BCME_RANGE -29 /* Range Error*/
1791 +#define BCME_NOTFOUND -30 /* Not found */
1792 +#define BCME_LAST BCME_NOTFOUND
1793 +
1794 +#ifndef ABS
1795 +#define ABS(a) (((a)<0)?-(a):(a))
1796 +#endif
1797 +
1798 +#ifndef MIN
1799 +#define MIN(a, b) (((a)<(b))?(a):(b))
1800 +#endif
1801 +
1802 +#ifndef MAX
1803 +#define MAX(a, b) (((a)>(b))?(a):(b))
1804 +#endif
1805 +
1806 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1807 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1808 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1809 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1810 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1811 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1812 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1813 +
1814 +/* bit map related macros */
1815 +#ifndef setbit
1816 +#define NBBY 8 /* 8 bits per byte */
1817 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1818 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1819 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1820 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1821 +#endif
1822 +
1823 +#define NBITS(type) (sizeof(type) * 8)
1824 +#define NBITVAL(bits) (1 << (bits))
1825 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1826 +
1827 +/* crc defines */
1828 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1829 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1830 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1831 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1832 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1833 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1834 +
1835 +/* bcm_format_flags() bit description structure */
1836 +typedef struct bcm_bit_desc {
1837 + uint32 bit;
1838 + char* name;
1839 +} bcm_bit_desc_t;
1840 +
1841 +/* tag_ID/length/value_buffer tuple */
1842 +typedef struct bcm_tlv {
1843 + uint8 id;
1844 + uint8 len;
1845 + uint8 data[1];
1846 +} bcm_tlv_t;
1847 +
1848 +/* Check that bcm_tlv_t fits into the given buflen */
1849 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1850 +
1851 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1852 +#define ETHER_ADDR_STR_LEN 18
1853 +
1854 +/* unaligned load and store macros */
1855 +#ifdef IL_BIGENDIAN
1856 +static INLINE uint32
1857 +load32_ua(uint8 *a)
1858 +{
1859 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1860 +}
1861 +
1862 +static INLINE void
1863 +store32_ua(uint8 *a, uint32 v)
1864 +{
1865 + a[0] = (v >> 24) & 0xff;
1866 + a[1] = (v >> 16) & 0xff;
1867 + a[2] = (v >> 8) & 0xff;
1868 + a[3] = v & 0xff;
1869 +}
1870 +
1871 +static INLINE uint16
1872 +load16_ua(uint8 *a)
1873 +{
1874 + return ((a[0] << 8) | a[1]);
1875 +}
1876 +
1877 +static INLINE void
1878 +store16_ua(uint8 *a, uint16 v)
1879 +{
1880 + a[0] = (v >> 8) & 0xff;
1881 + a[1] = v & 0xff;
1882 +}
1883 +
1884 +#else
1885 +
1886 +static INLINE uint32
1887 +load32_ua(uint8 *a)
1888 +{
1889 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1890 +}
1891 +
1892 +static INLINE void
1893 +store32_ua(uint8 *a, uint32 v)
1894 +{
1895 + a[3] = (v >> 24) & 0xff;
1896 + a[2] = (v >> 16) & 0xff;
1897 + a[1] = (v >> 8) & 0xff;
1898 + a[0] = v & 0xff;
1899 +}
1900 +
1901 +static INLINE uint16
1902 +load16_ua(uint8 *a)
1903 +{
1904 + return ((a[1] << 8) | a[0]);
1905 +}
1906 +
1907 +static INLINE void
1908 +store16_ua(uint8 *a, uint16 v)
1909 +{
1910 + a[1] = (v >> 8) & 0xff;
1911 + a[0] = v & 0xff;
1912 +}
1913 +
1914 +#endif
1915 +
1916 +/* externs */
1917 +/* crc */
1918 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1919 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1920 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1921 +/* format/print */
1922 +/* IE parsing */
1923 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1924 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1925 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1926 +
1927 +/* bcmerror*/
1928 +extern const char *bcmerrorstr(int bcmerror);
1929 +
1930 +/* multi-bool data type: set of bools, mbool is true if any is set */
1931 +typedef uint32 mbool;
1932 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1933 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1934 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1935 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1936 +
1937 +/* power conversion */
1938 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
1939 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
1940 +
1941 +/* generic datastruct to help dump routines */
1942 +struct fielddesc {
1943 + char *nameandfmt;
1944 + uint32 offset;
1945 + uint32 len;
1946 +};
1947 +
1948 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
1949 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
1950 +
1951 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
1952 +
1953 +#endif /* _bcmutils_h_ */
1954 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
1955 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
1956 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-11-07 21:57:07.849586000 +0100
1957 @@ -0,0 +1,85 @@
1958 +/*
1959 + * bit manipulation utility functions
1960 + *
1961 + * Copyright 2005, Broadcom Corporation
1962 + * All Rights Reserved.
1963 + *
1964 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1965 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1966 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1967 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1968 + * $Id$
1969 + */
1970 +
1971 +#ifndef _BITFUNCS_H
1972 +#define _BITFUNCS_H
1973 +
1974 +#include <typedefs.h>
1975 +
1976 +/* local prototypes */
1977 +static INLINE uint32 find_msbit(uint32 x);
1978 +
1979 +
1980 +/*
1981 + * find_msbit: returns index of most significant set bit in x, with index
1982 + * range defined as 0-31. NOTE: returns zero if input is zero.
1983 + */
1984 +
1985 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
1986 +
1987 +/*
1988 + * Implementation for Pentium processors and gcc. Note that this
1989 + * instruction is actually very slow on some processors (e.g., family 5,
1990 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
1991 + * implementation instead.
1992 + */
1993 +static INLINE uint32 find_msbit(uint32 x)
1994 +{
1995 + uint msbit;
1996 + __asm__("bsrl %1,%0"
1997 + :"=r" (msbit)
1998 + :"r" (x));
1999 + return msbit;
2000 +}
2001 +
2002 +#else
2003 +
2004 +/*
2005 + * Generic Implementation
2006 + */
2007 +
2008 +#define DB_POW_MASK16 0xffff0000
2009 +#define DB_POW_MASK8 0x0000ff00
2010 +#define DB_POW_MASK4 0x000000f0
2011 +#define DB_POW_MASK2 0x0000000c
2012 +#define DB_POW_MASK1 0x00000002
2013 +
2014 +static INLINE uint32 find_msbit(uint32 x)
2015 +{
2016 + uint32 temp_x = x;
2017 + uint msbit = 0;
2018 + if (temp_x & DB_POW_MASK16) {
2019 + temp_x >>= 16;
2020 + msbit = 16;
2021 + }
2022 + if (temp_x & DB_POW_MASK8) {
2023 + temp_x >>= 8;
2024 + msbit += 8;
2025 + }
2026 + if (temp_x & DB_POW_MASK4) {
2027 + temp_x >>= 4;
2028 + msbit += 4;
2029 + }
2030 + if (temp_x & DB_POW_MASK2) {
2031 + temp_x >>= 2;
2032 + msbit += 2;
2033 + }
2034 + if (temp_x & DB_POW_MASK1) {
2035 + msbit += 1;
2036 + }
2037 + return(msbit);
2038 +}
2039 +
2040 +#endif
2041 +
2042 +#endif /* _BITFUNCS_H */
2043 diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
2044 --- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2045 +++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-11-07 22:51:38.776726000 +0100
2046 @@ -0,0 +1,191 @@
2047 +/*
2048 + * CFE boot loader OS Abstraction Layer.
2049 + *
2050 + * Copyright 2005, Broadcom Corporation
2051 + * All Rights Reserved.
2052 + *
2053 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2054 + * the contents of this file may not be disclosed to third parties, copied
2055 + * or duplicated in any form, in whole or in part, without the prior
2056 + * written permission of Broadcom Corporation.
2057 + *
2058 + * $Id$
2059 + */
2060 +
2061 +#ifndef _cfe_osl_h_
2062 +#define _cfe_osl_h_
2063 +
2064 +#include <lib_types.h>
2065 +#include <lib_string.h>
2066 +#include <lib_printf.h>
2067 +#include <lib_malloc.h>
2068 +#include <cpu_config.h>
2069 +#include <cfe_timer.h>
2070 +#include <cfe_iocb.h>
2071 +#include <cfe_devfuncs.h>
2072 +#include <addrspace.h>
2073 +
2074 +#include <typedefs.h>
2075 +
2076 +/* dump string */
2077 +extern int (*xprinthook)(const char *str);
2078 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2079 +
2080 +/* assert and panic */
2081 +#define ASSERT(exp) do {} while (0)
2082 +
2083 +/* PCMCIA attribute space access macros */
2084 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2085 + bzero(buf, size)
2086 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2087 + do {} while (0)
2088 +
2089 +/* PCI configuration space access macros */
2090 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2091 + (offset == 8 ? 0 : 0xffffffff)
2092 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2093 + do {} while (0)
2094 +
2095 +/* PCI device bus # and slot # */
2096 +#define OSL_PCI_BUS(osh) (0)
2097 +#define OSL_PCI_SLOT(osh) (0)
2098 +
2099 +/* register access macros */
2100 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2101 +#define rreg32(r) (*(volatile uint32*)(r))
2102 +#ifdef IL_BIGENDIAN
2103 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2104 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2105 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2106 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2107 +#else
2108 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2109 +#define rreg16(r) (*(volatile uint16*)(r))
2110 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2111 +#define rreg8(r) (*(volatile uint8*)(r))
2112 +#endif
2113 +#define R_REG(r) ({ \
2114 + __typeof(*(r)) __osl_v; \
2115 + switch (sizeof(*(r))) { \
2116 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2117 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2118 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2119 + } \
2120 + __osl_v; \
2121 +})
2122 +#define W_REG(r, v) do { \
2123 + switch (sizeof(*(r))) { \
2124 + case sizeof(uint8): wreg8((r), (v)); break; \
2125 + case sizeof(uint16): wreg16((r), (v)); break; \
2126 + case sizeof(uint32): wreg32((r), (v)); break; \
2127 + } \
2128 +} while (0)
2129 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2130 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2131 +
2132 +/* bcopy, bcmp, and bzero */
2133 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2134 +
2135 +#define osl_attach(pdev) ((osl_t*)pdev)
2136 +#define osl_detach(osh)
2137 +
2138 +/* general purpose memory allocation */
2139 +#define MALLOC(osh, size) KMALLOC((size),0)
2140 +#define MFREE(osh, addr, size) KFREE((addr))
2141 +#define MALLOCED(osh) (0)
2142 +#define MALLOC_DUMP(osh, buf, sz)
2143 +#define MALLOC_FAILED(osh) (0)
2144 +
2145 +/* uncached virtual address */
2146 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2147 +
2148 +/* host/bus architecture-specific address byte swap */
2149 +#define BUS_SWAP32(v) (v)
2150 +
2151 +/* get processor cycle count */
2152 +#define OSL_GETCYCLES(x) ((x) = 0)
2153 +
2154 +/* microsecond delay */
2155 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2156 +
2157 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2158 +
2159 +/* map/unmap physical to virtual I/O */
2160 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2161 +#define REG_UNMAP(va) do {} while (0)
2162 +
2163 +/* dereference an address that may cause a bus exception */
2164 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2165 +extern int osl_busprobe(uint32 *val, uint32 addr);
2166 +
2167 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2168 +#define DMA_CONSISTENT_ALIGN 4096
2169 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2170 + osl_dma_alloc_consistent((size), (pap))
2171 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2172 + osl_dma_free_consistent((void*)(va))
2173 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2174 +extern void osl_dma_free_consistent(void *va);
2175 +
2176 +/* map/unmap direction */
2177 +#define DMA_TX 1
2178 +#define DMA_RX 2
2179 +
2180 +/* map/unmap shared (dma-able) memory */
2181 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2182 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2183 + PHYSADDR((ulong)(va)); \
2184 +})
2185 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2186 + do {} while (0)
2187 +
2188 +/* shared (dma-able) memory access macros */
2189 +#define R_SM(r) *(r)
2190 +#define W_SM(r, v) (*(r) = (v))
2191 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2192 +
2193 +/* generic packet structure */
2194 +#define LBUFSZ 4096
2195 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2196 +struct lbuf {
2197 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2198 + struct lbuf *link; /* pointer to next lbuf if in a list */
2199 + uchar *head; /* start of buffer */
2200 + uchar *end; /* end of buffer */
2201 + uchar *data; /* start of data */
2202 + uchar *tail; /* end of data */
2203 + uint len; /* nbytes of data */
2204 + void *cookie; /* generic cookie */
2205 +};
2206 +
2207 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2208 +#define PKTBUFSZ 2048
2209 +
2210 +/* packet primitives */
2211 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2212 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2213 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2214 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2215 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2216 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2217 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2218 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2219 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2220 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2221 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2222 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2223 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2224 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2225 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2226 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2227 +#define PKTPRIO(lb) (0)
2228 +#define PKTSETPRIO(lb, x) do {} while (0)
2229 +extern struct lbuf *osl_pktget(uint len);
2230 +extern void osl_pktfree(struct lbuf *lb);
2231 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2232 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2233 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2234 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2235 +extern int osl_error(int bcmerror);
2236 +
2237 +#endif /* _cfe_osl_h_ */
2238 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
2239 --- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2240 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-11-07 22:51:38.776726000 +0100
2241 @@ -0,0 +1,69 @@
2242 +/*
2243 + * Copyright 2005, Broadcom Corporation
2244 + * All Rights Reserved.
2245 + *
2246 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2247 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2248 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2249 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2250 + *
2251 + * $Id$
2252 + *
2253 +*/
2254 +
2255 +#ifndef _epivers_h_
2256 +#define _epivers_h_
2257 +
2258 +#ifdef linux
2259 +#include <linux/config.h>
2260 +#endif
2261 +
2262 +/* Vendor Name, ASCII, 32 chars max */
2263 +#ifdef COMPANYNAME
2264 +#define HPNA_VENDOR COMPANYNAME
2265 +#else
2266 +#define HPNA_VENDOR "Broadcom Corporation"
2267 +#endif
2268 +
2269 +/* Driver Date, ASCII, 32 chars max */
2270 +#define HPNA_DRV_BUILD_DATE __DATE__
2271 +
2272 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2273 +#define HPNA_HW_MFG_DATE "Not Specified"
2274 +
2275 +/* See documentation for Device Type values, 32 values max */
2276 +#ifndef HPNA_DEV_TYPE
2277 +
2278 +#if defined(CONFIG_BRCM_VJ)
2279 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2280 +
2281 +#elif defined(CONFIG_BCRM_93725)
2282 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2283 +
2284 +#else
2285 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2286 +
2287 +#endif
2288 +
2289 +#endif /* !HPNA_DEV_TYPE */
2290 +
2291 +
2292 +#define EPI_MAJOR_VERSION 3
2293 +
2294 +#define EPI_MINOR_VERSION 130
2295 +
2296 +#define EPI_RC_NUMBER 20
2297 +
2298 +#define EPI_INCREMENTAL_NUMBER 0
2299 +
2300 +#define EPI_BUILD_NUMBER 0
2301 +
2302 +#define EPI_VERSION 3,130,20,0
2303 +
2304 +#define EPI_VERSION_NUM 0x03821400
2305 +
2306 +/* Driver Version String, ASCII, 32 chars max */
2307 +#define EPI_VERSION_STR "3.130.20.0"
2308 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2309 +
2310 +#endif /* _epivers_h_ */
2311 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
2312 --- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2313 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-11-07 21:57:07.849586000 +0100
2314 @@ -0,0 +1,69 @@
2315 +/*
2316 + * Copyright 2005, Broadcom Corporation
2317 + * All Rights Reserved.
2318 + *
2319 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2320 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2321 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2322 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2323 + *
2324 + * $Id$
2325 + *
2326 +*/
2327 +
2328 +#ifndef _epivers_h_
2329 +#define _epivers_h_
2330 +
2331 +#ifdef linux
2332 +#include <linux/config.h>
2333 +#endif
2334 +
2335 +/* Vendor Name, ASCII, 32 chars max */
2336 +#ifdef COMPANYNAME
2337 +#define HPNA_VENDOR COMPANYNAME
2338 +#else
2339 +#define HPNA_VENDOR "Broadcom Corporation"
2340 +#endif
2341 +
2342 +/* Driver Date, ASCII, 32 chars max */
2343 +#define HPNA_DRV_BUILD_DATE __DATE__
2344 +
2345 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2346 +#define HPNA_HW_MFG_DATE "Not Specified"
2347 +
2348 +/* See documentation for Device Type values, 32 values max */
2349 +#ifndef HPNA_DEV_TYPE
2350 +
2351 +#if defined(CONFIG_BRCM_VJ)
2352 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2353 +
2354 +#elif defined(CONFIG_BCRM_93725)
2355 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2356 +
2357 +#else
2358 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2359 +
2360 +#endif
2361 +
2362 +#endif /* !HPNA_DEV_TYPE */
2363 +
2364 +
2365 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2366 +
2367 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2368 +
2369 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2370 +
2371 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2372 +
2373 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2374 +
2375 +#define EPI_VERSION @EPI_VERSION@
2376 +
2377 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2378 +
2379 +/* Driver Version String, ASCII, 32 chars max */
2380 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2381 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2382 +
2383 +#endif /* _epivers_h_ */
2384 diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
2385 --- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2386 +++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-11-07 21:57:07.861586750 +0100
2387 @@ -0,0 +1,59 @@
2388 +/*
2389 + * Driver-specific socket ioctls
2390 + * used by BSD, Linux, and PSOS
2391 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2392 + *
2393 + * Copyright 2005, Broadcom Corporation
2394 + * All Rights Reserved.
2395 + *
2396 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2397 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2398 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2399 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2400 + *
2401 + * $Id$
2402 + */
2403 +
2404 +#ifndef _etsockio_h_
2405 +#define _etsockio_h_
2406 +
2407 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2408 +
2409 +
2410 +#if defined(linux)
2411 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2412 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2413 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2414 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2415 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2416 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2417 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2418 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2419 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2420 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2421 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2422 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2423 +
2424 +#else /* !linux */
2425 +
2426 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2427 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2428 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2429 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2430 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2431 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2432 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2433 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2434 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2435 +
2436 +#endif
2437 +
2438 +/* arg to SIOCTXGEN */
2439 +struct txg {
2440 + uint32 num; /* number of frames to send */
2441 + uint32 delay; /* delay in microseconds between sending each */
2442 + uint32 size; /* size of ether frame to send */
2443 + uchar buf[1514]; /* starting ether frame data */
2444 +};
2445 +
2446 +#endif
2447 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
2448 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2449 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-11-07 21:57:07.861586750 +0100
2450 @@ -0,0 +1,188 @@
2451 +/*
2452 + * flash.h: Common definitions for flash access.
2453 + *
2454 + * Copyright 2005, Broadcom Corporation
2455 + * All Rights Reserved.
2456 + *
2457 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2458 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2459 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2460 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2461 + *
2462 + * $Id$
2463 + */
2464 +
2465 +/* Types of flashes we know about */
2466 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2467 +
2468 +/* Commands to write/erase the flases */
2469 +typedef struct _flash_cmds{
2470 + flash_type_t type;
2471 + bool need_unlock;
2472 + uint16 pre_erase;
2473 + uint16 erase_block;
2474 + uint16 erase_chip;
2475 + uint16 write_word;
2476 + uint16 write_buf;
2477 + uint16 clear_csr;
2478 + uint16 read_csr;
2479 + uint16 read_id;
2480 + uint16 confirm;
2481 + uint16 read_array;
2482 +} flash_cmds_t;
2483 +
2484 +#define UNLOCK_CMD_WORDS 2
2485 +
2486 +typedef struct _unlock_cmd {
2487 + uint addr[UNLOCK_CMD_WORDS];
2488 + uint16 cmd[UNLOCK_CMD_WORDS];
2489 +} unlock_cmd_t;
2490 +
2491 +/* Flash descriptors */
2492 +typedef struct _flash_desc {
2493 + uint16 mfgid; /* Manufacturer Id */
2494 + uint16 devid; /* Device Id */
2495 + uint size; /* Total size in bytes */
2496 + uint width; /* Device width in bytes */
2497 + flash_type_t type; /* Device type old, S, J */
2498 + uint bsize; /* Block size */
2499 + uint nb; /* Number of blocks */
2500 + uint ff; /* First full block */
2501 + uint lf; /* Last full block */
2502 + uint nsub; /* Number of subblocks */
2503 + uint *subblocks; /* Offsets for subblocks */
2504 + char *desc; /* Description */
2505 +} flash_desc_t;
2506 +
2507 +
2508 +#ifdef DECLARE_FLASHES
2509 +flash_cmds_t sflash_cmd_t =
2510 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2511 +
2512 +flash_cmds_t flash_cmds[] = {
2513 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2514 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2515 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2516 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2517 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2518 + { 0 }
2519 +};
2520 +
2521 +unlock_cmd_t unlock_cmd_amd = {
2522 +#ifdef MIPSEB
2523 +/* addr: */ { 0x0aa8, 0x0556},
2524 +#else
2525 +/* addr: */ { 0x0aaa, 0x0554},
2526 +#endif
2527 +/* data: */ { 0xaa, 0x55}
2528 +};
2529 +
2530 +unlock_cmd_t unlock_cmd_sst = {
2531 +#ifdef MIPSEB
2532 +/* addr: */ { 0xaaa8, 0x5556},
2533 +#else
2534 +/* addr: */ { 0xaaaa, 0x5554},
2535 +#endif
2536 +/* data: */ { 0xaa, 0x55}
2537 +};
2538 +
2539 +#define AMD_CMD 0xaaa
2540 +#define SST_CMD 0xaaaa
2541 +
2542 +/* intel unlock block cmds */
2543 +#define INTEL_UNLOCK1 0x60
2544 +#define INTEL_UNLOCK2 0xD0
2545 +
2546 +/* Just eight blocks of 8KB byte each */
2547 +
2548 +uint blk8x8k[] = { 0x00000000,
2549 + 0x00002000,
2550 + 0x00004000,
2551 + 0x00006000,
2552 + 0x00008000,
2553 + 0x0000a000,
2554 + 0x0000c000,
2555 + 0x0000e000,
2556 + 0x00010000
2557 +};
2558 +
2559 +/* Funky AMD arrangement for 29xx800's */
2560 +uint amd800[] = { 0x00000000, /* 16KB */
2561 + 0x00004000, /* 32KB */
2562 + 0x0000c000, /* 8KB */
2563 + 0x0000e000, /* 8KB */
2564 + 0x00010000, /* 8KB */
2565 + 0x00012000, /* 8KB */
2566 + 0x00014000, /* 32KB */
2567 + 0x0001c000, /* 16KB */
2568 + 0x00020000
2569 +};
2570 +
2571 +/* AMD arrangement for 29xx160's */
2572 +uint amd4112[] = { 0x00000000, /* 32KB */
2573 + 0x00008000, /* 8KB */
2574 + 0x0000a000, /* 8KB */
2575 + 0x0000c000, /* 16KB */
2576 + 0x00010000
2577 +};
2578 +uint amd2114[] = { 0x00000000, /* 16KB */
2579 + 0x00004000, /* 8KB */
2580 + 0x00006000, /* 8KB */
2581 + 0x00008000, /* 32KB */
2582 + 0x00010000
2583 +};
2584 +
2585 +
2586 +flash_desc_t sflash_desc =
2587 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2588 +
2589 +flash_desc_t flashes[] = {
2590 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2591 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2592 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2593 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2594 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2595 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2596 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2597 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2598 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2599 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2600 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2601 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2602 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2603 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2604 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2605 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2606 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2607 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2608 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2609 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2610 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2611 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2612 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2613 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2614 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2615 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2616 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2617 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2618 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2619 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2620 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2621 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2622 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2623 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2624 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2625 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2626 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2627 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2628 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2629 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2630 +};
2631 +
2632 +#else
2633 +
2634 +extern flash_cmds_t flash_cmds[];
2635 +extern unlock_cmd_t unlock_cmd;
2636 +extern flash_desc_t flashes[];
2637 +
2638 +#endif
2639 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
2640 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2641 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-11-07 21:57:07.861586750 +0100
2642 @@ -0,0 +1,27 @@
2643 +/*
2644 + * BCM47XX FLASH driver interface
2645 + *
2646 + * Copyright 2005, Broadcom Corporation
2647 + * All Rights Reserved.
2648 + *
2649 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2650 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2651 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2652 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2653 + * $Id$
2654 + */
2655 +
2656 +#ifndef _flashutl_h_
2657 +#define _flashutl_h_
2658 +
2659 +
2660 +#ifndef _LANGUAGE_ASSEMBLY
2661 +
2662 +int sysFlashInit(char *flash_str);
2663 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2664 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2665 +void nvWrite(unsigned short *data, unsigned int len);
2666 +
2667 +#endif /* _LANGUAGE_ASSEMBLY */
2668 +
2669 +#endif /* _flashutl_h_ */
2670 diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
2671 --- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2672 +++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-11-07 22:51:38.776726000 +0100
2673 @@ -0,0 +1,71 @@
2674 +/*
2675 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2676 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2677 + *
2678 + * Copyright 2005, Broadcom Corporation
2679 + * All Rights Reserved.
2680 + *
2681 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2682 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2683 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2684 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2685 + * $Id$
2686 + */
2687 +
2688 +#ifndef _hnddma_h_
2689 +#define _hnddma_h_
2690 +
2691 +/* export structure */
2692 +typedef volatile struct {
2693 + /* rx error counters */
2694 + uint rxgiants; /* rx giant frames */
2695 + uint rxnobuf; /* rx out of dma descriptors */
2696 + /* tx error counters */
2697 + uint txnobuf; /* tx out of dma descriptors */
2698 +} hnddma_t;
2699 +
2700 +#ifndef di_t
2701 +#define di_t void
2702 +#endif
2703 +
2704 +#ifndef osl_t
2705 +#define osl_t void
2706 +#endif
2707 +
2708 +/* externs */
2709 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2710 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2711 +extern void dma_detach(di_t *di);
2712 +extern void dma_txreset(di_t *di);
2713 +extern void dma_rxreset(di_t *di);
2714 +extern void dma_txinit(di_t *di);
2715 +extern bool dma_txenabled(di_t *di);
2716 +extern void dma_rxinit(di_t *di);
2717 +extern void dma_rxenable(di_t *di);
2718 +extern bool dma_rxenabled(di_t *di);
2719 +extern void dma_txsuspend(di_t *di);
2720 +extern void dma_txresume(di_t *di);
2721 +extern bool dma_txsuspended(di_t *di);
2722 +extern bool dma_txsuspendedidle(di_t *di);
2723 +extern bool dma_txstopped(di_t *di);
2724 +extern bool dma_rxstopped(di_t *di);
2725 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2726 +extern void dma_fifoloopbackenable(di_t *di);
2727 +extern void *dma_rx(di_t *di);
2728 +extern void dma_rxfill(di_t *di);
2729 +extern void dma_txreclaim(di_t *di, bool forceall);
2730 +extern void dma_rxreclaim(di_t *di);
2731 +extern uintptr dma_getvar(di_t *di, char *name);
2732 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2733 +extern void *dma_peeknexttxp(di_t *di);
2734 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2735 +extern void dma_txblock(di_t *di);
2736 +extern void dma_txunblock(di_t *di);
2737 +extern uint dma_txactive(di_t *di);
2738 +extern void dma_txrotate(di_t *di);
2739 +
2740 +extern void dma_rxpiomode(dma32regs_t *);
2741 +extern void dma_txpioloopback(dma32regs_t *);
2742 +
2743 +
2744 +#endif /* _hnddma_h_ */
2745 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
2746 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2747 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-11-07 21:57:07.861586750 +0100
2748 @@ -0,0 +1,16 @@
2749 +/*
2750 + * Alternate include file for HND sbmips.h since CFE also ships with
2751 + * a sbmips.h.
2752 + *
2753 + * Copyright 2005, Broadcom Corporation
2754 + * All Rights Reserved.
2755 + *
2756 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2757 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2758 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2759 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2760 + *
2761 + * $Id$
2762 + */
2763 +
2764 +#include "sbmips.h"
2765 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
2766 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2767 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-11-07 22:51:38.776726000 +0100
2768 @@ -0,0 +1,371 @@
2769 +/*
2770 + * Linux OS Independent Layer
2771 + *
2772 + * Copyright 2005, Broadcom Corporation
2773 + * All Rights Reserved.
2774 + *
2775 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2776 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2777 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2778 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2779 + *
2780 + * $Id$
2781 + */
2782 +
2783 +#ifndef _linux_osl_h_
2784 +#define _linux_osl_h_
2785 +
2786 +#include <typedefs.h>
2787 +
2788 +/* use current 2.4.x calling conventions */
2789 +#include <linuxver.h>
2790 +
2791 +/* assert and panic */
2792 +#ifdef __GNUC__
2793 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2794 +#if GCC_VERSION > 30100
2795 +#define ASSERT(exp) do {} while (0)
2796 +#else
2797 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2798 +#define ASSERT(exp)
2799 +#endif
2800 +#endif
2801 +
2802 +/* microsecond delay */
2803 +#define OSL_DELAY(usec) osl_delay(usec)
2804 +extern void osl_delay(uint usec);
2805 +
2806 +/* PCMCIA attribute space access macros */
2807 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2808 +struct pcmcia_dev {
2809 + dev_link_t link; /* PCMCIA device pointer */
2810 + dev_node_t node; /* PCMCIA node structure */
2811 + void *base; /* Mapped attribute memory window */
2812 + size_t size; /* Size of window */
2813 + void *drv; /* Driver data */
2814 +};
2815 +#endif
2816 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2817 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2818 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2819 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2820 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
2821 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
2822 +
2823 +/* PCI configuration space access macros */
2824 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2825 + osl_pci_read_config((osh), (offset), (size))
2826 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2827 + osl_pci_write_config((osh), (offset), (size), (val))
2828 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
2829 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
2830 +
2831 +/* PCI device bus # and slot # */
2832 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
2833 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
2834 +extern uint osl_pci_bus(osl_t *osh);
2835 +extern uint osl_pci_slot(osl_t *osh);
2836 +
2837 +/* OSL initialization */
2838 +extern osl_t *osl_attach(void *pdev);
2839 +extern void osl_detach(osl_t *osh);
2840 +
2841 +/* host/bus architecture-specific byte swap */
2842 +#define BUS_SWAP32(v) (v)
2843 +
2844 +/* general purpose memory allocation */
2845 +
2846 +#if defined(BCMDBG_MEM)
2847 +
2848 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2849 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2850 +#define MALLOCED(osh) osl_malloced((osh))
2851 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2852 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
2853 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
2854 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
2855 +
2856 +#else
2857 +
2858 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2859 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2860 +#define MALLOCED(osh) osl_malloced((osh))
2861 +
2862 +#endif /* BCMDBG_MEM */
2863 +
2864 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2865 +
2866 +extern void *osl_malloc(osl_t *osh, uint size);
2867 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
2868 +extern uint osl_malloced(osl_t *osh);
2869 +extern uint osl_malloc_failed(osl_t *osh);
2870 +
2871 +/* allocate/free shared (dma-able) consistent memory */
2872 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2873 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2874 + osl_dma_alloc_consistent((osh), (size), (pap))
2875 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2876 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2877 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
2878 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
2879 +
2880 +/* map/unmap direction */
2881 +#define DMA_TX 1
2882 +#define DMA_RX 2
2883 +
2884 +/* map/unmap shared (dma-able) memory */
2885 +#define DMA_MAP(osh, va, size, direction, p) \
2886 + osl_dma_map((osh), (va), (size), (direction))
2887 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2888 + osl_dma_unmap((osh), (pa), (size), (direction))
2889 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
2890 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
2891 +
2892 +/* register access macros */
2893 +#if defined(BCMJTAG)
2894 +#include <bcmjtag.h>
2895 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
2896 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
2897 +#endif
2898 +
2899 +/*
2900 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2901 + * Macros expand to calls to functions defined in linux_osl.c .
2902 + */
2903 +#ifndef BINOSL
2904 +
2905 +/* string library, kernel mode */
2906 +#define printf(fmt, args...) printk(fmt, ## args)
2907 +#include <linux/kernel.h>
2908 +#include <linux/string.h>
2909 +
2910 +/* register access macros */
2911 +#if !defined(BCMJTAG)
2912 +#ifndef IL_BIGENDIAN
2913 +#define R_REG(r) ( \
2914 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
2915 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
2916 + readl((volatile uint32*)(r)) \
2917 +)
2918 +#define W_REG(r, v) do { \
2919 + switch (sizeof(*(r))) { \
2920 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
2921 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
2922 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
2923 + } \
2924 +} while (0)
2925 +#else /* IL_BIGENDIAN */
2926 +#define R_REG(r) ({ \
2927 + __typeof(*(r)) __osl_v; \
2928 + switch (sizeof(*(r))) { \
2929 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
2930 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
2931 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
2932 + } \
2933 + __osl_v; \
2934 +})
2935 +#define W_REG(r, v) do { \
2936 + switch (sizeof(*(r))) { \
2937 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
2938 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
2939 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
2940 + } \
2941 +} while (0)
2942 +#endif
2943 +#endif
2944 +
2945 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2946 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2947 +
2948 +/* bcopy, bcmp, and bzero */
2949 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
2950 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
2951 +#define bzero(b, len) memset((b), '\0', (len))
2952 +
2953 +/* uncached virtual address */
2954 +#ifdef mips
2955 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
2956 +#include <asm/addrspace.h>
2957 +#else
2958 +#define OSL_UNCACHED(va) (va)
2959 +#endif
2960 +
2961 +/* get processor cycle count */
2962 +#if defined(mips)
2963 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
2964 +#elif defined(__i386__)
2965 +#define OSL_GETCYCLES(x) rdtscl((x))
2966 +#else
2967 +#define OSL_GETCYCLES(x) ((x) = 0)
2968 +#endif
2969 +
2970 +/* dereference an address that may cause a bus exception */
2971 +#ifdef mips
2972 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
2973 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
2974 +#else
2975 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
2976 +#include <asm/paccess.h>
2977 +#endif
2978 +#else
2979 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
2980 +#endif
2981 +
2982 +/* map/unmap physical to virtual I/O */
2983 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
2984 +#define REG_UNMAP(va) iounmap((void *)(va))
2985 +
2986 +/* shared (dma-able) memory access macros */
2987 +#define R_SM(r) *(r)
2988 +#define W_SM(r, v) (*(r) = (v))
2989 +#define BZERO_SM(r, len) memset((r), '\0', (len))
2990 +
2991 +/* packet primitives */
2992 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
2993 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
2994 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
2995 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
2996 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
2997 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
2998 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
2999 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3000 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3001 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3002 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3003 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3004 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3005 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3006 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3007 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3008 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3009 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3010 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3011 +extern void osl_pktfree(void *skb);
3012 +
3013 +#else /* BINOSL */
3014 +
3015 +/* string library */
3016 +#ifndef LINUX_OSL
3017 +#undef printf
3018 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3019 +#undef sprintf
3020 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3021 +#undef strcmp
3022 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3023 +#undef strncmp
3024 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3025 +#undef strlen
3026 +#define strlen(s) osl_strlen((s))
3027 +#undef strcpy
3028 +#define strcpy(d, s) osl_strcpy((d), (s))
3029 +#undef strncpy
3030 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3031 +#endif
3032 +extern int osl_printf(const char *format, ...);
3033 +extern int osl_sprintf(char *buf, const char *format, ...);
3034 +extern int osl_strcmp(const char *s1, const char *s2);
3035 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3036 +extern int osl_strlen(const char *s);
3037 +extern char* osl_strcpy(char *d, const char *s);
3038 +extern char* osl_strncpy(char *d, const char *s, uint n);
3039 +
3040 +/* register access macros */
3041 +#if !defined(BCMJTAG)
3042 +#define R_REG(r) ( \
3043 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3044 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3045 + osl_readl((volatile uint32*)(r)) \
3046 +)
3047 +#define W_REG(r, v) do { \
3048 + switch (sizeof(*(r))) { \
3049 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3050 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3051 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3052 + } \
3053 +} while (0)
3054 +#endif
3055 +
3056 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3057 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3058 +extern uint8 osl_readb(volatile uint8 *r);
3059 +extern uint16 osl_readw(volatile uint16 *r);
3060 +extern uint32 osl_readl(volatile uint32 *r);
3061 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3062 +extern void osl_writew(uint16 v, volatile uint16 *r);
3063 +extern void osl_writel(uint32 v, volatile uint32 *r);
3064 +
3065 +/* bcopy, bcmp, and bzero */
3066 +extern void bcopy(const void *src, void *dst, int len);
3067 +extern int bcmp(const void *b1, const void *b2, int len);
3068 +extern void bzero(void *b, int len);
3069 +
3070 +/* uncached virtual address */
3071 +#define OSL_UNCACHED(va) osl_uncached((va))
3072 +extern void *osl_uncached(void *va);
3073 +
3074 +/* get processor cycle count */
3075 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3076 +extern uint osl_getcycles(void);
3077 +
3078 +/* dereference an address that may target abort */
3079 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3080 +extern int osl_busprobe(uint32 *val, uint32 addr);
3081 +
3082 +/* map/unmap physical to virtual */
3083 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3084 +#define REG_UNMAP(va) osl_reg_unmap((va))
3085 +extern void *osl_reg_map(uint32 pa, uint size);
3086 +extern void osl_reg_unmap(void *va);
3087 +
3088 +/* shared (dma-able) memory access macros */
3089 +#define R_SM(r) *(r)
3090 +#define W_SM(r, v) (*(r) = (v))
3091 +#define BZERO_SM(r, len) bzero((r), (len))
3092 +
3093 +/* packet primitives */
3094 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3095 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3096 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3097 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3098 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3099 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3100 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3101 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3102 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3103 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3104 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3105 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3106 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3107 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3108 +#define PKTLINK(skb) osl_pktlink((skb))
3109 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3110 +#define PKTPRIO(skb) osl_pktprio((skb))
3111 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3112 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3113 +extern void osl_pktfree(void *skb);
3114 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3115 +extern uint osl_pktlen(osl_t *osh, void *skb);
3116 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3117 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3118 +extern void *osl_pktnext(osl_t *osh, void *skb);
3119 +extern void osl_pktsetnext(void *skb, void *x);
3120 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3121 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3122 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3123 +extern void *osl_pktdup(osl_t *osh, void *skb);
3124 +extern void *osl_pktcookie(void *skb);
3125 +extern void osl_pktsetcookie(void *skb, void *x);
3126 +extern void *osl_pktlink(void *skb);
3127 +extern void osl_pktsetlink(void *skb, void *x);
3128 +extern uint osl_pktprio(void *skb);
3129 +extern void osl_pktsetprio(void *skb, uint x);
3130 +
3131 +#endif /* BINOSL */
3132 +
3133 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3134 +extern int osl_error(int bcmerror);
3135 +
3136 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3137 +#define PKTBUFSZ 2048
3138 +
3139 +#endif /* _linux_osl_h_ */
3140 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
3141 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3142 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-11-07 22:51:38.780726250 +0100
3143 @@ -0,0 +1,411 @@
3144 +/*
3145 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3146 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3147 + *
3148 + * Copyright 2005, Broadcom Corporation
3149 + * All Rights Reserved.
3150 + *
3151 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3152 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3153 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3154 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3155 + *
3156 + * $Id$
3157 + */
3158 +
3159 +#ifndef _linuxver_h_
3160 +#define _linuxver_h_
3161 +
3162 +#include <linux/config.h>
3163 +#include <linux/version.h>
3164 +
3165 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3166 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3167 +#ifdef __UNDEF_NO_VERSION__
3168 +#undef __NO_VERSION__
3169 +#else
3170 +#define __NO_VERSION__
3171 +#endif
3172 +#endif
3173 +
3174 +#if defined(MODULE) && defined(MODVERSIONS)
3175 +#include <linux/modversions.h>
3176 +#endif
3177 +
3178 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3179 +#include <linux/moduleparam.h>
3180 +#endif
3181 +
3182 +
3183 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3184 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3185 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3186 +#endif
3187 +
3188 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3189 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3190 +#include <linux/malloc.h>
3191 +#else
3192 +#include <linux/slab.h>
3193 +#endif
3194 +
3195 +#include <linux/types.h>
3196 +#include <linux/init.h>
3197 +#include <linux/mm.h>
3198 +#include <linux/string.h>
3199 +#include <linux/pci.h>
3200 +#include <linux/interrupt.h>
3201 +#include <linux/netdevice.h>
3202 +#include <asm/io.h>
3203 +
3204 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3205 +#include <linux/workqueue.h>
3206 +#else
3207 +#include <linux/tqueue.h>
3208 +#ifndef work_struct
3209 +#define work_struct tq_struct
3210 +#endif
3211 +#ifndef INIT_WORK
3212 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3213 +#endif
3214 +#ifndef schedule_work
3215 +#define schedule_work(_work) schedule_task((_work))
3216 +#endif
3217 +#ifndef flush_scheduled_work
3218 +#define flush_scheduled_work() flush_scheduled_tasks()
3219 +#endif
3220 +#endif
3221 +
3222 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3223 +/* Some distributions have their own 2.6.x compatibility layers */
3224 +#ifndef IRQ_NONE
3225 +typedef void irqreturn_t;
3226 +#define IRQ_NONE
3227 +#define IRQ_HANDLED
3228 +#define IRQ_RETVAL(x)
3229 +#endif
3230 +#else
3231 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3232 +#endif
3233 +
3234 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3235 +
3236 +#include <pcmcia/version.h>
3237 +#include <pcmcia/cs_types.h>
3238 +#include <pcmcia/cs.h>
3239 +#include <pcmcia/cistpl.h>
3240 +#include <pcmcia/cisreg.h>
3241 +#include <pcmcia/ds.h>
3242 +
3243 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3244 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3245 + * does this, but it's not in 2.4 so we do our own for now. */
3246 +static inline void
3247 +cs_error(client_handle_t handle, int func, int ret)
3248 +{
3249 + error_info_t err = { func, ret };
3250 + CardServices(ReportError, handle, &err);
3251 +}
3252 +#endif
3253 +
3254 +#endif /* CONFIG_PCMCIA */
3255 +
3256 +#ifndef __exit
3257 +#define __exit
3258 +#endif
3259 +#ifndef __devexit
3260 +#define __devexit
3261 +#endif
3262 +#ifndef __devinit
3263 +#define __devinit __init
3264 +#endif
3265 +#ifndef __devinitdata
3266 +#define __devinitdata
3267 +#endif
3268 +#ifndef __devexit_p
3269 +#define __devexit_p(x) x
3270 +#endif
3271 +
3272 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3273 +
3274 +#define pci_get_drvdata(dev) (dev)->sysdata
3275 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3276 +
3277 +/*
3278 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3279 + */
3280 +
3281 +struct pci_device_id {
3282 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3283 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3284 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3285 + unsigned long driver_data; /* Data private to the driver */
3286 +};
3287 +
3288 +struct pci_driver {
3289 + struct list_head node;
3290 + char *name;
3291 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3292 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3293 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3294 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3295 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3296 +};
3297 +
3298 +#define MODULE_DEVICE_TABLE(type, name)
3299 +#define PCI_ANY_ID (~0)
3300 +
3301 +/* compatpci.c */
3302 +#define pci_module_init pci_register_driver
3303 +extern int pci_register_driver(struct pci_driver *drv);
3304 +extern void pci_unregister_driver(struct pci_driver *drv);
3305 +
3306 +#endif /* PCI registration */
3307 +
3308 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3309 +#ifdef MODULE
3310 +#define module_init(x) int init_module(void) { return x(); }
3311 +#define module_exit(x) void cleanup_module(void) { x(); }
3312 +#else
3313 +#define module_init(x) __initcall(x);
3314 +#define module_exit(x) __exitcall(x);
3315 +#endif
3316 +#endif
3317 +
3318 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3319 +#define list_for_each(pos, head) \
3320 + for (pos = (head)->next; pos != (head); pos = pos->next)
3321 +#endif
3322 +
3323 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3324 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3325 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3326 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3327 +#endif
3328 +
3329 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3330 +#define pci_enable_device(dev) do { } while (0)
3331 +#endif
3332 +
3333 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3334 +#define net_device device
3335 +#endif
3336 +
3337 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3338 +
3339 +/*
3340 + * DMA mapping
3341 + *
3342 + * See linux/Documentation/DMA-mapping.txt
3343 + */
3344 +
3345 +#ifndef PCI_DMA_TODEVICE
3346 +#define PCI_DMA_TODEVICE 1
3347 +#define PCI_DMA_FROMDEVICE 2
3348 +#endif
3349 +
3350 +typedef u32 dma_addr_t;
3351 +
3352 +/* Pure 2^n version of get_order */
3353 +static inline int get_order(unsigned long size)
3354 +{
3355 + int order;
3356 +
3357 + size = (size-1) >> (PAGE_SHIFT-1);
3358 + order = -1;
3359 + do {
3360 + size >>= 1;
3361 + order++;
3362 + } while (size);
3363 + return order;
3364 +}
3365 +
3366 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3367 + dma_addr_t *dma_handle)
3368 +{
3369 + void *ret;
3370 + int gfp = GFP_ATOMIC | GFP_DMA;
3371 +
3372 + ret = (void *)__get_free_pages(gfp, get_order(size));
3373 +
3374 + if (ret != NULL) {
3375 + memset(ret, 0, size);
3376 + *dma_handle = virt_to_bus(ret);
3377 + }
3378 + return ret;
3379 +}
3380 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3381 + void *vaddr, dma_addr_t dma_handle)
3382 +{
3383 + free_pages((unsigned long)vaddr, get_order(size));
3384 +}
3385 +#ifdef ILSIM
3386 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3387 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3388 +#else
3389 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3390 +#define pci_unmap_single(cookie, address, size, dir)
3391 +#endif
3392 +
3393 +#endif /* DMA mapping */
3394 +
3395 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3396 +
3397 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3398 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3399 +
3400 +/* pcmcia-cs provides its own netdevice compatibility layer */
3401 +#ifndef _COMPAT_NETDEVICE_H
3402 +
3403 +/*
3404 + * SoftNet
3405 + *
3406 + * For pre-softnet kernels we need to tell the upper layer not to
3407 + * re-enter start_xmit() while we are in there. However softnet
3408 + * guarantees not to enter while we are in there so there is no need
3409 + * to do the netif_stop_queue() dance unless the transmit queue really
3410 + * gets stuck. This should also improve performance according to tests
3411 + * done by Aman Singla.
3412 + */
3413 +
3414 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3415 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3416 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3417 +
3418 +static inline void netif_start_queue(struct net_device *dev)
3419 +{
3420 + dev->tbusy = 0;
3421 + dev->interrupt = 0;
3422 + dev->start = 1;
3423 +}
3424 +
3425 +#define netif_queue_stopped(dev) (dev)->tbusy
3426 +#define netif_running(dev) (dev)->start
3427 +
3428 +#endif /* _COMPAT_NETDEVICE_H */
3429 +
3430 +#define netif_device_attach(dev) netif_start_queue(dev)
3431 +#define netif_device_detach(dev) netif_stop_queue(dev)
3432 +
3433 +/* 2.4.x renamed bottom halves to tasklets */
3434 +#define tasklet_struct tq_struct
3435 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3436 +{
3437 + queue_task(tasklet, &tq_immediate);
3438 + mark_bh(IMMEDIATE_BH);
3439 +}
3440 +
3441 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3442 + void (*func)(unsigned long),
3443 + unsigned long data)
3444 +{
3445 + tasklet->next = NULL;
3446 + tasklet->sync = 0;
3447 + tasklet->routine = (void (*)(void *))func;
3448 + tasklet->data = (void *)data;
3449 +}
3450 +#define tasklet_kill(tasklet) {do{} while(0);}
3451 +
3452 +/* 2.4.x introduced del_timer_sync() */
3453 +#define del_timer_sync(timer) del_timer(timer)
3454 +
3455 +#else
3456 +
3457 +#define netif_down(dev)
3458 +
3459 +#endif /* SoftNet */
3460 +
3461 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3462 +
3463 +/*
3464 + * Emit code to initialise a tq_struct's routine and data pointers
3465 + */
3466 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3467 + do { \
3468 + (_tq)->routine = _routine; \
3469 + (_tq)->data = _data; \
3470 + } while (0)
3471 +
3472 +/*
3473 + * Emit code to initialise all of a tq_struct
3474 + */
3475 +#define INIT_TQUEUE(_tq, _routine, _data) \
3476 + do { \
3477 + INIT_LIST_HEAD(&(_tq)->list); \
3478 + (_tq)->sync = 0; \
3479 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3480 + } while (0)
3481 +
3482 +#endif
3483 +
3484 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3485 +
3486 +/* Power management related routines */
3487 +
3488 +static inline int
3489 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3490 +{
3491 + int i;
3492 + if (buffer) {
3493 + for (i = 0; i < 16; i++)
3494 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3495 + }
3496 + return 0;
3497 +}
3498 +
3499 +static inline int
3500 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3501 +{
3502 + int i;
3503 +
3504 + if (buffer) {
3505 + for (i = 0; i < 16; i++)
3506 + pci_write_config_dword(dev,i * 4, buffer[i]);
3507 + }
3508 + /*
3509 + * otherwise, write the context information we know from bootup.
3510 + * This works around a problem where warm-booting from Windows
3511 + * combined with a D3(hot)->D0 transition causes PCI config
3512 + * header data to be forgotten.
3513 + */
3514 + else {
3515 + for (i = 0; i < 6; i ++)
3516 + pci_write_config_dword(dev,
3517 + PCI_BASE_ADDRESS_0 + (i * 4),
3518 + pci_resource_start(dev, i));
3519 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3520 + }
3521 + return 0;
3522 +}
3523 +
3524 +#endif /* PCI power management */
3525 +
3526 +/* Old cp0 access macros deprecated in 2.4.19 */
3527 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3528 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3529 +#endif
3530 +
3531 +/* Module refcount handled internally in 2.6.x */
3532 +#ifndef SET_MODULE_OWNER
3533 +#define SET_MODULE_OWNER(dev) do {} while (0)
3534 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3535 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3536 +#else
3537 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3538 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3539 +#endif
3540 +
3541 +#ifndef SET_NETDEV_DEV
3542 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3543 +#endif
3544 +
3545 +#ifndef HAVE_FREE_NETDEV
3546 +#define free_netdev(dev) kfree(dev)
3547 +#endif
3548 +
3549 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3550 +/* struct packet_type redefined in 2.6.x */
3551 +#define af_packet_priv data
3552 +#endif
3553 +
3554 +#endif /* _linuxver_h_ */
3555 diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
3556 --- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3557 +++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-11-07 22:51:38.780726250 +0100
3558 @@ -0,0 +1,126 @@
3559 +/*
3560 + * HND Minimal OS Abstraction Layer.
3561 + *
3562 + * Copyright 2005, Broadcom Corporation
3563 + * All Rights Reserved.
3564 + *
3565 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3566 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3567 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3568 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3569 + *
3570 + * $Id$
3571 + */
3572 +
3573 +#ifndef _min_osl_h_
3574 +#define _min_osl_h_
3575 +
3576 +#include <typedefs.h>
3577 +#include <sbconfig.h>
3578 +#include <mipsinc.h>
3579 +
3580 +/* Cache support */
3581 +extern void caches_on(void);
3582 +extern void blast_dcache(void);
3583 +extern void blast_icache(void);
3584 +
3585 +/* uart output */
3586 +extern void putc(int c);
3587 +
3588 +/* lib functions */
3589 +extern int printf(const char *fmt, ...);
3590 +extern int sprintf(char *buf, const char *fmt, ...);
3591 +extern int strcmp(const char *s1, const char *s2);
3592 +extern int strncmp(const char *s1, const char *s2, uint n);
3593 +extern char *strcpy(char *dest, const char *src);
3594 +extern char *strncpy(char *dest, const char *src, uint n);
3595 +extern uint strlen(const char *s);
3596 +extern char *strchr(const char *str,int c);
3597 +extern char *strrchr(const char *str, int c);
3598 +extern char *strcat(char *d, const char *s);
3599 +extern void *memset(void *dest, int c, uint n);
3600 +extern void *memcpy(void *dest, const void *src, uint n);
3601 +extern int memcmp(const void *s1, const void *s2, uint n);
3602 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3603 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3604 +#define bzero(b, len) memset((b), '\0', (len))
3605 +
3606 +/* assert & debugging */
3607 +#define ASSERT(exp) do {} while (0)
3608 +
3609 +/* PCMCIA attribute space access macros */
3610 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3611 + ASSERT(0)
3612 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3613 + ASSERT(0)
3614 +
3615 +/* PCI configuration space access macros */
3616 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3617 + (offset == 8 ? 0 : 0xffffffff)
3618 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3619 + do {} while (0)
3620 +
3621 +/* PCI device bus # and slot # */
3622 +#define OSL_PCI_BUS(osh) (0)
3623 +#define OSL_PCI_SLOT(osh) (0)
3624 +
3625 +/* register access macros */
3626 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3627 +#define rreg32(r) (*(volatile uint32*)(r))
3628 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3629 +#define rreg16(r) (*(volatile uint16*)(r))
3630 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3631 +#define rreg8(r) (*(volatile uint8*)(r))
3632 +#define R_REG(r) ({ \
3633 + __typeof(*(r)) __osl_v; \
3634 + switch (sizeof(*(r))) { \
3635 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3636 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3637 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3638 + } \
3639 + __osl_v; \
3640 +})
3641 +#define W_REG(r, v) do { \
3642 + switch (sizeof(*(r))) { \
3643 + case sizeof(uint8): wreg8((r), (v)); break; \
3644 + case sizeof(uint16): wreg16((r), (v)); break; \
3645 + case sizeof(uint32): wreg32((r), (v)); break; \
3646 + } \
3647 +} while (0)
3648 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3649 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3650 +
3651 +/* general purpose memory allocation */
3652 +#define MALLOC(osh, size) malloc(size)
3653 +#define MFREE(osh, addr, size) free(addr)
3654 +#define MALLOCED(osh) 0
3655 +#define MALLOC_FAILED(osh) 0
3656 +#define MALLOC_DUMP(osh, buf, sz)
3657 +extern int free(void *ptr);
3658 +extern void *malloc(uint size);
3659 +
3660 +/* uncached virtual address */
3661 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3662 +
3663 +/* host/bus architecture-specific address byte swap */
3664 +#define BUS_SWAP32(v) (v)
3665 +
3666 +/* microsecond delay */
3667 +#define OSL_DELAY(usec) udelay(usec)
3668 +extern void udelay(uint32 usec);
3669 +
3670 +/* map/unmap physical to virtual I/O */
3671 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3672 +#define REG_UNMAP(va) do {} while (0)
3673 +
3674 +/* dereference an address that may cause a bus exception */
3675 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3676 +
3677 +/* Misc stubs */
3678 +#define osl_attach(pdev) ((osl_t*)pdev)
3679 +#define osl_detach(osh)
3680 +extern void *osl_init(void);
3681 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3682 +extern int osl_error(int);
3683 +
3684 +#endif /* _min_osl_h_ */
3685 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
3686 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3687 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-11-07 22:51:38.780726250 +0100
3688 @@ -0,0 +1,552 @@
3689 +/*
3690 + * HND Run Time Environment for standalone MIPS programs.
3691 + *
3692 + * Copyright 2005, Broadcom Corporation
3693 + * All Rights Reserved.
3694 + *
3695 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3696 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3697 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3698 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3699 + *
3700 + * $Id$
3701 + */
3702 +
3703 +#ifndef _MISPINC_H
3704 +#define _MISPINC_H
3705 +
3706 +
3707 +/* MIPS defines */
3708 +
3709 +#ifdef _LANGUAGE_ASSEMBLY
3710 +
3711 +/*
3712 + * Symbolic register names for 32 bit ABI
3713 + */
3714 +#define zero $0 /* wired zero */
3715 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3716 +#define v0 $2 /* return value */
3717 +#define v1 $3
3718 +#define a0 $4 /* argument registers */
3719 +#define a1 $5
3720 +#define a2 $6
3721 +#define a3 $7
3722 +#define t0 $8 /* caller saved */
3723 +#define t1 $9
3724 +#define t2 $10
3725 +#define t3 $11
3726 +#define t4 $12
3727 +#define t5 $13
3728 +#define t6 $14
3729 +#define t7 $15
3730 +#define s0 $16 /* callee saved */
3731 +#define s1 $17
3732 +#define s2 $18
3733 +#define s3 $19
3734 +#define s4 $20
3735 +#define s5 $21
3736 +#define s6 $22
3737 +#define s7 $23
3738 +#define t8 $24 /* caller saved */
3739 +#define t9 $25
3740 +#define jp $25 /* PIC jump register */
3741 +#define k0 $26 /* kernel scratch */
3742 +#define k1 $27
3743 +#define gp $28 /* global pointer */
3744 +#define sp $29 /* stack pointer */
3745 +#define fp $30 /* frame pointer */
3746 +#define s8 $30 /* same like fp! */
3747 +#define ra $31 /* return address */
3748 +
3749 +
3750 +/*
3751 + * CP0 Registers
3752 + */
3753 +
3754 +#define C0_INX $0
3755 +#define C0_RAND $1
3756 +#define C0_TLBLO0 $2
3757 +#define C0_TLBLO C0_TLBLO0
3758 +#define C0_TLBLO1 $3
3759 +#define C0_CTEXT $4
3760 +#define C0_PGMASK $5
3761 +#define C0_WIRED $6
3762 +#define C0_BADVADDR $8
3763 +#define C0_COUNT $9
3764 +#define C0_TLBHI $10
3765 +#define C0_COMPARE $11
3766 +#define C0_SR $12
3767 +#define C0_STATUS C0_SR
3768 +#define C0_CAUSE $13
3769 +#define C0_EPC $14
3770 +#define C0_PRID $15
3771 +#define C0_CONFIG $16
3772 +#define C0_LLADDR $17
3773 +#define C0_WATCHLO $18
3774 +#define C0_WATCHHI $19
3775 +#define C0_XCTEXT $20
3776 +#define C0_DIAGNOSTIC $22
3777 +#define C0_BROADCOM C0_DIAGNOSTIC
3778 +#define C0_PERFORMANCE $25
3779 +#define C0_ECC $26
3780 +#define C0_CACHEERR $27
3781 +#define C0_TAGLO $28
3782 +#define C0_TAGHI $29
3783 +#define C0_ERREPC $30
3784 +#define C0_DESAVE $31
3785 +
3786 +/*
3787 + * LEAF - declare leaf routine
3788 + */
3789 +#define LEAF(symbol) \
3790 + .globl symbol; \
3791 + .align 2; \
3792 + .type symbol,@function; \
3793 + .ent symbol,0; \
3794 +symbol: .frame sp,0,ra
3795 +
3796 +/*
3797 + * END - mark end of function
3798 + */
3799 +#define END(function) \
3800 + .end function; \
3801 + .size function,.-function
3802 +
3803 +#define _ULCAST_
3804 +
3805 +#else
3806 +
3807 +/*
3808 + * The following macros are especially useful for __asm__
3809 + * inline assembler.
3810 + */
3811 +#ifndef __STR
3812 +#define __STR(x) #x
3813 +#endif
3814 +#ifndef STR
3815 +#define STR(x) __STR(x)
3816 +#endif
3817 +
3818 +#define _ULCAST_ (unsigned long)
3819 +
3820 +
3821 +/*
3822 + * CP0 Registers
3823 + */
3824 +
3825 +#define C0_INX 0 /* CP0: TLB Index */
3826 +#define C0_RAND 1 /* CP0: TLB Random */
3827 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3828 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3829 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3830 +#define C0_CTEXT 4 /* CP0: Context */
3831 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3832 +#define C0_WIRED 6 /* CP0: TLB Wired */
3833 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3834 +#define C0_COUNT 9 /* CP0: Count */
3835 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3836 +#define C0_COMPARE 11 /* CP0: Compare */
3837 +#define C0_SR 12 /* CP0: Processor Status */
3838 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3839 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3840 +#define C0_EPC 14 /* CP0: Exception PC */
3841 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3842 +#define C0_CONFIG 16 /* CP0: Config */
3843 +#define C0_LLADDR 17 /* CP0: LLAddr */
3844 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3845 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3846 +#define C0_XCTEXT 20 /* CP0: XContext */
3847 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3848 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3849 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
3850 +#define C0_ECC 26 /* CP0: ECC */
3851 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3852 +#define C0_TAGLO 28 /* CP0: TagLo */
3853 +#define C0_TAGHI 29 /* CP0: TagHi */
3854 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3855 +#define C0_DESAVE 31 /* CP0: DebugSave */
3856 +
3857 +#endif /* _LANGUAGE_ASSEMBLY */
3858 +
3859 +/*
3860 + * Memory segments (32bit kernel mode addresses)
3861 + */
3862 +#undef KUSEG
3863 +#undef KSEG0
3864 +#undef KSEG1
3865 +#undef KSEG2
3866 +#undef KSEG3
3867 +#define KUSEG 0x00000000
3868 +#define KSEG0 0x80000000
3869 +#define KSEG1 0xa0000000
3870 +#define KSEG2 0xc0000000
3871 +#define KSEG3 0xe0000000
3872 +#define PHYSADDR_MASK 0x1fffffff
3873 +
3874 +/*
3875 + * Map an address to a certain kernel segment
3876 + */
3877 +#undef PHYSADDR
3878 +#undef KSEG0ADDR
3879 +#undef KSEG1ADDR
3880 +#undef KSEG2ADDR
3881 +#undef KSEG3ADDR
3882 +
3883 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3884 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3885 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3886 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3887 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3888 +
3889 +
3890 +#ifndef Index_Invalidate_I
3891 +/*
3892 + * Cache Operations
3893 + */
3894 +#define Index_Invalidate_I 0x00
3895 +#define Index_Writeback_Inv_D 0x01
3896 +#define Index_Invalidate_SI 0x02
3897 +#define Index_Writeback_Inv_SD 0x03
3898 +#define Index_Load_Tag_I 0x04
3899 +#define Index_Load_Tag_D 0x05
3900 +#define Index_Load_Tag_SI 0x06
3901 +#define Index_Load_Tag_SD 0x07
3902 +#define Index_Store_Tag_I 0x08
3903 +#define Index_Store_Tag_D 0x09
3904 +#define Index_Store_Tag_SI 0x0A
3905 +#define Index_Store_Tag_SD 0x0B
3906 +#define Create_Dirty_Excl_D 0x0d
3907 +#define Create_Dirty_Excl_SD 0x0f
3908 +#define Hit_Invalidate_I 0x10
3909 +#define Hit_Invalidate_D 0x11
3910 +#define Hit_Invalidate_SI 0x12
3911 +#define Hit_Invalidate_SD 0x13
3912 +#define Fill_I 0x14
3913 +#define Hit_Writeback_Inv_D 0x15
3914 + /* 0x16 is unused */
3915 +#define Hit_Writeback_Inv_SD 0x17
3916 +#define R5K_Page_Invalidate_S 0x17
3917 +#define Hit_Writeback_I 0x18
3918 +#define Hit_Writeback_D 0x19
3919 + /* 0x1a is unused */
3920 +#define Hit_Writeback_SD 0x1b
3921 + /* 0x1c is unused */
3922 + /* 0x1e is unused */
3923 +#define Hit_Set_Virtual_SI 0x1e
3924 +#define Hit_Set_Virtual_SD 0x1f
3925 +#endif
3926 +
3927 +
3928 +/*
3929 + * R4x00 interrupt enable / cause bits
3930 + */
3931 +#define IE_SW0 (_ULCAST_(1) << 8)
3932 +#define IE_SW1 (_ULCAST_(1) << 9)
3933 +#define IE_IRQ0 (_ULCAST_(1) << 10)
3934 +#define IE_IRQ1 (_ULCAST_(1) << 11)
3935 +#define IE_IRQ2 (_ULCAST_(1) << 12)
3936 +#define IE_IRQ3 (_ULCAST_(1) << 13)
3937 +#define IE_IRQ4 (_ULCAST_(1) << 14)
3938 +#define IE_IRQ5 (_ULCAST_(1) << 15)
3939 +
3940 +#ifndef ST0_UM
3941 +/*
3942 + * Bitfields in the mips32 cp0 status register
3943 + */
3944 +#define ST0_IE 0x00000001
3945 +#define ST0_EXL 0x00000002
3946 +#define ST0_ERL 0x00000004
3947 +#define ST0_UM 0x00000010
3948 +#define ST0_SWINT0 0x00000100
3949 +#define ST0_SWINT1 0x00000200
3950 +#define ST0_HWINT0 0x00000400
3951 +#define ST0_HWINT1 0x00000800
3952 +#define ST0_HWINT2 0x00001000
3953 +#define ST0_HWINT3 0x00002000
3954 +#define ST0_HWINT4 0x00004000
3955 +#define ST0_HWINT5 0x00008000
3956 +#define ST0_IM 0x0000ff00
3957 +#define ST0_NMI 0x00080000
3958 +#define ST0_SR 0x00100000
3959 +#define ST0_TS 0x00200000
3960 +#define ST0_BEV 0x00400000
3961 +#define ST0_RE 0x02000000
3962 +#define ST0_RP 0x08000000
3963 +#define ST0_CU 0xf0000000
3964 +#define ST0_CU0 0x10000000
3965 +#define ST0_CU1 0x20000000
3966 +#define ST0_CU2 0x40000000
3967 +#define ST0_CU3 0x80000000
3968 +#endif
3969 +
3970 +
3971 +/*
3972 + * Bitfields in the mips32 cp0 cause register
3973 + */
3974 +#define C_EXC 0x0000007c
3975 +#define C_EXC_SHIFT 2
3976 +#define C_INT 0x0000ff00
3977 +#define C_INT_SHIFT 8
3978 +#define C_SW0 (_ULCAST_(1) << 8)
3979 +#define C_SW1 (_ULCAST_(1) << 9)
3980 +#define C_IRQ0 (_ULCAST_(1) << 10)
3981 +#define C_IRQ1 (_ULCAST_(1) << 11)
3982 +#define C_IRQ2 (_ULCAST_(1) << 12)
3983 +#define C_IRQ3 (_ULCAST_(1) << 13)
3984 +#define C_IRQ4 (_ULCAST_(1) << 14)
3985 +#define C_IRQ5 (_ULCAST_(1) << 15)
3986 +#define C_WP 0x00400000
3987 +#define C_IV 0x00800000
3988 +#define C_CE 0x30000000
3989 +#define C_CE_SHIFT 28
3990 +#define C_BD 0x80000000
3991 +
3992 +/* Values in C_EXC */
3993 +#define EXC_INT 0
3994 +#define EXC_TLBM 1
3995 +#define EXC_TLBL 2
3996 +#define EXC_TLBS 3
3997 +#define EXC_AEL 4
3998 +#define EXC_AES 5
3999 +#define EXC_IBE 6
4000 +#define EXC_DBE 7
4001 +#define EXC_SYS 8
4002 +#define EXC_BPT 9
4003 +#define EXC_RI 10
4004 +#define EXC_CU 11
4005 +#define EXC_OV 12
4006 +#define EXC_TR 13
4007 +#define EXC_WATCH 23
4008 +#define EXC_MCHK 24
4009 +
4010 +
4011 +/*
4012 + * Bits in the cp0 config register.
4013 + */
4014 +#define CONF_CM_CACHABLE_NO_WA 0
4015 +#define CONF_CM_CACHABLE_WA 1
4016 +#define CONF_CM_UNCACHED 2
4017 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4018 +#define CONF_CM_CACHABLE_CE 4
4019 +#define CONF_CM_CACHABLE_COW 5
4020 +#define CONF_CM_CACHABLE_CUW 6
4021 +#define CONF_CM_CACHABLE_ACCELERATED 7
4022 +#define CONF_CM_CMASK 7
4023 +#define CONF_CU (_ULCAST_(1) << 3)
4024 +#define CONF_DB (_ULCAST_(1) << 4)
4025 +#define CONF_IB (_ULCAST_(1) << 5)
4026 +#define CONF_SE (_ULCAST_(1) << 12)
4027 +#define CONF_SC (_ULCAST_(1) << 17)
4028 +#define CONF_AC (_ULCAST_(1) << 23)
4029 +#define CONF_HALT (_ULCAST_(1) << 25)
4030 +
4031 +
4032 +/*
4033 + * Bits in the cp0 config register select 1.
4034 + */
4035 +#define CONF1_FP 0x00000001 /* FPU present */
4036 +#define CONF1_EP 0x00000002 /* EJTAG present */
4037 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4038 +#define CONF1_WR 0x00000008 /* Watch registers present */
4039 +#define CONF1_PC 0x00000010 /* Performance counters present */
4040 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4041 +#define CONF1_DA_MASK 0x00000380
4042 +#define CONF1_DA_BASE 1
4043 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4044 +#define CONF1_DL_MASK 0x00001c00
4045 +#define CONF1_DL_BASE 2
4046 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4047 +#define CONF1_DS_MASK 0x0000e000
4048 +#define CONF1_DS_BASE 64
4049 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4050 +#define CONF1_IA_MASK 0x00070000
4051 +#define CONF1_IA_BASE 1
4052 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4053 +#define CONF1_IL_MASK 0x00380000
4054 +#define CONF1_IL_BASE 2
4055 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4056 +#define CONF1_IS_MASK 0x01c00000
4057 +#define CONF1_IS_BASE 64
4058 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4059 +#define CONF1_MS_SHIFT 25
4060 +
4061 +/* PRID register */
4062 +#define PRID_COPT_MASK 0xff000000
4063 +#define PRID_COMP_MASK 0x00ff0000
4064 +#define PRID_IMP_MASK 0x0000ff00
4065 +#define PRID_REV_MASK 0x000000ff
4066 +
4067 +#define PRID_COMP_LEGACY 0x000000
4068 +#define PRID_COMP_MIPS 0x010000
4069 +#define PRID_COMP_BROADCOM 0x020000
4070 +#define PRID_COMP_ALCHEMY 0x030000
4071 +#define PRID_COMP_SIBYTE 0x040000
4072 +#define PRID_IMP_BCM4710 0x4000
4073 +#define PRID_IMP_BCM3302 0x9000
4074 +#define PRID_IMP_BCM3303 0x9100
4075 +
4076 +#define PRID_IMP_UNKNOWN 0xff00
4077 +
4078 +#define BCM330X(id) \
4079 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4080 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4081 +
4082 +/* Bits in C0_BROADCOM */
4083 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4084 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4085 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4086 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4087 +
4088 +/* PreFetch Cache aka Read Ahead Cache */
4089 +
4090 +#define PFC_CR0 0xff400000 /* control reg 0 */
4091 +#define PFC_CR1 0xff400004 /* control reg 1 */
4092 +
4093 +/* PFC operations */
4094 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
4095 +#define PFC_D 0x00000002 /* Enable PFC use for data */
4096 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
4097 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
4098 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
4099 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
4100 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
4101 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
4102 +#define PFC_BRR 0x40000000 /* Bus error indication */
4103 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
4104 +
4105 +/* Handy defaults */
4106 +#define PFC_DISABLED 0
4107 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
4108 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
4109 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
4110 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
4111 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
4112 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
4113 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
4114 +
4115 +
4116 +/*
4117 + * These are the UART port assignments, expressed as offsets from the base
4118 + * register. These assignments should hold for any serial port based on
4119 + * a 8250, 16450, or 16550(A).
4120 + */
4121 +
4122 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4123 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4124 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4125 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4126 +#define UART_LCR 3 /* Out: Line Control Register */
4127 +#define UART_MCR 4 /* Out: Modem Control Register */
4128 +#define UART_LSR 5 /* In: Line Status Register */
4129 +#define UART_MSR 6 /* In: Modem Status Register */
4130 +#define UART_SCR 7 /* I/O: Scratch Register */
4131 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4132 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4133 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4134 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4135 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4136 +
4137 +
4138 +#ifndef _LANGUAGE_ASSEMBLY
4139 +
4140 +/*
4141 + * Macros to access the system control coprocessor
4142 + */
4143 +
4144 +#define MFC0(source, sel) \
4145 +({ \
4146 + int __res; \
4147 + __asm__ __volatile__( \
4148 + ".set\tnoreorder\n\t" \
4149 + ".set\tnoat\n\t" \
4150 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
4151 + "move\t%0,$1\n\t" \
4152 + ".set\tat\n\t" \
4153 + ".set\treorder" \
4154 + :"=r" (__res) \
4155 + : \
4156 + :"$1"); \
4157 + __res; \
4158 +})
4159 +
4160 +#define MTC0(source, sel, value) \
4161 +do { \
4162 + __asm__ __volatile__( \
4163 + ".set\tnoreorder\n\t" \
4164 + ".set\tnoat\n\t" \
4165 + "move\t$1,%z0\n\t" \
4166 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
4167 + ".set\tat\n\t" \
4168 + ".set\treorder" \
4169 + : \
4170 + :"jr" (value) \
4171 + :"$1"); \
4172 +} while (0)
4173 +
4174 +#define get_c0_count() \
4175 +({ \
4176 + int __res; \
4177 + __asm__ __volatile__( \
4178 + ".set\tnoreorder\n\t" \
4179 + ".set\tnoat\n\t" \
4180 + "mfc0\t%0,$9\n\t" \
4181 + ".set\tat\n\t" \
4182 + ".set\treorder" \
4183 + :"=r" (__res)); \
4184 + __res; \
4185 +})
4186 +
4187 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
4188 +{
4189 + uint lsz, sets, ways;
4190 +
4191 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4192 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
4193 + lsz = CONF1_IL_BASE << lsz;
4194 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
4195 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
4196 + *size = lsz * sets * ways;
4197 + *lsize = lsz;
4198 +}
4199 +
4200 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
4201 +{
4202 + uint lsz, sets, ways;
4203 +
4204 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
4205 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
4206 + lsz = CONF1_DL_BASE << lsz;
4207 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
4208 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
4209 + *size = lsz * sets * ways;
4210 + *lsize = lsz;
4211 +}
4212 +
4213 +#define cache_op(base, op) \
4214 + __asm__ __volatile__(" \
4215 + .set noreorder; \
4216 + .set mips3; \
4217 + cache %1, (%0); \
4218 + .set mips0; \
4219 + .set reorder" \
4220 + : \
4221 + : "r" (base), \
4222 + "i" (op));
4223 +
4224 +#define cache_unroll4(base, delta, op) \
4225 + __asm__ __volatile__(" \
4226 + .set noreorder; \
4227 + .set mips3; \
4228 + cache %1,0(%0); \
4229 + cache %1,delta(%0); \
4230 + cache %1,(2 * delta)(%0); \
4231 + cache %1,(3 * delta)(%0); \
4232 + .set mips0; \
4233 + .set reorder" \
4234 + : \
4235 + : "r" (base), \
4236 + "i" (op));
4237 +
4238 +#endif /* !_LANGUAGE_ASSEMBLY */
4239 +
4240 +#endif /* _MISPINC_H */
4241 diff -urN linux.old/arch/mips/bcm947xx/include/nvports.h linux.dev/arch/mips/bcm947xx/include/nvports.h
4242 --- linux.old/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4243 +++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-11-07 21:57:07.865587000 +0100
4244 @@ -0,0 +1,55 @@
4245 +/*
4246 + * BCM53xx RoboSwitch utility functions
4247 + *
4248 + * Copyright (C) 2002 Broadcom Corporation
4249 + * $Id$
4250 + */
4251 +
4252 +#ifndef _nvports_h_
4253 +#define _nvports_h_
4254 +
4255 +#define uint32 unsigned long
4256 +#define uint16 unsigned short
4257 +#define uint unsigned int
4258 +#define uint8 unsigned char
4259 +#define uint64 unsigned long long
4260 +
4261 +enum FORCE_PORT {
4262 + FORCE_OFF,
4263 + FORCE_10H,
4264 + FORCE_10F,
4265 + FORCE_100H,
4266 + FORCE_100F,
4267 + FORCE_DOWN,
4268 + POWER_OFF
4269 +};
4270 +
4271 +typedef struct _PORT_ATTRIBS
4272 +{
4273 + uint autoneg;
4274 + uint force;
4275 + uint native;
4276 +} PORT_ATTRIBS;
4277 +
4278 +extern uint
4279 +nvExistsPortAttrib(char *attrib, uint portno);
4280 +
4281 +extern int
4282 +nvExistsAnyForcePortAttrib(uint portno);
4283 +
4284 +extern void
4285 +nvSetPortAttrib(char *attrib, uint portno);
4286 +
4287 +extern void
4288 +nvUnsetPortAttrib(char *attrib, uint portno);
4289 +
4290 +extern void
4291 +nvUnsetAllForcePortAttrib(uint portno);
4292 +
4293 +extern PORT_ATTRIBS
4294 +nvGetSwitchPortAttribs(uint portno);
4295 +
4296 +#endif /* _nvports_h_ */
4297 +
4298 +
4299 +
4300 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
4301 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4302 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-11-07 22:51:38.780726250 +0100
4303 @@ -0,0 +1,42 @@
4304 +/*
4305 + * OS Abstraction Layer
4306 + *
4307 + * Copyright 2005, Broadcom Corporation
4308 + * All Rights Reserved.
4309 + *
4310 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4311 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4312 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4313 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4314 + * $Id$
4315 + */
4316 +
4317 +#ifndef _osl_h_
4318 +#define _osl_h_
4319 +
4320 +/* osl handle type forward declaration */
4321 +typedef struct os_handle osl_t;
4322 +
4323 +#if defined(linux)
4324 +#include <linux_osl.h>
4325 +#elif defined(NDIS)
4326 +#include <ndis_osl.h>
4327 +#elif defined(_CFE_)
4328 +#include <cfe_osl.h>
4329 +#elif defined(_HNDRTE_)
4330 +#include <hndrte_osl.h>
4331 +#elif defined(_MINOSL_)
4332 +#include <min_osl.h>
4333 +#elif PMON
4334 +#include <pmon_osl.h>
4335 +#elif defined(MACOSX)
4336 +#include <macosx_osl.h>
4337 +#else
4338 +#error "Unsupported OSL requested"
4339 +#endif
4340 +
4341 +/* handy */
4342 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4343 +#define MAXPRIO 7 /* 0-7 */
4344 +
4345 +#endif /* _osl_h_ */
4346 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
4347 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4348 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-11-07 22:51:38.780726250 +0100
4349 @@ -0,0 +1,451 @@
4350 +/*
4351 + * pcicfg.h: PCI configuration constants and structures.
4352 + *
4353 + * Copyright 2005, Broadcom Corporation
4354 + * All Rights Reserved.
4355 + *
4356 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4357 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4358 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4359 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4360 + *
4361 + * $Id$
4362 + */
4363 +
4364 +#ifndef _h_pci_
4365 +#define _h_pci_
4366 +
4367 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4368 +#ifndef PCI_MAX_BUS
4369 +#define PCI_MAX_BUS 0x100
4370 +#endif
4371 +#ifndef PCI_MAX_DEVICES
4372 +#define PCI_MAX_DEVICES 0x20
4373 +#endif
4374 +#ifndef PCI_MAX_FUNCTION
4375 +#define PCI_MAX_FUNCTION 0x8
4376 +#endif
4377 +
4378 +#ifndef PCI_INVALID_VENDORID
4379 +#define PCI_INVALID_VENDORID 0xffff
4380 +#endif
4381 +#ifndef PCI_INVALID_DEVICEID
4382 +#define PCI_INVALID_DEVICEID 0xffff
4383 +#endif
4384 +
4385 +
4386 +/* Convert between bus-slot-function-register and config addresses */
4387 +
4388 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4389 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4390 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4391 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
4392 +
4393 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4394 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4395 +#define PCICFG_FUN_MASK 7 /* Function mask */
4396 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4397 +
4398 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4399 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4400 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4401 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4402 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4403 +
4404 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4405 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4406 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4407 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4408 +
4409 +/* PCIE Config space accessing MACROS*/
4410 +
4411 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
4412 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
4413 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
4414 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
4415 +
4416 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
4417 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
4418 +#define PCIECFG_FUN_MASK 7 /* Function mask */
4419 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
4420 +
4421 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
4422 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
4423 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
4424 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
4425 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
4426 +
4427 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
4428 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
4429 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
4430 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
4431 +
4432 +
4433 +/* The actual config space */
4434 +
4435 +#define PCI_BAR_MAX 6
4436 +
4437 +#define PCI_ROM_BAR 8
4438 +
4439 +#define PCR_RSVDA_MAX 2
4440 +
4441 +/* pci config status reg has a bit to indicate that capability ptr is present*/
4442 +
4443 +#define PCI_CAPPTR_PRESENT 0x0010
4444 +
4445 +typedef struct _pci_config_regs {
4446 + unsigned short vendor;
4447 + unsigned short device;
4448 + unsigned short command;
4449 + unsigned short status;
4450 + unsigned char rev_id;
4451 + unsigned char prog_if;
4452 + unsigned char sub_class;
4453 + unsigned char base_class;
4454 + unsigned char cache_line_size;
4455 + unsigned char latency_timer;
4456 + unsigned char header_type;
4457 + unsigned char bist;
4458 + unsigned long base[PCI_BAR_MAX];
4459 + unsigned long cardbus_cis;
4460 + unsigned short subsys_vendor;
4461 + unsigned short subsys_id;
4462 + unsigned long baserom;
4463 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4464 + unsigned char int_line;
4465 + unsigned char int_pin;
4466 + unsigned char min_gnt;
4467 + unsigned char max_lat;
4468 + unsigned char dev_dep[192];
4469 +} pci_config_regs;
4470 +
4471 +#define SZPCR (sizeof (pci_config_regs))
4472 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4473 +
4474 +/* A structure for the config registers is nice, but in most
4475 + * systems the config space is not memory mapped, so we need
4476 + * filed offsetts. :-(
4477 + */
4478 +#define PCI_CFG_VID 0
4479 +#define PCI_CFG_DID 2
4480 +#define PCI_CFG_CMD 4
4481 +#define PCI_CFG_STAT 6
4482 +#define PCI_CFG_REV 8
4483 +#define PCI_CFG_PROGIF 9
4484 +#define PCI_CFG_SUBCL 0xa
4485 +#define PCI_CFG_BASECL 0xb
4486 +#define PCI_CFG_CLSZ 0xc
4487 +#define PCI_CFG_LATTIM 0xd
4488 +#define PCI_CFG_HDR 0xe
4489 +#define PCI_CFG_BIST 0xf
4490 +#define PCI_CFG_BAR0 0x10
4491 +#define PCI_CFG_BAR1 0x14
4492 +#define PCI_CFG_BAR2 0x18
4493 +#define PCI_CFG_BAR3 0x1c
4494 +#define PCI_CFG_BAR4 0x20
4495 +#define PCI_CFG_BAR5 0x24
4496 +#define PCI_CFG_CIS 0x28
4497 +#define PCI_CFG_SVID 0x2c
4498 +#define PCI_CFG_SSID 0x2e
4499 +#define PCI_CFG_ROMBAR 0x30
4500 +#define PCI_CFG_CAPPTR 0x34
4501 +#define PCI_CFG_INT 0x3c
4502 +#define PCI_CFG_PIN 0x3d
4503 +#define PCI_CFG_MINGNT 0x3e
4504 +#define PCI_CFG_MAXLAT 0x3f
4505 +
4506 +/* Classes and subclasses */
4507 +
4508 +typedef enum {
4509 + PCI_CLASS_OLD = 0,
4510 + PCI_CLASS_DASDI,
4511 + PCI_CLASS_NET,
4512 + PCI_CLASS_DISPLAY,
4513 + PCI_CLASS_MMEDIA,
4514 + PCI_CLASS_MEMORY,
4515 + PCI_CLASS_BRIDGE,
4516 + PCI_CLASS_COMM,
4517 + PCI_CLASS_BASE,
4518 + PCI_CLASS_INPUT,
4519 + PCI_CLASS_DOCK,
4520 + PCI_CLASS_CPU,
4521 + PCI_CLASS_SERIAL,
4522 + PCI_CLASS_INTELLIGENT = 0xe,
4523 + PCI_CLASS_SATELLITE,
4524 + PCI_CLASS_CRYPT,
4525 + PCI_CLASS_DSP,
4526 + PCI_CLASS_MAX
4527 +} pci_classes;
4528 +
4529 +typedef enum {
4530 + PCI_DASDI_SCSI,
4531 + PCI_DASDI_IDE,
4532 + PCI_DASDI_FLOPPY,
4533 + PCI_DASDI_IPI,
4534 + PCI_DASDI_RAID,
4535 + PCI_DASDI_OTHER = 0x80
4536 +} pci_dasdi_subclasses;
4537 +
4538 +typedef enum {
4539 + PCI_NET_ETHER,
4540 + PCI_NET_TOKEN,
4541 + PCI_NET_FDDI,
4542 + PCI_NET_ATM,
4543 + PCI_NET_OTHER = 0x80
4544 +} pci_net_subclasses;
4545 +
4546 +typedef enum {
4547 + PCI_DISPLAY_VGA,
4548 + PCI_DISPLAY_XGA,
4549 + PCI_DISPLAY_3D,
4550 + PCI_DISPLAY_OTHER = 0x80
4551 +} pci_display_subclasses;
4552 +
4553 +typedef enum {
4554 + PCI_MMEDIA_VIDEO,
4555 + PCI_MMEDIA_AUDIO,
4556 + PCI_MMEDIA_PHONE,
4557 + PCI_MEDIA_OTHER = 0x80
4558 +} pci_mmedia_subclasses;
4559 +
4560 +typedef enum {
4561 + PCI_MEMORY_RAM,
4562 + PCI_MEMORY_FLASH,
4563 + PCI_MEMORY_OTHER = 0x80
4564 +} pci_memory_subclasses;
4565 +
4566 +typedef enum {
4567 + PCI_BRIDGE_HOST,
4568 + PCI_BRIDGE_ISA,
4569 + PCI_BRIDGE_EISA,
4570 + PCI_BRIDGE_MC,
4571 + PCI_BRIDGE_PCI,
4572 + PCI_BRIDGE_PCMCIA,
4573 + PCI_BRIDGE_NUBUS,
4574 + PCI_BRIDGE_CARDBUS,
4575 + PCI_BRIDGE_RACEWAY,
4576 + PCI_BRIDGE_OTHER = 0x80
4577 +} pci_bridge_subclasses;
4578 +
4579 +typedef enum {
4580 + PCI_COMM_UART,
4581 + PCI_COMM_PARALLEL,
4582 + PCI_COMM_MULTIUART,
4583 + PCI_COMM_MODEM,
4584 + PCI_COMM_OTHER = 0x80
4585 +} pci_comm_subclasses;
4586 +
4587 +typedef enum {
4588 + PCI_BASE_PIC,
4589 + PCI_BASE_DMA,
4590 + PCI_BASE_TIMER,
4591 + PCI_BASE_RTC,
4592 + PCI_BASE_PCI_HOTPLUG,
4593 + PCI_BASE_OTHER = 0x80
4594 +} pci_base_subclasses;
4595 +
4596 +typedef enum {
4597 + PCI_INPUT_KBD,
4598 + PCI_INPUT_PEN,
4599 + PCI_INPUT_MOUSE,
4600 + PCI_INPUT_SCANNER,
4601 + PCI_INPUT_GAMEPORT,
4602 + PCI_INPUT_OTHER = 0x80
4603 +} pci_input_subclasses;
4604 +
4605 +typedef enum {
4606 + PCI_DOCK_GENERIC,
4607 + PCI_DOCK_OTHER = 0x80
4608 +} pci_dock_subclasses;
4609 +
4610 +typedef enum {
4611 + PCI_CPU_386,
4612 + PCI_CPU_486,
4613 + PCI_CPU_PENTIUM,
4614 + PCI_CPU_ALPHA = 0x10,
4615 + PCI_CPU_POWERPC = 0x20,
4616 + PCI_CPU_MIPS = 0x30,
4617 + PCI_CPU_COPROC = 0x40,
4618 + PCI_CPU_OTHER = 0x80
4619 +} pci_cpu_subclasses;
4620 +
4621 +typedef enum {
4622 + PCI_SERIAL_IEEE1394,
4623 + PCI_SERIAL_ACCESS,
4624 + PCI_SERIAL_SSA,
4625 + PCI_SERIAL_USB,
4626 + PCI_SERIAL_FIBER,
4627 + PCI_SERIAL_SMBUS,
4628 + PCI_SERIAL_OTHER = 0x80
4629 +} pci_serial_subclasses;
4630 +
4631 +typedef enum {
4632 + PCI_INTELLIGENT_I2O,
4633 +} pci_intelligent_subclasses;
4634 +
4635 +typedef enum {
4636 + PCI_SATELLITE_TV,
4637 + PCI_SATELLITE_AUDIO,
4638 + PCI_SATELLITE_VOICE,
4639 + PCI_SATELLITE_DATA,
4640 + PCI_SATELLITE_OTHER = 0x80
4641 +} pci_satellite_subclasses;
4642 +
4643 +typedef enum {
4644 + PCI_CRYPT_NETWORK,
4645 + PCI_CRYPT_ENTERTAINMENT,
4646 + PCI_CRYPT_OTHER = 0x80
4647 +} pci_crypt_subclasses;
4648 +
4649 +typedef enum {
4650 + PCI_DSP_DPIO,
4651 + PCI_DSP_OTHER = 0x80
4652 +} pci_dsp_subclasses;
4653 +
4654 +/* Header types */
4655 +typedef enum {
4656 + PCI_HEADER_NORMAL,
4657 + PCI_HEADER_BRIDGE,
4658 + PCI_HEADER_CARDBUS
4659 +} pci_header_types;
4660 +
4661 +
4662 +/* Overlay for a PCI-to-PCI bridge */
4663 +
4664 +#define PPB_RSVDA_MAX 2
4665 +#define PPB_RSVDD_MAX 8
4666 +
4667 +typedef struct _ppb_config_regs {
4668 + unsigned short vendor;
4669 + unsigned short device;
4670 + unsigned short command;
4671 + unsigned short status;
4672 + unsigned char rev_id;
4673 + unsigned char prog_if;
4674 + unsigned char sub_class;
4675 + unsigned char base_class;
4676 + unsigned char cache_line_size;
4677 + unsigned char latency_timer;
4678 + unsigned char header_type;
4679 + unsigned char bist;
4680 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4681 + unsigned char prim_bus;
4682 + unsigned char sec_bus;
4683 + unsigned char sub_bus;
4684 + unsigned char sec_lat;
4685 + unsigned char io_base;
4686 + unsigned char io_lim;
4687 + unsigned short sec_status;
4688 + unsigned short mem_base;
4689 + unsigned short mem_lim;
4690 + unsigned short pf_mem_base;
4691 + unsigned short pf_mem_lim;
4692 + unsigned long pf_mem_base_hi;
4693 + unsigned long pf_mem_lim_hi;
4694 + unsigned short io_base_hi;
4695 + unsigned short io_lim_hi;
4696 + unsigned short subsys_vendor;
4697 + unsigned short subsys_id;
4698 + unsigned long rsvd_b;
4699 + unsigned char rsvd_c;
4700 + unsigned char int_pin;
4701 + unsigned short bridge_ctrl;
4702 + unsigned char chip_ctrl;
4703 + unsigned char diag_ctrl;
4704 + unsigned short arb_ctrl;
4705 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4706 + unsigned char dev_dep[192];
4707 +} ppb_config_regs;
4708 +
4709 +
4710 +/* PCI CAPABILITY DEFINES */
4711 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
4712 +#define PCI_CAP_MSICAP_ID 0x05
4713 +#define PCI_CAP_PCIECAP_ID 0x10
4714 +
4715 +/* Data structure to define the Message Signalled Interrupt facility
4716 + * Valid for PCI and PCIE configurations */
4717 +typedef struct _pciconfig_cap_msi {
4718 + unsigned char capID;
4719 + unsigned char nextptr;
4720 + unsigned short msgctrl;
4721 + unsigned int msgaddr;
4722 +} pciconfig_cap_msi;
4723 +
4724 +/* Data structure to define the Power managment facility
4725 + * Valid for PCI and PCIE configurations */
4726 +typedef struct _pciconfig_cap_pwrmgmt {
4727 + unsigned char capID;
4728 + unsigned char nextptr;
4729 + unsigned short pme_cap;
4730 + unsigned short pme_sts_ctrl;
4731 + unsigned char pme_bridge_ext;
4732 + unsigned char data;
4733 +} pciconfig_cap_pwrmgmt;
4734 +
4735 +/* Data structure to define the PCIE capability */
4736 +typedef struct _pciconfig_cap_pcie {
4737 + unsigned char capID;
4738 + unsigned char nextptr;
4739 + unsigned short pcie_cap;
4740 + unsigned int dev_cap;
4741 + unsigned short dev_ctrl;
4742 + unsigned short dev_status;
4743 + unsigned int link_cap;
4744 + unsigned short link_ctrl;
4745 + unsigned short link_status;
4746 +} pciconfig_cap_pcie;
4747 +
4748 +/* PCIE Enhanced CAPABILITY DEFINES */
4749 +#define PCIE_EXTCFG_OFFSET 0x100
4750 +#define PCIE_ADVERRREP_CAPID 0x0001
4751 +#define PCIE_VC_CAPID 0x0002
4752 +#define PCIE_DEVSNUM_CAPID 0x0003
4753 +#define PCIE_PWRBUDGET_CAPID 0x0004
4754 +
4755 +/* Header to define the PCIE specific capabilities in the extended config space */
4756 +typedef struct _pcie_enhanced_caphdr {
4757 + unsigned short capID;
4758 + unsigned short cap_ver : 4;
4759 + unsigned short next_ptr : 12;
4760 +} pcie_enhanced_caphdr;
4761 +
4762 +
4763 +/* Everything below is BRCM HND proprietary */
4764 +
4765 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4766 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4767 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4768 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4769 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4770 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4771 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4772 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4773 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4774 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4775 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4776 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4777 +
4778 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4779 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4780 +
4781 +/* PCI_INT_STATUS */
4782 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4783 +
4784 +/* PCI_INT_MASK */
4785 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4786 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4787 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4788 +
4789 +/* PCI_SPROM_CONTROL */
4790 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4791 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4792 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4793 +
4794 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4795 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4796 +
4797 +/* PCI_CFG_CMD_STAT */
4798 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4799 +
4800 +#endif
4801 diff -urN linux.old/arch/mips/bcm947xx/include/pmon_osl.h linux.dev/arch/mips/bcm947xx/include/pmon_osl.h
4802 --- linux.old/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4803 +++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-11-07 21:57:07.869587250 +0100
4804 @@ -0,0 +1,126 @@
4805 +/*
4806 + * MIPS PMON boot loader OS Abstraction Layer.
4807 + *
4808 + * Copyright 2005, Broadcom Corporation
4809 + * All Rights Reserved.
4810 + *
4811 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
4812 + * the contents of this file may not be disclosed to third parties, copied
4813 + * or duplicated in any form, in whole or in part, without the prior
4814 + * written permission of Broadcom Corporation.
4815 + * $Id$
4816 + */
4817 +
4818 +#ifndef _pmon_osl_h_
4819 +#define _pmon_osl_h_
4820 +
4821 +#include <typedefs.h>
4822 +#include <mips.h>
4823 +#include <string.h>
4824 +#include <utypes.h>
4825 +
4826 +extern int printf(char *fmt,...);
4827 +extern int sprintf(char *dst,char *fmt,...);
4828 +
4829 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
4830 +#define REG_MAP(pa, size) phy2k1((pa))
4831 +#define REG_UNMAP(va) /* nop */
4832 +
4833 +/* Common macros */
4834 +
4835 +#define BUSPROBE(val, addr) ((val) = *(addr))
4836 +
4837 +#define ASSERT(exp)
4838 +
4839 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
4840 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
4841 +
4842 +/* kludge */
4843 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
4844 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
4845 +
4846 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
4847 +#define rreg32(r) (*(volatile uint32 *)(r))
4848 +#ifdef IL_BIGENDIAN
4849 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
4850 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
4851 +#else
4852 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
4853 +#define rreg16(r) (*(volatile uint16 *)(r))
4854 +#endif
4855 +
4856 +#include <memory.h>
4857 +#define bcopy(src, dst, len) memcpy(dst, src, len)
4858 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
4859 +#define bzero(b, len) memset(b, '\0', len)
4860 +
4861 +/* register access macros */
4862 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
4863 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
4864 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
4865 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
4866 +
4867 +#define R_SM(r) *(r)
4868 +#define W_SM(r, v) (*(r) = (v))
4869 +#define BZERO_SM(r, len) memset(r, '\0', len)
4870 +
4871 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
4872 +#define BUS_SWAP32(v) (v)
4873 +
4874 +#define OSL_DELAY(usec) delay_us(usec)
4875 +extern void delay_us(uint usec);
4876 +
4877 +#define OSL_GETCYCLES(x) ((x) = 0)
4878 +
4879 +#define osl_attach(pdev) (pdev)
4880 +#define osl_detach(osh)
4881 +
4882 +#define MALLOC(osh, size) malloc(size)
4883 +#define MFREE(osh, addr, size) free(addr)
4884 +#define MALLOCED(osh) (0)
4885 +#define MALLOC_DUMP(osh, buf, sz)
4886 +#define MALLOC_FAILED(osh)
4887 +extern void *malloc();
4888 +extern void free(void *addr);
4889 +
4890 +#define DMA_CONSISTENT_ALIGN sizeof (int)
4891 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
4892 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
4893 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
4894 +#define DMA_TX 0
4895 +#define DMA_RX 1
4896 +
4897 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
4898 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
4899 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
4900 +
4901 +struct lbuf {
4902 + struct lbuf *next; /* pointer to next lbuf on freelist */
4903 + uchar *buf; /* pointer to buffer */
4904 + uint len; /* nbytes of data */
4905 +};
4906 +
4907 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
4908 +#define PKTBUFSZ 2048
4909 +
4910 +/* packet primitives */
4911 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
4912 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
4913 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
4914 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
4915 +#define PKTHEADROOM(drv, lb) (0)
4916 +#define PKTTAILROOM(drv, lb) (0)
4917 +#define PKTNEXT(drv, lb) NULL
4918 +#define PKTSETNEXT(lb, x) ASSERT(0)
4919 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
4920 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
4921 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
4922 +#define PKTDUP(drv, lb) ASSERT(0)
4923 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
4924 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
4925 +#define PKTPRIO(lb) (0)
4926 +#define PKTSETPRIO(lb, x) do {} while (0)
4927 +extern void *et_pktget(void *drv, uint len, bool send);
4928 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
4929 +
4930 +#endif /* _pmon_osl_h_ */
4931 diff -urN linux.old/arch/mips/bcm947xx/include/proto/802.11.h linux.dev/arch/mips/bcm947xx/include/proto/802.11.h
4932 --- linux.old/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
4933 +++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-11-07 22:51:38.784726500 +0100
4934 @@ -0,0 +1,930 @@
4935 +/*
4936 + * Copyright 2005, Broadcom Corporation
4937 + * All Rights Reserved.
4938 + *
4939 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4940 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4941 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4942 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4943 + *
4944 + * Fundamental types and constants relating to 802.11
4945 + *
4946 + * $Id$
4947 + */
4948 +
4949 +#ifndef _802_11_H_
4950 +#define _802_11_H_
4951 +
4952 +#ifndef _TYPEDEFS_H_
4953 +#include <typedefs.h>
4954 +#endif
4955 +
4956 +#ifndef _NET_ETHERNET_H_
4957 +#include <proto/ethernet.h>
4958 +#endif
4959 +
4960 +#include <proto/wpa.h>
4961 +
4962 +
4963 +/* enable structure packing */
4964 +#if defined(__GNUC__)
4965 +#define PACKED __attribute__((packed))
4966 +#else
4967 +#pragma pack(1)
4968 +#define PACKED
4969 +#endif
4970 +
4971 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
4972 +
4973 +/* Generic 802.11 frame constants */
4974 +#define DOT11_A3_HDR_LEN 24
4975 +#define DOT11_A4_HDR_LEN 30
4976 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
4977 +#define DOT11_FCS_LEN 4
4978 +#define DOT11_ICV_LEN 4
4979 +#define DOT11_ICV_AES_LEN 8
4980 +#define DOT11_QOS_LEN 2
4981 +
4982 +#define DOT11_KEY_INDEX_SHIFT 6
4983 +#define DOT11_IV_LEN 4
4984 +#define DOT11_IV_TKIP_LEN 8
4985 +#define DOT11_IV_AES_OCB_LEN 4
4986 +#define DOT11_IV_AES_CCM_LEN 8
4987 +
4988 +/* Includes MIC */
4989 +#define DOT11_MAX_MPDU_BODY_LEN 2304
4990 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
4991 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
4992 + DOT11_QOS_LEN + \
4993 + DOT11_IV_AES_CCM_LEN + \
4994 + DOT11_MAX_MPDU_BODY_LEN + \
4995 + DOT11_ICV_LEN + \
4996 + DOT11_FCS_LEN)
4997 +
4998 +#define DOT11_MAX_SSID_LEN 32
4999 +
5000 +/* dot11RTSThreshold */
5001 +#define DOT11_DEFAULT_RTS_LEN 2347
5002 +#define DOT11_MAX_RTS_LEN 2347
5003 +
5004 +/* dot11FragmentationThreshold */
5005 +#define DOT11_MIN_FRAG_LEN 256
5006 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
5007 +#define DOT11_DEFAULT_FRAG_LEN 2346
5008 +
5009 +/* dot11BeaconPeriod */
5010 +#define DOT11_MIN_BEACON_PERIOD 1
5011 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
5012 +
5013 +/* dot11DTIMPeriod */
5014 +#define DOT11_MIN_DTIM_PERIOD 1
5015 +#define DOT11_MAX_DTIM_PERIOD 0xFF
5016 +
5017 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
5018 +#define DOT11_LLC_SNAP_HDR_LEN 8
5019 +#define DOT11_OUI_LEN 3
5020 +struct dot11_llc_snap_header {
5021 + uint8 dsap; /* always 0xAA */
5022 + uint8 ssap; /* always 0xAA */
5023 + uint8 ctl; /* always 0x03 */
5024 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
5025 + Bridge-Tunnel: 0x00 0x00 0xF8 */
5026 + uint16 type; /* ethertype */
5027 +} PACKED;
5028 +
5029 +/* RFC1042 header used by 802.11 per 802.1H */
5030 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
5031 +
5032 +/* Generic 802.11 MAC header */
5033 +/*
5034 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
5035 + * The fields are defined such that the shorter 1, 2, and 3
5036 + * address headers just use the first k fields.
5037 + */
5038 +struct dot11_header {
5039 + uint16 fc; /* frame control */
5040 + uint16 durid; /* duration/ID */
5041 + struct ether_addr a1; /* address 1 */
5042 + struct ether_addr a2; /* address 2 */
5043 + struct ether_addr a3; /* address 3 */
5044 + uint16 seq; /* sequence control */
5045 + struct ether_addr a4; /* address 4 */
5046 +} PACKED;
5047 +
5048 +/* Control frames */
5049 +
5050 +struct dot11_rts_frame {
5051 + uint16 fc; /* frame control */
5052 + uint16 durid; /* duration/ID */
5053 + struct ether_addr ra; /* receiver address */
5054 + struct ether_addr ta; /* transmitter address */
5055 +} PACKED;
5056 +#define DOT11_RTS_LEN 16
5057 +
5058 +struct dot11_cts_frame {
5059 + uint16 fc; /* frame control */
5060 + uint16 durid; /* duration/ID */
5061 + struct ether_addr ra; /* receiver address */
5062 +} PACKED;
5063 +#define DOT11_CTS_LEN 10
5064 +
5065 +struct dot11_ack_frame {
5066 + uint16 fc; /* frame control */
5067 + uint16 durid; /* duration/ID */
5068 + struct ether_addr ra; /* receiver address */
5069 +} PACKED;
5070 +#define DOT11_ACK_LEN 10
5071 +
5072 +struct dot11_ps_poll_frame {
5073 + uint16 fc; /* frame control */
5074 + uint16 durid; /* AID */
5075 + struct ether_addr bssid; /* receiver address, STA in AP */
5076 + struct ether_addr ta; /* transmitter address */
5077 +} PACKED;
5078 +#define DOT11_PS_POLL_LEN 16
5079 +
5080 +struct dot11_cf_end_frame {
5081 + uint16 fc; /* frame control */
5082 + uint16 durid; /* duration/ID */
5083 + struct ether_addr ra; /* receiver address */
5084 + struct ether_addr bssid; /* transmitter address, STA in AP */
5085 +} PACKED;
5086 +#define DOT11_CS_END_LEN 16
5087 +
5088 +/* Management frame header */
5089 +struct dot11_management_header {
5090 + uint16 fc; /* frame control */
5091 + uint16 durid; /* duration/ID */
5092 + struct ether_addr da; /* receiver address */
5093 + struct ether_addr sa; /* transmitter address */
5094 + struct ether_addr bssid; /* BSS ID */
5095 + uint16 seq; /* sequence control */
5096 +} PACKED;
5097 +#define DOT11_MGMT_HDR_LEN 24
5098 +
5099 +/* Management frame payloads */
5100 +
5101 +struct dot11_bcn_prb {
5102 + uint32 timestamp[2];
5103 + uint16 beacon_interval;
5104 + uint16 capability;
5105 +} PACKED;
5106 +#define DOT11_BCN_PRB_LEN 12
5107 +
5108 +struct dot11_auth {
5109 + uint16 alg; /* algorithm */
5110 + uint16 seq; /* sequence control */
5111 + uint16 status; /* status code */
5112 +} PACKED;
5113 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
5114 +
5115 +struct dot11_assoc_req {
5116 + uint16 capability; /* capability information */
5117 + uint16 listen; /* listen interval */
5118 +} PACKED;
5119 +#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
5120 +
5121 +struct dot11_reassoc_req {
5122 + uint16 capability; /* capability information */
5123 + uint16 listen; /* listen interval */
5124 + struct ether_addr ap; /* Current AP address */
5125 +} PACKED;
5126 +#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
5127 +
5128 +struct dot11_assoc_resp {
5129 + uint16 capability; /* capability information */
5130 + uint16 status; /* status code */
5131 + uint16 aid; /* association ID */
5132 +} PACKED;
5133 +
5134 +struct dot11_action_measure {
5135 + uint8 category;
5136 + uint8 action;
5137 + uint8 token;
5138 + uint8 data[1];
5139 +} PACKED;
5140 +#define DOT11_ACTION_MEASURE_LEN 3
5141 +
5142 +struct dot11_action_switch_channel {
5143 + uint8 category;
5144 + uint8 action;
5145 + uint8 data[5]; /* for switch IE */
5146 +} PACKED;
5147 +
5148 +/**************
5149 + 802.11h related definitions.
5150 +**************/
5151 +typedef struct {
5152 + uint8 id;
5153 + uint8 len;
5154 + uint8 power;
5155 +} dot11_power_cnst_t;
5156 +
5157 +typedef struct {
5158 + uint8 min;
5159 + uint8 max;
5160 +} dot11_power_cap_t;
5161 +
5162 +typedef struct {
5163 + uint8 id;
5164 + uint8 len;
5165 + uint8 tx_pwr;
5166 + uint8 margin;
5167 +} dot11_tpc_rep_t;
5168 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
5169 +
5170 +typedef struct {
5171 + uint8 id;
5172 + uint8 len;
5173 + uint8 first_channel;
5174 + uint8 num_channels;
5175 +} dot11_supp_channels_t;
5176 +
5177 +/* csa mode type */
5178 +#define DOT11_CSA_MODE_ADVISORY 0
5179 +#define DOT11_CSA_MODE_NO_TX 1
5180 +struct dot11_channel_switch {
5181 + uint8 id;
5182 + uint8 len;
5183 + uint8 mode;
5184 + uint8 channel;
5185 + uint8 count;
5186 +} PACKED;
5187 +typedef struct dot11_channel_switch dot11_channel_switch_t;
5188 +
5189 +/* length of IE data, not including 2 byte header */
5190 +#define DOT11_SWITCH_IE_LEN 3
5191 +
5192 +/* 802.11h Measurement Request/Report IEs */
5193 +/* Measurement Type field */
5194 +#define DOT11_MEASURE_TYPE_BASIC 0
5195 +#define DOT11_MEASURE_TYPE_CCA 1
5196 +#define DOT11_MEASURE_TYPE_RPI 2
5197 +
5198 +/* Measurement Mode field */
5199 +
5200 +/* Measurement Request Modes */
5201 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
5202 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
5203 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
5204 +/* Measurement Report Modes */
5205 +#define DOT11_MEASURE_MODE_LATE (1<<0)
5206 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
5207 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
5208 +/* Basic Measurement Map bits */
5209 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
5210 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
5211 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
5212 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
5213 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
5214 +
5215 +typedef struct {
5216 + uint8 id;
5217 + uint8 len;
5218 + uint8 token;
5219 + uint8 mode;
5220 + uint8 type;
5221 + uint8 channel;
5222 + uint8 start_time[8];
5223 + uint16 duration;
5224 +} dot11_meas_req_t;
5225 +#define DOT11_MNG_IE_MREQ_LEN 14
5226 +/* length of Measure Request IE data not including variable len */
5227 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5228 +
5229 +struct dot11_meas_rep {
5230 + uint8 id;
5231 + uint8 len;
5232 + uint8 token;
5233 + uint8 mode;
5234 + uint8 type;
5235 + union
5236 + {
5237 + struct {
5238 + uint8 channel;
5239 + uint8 start_time[8];
5240 + uint16 duration;
5241 + uint8 map;
5242 + } PACKED basic;
5243 + uint8 data[1];
5244 + } PACKED rep;
5245 +} PACKED;
5246 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5247 +
5248 +/* length of Measure Report IE data not including variable len */
5249 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5250 +
5251 +struct dot11_meas_rep_basic {
5252 + uint8 channel;
5253 + uint8 start_time[8];
5254 + uint16 duration;
5255 + uint8 map;
5256 +} PACKED;
5257 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5258 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5259 +
5260 +struct dot11_quiet {
5261 + uint8 id;
5262 + uint8 len;
5263 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5264 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5265 + uint16 duration;/* Length of quiet period, in TU's */
5266 + uint16 offset; /* TU's offset from TBTT in Count field */
5267 +} PACKED;
5268 +typedef struct dot11_quiet dot11_quiet_t;
5269 +
5270 +typedef struct {
5271 + uint8 channel;
5272 + uint8 map;
5273 +} chan_map_tuple_t;
5274 +
5275 +typedef struct {
5276 + uint8 id;
5277 + uint8 len;
5278 + uint8 eaddr[ETHER_ADDR_LEN];
5279 + uint8 interval;
5280 + chan_map_tuple_t map[1];
5281 +} dot11_ibss_dfs_t;
5282 +
5283 +/* WME Elements */
5284 +#define WME_OUI "\x00\x50\xf2"
5285 +#define WME_VER 1
5286 +#define WME_TYPE 2
5287 +#define WME_SUBTYPE_IE 0 /* Information Element */
5288 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5289 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5290 +
5291 +/* WME Access Category Indices (ACIs) */
5292 +#define AC_BE 0 /* Best Effort */
5293 +#define AC_BK 1 /* Background */
5294 +#define AC_VI 2 /* Video */
5295 +#define AC_VO 3 /* Voice */
5296 +#define AC_MAX 4
5297 +
5298 +/* WME Information Element (IE) */
5299 +struct wme_ie {
5300 + uint8 oui[3];
5301 + uint8 type;
5302 + uint8 subtype;
5303 + uint8 version;
5304 + uint8 acinfo;
5305 +} PACKED;
5306 +typedef struct wme_ie wme_ie_t;
5307 +#define WME_IE_LEN 7
5308 +
5309 +struct wme_acparam {
5310 + uint8 ACI;
5311 + uint8 ECW;
5312 + uint16 TXOP; /* stored in network order (ls octet first) */
5313 +} PACKED;
5314 +typedef struct wme_acparam wme_acparam_t;
5315 +
5316 +/* WME Parameter Element (PE) */
5317 +struct wme_params {
5318 + uint8 oui[3];
5319 + uint8 type;
5320 + uint8 subtype;
5321 + uint8 version;
5322 + uint8 acinfo;
5323 + uint8 rsvd;
5324 + wme_acparam_t acparam[4];
5325 +} PACKED;
5326 +typedef struct wme_params wme_params_t;
5327 +#define WME_PARAMS_IE_LEN 24
5328 +
5329 +/* acinfo */
5330 +#define WME_COUNT_MASK 0x0f
5331 +/* ACI */
5332 +#define WME_AIFS_MASK 0x0f
5333 +#define WME_ACM_MASK 0x10
5334 +#define WME_ACI_MASK 0x60
5335 +#define WME_ACI_SHIFT 5
5336 +/* ECW */
5337 +#define WME_CWMIN_MASK 0x0f
5338 +#define WME_CWMAX_MASK 0xf0
5339 +#define WME_CWMAX_SHIFT 4
5340 +
5341 +#define WME_TXOP_UNITS 32
5342 +
5343 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5344 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5345 +#define WME_AC_BK_ACI_STA 0x27
5346 +#define WME_AC_BK_ECW_STA 0xA4
5347 +#define WME_AC_BK_TXOP_STA 0x0000
5348 +#define WME_AC_BE_ACI_STA 0x03
5349 +#define WME_AC_BE_ECW_STA 0xA4
5350 +#define WME_AC_BE_TXOP_STA 0x0000
5351 +#define WME_AC_VI_ACI_STA 0x42
5352 +#define WME_AC_VI_ECW_STA 0x43
5353 +#define WME_AC_VI_TXOP_STA 0x005e
5354 +#define WME_AC_VO_ACI_STA 0x62
5355 +#define WME_AC_VO_ECW_STA 0x32
5356 +#define WME_AC_VO_TXOP_STA 0x002f
5357 +
5358 +#define WME_AC_BK_ACI_AP 0x27
5359 +#define WME_AC_BK_ECW_AP 0xA4
5360 +#define WME_AC_BK_TXOP_AP 0x0000
5361 +#define WME_AC_BE_ACI_AP 0x03
5362 +#define WME_AC_BE_ECW_AP 0x64
5363 +#define WME_AC_BE_TXOP_AP 0x0000
5364 +#define WME_AC_VI_ACI_AP 0x41
5365 +#define WME_AC_VI_ECW_AP 0x43
5366 +#define WME_AC_VI_TXOP_AP 0x005e
5367 +#define WME_AC_VO_ACI_AP 0x61
5368 +#define WME_AC_VO_ECW_AP 0x32
5369 +#define WME_AC_VO_TXOP_AP 0x002f
5370 +
5371 +/* WME Traffic Specification (TSPEC) element */
5372 +#define WME_SUBTYPE_TSPEC 2
5373 +#define WME_TSPEC_HDR_LEN 2
5374 +#define WME_TSPEC_BODY_OFF 2
5375 +struct wme_tspec {
5376 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5377 + uint8 type; /* WME_TYPE */
5378 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5379 + uint8 version; /* WME_VERSION */
5380 + uint16 ts_info; /* TS Info */
5381 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5382 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5383 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5384 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5385 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5386 + uint32 service_start; /* Service Start Time (us) */
5387 + uint32 min_rate; /* Minimum Data Rate (bps) */
5388 + uint32 mean_rate; /* Mean Data Rate (bps) */
5389 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5390 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5391 + uint32 peak_rate; /* Peak Data Rate (bps) */
5392 + uint32 delay_bound; /* Delay Bound (us) */
5393 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5394 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5395 +} PACKED;
5396 +typedef struct wme_tspec wme_tspec_t;
5397 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5398 +
5399 +/* ts_info */
5400 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5401 +#define TS_INFO_PRIO_SHIFT_HI 11
5402 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5403 +#define TS_INFO_PRIO_SHIFT_LO 1
5404 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5405 +#define TS_INFO_CONTENTION_SHIFT 7
5406 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5407 +#define TS_INFO_DIRECTION_SHIFT 5
5408 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5409 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5410 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5411 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5412 +
5413 +/* nom_msdu_size */
5414 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5415 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5416 +
5417 +/* surplus_bandwidth */
5418 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5419 +#define INTEGER_SHIFT 13
5420 +#define FRACTION_MASK 0x1FFF
5421 +
5422 +/* Management Notification Frame */
5423 +struct dot11_management_notification {
5424 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5425 + uint8 action;
5426 + uint8 token;
5427 + uint8 status;
5428 + uint8 data[1]; /* Elements */
5429 +} PACKED;
5430 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5431 +
5432 +/* WME Action Codes */
5433 +#define WME_SETUP_REQUEST 0
5434 +#define WME_SETUP_RESPONSE 1
5435 +#define WME_TEARDOWN 2
5436 +
5437 +/* WME Setup Response Status Codes */
5438 +#define WME_ADMISSION_ACCEPTED 0
5439 +#define WME_INVALID_PARAMETERS 1
5440 +#define WME_ADMISSION_REFUSED 3
5441 +
5442 +/* Macro to take a pointer to a beacon or probe response
5443 + * header and return the char* pointer to the SSID info element
5444 + */
5445 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5446 +
5447 +/* Authentication frame payload constants */
5448 +#define DOT11_OPEN_SYSTEM 0
5449 +#define DOT11_SHARED_KEY 1
5450 +#define DOT11_CHALLENGE_LEN 128
5451 +
5452 +/* Frame control macros */
5453 +#define FC_PVER_MASK 0x3
5454 +#define FC_PVER_SHIFT 0
5455 +#define FC_TYPE_MASK 0xC
5456 +#define FC_TYPE_SHIFT 2
5457 +#define FC_SUBTYPE_MASK 0xF0
5458 +#define FC_SUBTYPE_SHIFT 4
5459 +#define FC_TODS 0x100
5460 +#define FC_TODS_SHIFT 8
5461 +#define FC_FROMDS 0x200
5462 +#define FC_FROMDS_SHIFT 9
5463 +#define FC_MOREFRAG 0x400
5464 +#define FC_MOREFRAG_SHIFT 10
5465 +#define FC_RETRY 0x800
5466 +#define FC_RETRY_SHIFT 11
5467 +#define FC_PM 0x1000
5468 +#define FC_PM_SHIFT 12
5469 +#define FC_MOREDATA 0x2000
5470 +#define FC_MOREDATA_SHIFT 13
5471 +#define FC_WEP 0x4000
5472 +#define FC_WEP_SHIFT 14
5473 +#define FC_ORDER 0x8000
5474 +#define FC_ORDER_SHIFT 15
5475 +
5476 +/* sequence control macros */
5477 +#define SEQNUM_SHIFT 4
5478 +#define FRAGNUM_MASK 0xF
5479 +
5480 +/* Frame Control type/subtype defs */
5481 +
5482 +/* FC Types */
5483 +#define FC_TYPE_MNG 0
5484 +#define FC_TYPE_CTL 1
5485 +#define FC_TYPE_DATA 2
5486 +
5487 +/* Management Subtypes */
5488 +#define FC_SUBTYPE_ASSOC_REQ 0
5489 +#define FC_SUBTYPE_ASSOC_RESP 1
5490 +#define FC_SUBTYPE_REASSOC_REQ 2
5491 +#define FC_SUBTYPE_REASSOC_RESP 3
5492 +#define FC_SUBTYPE_PROBE_REQ 4
5493 +#define FC_SUBTYPE_PROBE_RESP 5
5494 +#define FC_SUBTYPE_BEACON 8
5495 +#define FC_SUBTYPE_ATIM 9
5496 +#define FC_SUBTYPE_DISASSOC 10
5497 +#define FC_SUBTYPE_AUTH 11
5498 +#define FC_SUBTYPE_DEAUTH 12
5499 +#define FC_SUBTYPE_ACTION 13
5500 +
5501 +/* Control Subtypes */
5502 +#define FC_SUBTYPE_PS_POLL 10
5503 +#define FC_SUBTYPE_RTS 11
5504 +#define FC_SUBTYPE_CTS 12
5505 +#define FC_SUBTYPE_ACK 13
5506 +#define FC_SUBTYPE_CF_END 14
5507 +#define FC_SUBTYPE_CF_END_ACK 15
5508 +
5509 +/* Data Subtypes */
5510 +#define FC_SUBTYPE_DATA 0
5511 +#define FC_SUBTYPE_DATA_CF_ACK 1
5512 +#define FC_SUBTYPE_DATA_CF_POLL 2
5513 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5514 +#define FC_SUBTYPE_NULL 4
5515 +#define FC_SUBTYPE_CF_ACK 5
5516 +#define FC_SUBTYPE_CF_POLL 6
5517 +#define FC_SUBTYPE_CF_ACK_POLL 7
5518 +#define FC_SUBTYPE_QOS_DATA 8
5519 +#define FC_SUBTYPE_QOS_NULL 12
5520 +
5521 +/* type-subtype combos */
5522 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5523 +
5524 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5525 +
5526 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5527 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5528 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5529 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5530 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5531 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5532 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5533 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5534 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5535 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5536 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5537 +
5538 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5539 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5540 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5541 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5542 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5543 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5544 +
5545 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5546 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5547 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5548 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5549 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5550 +
5551 +/* QoS Control Field */
5552 +
5553 +/* 802.1D Tag */
5554 +#define QOS_PRIO_SHIFT 0
5555 +#define QOS_PRIO_MASK 0x0007
5556 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5557 +
5558 +#define QOS_TID_SHIFT 0
5559 +#define QOS_TID_MASK 0x000f
5560 +#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
5561 +
5562 +/* Ack Policy (0 means Acknowledge) */
5563 +#define QOS_ACK_SHIFT 5
5564 +#define QOS_ACK_MASK 0x0060
5565 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5566 +
5567 +/* Management Frames */
5568 +
5569 +/* Management Frame Constants */
5570 +
5571 +/* Fixed fields */
5572 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5573 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5574 +#define DOT11_MNG_BEACON_INT_LEN 2
5575 +#define DOT11_MNG_CAP_LEN 2
5576 +#define DOT11_MNG_AP_ADDR_LEN 6
5577 +#define DOT11_MNG_LISTEN_INT_LEN 2
5578 +#define DOT11_MNG_REASON_LEN 2
5579 +#define DOT11_MNG_AID_LEN 2
5580 +#define DOT11_MNG_STATUS_LEN 2
5581 +#define DOT11_MNG_TIMESTAMP_LEN 8
5582 +
5583 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5584 +#define DOT11_AID_MASK 0x3fff
5585 +
5586 +/* Reason Codes */
5587 +#define DOT11_RC_RESERVED 0
5588 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5589 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5590 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5591 + leaving (or has left) IBSS or ESS */
5592 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5593 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5594 + all currently associated stations */
5595 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5596 + nonauthenticated station */
5597 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5598 + nonassociated station */
5599 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5600 + leaving (or has left) BSS */
5601 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5602 + not authenticated with responding station */
5603 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5604 +
5605 +/* Status Codes */
5606 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5607 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5608 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5609 + in the Capability Information field */
5610 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5611 + confirm that association exists */
5612 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5613 + the scope of this standard */
5614 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5615 + specified authentication algorithm */
5616 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5617 + authentication transaction sequence number
5618 + out of expected sequence */
5619 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5620 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5621 + for next frame in sequence */
5622 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5623 + handle additional associated stations */
5624 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5625 + not supporting all of the data rates in the
5626 + BSSBasicRateSet parameter */
5627 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5628 + not supporting the Short Preamble option */
5629 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5630 + not supporting the PBCC Modulation option */
5631 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5632 + not supporting the Channel Agility option */
5633 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5634 + capability is required. */
5635 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5636 + Power Cap element is unacceptable. */
5637 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5638 + Supported Channel element is unacceptable */
5639 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5640 + not supporting the Short Slot Time option */
5641 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5642 + not supporting the ER-PBCC Modulation option */
5643 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5644 + not supporting the DSS-OFDM option */
5645 +
5646 +/* Info Elts, length of INFORMATION portion of Info Elts */
5647 +#define DOT11_MNG_DS_PARAM_LEN 1
5648 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5649 +
5650 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5651 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5652 +#define DOT11_MNG_TIM_FIXED_LEN 3
5653 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5654 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5655 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5656 +#define DOT11_MNG_TIM_PVB 3
5657 +
5658 +/* TLV defines */
5659 +#define TLV_TAG_OFF 0
5660 +#define TLV_LEN_OFF 1
5661 +#define TLV_HDR_LEN 2
5662 +#define TLV_BODY_OFF 2
5663 +
5664 +/* Management Frame Information Element IDs */
5665 +#define DOT11_MNG_SSID_ID 0
5666 +#define DOT11_MNG_RATES_ID 1
5667 +#define DOT11_MNG_FH_PARMS_ID 2
5668 +#define DOT11_MNG_DS_PARMS_ID 3
5669 +#define DOT11_MNG_CF_PARMS_ID 4
5670 +#define DOT11_MNG_TIM_ID 5
5671 +#define DOT11_MNG_IBSS_PARMS_ID 6
5672 +#define DOT11_MNG_COUNTRY_ID 7
5673 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5674 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5675 +#define DOT11_MNG_REQUEST_ID 10
5676 +#define DOT11_MNG_CHALLENGE_ID 16
5677 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5678 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5679 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5680 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5681 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5682 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5683 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5684 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5685 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5686 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5687 +#define DOT11_MNG_ERP_ID 42
5688 +#define DOT11_MNG_NONERP_ID 47
5689 +#ifdef BCMWPA2
5690 +#define DOT11_MNG_RSN_ID 48
5691 +#endif /* BCMWPA2 */
5692 +#define DOT11_MNG_EXT_RATES_ID 50
5693 +#define DOT11_MNG_WPA_ID 221
5694 +#define DOT11_MNG_PROPR_ID 221
5695 +
5696 +/* ERP info element bit values */
5697 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5698 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5699 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5700 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5701 +
5702 +/* Capability Information Field */
5703 +#define DOT11_CAP_ESS 0x0001
5704 +#define DOT11_CAP_IBSS 0x0002
5705 +#define DOT11_CAP_POLLABLE 0x0004
5706 +#define DOT11_CAP_POLL_RQ 0x0008
5707 +#define DOT11_CAP_PRIVACY 0x0010
5708 +#define DOT11_CAP_SHORT 0x0020
5709 +#define DOT11_CAP_PBCC 0x0040
5710 +#define DOT11_CAP_AGILITY 0x0080
5711 +#define DOT11_CAP_SPECTRUM 0x0100
5712 +#define DOT11_CAP_SHORTSLOT 0x0400
5713 +#define DOT11_CAP_CCK_OFDM 0x2000
5714 +
5715 +/* Action Frame Constants */
5716 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5717 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5718 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5719 +
5720 +#define DOT11_ACTION_ID_M_REQ 0
5721 +#define DOT11_ACTION_ID_M_REP 1
5722 +#define DOT11_ACTION_ID_TPC_REQ 2
5723 +#define DOT11_ACTION_ID_TPC_REP 3
5724 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5725 +
5726 +/* MLME Enumerations */
5727 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5728 +#define DOT11_BSSTYPE_INDEPENDENT 1
5729 +#define DOT11_BSSTYPE_ANY 2
5730 +#define DOT11_SCANTYPE_ACTIVE 0
5731 +#define DOT11_SCANTYPE_PASSIVE 1
5732 +
5733 +/* 802.11 A PHY constants */
5734 +#define APHY_SLOT_TIME 9
5735 +#define APHY_SIFS_TIME 16
5736 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5737 +#define APHY_PREAMBLE_TIME 16
5738 +#define APHY_SIGNAL_TIME 4
5739 +#define APHY_SYMBOL_TIME 4
5740 +#define APHY_SERVICE_NBITS 16
5741 +#define APHY_TAIL_NBITS 6
5742 +#define APHY_CWMIN 15
5743 +
5744 +/* 802.11 B PHY constants */
5745 +#define BPHY_SLOT_TIME 20
5746 +#define BPHY_SIFS_TIME 10
5747 +#define BPHY_DIFS_TIME 50
5748 +#define BPHY_PLCP_TIME 192
5749 +#define BPHY_PLCP_SHORT_TIME 96
5750 +#define BPHY_CWMIN 31
5751 +
5752 +/* 802.11 G constants */
5753 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5754 +
5755 +#define PHY_CWMAX 1023
5756 +
5757 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5758 +
5759 +/* dot11Counters Table - 802.11 spec., Annex D */
5760 +typedef struct d11cnt {
5761 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5762 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5763 + uint32 txfail; /* dot11FailedCount */
5764 + uint32 txretry; /* dot11RetryCount */
5765 + uint32 txretrie; /* dot11MultipleRetryCount */
5766 + uint32 rxdup; /* dot11FrameduplicateCount */
5767 + uint32 txrts; /* dot11RTSSuccessCount */
5768 + uint32 txnocts; /* dot11RTSFailureCount */
5769 + uint32 txnoack; /* dot11ACKFailureCount */
5770 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5771 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5772 + uint32 rxcrc; /* dot11FCSErrorCount */
5773 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5774 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5775 +} d11cnt_t;
5776 +
5777 +/* BRCM OUI */
5778 +#define BRCM_OUI "\x00\x10\x18"
5779 +
5780 +/* BRCM info element */
5781 +struct brcm_ie {
5782 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5783 + uchar len;
5784 + uchar oui[3];
5785 + uchar ver;
5786 + uchar assoc; /* # of assoc STAs */
5787 + uchar flags; /* misc flags */
5788 +} PACKED;
5789 +#define BRCM_IE_LEN 8
5790 +typedef struct brcm_ie brcm_ie_t;
5791 +#define BRCM_IE_VER 2
5792 +#define BRCM_IE_LEGACY_AES_VER 1
5793 +
5794 +/* brcm_ie flags */
5795 +#define BRF_ABCAP 0x1 /* afterburner capable */
5796 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5797 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5798 +#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
5799 +#define BRF_ABCOUNTER_SHIFT 4
5800 +
5801 +#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
5802 +#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
5803 +
5804 +
5805 +/* OUI for BRCM proprietary IE */
5806 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5807 +
5808 +/* Vendor IE structure */
5809 +struct vndr_ie {
5810 + uchar id;
5811 + uchar len;
5812 + uchar oui [3];
5813 + uchar data [1]; /* Variable size data */
5814 +}PACKED;
5815 +typedef struct vndr_ie vndr_ie_t;
5816 +
5817 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
5818 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
5819 +#define VNDR_IE_MAX_LEN 256
5820 +
5821 +/* WPA definitions */
5822 +#define WPA_VERSION 1
5823 +#define WPA_OUI "\x00\x50\xF2"
5824 +
5825 +#ifdef BCMWPA2
5826 +#define WPA2_VERSION 1
5827 +#define WPA2_VERSION_LEN 2
5828 +#define WPA2_OUI "\x00\x0F\xAC"
5829 +#endif /* BCMWPA2 */
5830 +
5831 +#define WPA_OUI_LEN 3
5832 +
5833 +/* RSN authenticated key managment suite */
5834 +#define RSN_AKM_NONE 0 /* None (IBSS) */
5835 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
5836 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
5837 +
5838 +
5839 +/* Key related defines */
5840 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
5841 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
5842 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
5843 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
5844 +
5845 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
5846 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
5847 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
5848 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
5849 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
5850 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
5851 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
5852 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
5853 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
5854 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
5855 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
5856 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
5857 +#define AES_KEY_SIZE 16 /* size of AES key */
5858 +
5859 +#undef PACKED
5860 +#if !defined(__GNUC__)
5861 +#pragma pack()
5862 +#endif
5863 +
5864 +#endif /* _802_11_H_ */
5865 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h
5866 --- linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
5867 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-11-07 22:51:38.784726500 +0100
5868 @@ -0,0 +1,103 @@
5869 +/*
5870 + * Broadcom Ethernettype protocol definitions
5871 + *
5872 + * Copyright 2005, Broadcom Corporation
5873 + * All Rights Reserved.
5874 + *
5875 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5876 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5877 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5878 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5879 + *
5880 + */
5881 +
5882 +/*
5883 + * Broadcom Ethernet protocol defines
5884 + *
5885 + */
5886 +
5887 +#ifndef _BCMETH_H_
5888 +#define _BCMETH_H_
5889 +
5890 +/* enable structure packing */
5891 +#if defined(__GNUC__)
5892 +#define PACKED __attribute__((packed))
5893 +#else
5894 +#pragma pack(1)
5895 +#define PACKED
5896 +#endif
5897 +
5898 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
5899 +
5900 +/*
5901 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
5902 + * in one of two formats: (only subtypes 32768-65535 are in use now)
5903 + *
5904 + * subtypes 0-32767:
5905 + * 8 bit subtype (0-127)
5906 + * 8 bit length in bytes (0-255)
5907 + *
5908 + * subtypes 32768-65535:
5909 + * 16 bit big-endian subtype
5910 + * 16 bit big-endian length in bytes (0-65535)
5911 + *
5912 + * length is the number of additional bytes beyond the 4 or 6 byte header
5913 + *
5914 + * Reserved values:
5915 + * 0 reserved
5916 + * 5-15 reserved for iLine protocol assignments
5917 + * 17-126 reserved, assignable
5918 + * 127 reserved
5919 + * 32768 reserved
5920 + * 32769-65534 reserved, assignable
5921 + * 65535 reserved
5922 + */
5923 +
5924 +/*
5925 + * While adding the subtypes and their specific processing code make sure
5926 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
5927 + */
5928 +
5929 +#define BCMILCP_SUBTYPE_RATE 1
5930 +#define BCMILCP_SUBTYPE_LINK 2
5931 +#define BCMILCP_SUBTYPE_CSA 3
5932 +#define BCMILCP_SUBTYPE_LARQ 4
5933 +#define BCMILCP_SUBTYPE_VENDOR 5
5934 +#define BCMILCP_SUBTYPE_FLH 17
5935 +
5936 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
5937 +#define BCMILCP_SUBTYPE_CERT 32770
5938 +#define BCMILCP_SUBTYPE_SES 32771
5939 +
5940 +
5941 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
5942 +#define BCMILCP_BCM_SUBTYPE_EVENT 1
5943 +#define BCMILCP_BCM_SUBTYPE_SES 2
5944 +/*
5945 +The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
5946 +within BCMILCP_BCM_SUBTYPE_EVENT type messages
5947 +*/
5948 +/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
5949 +
5950 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
5951 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
5952 +
5953 +/* These fields are stored in network order */
5954 +typedef struct bcmeth_hdr
5955 +{
5956 + uint16 subtype; /* Vendor specific..32769*/
5957 + uint16 length;
5958 + uint8 version; /* Version is 0*/
5959 + uint8 oui[3]; /* Broadcom OUI*/
5960 + /* user specific Data */
5961 + uint16 usr_subtype;
5962 +} PACKED bcmeth_hdr_t;
5963 +
5964 +
5965 +
5966 +#undef PACKED
5967 +#if !defined(__GNUC__)
5968 +#pragma pack()
5969 +#endif
5970 +
5971 +#endif
5972 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmip.h linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h
5973 --- linux.old/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
5974 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h 2005-11-08 00:15:47.881307500 +0100
5975 @@ -0,0 +1,42 @@
5976 +/*
5977 + * Copyright 2005, Broadcom Corporation
5978 + * All Rights Reserved.
5979 + *
5980 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
5981 + * the contents of this file may not be disclosed to third parties, copied
5982 + * or duplicated in any form, in whole or in part, without the prior
5983 + * written permission of Broadcom Corporation.
5984 + *
5985 + * Fundamental constants relating to IP Protocol
5986 + *
5987 + * $Id$
5988 + */
5989 +
5990 +#ifndef _bcmip_h_
5991 +#define _bcmip_h_
5992 +
5993 +/* IP header */
5994 +#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
5995 +#define IPV4_TOS_OFFSET 1 /* TOS offset */
5996 +#define IPV4_PROT_OFFSET 9 /* protocol type offset */
5997 +#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
5998 +#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
5999 +#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
6000 +
6001 +#define IPV4_VER_MASK 0xf0
6002 +#define IPV4_IHL_MASK 0x0f
6003 +
6004 +#define IPV4_PROT_UDP 17 /* UDP protocol type */
6005 +
6006 +#define IPV4_ADDR_LEN 4 /* IP v4 address length */
6007 +
6008 +#define IPV4_VER_NUM 0x40 /* IP v4 version number */
6009 +
6010 +/* NULL IP address check */
6011 +#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
6012 + ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
6013 +
6014 +#define IPV4_ADDR_STR_LEN 16
6015 +
6016 +#endif /* #ifndef _bcmip_h_ */
6017 +
6018 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
6019 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
6020 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-11-07 22:51:38.784726500 +0100
6021 @@ -0,0 +1,169 @@
6022 +/*******************************************************************************
6023 + * $Id$
6024 + * Copyright 2005, Broadcom Corporation
6025 + * All Rights Reserved.
6026 + *
6027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6031 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
6032 + ******************************************************************************/
6033 +
6034 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
6035 +#define _NET_ETHERNET_H_
6036 +
6037 +#ifndef _TYPEDEFS_H_
6038 +#include "typedefs.h"
6039 +#endif
6040 +
6041 +/* enable structure packing */
6042 +#if defined(__GNUC__)
6043 +#define PACKED __attribute__((packed))
6044 +#else
6045 +#pragma pack(1)
6046 +#define PACKED
6047 +#endif
6048 +
6049 +/*
6050 + * The number of bytes in an ethernet (MAC) address.
6051 + */
6052 +#define ETHER_ADDR_LEN 6
6053 +
6054 +/*
6055 + * The number of bytes in the type field.
6056 + */
6057 +#define ETHER_TYPE_LEN 2
6058 +
6059 +/*
6060 + * The number of bytes in the trailing CRC field.
6061 + */
6062 +#define ETHER_CRC_LEN 4
6063 +
6064 +/*
6065 + * The length of the combined header.
6066 + */
6067 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
6068 +
6069 +/*
6070 + * The minimum packet length.
6071 + */
6072 +#define ETHER_MIN_LEN 64
6073 +
6074 +/*
6075 + * The minimum packet user data length.
6076 + */
6077 +#define ETHER_MIN_DATA 46
6078 +
6079 +/*
6080 + * The maximum packet length.
6081 + */
6082 +#define ETHER_MAX_LEN 1518
6083 +
6084 +/*
6085 + * The maximum packet user data length.
6086 + */
6087 +#define ETHER_MAX_DATA 1500
6088 +
6089 +/* ether types */
6090 +#define ETHER_TYPE_IP 0x0800 /* IP */
6091 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
6092 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
6093 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
6094 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
6095 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
6096 +
6097 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
6098 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
6099 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
6100 +
6101 +/* ether header */
6102 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
6103 +#define ETHER_SRC_OFFSET 6 /* src address offset */
6104 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
6105 +
6106 +/*
6107 + * A macro to validate a length with
6108 + */
6109 +#define ETHER_IS_VALID_LEN(foo) \
6110 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
6111 +
6112 +
6113 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
6114 +/*
6115 + * Structure of a 10Mb/s Ethernet header.
6116 + */
6117 +struct ether_header {
6118 + uint8 ether_dhost[ETHER_ADDR_LEN];
6119 + uint8 ether_shost[ETHER_ADDR_LEN];
6120 + uint16 ether_type;
6121 +} PACKED;
6122 +
6123 +/*
6124 + * Structure of a 48-bit Ethernet address.
6125 + */
6126 +struct ether_addr {
6127 + uint8 octet[ETHER_ADDR_LEN];
6128 +} PACKED;
6129 +#endif
6130 +
6131 +/*
6132 + * Takes a pointer, sets locally admininistered
6133 + * address bit in the 48-bit Ethernet address.
6134 + */
6135 +#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
6136 + (((uint8 *)(ea))[0] | 2) )
6137 +
6138 +/*
6139 + * Takes a pointer, returns true if a 48-bit multicast address
6140 + * (including broadcast, since it is all ones)
6141 + */
6142 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
6143 +
6144 +
6145 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
6146 +#define ether_cmp(a, b) ( \
6147 + !(((short*)a)[0] == ((short*)b)[0]) | \
6148 + !(((short*)a)[1] == ((short*)b)[1]) | \
6149 + !(((short*)a)[2] == ((short*)b)[2]))
6150 +
6151 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
6152 +#define ether_copy(s, d) { \
6153 + ((short*)d)[0] = ((short*)s)[0]; \
6154 + ((short*)d)[1] = ((short*)s)[1]; \
6155 + ((short*)d)[2] = ((short*)s)[2]; }
6156 +
6157 +/*
6158 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
6159 + */
6160 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
6161 + ((uint8 *)(ea))[1] & \
6162 + ((uint8 *)(ea))[2] & \
6163 + ((uint8 *)(ea))[3] & \
6164 + ((uint8 *)(ea))[4] & \
6165 + ((uint8 *)(ea))[5]) == 0xff)
6166 +
6167 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
6168 +
6169 +/*
6170 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
6171 + */
6172 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
6173 + ((uint8 *)(ea))[1] | \
6174 + ((uint8 *)(ea))[2] | \
6175 + ((uint8 *)(ea))[3] | \
6176 + ((uint8 *)(ea))[4] | \
6177 + ((uint8 *)(ea))[5]) == 0)
6178 +
6179 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
6180 +#define DSCP_MASK 0xFC /* upper 6 bits */
6181 +#define DSCP_SHIFT 2
6182 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
6183 +#define DSCP_WME_PRI_SHIFT 5
6184 +
6185 +#undef PACKED
6186 +#if !defined(__GNUC__)
6187 +#pragma pack()
6188 +#endif
6189 +
6190 +#endif /* _NET_ETHERNET_H_ */
6191 diff -urN linux.old/arch/mips/bcm947xx/include/proto/vlan.h linux.dev/arch/mips/bcm947xx/include/proto/vlan.h
6192 --- linux.old/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
6193 +++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-11-07 21:57:07.873587500 +0100
6194 @@ -0,0 +1,50 @@
6195 +/*
6196 + * 802.1Q VLAN protocol definitions
6197 + *
6198 + * Copyright 2005, Broadcom Corporation
6199 + * All Rights Reserved.
6200 + *
6201 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6202 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6203 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6204 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6205 + *
6206 + * $Id$
6207 + */
6208 +
6209 +#ifndef _vlan_h_
6210 +#define _vlan_h_
6211 +
6212 +/* enable structure packing */
6213 +#if defined(__GNUC__)
6214 +#define PACKED __attribute__((packed))
6215 +#else
6216 +#pragma pack(1)
6217 +#define PACKED
6218 +#endif
6219 +
6220 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
6221 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
6222 +#define VLAN_PRI_SHIFT 13 /* user priority */
6223 +
6224 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
6225 +
6226 +#define VLAN_TAG_LEN 4
6227 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
6228 +
6229 +struct ethervlan_header {
6230 + uint8 ether_dhost[ETHER_ADDR_LEN];
6231 + uint8 ether_shost[ETHER_ADDR_LEN];
6232 + uint16 vlan_type; /* 0x8100 */
6233 + uint16 vlan_tag; /* priority, cfi and vid */
6234 + uint16 ether_type;
6235 +};
6236 +
6237 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
6238 +
6239 +#undef PACKED
6240 +#if !defined(__GNUC__)
6241 +#pragma pack()
6242 +#endif
6243 +
6244 +#endif /* _vlan_h_ */
6245 diff -urN linux.old/arch/mips/bcm947xx/include/proto/wpa.h linux.dev/arch/mips/bcm947xx/include/proto/wpa.h
6246 --- linux.old/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
6247 +++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-11-07 21:57:07.873587500 +0100
6248 @@ -0,0 +1,140 @@
6249 +/*
6250 + * Fundamental types and constants relating to WPA
6251 + *
6252 + * Copyright 2005, Broadcom Corporation
6253 + * All Rights Reserved.
6254 + *
6255 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6256 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6257 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6258 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6259 + *
6260 + * $Id$
6261 + */
6262 +
6263 +#ifndef _proto_wpa_h_
6264 +#define _proto_wpa_h_
6265 +
6266 +#include <typedefs.h>
6267 +#include <proto/ethernet.h>
6268 +
6269 +/* enable structure packing */
6270 +#if defined(__GNUC__)
6271 +#define PACKED __attribute__((packed))
6272 +#else
6273 +#pragma pack(1)
6274 +#define PACKED
6275 +#endif
6276 +
6277 +/* Reason Codes */
6278 +
6279 +/* 10 and 11 are from TGh. */
6280 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
6281 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
6282 +/* 12 is unused */
6283 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
6284 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
6285 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
6286 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
6287 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
6288 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
6289 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6290 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6291 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6292 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6293 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6294 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6295 +
6296 +#define WPA2_PMKID_LEN 16
6297 +
6298 +/* WPA IE fixed portion */
6299 +typedef struct
6300 +{
6301 + uint8 tag; /* TAG */
6302 + uint8 length; /* TAG length */
6303 + uint8 oui[3]; /* IE OUI */
6304 + uint8 oui_type; /* OUI type */
6305 + struct {
6306 + uint8 low;
6307 + uint8 high;
6308 + } PACKED version; /* IE version */
6309 +} PACKED wpa_ie_fixed_t;
6310 +#define WPA_IE_OUITYPE_LEN 4
6311 +#define WPA_IE_FIXED_LEN 8
6312 +#define WPA_IE_TAG_FIXED_LEN 6
6313 +
6314 +typedef struct {
6315 + uint8 tag; /* TAG */
6316 + uint8 length; /* TAG length */
6317 + struct {
6318 + uint8 low;
6319 + uint8 high;
6320 + } PACKED version; /* IE version */
6321 +} PACKED wpa_rsn_ie_fixed_t;
6322 +#define WPA_RSN_IE_FIXED_LEN 4
6323 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6324 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6325 +
6326 +/* WPA suite/multicast suite */
6327 +typedef struct
6328 +{
6329 + uint8 oui[3];
6330 + uint8 type;
6331 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6332 +#define WPA_SUITE_LEN 4
6333 +
6334 +/* WPA unicast suite list/key management suite list */
6335 +typedef struct
6336 +{
6337 + struct {
6338 + uint8 low;
6339 + uint8 high;
6340 + } PACKED count;
6341 + wpa_suite_t list[1];
6342 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6343 +#define WPA_IE_SUITE_COUNT_LEN 2
6344 +typedef struct
6345 +{
6346 + struct {
6347 + uint8 low;
6348 + uint8 high;
6349 + } PACKED count;
6350 + wpa_pmkid_t list[1];
6351 +} PACKED wpa_pmkid_list_t;
6352 +
6353 +/* WPA cipher suites */
6354 +#define WPA_CIPHER_NONE 0 /* None */
6355 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6356 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6357 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6358 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6359 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6360 +
6361 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6362 + (cipher) == WPA_CIPHER_WEP_40 || \
6363 + (cipher) == WPA_CIPHER_WEP_104 || \
6364 + (cipher) == WPA_CIPHER_TKIP || \
6365 + (cipher) == WPA_CIPHER_AES_OCB || \
6366 + (cipher) == WPA_CIPHER_AES_CCM)
6367 +
6368 +/* WPA TKIP countermeasures parameters */
6369 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6370 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6371 +
6372 +/* WPA capabilities defined in 802.11i */
6373 +#define WPA_CAP_4_REPLAY_CNTRS 2
6374 +#define WPA_CAP_16_REPLAY_CNTRS 3
6375 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6376 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6377 +
6378 +/* WPA Specific defines */
6379 +#define WPA_CAP_LEN 2
6380 +
6381 +#define WPA_CAP_WPA2_PREAUTH 1
6382 +
6383 +#undef PACKED
6384 +#if !defined(__GNUC__)
6385 +#pragma pack()
6386 +#endif
6387 +
6388 +#endif /* _proto_wpa_h_ */
6389 diff -urN linux.old/arch/mips/bcm947xx/include/rts/crc.h linux.dev/arch/mips/bcm947xx/include/rts/crc.h
6390 --- linux.old/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6391 +++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-11-07 21:57:07.873587500 +0100
6392 @@ -0,0 +1,69 @@
6393 +/*******************************************************************************
6394 + * $Id$
6395 + * Copyright 2005, Broadcom Corporation
6396 + * All Rights Reserved.
6397 + *
6398 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6399 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6400 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6401 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6402 + * crc.h - a function to compute crc for iLine10 headers
6403 + ******************************************************************************/
6404 +
6405 +#ifndef _RTS_CRC_H_
6406 +#define _RTS_CRC_H_ 1
6407 +
6408 +#include "typedefs.h"
6409 +
6410 +#ifdef __cplusplus
6411 +extern "C" {
6412 +#endif
6413 +
6414 +
6415 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6416 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6417 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6418 +
6419 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6420 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6421 +
6422 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6423 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6424 +
6425 +void hcs(uint8 *, uint);
6426 +uint8 crc8(uint8 *, uint, uint8);
6427 +uint16 crc16(uint8 *, uint, uint16);
6428 +uint32 crc32(uint8 *, uint, uint32);
6429 +
6430 +/* macros for common usage */
6431 +
6432 +#define APPEND_CRC8(pbytes, nbytes) \
6433 +do { \
6434 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6435 + (pbytes)[(nbytes)] = tmp; \
6436 + (nbytes) += 1; \
6437 +} while (0)
6438 +
6439 +#define APPEND_CRC16(pbytes, nbytes) \
6440 +do { \
6441 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6442 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6443 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6444 + (nbytes) += 2; \
6445 +} while (0)
6446 +
6447 +#define APPEND_CRC32(pbytes, nbytes) \
6448 +do { \
6449 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6450 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6451 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6452 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6453 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6454 + (nbytes) += 4; \
6455 +} while (0)
6456 +
6457 +#ifdef __cplusplus
6458 +}
6459 +#endif
6460 +
6461 +#endif /* _RTS_CRC_H_ */
6462 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6463 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6464 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-11-07 22:51:38.784726500 +0100
6465 @@ -0,0 +1,440 @@
6466 +/*
6467 + * SiliconBackplane Chipcommon core hardware definitions.
6468 + *
6469 + * The chipcommon core provides chip identification, SB control,
6470 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6471 + * gpio interface, extbus, and support for serial and parallel flashes.
6472 + *
6473 + * $Id$
6474 + * Copyright 2005, Broadcom Corporation
6475 + * All Rights Reserved.
6476 + *
6477 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6478 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6479 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6480 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6481 + *
6482 + */
6483 +
6484 +#ifndef _SBCHIPC_H
6485 +#define _SBCHIPC_H
6486 +
6487 +
6488 +#ifndef _LANGUAGE_ASSEMBLY
6489 +
6490 +/* cpp contortions to concatenate w/arg prescan */
6491 +#ifndef PAD
6492 +#define _PADLINE(line) pad ## line
6493 +#define _XSTR(line) _PADLINE(line)
6494 +#define PAD _XSTR(__LINE__)
6495 +#endif /* PAD */
6496 +
6497 +typedef volatile struct {
6498 + uint32 chipid; /* 0x0 */
6499 + uint32 capabilities;
6500 + uint32 corecontrol; /* corerev >= 1 */
6501 + uint32 bist;
6502 +
6503 + /* OTP */
6504 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6505 + uint32 otpcontrol;
6506 + uint32 otpprog;
6507 + uint32 PAD;
6508 +
6509 + /* Interrupt control */
6510 + uint32 intstatus; /* 0x20 */
6511 + uint32 intmask;
6512 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6513 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6514 +
6515 + /* Jtag Master */
6516 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6517 + uint32 jtagir;
6518 + uint32 jtagdr;
6519 + uint32 jtagctrl;
6520 +
6521 + /* serial flash interface registers */
6522 + uint32 flashcontrol; /* 0x40 */
6523 + uint32 flashaddress;
6524 + uint32 flashdata;
6525 + uint32 PAD[1];
6526 +
6527 + /* Silicon backplane configuration broadcast control */
6528 + uint32 broadcastaddress; /* 0x50 */
6529 + uint32 broadcastdata;
6530 + uint32 PAD[2];
6531 +
6532 + /* gpio - cleared only by power-on-reset */
6533 + uint32 gpioin; /* 0x60 */
6534 + uint32 gpioout;
6535 + uint32 gpioouten;
6536 + uint32 gpiocontrol;
6537 + uint32 gpiointpolarity;
6538 + uint32 gpiointmask;
6539 + uint32 PAD[2];
6540 +
6541 + /* Watchdog timer */
6542 + uint32 watchdog; /* 0x80 */
6543 + uint32 PAD[1];
6544 +
6545 + /*GPIO based LED powersave registers corerev >= 16*/
6546 + uint32 gpiotimerval; /*0x88 */
6547 + uint32 gpiotimeroutmask;
6548 +
6549 + /* clock control */
6550 + uint32 clockcontrol_n; /* 0x90 */
6551 + uint32 clockcontrol_sb; /* aka m0 */
6552 + uint32 clockcontrol_pci; /* aka m1 */
6553 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6554 + uint32 clockcontrol_mips; /* aka m3 */
6555 + uint32 clkdiv; /* corerev >= 3 */
6556 + uint32 PAD[2];
6557 +
6558 + /* pll delay registers (corerev >= 4) */
6559 + uint32 pll_on_delay; /* 0xb0 */
6560 + uint32 fref_sel_delay;
6561 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6562 + uint32 PAD[1];
6563 +
6564 + /* Instaclock registers (corerev >= 10) */
6565 + uint32 system_clk_ctl; /* 0xc0 */
6566 + uint32 clkstatestretch;
6567 + uint32 PAD[14];
6568 +
6569 + /* ExtBus control registers (corerev >= 3) */
6570 + uint32 pcmcia_config; /* 0x100 */
6571 + uint32 pcmcia_memwait;
6572 + uint32 pcmcia_attrwait;
6573 + uint32 pcmcia_iowait;
6574 + uint32 ide_config;
6575 + uint32 ide_memwait;
6576 + uint32 ide_attrwait;
6577 + uint32 ide_iowait;
6578 + uint32 prog_config;
6579 + uint32 prog_waitcount;
6580 + uint32 flash_config;
6581 + uint32 flash_waitcount;
6582 + uint32 PAD[116];
6583 +
6584 + /* uarts */
6585 + uint8 uart0data; /* 0x300 */
6586 + uint8 uart0imr;
6587 + uint8 uart0fcr;
6588 + uint8 uart0lcr;
6589 + uint8 uart0mcr;
6590 + uint8 uart0lsr;
6591 + uint8 uart0msr;
6592 + uint8 uart0scratch;
6593 + uint8 PAD[248]; /* corerev >= 1 */
6594 +
6595 + uint8 uart1data; /* 0x400 */
6596 + uint8 uart1imr;
6597 + uint8 uart1fcr;
6598 + uint8 uart1lcr;
6599 + uint8 uart1mcr;
6600 + uint8 uart1lsr;
6601 + uint8 uart1msr;
6602 + uint8 uart1scratch;
6603 +} chipcregs_t;
6604 +
6605 +#endif /* _LANGUAGE_ASSEMBLY */
6606 +
6607 +#define CC_CHIPID 0
6608 +#define CC_CAPABILITIES 4
6609 +#define CC_JTAGCMD 0x30
6610 +#define CC_JTAGIR 0x34
6611 +#define CC_JTAGDR 0x38
6612 +#define CC_JTAGCTRL 0x3c
6613 +#define CC_WATCHDOG 0x80
6614 +#define CC_CLKC_N 0x90
6615 +#define CC_CLKC_M0 0x94
6616 +#define CC_CLKC_M1 0x98
6617 +#define CC_CLKC_M2 0x9c
6618 +#define CC_CLKC_M3 0xa0
6619 +#define CC_CLKDIV 0xa4
6620 +#define CC_SYS_CLK_CTL 0xc0
6621 +#define CC_OTP 0x800
6622 +
6623 +/* chipid */
6624 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6625 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6626 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6627 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6628 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6629 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6630 +#define CID_CC_SHIFT 24
6631 +
6632 +/* capabilities */
6633 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6634 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6635 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6636 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6637 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6638 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6639 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6640 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6641 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6642 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6643 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6644 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6645 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6646 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6647 +
6648 +/* PLL type */
6649 +#define PLL_NONE 0x00000000
6650 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6651 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6652 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6653 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6654 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6655 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6656 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6657 +
6658 +/* corecontrol */
6659 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6660 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6661 +
6662 +/* Fields in the otpstatus register */
6663 +#define OTPS_PROGFAIL 0x80000000
6664 +#define OTPS_PROTECT 0x00000007
6665 +#define OTPS_HW_PROTECT 0x00000001
6666 +#define OTPS_SW_PROTECT 0x00000002
6667 +#define OTPS_CID_PROTECT 0x00000004
6668 +
6669 +/* Fields in the otpcontrol register */
6670 +#define OTPC_RECWAIT 0xff000000
6671 +#define OTPC_PROGWAIT 0x00ffff00
6672 +#define OTPC_PRW_SHIFT 8
6673 +#define OTPC_MAXFAIL 0x00000038
6674 +#define OTPC_VSEL 0x00000006
6675 +#define OTPC_SELVL 0x00000001
6676 +
6677 +/* Fields in otpprog */
6678 +#define OTPP_COL_MASK 0x000000ff
6679 +#define OTPP_ROW_MASK 0x0000ff00
6680 +#define OTPP_ROW_SHIFT 8
6681 +#define OTPP_READERR 0x10000000
6682 +#define OTPP_VALUE 0x20000000
6683 +#define OTPP_VALUE_SHIFT 29
6684 +#define OTPP_READ 0x40000000
6685 +#define OTPP_START 0x80000000
6686 +#define OTPP_BUSY 0x80000000
6687 +
6688 +/* jtagcmd */
6689 +#define JCMD_START 0x80000000
6690 +#define JCMD_BUSY 0x80000000
6691 +#define JCMD_PAUSE 0x40000000
6692 +#define JCMD0_ACC_MASK 0x0000f000
6693 +#define JCMD0_ACC_IRDR 0x00000000
6694 +#define JCMD0_ACC_DR 0x00001000
6695 +#define JCMD0_ACC_IR 0x00002000
6696 +#define JCMD0_ACC_RESET 0x00003000
6697 +#define JCMD0_ACC_IRPDR 0x00004000
6698 +#define JCMD0_ACC_PDR 0x00005000
6699 +#define JCMD0_IRW_MASK 0x00000f00
6700 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6701 +#define JCMD_ACC_IRDR 0x00000000
6702 +#define JCMD_ACC_DR 0x00010000
6703 +#define JCMD_ACC_IR 0x00020000
6704 +#define JCMD_ACC_RESET 0x00030000
6705 +#define JCMD_ACC_IRPDR 0x00040000
6706 +#define JCMD_ACC_PDR 0x00050000
6707 +#define JCMD_IRW_MASK 0x00001f00
6708 +#define JCMD_IRW_SHIFT 8
6709 +#define JCMD_DRW_MASK 0x0000003f
6710 +
6711 +/* jtagctrl */
6712 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6713 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6714 +#define JCTRL_EN 1 /* Enable Jtag master */
6715 +
6716 +/* Fields in clkdiv */
6717 +#define CLKD_SFLASH 0x0f000000
6718 +#define CLKD_SFLASH_SHIFT 24
6719 +#define CLKD_OTP 0x000f0000
6720 +#define CLKD_OTP_SHIFT 16
6721 +#define CLKD_JTAG 0x00000f00
6722 +#define CLKD_JTAG_SHIFT 8
6723 +#define CLKD_UART 0x000000ff
6724 +
6725 +/* intstatus/intmask */
6726 +#define CI_GPIO 0x00000001 /* gpio intr */
6727 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6728 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6729 +
6730 +/* slow_clk_ctl */
6731 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6732 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6733 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6734 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6735 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6736 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6737 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6738 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6739 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6740 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6741 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6742 +#define SCC_CD_SHIFT 16
6743 +
6744 +/* system_clk_ctl */
6745 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6746 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6747 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6748 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6749 +#define SYCC_HR 0x00000010 /* Force HT */
6750 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
6751 +#define SYCC_CD_SHIFT 16
6752 +
6753 +/* gpiotimerval*/
6754 +#define GPIO_ONTIME_SHIFT 16
6755 +
6756 +/* clockcontrol_n */
6757 +#define CN_N1_MASK 0x3f /* n1 control */
6758 +#define CN_N2_MASK 0x3f00 /* n2 control */
6759 +#define CN_N2_SHIFT 8
6760 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6761 +#define CN_PLLC_SHIFT 16
6762 +
6763 +/* clockcontrol_sb/pci/uart */
6764 +#define CC_M1_MASK 0x3f /* m1 control */
6765 +#define CC_M2_MASK 0x3f00 /* m2 control */
6766 +#define CC_M2_SHIFT 8
6767 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6768 +#define CC_M3_SHIFT 16
6769 +#define CC_MC_MASK 0x1f000000 /* mux control */
6770 +#define CC_MC_SHIFT 24
6771 +
6772 +/* N3M Clock control magic field values */
6773 +#define CC_F6_2 0x02 /* A factor of 2 in */
6774 +#define CC_F6_3 0x03 /* 6-bit fields like */
6775 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6776 +#define CC_F6_5 0x09
6777 +#define CC_F6_6 0x11
6778 +#define CC_F6_7 0x21
6779 +
6780 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6781 +
6782 +#define CC_MC_BYPASS 0x08
6783 +#define CC_MC_M1 0x04
6784 +#define CC_MC_M1M2 0x02
6785 +#define CC_MC_M1M2M3 0x01
6786 +#define CC_MC_M1M3 0x11
6787 +
6788 +/* Type 2 Clock control magic field values */
6789 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6790 +#define CC_T2M2_BIAS 3 /* m2 bias */
6791 +
6792 +#define CC_T2MC_M1BYP 1
6793 +#define CC_T2MC_M2BYP 2
6794 +#define CC_T2MC_M3BYP 4
6795 +
6796 +/* Type 6 Clock control magic field values */
6797 +#define CC_T6_MMASK 1 /* bits of interest in m */
6798 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6799 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6800 +#define SB2MIPS_T6(sb) (2 * (sb))
6801 +
6802 +/* Common clock base */
6803 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6804 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6805 +
6806 +/* Clock control values for 200Mhz in 5350 */
6807 +#define CLKC_5350_N 0x0311
6808 +#define CLKC_5350_M 0x04020009
6809 +
6810 +/* Flash types in the chipcommon capabilities register */
6811 +#define FLASH_NONE 0x000 /* No flash */
6812 +#define SFLASH_ST 0x100 /* ST serial flash */
6813 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6814 +#define PFLASH 0x700 /* Parallel flash */
6815 +
6816 +/* Bits in the config registers */
6817 +#define CC_CFG_EN 0x0001 /* Enable */
6818 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6819 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
6820 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
6821 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
6822 +#define CC_CFG_EM_IDE 0x000a /* IDE */
6823 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6824 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6825 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6826 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6827 +
6828 +/* Start/busy bit in flashcontrol */
6829 +#define SFLASH_START 0x80000000
6830 +#define SFLASH_BUSY SFLASH_START
6831 +
6832 +/* flashcontrol opcodes for ST flashes */
6833 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6834 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6835 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6836 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6837 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6838 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6839 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6840 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6841 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6842 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6843 +
6844 +/* Status register bits for ST flashes */
6845 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6846 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6847 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6848 +#define SFLASH_ST_BP_SHIFT 2
6849 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6850 +
6851 +/* flashcontrol opcodes for Atmel flashes */
6852 +#define SFLASH_AT_READ 0x07e8
6853 +#define SFLASH_AT_PAGE_READ 0x07d2
6854 +#define SFLASH_AT_BUF1_READ
6855 +#define SFLASH_AT_BUF2_READ
6856 +#define SFLASH_AT_STATUS 0x01d7
6857 +#define SFLASH_AT_BUF1_WRITE 0x0384
6858 +#define SFLASH_AT_BUF2_WRITE 0x0387
6859 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6860 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6861 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6862 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6863 +#define SFLASH_AT_PAGE_ERASE 0x0281
6864 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6865 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6866 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6867 +#define SFLASH_AT_BUF1_LOAD 0x0253
6868 +#define SFLASH_AT_BUF2_LOAD 0x0255
6869 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6870 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6871 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6872 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6873 +
6874 +/* Status register bits for Atmel flashes */
6875 +#define SFLASH_AT_READY 0x80
6876 +#define SFLASH_AT_MISMATCH 0x40
6877 +#define SFLASH_AT_ID_MASK 0x38
6878 +#define SFLASH_AT_ID_SHIFT 3
6879 +
6880 +/* OTP regions */
6881 +#define OTP_HW_REGION OTPS_HW_PROTECT
6882 +#define OTP_SW_REGION OTPS_SW_PROTECT
6883 +#define OTP_CID_REGION OTPS_CID_PROTECT
6884 +
6885 +/* OTP regions (Byte offsets from otp size) */
6886 +#define OTP_SWLIM_OFF (-8)
6887 +#define OTP_CIDBASE_OFF 0
6888 +#define OTP_CIDLIM_OFF 8
6889 +
6890 +/* Predefined OTP words (Word offset from otp size) */
6891 +#define OTP_BOUNDARY_OFF (-4)
6892 +#define OTP_HWSIGN_OFF (-3)
6893 +#define OTP_SWSIGN_OFF (-2)
6894 +#define OTP_CIDSIGN_OFF (-1)
6895 +
6896 +#define OTP_CID_OFF 0
6897 +#define OTP_PKG_OFF 1
6898 +#define OTP_FID_OFF 2
6899 +#define OTP_RSV_OFF 3
6900 +#define OTP_LIM_OFF 4
6901 +
6902 +#define OTP_SIGNATURE 0x578a
6903 +#define OTP_MAGIC 0x4e56
6904 +
6905 +#endif /* _SBCHIPC_H */
6906 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6907 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6908 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-11-07 22:51:38.784726500 +0100
6909 @@ -0,0 +1,342 @@
6910 +/*
6911 + * Broadcom SiliconBackplane hardware register definitions.
6912 + *
6913 + * Copyright 2005, Broadcom Corporation
6914 + * All Rights Reserved.
6915 + *
6916 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6917 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6918 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6919 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6920 + * $Id$
6921 + */
6922 +
6923 +#ifndef _SBCONFIG_H
6924 +#define _SBCONFIG_H
6925 +
6926 +/* cpp contortions to concatenate w/arg prescan */
6927 +#ifndef PAD
6928 +#define _PADLINE(line) pad ## line
6929 +#define _XSTR(line) _PADLINE(line)
6930 +#define PAD _XSTR(__LINE__)
6931 +#endif
6932 +
6933 +/*
6934 + * SiliconBackplane Address Map.
6935 + * All regions may not exist on all chips.
6936 + */
6937 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6938 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6939 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6940 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6941 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6942 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6943 +
6944 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6945 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6946 +
6947 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6948 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
6949 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
6950 +
6951 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6952 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6953 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
6954 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
6955 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6956 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6957 +
6958 +
6959 +/* enumeration space related defs */
6960 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6961 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6962 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6963 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6964 +
6965 +/* mips address */
6966 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6967 +
6968 +/*
6969 + * Sonics Configuration Space Registers.
6970 + */
6971 +#define SBIPSFLAG 0x08
6972 +#define SBTPSFLAG 0x18
6973 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6974 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6975 +#define SBADMATCH3 0x60
6976 +#define SBADMATCH2 0x68
6977 +#define SBADMATCH1 0x70
6978 +#define SBIMSTATE 0x90
6979 +#define SBINTVEC 0x94
6980 +#define SBTMSTATELOW 0x98
6981 +#define SBTMSTATEHIGH 0x9c
6982 +#define SBBWA0 0xa0
6983 +#define SBIMCONFIGLOW 0xa8
6984 +#define SBIMCONFIGHIGH 0xac
6985 +#define SBADMATCH0 0xb0
6986 +#define SBTMCONFIGLOW 0xb8
6987 +#define SBTMCONFIGHIGH 0xbc
6988 +#define SBBCONFIG 0xc0
6989 +#define SBBSTATE 0xc8
6990 +#define SBACTCNFG 0xd8
6991 +#define SBFLAGST 0xe8
6992 +#define SBIDLOW 0xf8
6993 +#define SBIDHIGH 0xfc
6994 +
6995 +#ifndef _LANGUAGE_ASSEMBLY
6996 +
6997 +typedef volatile struct _sbconfig {
6998 + uint32 PAD[2];
6999 + uint32 sbipsflag; /* initiator port ocp slave flag */
7000 + uint32 PAD[3];
7001 + uint32 sbtpsflag; /* target port ocp slave flag */
7002 + uint32 PAD[11];
7003 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
7004 + uint32 PAD;
7005 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
7006 + uint32 PAD[3];
7007 + uint32 sbadmatch3; /* address match3 */
7008 + uint32 PAD;
7009 + uint32 sbadmatch2; /* address match2 */
7010 + uint32 PAD;
7011 + uint32 sbadmatch1; /* address match1 */
7012 + uint32 PAD[7];
7013 + uint32 sbimstate; /* initiator agent state */
7014 + uint32 sbintvec; /* interrupt mask */
7015 + uint32 sbtmstatelow; /* target state */
7016 + uint32 sbtmstatehigh; /* target state */
7017 + uint32 sbbwa0; /* bandwidth allocation table0 */
7018 + uint32 PAD;
7019 + uint32 sbimconfiglow; /* initiator configuration */
7020 + uint32 sbimconfighigh; /* initiator configuration */
7021 + uint32 sbadmatch0; /* address match0 */
7022 + uint32 PAD;
7023 + uint32 sbtmconfiglow; /* target configuration */
7024 + uint32 sbtmconfighigh; /* target configuration */
7025 + uint32 sbbconfig; /* broadcast configuration */
7026 + uint32 PAD;
7027 + uint32 sbbstate; /* broadcast state */
7028 + uint32 PAD[3];
7029 + uint32 sbactcnfg; /* activate configuration */
7030 + uint32 PAD[3];
7031 + uint32 sbflagst; /* current sbflags */
7032 + uint32 PAD[3];
7033 + uint32 sbidlow; /* identification */
7034 + uint32 sbidhigh; /* identification */
7035 +} sbconfig_t;
7036 +
7037 +#endif /* _LANGUAGE_ASSEMBLY */
7038 +
7039 +/* sbipsflag */
7040 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
7041 +#define SBIPS_INT1_SHIFT 0
7042 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
7043 +#define SBIPS_INT2_SHIFT 8
7044 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
7045 +#define SBIPS_INT3_SHIFT 16
7046 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
7047 +#define SBIPS_INT4_SHIFT 24
7048 +
7049 +/* sbtpsflag */
7050 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
7051 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
7052 +
7053 +/* sbtmerrlog */
7054 +#define SBTMEL_CM 0x00000007 /* command */
7055 +#define SBTMEL_CI 0x0000ff00 /* connection id */
7056 +#define SBTMEL_EC 0x0f000000 /* error code */
7057 +#define SBTMEL_ME 0x80000000 /* multiple error */
7058 +
7059 +/* sbimstate */
7060 +#define SBIM_PC 0xf /* pipecount */
7061 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
7062 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
7063 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
7064 +#define SBIM_AP_TK 0x20 /* use token only */
7065 +#define SBIM_AP_RSV 0x30 /* reserved */
7066 +#define SBIM_IBE 0x20000 /* inbanderror */
7067 +#define SBIM_TO 0x40000 /* timeout */
7068 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
7069 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
7070 +
7071 +/* sbtmstatelow */
7072 +#define SBTML_RESET 0x1 /* reset */
7073 +#define SBTML_REJ_MASK 0x6 /* reject */
7074 +#define SBTML_REJ_SHIFT 1
7075 +#define SBTML_CLK 0x10000 /* clock enable */
7076 +#define SBTML_FGC 0x20000 /* force gated clocks on */
7077 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
7078 +#define SBTML_PE 0x40000000 /* pme enable */
7079 +#define SBTML_BE 0x80000000 /* bist enable */
7080 +
7081 +/* sbtmstatehigh */
7082 +#define SBTMH_SERR 0x1 /* serror */
7083 +#define SBTMH_INT 0x2 /* interrupt */
7084 +#define SBTMH_BUSY 0x4 /* busy */
7085 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
7086 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
7087 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
7088 +#define SBTMH_GCR 0x20000000 /* gated clock request */
7089 +#define SBTMH_BISTF 0x40000000 /* bist failed */
7090 +#define SBTMH_BISTD 0x80000000 /* bist done */
7091 +
7092 +
7093 +/* sbbwa0 */
7094 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
7095 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
7096 +#define SBBWA_TAB1_SHIFT 16
7097 +
7098 +/* sbimconfiglow */
7099 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
7100 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
7101 +#define SBIMCL_RTO_SHIFT 4
7102 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
7103 +#define SBIMCL_CID_SHIFT 16
7104 +
7105 +/* sbimconfighigh */
7106 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
7107 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
7108 +#define SBIMCH_TEM_SHIFT 4
7109 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
7110 +#define SBIMCH_BEM_SHIFT 6
7111 +
7112 +/* sbadmatch0 */
7113 +#define SBAM_TYPE_MASK 0x3 /* address type */
7114 +#define SBAM_AD64 0x4 /* reserved */
7115 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
7116 +#define SBAM_ADINT0_SHIFT 3
7117 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
7118 +#define SBAM_ADINT1_SHIFT 3
7119 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
7120 +#define SBAM_ADINT2_SHIFT 3
7121 +#define SBAM_ADEN 0x400 /* enable */
7122 +#define SBAM_ADNEG 0x800 /* negative decode */
7123 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
7124 +#define SBAM_BASE0_SHIFT 8
7125 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
7126 +#define SBAM_BASE1_SHIFT 12
7127 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
7128 +#define SBAM_BASE2_SHIFT 16
7129 +
7130 +/* sbtmconfiglow */
7131 +#define SBTMCL_CD_MASK 0xff /* clock divide */
7132 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
7133 +#define SBTMCL_CO_SHIFT 11
7134 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
7135 +#define SBTMCL_IF_SHIFT 18
7136 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
7137 +#define SBTMCL_IM_SHIFT 24
7138 +
7139 +/* sbtmconfighigh */
7140 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
7141 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
7142 +#define SBTMCH_RM_SHIFT 2
7143 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
7144 +#define SBTMCH_SM_SHIFT 4
7145 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
7146 +#define SBTMCH_EM_SHIFT 8
7147 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
7148 +#define SBTMCH_IM_SHIFT 10
7149 +
7150 +/* sbbconfig */
7151 +#define SBBC_LAT_MASK 0x3 /* sb latency */
7152 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
7153 +#define SBBC_MAX0_SHIFT 16
7154 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
7155 +#define SBBC_MAX1_SHIFT 20
7156 +
7157 +/* sbbstate */
7158 +#define SBBS_SRD 0x1 /* st reg disable */
7159 +#define SBBS_HRD 0x2 /* hold reg disable */
7160 +
7161 +/* sbidlow */
7162 +#define SBIDL_CS_MASK 0x3 /* config space */
7163 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
7164 +#define SBIDL_AR_SHIFT 3
7165 +#define SBIDL_SYNCH 0x40 /* sync */
7166 +#define SBIDL_INIT 0x80 /* initiator */
7167 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
7168 +#define SBIDL_MINLAT_SHIFT 8
7169 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
7170 +#define SBIDL_MAXLAT_SHIFT 12
7171 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
7172 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
7173 +#define SBIDL_CW_SHIFT 18
7174 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
7175 +#define SBIDL_TP_SHIFT 20
7176 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
7177 +#define SBIDL_IP_SHIFT 24
7178 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
7179 +#define SBIDL_RV_SHIFT 28
7180 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
7181 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
7182 +
7183 +/* sbidhigh */
7184 +#define SBIDH_RC_MASK 0x000f /* revision code */
7185 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
7186 +#define SBIDH_RCE_SHIFT 8
7187 +#define SBCOREREV(sbidh) \
7188 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
7189 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
7190 +#define SBIDH_CC_SHIFT 4
7191 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
7192 +#define SBIDH_VC_SHIFT 16
7193 +
7194 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
7195 +
7196 +/* vendor codes */
7197 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
7198 +
7199 +/* core codes */
7200 +#define SB_CC 0x800 /* chipcommon core */
7201 +#define SB_ILINE20 0x801 /* iline20 core */
7202 +#define SB_SDRAM 0x803 /* sdram core */
7203 +#define SB_PCI 0x804 /* pci core */
7204 +#define SB_MIPS 0x805 /* mips core */
7205 +#define SB_ENET 0x806 /* enet mac core */
7206 +#define SB_CODEC 0x807 /* v90 codec core */
7207 +#define SB_USB 0x808 /* usb 1.1 host/device core */
7208 +#define SB_ADSL 0x809 /* ADSL core */
7209 +#define SB_ILINE100 0x80a /* iline100 core */
7210 +#define SB_IPSEC 0x80b /* ipsec core */
7211 +#define SB_PCMCIA 0x80d /* pcmcia core */
7212 +#define SB_SOCRAM 0x80e /* internal memory core */
7213 +#define SB_MEMC 0x80f /* memc sdram core */
7214 +#define SB_EXTIF 0x811 /* external interface core */
7215 +#define SB_D11 0x812 /* 802.11 MAC core */
7216 +#define SB_MIPS33 0x816 /* mips3302 core */
7217 +#define SB_USB11H 0x817 /* usb 1.1 host core */
7218 +#define SB_USB11D 0x818 /* usb 1.1 device core */
7219 +#define SB_USB20H 0x819 /* usb 2.0 host core */
7220 +#define SB_USB20D 0x81a /* usb 2.0 device core */
7221 +#define SB_SDIOH 0x81b /* sdio host core */
7222 +#define SB_ROBO 0x81c /* roboswitch core */
7223 +#define SB_ATA100 0x81d /* parallel ATA core */
7224 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
7225 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
7226 +#define SB_PCIE 0x820 /* pci express core */
7227 +#define SB_SRAMC 0x822 /* SRAM controller core */
7228 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
7229 +
7230 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
7231 +
7232 +/* Not really related to Silicon Backplane, but a couple of software
7233 + * conventions for the use the flash space:
7234 + */
7235 +
7236 +/* Minumum amount of flash we support */
7237 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
7238 +
7239 +/* A boot/binary may have an embedded block that describes its size */
7240 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
7241 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
7242 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
7243 +#define BISZ_TXTST_IDX 1 /* 1: text start */
7244 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
7245 +#define BISZ_DATAST_IDX 3 /* 3: text start */
7246 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
7247 +#define BISZ_BSSST_IDX 5 /* 5: text start */
7248 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
7249 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
7250 +
7251 +#endif /* _SBCONFIG_H */
7252 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
7253 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
7254 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-11-07 21:57:07.877587750 +0100
7255 @@ -0,0 +1,242 @@
7256 +/*
7257 + * Hardware-specific External Interface I/O core definitions
7258 + * for the BCM47xx family of SiliconBackplane-based chips.
7259 + *
7260 + * The External Interface core supports a total of three external chip selects
7261 + * supporting external interfaces. One of the external chip selects is
7262 + * used for Flash, one is used for PCMCIA, and the other may be
7263 + * programmed to support either a synchronous interface or an
7264 + * asynchronous interface. The asynchronous interface can be used to
7265 + * support external devices such as UARTs and the BCM2019 Bluetooth
7266 + * baseband processor.
7267 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7268 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7269 + *
7270 + * Copyright 2005, Broadcom Corporation
7271 + * All Rights Reserved.
7272 + *
7273 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7274 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7275 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7276 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7277 + * $Id$
7278 + */
7279 +
7280 +#ifndef _SBEXTIF_H
7281 +#define _SBEXTIF_H
7282 +
7283 +/* external interface address space */
7284 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
7285 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
7286 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
7287 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
7288 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
7289 +
7290 +/* cpp contortions to concatenate w/arg prescan */
7291 +#ifndef PAD
7292 +#define _PADLINE(line) pad ## line
7293 +#define _XSTR(line) _PADLINE(line)
7294 +#define PAD _XSTR(__LINE__)
7295 +#endif /* PAD */
7296 +
7297 +/*
7298 + * The multiple instances of output and output enable registers
7299 + * are present to allow driver software for multiple cores to control
7300 + * gpio outputs without needing to share a single register pair.
7301 + */
7302 +struct gpiouser {
7303 + uint32 out;
7304 + uint32 outen;
7305 +};
7306 +#define NGPIOUSER 5
7307 +
7308 +typedef volatile struct {
7309 + uint32 corecontrol;
7310 + uint32 extstatus;
7311 + uint32 PAD[2];
7312 +
7313 + /* pcmcia control registers */
7314 + uint32 pcmcia_config;
7315 + uint32 pcmcia_memwait;
7316 + uint32 pcmcia_attrwait;
7317 + uint32 pcmcia_iowait;
7318 +
7319 + /* programmable interface control registers */
7320 + uint32 prog_config;
7321 + uint32 prog_waitcount;
7322 +
7323 + /* flash control registers */
7324 + uint32 flash_config;
7325 + uint32 flash_waitcount;
7326 + uint32 PAD[4];
7327 +
7328 + uint32 watchdog;
7329 +
7330 + /* clock control */
7331 + uint32 clockcontrol_n;
7332 + uint32 clockcontrol_sb;
7333 + uint32 clockcontrol_pci;
7334 + uint32 clockcontrol_mii;
7335 + uint32 PAD[3];
7336 +
7337 + /* gpio */
7338 + uint32 gpioin;
7339 + struct gpiouser gpio[NGPIOUSER];
7340 + uint32 PAD;
7341 + uint32 ejtagouten;
7342 + uint32 gpiointpolarity;
7343 + uint32 gpiointmask;
7344 + uint32 PAD[153];
7345 +
7346 + uint8 uartdata;
7347 + uint8 PAD[3];
7348 + uint8 uartimer;
7349 + uint8 PAD[3];
7350 + uint8 uartfcr;
7351 + uint8 PAD[3];
7352 + uint8 uartlcr;
7353 + uint8 PAD[3];
7354 + uint8 uartmcr;
7355 + uint8 PAD[3];
7356 + uint8 uartlsr;
7357 + uint8 PAD[3];
7358 + uint8 uartmsr;
7359 + uint8 PAD[3];
7360 + uint8 uartscratch;
7361 + uint8 PAD[3];
7362 +} extifregs_t;
7363 +
7364 +/* corecontrol */
7365 +#define CC_UE (1 << 0) /* uart enable */
7366 +
7367 +/* extstatus */
7368 +#define ES_EM (1 << 0) /* endian mode (ro) */
7369 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7370 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7371 +
7372 +/* gpio bit mask */
7373 +#define GPIO_BIT0 (1 << 0)
7374 +#define GPIO_BIT1 (1 << 1)
7375 +#define GPIO_BIT2 (1 << 2)
7376 +#define GPIO_BIT3 (1 << 3)
7377 +#define GPIO_BIT4 (1 << 4)
7378 +#define GPIO_BIT5 (1 << 5)
7379 +#define GPIO_BIT6 (1 << 6)
7380 +#define GPIO_BIT7 (1 << 7)
7381 +
7382 +
7383 +/* pcmcia/prog/flash_config */
7384 +#define CF_EN (1 << 0) /* enable */
7385 +#define CF_EM_MASK 0xe /* mode */
7386 +#define CF_EM_SHIFT 1
7387 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7388 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7389 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7390 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7391 +#define CF_BS (1 << 5) /* byteswap */
7392 +#define CF_CD_MASK 0xc0 /* clock divider */
7393 +#define CF_CD_SHIFT 6
7394 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7395 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7396 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7397 +#define CF_CE (1 << 8) /* clock enable */
7398 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7399 +
7400 +/* pcmcia_memwait */
7401 +#define PM_W0_MASK 0x3f /* waitcount0 */
7402 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7403 +#define PM_W1_SHIFT 8
7404 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7405 +#define PM_W2_SHIFT 16
7406 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7407 +#define PM_W3_SHIFT 24
7408 +
7409 +/* pcmcia_attrwait */
7410 +#define PA_W0_MASK 0x3f /* waitcount0 */
7411 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7412 +#define PA_W1_SHIFT 8
7413 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7414 +#define PA_W2_SHIFT 16
7415 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7416 +#define PA_W3_SHIFT 24
7417 +
7418 +/* pcmcia_iowait */
7419 +#define PI_W0_MASK 0x3f /* waitcount0 */
7420 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7421 +#define PI_W1_SHIFT 8
7422 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7423 +#define PI_W2_SHIFT 16
7424 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7425 +#define PI_W3_SHIFT 24
7426 +
7427 +/* prog_waitcount */
7428 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7429 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7430 +#define PW_W1_SHIFT 8
7431 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7432 +#define PW_W2_SHIFT 16
7433 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7434 +#define PW_W3_SHIFT 24
7435 +
7436 +#define PW_W0 0x0000000c
7437 +#define PW_W1 0x00000a00
7438 +#define PW_W2 0x00020000
7439 +#define PW_W3 0x01000000
7440 +
7441 +/* flash_waitcount */
7442 +#define FW_W0_MASK 0x1f /* waitcount0 */
7443 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7444 +#define FW_W1_SHIFT 8
7445 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7446 +#define FW_W2_SHIFT 16
7447 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7448 +#define FW_W3_SHIFT 24
7449 +
7450 +/* watchdog */
7451 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7452 +
7453 +/* clockcontrol_n */
7454 +#define CN_N1_MASK 0x3f /* n1 control */
7455 +#define CN_N2_MASK 0x3f00 /* n2 control */
7456 +#define CN_N2_SHIFT 8
7457 +
7458 +/* clockcontrol_sb/pci/mii */
7459 +#define CC_M1_MASK 0x3f /* m1 control */
7460 +#define CC_M2_MASK 0x3f00 /* m2 control */
7461 +#define CC_M2_SHIFT 8
7462 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7463 +#define CC_M3_SHIFT 16
7464 +#define CC_MC_MASK 0x1f000000 /* mux control */
7465 +#define CC_MC_SHIFT 24
7466 +
7467 +/* Clock control default values */
7468 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7469 +#define CC_DEF_100 0x04020011
7470 +#define CC_DEF_33 0x11030011
7471 +#define CC_DEF_25 0x11050011
7472 +
7473 +/* Clock control values for 125Mhz */
7474 +#define CC_125_N 0x0802
7475 +#define CC_125_M 0x04020009
7476 +#define CC_125_M25 0x11090009
7477 +#define CC_125_M33 0x11090005
7478 +
7479 +/* Clock control magic field values */
7480 +#define CC_F6_2 0x02 /* A factor of 2 in */
7481 +#define CC_F6_3 0x03 /* 6-bit fields like */
7482 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7483 +#define CC_F6_5 0x09
7484 +#define CC_F6_6 0x11
7485 +#define CC_F6_7 0x21
7486 +
7487 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7488 +
7489 +#define CC_MC_BYPASS 0x08
7490 +#define CC_MC_M1 0x04
7491 +#define CC_MC_M1M2 0x02
7492 +#define CC_MC_M1M2M3 0x01
7493 +#define CC_MC_M1M3 0x11
7494 +
7495 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7496 +
7497 +#endif /* _SBEXTIF_H */
7498 diff -urN linux.old/arch/mips/bcm947xx/include/sbhnddma.h linux.dev/arch/mips/bcm947xx/include/sbhnddma.h
7499 --- linux.old/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
7500 +++ linux.dev/arch/mips/bcm947xx/include/sbhnddma.h 2005-11-07 23:37:03.453685750 +0100
7501 @@ -0,0 +1,312 @@
7502 +/*
7503 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
7504 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7505 + *
7506 + * Copyright 2005, Broadcom Corporation
7507 + * All Rights Reserved.
7508 + *
7509 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7510 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7511 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7512 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7513 + * $Id$
7514 + */
7515 +
7516 +#ifndef _sbhnddma_h_
7517 +#define _sbhnddma_h_
7518 +
7519 +
7520 +/* 2byte-wide pio register set per channel(xmt or rcv) */
7521 +typedef volatile struct {
7522 + uint16 fifocontrol;
7523 + uint16 fifodata;
7524 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
7525 + uint16 PAD;
7526 +} pio2regs_t;
7527 +
7528 +/* a pair of pio channels(tx and rx) */
7529 +typedef volatile struct {
7530 + pio2regs_t tx;
7531 + pio2regs_t rx;
7532 +} pio2regp_t;
7533 +
7534 +/* 4byte-wide pio register set per channel(xmt or rcv) */
7535 +typedef volatile struct {
7536 + uint32 fifocontrol;
7537 + uint32 fifodata;
7538 +} pio4regs_t;
7539 +
7540 +/* a pair of pio channels(tx and rx) */
7541 +typedef volatile struct {
7542 + pio4regs_t tx;
7543 + pio4regs_t rx;
7544 +} pio4regp_t;
7545 +
7546 +
7547 +
7548 +/* DMA structure:
7549 + * support two DMA engines: 32 bits address or 64 bit addressing
7550 + * basic DMA register set is per channel(transmit or receive)
7551 + * a pair of channels is defined for convenience
7552 + */
7553 +
7554 +
7555 +/*** 32 bits addressing ***/
7556 +
7557 +/* dma registers per channel(xmt or rcv) */
7558 +typedef volatile struct {
7559 + uint32 control; /* enable, et al */
7560 + uint32 addr; /* descriptor ring base address (4K aligned) */
7561 + uint32 ptr; /* last descriptor posted to chip */
7562 + uint32 status; /* current active descriptor, et al */
7563 +} dma32regs_t;
7564 +
7565 +typedef volatile struct {
7566 + dma32regs_t xmt; /* dma tx channel */
7567 + dma32regs_t rcv; /* dma rx channel */
7568 +} dma32regp_t;
7569 +
7570 +typedef volatile struct { /* diag access */
7571 + uint32 fifoaddr; /* diag address */
7572 + uint32 fifodatalow; /* low 32bits of data */
7573 + uint32 fifodatahigh; /* high 32bits of data */
7574 + uint32 pad; /* reserved */
7575 +} dma32diag_t;
7576 +
7577 +/*
7578 + * DMA Descriptor
7579 + * Descriptors are only read by the hardware, never written back.
7580 + */
7581 +typedef volatile struct {
7582 + uint32 ctrl; /* misc control bits & bufcount */
7583 + uint32 addr; /* data buffer address */
7584 +} dma32dd_t;
7585 +
7586 +/*
7587 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
7588 + */
7589 +#define D32MAXRINGSZ 4096
7590 +#define D32RINGALIGN 4096
7591 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
7592 +
7593 +/* transmit channel control */
7594 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7595 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7596 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7597 +#define XC_FL ((uint32)1 << 4) /* flush request */
7598 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
7599 +#define XC_AE_SHIFT 16
7600 +
7601 +/* transmit descriptor table pointer */
7602 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7603 +
7604 +/* transmit channel status */
7605 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7606 +#define XS_XS_MASK 0xf000 /* transmit state */
7607 +#define XS_XS_SHIFT 12
7608 +#define XS_XS_DISABLED 0x0000 /* disabled */
7609 +#define XS_XS_ACTIVE 0x1000 /* active */
7610 +#define XS_XS_IDLE 0x2000 /* idle wait */
7611 +#define XS_XS_STOPPED 0x3000 /* stopped */
7612 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7613 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7614 +#define XS_XE_SHIFT 16
7615 +#define XS_XE_NOERR 0x00000 /* no error */
7616 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7617 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7618 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7619 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7620 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
7621 +#define XS_AD_SHIFT 20
7622 +
7623 +/* receive channel control */
7624 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7625 +#define RC_RO_MASK 0xfe /* receive frame offset */
7626 +#define RC_RO_SHIFT 1
7627 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7628 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
7629 +#define RC_AE_SHIFT 16
7630 +
7631 +/* receive descriptor table pointer */
7632 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7633 +
7634 +/* receive channel status */
7635 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7636 +#define RS_RS_MASK 0xf000 /* receive state */
7637 +#define RS_RS_SHIFT 12
7638 +#define RS_RS_DISABLED 0x0000 /* disabled */
7639 +#define RS_RS_ACTIVE 0x1000 /* active */
7640 +#define RS_RS_IDLE 0x2000 /* idle wait */
7641 +#define RS_RS_STOPPED 0x3000 /* reserved */
7642 +#define RS_RE_MASK 0xf0000 /* receive errors */
7643 +#define RS_RE_SHIFT 16
7644 +#define RS_RE_NOERR 0x00000 /* no error */
7645 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7646 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7647 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7648 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7649 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
7650 +#define RS_AD_SHIFT 20
7651 +
7652 +/* fifoaddr */
7653 +#define FA_OFF_MASK 0xffff /* offset */
7654 +#define FA_SEL_MASK 0xf0000 /* select */
7655 +#define FA_SEL_SHIFT 16
7656 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7657 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7658 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7659 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7660 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7661 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7662 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7663 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7664 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
7665 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7666 +
7667 +/* descriptor control flags */
7668 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7669 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
7670 +#define CTRL_AE_SHIFT 16
7671 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7672 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7673 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7674 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7675 +
7676 +/* control flags in the range [27:20] are core-specific and not defined here */
7677 +#define CTRL_CORE_MASK 0x0ff00000
7678 +
7679 +/*** 64 bits addressing ***/
7680 +
7681 +/* dma registers per channel(xmt or rcv) */
7682 +typedef volatile struct {
7683 + uint32 control; /* enable, et al */
7684 + uint32 ptr; /* last descriptor posted to chip */
7685 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
7686 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
7687 + uint32 status0; /* current descriptor, xmt state */
7688 + uint32 status1; /* active descriptor, xmt error */
7689 +} dma64regs_t;
7690 +
7691 +typedef volatile struct {
7692 + dma64regs_t tx; /* dma64 tx channel */
7693 + dma64regs_t rx; /* dma64 rx channel */
7694 +} dma64regp_t;
7695 +
7696 +typedef volatile struct { /* diag access */
7697 + uint32 fifoaddr; /* diag address */
7698 + uint32 fifodatalow; /* low 32bits of data */
7699 + uint32 fifodatahigh; /* high 32bits of data */
7700 + uint32 pad; /* reserved */
7701 +} dma64diag_t;
7702 +
7703 +/*
7704 + * DMA Descriptor
7705 + * Descriptors are only read by the hardware, never written back.
7706 + */
7707 +typedef volatile struct {
7708 + uint32 ctrl1; /* misc control bits & bufcount */
7709 + uint32 ctrl2; /* buffer count and address extension */
7710 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
7711 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
7712 +} dma64dd_t;
7713 +
7714 +/*
7715 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
7716 + */
7717 +#define D64MAXRINGSZ 8192
7718 +#define D64RINGALIGN 8192
7719 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
7720 +
7721 +/* transmit channel control */
7722 +#define D64_XC_XE 0x00000001 /* transmit enable */
7723 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
7724 +#define D64_XC_LE 0x00000004 /* loopback enable */
7725 +#define D64_XC_FL 0x00000010 /* flush request */
7726 +#define D64_XC_AE 0x00110000 /* address extension bits */
7727 +#define D64_XC_AE_SHIFT 16
7728 +
7729 +/* transmit descriptor table pointer */
7730 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
7731 +
7732 +/* transmit channel status */
7733 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
7734 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
7735 +#define D64_XS0_XS_SHIFT 28
7736 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
7737 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
7738 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
7739 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
7740 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
7741 +
7742 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
7743 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
7744 +#define D64_XS1_XE_SHIFT 28
7745 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
7746 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
7747 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
7748 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
7749 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
7750 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
7751 +
7752 +/* receive channel control */
7753 +#define D64_RC_RE 0x00000001 /* receive enable */
7754 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
7755 +#define D64_RC_RO_SHIFT 1
7756 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
7757 +#define D64_RC_AE 0x00110000 /* address extension bits */
7758 +#define D64_RC_AE_SHIFT 16
7759 +
7760 +/* receive descriptor table pointer */
7761 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
7762 +
7763 +/* receive channel status */
7764 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
7765 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
7766 +#define D64_RS0_RS_SHIFT 28
7767 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
7768 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
7769 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
7770 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
7771 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
7772 +
7773 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
7774 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
7775 +#define D64_RS1_RE_SHIFT 28
7776 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
7777 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
7778 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
7779 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
7780 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
7781 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
7782 +
7783 +/* fifoaddr */
7784 +#define D64_FA_OFF_MASK 0xffff /* offset */
7785 +#define D64_FA_SEL_MASK 0xf0000 /* select */
7786 +#define D64_FA_SEL_SHIFT 16
7787 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
7788 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
7789 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
7790 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
7791 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
7792 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7793 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
7794 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7795 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
7796 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7797 +
7798 +/* descriptor control flags 1 */
7799 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
7800 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
7801 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
7802 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
7803 +
7804 +/* descriptor control flags 2 */
7805 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
7806 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
7807 +#define D64_CTRL2_AE_SHIFT 16
7808 +
7809 +/* control flags in the range [27:20] are core-specific and not defined here */
7810 +#define D64_CTRL_CORE_MASK 0x0ff00000
7811 +
7812 +
7813 +#endif /* _sbhnddma_h_ */
7814 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7815 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7816 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-11-07 22:51:38.784726500 +0100
7817 @@ -0,0 +1,148 @@
7818 +/*
7819 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7820 + *
7821 + * Copyright 2005, Broadcom Corporation
7822 + * All Rights Reserved.
7823 + *
7824 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7825 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7826 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7827 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7828 + *
7829 + * $Id$
7830 + */
7831 +
7832 +#ifndef _SBMEMC_H
7833 +#define _SBMEMC_H
7834 +
7835 +#ifdef _LANGUAGE_ASSEMBLY
7836 +
7837 +#define MEMC_CONTROL 0x00
7838 +#define MEMC_CONFIG 0x04
7839 +#define MEMC_REFRESH 0x08
7840 +#define MEMC_BISTSTAT 0x0c
7841 +#define MEMC_MODEBUF 0x10
7842 +#define MEMC_BKCLS 0x14
7843 +#define MEMC_PRIORINV 0x18
7844 +#define MEMC_DRAMTIM 0x1c
7845 +#define MEMC_INTSTAT 0x20
7846 +#define MEMC_INTMASK 0x24
7847 +#define MEMC_INTINFO 0x28
7848 +#define MEMC_NCDLCTL 0x30
7849 +#define MEMC_RDNCDLCOR 0x34
7850 +#define MEMC_WRNCDLCOR 0x38
7851 +#define MEMC_MISCDLYCTL 0x3c
7852 +#define MEMC_DQSGATENCDL 0x40
7853 +#define MEMC_SPARE 0x44
7854 +#define MEMC_TPADDR 0x48
7855 +#define MEMC_TPDATA 0x4c
7856 +#define MEMC_BARRIER 0x50
7857 +#define MEMC_CORE 0x54
7858 +
7859 +
7860 +#else
7861 +
7862 +/* Sonics side: MEMC core registers */
7863 +typedef volatile struct sbmemcregs {
7864 + uint32 control;
7865 + uint32 config;
7866 + uint32 refresh;
7867 + uint32 biststat;
7868 + uint32 modebuf;
7869 + uint32 bkcls;
7870 + uint32 priorinv;
7871 + uint32 dramtim;
7872 + uint32 intstat;
7873 + uint32 intmask;
7874 + uint32 intinfo;
7875 + uint32 reserved1;
7876 + uint32 ncdlctl;
7877 + uint32 rdncdlcor;
7878 + uint32 wrncdlcor;
7879 + uint32 miscdlyctl;
7880 + uint32 dqsgatencdl;
7881 + uint32 spare;
7882 + uint32 tpaddr;
7883 + uint32 tpdata;
7884 + uint32 barrier;
7885 + uint32 core;
7886 +} sbmemcregs_t;
7887 +
7888 +#endif
7889 +
7890 +/* MEMC Core Init values (OCP ID 0x80f) */
7891 +
7892 +/* For sdr: */
7893 +#define MEMC_SD_CONFIG_INIT 0x00048000
7894 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7895 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7896 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7897 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7898 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7899 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7900 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7901 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7902 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7903 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7904 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7905 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7906 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7907 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7908 +
7909 +
7910 +/* This is for SDRM8X8X4 */
7911 +#define MEMC_SDR_INIT 0x0008
7912 +#define MEMC_SDR_MODE 0x32
7913 +#define MEMC_SDR_NCDL 0x00020032
7914 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7915 +
7916 +/* For ddr: */
7917 +#define MEMC_CONFIG_INIT 0x00048000
7918 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7919 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7920 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7921 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7922 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7923 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7924 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7925 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7926 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7927 +#define MEMC_NCDLCTL_INIT 0x00002001
7928 +#define MEMC_CONTROL_INIT0 0x00000002
7929 +#define MEMC_CONTROL_INIT1 0x00000008
7930 +#define MEMC_MODEBUF_INIT0 0x00004000
7931 +#define MEMC_CONTROL_INIT2 0x00000010
7932 +#define MEMC_MODEBUF_INIT1 0x00000100
7933 +#define MEMC_CONTROL_INIT3 0x00000010
7934 +#define MEMC_CONTROL_INIT4 0x00000008
7935 +#define MEMC_REFRESH_INIT 0x0000840f
7936 +#define MEMC_CONTROL_INIT5 0x00000004
7937 +#define MEMC_MODEBUF_INIT2 0x00000000
7938 +#define MEMC_CONTROL_INIT6 0x00000010
7939 +#define MEMC_CONTROL_INIT7 0x00000001
7940 +
7941 +
7942 +/* This is for DDRM16X16X2 */
7943 +#define MEMC_DDR_INIT 0x0009
7944 +#define MEMC_DDR_MODE 0x62
7945 +#define MEMC_DDR_NCDL 0x0005050a
7946 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7947 +
7948 +/* mask for sdr/ddr calibration registers */
7949 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7950 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7951 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7952 +
7953 +/* masks for miscdlyctl registers */
7954 +#define MEMC_MISC_SM_MASK 0x30000000
7955 +#define MEMC_MISC_SM_SHIFT 28
7956 +#define MEMC_MISC_SD_MASK 0x0f000000
7957 +#define MEMC_MISC_SD_SHIFT 24
7958 +
7959 +/* hw threshhold for calculating wr/rd for sdr memc */
7960 +#define MEMC_CD_THRESHOLD 128
7961 +
7962 +/* Low bit of init register says if memc is ddr or sdr */
7963 +#define MEMC_CONFIG_DDR 0x00000001
7964 +
7965 +#endif /* _SBMEMC_H */
7966 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
7967 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
7968 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-11-07 22:51:38.784726500 +0100
7969 @@ -0,0 +1,62 @@
7970 +/*
7971 + * Broadcom SiliconBackplane MIPS definitions
7972 + *
7973 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7974 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7975 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7976 + * interface. The core revision is stored in the SB ID register in SB
7977 + * configuration space.
7978 + *
7979 + * Copyright 2005, Broadcom Corporation
7980 + * All Rights Reserved.
7981 + *
7982 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7983 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7984 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7985 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7986 + *
7987 + * $Id$
7988 + */
7989 +
7990 +#ifndef _SBMIPS_H
7991 +#define _SBMIPS_H
7992 +
7993 +#include <mipsinc.h>
7994 +
7995 +#ifndef _LANGUAGE_ASSEMBLY
7996 +
7997 +/* cpp contortions to concatenate w/arg prescan */
7998 +#ifndef PAD
7999 +#define _PADLINE(line) pad ## line
8000 +#define _XSTR(line) _PADLINE(line)
8001 +#define PAD _XSTR(__LINE__)
8002 +#endif /* PAD */
8003 +
8004 +typedef volatile struct {
8005 + uint32 corecontrol;
8006 + uint32 PAD[2];
8007 + uint32 biststatus;
8008 + uint32 PAD[4];
8009 + uint32 intstatus;
8010 + uint32 intmask;
8011 + uint32 timer;
8012 +} mipsregs_t;
8013 +
8014 +extern uint32 sb_flag(sb_t *sbh);
8015 +extern uint sb_irq(sb_t *sbh);
8016 +
8017 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
8018 +
8019 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
8020 +extern void sb_jtagm_disable(void *h);
8021 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
8022 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
8023 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
8024 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
8025 +extern void BCMINIT(enable_pfc)(uint32 mode);
8026 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
8027 +
8028 +
8029 +#endif /* _LANGUAGE_ASSEMBLY */
8030 +
8031 +#endif /* _SBMIPS_H */
8032 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
8033 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
8034 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-11-07 22:51:38.788726750 +0100
8035 @@ -0,0 +1,122 @@
8036 +/*
8037 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
8038 + *
8039 + * $Id$
8040 + * Copyright 2005, Broadcom Corporation
8041 + * All Rights Reserved.
8042 + *
8043 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8044 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8045 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8046 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8047 + */
8048 +
8049 +#ifndef _SBPCI_H
8050 +#define _SBPCI_H
8051 +
8052 +/* cpp contortions to concatenate w/arg prescan */
8053 +#ifndef PAD
8054 +#define _PADLINE(line) pad ## line
8055 +#define _XSTR(line) _PADLINE(line)
8056 +#define PAD _XSTR(__LINE__)
8057 +#endif
8058 +
8059 +/* Sonics side: PCI core and host control registers */
8060 +typedef struct sbpciregs {
8061 + uint32 control; /* PCI control */
8062 + uint32 PAD[3];
8063 + uint32 arbcontrol; /* PCI arbiter control */
8064 + uint32 PAD[3];
8065 + uint32 intstatus; /* Interrupt status */
8066 + uint32 intmask; /* Interrupt mask */
8067 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
8068 + uint32 PAD[9];
8069 + uint32 bcastaddr; /* Sonics broadcast address */
8070 + uint32 bcastdata; /* Sonics broadcast data */
8071 + uint32 PAD[2];
8072 + uint32 gpioin; /* ro: gpio input (>=rev2) */
8073 + uint32 gpioout; /* rw: gpio output (>=rev2) */
8074 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
8075 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
8076 + uint32 PAD[36];
8077 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
8078 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
8079 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
8080 + uint32 PAD[445];
8081 + uint16 sprom[36]; /* SPROM shadow Area */
8082 + uint32 PAD[46];
8083 +} sbpciregs_t;
8084 +
8085 +/* PCI control */
8086 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
8087 +#define PCI_RST 0x02 /* Value driven out to pin */
8088 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
8089 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
8090 +
8091 +/* PCI arbiter control */
8092 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
8093 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
8094 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
8095 +#define PCI_PARKID_SHIFT 1
8096 +#define PCI_PARKID_LAST 0 /* Last requestor */
8097 +#define PCI_PARKID_4710 1 /* 4710 */
8098 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
8099 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
8100 +
8101 +/* Interrupt status/mask */
8102 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
8103 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
8104 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
8105 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
8106 +#define PCI_PME 0x10 /* PCI PME# is asserted */
8107 +
8108 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
8109 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
8110 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
8111 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
8112 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
8113 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
8114 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
8115 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
8116 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
8117 +
8118 +/* Sonics broadcast address */
8119 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
8120 +
8121 +/* Sonics to PCI translation types */
8122 +#define SBTOPCI0_MASK 0xfc000000
8123 +#define SBTOPCI1_MASK 0xfc000000
8124 +#define SBTOPCI2_MASK 0xc0000000
8125 +#define SBTOPCI_MEM 0
8126 +#define SBTOPCI_IO 1
8127 +#define SBTOPCI_CFG0 2
8128 +#define SBTOPCI_CFG1 3
8129 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
8130 +#define SBTOPCI_BURST 0x8 /* burst enable */
8131 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
8132 +#define SBTOPCI_RC_READ 0x00 /* memory read */
8133 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
8134 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
8135 +
8136 +/* PCI core index in SROM shadow area */
8137 +#define SRSH_PI_OFFSET 0 /* first word */
8138 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
8139 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
8140 +
8141 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
8142 +#define cap_list rsvd_a[0]
8143 +#define bar0_window dev_dep[0x80 - 0x40]
8144 +#define bar1_window dev_dep[0x84 - 0x40]
8145 +#define sprom_control dev_dep[0x88 - 0x40]
8146 +
8147 +#ifndef _LANGUAGE_ASSEMBLY
8148 +
8149 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8150 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8151 +extern void sbpci_ban(uint16 core);
8152 +extern int sbpci_init(sb_t *sbh);
8153 +extern void sbpci_check(sb_t *sbh);
8154 +
8155 +#endif /* !_LANGUAGE_ASSEMBLY */
8156 +
8157 +#endif /* _SBPCI_H */
8158 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
8159 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
8160 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2005-11-07 23:39:41.403557000 +0100
8161 @@ -0,0 +1,199 @@
8162 +/*
8163 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
8164 + *
8165 + * $Id:
8166 + * Copyright 2005, Broadcom Corporation
8167 + * All Rights Reserved.
8168 + *
8169 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8170 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8171 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8172 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8173 + */
8174 +
8175 +#ifndef _SBPCIE_H
8176 +#define _SBPCIE_H
8177 +
8178 +/* cpp contortions to concatenate w/arg prescan */
8179 +#ifndef PAD
8180 +#define _PADLINE(line) pad ## line
8181 +#define _XSTR(line) _PADLINE(line)
8182 +#define PAD _XSTR(__LINE__)
8183 +#endif
8184 +
8185 +/* PCIE Enumeration space offsets*/
8186 +#define PCIE_CORE_CONFIG_OFFSET 0x0
8187 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
8188 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
8189 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
8190 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
8191 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
8192 +#define PCIE_SBCONFIG_OFFSET 0xE00
8193 +
8194 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
8195 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
8196 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
8197 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
8198 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
8199 +
8200 +/* SB side: PCIE core and host control registers */
8201 +typedef struct sbpcieregs {
8202 +
8203 + uint32 PAD[3];
8204 + uint32 biststatus; /* bist Status: 0x00C*/
8205 + uint32 PAD[6];
8206 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
8207 + uint32 PAD[54];
8208 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
8209 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
8210 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
8211 + uint32 PAD[4];
8212 +
8213 + /* pcie core supports in direct access to config space */
8214 + uint32 configaddr; /* pcie config space access: Address field: 0x120*/
8215 + uint32 configdata; /* pcie config space access: Data field: 0x124*/
8216 +
8217 + /* mdio access to serdes */
8218 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
8219 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
8220 +
8221 + /* pcie protocol phy/dllp/tlp register access mechanism*/
8222 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
8223 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
8224 +
8225 + uint32 PAD[434];
8226 + uint16 sprom[36]; /* SPROM shadow Area */
8227 +} sbpcieregs_t;
8228 +
8229 +/* SB to PCIE translation masks */
8230 +#define SBTOPCIE0_MASK 0xfc000000
8231 +#define SBTOPCIE1_MASK 0xfc000000
8232 +#define SBTOPCIE2_MASK 0xc0000000
8233 +
8234 +/* Access type bits (0:1)*/
8235 +#define SBTOPCIE_MEM 0
8236 +#define SBTOPCIE_IO 1
8237 +#define SBTOPCIE_CFG0 2
8238 +#define SBTOPCIE_CFG1 3
8239 +
8240 +/*Prefetch enable bit 2*/
8241 +#define SBTOPCIE_PF 4
8242 +
8243 +/*Write Burst enable for memory write bit 3*/
8244 +#define SBTOPCIE_WR_BURST 8
8245 +
8246 +/* config access */
8247 +#define CONFIGADDR_FUNC_MASK 0x7000
8248 +#define CONFIGADDR_FUNC_SHF 12
8249 +#define CONFIGADDR_REG_MASK 0x0FFF
8250 +#define CONFIGADDR_REG_SHF 0
8251 +
8252 +/* PCIE protocol regs Indirect Address */
8253 +#define PCIEADDR_PROT_MASK 0x300
8254 +#define PCIEADDR_PROT_SHF 8
8255 +#define PCIEADDR_PL_TLP 0
8256 +#define PCIEADDR_PL_DLLP 1
8257 +#define PCIEADDR_PL_PLP 2
8258 +
8259 +/* PCIE protocol PHY diagnostic registers */
8260 +#define PCIE_PLP_MODEREG 0x200 /* Mode*/
8261 +#define PCIE_PLP_STATUSREG 0x204 /* Status*/
8262 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
8263 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
8264 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
8265 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
8266 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
8267 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
8268 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
8269 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
8270 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
8271 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
8272 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
8273 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
8274 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
8275 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
8276 +
8277 +/* PCIE protocol DLLP diagnostic registers */
8278 +#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
8279 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
8280 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
8281 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
8282 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
8283 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
8284 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
8285 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
8286 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
8287 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
8288 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
8289 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
8290 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
8291 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
8292 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
8293 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
8294 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
8295 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
8296 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
8297 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
8298 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
8299 +
8300 +/* PCIE protocol TLP diagnostic registers */
8301 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
8302 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
8303 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
8304 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
8305 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
8306 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
8307 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
8308 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
8309 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
8310 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
8311 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
8312 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
8313 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
8314 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
8315 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
8316 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
8317 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
8318 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
8319 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
8320 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
8321 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
8322 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
8323 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
8324 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
8325 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
8326 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
8327 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
8328 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
8329 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
8330 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
8331 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
8332 +
8333 +/* MDIO control */
8334 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
8335 +#define MDIOCTL_DIVISOR_VAL 0x2
8336 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
8337 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
8338 +
8339 +/* MDIO Data */
8340 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
8341 +#define MDIODATA_TA 0x00020000 /* Turnaround */
8342 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
8343 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
8344 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
8345 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
8346 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
8347 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
8348 +#define MDIODATA_START 0x40000000 /* start of Transaction */
8349 +
8350 +/* MDIO devices (SERDES modules) */
8351 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
8352 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
8353 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
8354 +
8355 +/* SERDES registers */
8356 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
8357 +#define SERDES_RX_CDR 6 /* CDR */
8358 +#define SERDES_RX_CDRBW 7 /* CDR BW */
8359 +
8360 +#endif /* _SBPCIE_H */
8361 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
8362 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
8363 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-11-07 22:51:38.788726750 +0100
8364 @@ -0,0 +1,146 @@
8365 +/*
8366 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
8367 + *
8368 + * $Id$
8369 + * Copyright 2005, Broadcom Corporation
8370 + * All Rights Reserved.
8371 + *
8372 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8373 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8374 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8375 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8376 + */
8377 +
8378 +#ifndef _SBPCMCIA_H
8379 +#define _SBPCMCIA_H
8380 +
8381 +
8382 +/* All the addresses that are offsets in attribute space are divided
8383 + * by two to account for the fact that odd bytes are invalid in
8384 + * attribute space and our read/write routines make the space appear
8385 + * as if they didn't exist. Still we want to show the original numbers
8386 + * as documented in the hnd_pcmcia core manual.
8387 + */
8388 +
8389 +/* PCMCIA Function Configuration Registers */
8390 +#define PCMCIA_FCR (0x700 / 2)
8391 +
8392 +#define FCR0_OFF 0
8393 +#define FCR1_OFF (0x40 / 2)
8394 +#define FCR2_OFF (0x80 / 2)
8395 +#define FCR3_OFF (0xc0 / 2)
8396 +
8397 +#define PCMCIA_FCR0 (0x700 / 2)
8398 +#define PCMCIA_FCR1 (0x740 / 2)
8399 +#define PCMCIA_FCR2 (0x780 / 2)
8400 +#define PCMCIA_FCR3 (0x7c0 / 2)
8401 +
8402 +/* Standard PCMCIA FCR registers */
8403 +
8404 +#define PCMCIA_COR 0
8405 +
8406 +#define COR_RST 0x80
8407 +#define COR_LEV 0x40
8408 +#define COR_IRQEN 0x04
8409 +#define COR_BLREN 0x01
8410 +#define COR_FUNEN 0x01
8411 +
8412 +
8413 +#define PCICIA_FCSR (2 / 2)
8414 +#define PCICIA_PRR (4 / 2)
8415 +#define PCICIA_SCR (6 / 2)
8416 +#define PCICIA_ESR (8 / 2)
8417 +
8418 +
8419 +#define PCM_MEMOFF 0x0000
8420 +#define F0_MEMOFF 0x1000
8421 +#define F1_MEMOFF 0x2000
8422 +#define F2_MEMOFF 0x3000
8423 +#define F3_MEMOFF 0x4000
8424 +
8425 +/* Memory base in the function fcr's */
8426 +#define MEM_ADDR0 (0x728 / 2)
8427 +#define MEM_ADDR1 (0x72a / 2)
8428 +#define MEM_ADDR2 (0x72c / 2)
8429 +
8430 +/* PCMCIA base plus Srom access in fcr0: */
8431 +#define PCMCIA_ADDR0 (0x072e / 2)
8432 +#define PCMCIA_ADDR1 (0x0730 / 2)
8433 +#define PCMCIA_ADDR2 (0x0732 / 2)
8434 +
8435 +#define MEM_SEG (0x0734 / 2)
8436 +#define SROM_CS (0x0736 / 2)
8437 +#define SROM_DATAL (0x0738 / 2)
8438 +#define SROM_DATAH (0x073a / 2)
8439 +#define SROM_ADDRL (0x073c / 2)
8440 +#define SROM_ADDRH (0x073e / 2)
8441 +
8442 +/* Values for srom_cs: */
8443 +#define SROM_IDLE 0
8444 +#define SROM_WRITE 1
8445 +#define SROM_READ 2
8446 +#define SROM_WEN 4
8447 +#define SROM_WDS 7
8448 +#define SROM_DONE 8
8449 +
8450 +/* CIS stuff */
8451 +
8452 +/* The CIS stops where the FCRs start */
8453 +#define CIS_SIZE PCMCIA_FCR
8454 +
8455 +/* Standard tuples we know about */
8456 +
8457 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
8458 +#define CISTPL_FUNCE 0x22 /* Function extensions */
8459 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
8460 +
8461 +/* Function extensions for LANs */
8462 +
8463 +#define LAN_TECH 1 /* Technology type */
8464 +#define LAN_SPEED 2 /* Raw bit rate */
8465 +#define LAN_MEDIA 3 /* Transmission media */
8466 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
8467 +#define LAN_CONN 5 /* Connector standard */
8468 +
8469 +
8470 +/* CFTable */
8471 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
8472 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
8473 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
8474 +
8475 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
8476 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
8477 + */
8478 +
8479 +#define CISTPL_BRCM_HNBU 0x80
8480 +
8481 +/* Subtypes of BRCM_HNBU: */
8482 +
8483 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
8484 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
8485 + * device id and chiprev
8486 + */
8487 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
8488 +#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
8489 + * or 9 (sromrev > 1) bytes */
8490 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
8491 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
8492 +#define HNBU_AA 0x06 /* Antennas available */
8493 +#define HNBU_AG 0x07 /* Antenna gain */
8494 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
8495 +#define HNBU_LEDS 0x09 /* LED set */
8496 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
8497 + * in rev 2
8498 + */
8499 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
8500 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
8501 +
8502 +
8503 +/* sbtmstatelow */
8504 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
8505 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
8506 +
8507 +/* sbtmstatehigh */
8508 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
8509 +
8510 +#endif /* _SBPCMCIA_H */
8511 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
8512 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
8513 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-11-07 21:57:07.877587750 +0100
8514 @@ -0,0 +1,75 @@
8515 +/*
8516 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
8517 + *
8518 + * Copyright 2005, Broadcom Corporation
8519 + * All Rights Reserved.
8520 + *
8521 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8522 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8523 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8524 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8525 + * $Id$
8526 + */
8527 +
8528 +#ifndef _SBSDRAM_H
8529 +#define _SBSDRAM_H
8530 +
8531 +#ifndef _LANGUAGE_ASSEMBLY
8532 +
8533 +/* Sonics side: SDRAM core registers */
8534 +typedef volatile struct sbsdramregs {
8535 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
8536 + uint32 config; /* Initializes external SDRAM mode register */
8537 + uint32 refresh; /* Controls external SDRAM refresh rate */
8538 + uint32 pad1;
8539 + uint32 pad2;
8540 +} sbsdramregs_t;
8541 +
8542 +#endif
8543 +
8544 +/* SDRAM initialization control (initcontrol) register bits */
8545 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
8546 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
8547 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
8548 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
8549 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
8550 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
8551 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
8552 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
8553 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
8554 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
8555 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
8556 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
8557 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
8558 +
8559 +/* SDRAM configuration (config) register bits */
8560 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
8561 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
8562 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
8563 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
8564 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
8565 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
8566 +
8567 +/* SDRAM refresh control (refresh) register bits */
8568 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
8569 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
8570 +
8571 +/* SDRAM Core default Init values (OCP ID 0x803) */
8572 +#define SDRAM_INIT MEM4MX16X2
8573 +#define SDRAM_CONFIG SDRAM_BURSTFULL
8574 +#define SDRAM_REFRESH SDRAM_REF(0x40)
8575 +
8576 +#define MEM1MX16 0x009 /* 2 MB */
8577 +#define MEM1MX16X2 0x409 /* 4 MB */
8578 +#define MEM2MX8X2 0x809 /* 4 MB */
8579 +#define MEM2MX8X4 0xc09 /* 8 MB */
8580 +#define MEM2MX32 0x439 /* 8 MB */
8581 +#define MEM4MX16 0x019 /* 8 MB */
8582 +#define MEM4MX16X2 0x419 /* 16 MB */
8583 +#define MEM8MX8X2 0x819 /* 16 MB */
8584 +#define MEM8MX16 0x829 /* 16 MB */
8585 +#define MEM4MX32 0x429 /* 16 MB */
8586 +#define MEM8MX8X4 0xc19 /* 32 MB */
8587 +#define MEM8MX16X2 0xc29 /* 32 MB */
8588 +
8589 +#endif /* _SBSDRAM_H */
8590 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
8591 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
8592 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-11-07 21:57:07.877587750 +0100
8593 @@ -0,0 +1,37 @@
8594 +/*
8595 + * BCM47XX Sonics SiliconBackplane embedded ram core
8596 + *
8597 + * Copyright 2005, Broadcom Corporation
8598 + * All Rights Reserved.
8599 + *
8600 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8601 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8602 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8603 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8604 + *
8605 + * $Id$
8606 + */
8607 +
8608 +#ifndef _SBSOCRAM_H
8609 +#define _SBSOCRAM_H
8610 +
8611 +#define SOCRAM_MEMSIZE 0x00
8612 +#define SOCRAM_BISTSTAT 0x0c
8613 +
8614 +
8615 +#ifndef _LANGUAGE_ASSEMBLY
8616 +
8617 +/* Memcsocram core registers */
8618 +typedef volatile struct sbsocramregs {
8619 + uint32 memsize;
8620 + uint32 biststat;
8621 +} sbsocramregs_t;
8622 +
8623 +#endif
8624 +
8625 +/* Them memory size is 2 to the power of the following
8626 + * base added to the contents of the memsize register.
8627 + */
8628 +#define SOCRAM_MEMSIZE_BASESHIFT 16
8629 +
8630 +#endif /* _SBSOCRAM_H */
8631 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8632 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8633 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-11-07 22:51:38.788726750 +0100
8634 @@ -0,0 +1,140 @@
8635 +/*
8636 + * Misc utility routines for accessing chip-specific features
8637 + * of Broadcom HNBU SiliconBackplane-based chips.
8638 + *
8639 + * Copyright 2005, Broadcom Corporation
8640 + * All Rights Reserved.
8641 + *
8642 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8643 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8644 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8645 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8646 + *
8647 + * $Id$
8648 + */
8649 +
8650 +#ifndef _sbutils_h_
8651 +#define _sbutils_h_
8652 +
8653 +/*
8654 + * Datastructure to export all chip specific common variables
8655 + * public (read-only) portion of sbutils handle returned by
8656 + * sb_attach()/sb_kattach()
8657 +*/
8658 +
8659 +struct sb_pub {
8660 +
8661 + uint bustype; /* SB_BUS, PCI_BUS */
8662 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
8663 + uint buscorerev; /* buscore rev */
8664 + uint buscoreidx; /* buscore index */
8665 + int ccrev; /* chip common core rev */
8666 + uint boardtype; /* board type */
8667 + uint boardvendor; /* board vendor */
8668 + uint chip; /* chip number */
8669 + uint chiprev; /* chip revision */
8670 + uint chippkg; /* chip package option */
8671 + uint sonicsrev; /* sonics backplane rev */
8672 +};
8673 +
8674 +typedef const struct sb_pub sb_t;
8675 +
8676 +/*
8677 + * Many of the routines below take an 'sbh' handle as their first arg.
8678 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8679 + * At any one time, the sbh is logically focused on one particular sb core
8680 + * (the "current core").
8681 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8682 + */
8683 +
8684 +/* exported externs */
8685 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
8686 +extern sb_t * BCMINIT(sb_kattach)(void);
8687 +extern void sb_detach(sb_t *sbh);
8688 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
8689 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
8690 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
8691 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
8692 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
8693 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
8694 +extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
8695 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
8696 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
8697 +extern uint sb_bus(sb_t *sbh);
8698 +extern uint sb_buscoretype(sb_t *sbh);
8699 +extern uint sb_buscorerev(sb_t *sbh);
8700 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8701 +extern uint sb_coreid(sb_t *sbh);
8702 +extern uint sb_coreidx(sb_t *sbh);
8703 +extern uint sb_coreunit(sb_t *sbh);
8704 +extern uint sb_corevendor(sb_t *sbh);
8705 +extern uint sb_corerev(sb_t *sbh);
8706 +extern void *sb_osh(sb_t *sbh);
8707 +extern void *sb_coreregs(sb_t *sbh);
8708 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8709 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8710 +extern bool sb_iscoreup(sb_t *sbh);
8711 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8712 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8713 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
8714 +extern void sb_commit(sb_t *sbh);
8715 +extern uint32 sb_base(uint32 admatch);
8716 +extern uint32 sb_size(uint32 admatch);
8717 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
8718 +extern void sb_core_tofixup(sb_t *sbh);
8719 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8720 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8721 +extern uint32 sb_clock(sb_t *sbh);
8722 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8723 +extern void sb_pcmcia_init(sb_t *sbh);
8724 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8725 +extern void *sb_gpiosetcore(sb_t *sbh);
8726 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8727 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8728 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8729 +extern uint32 sb_gpioin(sb_t *sbh);
8730 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8731 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8732 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8733 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8734 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8735 +
8736 +extern void sb_clkctl_init(sb_t *sbh);
8737 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8738 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8739 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8740 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
8741 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
8742 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8743 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
8744 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
8745 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8746 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8747 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8748 +
8749 +
8750 +
8751 +/*
8752 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8753 +* The returned path is NULL terminated and has trailing '/'.
8754 +* Return 0 on success, nonzero otherwise.
8755 +*/
8756 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8757 +
8758 +/* clkctl xtal what flags */
8759 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8760 +#define PLL 0x2 /* main chip pll */
8761 +
8762 +/* clkctl clk mode */
8763 +#define CLK_FAST 0 /* force fast (pll) clock */
8764 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8765 +
8766 +
8767 +/* GPIO usage priorities */
8768 +#define GPIO_DRV_PRIORITY 0
8769 +#define GPIO_APP_PRIORITY 1
8770 +
8771 +/* device path */
8772 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8773 +
8774 +#endif /* _sbutils_h_ */
8775 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8776 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8777 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-11-07 21:57:07.881588000 +0100
8778 @@ -0,0 +1,36 @@
8779 +/*
8780 + * Broadcom SiliconBackplane chipcommon serial flash interface
8781 + *
8782 + * Copyright 2005, Broadcom Corporation
8783 + * All Rights Reserved.
8784 + *
8785 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8786 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8787 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8788 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8789 + *
8790 + * $Id$
8791 + */
8792 +
8793 +#ifndef _sflash_h_
8794 +#define _sflash_h_
8795 +
8796 +#include <typedefs.h>
8797 +#include <sbchipc.h>
8798 +
8799 +struct sflash {
8800 + uint blocksize; /* Block size */
8801 + uint numblocks; /* Number of blocks */
8802 + uint32 type; /* Type */
8803 + uint size; /* Total size in bytes */
8804 +};
8805 +
8806 +/* Utility functions */
8807 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8808 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8809 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8810 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8811 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8812 +extern struct sflash * sflash_init(chipcregs_t *cc);
8813 +
8814 +#endif /* _sflash_h_ */
8815 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8816 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8817 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-11-07 21:57:07.881588000 +0100
8818 @@ -0,0 +1,33 @@
8819 +/*
8820 + * TRX image file header format.
8821 + *
8822 + * Copyright 2005, Broadcom Corporation
8823 + * All Rights Reserved.
8824 + *
8825 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8826 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8827 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8828 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8829 + *
8830 + * $Id$
8831 + */
8832 +
8833 +#include <typedefs.h>
8834 +
8835 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8836 +#define TRX_VERSION 1
8837 +#define TRX_MAX_LEN 0x3A0000
8838 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8839 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8840 +#define TRX_MAX_OFFSET 3
8841 +
8842 +struct trx_header {
8843 + uint32 magic; /* "HDR0" */
8844 + uint32 len; /* Length of file including header */
8845 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8846 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8847 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8848 +};
8849 +
8850 +/* Compatibility */
8851 +typedef struct trx_header TRXHDR, *PTRXHDR;
8852 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8853 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8854 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-11-07 22:51:38.788726750 +0100
8855 @@ -0,0 +1,326 @@
8856 +/*
8857 + * Copyright 2005, Broadcom Corporation
8858 + * All Rights Reserved.
8859 + *
8860 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8861 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8862 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8863 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8864 + * $Id$
8865 + */
8866 +
8867 +#ifndef _TYPEDEFS_H_
8868 +#define _TYPEDEFS_H_
8869 +
8870 +
8871 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8872 + * typedef file "site_typedefs.h".
8873 + *
8874 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8875 + * section of this file makes inferences about the compile environment
8876 + * based on defined symbols and possibly compiler pragmas.
8877 + *
8878 + * Following these two sections is the "Default Typedefs"
8879 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8880 + * defined. This section has a default set of typedefs and a few
8881 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8882 + */
8883 +
8884 +#ifdef SITE_TYPEDEFS
8885 +
8886 +/*******************************************************************************
8887 + * Site Specific Typedefs
8888 + *******************************************************************************/
8889 +
8890 +#include "site_typedefs.h"
8891 +
8892 +#else
8893 +
8894 +/*******************************************************************************
8895 + * Inferred Typedefs
8896 + *******************************************************************************/
8897 +
8898 +/* Infer the compile environment based on preprocessor symbols and pramas.
8899 + * Override type definitions as needed, and include configuration dependent
8900 + * header files to define types.
8901 + */
8902 +
8903 +#ifdef __cplusplus
8904 +
8905 +#define TYPEDEF_BOOL
8906 +#ifndef FALSE
8907 +#define FALSE false
8908 +#endif
8909 +#ifndef TRUE
8910 +#define TRUE true
8911 +#endif
8912 +
8913 +#else /* ! __cplusplus */
8914 +
8915 +#if defined(_WIN32)
8916 +
8917 +#define TYPEDEF_BOOL
8918 +typedef unsigned char bool; /* consistent w/BOOL */
8919 +
8920 +#endif /* _WIN32 */
8921 +
8922 +#endif /* ! __cplusplus */
8923 +
8924 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8925 +#if defined(_WIN64)
8926 +#include <basetsd.h>
8927 +#define TYPEDEF_UINTPTR
8928 +typedef ULONG_PTR uintptr;
8929 +#endif
8930 +
8931 +#ifdef _HNDRTE_
8932 +typedef long unsigned int size_t;
8933 +#endif
8934 +
8935 +#ifdef _MSC_VER /* Microsoft C */
8936 +#define TYPEDEF_INT64
8937 +#define TYPEDEF_UINT64
8938 +typedef signed __int64 int64;
8939 +typedef unsigned __int64 uint64;
8940 +#endif
8941 +
8942 +#if defined(MACOSX) && defined(KERNEL)
8943 +#define TYPEDEF_BOOL
8944 +#endif
8945 +
8946 +
8947 +#if defined(linux)
8948 +#define TYPEDEF_UINT
8949 +#define TYPEDEF_USHORT
8950 +#define TYPEDEF_ULONG
8951 +#endif
8952 +
8953 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8954 +#define TYPEDEF_UINT
8955 +#define TYPEDEF_USHORT
8956 +#endif
8957 +
8958 +
8959 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8960 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8961 +#define TYPEDEF_INT64
8962 +#define TYPEDEF_UINT64
8963 +#endif
8964 +
8965 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8966 + * for singned or unsigned */
8967 +#if defined(__ICL)
8968 +
8969 +#define TYPEDEF_INT64
8970 +
8971 +#if defined(__STDC__)
8972 +#define TYPEDEF_UINT64
8973 +#endif
8974 +
8975 +#endif /* __ICL */
8976 +
8977 +
8978 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8979 +
8980 +/* pick up ushort & uint from standard types.h */
8981 +#if defined(linux) && defined(__KERNEL__)
8982 +
8983 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8984 +
8985 +#else
8986 +
8987 +#include <sys/types.h>
8988 +
8989 +#endif
8990 +
8991 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
8992 +
8993 +#if defined(MACOSX) && defined(KERNEL)
8994 +#include <IOKit/IOTypes.h>
8995 +#endif
8996 +
8997 +
8998 +/* use the default typedefs in the next section of this file */
8999 +#define USE_TYPEDEF_DEFAULTS
9000 +
9001 +#endif /* SITE_TYPEDEFS */
9002 +
9003 +
9004 +/*******************************************************************************
9005 + * Default Typedefs
9006 + *******************************************************************************/
9007 +
9008 +#ifdef USE_TYPEDEF_DEFAULTS
9009 +#undef USE_TYPEDEF_DEFAULTS
9010 +
9011 +#ifndef TYPEDEF_BOOL
9012 +typedef /*@abstract@*/ unsigned char bool;
9013 +#endif
9014 +
9015 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
9016 +
9017 +#ifndef TYPEDEF_UCHAR
9018 +typedef unsigned char uchar;
9019 +#endif
9020 +
9021 +#ifndef TYPEDEF_USHORT
9022 +typedef unsigned short ushort;
9023 +#endif
9024 +
9025 +#ifndef TYPEDEF_UINT
9026 +typedef unsigned int uint;
9027 +#endif
9028 +
9029 +#ifndef TYPEDEF_ULONG
9030 +typedef unsigned long ulong;
9031 +#endif
9032 +
9033 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
9034 +
9035 +#ifndef TYPEDEF_UINT8
9036 +typedef unsigned char uint8;
9037 +#endif
9038 +
9039 +#ifndef TYPEDEF_UINT16
9040 +typedef unsigned short uint16;
9041 +#endif
9042 +
9043 +#ifndef TYPEDEF_UINT32
9044 +typedef unsigned int uint32;
9045 +#endif
9046 +
9047 +#ifndef TYPEDEF_UINT64
9048 +typedef unsigned long long uint64;
9049 +#endif
9050 +
9051 +#ifndef TYPEDEF_UINTPTR
9052 +typedef unsigned int uintptr;
9053 +#endif
9054 +
9055 +#ifndef TYPEDEF_INT8
9056 +typedef signed char int8;
9057 +#endif
9058 +
9059 +#ifndef TYPEDEF_INT16
9060 +typedef signed short int16;
9061 +#endif
9062 +
9063 +#ifndef TYPEDEF_INT32
9064 +typedef signed int int32;
9065 +#endif
9066 +
9067 +#ifndef TYPEDEF_INT64
9068 +typedef signed long long int64;
9069 +#endif
9070 +
9071 +/*----------------------- define float32/64, float_t -----------------------*/
9072 +
9073 +#ifndef TYPEDEF_FLOAT32
9074 +typedef float float32;
9075 +#endif
9076 +
9077 +#ifndef TYPEDEF_FLOAT64
9078 +typedef double float64;
9079 +#endif
9080 +
9081 +/*
9082 + * abstracted floating point type allows for compile time selection of
9083 + * single or double precision arithmetic. Compiling with -DFLOAT32
9084 + * selects single precision; the default is double precision.
9085 + */
9086 +
9087 +#ifndef TYPEDEF_FLOAT_T
9088 +
9089 +#if defined(FLOAT32)
9090 +typedef float32 float_t;
9091 +#else /* default to double precision floating point */
9092 +typedef float64 float_t;
9093 +#endif
9094 +
9095 +#endif /* TYPEDEF_FLOAT_T */
9096 +
9097 +/*----------------------- define macro values -----------------------------*/
9098 +
9099 +#ifndef FALSE
9100 +#define FALSE 0
9101 +#endif
9102 +
9103 +#ifndef TRUE
9104 +#define TRUE 1
9105 +#endif
9106 +
9107 +#ifndef NULL
9108 +#define NULL 0
9109 +#endif
9110 +
9111 +#ifndef OFF
9112 +#define OFF 0
9113 +#endif
9114 +
9115 +#ifndef ON
9116 +#define ON 1
9117 +#endif
9118 +
9119 +#define AUTO (-1)
9120 +
9121 +/* Reclaiming text and data :
9122 + The following macros specify special linker sections that can be reclaimed
9123 + after a system is considered 'up'.
9124 + */
9125 +#if defined(__GNUC__) && defined(BCMRECLAIM)
9126 +extern bool bcmreclaimed;
9127 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
9128 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
9129 +#define BCMINIT(_id) _id##_ini
9130 +#else
9131 +#define BCMINITDATA(_data) _data
9132 +#define BCMINITFN(_fn) _fn
9133 +#define BCMINIT(_id) _id
9134 +#define bcmreclaimed 0
9135 +#endif
9136 +
9137 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
9138 +
9139 +#ifndef PTRSZ
9140 +#define PTRSZ sizeof (char*)
9141 +#endif
9142 +
9143 +#ifndef INLINE
9144 +
9145 +#ifdef _MSC_VER
9146 +
9147 +#define INLINE __inline
9148 +
9149 +#elif __GNUC__
9150 +
9151 +#define INLINE __inline__
9152 +
9153 +#else
9154 +
9155 +#define INLINE
9156 +
9157 +#endif /* _MSC_VER */
9158 +
9159 +#endif /* INLINE */
9160 +
9161 +#undef TYPEDEF_BOOL
9162 +#undef TYPEDEF_UCHAR
9163 +#undef TYPEDEF_USHORT
9164 +#undef TYPEDEF_UINT
9165 +#undef TYPEDEF_ULONG
9166 +#undef TYPEDEF_UINT8
9167 +#undef TYPEDEF_UINT16
9168 +#undef TYPEDEF_UINT32
9169 +#undef TYPEDEF_UINT64
9170 +#undef TYPEDEF_UINTPTR
9171 +#undef TYPEDEF_INT8
9172 +#undef TYPEDEF_INT16
9173 +#undef TYPEDEF_INT32
9174 +#undef TYPEDEF_INT64
9175 +#undef TYPEDEF_FLOAT32
9176 +#undef TYPEDEF_FLOAT64
9177 +#undef TYPEDEF_FLOAT_T
9178 +
9179 +#endif /* USE_TYPEDEF_DEFAULTS */
9180 +
9181 +#endif /* _TYPEDEFS_H_ */
9182 diff -urN linux.old/arch/mips/bcm947xx/include/wlioctl.h linux.dev/arch/mips/bcm947xx/include/wlioctl.h
9183 --- linux.old/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
9184 +++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-11-07 22:51:38.792727000 +0100
9185 @@ -0,0 +1,1030 @@
9186 +/*
9187 + * Custom OID/ioctl definitions for
9188 + * Broadcom 802.11abg Networking Device Driver
9189 + *
9190 + * Definitions subject to change without notice.
9191 + *
9192 + * Copyright 2005, Broadcom Corporation
9193 + * All Rights Reserved.
9194 + *
9195 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9196 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9197 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9198 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9199 + *
9200 + * $Id$
9201 + */
9202 +
9203 +#ifndef _wlioctl_h_
9204 +#define _wlioctl_h_
9205 +
9206 +#include <typedefs.h>
9207 +#include <proto/ethernet.h>
9208 +#include <proto/bcmeth.h>
9209 +#include <proto/bcmevent.h>
9210 +#include <proto/802.11.h>
9211 +
9212 +/* require default structure packing */
9213 +#if !defined(__GNUC__)
9214 +#pragma pack(push,8)
9215 +#endif
9216 +
9217 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
9218 +
9219 +typedef struct wl_rateset {
9220 + uint32 count; /* # rates in this set */
9221 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
9222 +} wl_rateset_t;
9223 +
9224 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
9225 +#define WL_CHANSPEC_BAND_MASK 0xf000
9226 +#define WL_CHANSPEC_BAND_SHIFT 12
9227 +#define WL_CHANSPEC_BAND_A 0x1000
9228 +#define WL_CHANSPEC_BAND_B 0x2000
9229 +
9230 +/*
9231 + * Per-bss information structure.
9232 + */
9233 +
9234 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
9235 +
9236 +typedef struct wl_bss_info {
9237 + uint32 version; /* version field */
9238 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
9239 + struct ether_addr BSSID;
9240 + uint16 beacon_period; /* units are Kusec */
9241 + uint16 capability; /* Capability information */
9242 + uint8 SSID_len;
9243 + uint8 SSID[32];
9244 + struct {
9245 + uint count; /* # rates in this set */
9246 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
9247 + } rateset; /* supported rates */
9248 + uint8 channel; /* Channel no. */
9249 + uint16 atim_window; /* units are Kusec */
9250 + uint8 dtim_period; /* DTIM period */
9251 + int16 RSSI; /* receive signal strength (in dBm) */
9252 + int8 phy_noise; /* noise (in dBm) */
9253 + uint32 ie_length; /* byte length of Information Elements */
9254 + /* variable length Information Elements */
9255 +} wl_bss_info_t;
9256 +
9257 +typedef struct wlc_ssid {
9258 + uint32 SSID_len;
9259 + uchar SSID[32];
9260 +} wlc_ssid_t;
9261 +
9262 +typedef struct wl_scan_params {
9263 + wlc_ssid_t ssid; /* default is {0, ""} */
9264 + struct ether_addr bssid;/* default is bcast */
9265 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
9266 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
9267 + int32 nprobes; /* -1 use default, number of probes per channel */
9268 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
9269 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
9270 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
9271 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
9272 + uint16 channel_list[1]; /* list of chanspecs */
9273 +} wl_scan_params_t;
9274 +/* size of wl_scan_params not including variable length array */
9275 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
9276 +
9277 +typedef struct wl_scan_results {
9278 + uint32 buflen;
9279 + uint32 version;
9280 + uint32 count;
9281 + wl_bss_info_t bss_info[1];
9282 +} wl_scan_results_t;
9283 +/* size of wl_scan_results not including variable length array */
9284 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
9285 +
9286 +/* uint32 list */
9287 +typedef struct wl_uint32_list {
9288 + /* in - # of elements, out - # of entries */
9289 + uint32 count;
9290 + /* variable length uint32 list */
9291 + uint32 element[1];
9292 +} wl_uint32_list_t;
9293 +
9294 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
9295 +
9296 +typedef struct wl_channels_in_country {
9297 + uint32 buflen;
9298 + uint32 band;
9299 + char country_abbrev[WLC_CNTRY_BUF_SZ];
9300 + uint32 count;
9301 + uint32 channel[1];
9302 +} wl_channels_in_country_t;
9303 +
9304 +typedef struct wl_country_list {
9305 + uint32 buflen;
9306 + uint32 band_set;
9307 + uint32 band;
9308 + uint32 count;
9309 + char country_abbrev[1];
9310 +} wl_country_list_t;
9311 +
9312 +#define WL_RM_TYPE_BASIC 1
9313 +#define WL_RM_TYPE_CCA 2
9314 +#define WL_RM_TYPE_RPI 3
9315 +
9316 +#define WL_RM_FLAG_PARALLEL (1<<0)
9317 +
9318 +#define WL_RM_FLAG_LATE (1<<1)
9319 +#define WL_RM_FLAG_INCAPABLE (1<<2)
9320 +#define WL_RM_FLAG_REFUSED (1<<3)
9321 +
9322 +typedef struct wl_rm_req_elt {
9323 + int8 type;
9324 + int8 flags;
9325 + uint16 chanspec;
9326 + uint32 token; /* token for this measurement */
9327 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9328 + uint32 tsf_l; /* TSF low 32-bits */
9329 + uint32 dur; /* TUs */
9330 +} wl_rm_req_elt_t;
9331 +
9332 +typedef struct wl_rm_req {
9333 + uint32 token; /* overall measurement set token */
9334 + uint32 count; /* number of measurement reqests */
9335 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
9336 +} wl_rm_req_t;
9337 +#define WL_RM_REQ_FIXED_LEN 8
9338 +
9339 +typedef struct wl_rm_rep_elt {
9340 + int8 type;
9341 + int8 flags;
9342 + uint16 chanspec;
9343 + uint32 token; /* token for this measurement */
9344 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9345 + uint32 tsf_l; /* TSF low 32-bits */
9346 + uint32 dur; /* TUs */
9347 + uint32 len; /* byte length of data block */
9348 + uint8 data[1]; /* variable length data block */
9349 +} wl_rm_rep_elt_t;
9350 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
9351 +
9352 +#define WL_RPI_REP_BIN_NUM 8
9353 +typedef struct wl_rm_rpi_rep {
9354 + uint8 rpi[WL_RPI_REP_BIN_NUM];
9355 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
9356 +} wl_rm_rpi_rep_t;
9357 +
9358 +typedef struct wl_rm_rep {
9359 + uint32 token; /* overall measurement set token */
9360 + uint32 len; /* length of measurement report block */
9361 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
9362 +} wl_rm_rep_t;
9363 +#define WL_RM_REP_FIXED_LEN 8
9364 +
9365 +
9366 +#if defined(BCMSUP_PSK)
9367 +typedef enum sup_auth_status {
9368 + WLC_SUP_DISCONNECTED = 0,
9369 + WLC_SUP_CONNECTING,
9370 + WLC_SUP_IDREQUIRED,
9371 + WLC_SUP_AUTHENTICATING,
9372 + WLC_SUP_AUTHENTICATED,
9373 + WLC_SUP_KEYXCHANGE,
9374 + WLC_SUP_KEYED,
9375 + WLC_SUP_TIMEOUT
9376 +} sup_auth_status_t;
9377 +#endif /* BCMCCX | BCMSUP_PSK */
9378 +
9379 +/* Enumerate crypto algorithms */
9380 +#define CRYPTO_ALGO_OFF 0
9381 +#define CRYPTO_ALGO_WEP1 1
9382 +#define CRYPTO_ALGO_TKIP 2
9383 +#define CRYPTO_ALGO_WEP128 3
9384 +#define CRYPTO_ALGO_AES_CCM 4
9385 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
9386 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
9387 +#define CRYPTO_ALGO_NALG 7
9388 +
9389 +#define WSEC_GEN_MIC_ERROR 0x0001
9390 +#define WSEC_GEN_REPLAY 0x0002
9391 +
9392 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
9393 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
9394 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
9395 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
9396 +
9397 +typedef struct wl_wsec_key {
9398 + uint32 index; /* key index */
9399 + uint32 len; /* key length */
9400 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
9401 + uint32 pad_1[18];
9402 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
9403 + uint32 flags; /* misc flags */
9404 + uint32 pad_2[2];
9405 + int pad_3;
9406 + int iv_initialized; /* has IV been initialized already? */
9407 + int pad_4;
9408 + /* Rx IV */
9409 + struct {
9410 + uint32 hi; /* upper 32 bits of IV */
9411 + uint16 lo; /* lower 16 bits of IV */
9412 + } rxiv;
9413 + uint32 pad_5[2];
9414 + struct ether_addr ea; /* per station */
9415 +} wl_wsec_key_t;
9416 +
9417 +
9418 +#define WSEC_MIN_PSK_LEN 8
9419 +#define WSEC_MAX_PSK_LEN 64
9420 +
9421 +/* Flag for key material needing passhash'ing */
9422 +#define WSEC_PASSPHRASE (1<<0)
9423 +
9424 +/* recepticle for WLC_SET_WSEC_PMK parameter */
9425 +typedef struct {
9426 + ushort key_len; /* octets in key material */
9427 + ushort flags; /* key handling qualification */
9428 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
9429 +} wsec_pmk_t;
9430 +
9431 +/* wireless security bitvec */
9432 +#define WEP_ENABLED 0x0001
9433 +#define TKIP_ENABLED 0x0002
9434 +#define AES_ENABLED 0x0004
9435 +#define WSEC_SWFLAG 0x0008
9436 +#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
9437 +
9438 +/* WPA authentication mode bitvec */
9439 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
9440 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
9441 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
9442 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
9443 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
9444 +
9445 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
9446 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
9447 +
9448 +
9449 +
9450 +/* pmkid */
9451 +#define MAXPMKID 16
9452 +
9453 +typedef struct _pmkid
9454 +{
9455 + struct ether_addr BSSID;
9456 + uint8 PMKID[WPA2_PMKID_LEN];
9457 +} pmkid_t;
9458 +
9459 +typedef struct _pmkid_list
9460 +{
9461 + uint32 npmkid;
9462 + pmkid_t pmkid[1];
9463 +} pmkid_list_t;
9464 +
9465 +typedef struct _pmkid_cand {
9466 + struct ether_addr BSSID;
9467 + uint8 preauth;
9468 +} pmkid_cand_t;
9469 +
9470 +typedef struct _pmkid_cand_list {
9471 + uint32 npmkid_cand;
9472 + pmkid_cand_t pmkid_cand[1];
9473 +} pmkid_cand_list_t;
9474 +
9475 +
9476 +typedef struct wl_led_info {
9477 + uint32 index; /* led index */
9478 + uint32 behavior;
9479 + bool activehi;
9480 +} wl_led_info_t;
9481 +
9482 +typedef struct wlc_assoc_info {
9483 + uint32 req_len;
9484 + uint32 resp_len;
9485 + uint32 flags;
9486 + struct dot11_assoc_req req;
9487 + struct ether_addr reassoc_bssid; /* used in reassoc's */
9488 + struct dot11_assoc_resp resp;
9489 +} wl_assoc_info_t;
9490 +/* flags */
9491 +#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
9492 +/* srom read/write struct passed through ioctl */
9493 +typedef struct {
9494 + uint byteoff; /* byte offset */
9495 + uint nbytes; /* number of bytes */
9496 + uint16 buf[1];
9497 +} srom_rw_t;
9498 +
9499 +/* R_REG and W_REG struct passed through ioctl */
9500 +typedef struct {
9501 + uint32 byteoff; /* byte offset of the field in d11regs_t */
9502 + uint32 val; /* read/write value of the field */
9503 + uint32 size; /* sizeof the field */
9504 + uint band; /* band (optional) */
9505 +} rw_reg_t;
9506 +
9507 +/* Structure used by GET/SET_ATTEN ioctls */
9508 +typedef struct {
9509 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
9510 + uint16 bb; /* Baseband attenuation */
9511 + uint16 radio; /* Radio attenuation */
9512 + uint16 txctl1; /* Radio TX_CTL1 value */
9513 +} atten_t;
9514 +
9515 +/* Used to get specific STA parameters */
9516 +typedef struct {
9517 + uint32 val;
9518 + struct ether_addr ea;
9519 +} scb_val_t;
9520 +
9521 +
9522 +/* Event data type */
9523 +typedef struct wlc_event {
9524 + wl_event_msg_t event; /* encapsulated event */
9525 + struct ether_addr *addr; /* used to keep a trace of the potential present of
9526 + an address in wlc_event_msg_t */
9527 + void *data; /* used to hang additional data on an event */
9528 + struct wlc_event *next; /* enables ordered list of pending events */
9529 +} wlc_event_t;
9530 +
9531 +#define BCM_MAC_STATUS_INDICATION (0x40010200L)
9532 +
9533 +typedef struct {
9534 + uint16 ver; /* version of this struct */
9535 + uint16 len; /* length in bytes of this structure */
9536 + uint16 cap; /* sta's advertized capabilities */
9537 + uint32 flags; /* flags defined below */
9538 + uint32 idle; /* time since data pkt rx'd from sta */
9539 + struct ether_addr ea; /* Station address */
9540 + wl_rateset_t rateset; /* rateset in use */
9541 + uint32 in; /* seconds elapsed since associated */
9542 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
9543 +} sta_info_t;
9544 +
9545 +#define WL_STA_VER 2
9546 +
9547 +/* flags fields */
9548 +#define WL_STA_BRCM 0x01
9549 +#define WL_STA_WME 0x02
9550 +#define WL_STA_ABCAP 0x04
9551 +#define WL_STA_AUTHE 0x08
9552 +#define WL_STA_ASSOC 0x10
9553 +#define WL_STA_AUTHO 0x20
9554 +#define WL_STA_WDS 0x40
9555 +#define WL_WDS_LINKUP 0x80
9556 +
9557 +
9558 +/*
9559 + * Country locale determines which channels are available to us.
9560 + */
9561 +typedef enum _wlc_locale {
9562 + WLC_WW = 0, /* Worldwide */
9563 + WLC_THA, /* Thailand */
9564 + WLC_ISR, /* Israel */
9565 + WLC_JDN, /* Jordan */
9566 + WLC_PRC, /* China */
9567 + WLC_JPN, /* Japan */
9568 + WLC_FCC, /* USA */
9569 + WLC_EUR, /* Europe */
9570 + WLC_USL, /* US Low Band only */
9571 + WLC_JPH, /* Japan High Band only */
9572 + WLC_ALL, /* All the channels in this band */
9573 + WLC_11D, /* Represents locale recieved by 11d beacons */
9574 + WLC_LAST_LOCALE,
9575 + WLC_UNDEFINED_LOCALE = 0xf
9576 +} wlc_locale_t;
9577 +
9578 +/* channel encoding */
9579 +typedef struct channel_info {
9580 + int hw_channel;
9581 + int target_channel;
9582 + int scan_channel;
9583 +} channel_info_t;
9584 +
9585 +/* For ioctls that take a list of MAC addresses */
9586 +struct maclist {
9587 + uint count; /* number of MAC addresses */
9588 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
9589 +};
9590 +
9591 +/* get pkt count struct passed through ioctl */
9592 +typedef struct get_pktcnt {
9593 + uint rx_good_pkt;
9594 + uint rx_bad_pkt;
9595 + uint tx_good_pkt;
9596 + uint tx_bad_pkt;
9597 +} get_pktcnt_t;
9598 +
9599 +/* Linux network driver ioctl encoding */
9600 +typedef struct wl_ioctl {
9601 + uint cmd; /* common ioctl definition */
9602 + void *buf; /* pointer to user buffer */
9603 + uint len; /* length of user buffer */
9604 + bool set; /* get or set request (optional) */
9605 + uint used; /* bytes read or written (optional) */
9606 + uint needed; /* bytes needed (optional) */
9607 +} wl_ioctl_t;
9608 +
9609 +/*
9610 + * Structure for passing hardware and software
9611 + * revision info up from the driver.
9612 + */
9613 +typedef struct wlc_rev_info {
9614 + uint vendorid; /* PCI vendor id */
9615 + uint deviceid; /* device id of chip */
9616 + uint radiorev; /* radio revision */
9617 + uint chiprev; /* chip revision */
9618 + uint corerev; /* core revision */
9619 + uint boardid; /* board identifier (usu. PCI sub-device id) */
9620 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
9621 + uint boardrev; /* board revision */
9622 + uint driverrev; /* driver version */
9623 + uint ucoderev; /* microcode version */
9624 + uint bus; /* bus type */
9625 + uint chipnum; /* chip number */
9626 +} wlc_rev_info_t;
9627 +
9628 +#define WL_BRAND_MAX 10
9629 +typedef struct wl_instance_info {
9630 + uint instance;
9631 + char brand[WL_BRAND_MAX];
9632 +} wl_instance_info_t;
9633 +
9634 +/* check this magic number */
9635 +#define WLC_IOCTL_MAGIC 0x14e46c77
9636 +
9637 +/* bump this number if you change the ioctl interface */
9638 +#define WLC_IOCTL_VERSION 1
9639 +
9640 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
9641 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
9642 +
9643 +/* common ioctl definitions */
9644 +#define WLC_GET_MAGIC 0
9645 +#define WLC_GET_VERSION 1
9646 +#define WLC_UP 2
9647 +#define WLC_DOWN 3
9648 +#define WLC_DUMP 6
9649 +#define WLC_GET_MSGLEVEL 7
9650 +#define WLC_SET_MSGLEVEL 8
9651 +#define WLC_GET_PROMISC 9
9652 +#define WLC_SET_PROMISC 10
9653 +#define WLC_GET_RATE 12
9654 +/* #define WLC_SET_RATE 13 */ /* no longer supported */
9655 +#define WLC_GET_INSTANCE 14
9656 +/* #define WLC_GET_FRAG 15 */ /* no longer supported */
9657 +/* #define WLC_SET_FRAG 16 */ /* no longer supported */
9658 +/* #define WLC_GET_RTS 17 */ /* no longer supported */
9659 +/* #define WLC_SET_RTS 18 */ /* no longer supported */
9660 +#define WLC_GET_INFRA 19
9661 +#define WLC_SET_INFRA 20
9662 +#define WLC_GET_AUTH 21
9663 +#define WLC_SET_AUTH 22
9664 +#define WLC_GET_BSSID 23
9665 +#define WLC_SET_BSSID 24
9666 +#define WLC_GET_SSID 25
9667 +#define WLC_SET_SSID 26
9668 +#define WLC_RESTART 27
9669 +#define WLC_GET_CHANNEL 29
9670 +#define WLC_SET_CHANNEL 30
9671 +#define WLC_GET_SRL 31
9672 +#define WLC_SET_SRL 32
9673 +#define WLC_GET_LRL 33
9674 +#define WLC_SET_LRL 34
9675 +#define WLC_GET_PLCPHDR 35
9676 +#define WLC_SET_PLCPHDR 36
9677 +#define WLC_GET_RADIO 37
9678 +#define WLC_SET_RADIO 38
9679 +#define WLC_GET_PHYTYPE 39
9680 +/* #define WLC_GET_WEP 42 */ /* no longer supported */
9681 +/* #define WLC_SET_WEP 43 */ /* no longer supported */
9682 +#define WLC_GET_KEY 44
9683 +#define WLC_SET_KEY 45
9684 +#define WLC_GET_REGULATORY 46
9685 +#define WLC_SET_REGULATORY 47
9686 +#define WLC_SCAN 50
9687 +#define WLC_SCAN_RESULTS 51
9688 +#define WLC_DISASSOC 52
9689 +#define WLC_REASSOC 53
9690 +#define WLC_GET_ROAM_TRIGGER 54
9691 +#define WLC_SET_ROAM_TRIGGER 55
9692 +#define WLC_GET_TXANT 61
9693 +#define WLC_SET_TXANT 62
9694 +#define WLC_GET_ANTDIV 63
9695 +#define WLC_SET_ANTDIV 64
9696 +/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
9697 +/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
9698 +#define WLC_GET_CLOSED 67
9699 +#define WLC_SET_CLOSED 68
9700 +#define WLC_GET_MACLIST 69
9701 +#define WLC_SET_MACLIST 70
9702 +#define WLC_GET_RATESET 71
9703 +#define WLC_SET_RATESET 72
9704 +#define WLC_GET_LOCALE 73
9705 +#define WLC_LONGTRAIN 74
9706 +#define WLC_GET_BCNPRD 75
9707 +#define WLC_SET_BCNPRD 76
9708 +#define WLC_GET_DTIMPRD 77
9709 +#define WLC_SET_DTIMPRD 78
9710 +#define WLC_GET_SROM 79
9711 +#define WLC_SET_SROM 80
9712 +#define WLC_GET_WEP_RESTRICT 81
9713 +#define WLC_SET_WEP_RESTRICT 82
9714 +#define WLC_GET_COUNTRY 83
9715 +#define WLC_SET_COUNTRY 84
9716 +#define WLC_GET_REVINFO 98
9717 +#define WLC_GET_MACMODE 105
9718 +#define WLC_SET_MACMODE 106
9719 +#define WLC_GET_GMODE 109
9720 +#define WLC_SET_GMODE 110
9721 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
9722 +#define WLC_GET_SCANSUPPRESS 115
9723 +#define WLC_SET_SCANSUPPRESS 116
9724 +#define WLC_GET_AP 117
9725 +#define WLC_SET_AP 118
9726 +#define WLC_GET_EAP_RESTRICT 119
9727 +#define WLC_SET_EAP_RESTRICT 120
9728 +#define WLC_GET_WDSLIST 123
9729 +#define WLC_SET_WDSLIST 124
9730 +#define WLC_GET_RSSI 127
9731 +#define WLC_GET_WSEC 133
9732 +#define WLC_SET_WSEC 134
9733 +#define WLC_GET_BSS_INFO 136
9734 +#define WLC_GET_LAZYWDS 138
9735 +#define WLC_SET_LAZYWDS 139
9736 +#define WLC_GET_BANDLIST 140
9737 +#define WLC_GET_BAND 141
9738 +#define WLC_SET_BAND 142
9739 +#define WLC_GET_SHORTSLOT 144
9740 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
9741 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
9742 +#define WLC_GET_SHORTSLOT_RESTRICT 147
9743 +#define WLC_SET_SHORTSLOT_RESTRICT 148
9744 +#define WLC_GET_GMODE_PROTECTION 149
9745 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
9746 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
9747 +#define WLC_UPGRADE 152
9748 +/* #define WLC_GET_MRATE 153 */ /* no longer supported */
9749 +/* #define WLC_SET_MRATE 154 */ /* no longer supported */
9750 +#define WLC_GET_ASSOCLIST 159
9751 +#define WLC_GET_CLK 160
9752 +#define WLC_SET_CLK 161
9753 +#define WLC_GET_UP 162
9754 +#define WLC_OUT 163
9755 +#define WLC_GET_WPA_AUTH 164
9756 +#define WLC_SET_WPA_AUTH 165
9757 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
9758 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
9759 +#define WLC_GET_PHYLIST 180
9760 +#define WLC_GET_KEY_SEQ 183
9761 +#define WLC_GET_GMODE_PROTECTION_CTS 198
9762 +#define WLC_SET_GMODE_PROTECTION_CTS 199
9763 +#define WLC_GET_PIOMODE 203
9764 +#define WLC_SET_PIOMODE 204
9765 +#define WLC_SET_LED 209
9766 +#define WLC_GET_LED 210
9767 +#define WLC_GET_CHANNEL_SEL 215
9768 +#define WLC_START_CHANNEL_SEL 216
9769 +#define WLC_GET_VALID_CHANNELS 217
9770 +#define WLC_GET_FAKEFRAG 218
9771 +#define WLC_SET_FAKEFRAG 219
9772 +#define WLC_GET_WET 230
9773 +#define WLC_SET_WET 231
9774 +#define WLC_GET_KEY_PRIMARY 235
9775 +#define WLC_SET_KEY_PRIMARY 236
9776 +#define WLC_GET_RADAR 242
9777 +#define WLC_SET_RADAR 243
9778 +#define WLC_SET_SPECT_MANAGMENT 244
9779 +#define WLC_GET_SPECT_MANAGMENT 245
9780 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
9781 +#define WLC_SET_CS_SCAN_TIMER 248
9782 +#define WLC_GET_CS_SCAN_TIMER 249
9783 +#define WLC_SEND_PWR_CONSTRAINT 254
9784 +#define WLC_CURRENT_PWR 256
9785 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
9786 +#define WLC_GET_COUNTRY_LIST 261
9787 +#define WLC_GET_VAR 262 /* get value of named variable */
9788 +#define WLC_SET_VAR 263 /* set named variable to value */
9789 +#define WLC_NVRAM_GET 264
9790 +#define WLC_NVRAM_SET 265
9791 +#define WLC_SET_WSEC_PMK 268
9792 +#define WLC_GET_AUTH_MODE 269
9793 +#define WLC_SET_AUTH_MODE 270
9794 +#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
9795 +#define WLC_NVOTPW 274
9796 +/* #define WLC_OTPW 275 */ /* no longer supported */
9797 +#define WLC_SET_LOCALE 278
9798 +#define WLC_LAST 279 /* do not change - use get_var/set_var */
9799 +
9800 +/*
9801 + * Minor kludge alert:
9802 + * Duplicate a few definitions that irelay requires from epiioctl.h here
9803 + * so caller doesn't have to include this file and epiioctl.h .
9804 + * If this grows any more, it would be time to move these irelay-specific
9805 + * definitions out of the epiioctl.h and into a separate driver common file.
9806 + */
9807 +#ifndef EPICTRL_COOKIE
9808 +#define EPICTRL_COOKIE 0xABADCEDE
9809 +#endif
9810 +
9811 +/* vx wlc ioctl's offset */
9812 +#define CMN_IOCTL_OFF 0x180
9813 +
9814 +/*
9815 + * custom OID support
9816 + *
9817 + * 0xFF - implementation specific OID
9818 + * 0xE4 - first byte of Broadcom PCI vendor ID
9819 + * 0x14 - second byte of Broadcom PCI vendor ID
9820 + * 0xXX - the custom OID number
9821 + */
9822 +
9823 +/* begin 0x1f values beyond the start of the ET driver range. */
9824 +#define WL_OID_BASE 0xFFE41420
9825 +
9826 +/* NDIS overrides */
9827 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
9828 +#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
9829 +
9830 +#define WL_DECRYPT_STATUS_SUCCESS 1
9831 +#define WL_DECRYPT_STATUS_FAILURE 2
9832 +#define WL_DECRYPT_STATUS_UNKNOWN 3
9833 +
9834 +/* allows user-mode app to poll the status of USB image upgrade */
9835 +#define WLC_UPGRADE_SUCCESS 0
9836 +#define WLC_UPGRADE_PENDING 1
9837 +
9838 +#ifdef CONFIG_USBRNDIS_RETAIL
9839 +/* struct passed in for WLC_NDCONFIG_ITEM */
9840 +typedef struct {
9841 + char *name;
9842 + void *param;
9843 +} ndconfig_item_t;
9844 +#endif
9845 +
9846 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
9847 +#define WL_RADIO_SW_DISABLE (1<<0)
9848 +#define WL_RADIO_HW_DISABLE (1<<1)
9849 +#define WL_RADIO_MPC_DISABLE (1<<2)
9850 +#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
9851 +
9852 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
9853 +#define WL_TXPWR_OVERRIDE (1<<31)
9854 +
9855 +/* "diag" iovar argument and error code */
9856 +#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
9857 +#define WL_DIAG_MEMORY 3 /* d11 memory test */
9858 +#define WL_DIAG_LED 4 /* LED test */
9859 +#define WL_DIAG_REG 5 /* d11/phy register test */
9860 +#define WL_DIAG_SROM 6 /* srom read/crc test */
9861 +#define WL_DIAG_DMA 7 /* DMA test */
9862 +
9863 +#define WL_DIAGERR_SUCCESS 0
9864 +#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
9865 +#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
9866 +#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
9867 +#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
9868 +#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
9869 +#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
9870 +#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
9871 +#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
9872 +#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
9873 +#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
9874 +
9875 +/* Bus types */
9876 +#define WL_SB_BUS 0 /* Silicon Backplane */
9877 +#define WL_PCI_BUS 1 /* PCI target */
9878 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
9879 +
9880 +/* band types */
9881 +#define WLC_BAND_AUTO 0 /* auto-select */
9882 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
9883 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
9884 +#define WLC_BAND_ALL 3 /* all bands */
9885 +
9886 +/* phy types (returned by WLC_GET_PHYTPE) */
9887 +#define WLC_PHY_TYPE_A 0
9888 +#define WLC_PHY_TYPE_B 1
9889 +#define WLC_PHY_TYPE_G 2
9890 +#define WLC_PHY_TYPE_NULL 0xf
9891 +
9892 +/* MAC list modes */
9893 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
9894 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
9895 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
9896 +
9897 +/*
9898 + *
9899 + */
9900 +#define GMODE_LEGACY_B 0
9901 +#define GMODE_AUTO 1
9902 +#define GMODE_ONLY 2
9903 +#define GMODE_B_DEFERRED 3
9904 +#define GMODE_PERFORMANCE 4
9905 +#define GMODE_LRS 5
9906 +#define GMODE_MAX 6
9907 +
9908 +/* values for PLCPHdr_override */
9909 +#define WLC_PLCP_AUTO -1
9910 +#define WLC_PLCP_SHORT 0
9911 +#define WLC_PLCP_LONG 1
9912 +
9913 +/* values for g_protection_override */
9914 +#define WLC_G_PROTECTION_AUTO -1
9915 +#define WLC_G_PROTECTION_OFF 0
9916 +#define WLC_G_PROTECTION_ON 1
9917 +
9918 +/* values for g_protection_control */
9919 +#define WLC_G_PROTECTION_CTL_OFF 0
9920 +#define WLC_G_PROTECTION_CTL_LOCAL 1
9921 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
9922 +
9923 +/* Values for PM */
9924 +#define PM_OFF 0
9925 +#define PM_MAX 1
9926 +#define PM_FAST 2
9927 +
9928 +
9929 +
9930 +typedef struct {
9931 + int npulses; /* required number of pulses at n * t_int */
9932 + int ncontig; /* required number of pulses at t_int */
9933 + int min_pw; /* minimum pulse width (20 MHz clocks) */
9934 + int max_pw; /* maximum pulse width (20 MHz clocks) */
9935 + uint16 thresh0; /* Radar detection, thresh 0 */
9936 + uint16 thresh1; /* Radar detection, thresh 1 */
9937 +} wl_radar_args_t;
9938 +
9939 +/* radar iovar SET defines */
9940 +#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
9941 +#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
9942 +#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
9943 +
9944 +/* dfs_status iovar-related defines */
9945 +
9946 +/* cac - channel availability check,
9947 + * ism - in-service monitoring
9948 + * csa - channel switching anouncement
9949 + */
9950 +
9951 +/* cac state values */
9952 +#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
9953 +#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
9954 +#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
9955 +#define WL_DFS_CACSTATE_CSA 3 /* csa */
9956 +#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
9957 +#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
9958 +#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
9959 +#define WL_DFS_CACSTATES 7 /* this many states exist */
9960 +
9961 +/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
9962 +typedef struct {
9963 + uint state; /* noted by WL_DFS_CACSTATE_XX. */
9964 + uint duration; /* time spent in ms in state. */
9965 + /* as dfs enters ISM state, it removes the operational channel from quiet channel list
9966 + * and notes the channel in channel_cleared. set to 0 if no channel is cleared
9967 + */
9968 + uint channel_cleared;
9969 +} wl_dfs_status_t;
9970 +
9971 +#define NUM_PWRCTRL_RATES 12
9972 +
9973 +
9974 +/* 802.11h enforcement levels */
9975 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
9976 +#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
9977 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
9978 +#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
9979 +
9980 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
9981 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
9982 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
9983 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
9984 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
9985 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
9986 +
9987 +#define WL_MPC_VAL 0x00400000
9988 +#define WL_APSTA_VAL 0x00800000
9989 +#define WL_DFS_VAL 0x01000000
9990 +
9991 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
9992 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
9993 +
9994 +/* led per-pin behaviors */
9995 +#define WL_LED_OFF 0 /* always off */
9996 +#define WL_LED_ON 1 /* always on */
9997 +#define WL_LED_ACTIVITY 2 /* activity */
9998 +#define WL_LED_RADIO 3 /* radio enabled */
9999 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
10000 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
10001 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
10002 +#define WL_LED_WI1 7
10003 +#define WL_LED_WI2 8
10004 +#define WL_LED_WI3 9
10005 +#define WL_LED_ASSOC 10 /* associated state indicator */
10006 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
10007 +#define WL_LED_NUMBEHAVIOR 12
10008 +
10009 +/* led behavior numeric value format */
10010 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
10011 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
10012 +
10013 +
10014 +/* WDS link local endpoint WPA role */
10015 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
10016 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
10017 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
10018 +
10019 +/* number of bytes needed to define a 128-bit mask for MAC event reporting */
10020 +#define WL_EVENTING_MASK_LEN 16
10021 +
10022 +/* Structures and constants used for "vndr_ie" IOVar interface */
10023 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
10024 +
10025 +/* 802.11 Mgmt Packet flags */
10026 +#define VNDR_IE_BEACON_FLAG 0x1
10027 +#define VNDR_IE_PRBRSP_FLAG 0x2
10028 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
10029 +#define VNDR_IE_AUTHRSP_FLAG 0x8
10030 +
10031 +typedef struct {
10032 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
10033 + vndr_ie_t vndr_ie_data; /* vendor IE data */
10034 +} vndr_ie_info_t;
10035 +
10036 +typedef struct {
10037 + int iecount; /* number of entries in the vndr_ie_list[] array */
10038 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
10039 +} vndr_ie_buf_t;
10040 +
10041 +typedef struct {
10042 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
10043 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
10044 +} vndr_ie_setbuf_t;
10045 +
10046 +/* join target preference types */
10047 +#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
10048 +#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
10049 +#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
10050 +
10051 +/* band preference */
10052 +#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
10053 + /* others use WLC_BAND_XXXX as values */
10054 +
10055 +/* any multicast cipher suite */
10056 +#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
10057 +
10058 +#if !defined(__GNUC__)
10059 +#pragma pack(pop)
10060 +#endif
10061 +
10062 +#define NFIFO 6 /* # tx/rx fifopairs */
10063 +
10064 +#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
10065 +
10066 +typedef struct {
10067 + uint16 version; /* see definition of WL_CNT_T_VERSION */
10068 + uint16 length; /* length of entire structure */
10069 +
10070 + /* transmit stat counters */
10071 + uint32 txframe; /* tx data frames */
10072 + uint32 txbyte; /* tx data bytes */
10073 + uint32 txretrans; /* tx mac retransmits */
10074 + uint32 txerror; /* tx data errors */
10075 + uint32 txctl; /* tx management frames */
10076 + uint32 txprshort; /* tx short preamble frames */
10077 + uint32 txserr; /* tx status errors */
10078 + uint32 txnobuf; /* tx out of buffers errors */
10079 + uint32 txnoassoc; /* tx discard because we're not associated */
10080 + uint32 txrunt; /* tx runt frames */
10081 + uint32 txchit; /* tx header cache hit (fastpath) */
10082 + uint32 txcmiss; /* tx header cache miss (slowpath) */
10083 +
10084 + /* transmit chip error counters */
10085 + uint32 txuflo; /* tx fifo underflows */
10086 + uint32 txphyerr; /* tx phy errors (indicated in tx status) */
10087 + uint32 txphycrs;
10088 +
10089 + /* receive stat counters */
10090 + uint32 rxframe; /* rx data frames */
10091 + uint32 rxbyte; /* rx data bytes */
10092 + uint32 rxerror; /* rx data errors */
10093 + uint32 rxctl; /* rx management frames */
10094 + uint32 rxnobuf; /* rx out of buffers errors */
10095 + uint32 rxnondata; /* rx non data frames in the data channel errors */
10096 + uint32 rxbadds; /* rx bad DS errors */
10097 + uint32 rxbadcm; /* rx bad control or management frames */
10098 + uint32 rxfragerr; /* rx fragmentation errors */
10099 + uint32 rxrunt; /* rx runt frames */
10100 + uint32 rxgiant; /* rx giant frames */
10101 + uint32 rxnoscb; /* rx no scb error */
10102 + uint32 rxbadproto; /* rx invalid frames */
10103 + uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
10104 + uint32 rxbadda; /* rx frames tossed for invalid da */
10105 + uint32 rxfilter; /* rx frames filtered out */
10106 +
10107 + /* receive chip error counters */
10108 + uint32 rxoflo; /* rx fifo overflow errors */
10109 + uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
10110 +
10111 + uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
10112 + uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
10113 + uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
10114 +
10115 + /* misc counters */
10116 + uint32 dmade; /* tx/rx dma descriptor errors */
10117 + uint32 dmada; /* tx/rx dma data errors */
10118 + uint32 dmape; /* tx/rx dma descriptor protocol errors */
10119 + uint32 reset; /* reset count */
10120 + uint32 tbtt; /* cnts the TBTT int's */
10121 + uint32 txdmawar;
10122 +
10123 + /* MAC counters: 32-bit version of d11.h's macstat_t */
10124 + uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
10125 + Control Management (includes retransmissions) */
10126 + uint32 txrtsfrm; /* number of RTS sent out by the MAC */
10127 + uint32 txctsfrm; /* number of CTS sent out by the MAC */
10128 + uint32 txackfrm; /* number of ACK frames sent out */
10129 + uint32 txdnlfrm; /* Not used */
10130 + uint32 txbcnfrm; /* beacons transmitted */
10131 + uint32 txfunfl[8]; /* per-fifo tx underflows */
10132 + uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
10133 + uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
10134 + driver enqueued frames*/
10135 + uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
10136 + uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
10137 + uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
10138 + data/control/management*/
10139 + uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
10140 + uint32 rxbadplcp; /* parity check of the PLCP header failed */
10141 + uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
10142 + uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
10143 + uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
10144 + uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
10145 + uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
10146 + uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
10147 + uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
10148 + uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
10149 + uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
10150 + uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
10151 + uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
10152 + uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
10153 + uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
10154 + uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
10155 + uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
10156 + uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
10157 + to see these) */
10158 + uint32 rxbeaconmbss; /* beacons received from member of BSS */
10159 + uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
10160 + uint32 rxbeaconobss; /* beacons received from other BSS */
10161 + uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
10162 + response */
10163 + uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
10164 + uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
10165 + uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
10166 + uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
10167 + uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
10168 + uint32 pmqovfl; /* Number of PMQ overflows */
10169 + uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
10170 + uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
10171 + uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
10172 + uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
10173 + uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
10174 + a probe response could not be sent out within the time limit defined
10175 + in M_PRS_MAXTIME */
10176 + uint32 rxnack; /* Number of NACKS received (Afterburner) */
10177 + uint32 frmscons; /* Number of frames completed without transmission because of an
10178 + Afterburner re-queue */
10179 + uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
10180 + uint32 txglitch_nack; /* obsolete */
10181 + uint32 txburst; /* obsolete */
10182 + uint32 rxburst; /* obsolete */
10183 +
10184 + /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
10185 + uint32 txfrag; /* dot11TransmittedFragmentCount */
10186 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
10187 + uint32 txfail; /* dot11FailedCount */
10188 + uint32 txretry; /* dot11RetryCount */
10189 + uint32 txretrie; /* dot11MultipleRetryCount */
10190 + uint32 rxdup; /* dot11FrameduplicateCount */
10191 + uint32 txrts; /* dot11RTSSuccessCount */
10192 + uint32 txnocts; /* dot11RTSFailureCount */
10193 + uint32 txnoack; /* dot11ACKFailureCount */
10194 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
10195 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
10196 + uint32 rxcrc; /* dot11FCSErrorCount */
10197 + uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
10198 + uint32 rxundec; /* dot11WEPUndecryptableCount */
10199 +
10200 + /* WPA2 counters (see rxundec for DecryptFailureCount) */
10201 + uint32 tkipmicfaill; /* TKIPLocalMICFailures */
10202 + uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
10203 + uint32 tkipreplay; /* TKIPReplays */
10204 + uint32 ccmpfmterr; /* CCMPFormatErrors */
10205 + uint32 ccmpreplay; /* CCMPReplays */
10206 + uint32 ccmpundec; /* CCMPDecryptErrors */
10207 + uint32 fourwayfail; /* FourWayHandshakeFailures */
10208 + uint32 wepundec; /* dot11WEPUndecryptableCount */
10209 + uint32 wepicverr; /* dot11WEPICVErrorCount */
10210 + uint32 decsuccess; /* DecryptSuccessCount */
10211 + uint32 tkipicverr; /* TKIPICVErrorCount */
10212 + uint32 wepexcluded; /* dot11WEPExcludedCount */
10213 +} wl_cnt_t;
10214 +
10215 +#endif /* _wlioctl_h_ */
10216 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
10217 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
10218 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-11-07 21:57:07.881588000 +0100
10219 @@ -0,0 +1,321 @@
10220 +/*
10221 + * NVRAM variable manipulation (common)
10222 + *
10223 + * Copyright 2004, Broadcom Corporation
10224 + * All Rights Reserved.
10225 + *
10226 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10227 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10228 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10229 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10230 + *
10231 + * $Id$
10232 + */
10233 +
10234 +#include <typedefs.h>
10235 +#include <osl.h>
10236 +#include <bcmendian.h>
10237 +#include <bcmnvram.h>
10238 +#include <bcmutils.h>
10239 +#include <sbsdram.h>
10240 +
10241 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
10242 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
10243 +extern int BCMINIT(_nvram_read)(void *buf);
10244 +
10245 +char * BCMINIT(_nvram_get)(const char *name);
10246 +int BCMINIT(_nvram_set)(const char *name, const char *value);
10247 +int BCMINIT(_nvram_unset)(const char *name);
10248 +int BCMINIT(_nvram_getall)(char *buf, int count);
10249 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
10250 +int BCMINIT(_nvram_init)(void);
10251 +void BCMINIT(_nvram_exit)(void);
10252 +
10253 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
10254 +static struct nvram_tuple * nvram_dead;
10255 +
10256 +/* Free all tuples. Should be locked. */
10257 +static void
10258 +BCMINITFN(nvram_free)(void)
10259 +{
10260 + uint i;
10261 + struct nvram_tuple *t, *next;
10262 +
10263 + /* Free hash table */
10264 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10265 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
10266 + next = t->next;
10267 + BCMINIT(_nvram_free)(t);
10268 + }
10269 + BCMINIT(nvram_hash)[i] = NULL;
10270 + }
10271 +
10272 + /* Free dead table */
10273 + for (t = nvram_dead; t; t = next) {
10274 + next = t->next;
10275 + BCMINIT(_nvram_free)(t);
10276 + }
10277 + nvram_dead = NULL;
10278 +
10279 + /* Indicate to per-port code that all tuples have been freed */
10280 + BCMINIT(_nvram_free)(NULL);
10281 +}
10282 +
10283 +/* String hash */
10284 +static INLINE uint
10285 +hash(const char *s)
10286 +{
10287 + uint hash = 0;
10288 +
10289 + while (*s)
10290 + hash = 31 * hash + *s++;
10291 +
10292 + return hash;
10293 +}
10294 +
10295 +/* (Re)initialize the hash table. Should be locked. */
10296 +static int
10297 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
10298 +{
10299 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
10300 +
10301 + /* (Re)initialize hash table */
10302 + BCMINIT(nvram_free)();
10303 +
10304 + /* Parse and set "name=value\0 ... \0\0" */
10305 + name = (char *) &header[1];
10306 + end = (char *) header + NVRAM_SPACE - 2;
10307 + end[0] = end[1] = '\0';
10308 + for (; *name; name = value + strlen(value) + 1) {
10309 + if (!(eq = strchr(name, '=')))
10310 + break;
10311 + *eq = '\0';
10312 + value = eq + 1;
10313 + BCMINIT(_nvram_set)(name, value);
10314 + *eq = '=';
10315 + }
10316 +
10317 + /* Set special SDRAM parameters */
10318 + if (!BCMINIT(_nvram_get)("sdram_init")) {
10319 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
10320 + BCMINIT(_nvram_set)("sdram_init", buf);
10321 + }
10322 + if (!BCMINIT(_nvram_get)("sdram_config")) {
10323 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
10324 + BCMINIT(_nvram_set)("sdram_config", buf);
10325 + }
10326 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
10327 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
10328 + BCMINIT(_nvram_set)("sdram_refresh", buf);
10329 + }
10330 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
10331 + sprintf(buf, "0x%08X", header->config_ncdl);
10332 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
10333 + }
10334 +
10335 + return 0;
10336 +}
10337 +
10338 +/* Get the value of an NVRAM variable. Should be locked. */
10339 +char *
10340 +BCMINITFN(_nvram_get)(const char *name)
10341 +{
10342 + uint i;
10343 + struct nvram_tuple *t;
10344 + char *value;
10345 +
10346 + if (!name)
10347 + return NULL;
10348 +
10349 + /* Hash the name */
10350 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10351 +
10352 + /* Find the associated tuple in the hash table */
10353 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
10354 +
10355 + value = t ? t->value : NULL;
10356 +
10357 + return value;
10358 +}
10359 +
10360 +/* Get the value of an NVRAM variable. Should be locked. */
10361 +int
10362 +BCMINITFN(_nvram_set)(const char *name, const char *value)
10363 +{
10364 + uint i;
10365 + struct nvram_tuple *t, *u, **prev;
10366 +
10367 + /* Hash the name */
10368 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10369 +
10370 + /* Find the associated tuple in the hash table */
10371 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10372 +
10373 + /* (Re)allocate tuple */
10374 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
10375 + return -12; /* -ENOMEM */
10376 +
10377 + /* Value reallocated */
10378 + if (t && t == u)
10379 + return 0;
10380 +
10381 + /* Move old tuple to the dead table */
10382 + if (t) {
10383 + *prev = t->next;
10384 + t->next = nvram_dead;
10385 + nvram_dead = t;
10386 + }
10387 +
10388 + /* Add new tuple to the hash table */
10389 + u->next = BCMINIT(nvram_hash)[i];
10390 + BCMINIT(nvram_hash)[i] = u;
10391 +
10392 + return 0;
10393 +}
10394 +
10395 +/* Unset the value of an NVRAM variable. Should be locked. */
10396 +int
10397 +BCMINITFN(_nvram_unset)(const char *name)
10398 +{
10399 + uint i;
10400 + struct nvram_tuple *t, **prev;
10401 +
10402 + if (!name)
10403 + return 0;
10404 +
10405 + /* Hash the name */
10406 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10407 +
10408 + /* Find the associated tuple in the hash table */
10409 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10410 +
10411 + /* Move it to the dead table */
10412 + if (t) {
10413 + *prev = t->next;
10414 + t->next = nvram_dead;
10415 + nvram_dead = t;
10416 + }
10417 +
10418 + return 0;
10419 +}
10420 +
10421 +/* Get all NVRAM variables. Should be locked. */
10422 +int
10423 +BCMINITFN(_nvram_getall)(char *buf, int count)
10424 +{
10425 + uint i;
10426 + struct nvram_tuple *t;
10427 + int len = 0;
10428 +
10429 + bzero(buf, count);
10430 +
10431 + /* Write name=value\0 ... \0\0 */
10432 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10433 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10434 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
10435 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
10436 + else
10437 + break;
10438 + }
10439 + }
10440 +
10441 + return 0;
10442 +}
10443 +
10444 +/* Regenerate NVRAM. Should be locked. */
10445 +int
10446 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
10447 +{
10448 + char *init, *config, *refresh, *ncdl;
10449 + char *ptr, *end;
10450 + int i;
10451 + struct nvram_tuple *t;
10452 + struct nvram_header tmp;
10453 + uint8 crc;
10454 +
10455 + /* Regenerate header */
10456 + header->magic = NVRAM_MAGIC;
10457 + header->crc_ver_init = (NVRAM_VERSION << 8);
10458 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
10459 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
10460 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
10461 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
10462 + header->crc_ver_init |= SDRAM_INIT << 16;
10463 + header->config_refresh = SDRAM_CONFIG;
10464 + header->config_refresh |= SDRAM_REFRESH << 16;
10465 + header->config_ncdl = 0;
10466 + } else {
10467 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
10468 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
10469 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
10470 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
10471 + }
10472 +
10473 + /* Clear data area */
10474 + ptr = (char *) header + sizeof(struct nvram_header);
10475 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
10476 +
10477 + /* Leave space for a double NUL at the end */
10478 + end = (char *) header + NVRAM_SPACE - 2;
10479 +
10480 + /* Write out all tuples */
10481 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10482 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10483 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
10484 + break;
10485 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
10486 + }
10487 + }
10488 +
10489 + /* End with a double NUL */
10490 + ptr += 2;
10491 +
10492 + /* Set new length */
10493 + header->len = ROUNDUP(ptr - (char *) header, 4);
10494 +
10495 + /* Little-endian CRC8 over the last 11 bytes of the header */
10496 + tmp.crc_ver_init = htol32(header->crc_ver_init);
10497 + tmp.config_refresh = htol32(header->config_refresh);
10498 + tmp.config_ncdl = htol32(header->config_ncdl);
10499 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
10500 +
10501 + /* Continue CRC8 over data bytes */
10502 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
10503 +
10504 + /* Set new CRC8 */
10505 + header->crc_ver_init |= crc;
10506 +
10507 + /* Reinitialize hash table */
10508 + return BCMINIT(nvram_rehash)(header);
10509 +}
10510 +
10511 +/* Initialize hash table. Should be locked. */
10512 +int
10513 +BCMINITFN(_nvram_init)(void)
10514 +{
10515 + struct nvram_header *header;
10516 + int ret;
10517 + void *osh;
10518 +
10519 + /* get kernel osl handler */
10520 + osh = osl_attach(NULL);
10521 +
10522 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
10523 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
10524 + return -12; /* -ENOMEM */
10525 + }
10526 +
10527 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
10528 + header->magic == NVRAM_MAGIC)
10529 + BCMINIT(nvram_rehash)(header);
10530 +
10531 + MFREE(osh, header, NVRAM_SPACE);
10532 + return ret;
10533 +}
10534 +
10535 +/* Free hash table. Should be locked. */
10536 +void
10537 +BCMINITFN(_nvram_exit)(void)
10538 +{
10539 + BCMINIT(nvram_free)();
10540 +}
10541 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
10542 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
10543 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-11-08 00:54:56.755597250 +0100
10544 @@ -0,0 +1,633 @@
10545 +/*
10546 + * NVRAM variable manipulation (Linux kernel half)
10547 + *
10548 + * Copyright 2005, Broadcom Corporation
10549 + * All Rights Reserved.
10550 + *
10551 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10552 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10553 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10554 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10555 + *
10556 + * $Id$
10557 + */
10558 +
10559 +#include <linux/config.h>
10560 +#include <linux/init.h>
10561 +#include <linux/module.h>
10562 +#include <linux/kernel.h>
10563 +#include <linux/string.h>
10564 +#include <linux/interrupt.h>
10565 +#include <linux/spinlock.h>
10566 +#include <linux/slab.h>
10567 +#include <linux/bootmem.h>
10568 +#include <linux/wrapper.h>
10569 +#include <linux/fs.h>
10570 +#include <linux/miscdevice.h>
10571 +#include <linux/mtd/mtd.h>
10572 +#include <asm/addrspace.h>
10573 +#include <asm/io.h>
10574 +#include <asm/uaccess.h>
10575 +
10576 +#include <typedefs.h>
10577 +#include <bcmendian.h>
10578 +#include <bcmnvram.h>
10579 +#include <bcmutils.h>
10580 +#include <sbconfig.h>
10581 +#include <sbchipc.h>
10582 +#include <sbutils.h>
10583 +#include <sbmips.h>
10584 +#include <sflash.h>
10585 +
10586 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
10587 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
10588 +
10589 +#ifdef MODULE
10590 +
10591 +#define early_nvram_get(name) nvram_get(name)
10592 +
10593 +#else /* !MODULE */
10594 +
10595 +/* Global SB handle */
10596 +extern void *bcm947xx_sbh;
10597 +extern spinlock_t bcm947xx_sbh_lock;
10598 +
10599 +/* Convenience */
10600 +#define sbh bcm947xx_sbh
10601 +#define sbh_lock bcm947xx_sbh_lock
10602 +#define KB * 1024
10603 +#define MB * 1024 * 1024
10604 +
10605 +/* Probe for NVRAM header */
10606 +static void __init
10607 +early_nvram_init(void)
10608 +{
10609 + struct nvram_header *header;
10610 + chipcregs_t *cc;
10611 + struct sflash *info = NULL;
10612 + int i;
10613 + uint32 base, off, lim;
10614 + u32 *src, *dst;
10615 +
10616 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10617 + base = KSEG1ADDR(SB_FLASH2);
10618 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
10619 + case PFLASH:
10620 + lim = SB_FLASH2_SZ;
10621 + break;
10622 +
10623 + case SFLASH_ST:
10624 + case SFLASH_AT:
10625 + if ((info = sflash_init(cc)) == NULL)
10626 + return;
10627 + lim = info->size;
10628 + break;
10629 +
10630 + case FLASH_NONE:
10631 + default:
10632 + return;
10633 + }
10634 + } else {
10635 + /* extif assumed, Stop at 4 MB */
10636 + base = KSEG1ADDR(SB_FLASH1);
10637 + lim = SB_FLASH1_SZ;
10638 + }
10639 +
10640 + off = FLASH_MIN;
10641 + while (off <= lim) {
10642 + /* Windowed flash access */
10643 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
10644 + if (header->magic == NVRAM_MAGIC)
10645 + goto found;
10646 + off <<= 1;
10647 + }
10648 +
10649 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
10650 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
10651 + if (header->magic == NVRAM_MAGIC)
10652 + goto found;
10653 +
10654 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
10655 + if (header->magic == NVRAM_MAGIC)
10656 + goto found;
10657 +
10658 + printk("early_nvram_init: NVRAM not found\n");
10659 + return;
10660 +
10661 +found:
10662 + src = (u32 *) header;
10663 + dst = (u32 *) nvram_buf;
10664 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
10665 + *dst++ = *src++;
10666 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
10667 + *dst++ = ltoh32(*src++);
10668 +}
10669 +
10670 +/* Early (before mm or mtd) read-only access to NVRAM */
10671 +static char * __init
10672 +early_nvram_get(const char *name)
10673 +{
10674 + char *var, *value, *end, *eq;
10675 +
10676 + if (!name)
10677 + return NULL;
10678 +
10679 + /* Too early? */
10680 + if (sbh == NULL)
10681 + return NULL;
10682 +
10683 + if (!nvram_buf[0])
10684 + early_nvram_init();
10685 +
10686 + /* Look for name=value and return value */
10687 + var = &nvram_buf[sizeof(struct nvram_header)];
10688 + end = nvram_buf + sizeof(nvram_buf) - 2;
10689 + end[0] = end[1] = '\0';
10690 + for (; *var; var = value + strlen(value) + 1) {
10691 + if (!(eq = strchr(var, '=')))
10692 + break;
10693 + value = eq + 1;
10694 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
10695 + return value;
10696 + }
10697 +
10698 + return NULL;
10699 +}
10700 +
10701 +#endif /* !MODULE */
10702 +
10703 +extern char * _nvram_get(const char *name);
10704 +extern int _nvram_set(const char *name, const char *value);
10705 +extern int _nvram_unset(const char *name);
10706 +extern int _nvram_getall(char *buf, int count);
10707 +extern int _nvram_commit(struct nvram_header *header);
10708 +extern int _nvram_init(void);
10709 +extern void _nvram_exit(void);
10710 +
10711 +/* Globals */
10712 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
10713 +static struct semaphore nvram_sem;
10714 +static unsigned long nvram_offset = 0;
10715 +static int nvram_major = -1;
10716 +static devfs_handle_t nvram_handle = NULL;
10717 +static struct mtd_info *nvram_mtd = NULL;
10718 +
10719 +int
10720 +_nvram_read(char *buf)
10721 +{
10722 + struct nvram_header *header = (struct nvram_header *) buf;
10723 + size_t len;
10724 +
10725 + if (!nvram_mtd ||
10726 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
10727 + len != NVRAM_SPACE ||
10728 + header->magic != NVRAM_MAGIC) {
10729 + /* Maybe we can recover some data from early initialization */
10730 + memcpy(buf, nvram_buf, NVRAM_SPACE);
10731 + }
10732 +
10733 + return 0;
10734 +}
10735 +
10736 +struct nvram_tuple *
10737 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
10738 +{
10739 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
10740 + return NULL;
10741 +
10742 + if (!t) {
10743 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
10744 + return NULL;
10745 +
10746 + /* Copy name */
10747 + t->name = (char *) &t[1];
10748 + strcpy(t->name, name);
10749 +
10750 + t->value = NULL;
10751 + }
10752 +
10753 + /* Copy value */
10754 + if (!t->value || strcmp(t->value, value)) {
10755 + t->value = &nvram_buf[nvram_offset];
10756 + strcpy(t->value, value);
10757 + nvram_offset += strlen(value) + 1;
10758 + }
10759 +
10760 + return t;
10761 +}
10762 +
10763 +void
10764 +_nvram_free(struct nvram_tuple *t)
10765 +{
10766 + if (!t)
10767 + nvram_offset = 0;
10768 + else
10769 + kfree(t);
10770 +}
10771 +
10772 +int
10773 +nvram_set(const char *name, const char *value)
10774 +{
10775 + unsigned long flags;
10776 + int ret;
10777 + struct nvram_header *header;
10778 +
10779 + spin_lock_irqsave(&nvram_lock, flags);
10780 + if ((ret = _nvram_set(name, value))) {
10781 + /* Consolidate space and try again */
10782 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
10783 + if (_nvram_commit(header) == 0)
10784 + ret = _nvram_set(name, value);
10785 + kfree(header);
10786 + }
10787 + }
10788 + spin_unlock_irqrestore(&nvram_lock, flags);
10789 +
10790 + return ret;
10791 +}
10792 +
10793 +char *
10794 +real_nvram_get(const char *name)
10795 +{
10796 + unsigned long flags;
10797 + char *value;
10798 +
10799 + spin_lock_irqsave(&nvram_lock, flags);
10800 + value = _nvram_get(name);
10801 + spin_unlock_irqrestore(&nvram_lock, flags);
10802 +
10803 + return value;
10804 +}
10805 +
10806 +char *
10807 +nvram_get(const char *name)
10808 +{
10809 + if (nvram_major >= 0)
10810 + return real_nvram_get(name);
10811 + else
10812 + return early_nvram_get(name);
10813 +}
10814 +
10815 +int
10816 +nvram_unset(const char *name)
10817 +{
10818 + unsigned long flags;
10819 + int ret;
10820 +
10821 + spin_lock_irqsave(&nvram_lock, flags);
10822 + ret = _nvram_unset(name);
10823 + spin_unlock_irqrestore(&nvram_lock, flags);
10824 +
10825 + return ret;
10826 +}
10827 +
10828 +static void
10829 +erase_callback(struct erase_info *done)
10830 +{
10831 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
10832 + wake_up(wait_q);
10833 +}
10834 +
10835 +int
10836 +nvram_commit(void)
10837 +{
10838 + char *buf;
10839 + size_t erasesize, len;
10840 + unsigned int i;
10841 + int ret;
10842 + struct nvram_header *header;
10843 + unsigned long flags;
10844 + u_int32_t offset;
10845 + DECLARE_WAITQUEUE(wait, current);
10846 + wait_queue_head_t wait_q;
10847 + struct erase_info erase;
10848 +
10849 + if (!nvram_mtd) {
10850 + printk("nvram_commit: NVRAM not found\n");
10851 + return -ENODEV;
10852 + }
10853 +
10854 + if (in_interrupt()) {
10855 + printk("nvram_commit: not committing in interrupt\n");
10856 + return -EINVAL;
10857 + }
10858 +
10859 + /* Backup sector blocks to be erased */
10860 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
10861 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
10862 + printk("nvram_commit: out of memory\n");
10863 + return -ENOMEM;
10864 + }
10865 +
10866 + down(&nvram_sem);
10867 +
10868 + if ((i = erasesize - NVRAM_SPACE) > 0) {
10869 + offset = nvram_mtd->size - erasesize;
10870 + len = 0;
10871 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
10872 + if (ret || len != i) {
10873 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
10874 + ret = -EIO;
10875 + goto done;
10876 + }
10877 + header = (struct nvram_header *)(buf + i);
10878 + } else {
10879 + offset = nvram_mtd->size - NVRAM_SPACE;
10880 + header = (struct nvram_header *)buf;
10881 + }
10882 +
10883 + /* Regenerate NVRAM */
10884 + spin_lock_irqsave(&nvram_lock, flags);
10885 + ret = _nvram_commit(header);
10886 + spin_unlock_irqrestore(&nvram_lock, flags);
10887 + if (ret)
10888 + goto done;
10889 +
10890 + /* Erase sector blocks */
10891 + init_waitqueue_head(&wait_q);
10892 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
10893 + erase.mtd = nvram_mtd;
10894 + erase.addr = offset;
10895 + erase.len = nvram_mtd->erasesize;
10896 + erase.callback = erase_callback;
10897 + erase.priv = (u_long) &wait_q;
10898 +
10899 + set_current_state(TASK_INTERRUPTIBLE);
10900 + add_wait_queue(&wait_q, &wait);
10901 +
10902 + /* Unlock sector blocks */
10903 + if (nvram_mtd->unlock)
10904 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
10905 +
10906 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
10907 + set_current_state(TASK_RUNNING);
10908 + remove_wait_queue(&wait_q, &wait);
10909 + printk("nvram_commit: erase error\n");
10910 + goto done;
10911 + }
10912 +
10913 + /* Wait for erase to finish */
10914 + schedule();
10915 + remove_wait_queue(&wait_q, &wait);
10916 + }
10917 +
10918 + /* Write partition up to end of data area */
10919 + offset = nvram_mtd->size - erasesize;
10920 + i = erasesize - NVRAM_SPACE + header->len;
10921 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
10922 + if (ret || len != i) {
10923 + printk("nvram_commit: write error\n");
10924 + ret = -EIO;
10925 + goto done;
10926 + }
10927 +
10928 + offset = nvram_mtd->size - erasesize;
10929 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
10930 +
10931 + done:
10932 + up(&nvram_sem);
10933 + kfree(buf);
10934 + return ret;
10935 +}
10936 +
10937 +int
10938 +nvram_getall(char *buf, int count)
10939 +{
10940 + unsigned long flags;
10941 + int ret;
10942 +
10943 + spin_lock_irqsave(&nvram_lock, flags);
10944 + ret = _nvram_getall(buf, count);
10945 + spin_unlock_irqrestore(&nvram_lock, flags);
10946 +
10947 + return ret;
10948 +}
10949 +
10950 +EXPORT_SYMBOL(nvram_get);
10951 +EXPORT_SYMBOL(nvram_getall);
10952 +EXPORT_SYMBOL(nvram_set);
10953 +EXPORT_SYMBOL(nvram_unset);
10954 +EXPORT_SYMBOL(nvram_commit);
10955 +
10956 +/* User mode interface below */
10957 +
10958 +static ssize_t
10959 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
10960 +{
10961 + char tmp[100], *name = tmp, *value;
10962 + ssize_t ret;
10963 + unsigned long off;
10964 +
10965 + if (count > sizeof(tmp)) {
10966 + if (!(name = kmalloc(count, GFP_KERNEL)))
10967 + return -ENOMEM;
10968 + }
10969 +
10970 + if (copy_from_user(name, buf, count)) {
10971 + ret = -EFAULT;
10972 + goto done;
10973 + }
10974 +
10975 + if (*name == '\0') {
10976 + /* Get all variables */
10977 + ret = nvram_getall(name, count);
10978 + if (ret == 0) {
10979 + if (copy_to_user(buf, name, count)) {
10980 + ret = -EFAULT;
10981 + goto done;
10982 + }
10983 + ret = count;
10984 + }
10985 + } else {
10986 + if (!(value = nvram_get(name))) {
10987 + ret = 0;
10988 + goto done;
10989 + }
10990 +
10991 + /* Provide the offset into mmap() space */
10992 + off = (unsigned long) value - (unsigned long) nvram_buf;
10993 +
10994 + if (put_user(off, (unsigned long *) buf)) {
10995 + ret = -EFAULT;
10996 + goto done;
10997 + }
10998 +
10999 + ret = sizeof(unsigned long);
11000 + }
11001 +
11002 + flush_cache_all();
11003 +
11004 +done:
11005 + if (name != tmp)
11006 + kfree(name);
11007 +
11008 + return ret;
11009 +}
11010 +
11011 +static ssize_t
11012 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
11013 +{
11014 + char tmp[100], *name = tmp, *value;
11015 + ssize_t ret;
11016 +
11017 + if (count > sizeof(tmp)) {
11018 + if (!(name = kmalloc(count, GFP_KERNEL)))
11019 + return -ENOMEM;
11020 + }
11021 +
11022 + if (copy_from_user(name, buf, count)) {
11023 + ret = -EFAULT;
11024 + goto done;
11025 + }
11026 +
11027 + value = name;
11028 + name = strsep(&value, "=");
11029 + if (value)
11030 + ret = nvram_set(name, value) ? : count;
11031 + else
11032 + ret = nvram_unset(name) ? : count;
11033 +
11034 + done:
11035 + if (name != tmp)
11036 + kfree(name);
11037 +
11038 + return ret;
11039 +}
11040 +
11041 +static int
11042 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
11043 +{
11044 + if (cmd != NVRAM_MAGIC)
11045 + return -EINVAL;
11046 + return nvram_commit();
11047 +}
11048 +
11049 +static int
11050 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
11051 +{
11052 + unsigned long offset = virt_to_phys(nvram_buf);
11053 +
11054 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
11055 + vma->vm_page_prot))
11056 + return -EAGAIN;
11057 +
11058 + return 0;
11059 +}
11060 +
11061 +static int
11062 +dev_nvram_open(struct inode *inode, struct file * file)
11063 +{
11064 + MOD_INC_USE_COUNT;
11065 + return 0;
11066 +}
11067 +
11068 +static int
11069 +dev_nvram_release(struct inode *inode, struct file * file)
11070 +{
11071 + MOD_DEC_USE_COUNT;
11072 + return 0;
11073 +}
11074 +
11075 +static struct file_operations dev_nvram_fops = {
11076 + owner: THIS_MODULE,
11077 + open: dev_nvram_open,
11078 + release: dev_nvram_release,
11079 + read: dev_nvram_read,
11080 + write: dev_nvram_write,
11081 + ioctl: dev_nvram_ioctl,
11082 + mmap: dev_nvram_mmap,
11083 +};
11084 +
11085 +static void
11086 +dev_nvram_exit(void)
11087 +{
11088 + int order = 0;
11089 + struct page *page, *end;
11090 +
11091 + if (nvram_handle)
11092 + devfs_unregister(nvram_handle);
11093 +
11094 + if (nvram_major >= 0)
11095 + devfs_unregister_chrdev(nvram_major, "nvram");
11096 +
11097 + if (nvram_mtd)
11098 + put_mtd_device(nvram_mtd);
11099 +
11100 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11101 + order++;
11102 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11103 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11104 + mem_map_unreserve(page);
11105 +
11106 + _nvram_exit();
11107 +}
11108 +
11109 +static int __init
11110 +dev_nvram_init(void)
11111 +{
11112 + int order = 0, ret = 0;
11113 + struct page *page, *end;
11114 + unsigned int i;
11115 +
11116 + /* Allocate and reserve memory to mmap() */
11117 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11118 + order++;
11119 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11120 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11121 + mem_map_reserve(page);
11122 +
11123 +#ifdef CONFIG_MTD
11124 + /* Find associated MTD device */
11125 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
11126 + nvram_mtd = get_mtd_device(NULL, i);
11127 + if (nvram_mtd) {
11128 + if (!strcmp(nvram_mtd->name, "nvram") &&
11129 + nvram_mtd->size >= NVRAM_SPACE)
11130 + break;
11131 + put_mtd_device(nvram_mtd);
11132 + }
11133 + }
11134 + if (i >= MAX_MTD_DEVICES)
11135 + nvram_mtd = NULL;
11136 +#endif
11137 +
11138 + /* Initialize hash table lock */
11139 + spin_lock_init(&nvram_lock);
11140 +
11141 + /* Initialize commit semaphore */
11142 + init_MUTEX(&nvram_sem);
11143 +
11144 + /* Register char device */
11145 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
11146 + ret = nvram_major;
11147 + goto err;
11148 + }
11149 +
11150 + /* Initialize hash table */
11151 + _nvram_init();
11152 +
11153 + /* Create /dev/nvram handle */
11154 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
11155 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
11156 +
11157 + /* Set the SDRAM NCDL value into NVRAM if not already done */
11158 + if (getintvar(NULL, "sdram_ncdl") == 0) {
11159 + unsigned int ncdl;
11160 + char buf[] = "0x00000000";
11161 +
11162 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
11163 + sprintf(buf, "0x%08x", ncdl);
11164 + nvram_set("sdram_ncdl", buf);
11165 + nvram_commit();
11166 + }
11167 + }
11168 +
11169 + return 0;
11170 +
11171 + err:
11172 + dev_nvram_exit();
11173 + return ret;
11174 +}
11175 +
11176 +module_init(dev_nvram_init);
11177 +module_exit(dev_nvram_exit);
11178 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
11179 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
11180 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-11-07 23:59:38.908750500 +0100
11181 @@ -0,0 +1,355 @@
11182 +/*
11183 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
11184 + *
11185 + * Copyright 2005, Broadcom Corporation
11186 + * All Rights Reserved.
11187 + *
11188 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11189 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11190 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11191 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11192 + *
11193 + * $Id$
11194 + */
11195 +
11196 +#include <linux/config.h>
11197 +#include <linux/types.h>
11198 +#include <linux/kernel.h>
11199 +#include <linux/sched.h>
11200 +#include <linux/pci.h>
11201 +#include <linux/init.h>
11202 +#include <linux/delay.h>
11203 +#include <asm/io.h>
11204 +#include <asm/irq.h>
11205 +#include <asm/paccess.h>
11206 +
11207 +#include <typedefs.h>
11208 +#include <bcmutils.h>
11209 +#include <sbconfig.h>
11210 +#include <sbutils.h>
11211 +#include <sbpci.h>
11212 +#include <pcicfg.h>
11213 +#include <bcmdevs.h>
11214 +#include <bcmnvram.h>
11215 +
11216 +/* Global SB handle */
11217 +extern sb_t *bcm947xx_sbh;
11218 +extern spinlock_t bcm947xx_sbh_lock;
11219 +
11220 +/* Convenience */
11221 +#define sbh bcm947xx_sbh
11222 +#define sbh_lock bcm947xx_sbh_lock
11223 +
11224 +static int
11225 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
11226 +{
11227 + unsigned long flags;
11228 + int ret;
11229 +
11230 + spin_lock_irqsave(&sbh_lock, flags);
11231 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11232 + spin_unlock_irqrestore(&sbh_lock, flags);
11233 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11234 +}
11235 +
11236 +static int
11237 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
11238 +{
11239 + unsigned long flags;
11240 + int ret;
11241 +
11242 + spin_lock_irqsave(&sbh_lock, flags);
11243 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11244 + spin_unlock_irqrestore(&sbh_lock, flags);
11245 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11246 +}
11247 +
11248 +static int
11249 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
11250 +{
11251 + unsigned long flags;
11252 + int ret;
11253 +
11254 + spin_lock_irqsave(&sbh_lock, flags);
11255 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11256 + spin_unlock_irqrestore(&sbh_lock, flags);
11257 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11258 +}
11259 +
11260 +static int
11261 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
11262 +{
11263 + unsigned long flags;
11264 + int ret;
11265 +
11266 + spin_lock_irqsave(&sbh_lock, flags);
11267 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11268 + spin_unlock_irqrestore(&sbh_lock, flags);
11269 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11270 +}
11271 +
11272 +static int
11273 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
11274 +{
11275 + unsigned long flags;
11276 + int ret;
11277 +
11278 + spin_lock_irqsave(&sbh_lock, flags);
11279 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11280 + spin_unlock_irqrestore(&sbh_lock, flags);
11281 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11282 +}
11283 +
11284 +static int
11285 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
11286 +{
11287 + unsigned long flags;
11288 + int ret;
11289 +
11290 + spin_lock_irqsave(&sbh_lock, flags);
11291 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11292 + spin_unlock_irqrestore(&sbh_lock, flags);
11293 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11294 +}
11295 +
11296 +static struct pci_ops pcibios_ops = {
11297 + sbpci_read_config_byte,
11298 + sbpci_read_config_word,
11299 + sbpci_read_config_dword,
11300 + sbpci_write_config_byte,
11301 + sbpci_write_config_word,
11302 + sbpci_write_config_dword
11303 +};
11304 +
11305 +
11306 +void __init
11307 +pcibios_init(void)
11308 +{
11309 + ulong flags;
11310 +
11311 + if (!(sbh = sb_kattach()))
11312 + panic("sb_kattach failed");
11313 + spin_lock_init(&sbh_lock);
11314 +
11315 + spin_lock_irqsave(&sbh_lock, flags);
11316 + sbpci_init(sbh);
11317 + spin_unlock_irqrestore(&sbh_lock, flags);
11318 +
11319 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11320 +
11321 + mdelay(300); //By Joey for Atheros Card
11322 +
11323 + /* Scan the SB bus */
11324 + pci_scan_bus(0, &pcibios_ops, NULL);
11325 +
11326 +}
11327 +
11328 +char * __init
11329 +pcibios_setup(char *str)
11330 +{
11331 + if (!strncmp(str, "ban=", 4)) {
11332 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
11333 + return NULL;
11334 + }
11335 +
11336 + return (str);
11337 +}
11338 +
11339 +static u32 pci_iobase = 0x100;
11340 +static u32 pci_membase = SB_PCI_DMA;
11341 +
11342 +void __init
11343 +pcibios_fixup_bus(struct pci_bus *b)
11344 +{
11345 + struct list_head *ln;
11346 + struct pci_dev *d;
11347 + struct resource *res;
11348 + int pos, size;
11349 + u32 *base;
11350 + u8 irq;
11351 +
11352 + printk("PCI: Fixing up bus %d\n", b->number);
11353 +
11354 + /* Fix up SB */
11355 + if (b->number == 0) {
11356 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11357 + d = pci_dev_b(ln);
11358 + /* Fix up interrupt lines */
11359 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
11360 + d->irq = irq + 2;
11361 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11362 + }
11363 + }
11364 +
11365 + /* Fix up external PCI */
11366 + else {
11367 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11368 + d = pci_dev_b(ln);
11369 + /* Fix up resource bases */
11370 + for (pos = 0; pos < 6; pos++) {
11371 + res = &d->resource[pos];
11372 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
11373 + if (res->end) {
11374 + size = res->end - res->start + 1;
11375 + if (*base & (size - 1))
11376 + *base = (*base + size) & ~(size - 1);
11377 + res->start = *base;
11378 + res->end = res->start + size - 1;
11379 + *base += size;
11380 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11381 + }
11382 + /* Fix up PCI bridge BAR0 only */
11383 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
11384 + break;
11385 + }
11386 + /* Fix up interrupt lines */
11387 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11388 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11389 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11390 + }
11391 + }
11392 +}
11393 +
11394 +unsigned int
11395 +pcibios_assign_all_busses(void)
11396 +{
11397 + return 1;
11398 +}
11399 +
11400 +void
11401 +pcibios_align_resource(void *data, struct resource *res,
11402 + unsigned long size, unsigned long align)
11403 +{
11404 +}
11405 +
11406 +int
11407 +pcibios_enable_resources(struct pci_dev *dev)
11408 +{
11409 + u16 cmd, old_cmd;
11410 + int idx;
11411 + struct resource *r;
11412 +
11413 + /* External PCI only */
11414 + if (dev->bus->number == 0)
11415 + return 0;
11416 +
11417 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11418 + old_cmd = cmd;
11419 + for(idx=0; idx<6; idx++) {
11420 + r = &dev->resource[idx];
11421 + if (r->flags & IORESOURCE_IO)
11422 + cmd |= PCI_COMMAND_IO;
11423 + if (r->flags & IORESOURCE_MEM)
11424 + cmd |= PCI_COMMAND_MEMORY;
11425 + }
11426 + if (dev->resource[PCI_ROM_RESOURCE].start)
11427 + cmd |= PCI_COMMAND_MEMORY;
11428 + if (cmd != old_cmd) {
11429 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
11430 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11431 + }
11432 + return 0;
11433 +}
11434 +
11435 +int
11436 +pcibios_enable_device(struct pci_dev *dev, int mask)
11437 +{
11438 + ulong flags;
11439 + uint coreidx;
11440 +
11441 + /* External PCI device enable */
11442 + if (dev->bus->number != 0)
11443 + return pcibios_enable_resources(dev);
11444 +
11445 + /* These cores come out of reset enabled */
11446 + if (dev->device == SB_MIPS ||
11447 + dev->device == SB_MIPS33 ||
11448 + dev->device == SB_EXTIF ||
11449 + dev->device == SB_CC)
11450 + return 0;
11451 +
11452 + spin_lock_irqsave(&sbh_lock, flags);
11453 + coreidx = sb_coreidx(sbh);
11454 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
11455 + return PCIBIOS_DEVICE_NOT_FOUND;
11456 +
11457 + /*
11458 + * The USB core requires a special bit to be set during core
11459 + * reset to enable host (OHCI) mode. Resetting the SB core in
11460 + * pcibios_enable_device() is a hack for compatibility with
11461 + * vanilla usb-ohci so that it does not have to know about
11462 + * SB. A driver that wants to use the USB core in device mode
11463 + * should know about SB and should reset the bit back to 0
11464 + * after calling pcibios_enable_device().
11465 + */
11466 + if (sb_coreid(sbh) == SB_USB) {
11467 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11468 + sb_core_reset(sbh, 1 << 29);
11469 + } else
11470 + sb_core_reset(sbh, 0);
11471 +
11472 + sb_setcoreidx(sbh, coreidx);
11473 + spin_unlock_irqrestore(&sbh_lock, flags);
11474 +
11475 + return 0;
11476 +}
11477 +
11478 +void
11479 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
11480 + struct resource *res, int resource)
11481 +{
11482 + unsigned long where, size;
11483 + u32 reg;
11484 +
11485 + /* External PCI only */
11486 + if (dev->bus->number == 0)
11487 + return;
11488 +
11489 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
11490 + size = res->end - res->start;
11491 + pci_read_config_dword(dev, where, &reg);
11492 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
11493 + pci_write_config_dword(dev, where, reg);
11494 +}
11495 +
11496 +static void __init
11497 +quirk_sbpci_bridge(struct pci_dev *dev)
11498 +{
11499 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11500 + return;
11501 +
11502 + printk("PCI: Fixing up bridge\n");
11503 +
11504 + /* Enable PCI bridge bus mastering and memory space */
11505 + pci_set_master(dev);
11506 + pcibios_enable_resources(dev);
11507 +
11508 + /* Enable PCI bridge BAR1 prefetch and burst */
11509 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11510 +}
11511 +
11512 +struct pci_fixup pcibios_fixups[] = {
11513 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
11514 + { 0 }
11515 +};
11516 +
11517 +/*
11518 + * If we set up a device for bus mastering, we need to check the latency
11519 + * timer as certain crappy BIOSes forget to set it properly.
11520 + */
11521 +unsigned int pcibios_max_latency = 255;
11522 +
11523 +void pcibios_set_master(struct pci_dev *dev)
11524 +{
11525 + u8 lat;
11526 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
11527 + if (lat < 16)
11528 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
11529 + else if (lat > pcibios_max_latency)
11530 + lat = pcibios_max_latency;
11531 + else
11532 + return;
11533 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
11534 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
11535 +}
11536 +
11537 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11538 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11539 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-11-07 21:57:07.885588250 +0100
11540 @@ -0,0 +1,41 @@
11541 +/*
11542 + * Early initialization code for BCM94710 boards
11543 + *
11544 + * Copyright 2004, Broadcom Corporation
11545 + * All Rights Reserved.
11546 + *
11547 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11548 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11549 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11550 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11551 + *
11552 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
11553 + */
11554 +
11555 +#include <linux/config.h>
11556 +#include <linux/init.h>
11557 +#include <linux/kernel.h>
11558 +#include <linux/types.h>
11559 +#include <asm/bootinfo.h>
11560 +
11561 +void __init
11562 +prom_init(int argc, const char **argv)
11563 +{
11564 + unsigned long mem;
11565 +
11566 + mips_machgroup = MACH_GROUP_BRCM;
11567 + mips_machtype = MACH_BCM947XX;
11568 +
11569 + /* Figure out memory size by finding aliases */
11570 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11571 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11572 + *(unsigned long *)(prom_init))
11573 + break;
11574 + }
11575 + add_memory_region(0, mem, BOOT_MEM_RAM);
11576 +}
11577 +
11578 +void __init
11579 +prom_free_prom_memory(void)
11580 +{
11581 +}
11582 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
11583 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
11584 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-11-07 23:55:45.682174750 +0100
11585 @@ -0,0 +1,1038 @@
11586 +/*
11587 + * BCM47XX Sonics SiliconBackplane MIPS core routines
11588 + *
11589 + * Copyright 2005, Broadcom Corporation
11590 + * All Rights Reserved.
11591 + *
11592 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11593 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11594 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11595 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11596 + *
11597 + * $Id$
11598 + */
11599 +
11600 +#include <typedefs.h>
11601 +#include <osl.h>
11602 +#include <sbutils.h>
11603 +#include <bcmdevs.h>
11604 +#include <bcmnvram.h>
11605 +#include <bcmutils.h>
11606 +#include <hndmips.h>
11607 +#include <sbconfig.h>
11608 +#include <sbextif.h>
11609 +#include <sbchipc.h>
11610 +#include <sbmemc.h>
11611 +#include <mipsinc.h>
11612 +#include <sbutils.h>
11613 +
11614 +/*
11615 + * Returns TRUE if an external UART exists at the given base
11616 + * register.
11617 + */
11618 +static bool
11619 +BCMINITFN(serial_exists)(uint8 *regs)
11620 +{
11621 + uint8 save_mcr, status1;
11622 +
11623 + save_mcr = R_REG(&regs[UART_MCR]);
11624 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
11625 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
11626 + W_REG(&regs[UART_MCR], save_mcr);
11627 +
11628 + return (status1 == 0x90);
11629 +}
11630 +
11631 +/*
11632 + * Initializes UART access. The callback function will be called once
11633 + * per found UART.
11634 + */
11635 +void
11636 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
11637 +{
11638 + void *regs;
11639 + ulong base;
11640 + uint irq;
11641 + int i, n;
11642 +
11643 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
11644 + extifregs_t *eir = (extifregs_t *) regs;
11645 + sbconfig_t *sb;
11646 +
11647 + /* Determine external UART register base */
11648 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
11649 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
11650 +
11651 + /* Determine IRQ */
11652 + irq = sb_irq(sbh);
11653 +
11654 + /* Disable GPIO interrupt initially */
11655 + W_REG(&eir->gpiointpolarity, 0);
11656 + W_REG(&eir->gpiointmask, 0);
11657 +
11658 + /* Search for external UARTs */
11659 + n = 2;
11660 + for (i = 0; i < 2; i++) {
11661 + regs = (void *) REG_MAP(base + (i * 8), 8);
11662 + if (BCMINIT(serial_exists)(regs)) {
11663 + /* Set GPIO 1 to be the external UART IRQ */
11664 + W_REG(&eir->gpiointmask, 2);
11665 + if (add)
11666 + add(regs, irq, 13500000, 0);
11667 + }
11668 + }
11669 +
11670 + /* Add internal UART if enabled */
11671 + if (R_REG(&eir->corecontrol) & CC_UE)
11672 + if (add)
11673 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
11674 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
11675 + chipcregs_t *cc = (chipcregs_t *) regs;
11676 + uint32 rev, cap, pll, baud_base, div;
11677 +
11678 + /* Determine core revision and capabilities */
11679 + rev = sb_corerev(sbh);
11680 + cap = R_REG(&cc->capabilities);
11681 + pll = cap & CAP_PLL_MASK;
11682 +
11683 + /* Determine IRQ */
11684 + irq = sb_irq(sbh);
11685 +
11686 + if (pll == PLL_TYPE1) {
11687 + /* PLL clock */
11688 + baud_base = sb_clock_rate(pll,
11689 + R_REG(&cc->clockcontrol_n),
11690 + R_REG(&cc->clockcontrol_m2));
11691 + div = 1;
11692 + } else {
11693 + if (rev >= 11) {
11694 + /* Fixed ALP clock */
11695 + baud_base = 20000000;
11696 + div = 1;
11697 + /* Set the override bit so we don't divide it */
11698 + W_REG(&cc->corecontrol, CC_UARTCLKO);
11699 + } else if (rev >= 3) {
11700 + /* Internal backplane clock */
11701 + baud_base = sb_clock(sbh);
11702 + div = 2; /* Minimum divisor */
11703 + W_REG(&cc->clkdiv,
11704 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
11705 + } else {
11706 + /* Fixed internal backplane clock */
11707 + baud_base = 88000000;
11708 + div = 48;
11709 + }
11710 +
11711 + /* Clock source depends on strapping if UartClkOverride is unset */
11712 + if ((rev > 0) &&
11713 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
11714 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
11715 + /* Internal divided backplane clock */
11716 + baud_base /= div;
11717 + } else {
11718 + /* Assume external clock of 1.8432 MHz */
11719 + baud_base = 1843200;
11720 + }
11721 + }
11722 + }
11723 +
11724 + /* Add internal UARTs */
11725 + n = cap & CAP_UARTS_MASK;
11726 + for (i = 0; i < n; i++) {
11727 + /* Register offset changed after revision 0 */
11728 + if (rev)
11729 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
11730 + else
11731 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
11732 +
11733 + if (add)
11734 + add(regs, irq, baud_base, 0);
11735 + }
11736 + }
11737 +}
11738 +
11739 +/*
11740 + * Initialize jtag master and return handle for
11741 + * jtag_rwreg. Returns NULL on failure.
11742 + */
11743 +void *
11744 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
11745 +{
11746 + void *regs;
11747 +
11748 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
11749 + chipcregs_t *cc = (chipcregs_t *) regs;
11750 + uint32 tmp;
11751 +
11752 + /*
11753 + * Determine jtagm availability from
11754 + * core revision and capabilities.
11755 + */
11756 + tmp = sb_corerev(sbh);
11757 + /*
11758 + * Corerev 10 has jtagm, but the only chip
11759 + * with it does not have a mips, and
11760 + * the layout of the jtagcmd register is
11761 + * different. We'll only accept >= 11.
11762 + */
11763 + if (tmp < 11)
11764 + return (NULL);
11765 +
11766 + tmp = R_REG(&cc->capabilities);
11767 + if ((tmp & CAP_JTAGP) == 0)
11768 + return (NULL);
11769 +
11770 + /* Set clock divider if requested */
11771 + if (clkd != 0) {
11772 + tmp = R_REG(&cc->clkdiv);
11773 + tmp = (tmp & ~CLKD_JTAG) |
11774 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
11775 + W_REG(&cc->clkdiv, tmp);
11776 + }
11777 +
11778 + /* Enable jtagm */
11779 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
11780 + W_REG(&cc->jtagctrl, tmp);
11781 + }
11782 +
11783 + return (regs);
11784 +}
11785 +
11786 +void
11787 +sb_jtagm_disable(void *h)
11788 +{
11789 + chipcregs_t *cc = (chipcregs_t *)h;
11790 +
11791 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
11792 +}
11793 +
11794 +/*
11795 + * Read/write a jtag register. Assumes a target with
11796 + * 8 bit IR and 32 bit DR.
11797 + */
11798 +#define IRWIDTH 8
11799 +#define DRWIDTH 32
11800 +uint32
11801 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
11802 +{
11803 + chipcregs_t *cc = (chipcregs_t *) h;
11804 + uint32 tmp;
11805 +
11806 + W_REG(&cc->jtagir, ir);
11807 + W_REG(&cc->jtagdr, dr);
11808 + tmp = JCMD_START | JCMD_ACC_IRDR |
11809 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
11810 + (DRWIDTH - 1);
11811 + W_REG(&cc->jtagcmd, tmp);
11812 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
11813 + /* OSL_DELAY(1); */
11814 + }
11815 +
11816 + tmp = R_REG(&cc->jtagdr);
11817 + return (tmp);
11818 +}
11819 +
11820 +/* Returns the SB interrupt flag of the current core. */
11821 +uint32
11822 +sb_flag(sb_t *sbh)
11823 +{
11824 + void *regs;
11825 + sbconfig_t *sb;
11826 +
11827 + regs = sb_coreregs(sbh);
11828 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11829 +
11830 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
11831 +}
11832 +
11833 +static const uint32 sbips_int_mask[] = {
11834 + 0,
11835 + SBIPS_INT1_MASK,
11836 + SBIPS_INT2_MASK,
11837 + SBIPS_INT3_MASK,
11838 + SBIPS_INT4_MASK
11839 +};
11840 +
11841 +static const uint32 sbips_int_shift[] = {
11842 + 0,
11843 + 0,
11844 + SBIPS_INT2_SHIFT,
11845 + SBIPS_INT3_SHIFT,
11846 + SBIPS_INT4_SHIFT
11847 +};
11848 +
11849 +/*
11850 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
11851 + * 0 is returned.
11852 + */
11853 +uint
11854 +sb_irq(sb_t *sbh)
11855 +{
11856 + uint idx;
11857 + void *regs;
11858 + sbconfig_t *sb;
11859 + uint32 flag, sbipsflag;
11860 + uint irq = 0;
11861 +
11862 + flag = sb_flag(sbh);
11863 +
11864 + idx = sb_coreidx(sbh);
11865 +
11866 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
11867 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
11868 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11869 +
11870 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
11871 + sbipsflag = R_REG(&sb->sbipsflag);
11872 + for (irq = 1; irq <= 4; irq++) {
11873 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
11874 + break;
11875 + }
11876 + if (irq == 5)
11877 + irq = 0;
11878 + }
11879 +
11880 + sb_setcoreidx(sbh, idx);
11881 +
11882 + return irq;
11883 +}
11884 +
11885 +/* Clears the specified MIPS IRQ. */
11886 +static void
11887 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
11888 +{
11889 + void *regs;
11890 + sbconfig_t *sb;
11891 +
11892 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
11893 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
11894 + ASSERT(regs);
11895 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11896 +
11897 + if (irq == 0)
11898 + W_REG(&sb->sbintvec, 0);
11899 + else
11900 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
11901 +}
11902 +
11903 +/*
11904 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
11905 + * IRQ 0 may be assigned more than once.
11906 + */
11907 +static void
11908 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
11909 +{
11910 + void *regs;
11911 + sbconfig_t *sb;
11912 + uint32 flag;
11913 +
11914 + regs = sb_setcore(sbh, coreid, coreunit);
11915 + ASSERT(regs);
11916 + flag = sb_flag(sbh);
11917 +
11918 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
11919 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
11920 + ASSERT(regs);
11921 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11922 +
11923 + if (irq == 0)
11924 + OR_REG(&sb->sbintvec, 1 << flag);
11925 + else {
11926 + flag <<= sbips_int_shift[irq];
11927 + ASSERT(!(flag & ~sbips_int_mask[irq]));
11928 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
11929 + W_REG(&sb->sbipsflag, flag);
11930 + }
11931 +}
11932 +
11933 +/*
11934 + * Initializes clocks and interrupts. SB and NVRAM access must be
11935 + * initialized prior to calling.
11936 + */
11937 +void
11938 +BCMINITFN(sb_mips_init)(sb_t *sbh)
11939 +{
11940 + ulong hz, ns, tmp;
11941 + extifregs_t *eir;
11942 + chipcregs_t *cc;
11943 + char *value;
11944 + uint irq;
11945 +
11946 + /* Figure out current SB clock speed */
11947 + if ((hz = sb_clock(sbh)) == 0)
11948 + hz = 100000000;
11949 + ns = 1000000000 / hz;
11950 +
11951 + /* Setup external interface timing */
11952 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
11953 + /* Initialize extif so we can get to the LEDs and external UART */
11954 + W_REG(&eir->prog_config, CF_EN);
11955 +
11956 + /* Set timing for the flash */
11957 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
11958 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
11959 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
11960 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
11961 +
11962 + /* Set programmable interface timing for external uart */
11963 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
11964 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
11965 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
11966 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
11967 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
11968 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
11969 + /* Set timing for the flash */
11970 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
11971 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
11972 + tmp |= CEIL(120, ns); /* W0 = 120nS */
11973 +
11974 + // Added by Chen-I for 5365
11975 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
11976 + {
11977 + W_REG(&cc->flash_waitcount, tmp);
11978 + W_REG(&cc->pcmcia_memwait, tmp);
11979 + }
11980 + else
11981 + {
11982 + if (sb_corerev(sbh) < 9)
11983 + W_REG(&cc->flash_waitcount, tmp);
11984 +
11985 + if ((sb_corerev(sbh) < 9) ||
11986 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
11987 + W_REG(&cc->pcmcia_memwait, tmp);
11988 + }
11989 + }
11990 + }
11991 +
11992 + /* Chip specific initialization */
11993 + switch (BCMINIT(sb_chip)(sbh)) {
11994 + case BCM4710_DEVICE_ID:
11995 + /* Clear interrupt map */
11996 + for (irq = 0; irq <= 4; irq++)
11997 + BCMINIT(sb_clearirq)(sbh, irq);
11998 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
11999 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
12000 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
12001 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
12002 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
12003 + ASSERT(eir);
12004 + value = BCMINIT(nvram_get)("et0phyaddr");
12005 + if (value && !strcmp(value, "31")) {
12006 + /* Enable internal UART */
12007 + W_REG(&eir->corecontrol, CC_UE);
12008 + /* Give USB its own interrupt */
12009 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
12010 + } else {
12011 + /* Disable internal UART */
12012 + W_REG(&eir->corecontrol, 0);
12013 + /* Give Ethernet its own interrupt */
12014 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
12015 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
12016 + }
12017 + break;
12018 + case BCM5350_DEVICE_ID:
12019 + /* Clear interrupt map */
12020 + for (irq = 0; irq <= 4; irq++)
12021 + BCMINIT(sb_clearirq)(sbh, irq);
12022 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
12023 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
12024 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
12025 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
12026 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
12027 + break;
12028 + }
12029 +}
12030 +
12031 +uint32
12032 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
12033 +{
12034 + extifregs_t *eir;
12035 + chipcregs_t *cc;
12036 + uint32 n, m;
12037 + uint idx;
12038 + uint32 pll_type, rate = 0;
12039 +
12040 + /* get index of the current core */
12041 + idx = sb_coreidx(sbh);
12042 + pll_type = PLL_TYPE1;
12043 +
12044 + /* switch to extif or chipc core */
12045 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12046 + n = R_REG(&eir->clockcontrol_n);
12047 + m = R_REG(&eir->clockcontrol_sb);
12048 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12049 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12050 + n = R_REG(&cc->clockcontrol_n);
12051 + if ((pll_type == PLL_TYPE2) ||
12052 + (pll_type == PLL_TYPE4) ||
12053 + (pll_type == PLL_TYPE6) ||
12054 + (pll_type == PLL_TYPE7))
12055 + m = R_REG(&cc->clockcontrol_mips);
12056 + else if (pll_type == PLL_TYPE5) {
12057 + rate = 200000000;
12058 + goto out;
12059 + }
12060 + else if (pll_type == PLL_TYPE3) {
12061 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
12062 + rate = 200000000;
12063 + goto out;
12064 + } else
12065 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
12066 + } else
12067 + m = R_REG(&cc->clockcontrol_sb);
12068 + } else
12069 + goto out;
12070 +
12071 + // Added by Chen-I for 5365
12072 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12073 + rate = 100000000;
12074 + else
12075 + /* calculate rate */
12076 + rate = sb_clock_rate(pll_type, n, m);
12077 +
12078 + if (pll_type == PLL_TYPE6)
12079 + rate = SB2MIPS_T6(rate);
12080 +
12081 +out:
12082 + /* switch back to previous core */
12083 + sb_setcoreidx(sbh, idx);
12084 +
12085 + return rate;
12086 +}
12087 +
12088 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
12089 +
12090 +static void
12091 +BCMINITFN(handler)(void)
12092 +{
12093 + /* Step 11 */
12094 + __asm__ (
12095 + ".set\tmips32\n\t"
12096 + "ssnop\n\t"
12097 + "ssnop\n\t"
12098 + /* Disable interrupts */
12099 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
12100 + "mfc0 $15, $12\n\t"
12101 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
12102 + "li $14, -31746\n\t"
12103 + "and $15, $15, $14\n\t"
12104 + "mtc0 $15, $12\n\t"
12105 + "eret\n\t"
12106 + "nop\n\t"
12107 + "nop\n\t"
12108 + ".set\tmips0"
12109 + );
12110 +}
12111 +
12112 +/* The following MUST come right after handler() */
12113 +static void
12114 +BCMINITFN(afterhandler)(void)
12115 +{
12116 +}
12117 +
12118 +/*
12119 + * Set the MIPS, backplane and PCI clocks as closely as possible.
12120 + */
12121 +bool
12122 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
12123 +{
12124 + extifregs_t *eir = NULL;
12125 + chipcregs_t *cc = NULL;
12126 + mipsregs_t *mipsr = NULL;
12127 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
12128 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
12129 + uint32 pll_type, sync_mode;
12130 + uint ic_size, ic_lsize;
12131 + uint idx, i;
12132 + typedef struct {
12133 + uint32 mipsclock;
12134 + uint16 n;
12135 + uint32 sb;
12136 + uint32 pci33;
12137 + uint32 pci25;
12138 + } n3m_table_t;
12139 + static n3m_table_t BCMINITDATA(type1_table)[] = {
12140 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
12141 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
12142 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
12143 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
12144 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
12145 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
12146 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
12147 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
12148 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
12149 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
12150 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
12151 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
12152 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
12153 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
12154 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
12155 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
12156 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
12157 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
12158 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
12159 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
12160 + };
12161 + typedef struct {
12162 + uint32 mipsclock;
12163 + uint16 n;
12164 + uint32 m2; /* that is the clockcontrol_m2 */
12165 + } type3_table_t;
12166 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
12167 + { 150000000, 0x311, 0x4020005 },
12168 + { 200000000, 0x311, 0x4020003 },
12169 + };
12170 + typedef struct {
12171 + uint32 mipsclock;
12172 + uint32 sbclock;
12173 + uint16 n;
12174 + uint32 sb;
12175 + uint32 pci33;
12176 + uint32 m2;
12177 + uint32 m3;
12178 + uint32 ratio_cfg;
12179 + uint32 ratio_parm;
12180 + } n4m_table_t;
12181 +
12182 + static n4m_table_t BCMINITDATA(type2_table)[] = {
12183 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12184 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12185 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
12186 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12187 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12188 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12189 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12190 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12191 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12192 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12193 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12194 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12195 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12196 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12197 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12198 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12199 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
12200 + };
12201 +
12202 + static n4m_table_t BCMINITDATA(type4_table)[] = {
12203 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12204 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12205 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12206 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12207 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12208 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12209 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12210 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12211 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
12212 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12213 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
12214 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12215 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
12216 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12217 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12218 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12219 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12220 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12221 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
12222 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
12223 + };
12224 +
12225 + static n4m_table_t BCMINITDATA(type7_table)[] = {
12226 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12227 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12228 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12229 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
12230 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12231 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12232 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12233 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12234 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12235 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12236 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12237 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12238 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
12239 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
12240 + };
12241 +
12242 + ulong start, end, dst;
12243 + bool ret = FALSE;
12244 +
12245 + /* get index of the current core */
12246 + idx = sb_coreidx(sbh);
12247 + clockcontrol_m2 = NULL;
12248 +
12249 + /* switch to extif or chipc core */
12250 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12251 + pll_type = PLL_TYPE1;
12252 + clockcontrol_n = &eir->clockcontrol_n;
12253 + clockcontrol_sb = &eir->clockcontrol_sb;
12254 + clockcontrol_pci = &eir->clockcontrol_pci;
12255 + clockcontrol_m2 = &cc->clockcontrol_m2;
12256 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12257 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12258 + if (pll_type == PLL_TYPE6) {
12259 + clockcontrol_n = NULL;
12260 + clockcontrol_sb = NULL;
12261 + clockcontrol_pci = NULL;
12262 + } else {
12263 + clockcontrol_n = &cc->clockcontrol_n;
12264 + clockcontrol_sb = &cc->clockcontrol_sb;
12265 + clockcontrol_pci = &cc->clockcontrol_pci;
12266 + clockcontrol_m2 = &cc->clockcontrol_m2;
12267 + }
12268 + } else
12269 + goto done;
12270 +
12271 + if (pll_type == PLL_TYPE6) {
12272 + /* Silence compilers */
12273 + orig_n = orig_sb = orig_pci = 0;
12274 + } else {
12275 + /* Store the current clock register values */
12276 + orig_n = R_REG(clockcontrol_n);
12277 + orig_sb = R_REG(clockcontrol_sb);
12278 + orig_pci = R_REG(clockcontrol_pci);
12279 + }
12280 +
12281 + if (pll_type == PLL_TYPE1) {
12282 + /* Keep the current PCI clock if not specified */
12283 + if (pciclock == 0) {
12284 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
12285 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
12286 + }
12287 +
12288 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12289 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
12290 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
12291 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
12292 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
12293 + break;
12294 + }
12295 + if (i == 0) {
12296 + ret = FALSE;
12297 + goto done;
12298 + } else {
12299 + ret = TRUE;
12300 + i--;
12301 + }
12302 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
12303 +
12304 + /* No PLL change */
12305 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
12306 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
12307 + (orig_pci == BCMINIT(type1_table)[i].pci33))
12308 + goto done;
12309 +
12310 + /* Set the PLL controls */
12311 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
12312 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
12313 + if (pciclock == 25000000)
12314 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
12315 + else
12316 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
12317 +
12318 + /* Reset */
12319 + sb_watchdog(sbh, 1);
12320 +
12321 + while (1);
12322 + } else if ((pll_type == PLL_TYPE3) &&
12323 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
12324 + /* 5350 */
12325 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12326 +
12327 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
12328 + if (type3_table[i].mipsclock > mipsclock)
12329 + break;
12330 + }
12331 + if (i == 0) {
12332 + ret = FALSE;
12333 + goto done;
12334 + } else {
12335 + ret = TRUE;
12336 + i--;
12337 + }
12338 + ASSERT(type3_table[i].mipsclock <= mipsclock);
12339 +
12340 + /* No PLL change */
12341 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12342 + if ((orig_n == type3_table[i].n) &&
12343 + (orig_m2 == type3_table[i].m2)) {
12344 + goto done;
12345 + }
12346 +
12347 + /* Set the PLL controls */
12348 + W_REG(clockcontrol_n, type3_table[i].n);
12349 + W_REG(clockcontrol_m2, type3_table[i].m2);
12350 +
12351 + /* Reset */
12352 + sb_watchdog(sbh, 1);
12353 + while (1);
12354 + } else if ((pll_type == PLL_TYPE2) ||
12355 + (pll_type == PLL_TYPE4) ||
12356 + (pll_type == PLL_TYPE6) ||
12357 + (pll_type == PLL_TYPE7)) {
12358 + n4m_table_t *table = NULL, *te;
12359 + uint tabsz = 0;
12360 +
12361 + ASSERT(cc);
12362 +
12363 + orig_mips = R_REG(&cc->clockcontrol_mips);
12364 +
12365 + if (pll_type == PLL_TYPE6) {
12366 + uint32 new_mips = 0;
12367 +
12368 + ret = TRUE;
12369 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
12370 + new_mips = CC_T6_MMASK;
12371 +
12372 + if (orig_mips == new_mips)
12373 + goto done;
12374 +
12375 + W_REG(&cc->clockcontrol_mips, new_mips);
12376 + goto end_fill;
12377 + }
12378 +
12379 + if (pll_type == PLL_TYPE2) {
12380 + table = BCMINIT(type2_table);
12381 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
12382 + } else if (pll_type == PLL_TYPE4) {
12383 + table = BCMINIT(type4_table);
12384 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
12385 + } else if (pll_type == PLL_TYPE7) {
12386 + table = BCMINIT(type7_table);
12387 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
12388 + } else
12389 + ASSERT("No table for plltype" == NULL);
12390 +
12391 + /* Store the current clock register values */
12392 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12393 + orig_ratio_parm = 0;
12394 + orig_ratio_cfg = 0;
12395 +
12396 + /* Look up current ratio */
12397 + for (i = 0; i < tabsz; i++) {
12398 + if ((orig_n == table[i].n) &&
12399 + (orig_sb == table[i].sb) &&
12400 + (orig_pci == table[i].pci33) &&
12401 + (orig_m2 == table[i].m2) &&
12402 + (orig_mips == table[i].m3)) {
12403 + orig_ratio_parm = table[i].ratio_parm;
12404 + orig_ratio_cfg = table[i].ratio_cfg;
12405 + break;
12406 + }
12407 + }
12408 +
12409 + /* Search for the closest MIPS clock greater or equal to a preferred value */
12410 + for (i = 0; i < tabsz; i++) {
12411 + ASSERT(table[i].mipsclock ==
12412 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
12413 + if ((mipsclock <= table[i].mipsclock) &&
12414 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
12415 + break;
12416 + }
12417 + if (i == tabsz) {
12418 + ret = FALSE;
12419 + goto done;
12420 + } else {
12421 + te = &table[i];
12422 + ret = TRUE;
12423 + }
12424 +
12425 + /* No PLL change */
12426 + if ((orig_n == te->n) &&
12427 + (orig_sb == te->sb) &&
12428 + (orig_pci == te->pci33) &&
12429 + (orig_m2 == te->m2) &&
12430 + (orig_mips == te->m3))
12431 + goto done;
12432 +
12433 + /* Set the PLL controls */
12434 + W_REG(clockcontrol_n, te->n);
12435 + W_REG(clockcontrol_sb, te->sb);
12436 + W_REG(clockcontrol_pci, te->pci33);
12437 + W_REG(&cc->clockcontrol_m2, te->m2);
12438 + W_REG(&cc->clockcontrol_mips, te->m3);
12439 +
12440 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
12441 + if ((pll_type == PLL_TYPE7) &&
12442 + (te->sb != te->m2) &&
12443 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
12444 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
12445 +
12446 + /* No ratio change */
12447 + if (orig_ratio_parm == te->ratio_parm)
12448 + goto end_fill;
12449 +
12450 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
12451 +
12452 + /* Preload the code into the cache */
12453 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
12454 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
12455 + while (start < end) {
12456 + cache_op(start, Fill_I);
12457 + start += ic_lsize;
12458 + }
12459 +
12460 + /* Copy the handler */
12461 + start = (ulong) &BCMINIT(handler);
12462 + end = (ulong) &BCMINIT(afterhandler);
12463 + dst = KSEG1ADDR(0x180);
12464 + for (i = 0; i < (end - start); i += 4)
12465 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
12466 +
12467 + /* Preload handler into the cache one line at a time */
12468 + for (i = 0; i < (end - start); i += 4)
12469 + cache_op(dst + i, Fill_I);
12470 +
12471 + /* Clear BEV bit */
12472 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
12473 +
12474 + /* Enable interrupts */
12475 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
12476 +
12477 + /* Enable MIPS timer interrupt */
12478 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
12479 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
12480 + ASSERT(mipsr);
12481 + W_REG(&mipsr->intmask, 1);
12482 +
12483 + start_fill:
12484 + /* step 1, set clock ratios */
12485 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
12486 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
12487 +
12488 + /* step 2: program timer intr */
12489 + W_REG(&mipsr->timer, 100);
12490 + (void) R_REG(&mipsr->timer);
12491 +
12492 + /* step 3, switch to async */
12493 + sync_mode = MFC0(C0_BROADCOM, 4);
12494 + MTC0(C0_BROADCOM, 4, 1 << 22);
12495 +
12496 + /* step 4, set cfg active */
12497 + MTC0(C0_BROADCOM, 2, 0x9);
12498 +
12499 +
12500 + /* steps 5 & 6 */
12501 + __asm__ __volatile__ (
12502 + ".set\tmips3\n\t"
12503 + "wait\n\t"
12504 + ".set\tmips0"
12505 + );
12506 +
12507 + /* step 7, clear cfg_active */
12508 + MTC0(C0_BROADCOM, 2, 0);
12509 +
12510 + /* Additional Step: set back to orig sync mode */
12511 + MTC0(C0_BROADCOM, 4, sync_mode);
12512 +
12513 + /* step 8, fake soft reset */
12514 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
12515 +
12516 + end_fill:
12517 + /* step 9 set watchdog timer */
12518 + sb_watchdog(sbh, 20);
12519 + (void) R_REG(&cc->chipid);
12520 +
12521 + /* step 11 */
12522 + __asm__ __volatile__ (
12523 + ".set\tmips3\n\t"
12524 + "sync\n\t"
12525 + "wait\n\t"
12526 + ".set\tmips0"
12527 + );
12528 + while (1);
12529 + }
12530 +
12531 +done:
12532 + /* switch back to previous core */
12533 + sb_setcoreidx(sbh, idx);
12534 +
12535 + return ret;
12536 +}
12537 +
12538 +/*
12539 + * This also must be run from the cache on 47xx
12540 + * so there are no mips core BIU ops in progress
12541 + * when the PFC is enabled.
12542 + */
12543 +
12544 +static void
12545 +BCMINITFN(_enable_pfc)(uint32 mode)
12546 +{
12547 + /* write range */
12548 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
12549 +
12550 + /* enable */
12551 + *(volatile uint32 *)PFC_CR0 = mode;
12552 +}
12553 +
12554 +void
12555 +BCMINITFN(enable_pfc)(uint32 mode)
12556 +{
12557 + ulong start, end;
12558 + int i;
12559 +
12560 + /* If auto then choose the correct mode for this
12561 + platform, currently we only ever select one mode */
12562 + if (mode == PFC_AUTO)
12563 + mode = PFC_INST;
12564 +
12565 + /* enable prefetch cache if available */
12566 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
12567 + start = (ulong) &BCMINIT(_enable_pfc);
12568 + end = (ulong) &BCMINIT(enable_pfc);
12569 +
12570 + /* Preload handler into the cache one line at a time */
12571 + for (i = 0; i < (end - start); i += 4)
12572 + cache_op(start + i, Fill_I);
12573 +
12574 + BCMINIT(_enable_pfc)(mode);
12575 + }
12576 +}
12577 +
12578 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
12579 +uint32
12580 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
12581 +{
12582 + sbmemcregs_t *memc;
12583 + uint32 ret = 0;
12584 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
12585 + uint idx, rev;
12586 +
12587 + idx = sb_coreidx(sbh);
12588 +
12589 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
12590 + if (memc == 0)
12591 + goto out;
12592 +
12593 + rev = sb_corerev(sbh);
12594 +
12595 + config = R_REG(&memc->config);
12596 + wr = R_REG(&memc->wrncdlcor);
12597 + rd = R_REG(&memc->rdncdlcor);
12598 + misc = R_REG(&memc->miscdlyctl);
12599 + dqsg = R_REG(&memc->dqsgatencdl);
12600 +
12601 + rd &= MEMC_RDNCDLCOR_RD_MASK;
12602 + wr &= MEMC_WRNCDLCOR_WR_MASK;
12603 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
12604 +
12605 + if (config & MEMC_CONFIG_DDR) {
12606 + ret = (wr << 16) | (rd << 8) | dqsg;
12607 + } else {
12608 + if (rev > 0)
12609 + cd = rd;
12610 + else
12611 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
12612 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
12613 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
12614 + ret = (sm << 16) | (sd << 8) | cd;
12615 + }
12616 +
12617 +out:
12618 + /* switch back to previous core */
12619 + sb_setcoreidx(sbh, idx);
12620 +
12621 + return ret;
12622 +}
12623 +
12624 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
12625 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
12626 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-11-07 23:53:20.981131500 +0100
12627 @@ -0,0 +1,588 @@
12628 +/*
12629 + * Low-Level PCI and SB support for BCM47xx
12630 + *
12631 + * Copyright 2005, Broadcom Corporation
12632 + * All Rights Reserved.
12633 + *
12634 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12635 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12636 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12637 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12638 + *
12639 + * $Id$
12640 + */
12641 +
12642 +#include <typedefs.h>
12643 +#include <pcicfg.h>
12644 +#include <bcmdevs.h>
12645 +#include <sbconfig.h>
12646 +#include <osl.h>
12647 +#include <sbutils.h>
12648 +#include <sbpci.h>
12649 +#include <bcmendian.h>
12650 +#include <bcmutils.h>
12651 +#include <bcmnvram.h>
12652 +#include <hndmips.h>
12653 +
12654 +/* Can free sbpci_init() memory after boot */
12655 +#ifndef linux
12656 +#define __init
12657 +#endif
12658 +
12659 +/* Emulated configuration space */
12660 +static pci_config_regs sb_config_regs[SB_MAXCORES];
12661 +
12662 +/* Banned cores */
12663 +static uint16 pci_ban[32] = { 0 };
12664 +static uint pci_banned = 0;
12665 +
12666 +/* CardBus mode */
12667 +static bool cardbus = FALSE;
12668 +
12669 +/* Disable PCI host core */
12670 +static bool pci_disabled = FALSE;
12671 +
12672 +/*
12673 + * Functions for accessing external PCI configuration space
12674 + */
12675 +
12676 +/* Assume one-hot slot wiring */
12677 +#define PCI_SLOT_MAX 16
12678 +
12679 +static uint32
12680 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
12681 +{
12682 + uint coreidx;
12683 + sbpciregs_t *regs;
12684 + uint32 addr = 0;
12685 +
12686 + /* CardBusMode supports only one device */
12687 + if (cardbus && dev > 1)
12688 + return 0;
12689 +
12690 + coreidx = sb_coreidx(sbh);
12691 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
12692 +
12693 + /* Type 0 transaction */
12694 + if (bus == 1) {
12695 + /* Skip unwired slots */
12696 + if (dev < PCI_SLOT_MAX) {
12697 + /* Slide the PCI window to the appropriate slot */
12698 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
12699 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
12700 + (func << 8) | (off & ~3);
12701 + }
12702 + }
12703 +
12704 + /* Type 1 transaction */
12705 + else {
12706 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
12707 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
12708 + }
12709 +
12710 + sb_setcoreidx(sbh, coreidx);
12711 +
12712 + return addr;
12713 +}
12714 +
12715 +static int
12716 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12717 +{
12718 + uint32 addr, *reg = NULL, val;
12719 + int ret = 0;
12720 +
12721 + if (pci_disabled ||
12722 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12723 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12724 + BUSPROBE(val, reg))
12725 + val = 0xffffffff;
12726 +
12727 + val >>= 8 * (off & 3);
12728 + if (len == 4)
12729 + *((uint32 *) buf) = val;
12730 + else if (len == 2)
12731 + *((uint16 *) buf) = (uint16) val;
12732 + else if (len == 1)
12733 + *((uint8 *) buf) = (uint8) val;
12734 + else
12735 + ret = -1;
12736 +
12737 + if (reg)
12738 + REG_UNMAP(reg);
12739 +
12740 + return ret;
12741 +}
12742 +
12743 +static int
12744 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12745 +{
12746 + uint32 addr, *reg = NULL, val;
12747 + int ret = 0;
12748 +
12749 + if (pci_disabled ||
12750 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12751 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12752 + BUSPROBE(val, reg))
12753 + goto done;
12754 +
12755 + if (len == 4)
12756 + val = *((uint32 *) buf);
12757 + else if (len == 2) {
12758 + val &= ~(0xffff << (8 * (off & 3)));
12759 + val |= *((uint16 *) buf) << (8 * (off & 3));
12760 + } else if (len == 1) {
12761 + val &= ~(0xff << (8 * (off & 3)));
12762 + val |= *((uint8 *) buf) << (8 * (off & 3));
12763 + } else
12764 + ret = -1;
12765 +
12766 + W_REG(reg, val);
12767 +
12768 + done:
12769 + if (reg)
12770 + REG_UNMAP(reg);
12771 +
12772 + return ret;
12773 +}
12774 +
12775 +/*
12776 + * Functions for accessing translated SB configuration space
12777 + */
12778 +
12779 +static int
12780 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12781 +{
12782 + pci_config_regs *cfg;
12783 +
12784 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12785 + return -1;
12786 + cfg = &sb_config_regs[dev];
12787 +
12788 + ASSERT(ISALIGNED(off, len));
12789 + ASSERT(ISALIGNED((uintptr)buf, len));
12790 +
12791 + if (len == 4)
12792 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
12793 + else if (len == 2)
12794 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
12795 + else if (len == 1)
12796 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
12797 + else
12798 + return -1;
12799 +
12800 + return 0;
12801 +}
12802 +
12803 +static int
12804 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12805 +{
12806 + uint coreidx, n;
12807 + void *regs;
12808 + sbconfig_t *sb;
12809 + pci_config_regs *cfg;
12810 +
12811 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12812 + return -1;
12813 + cfg = &sb_config_regs[dev];
12814 +
12815 + ASSERT(ISALIGNED(off, len));
12816 + ASSERT(ISALIGNED((uintptr)buf, len));
12817 +
12818 + /* Emulate BAR sizing */
12819 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
12820 + len == 4 && *((uint32 *) buf) == ~0) {
12821 + coreidx = sb_coreidx(sbh);
12822 + if ((regs = sb_setcoreidx(sbh, dev))) {
12823 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12824 + /* Highest numbered address match register */
12825 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
12826 + if (off == OFFSETOF(pci_config_regs, base[0]))
12827 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
12828 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
12829 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
12830 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
12831 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
12832 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
12833 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
12834 + }
12835 + sb_setcoreidx(sbh, coreidx);
12836 + return 0;
12837 + }
12838 +
12839 + if (len == 4)
12840 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
12841 + else if (len == 2)
12842 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
12843 + else if (len == 1)
12844 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
12845 + else
12846 + return -1;
12847 +
12848 + return 0;
12849 +}
12850 +
12851 +int
12852 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12853 +{
12854 + if (bus == 0)
12855 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
12856 + else
12857 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
12858 +}
12859 +
12860 +int
12861 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12862 +{
12863 + if (bus == 0)
12864 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
12865 + else
12866 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
12867 +}
12868 +
12869 +void
12870 +sbpci_ban(uint16 core)
12871 +{
12872 + if (pci_banned < ARRAYSIZE(pci_ban))
12873 + pci_ban[pci_banned++] = core;
12874 +}
12875 +
12876 +static int
12877 +sbpci_init_pci(sb_t *sbh)
12878 +{
12879 + uint chip, chiprev, chippkg, host;
12880 + uint32 boardflags;
12881 + sbpciregs_t *pci;
12882 + sbconfig_t *sb;
12883 + uint32 val;
12884 +
12885 + chip = sb_chip(sbh);
12886 + chiprev = sb_chiprev(sbh);
12887 + chippkg = sb_chippkg(sbh);
12888 +
12889 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
12890 + printf("PCI: no core\n");
12891 + pci_disabled = TRUE;
12892 + return -1;
12893 + }
12894 + sb_core_reset(sbh, 0);
12895 +
12896 + boardflags = (uint32) getintvar(NULL, "boardflags");
12897 +
12898 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
12899 + pci_disabled = TRUE;
12900 +
12901 + /*
12902 + * The 200-pin BCM4712 package does not bond out PCI. Even when
12903 + * PCI is bonded out, some boards may leave the pins
12904 + * floating.
12905 + */
12906 + if (((chip == BCM4712_DEVICE_ID) &&
12907 + ((chippkg == BCM4712SMALL_PKG_ID) ||
12908 + (chippkg == BCM4712MID_PKG_ID))) ||
12909 + (boardflags & BFL_NOPCI))
12910 + pci_disabled = TRUE;
12911 +
12912 + /*
12913 + * If the PCI core should not be touched (disabled, not bonded
12914 + * out, or pins floating), do not even attempt to access core
12915 + * registers. Otherwise, try to determine if it is in host
12916 + * mode.
12917 + */
12918 + if (pci_disabled)
12919 + host = 0;
12920 + else
12921 + host = !BUSPROBE(val, &pci->control);
12922 +
12923 + if (!host) {
12924 + /* Disable PCI interrupts in client mode */
12925 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
12926 + W_REG(&sb->sbintvec, 0);
12927 +
12928 + /* Disable the PCI bridge in client mode */
12929 + sbpci_ban(SB_PCI);
12930 + printf("PCI: Disabled\n");
12931 + } else {
12932 + /* Reset the external PCI bus and enable the clock */
12933 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
12934 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
12935 + OSL_DELAY(150); /* delay > 100 us */
12936 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
12937 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
12938 + OSL_DELAY(1); /* delay 1 us */
12939 +
12940 + /* Enable CardBusMode */
12941 + cardbus = nvram_match("cardbus", "1");
12942 + if (cardbus) {
12943 + printf("PCI: Enabling CardBus\n");
12944 + /* GPIO 1 resets the CardBus device on bcm94710ap */
12945 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
12946 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
12947 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
12948 + }
12949 +
12950 + /* 64 MB I/O access window */
12951 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
12952 + /* 64 MB configuration access window */
12953 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
12954 + /* 1 GB memory access window */
12955 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
12956 +
12957 + /* Enable PCI bridge BAR0 prefetch and burst */
12958 + val = 6;
12959 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
12960 +
12961 + /* Enable PCI interrupts */
12962 + W_REG(&pci->intmask, PCI_INTA);
12963 + }
12964 +
12965 + return 0;
12966 +}
12967 +
12968 +static int
12969 +sbpci_init_cores(sb_t *sbh)
12970 +{
12971 + uint chip, chiprev, chippkg, coreidx, i;
12972 + sbconfig_t *sb;
12973 + pci_config_regs *cfg;
12974 + void *regs;
12975 + char varname[8];
12976 + uint wlidx = 0;
12977 + uint16 vendor, core;
12978 + uint8 class, subclass, progif;
12979 + uint32 val;
12980 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
12981 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
12982 +
12983 + chip = sb_chip(sbh);
12984 + chiprev = sb_chiprev(sbh);
12985 + chippkg = sb_chippkg(sbh);
12986 + coreidx = sb_coreidx(sbh);
12987 +
12988 + /* Scan the SB bus */
12989 + bzero(sb_config_regs, sizeof(sb_config_regs));
12990 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
12991 + cfg->vendor = 0xffff;
12992 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
12993 + continue;
12994 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12995 +
12996 + /* Read ID register and parse vendor and core */
12997 + val = R_REG(&sb->sbidhigh);
12998 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
12999 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
13000 + progif = 0;
13001 +
13002 + /* Check if this core is banned */
13003 + for (i = 0; i < pci_banned; i++)
13004 + if (core == pci_ban[i])
13005 + break;
13006 + if (i < pci_banned)
13007 + continue;
13008 +
13009 + /* Known vendor translations */
13010 + switch (vendor) {
13011 + case SB_VEND_BCM:
13012 + vendor = VENDOR_BROADCOM;
13013 + break;
13014 + }
13015 +
13016 + /* Determine class based on known core codes */
13017 + switch (core) {
13018 + case SB_ILINE20:
13019 + class = PCI_CLASS_NET;
13020 + subclass = PCI_NET_ETHER;
13021 + core = BCM47XX_ILINE_ID;
13022 + break;
13023 + case SB_ILINE100:
13024 + class = PCI_CLASS_NET;
13025 + subclass = PCI_NET_ETHER;
13026 + core = BCM4610_ILINE_ID;
13027 + break;
13028 + case SB_ENET:
13029 + class = PCI_CLASS_NET;
13030 + subclass = PCI_NET_ETHER;
13031 + core = BCM47XX_ENET_ID;
13032 + break;
13033 + case SB_SDRAM:
13034 + case SB_MEMC:
13035 + class = PCI_CLASS_MEMORY;
13036 + subclass = PCI_MEMORY_RAM;
13037 + break;
13038 + case SB_PCI:
13039 + class = PCI_CLASS_BRIDGE;
13040 + subclass = PCI_BRIDGE_PCI;
13041 + break;
13042 + case SB_MIPS:
13043 + case SB_MIPS33:
13044 + class = PCI_CLASS_CPU;
13045 + subclass = PCI_CPU_MIPS;
13046 + break;
13047 + case SB_CODEC:
13048 + class = PCI_CLASS_COMM;
13049 + subclass = PCI_COMM_MODEM;
13050 + core = BCM47XX_V90_ID;
13051 + break;
13052 + case SB_USB:
13053 + class = PCI_CLASS_SERIAL;
13054 + subclass = PCI_SERIAL_USB;
13055 + progif = 0x10; /* OHCI */
13056 + core = BCM47XX_USB_ID;
13057 + break;
13058 + case SB_USB11H:
13059 + class = PCI_CLASS_SERIAL;
13060 + subclass = PCI_SERIAL_USB;
13061 + progif = 0x10; /* OHCI */
13062 + core = BCM47XX_USBH_ID;
13063 + break;
13064 + case SB_USB11D:
13065 + class = PCI_CLASS_SERIAL;
13066 + subclass = PCI_SERIAL_USB;
13067 + core = BCM47XX_USBD_ID;
13068 + break;
13069 + case SB_IPSEC:
13070 + class = PCI_CLASS_CRYPT;
13071 + subclass = PCI_CRYPT_NETWORK;
13072 + core = BCM47XX_IPSEC_ID;
13073 + break;
13074 + case SB_ROBO:
13075 + class = PCI_CLASS_NET;
13076 + subclass = PCI_NET_OTHER;
13077 + core = BCM47XX_ROBO_ID;
13078 + break;
13079 + case SB_EXTIF:
13080 + case SB_CC:
13081 + class = PCI_CLASS_MEMORY;
13082 + subclass = PCI_MEMORY_FLASH;
13083 + break;
13084 + case SB_D11:
13085 + class = PCI_CLASS_NET;
13086 + subclass = PCI_NET_OTHER;
13087 + /* Let an nvram variable override this */
13088 + sprintf(varname, "wl%did", wlidx);
13089 + wlidx++;
13090 + if ((core = getintvar(NULL, varname)) == 0) {
13091 + if (chip == BCM4712_DEVICE_ID) {
13092 + if (chippkg == BCM4712SMALL_PKG_ID)
13093 + core = BCM4306_D11G_ID;
13094 + else
13095 + core = BCM4306_D11DUAL_ID;
13096 + } else {
13097 + /* 4310 */
13098 + core = BCM4310_D11B_ID;
13099 + }
13100 + }
13101 + break;
13102 +
13103 + default:
13104 + class = subclass = progif = 0xff;
13105 + break;
13106 + }
13107 +
13108 + /* Supported translations */
13109 + cfg->vendor = htol16(vendor);
13110 + cfg->device = htol16(core);
13111 + cfg->rev_id = chiprev;
13112 + cfg->prog_if = progif;
13113 + cfg->sub_class = subclass;
13114 + cfg->base_class = class;
13115 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
13116 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
13117 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
13118 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
13119 + cfg->base[4] = 0;
13120 + cfg->base[5] = 0;
13121 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
13122 + cfg->header_type = PCI_HEADER_BRIDGE;
13123 + else
13124 + cfg->header_type = PCI_HEADER_NORMAL;
13125 + /* Save core interrupt flag */
13126 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
13127 + /* Default to MIPS shared interrupt 0 */
13128 + cfg->int_line = 0;
13129 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
13130 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
13131 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
13132 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13133 + val = R_REG(&sb->sbipsflag);
13134 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
13135 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
13136 + break;
13137 + }
13138 + if (cfg->int_line > 4)
13139 + cfg->int_line = 0;
13140 + }
13141 + /* Emulated core */
13142 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
13143 + }
13144 +
13145 + sb_setcoreidx(sbh, coreidx);
13146 + return 0;
13147 +}
13148 +
13149 +int __init
13150 +sbpci_init(sb_t *sbh)
13151 +{
13152 + sbpci_init_pci(sbh);
13153 + sbpci_init_cores(sbh);
13154 + return 0;
13155 +}
13156 +
13157 +void
13158 +sbpci_check(sb_t *sbh)
13159 +{
13160 + uint coreidx;
13161 + sbpciregs_t *pci;
13162 + uint32 sbtopci1;
13163 + uint32 buf[64], *ptr, i;
13164 + ulong pa;
13165 + volatile uint j;
13166 +
13167 + coreidx = sb_coreidx(sbh);
13168 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
13169 +
13170 + /* Clear the test array */
13171 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
13172 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13173 + memset(ptr, 0, sizeof(buf));
13174 +
13175 + /* Point PCI window 1 to memory */
13176 + sbtopci1 = R_REG(&pci->sbtopci1);
13177 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
13178 +
13179 + /* Fill the test array via PCI window 1 */
13180 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
13181 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13182 + for (j = 0; j < 2; j++);
13183 + W_REG(&ptr[i], i);
13184 + }
13185 + REG_UNMAP(ptr);
13186 +
13187 + /* Restore PCI window 1 */
13188 + W_REG(&pci->sbtopci1, sbtopci1);
13189 +
13190 + /* Check the test array */
13191 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
13192 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13193 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13194 + if (ptr[i] != i)
13195 + break;
13196 + }
13197 +
13198 + /* Change the clock if the test fails */
13199 + if (i < ARRAYSIZE(buf)) {
13200 + uint32 req, cur;
13201 +
13202 + cur = sb_clock(sbh);
13203 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
13204 + for (req = 104000000; req < 176000000; req += 4000000) {
13205 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
13206 + /* This will only reset if the clocks are valid and have changed */
13207 + sb_mips_setclock(sbh, req, 0, 0);
13208 + }
13209 + /* Should not reach here */
13210 + ASSERT(0);
13211 + }
13212 +
13213 + sb_setcoreidx(sbh, coreidx);
13214 +}
13215 +
13216 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
13217 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
13218 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-11-08 00:11:55.346775000 +0100
13219 @@ -0,0 +1,272 @@
13220 +/*
13221 + * Generic setup routines for Broadcom MIPS boards
13222 + *
13223 + * Copyright 2005, Broadcom Corporation
13224 + * All Rights Reserved.
13225 + *
13226 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13227 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13228 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13229 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13230 + *
13231 + * $Id$
13232 + */
13233 +
13234 +#include <linux/config.h>
13235 +#include <linux/init.h>
13236 +#include <linux/kernel.h>
13237 +#include <linux/serialP.h>
13238 +#include <linux/ide.h>
13239 +#include <asm/bootinfo.h>
13240 +#include <asm/cpu.h>
13241 +#include <asm/time.h>
13242 +#include <asm/reboot.h>
13243 +
13244 +#ifdef CONFIG_MTD_PARTITIONS
13245 +#include <linux/mtd/mtd.h>
13246 +#include <linux/mtd/partitions.h>
13247 +#endif
13248 +
13249 +#include <typedefs.h>
13250 +#include <osl.h>
13251 +#include <sbutils.h>
13252 +#include <bcmutils.h>
13253 +#include <bcmnvram.h>
13254 +#include <sbmips.h>
13255 +#include <trxhdr.h>
13256 +
13257 +extern void bcm947xx_time_init(void);
13258 +extern void bcm947xx_timer_setup(struct irqaction *irq);
13259 +
13260 +#ifdef CONFIG_REMOTE_DEBUG
13261 +extern void set_debug_traps(void);
13262 +extern void rs_kgdb_hook(struct serial_state *);
13263 +extern void breakpoint(void);
13264 +#endif
13265 +
13266 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13267 +extern struct ide_ops std_ide_ops;
13268 +#endif
13269 +
13270 +/* Global SB handle */
13271 +sb_t *bcm947xx_sbh = NULL;
13272 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
13273 +EXPORT_SYMBOL(bcm947xx_sbh);
13274 +EXPORT_SYMBOL(bcm947xx_sbh_lock);
13275 +
13276 +/* Convenience */
13277 +#define sbh bcm947xx_sbh
13278 +#define sbh_lock bcm947xx_sbh_lock
13279 +
13280 +/* Kernel command line */
13281 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
13282 +
13283 +void
13284 +bcm947xx_machine_restart(char *command)
13285 +{
13286 + printk("Please stand by while rebooting the system...\n");
13287 +
13288 + /* Set the watchdog timer to reset immediately */
13289 + __cli();
13290 + sb_watchdog(sbh, 1);
13291 + while (1);
13292 +}
13293 +
13294 +void
13295 +bcm947xx_machine_halt(void)
13296 +{
13297 + printk("System halted\n");
13298 +
13299 + /* Disable interrupts and watchdog and spin forever */
13300 + __cli();
13301 + sb_watchdog(sbh, 0);
13302 + while (1);
13303 +}
13304 +
13305 +#ifdef CONFIG_SERIAL
13306 +
13307 +static struct serial_struct rs = {
13308 + line: 0,
13309 + flags: ASYNC_BOOT_AUTOCONF,
13310 + io_type: SERIAL_IO_MEM,
13311 +};
13312 +
13313 +static void __init
13314 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
13315 +{
13316 + rs.iomem_base = regs;
13317 + rs.irq = irq + 2;
13318 + rs.baud_base = baud_base / 16;
13319 + rs.iomem_reg_shift = reg_shift;
13320 +
13321 + early_serial_setup(&rs);
13322 +
13323 + rs.line++;
13324 +}
13325 +
13326 +static void __init
13327 +serial_setup(sb_t *sbh)
13328 +{
13329 + sb_serial_init(sbh, serial_add);
13330 +
13331 +#ifdef CONFIG_REMOTE_DEBUG
13332 + /* Use the last port for kernel debugging */
13333 + if (rs.iomem_base)
13334 + rs_kgdb_hook(&rs);
13335 +#endif
13336 +}
13337 +
13338 +#endif /* CONFIG_SERIAL */
13339 +
13340 +void __init
13341 +brcm_setup(void)
13342 +{
13343 + char *value;
13344 +
13345 + /* Get global SB handle */
13346 + sbh = sb_kattach();
13347 +
13348 + /* Initialize clocks and interrupts */
13349 + sb_mips_init(sbh);
13350 +
13351 + if (BCM330X(current_cpu_data.processor_id) &&
13352 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
13353 + /*
13354 + * Now that the sbh is inited set the proper PFC value
13355 + */
13356 + printk("Setting the PFC to its default value\n");
13357 + enable_pfc(PFC_AUTO);
13358 + }
13359 +
13360 +
13361 +#ifdef CONFIG_SERIAL
13362 + /* Initialize UARTs */
13363 + serial_setup(sbh);
13364 +#endif
13365 +
13366 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13367 + ide_ops = &std_ide_ops;
13368 +#endif
13369 +
13370 + /* Override default command line arguments */
13371 + value = nvram_get("kernel_cmdline");
13372 + if (value && strlen(value) && strncmp(value, "empty", 5))
13373 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
13374 +
13375 +
13376 + /* Generic setup */
13377 + _machine_restart = bcm947xx_machine_restart;
13378 + _machine_halt = bcm947xx_machine_halt;
13379 + _machine_power_off = bcm947xx_machine_halt;
13380 +
13381 + board_time_init = bcm947xx_time_init;
13382 + board_timer_setup = bcm947xx_timer_setup;
13383 +}
13384 +
13385 +const char *
13386 +get_system_type(void)
13387 +{
13388 + static char s[32];
13389 +
13390 + if (bcm947xx_sbh) {
13391 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
13392 + sb_chiprev(bcm947xx_sbh));
13393 + return s;
13394 + }
13395 + else
13396 + return "Broadcom BCM947XX";
13397 +}
13398 +
13399 +void __init
13400 +bus_error_init(void)
13401 +{
13402 +}
13403 +
13404 +#ifdef CONFIG_MTD_PARTITIONS
13405 +
13406 +static struct mtd_partition bcm947xx_parts[] = {
13407 + { name: "pmon", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
13408 + { name: "linux", offset: 0, size: 0, },
13409 + { name: "rootfs", offset: 0, size: 0, },
13410 + { name: "nvram", offset: 0, size: 0, },
13411 + { name: "OpenWrt", offset: 0, size: 0, },
13412 + { name: NULL, },
13413 +};
13414 +
13415 +static int __init
13416 +find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
13417 +{
13418 + struct trx_header *trx;
13419 + unsigned char buf[512];
13420 + int off;
13421 + size_t len;
13422 +
13423 + trx = (struct trx_header *) buf;
13424 +
13425 + for (off = (256*1024); off < size; off += mtd->erasesize) {
13426 + memset(buf, 0xe5, sizeof(buf));
13427 +
13428 + /*
13429 + * Read into buffer
13430 + */
13431 + if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
13432 + len != sizeof(buf))
13433 + continue;
13434 +
13435 + /* found a TRX header */
13436 + if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
13437 + part->offset = le32_to_cpu(trx->offsets[2]) ? :
13438 + le32_to_cpu(trx->offsets[1]);
13439 + part->size = le32_to_cpu(trx->len);
13440 +
13441 + part->size -= part->offset;
13442 + part->offset += off;
13443 +
13444 + goto done;
13445 + }
13446 + }
13447 +
13448 + printk(KERN_NOTICE
13449 + "%s: Couldn't find root filesystem\n",
13450 + mtd->name);
13451 + return -1;
13452 +
13453 + done:
13454 + return part->size;
13455 +}
13456 +
13457 +struct mtd_partition * __init
13458 +init_mtd_partitions(struct mtd_info *mtd, size_t size)
13459 +{
13460 +
13461 + /* boot loader */
13462 + bcm947xx_parts[0].offset=0;
13463 + bcm947xx_parts[0].size=256*1024;
13464 +
13465 + /* nvram */
13466 + bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
13467 + bcm947xx_parts[3].size = size - bcm947xx_parts[3].offset;
13468 +
13469 + /* Size linux (kernel and rootfs) */
13470 + bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
13471 + bcm947xx_parts[1].size = bcm947xx_parts[3].offset - bcm947xx_parts[1].offset;
13472 +
13473 + /* Find and size rootfs */
13474 + if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
13475 + /* entirely jffs2 */
13476 + bcm947xx_parts[2].size = bcm947xx_parts[3].offset - bcm947xx_parts[2].offset;
13477 + bcm947xx_parts[4].name = NULL;
13478 + } else {
13479 + /* legacy setup */
13480 + /* calculate leftover flash, and assign it to the jffs2 partition */
13481 + bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + bcm947xx_parts[2].size;
13482 + bcm947xx_parts[4].offset = ROUNDUP(bcm947xx_parts[4].offset, mtd->erasesize);
13483 + bcm947xx_parts[4].size = bcm947xx_parts[3].offset - bcm947xx_parts[4].offset;
13484 + }
13485 +
13486 + return bcm947xx_parts;
13487 +}
13488 +
13489 +EXPORT_SYMBOL(init_mtd_partitions);
13490 +
13491 +#endif
13492 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
13493 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
13494 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2005-11-08 00:54:43.022739000 +0100
13495 @@ -0,0 +1,418 @@
13496 +/*
13497 + * Broadcom SiliconBackplane chipcommon serial flash interface
13498 + *
13499 + * Copyright 2005, Broadcom Corporation
13500 + * All Rights Reserved.
13501 + *
13502 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13503 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13504 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13505 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13506 + *
13507 + * $Id$
13508 + */
13509 +
13510 +#include <osl.h>
13511 +#include <typedefs.h>
13512 +#include <sbconfig.h>
13513 +#include <sbchipc.h>
13514 +#include <mipsinc.h>
13515 +#include <bcmutils.h>
13516 +#include <bcmdevs.h>
13517 +#include <sflash.h>
13518 +
13519 +/* Private global state */
13520 +static struct sflash sflash;
13521 +
13522 +/* Issue a serial flash command */
13523 +static INLINE void
13524 +sflash_cmd(chipcregs_t *cc, uint opcode)
13525 +{
13526 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
13527 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
13528 +}
13529 +
13530 +/* Initialize serial flash access */
13531 +struct sflash *
13532 +sflash_init(chipcregs_t *cc)
13533 +{
13534 + uint32 id, id2;
13535 +
13536 + bzero(&sflash, sizeof(sflash));
13537 +
13538 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
13539 +
13540 + switch (sflash.type) {
13541 + case SFLASH_ST:
13542 + /* Probe for ST chips */
13543 + sflash_cmd(cc, SFLASH_ST_DP);
13544 + sflash_cmd(cc, SFLASH_ST_RES);
13545 + id = R_REG(&cc->flashdata);
13546 + switch (id) {
13547 + case 0x11:
13548 + /* ST M25P20 2 Mbit Serial Flash */
13549 + sflash.blocksize = 64 * 1024;
13550 + sflash.numblocks = 4;
13551 + break;
13552 + case 0x12:
13553 + /* ST M25P40 4 Mbit Serial Flash */
13554 + sflash.blocksize = 64 * 1024;
13555 + sflash.numblocks = 8;
13556 + break;
13557 + case 0x13:
13558 + /* ST M25P80 8 Mbit Serial Flash */
13559 + sflash.blocksize = 64 * 1024;
13560 + sflash.numblocks = 16;
13561 + break;
13562 + case 0x14:
13563 + /* ST M25P16 16 Mbit Serial Flash */
13564 + sflash.blocksize = 64 * 1024;
13565 + sflash.numblocks = 32;
13566 + break;
13567 + case 0x15:
13568 + /* ST M25P32 32 Mbit Serial Flash */
13569 + sflash.blocksize = 64 * 1024;
13570 + sflash.numblocks = 64;
13571 + break;
13572 + case 0xbf:
13573 + W_REG(&cc->flashaddress, 1);
13574 + sflash_cmd(cc, SFLASH_ST_RES);
13575 + id2 = R_REG(&cc->flashdata);
13576 + if (id2 == 0x44) {
13577 + /* SST M25VF80 4 Mbit Serial Flash */
13578 + sflash.blocksize = 64 * 1024;
13579 + sflash.numblocks = 8;
13580 + }
13581 + break;
13582 + }
13583 + break;
13584 +
13585 + case SFLASH_AT:
13586 + /* Probe for Atmel chips */
13587 + sflash_cmd(cc, SFLASH_AT_STATUS);
13588 + id = R_REG(&cc->flashdata) & 0x3c;
13589 + switch (id) {
13590 + case 0xc:
13591 + /* Atmel AT45DB011 1Mbit Serial Flash */
13592 + sflash.blocksize = 256;
13593 + sflash.numblocks = 512;
13594 + break;
13595 + case 0x14:
13596 + /* Atmel AT45DB021 2Mbit Serial Flash */
13597 + sflash.blocksize = 256;
13598 + sflash.numblocks = 1024;
13599 + break;
13600 + case 0x1c:
13601 + /* Atmel AT45DB041 4Mbit Serial Flash */
13602 + sflash.blocksize = 256;
13603 + sflash.numblocks = 2048;
13604 + break;
13605 + case 0x24:
13606 + /* Atmel AT45DB081 8Mbit Serial Flash */
13607 + sflash.blocksize = 256;
13608 + sflash.numblocks = 4096;
13609 + break;
13610 + case 0x2c:
13611 + /* Atmel AT45DB161 16Mbit Serial Flash */
13612 + sflash.blocksize = 512;
13613 + sflash.numblocks = 4096;
13614 + break;
13615 + case 0x34:
13616 + /* Atmel AT45DB321 32Mbit Serial Flash */
13617 + sflash.blocksize = 512;
13618 + sflash.numblocks = 8192;
13619 + break;
13620 + case 0x3c:
13621 + /* Atmel AT45DB642 64Mbit Serial Flash */
13622 + sflash.blocksize = 1024;
13623 + sflash.numblocks = 8192;
13624 + break;
13625 + }
13626 + break;
13627 + }
13628 +
13629 + sflash.size = sflash.blocksize * sflash.numblocks;
13630 + return sflash.size ? &sflash : NULL;
13631 +}
13632 +
13633 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
13634 +int
13635 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
13636 +{
13637 + int cnt;
13638 + uint32 *from, *to;
13639 +
13640 + if (!len)
13641 + return 0;
13642 +
13643 + if ((offset + len) > sflash.size)
13644 + return -22;
13645 +
13646 + if ((len >= 4) && (offset & 3))
13647 + cnt = 4 - (offset & 3);
13648 + else if ((len >= 4) && ((uint32)buf & 3))
13649 + cnt = 4 - ((uint32)buf & 3);
13650 + else
13651 + cnt = len;
13652 +
13653 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
13654 + to = (uint32 *)buf;
13655 +
13656 + if (cnt < 4) {
13657 + bcopy(from, to, cnt);
13658 + return cnt;
13659 + }
13660 +
13661 + while (cnt >= 4) {
13662 + *to++ = *from++;
13663 + cnt -= 4;
13664 + }
13665 +
13666 + return (len - cnt);
13667 +}
13668 +
13669 +/* Poll for command completion. Returns zero when complete. */
13670 +int
13671 +sflash_poll(chipcregs_t *cc, uint offset)
13672 +{
13673 + if (offset >= sflash.size)
13674 + return -22;
13675 +
13676 + switch (sflash.type) {
13677 + case SFLASH_ST:
13678 + /* Check for ST Write In Progress bit */
13679 + sflash_cmd(cc, SFLASH_ST_RDSR);
13680 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
13681 + case SFLASH_AT:
13682 + /* Check for Atmel Ready bit */
13683 + sflash_cmd(cc, SFLASH_AT_STATUS);
13684 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
13685 + }
13686 +
13687 + return 0;
13688 +}
13689 +
13690 +/* Write len bytes starting at offset into buf. Returns number of bytes
13691 + * written. Caller should poll for completion.
13692 + */
13693 +int
13694 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13695 +{
13696 + struct sflash *sfl;
13697 + int ret = 0;
13698 + bool is4712b0;
13699 + uint32 page, byte, mask;
13700 +
13701 + if (!len)
13702 + return 0;
13703 +
13704 + if ((offset + len) > sflash.size)
13705 + return -22;
13706 +
13707 + sfl = &sflash;
13708 + switch (sfl->type) {
13709 + case SFLASH_ST:
13710 + mask = R_REG(&cc->chipid);
13711 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
13712 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
13713 + /* Enable writes */
13714 + sflash_cmd(cc, SFLASH_ST_WREN);
13715 + if (is4712b0) {
13716 + mask = 1 << 14;
13717 + W_REG(&cc->flashaddress, offset);
13718 + W_REG(&cc->flashdata, *buf++);
13719 + /* Set chip select */
13720 + OR_REG(&cc->gpioout, mask);
13721 + /* Issue a page program with the first byte */
13722 + sflash_cmd(cc, SFLASH_ST_PP);
13723 + ret = 1;
13724 + offset++;
13725 + len--;
13726 + while (len > 0) {
13727 + if ((offset & 255) == 0) {
13728 + /* Page boundary, drop cs and return */
13729 + AND_REG(&cc->gpioout, ~mask);
13730 + if (!sflash_poll(cc, offset)) {
13731 + /* Flash rejected command */
13732 + return -11;
13733 + }
13734 + return ret;
13735 + } else {
13736 + /* Write single byte */
13737 + sflash_cmd(cc, *buf++);
13738 + }
13739 + ret++;
13740 + offset++;
13741 + len--;
13742 + }
13743 + /* All done, drop cs if needed */
13744 + if ((offset & 255) != 1) {
13745 + /* Drop cs */
13746 + AND_REG(&cc->gpioout, ~mask);
13747 + if (!sflash_poll(cc, offset)) {
13748 + /* Flash rejected command */
13749 + return -12;
13750 + }
13751 + }
13752 + } else {
13753 + ret = 1;
13754 + W_REG(&cc->flashaddress, offset);
13755 + W_REG(&cc->flashdata, *buf);
13756 + /* Page program */
13757 + sflash_cmd(cc, SFLASH_ST_PP);
13758 + }
13759 + break;
13760 + case SFLASH_AT:
13761 + mask = sfl->blocksize - 1;
13762 + page = (offset & ~mask) << 1;
13763 + byte = offset & mask;
13764 + /* Read main memory page into buffer 1 */
13765 + if (byte || len < sfl->blocksize) {
13766 + W_REG(&cc->flashaddress, page);
13767 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
13768 + /* 250 us for AT45DB321B */
13769 + SPINWAIT(sflash_poll(cc, offset), 1000);
13770 + ASSERT(!sflash_poll(cc, offset));
13771 + }
13772 + /* Write into buffer 1 */
13773 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
13774 + W_REG(&cc->flashaddress, byte++);
13775 + W_REG(&cc->flashdata, *buf++);
13776 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
13777 + }
13778 + /* Write buffer 1 into main memory page */
13779 + W_REG(&cc->flashaddress, page);
13780 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
13781 + break;
13782 + }
13783 +
13784 + return ret;
13785 +}
13786 +
13787 +/* Erase a region. Returns number of bytes scheduled for erasure.
13788 + * Caller should poll for completion.
13789 + */
13790 +int
13791 +sflash_erase(chipcregs_t *cc, uint offset)
13792 +{
13793 + struct sflash *sfl;
13794 +
13795 + if (offset >= sflash.size)
13796 + return -22;
13797 +
13798 + sfl = &sflash;
13799 + switch (sfl->type) {
13800 + case SFLASH_ST:
13801 + sflash_cmd(cc, SFLASH_ST_WREN);
13802 + W_REG(&cc->flashaddress, offset);
13803 + sflash_cmd(cc, SFLASH_ST_SE);
13804 + return sfl->blocksize;
13805 + case SFLASH_AT:
13806 + W_REG(&cc->flashaddress, offset << 1);
13807 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
13808 + return sfl->blocksize;
13809 + }
13810 +
13811 + return 0;
13812 +}
13813 +
13814 +/*
13815 + * writes the appropriate range of flash, a NULL buf simply erases
13816 + * the region of flash
13817 + */
13818 +int
13819 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13820 +{
13821 + struct sflash *sfl;
13822 + uchar *block = NULL, *cur_ptr, *blk_ptr;
13823 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
13824 + uint blk_offset, blk_len, copied;
13825 + int bytes, ret = 0;
13826 +
13827 + /* Check address range */
13828 + if (len <= 0)
13829 + return 0;
13830 +
13831 + sfl = &sflash;
13832 + if ((offset + len) > sfl->size)
13833 + return -1;
13834 +
13835 + blocksize = sfl->blocksize;
13836 + mask = blocksize - 1;
13837 +
13838 + /* Allocate a block of mem */
13839 + if (!(block = MALLOC(NULL, blocksize)))
13840 + return -1;
13841 +
13842 + while (len) {
13843 + /* Align offset */
13844 + cur_offset = offset & ~mask;
13845 + cur_length = blocksize;
13846 + cur_ptr = block;
13847 +
13848 + remainder = blocksize - (offset & mask);
13849 + if (len < remainder)
13850 + cur_retlen = len;
13851 + else
13852 + cur_retlen = remainder;
13853 +
13854 + /* buf == NULL means erase only */
13855 + if (buf) {
13856 + /* Copy existing data into holding block if necessary */
13857 + if ((offset & mask) || (len < blocksize)) {
13858 + blk_offset = cur_offset;
13859 + blk_len = cur_length;
13860 + blk_ptr = cur_ptr;
13861 +
13862 + /* Copy entire block */
13863 + while(blk_len) {
13864 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
13865 + blk_offset += copied;
13866 + blk_len -= copied;
13867 + blk_ptr += copied;
13868 + }
13869 + }
13870 +
13871 + /* Copy input data into holding block */
13872 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
13873 + }
13874 +
13875 + /* Erase block */
13876 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
13877 + goto done;
13878 + while (sflash_poll(cc, (uint) cur_offset));
13879 +
13880 + /* buf == NULL means erase only */
13881 + if (!buf) {
13882 + offset += cur_retlen;
13883 + len -= cur_retlen;
13884 + continue;
13885 + }
13886 +
13887 + /* Write holding block */
13888 + while (cur_length > 0) {
13889 + if ((bytes = sflash_write(cc,
13890 + (uint) cur_offset,
13891 + (uint) cur_length,
13892 + (uchar *) cur_ptr)) < 0) {
13893 + ret = bytes;
13894 + goto done;
13895 + }
13896 + while (sflash_poll(cc, (uint) cur_offset));
13897 + cur_offset += bytes;
13898 + cur_length -= bytes;
13899 + cur_ptr += bytes;
13900 + }
13901 +
13902 + offset += cur_retlen;
13903 + len -= cur_retlen;
13904 + buf += cur_retlen;
13905 + }
13906 +
13907 + ret = len;
13908 +done:
13909 + if (block)
13910 + MFREE(NULL, block, blocksize);
13911 + return ret;
13912 +}
13913 +
13914 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
13915 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
13916 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-11-07 23:47:27.528101500 +0100
13917 @@ -0,0 +1,118 @@
13918 +/*
13919 + * Copyright 2004, Broadcom Corporation
13920 + * All Rights Reserved.
13921 + *
13922 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13923 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13924 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13925 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13926 + *
13927 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
13928 + */
13929 +#include <linux/config.h>
13930 +#include <linux/init.h>
13931 +#include <linux/kernel.h>
13932 +#include <linux/sched.h>
13933 +#include <linux/serial_reg.h>
13934 +#include <linux/interrupt.h>
13935 +#include <asm/addrspace.h>
13936 +#include <asm/io.h>
13937 +#include <asm/time.h>
13938 +
13939 +#include <typedefs.h>
13940 +#include <osl.h>
13941 +#include <sbutils.h>
13942 +#include <bcmnvram.h>
13943 +#include <sbconfig.h>
13944 +#include <sbextif.h>
13945 +#include <sbmips.h>
13946 +
13947 +/* Global SB handle */
13948 +extern void *bcm947xx_sbh;
13949 +extern spinlock_t bcm947xx_sbh_lock;
13950 +
13951 +/* Convenience */
13952 +#define sbh bcm947xx_sbh
13953 +#define sbh_lock bcm947xx_sbh_lock
13954 +
13955 +extern int panic_timeout;
13956 +static int watchdog = 0;
13957 +static u8 *mcr = NULL;
13958 +
13959 +void __init
13960 +bcm947xx_time_init(void)
13961 +{
13962 + unsigned int hz;
13963 + extifregs_t *eir;
13964 +
13965 + /*
13966 + * Use deterministic values for initial counter interrupt
13967 + * so that calibrate delay avoids encountering a counter wrap.
13968 + */
13969 + write_c0_count(0);
13970 + write_c0_compare(0xffff);
13971 +
13972 + if (!(hz = sb_mips_clock(sbh)))
13973 + hz = 100000000;
13974 +
13975 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
13976 + (hz + 500000) / 1000000);
13977 +
13978 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
13979 + mips_hpt_frequency = hz / 2;
13980 +
13981 + /* Set watchdog interval in ms */
13982 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
13983 +
13984 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
13985 + if (watchdog > 0) {
13986 + if (watchdog < 3000)
13987 + watchdog = 3000;
13988 + }
13989 +
13990 +
13991 + /* Set panic timeout in seconds */
13992 + panic_timeout = watchdog / 1000;
13993 +
13994 + /* Setup blink */
13995 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
13996 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
13997 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
13998 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
13999 + }
14000 +}
14001 +
14002 +static void
14003 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
14004 +{
14005 + /* Generic MIPS timer code */
14006 + timer_interrupt(irq, dev_id, regs);
14007 +
14008 + /* Set the watchdog timer to reset after the specified number of ms */
14009 + if (watchdog > 0)
14010 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
14011 +
14012 +#ifdef CONFIG_HWSIM
14013 + (*((int *)0xa0000f1c))++;
14014 +#else
14015 + /* Blink one of the LEDs in the external UART */
14016 + if (mcr && !(jiffies % (HZ/2)))
14017 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
14018 +#endif
14019 +}
14020 +
14021 +static struct irqaction bcm947xx_timer_irqaction = {
14022 + bcm947xx_timer_interrupt,
14023 + SA_INTERRUPT,
14024 + 0,
14025 + "timer",
14026 + NULL,
14027 + NULL
14028 +};
14029 +
14030 +void __init
14031 +bcm947xx_timer_setup(struct irqaction *irq)
14032 +{
14033 + /* Enable the timer interrupt */
14034 + setup_irq(7, &bcm947xx_timer_irqaction);
14035 +}
14036 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
14037 --- linux.old/arch/mips/config-shared.in 2005-11-07 23:12:50.850903750 +0100
14038 +++ linux.dev/arch/mips/config-shared.in 2005-11-07 21:57:07.889588500 +0100
14039 @@ -208,6 +208,14 @@
14040 fi
14041 define_bool CONFIG_MIPS_RTC y
14042 fi
14043 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
14044 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
14045 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14046 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
14047 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
14048 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
14049 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
14050 +fi
14051 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
14052 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
14053 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
14054 @@ -229,6 +237,11 @@
14055 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
14056
14057 #
14058 +# Provide an option for a default kernel command line
14059 +#
14060 +string 'Default kernel command string' CONFIG_CMDLINE ""
14061 +
14062 +#
14063 # Select some configuration options automatically based on user selections.
14064 #
14065 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
14066 @@ -554,6 +567,13 @@
14067 define_bool CONFIG_SWAP_IO_SPACE_L y
14068 define_bool CONFIG_BOOT_ELF32 y
14069 fi
14070 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14071 + define_bool CONFIG_PCI y
14072 + define_bool CONFIG_NONCOHERENT_IO y
14073 + define_bool CONFIG_NEW_TIME_C y
14074 + define_bool CONFIG_NEW_IRQ y
14075 + define_bool CONFIG_HND y
14076 +fi
14077 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
14078 define_bool CONFIG_ARC32 y
14079 define_bool CONFIG_ARC_MEMORY y
14080 @@ -1042,7 +1062,11 @@
14081
14082 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
14083 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
14084 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
14085 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14086 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
14087 +else
14088 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
14089 +fi
14090 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
14091 if [ "$CONFIG_KGDB" = "y" ]; then
14092 define_bool CONFIG_DEBUG_INFO y
14093 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
14094 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-11-07 23:12:50.890906250 +0100
14095 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-11-07 21:57:07.893588750 +0100
14096 @@ -163,7 +163,7 @@
14097
14098 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
14099 {
14100 - switch (c->processor_id & 0xff00) {
14101 + switch (c->processor_id & PRID_IMP_MASK) {
14102 case PRID_IMP_R2000:
14103 c->cputype = CPU_R2000;
14104 c->isa_level = MIPS_CPU_ISA_I;
14105 @@ -173,7 +173,7 @@
14106 c->tlbsize = 64;
14107 break;
14108 case PRID_IMP_R3000:
14109 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
14110 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
14111 if (cpu_has_confreg())
14112 c->cputype = CPU_R3081E;
14113 else
14114 @@ -188,12 +188,12 @@
14115 break;
14116 case PRID_IMP_R4000:
14117 if (read_c0_config() & CONF_SC) {
14118 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14119 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14120 c->cputype = CPU_R4400PC;
14121 else
14122 c->cputype = CPU_R4000PC;
14123 } else {
14124 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14125 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14126 c->cputype = CPU_R4400SC;
14127 else
14128 c->cputype = CPU_R4000SC;
14129 @@ -439,7 +439,7 @@
14130 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
14131 {
14132 decode_config1(c);
14133 - switch (c->processor_id & 0xff00) {
14134 + switch (c->processor_id & PRID_IMP_MASK) {
14135 case PRID_IMP_4KC:
14136 c->cputype = CPU_4KC;
14137 c->isa_level = MIPS_CPU_ISA_M32;
14138 @@ -480,10 +480,10 @@
14139 {
14140 decode_config1(c);
14141 c->options |= MIPS_CPU_PREFETCH;
14142 - switch (c->processor_id & 0xff00) {
14143 + switch (c->processor_id & PRID_IMP_MASK) {
14144 case PRID_IMP_AU1_REV1:
14145 case PRID_IMP_AU1_REV2:
14146 - switch ((c->processor_id >> 24) & 0xff) {
14147 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
14148 case 0:
14149 c->cputype = CPU_AU1000;
14150 break;
14151 @@ -511,10 +511,34 @@
14152 }
14153 }
14154
14155 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
14156 +{
14157 + decode_config1(c);
14158 + c->options |= MIPS_CPU_PREFETCH;
14159 + switch (c->processor_id & PRID_IMP_MASK) {
14160 + case PRID_IMP_BCM4710:
14161 + c->cputype = CPU_BCM4710;
14162 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14163 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14164 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14165 + break;
14166 + case PRID_IMP_4KC:
14167 + case PRID_IMP_BCM3302:
14168 + c->cputype = CPU_BCM3302;
14169 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14170 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14171 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14172 + break;
14173 + default:
14174 + c->cputype = CPU_UNKNOWN;
14175 + break;
14176 + }
14177 +}
14178 +
14179 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
14180 {
14181 decode_config1(c);
14182 - switch (c->processor_id & 0xff00) {
14183 + switch (c->processor_id & PRID_IMP_MASK) {
14184 case PRID_IMP_SB1:
14185 c->cputype = CPU_SB1;
14186 c->isa_level = MIPS_CPU_ISA_M64;
14187 @@ -536,7 +560,7 @@
14188 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
14189 {
14190 decode_config1(c);
14191 - switch (c->processor_id & 0xff00) {
14192 + switch (c->processor_id & PRID_IMP_MASK) {
14193 case PRID_IMP_SR71000:
14194 c->cputype = CPU_SR71000;
14195 c->isa_level = MIPS_CPU_ISA_M64;
14196 @@ -561,7 +585,7 @@
14197 c->cputype = CPU_UNKNOWN;
14198
14199 c->processor_id = read_c0_prid();
14200 - switch (c->processor_id & 0xff0000) {
14201 + switch (c->processor_id & PRID_COMP_MASK) {
14202
14203 case PRID_COMP_LEGACY:
14204 cpu_probe_legacy(c);
14205 @@ -572,6 +596,9 @@
14206 case PRID_COMP_ALCHEMY:
14207 cpu_probe_alchemy(c);
14208 break;
14209 + case PRID_COMP_BROADCOM:
14210 + cpu_probe_broadcom(c);
14211 + break;
14212 case PRID_COMP_SIBYTE:
14213 cpu_probe_sibyte(c);
14214 break;
14215 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
14216 --- linux.old/arch/mips/kernel/head.S 2005-11-07 23:12:50.898906750 +0100
14217 +++ linux.dev/arch/mips/kernel/head.S 2005-11-07 21:57:07.893588750 +0100
14218 @@ -28,12 +28,20 @@
14219 #include <asm/mipsregs.h>
14220 #include <asm/stackframe.h>
14221
14222 +#ifdef CONFIG_BCM4710
14223 +#undef eret
14224 +#define eret nop; nop; eret
14225 +#endif
14226 +
14227 .text
14228 + j kernel_entry
14229 + nop
14230 +
14231 /*
14232 * Reserved space for exception handlers.
14233 * Necessary for machines which link their kernels at KSEG0.
14234 */
14235 - .fill 0x400
14236 + .fill 0x3f4
14237
14238 /* The following two symbols are used for kernel profiling. */
14239 EXPORT(stext)
14240 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
14241 --- linux.old/arch/mips/kernel/proc.c 2005-11-07 23:12:50.906907250 +0100
14242 +++ linux.dev/arch/mips/kernel/proc.c 2005-11-07 21:57:07.893588750 +0100
14243 @@ -78,9 +78,10 @@
14244 [CPU_AU1550] "Au1550",
14245 [CPU_24K] "MIPS 24K",
14246 [CPU_AU1200] "Au1200",
14247 + [CPU_BCM4710] "BCM4710",
14248 + [CPU_BCM3302] "BCM3302",
14249 };
14250
14251 -
14252 static int show_cpuinfo(struct seq_file *m, void *v)
14253 {
14254 unsigned int version = current_cpu_data.processor_id;
14255 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
14256 --- linux.old/arch/mips/kernel/setup.c 2005-11-07 23:12:50.906907250 +0100
14257 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-07 21:57:07.893588750 +0100
14258 @@ -493,6 +493,7 @@
14259 void swarm_setup(void);
14260 void hp_setup(void);
14261 void au1x00_setup(void);
14262 + void brcm_setup(void);
14263 void frame_info_init(void);
14264
14265 frame_info_init();
14266 @@ -691,6 +692,11 @@
14267 pmc_yosemite_setup();
14268 break;
14269 #endif
14270 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
14271 + case MACH_GROUP_BRCM:
14272 + brcm_setup();
14273 + break;
14274 +#endif
14275 default:
14276 panic("Unsupported architecture");
14277 }
14278 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
14279 --- linux.old/arch/mips/kernel/traps.c 2005-11-07 23:12:50.922908250 +0100
14280 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-07 21:57:07.893588750 +0100
14281 @@ -920,6 +920,7 @@
14282 void __init trap_init(void)
14283 {
14284 extern char except_vec1_generic;
14285 + extern char except_vec2_generic;
14286 extern char except_vec3_generic, except_vec3_r4000;
14287 extern char except_vec_ejtag_debug;
14288 extern char except_vec4;
14289 @@ -927,6 +928,7 @@
14290
14291 /* Copy the generic exception handler code to it's final destination. */
14292 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
14293 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
14294
14295 /*
14296 * Setup default vectors
14297 @@ -985,6 +987,12 @@
14298 set_except_vector(13, handle_tr);
14299 set_except_vector(22, handle_mdmx);
14300
14301 + if (current_cpu_data.cputype == CPU_SB1) {
14302 + /* Enable timer interrupt and scd mapped interrupt */
14303 + clear_c0_status(0xf000);
14304 + set_c0_status(0xc00);
14305 + }
14306 +
14307 if (cpu_has_fpu && !cpu_has_nofpuex)
14308 set_except_vector(15, handle_fpe);
14309
14310 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
14311 --- linux.old/arch/mips/mm/c-r4k.c 2005-11-07 23:12:50.954910250 +0100
14312 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-11-07 21:57:08.157605250 +0100
14313 @@ -1166,3 +1166,47 @@
14314 build_clear_page();
14315 build_copy_page();
14316 }
14317 +
14318 +#ifdef CONFIG_BCM4704
14319 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
14320 +{
14321 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
14322 + int i;
14323 + for (i = 0; i < nbytes; i += ic_lsize)
14324 + fill_icache_line((addr + i));
14325 +}
14326 +
14327 +/*
14328 + * This must be run from the cache on 4704A0
14329 + * so there are no mips core BIU ops in progress
14330 + * when the PFC is enabled.
14331 + */
14332 +#define PFC_CR0 0xff400000 /* control reg 0 */
14333 +#define PFC_CR1 0xff400004 /* control reg 1 */
14334 +static void __init enable_pfc(u32 mode)
14335 +{
14336 + /* write range */
14337 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
14338 +
14339 + /* enable */
14340 + *(volatile u32 *)PFC_CR0 = mode;
14341 +}
14342 +#endif
14343 +
14344 +
14345 +void check_enable_mips_pfc(int val)
14346 +{
14347 +
14348 +#ifdef CONFIG_BCM4704
14349 + struct cpuinfo_mips *c = &current_cpu_data;
14350 +
14351 + /* enable prefetch cache */
14352 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
14353 + && (read_c0_diag() & (1 << 29))) {
14354 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
14355 + enable_pfc(val);
14356 + }
14357 +#endif
14358 +}
14359 +
14360 +
14361 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
14362 --- linux.old/arch/mips/pci/Makefile 2005-11-07 23:12:50.978911750 +0100
14363 +++ linux.dev/arch/mips/pci/Makefile 2005-11-07 21:57:07.897589000 +0100
14364 @@ -13,7 +13,9 @@
14365 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
14366 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
14367 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
14368 +ifndef CONFIG_BCM947XX
14369 obj-y += pci.o
14370 +endif
14371 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
14372
14373 include $(TOPDIR)/Rules.make
14374 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
14375 --- linux.old/drivers/char/serial.c 2005-11-07 23:12:51.038915500 +0100
14376 +++ linux.dev/drivers/char/serial.c 2005-11-07 21:57:07.901589250 +0100
14377 @@ -444,6 +444,10 @@
14378 return inb(info->port+1);
14379 #endif
14380 case SERIAL_IO_MEM:
14381 +#ifdef CONFIG_BCM4310
14382 + readb((unsigned long) info->iomem_base +
14383 + (UART_SCR<<info->iomem_reg_shift));
14384 +#endif
14385 return readb((unsigned long) info->iomem_base +
14386 (offset<<info->iomem_reg_shift));
14387 default:
14388 @@ -464,6 +468,9 @@
14389 case SERIAL_IO_MEM:
14390 writeb(value, (unsigned long) info->iomem_base +
14391 (offset<<info->iomem_reg_shift));
14392 +#ifdef CONFIG_BCM4704
14393 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
14394 +#endif
14395 break;
14396 default:
14397 outb(value, info->port+offset);
14398 @@ -1728,7 +1735,7 @@
14399 /* Special case since 134 is really 134.5 */
14400 quot = (2*baud_base / 269);
14401 else if (baud)
14402 - quot = baud_base / baud;
14403 + quot = (baud_base + (baud / 2)) / baud;
14404 }
14405 /* If the quotient is zero refuse the change */
14406 if (!quot && old_termios) {
14407 @@ -1745,12 +1752,12 @@
14408 /* Special case since 134 is really 134.5 */
14409 quot = (2*baud_base / 269);
14410 else if (baud)
14411 - quot = baud_base / baud;
14412 + quot = (baud_base + (baud / 2)) / baud;
14413 }
14414 }
14415 /* As a last resort, if the quotient is zero, default to 9600 bps */
14416 if (!quot)
14417 - quot = baud_base / 9600;
14418 + quot = (baud_base + 4800) / 9600;
14419 /*
14420 * Work around a bug in the Oxford Semiconductor 952 rev B
14421 * chip which causes it to seriously miscalculate baud rates
14422 @@ -5984,6 +5991,13 @@
14423 * Divisor, bytesize and parity
14424 */
14425 state = rs_table + co->index;
14426 + /*
14427 + * Safe guard: state structure must have been initialized
14428 + */
14429 + if (state->iomem_base == NULL) {
14430 + printk("!unable to setup serial console!\n");
14431 + return -1;
14432 + }
14433 if (doflow)
14434 state->flags |= ASYNC_CONS_FLOW;
14435 info = &async_sercons;
14436 @@ -5997,7 +6011,7 @@
14437 info->io_type = state->io_type;
14438 info->iomem_base = state->iomem_base;
14439 info->iomem_reg_shift = state->iomem_reg_shift;
14440 - quot = state->baud_base / baud;
14441 + quot = (state->baud_base + (baud / 2)) / baud;
14442 cval = cflag & (CSIZE | CSTOPB);
14443 #if defined(__powerpc__) || defined(__alpha__)
14444 cval >>= 8;
14445 diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
14446 --- linux.old/drivers/mtd/maps/Config.in 2005-11-07 23:12:51.086918500 +0100
14447 +++ linux.dev/drivers/mtd/maps/Config.in 2005-11-07 21:57:07.901589250 +0100
14448 @@ -48,6 +48,7 @@
14449 fi
14450
14451 if [ "$CONFIG_MIPS" = "y" ]; then
14452 + dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
14453 dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
14454 dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
14455 dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
14456 diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
14457 --- linux.old/drivers/mtd/maps/Makefile 2005-11-07 23:12:51.086918500 +0100
14458 +++ linux.dev/drivers/mtd/maps/Makefile 2005-11-07 21:57:07.905589500 +0100
14459 @@ -3,6 +3,8 @@
14460 #
14461 # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
14462
14463 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14464 +
14465 BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
14466
14467 ifeq ($(BELOW25),y)
14468 @@ -10,6 +12,7 @@
14469 endif
14470
14471 # Chip mappings
14472 +obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
14473 obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
14474 obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
14475 obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
14476 diff -urN linux.old/drivers/mtd/maps/bcm947xx-flash.c linux.dev/drivers/mtd/maps/bcm947xx-flash.c
14477 --- linux.old/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
14478 +++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-11-07 23:33:20.715765500 +0100
14479 @@ -0,0 +1,237 @@
14480 +/*
14481 + * Flash mapping for BCM947XX boards
14482 + *
14483 + * Copyright 2004, Broadcom Corporation
14484 + * All Rights Reserved.
14485 + *
14486 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14487 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14488 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14489 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14490 + *
14491 + * $Id: bcm947xx-flash.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
14492 + */
14493 +
14494 +#include <linux/module.h>
14495 +#include <linux/types.h>
14496 +#include <linux/kernel.h>
14497 +#include <asm/io.h>
14498 +#include <linux/mtd/mtd.h>
14499 +#include <linux/mtd/map.h>
14500 +#include <linux/mtd/partitions.h>
14501 +#include <linux/config.h>
14502 +
14503 +#include <osl.h>
14504 +#include <typedefs.h>
14505 +#include <bcmnvram.h>
14506 +#include <bcmutils.h>
14507 +#include <sbconfig.h>
14508 +#include <sbchipc.h>
14509 +#include <sbutils.h>
14510 +#include <trxhdr.h>
14511 +
14512 +/* Global SB handle */
14513 +extern void *bcm947xx_sbh;
14514 +extern spinlock_t bcm947xx_sbh_lock;
14515 +
14516 +/* Convenience */
14517 +#define sbh bcm947xx_sbh
14518 +#define sbh_lock bcm947xx_sbh_lock
14519 +
14520 +#ifdef CONFIG_MTD_PARTITIONS
14521 +extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
14522 +#endif
14523 +
14524 +#define WINDOW_ADDR 0x1fc00000
14525 +#define WINDOW_SIZE 0x400000
14526 +#define BUSWIDTH 2
14527 +
14528 +/* e.g., flash=2M or flash=4M */
14529 +static int flash = 0;
14530 +MODULE_PARM(flash, "i");
14531 +static int __init
14532 +bcm947xx_setup(char *str)
14533 +{
14534 + flash = memparse(str, &str);
14535 + return 1;
14536 +}
14537 +__setup("flash=", bcm947xx_setup);
14538 +
14539 +static struct mtd_info *bcm947xx_mtd;
14540 +
14541 +__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
14542 +{
14543 + if (map->map_priv_2 == 1)
14544 + return __raw_readb(map->map_priv_1 + ofs);
14545 +
14546 + u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
14547 + if (ofs & 1)
14548 + return ((val >> 8) & 0xff);
14549 + else
14550 + return (val & 0xff);
14551 +}
14552 +
14553 +__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
14554 +{
14555 + return __raw_readw(map->map_priv_1 + ofs);
14556 +}
14557 +
14558 +__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
14559 +{
14560 + return __raw_readl(map->map_priv_1 + ofs);
14561 +}
14562 +
14563 +void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
14564 +{
14565 + if (len==1) {
14566 + memcpy_fromio(to, map->map_priv_1 + from, len);
14567 + } else {
14568 + int i;
14569 + u16 *dest = (u16 *) to;
14570 + u16 *src = (u16 *) (map->map_priv_1 + from);
14571 + for (i = 0; i < (len / 2); i++) {
14572 + dest[i] = src[i];
14573 + }
14574 + if (len & 1)
14575 + *((u8 *)dest+len-1) = src[i] & 0xff;
14576 + }
14577 +}
14578 +
14579 +void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
14580 +{
14581 + __raw_writeb(d, map->map_priv_1 + adr);
14582 + mb();
14583 +}
14584 +
14585 +void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
14586 +{
14587 + __raw_writew(d, map->map_priv_1 + adr);
14588 + mb();
14589 +}
14590 +
14591 +void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
14592 +{
14593 + __raw_writel(d, map->map_priv_1 + adr);
14594 + mb();
14595 +}
14596 +
14597 +void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
14598 +{
14599 + memcpy_toio(map->map_priv_1 + to, from, len);
14600 +}
14601 +
14602 +struct map_info bcm947xx_map = {
14603 + name: "Physically mapped flash",
14604 + size: WINDOW_SIZE,
14605 + buswidth: BUSWIDTH,
14606 + read8: bcm947xx_map_read8,
14607 + read16: bcm947xx_map_read16,
14608 + read32: bcm947xx_map_read32,
14609 + copy_from: bcm947xx_map_copy_from,
14610 + write8: bcm947xx_map_write8,
14611 + write16: bcm947xx_map_write16,
14612 + write32: bcm947xx_map_write32,
14613 + copy_to: bcm947xx_map_copy_to
14614 +};
14615 +
14616 +#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
14617 +#define init_bcm947xx_map init_module
14618 +#define cleanup_bcm947xx_map cleanup_module
14619 +#endif
14620 +
14621 +mod_init_t init_bcm947xx_map(void)
14622 +{
14623 + ulong flags;
14624 + uint coreidx;
14625 + chipcregs_t *cc;
14626 + uint32 fltype;
14627 + uint window_addr = 0, window_size = 0;
14628 + size_t size;
14629 + int ret = 0;
14630 +#ifdef CONFIG_MTD_PARTITIONS
14631 + struct mtd_partition *parts;
14632 + int i;
14633 +#endif
14634 +
14635 + spin_lock_irqsave(&sbh_lock, flags);
14636 + coreidx = sb_coreidx(sbh);
14637 +
14638 + /* Check strapping option if chipcommon exists */
14639 + if ((cc = sb_setcore(sbh, SB_CC, 0))) {
14640 + fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
14641 + if (fltype == PFLASH) {
14642 + bcm947xx_map.map_priv_2 = 1;
14643 + window_addr = 0x1c000000;
14644 + bcm947xx_map.size = window_size = 32 * 1024 * 1024;
14645 + if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
14646 + bcm947xx_map.buswidth = 1;
14647 + }
14648 + } else {
14649 + fltype = PFLASH;
14650 + bcm947xx_map.map_priv_2 = 0;
14651 + window_addr = WINDOW_ADDR;
14652 + window_size = WINDOW_SIZE;
14653 + }
14654 +
14655 + sb_setcoreidx(sbh, coreidx);
14656 + spin_unlock_irqrestore(&sbh_lock, flags);
14657 +
14658 + if (fltype != PFLASH) {
14659 + printk(KERN_ERR "pflash: found no supported devices\n");
14660 + ret = -ENODEV;
14661 + goto fail;
14662 + }
14663 +
14664 + bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
14665 + if (!bcm947xx_map.map_priv_1) {
14666 + printk(KERN_ERR "pflash: ioremap failed\n");
14667 + ret = -EIO;
14668 + goto fail;
14669 + }
14670 +
14671 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
14672 + printk(KERN_ERR "pflash: cfi_probe failed\n");
14673 + ret = -ENXIO;
14674 + goto fail;
14675 + }
14676 +
14677 + bcm947xx_mtd->module = THIS_MODULE;
14678 +
14679 + /* Allow size override for testing */
14680 + size = flash ? : bcm947xx_mtd->size;
14681 +
14682 + printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
14683 +
14684 +#ifdef CONFIG_MTD_PARTITIONS
14685 + parts = init_mtd_partitions(bcm947xx_mtd, size);
14686 + for (i = 0; parts[i].name; i++);
14687 + ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
14688 + if (ret) {
14689 + printk(KERN_ERR "pflash: add_mtd_partitions failed\n");
14690 + goto fail;
14691 + }
14692 +#endif
14693 +
14694 + return 0;
14695 +
14696 + fail:
14697 + if (bcm947xx_mtd)
14698 + map_destroy(bcm947xx_mtd);
14699 + if (bcm947xx_map.map_priv_1)
14700 + iounmap((void *) bcm947xx_map.map_priv_1);
14701 + bcm947xx_map.map_priv_1 = 0;
14702 + return ret;
14703 +}
14704 +
14705 +mod_exit_t cleanup_bcm947xx_map(void)
14706 +{
14707 +#ifdef CONFIG_MTD_PARTITIONS
14708 + del_mtd_partitions(bcm947xx_mtd);
14709 +#endif
14710 + map_destroy(bcm947xx_mtd);
14711 + iounmap((void *) bcm947xx_map.map_priv_1);
14712 + bcm947xx_map.map_priv_1 = 0;
14713 +}
14714 +
14715 +module_init(init_bcm947xx_map);
14716 +module_exit(cleanup_bcm947xx_map);
14717 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
14718 --- linux.old/drivers/net/Config.in 2005-11-07 23:12:51.110920000 +0100
14719 +++ linux.dev/drivers/net/Config.in 2005-11-07 21:57:07.905589500 +0100
14720 @@ -2,6 +2,8 @@
14721 # Network device configuration
14722 #
14723
14724 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
14725 +
14726 source drivers/net/arcnet/Config.in
14727
14728 tristate 'Dummy net driver support' CONFIG_DUMMY
14729 @@ -174,6 +176,7 @@
14730
14731 dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
14732 dep_tristate ' Broadcom 4400 ethernet support (EXPERIMENTAL)' CONFIG_B44 $CONFIG_PCI $CONFIG_EXPERIMENTAL
14733 + dep_tristate ' Proprietary Broadcom 10/100 Ethernet support' CONFIG_ET $CONFIG_PCI
14734 dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
14735 dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
14736 if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
14737 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
14738 --- linux.old/drivers/net/Makefile 2005-11-07 23:12:51.110920000 +0100
14739 +++ linux.dev/drivers/net/Makefile 2005-11-07 21:57:07.905589500 +0100
14740 @@ -3,6 +3,8 @@
14741 # Makefile for the Linux network (ethercard) device drivers.
14742 #
14743
14744 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14745 +
14746 obj-y :=
14747 obj-m :=
14748 obj-n :=
14749 @@ -39,6 +41,9 @@
14750 obj-$(CONFIG_ISDN) += slhc.o
14751 endif
14752
14753 +subdir-$(CONFIG_HND) += hnd
14754 +subdir-$(CONFIG_ET) += et
14755 +subdir-$(CONFIG_WL) += wl
14756 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
14757 subdir-$(CONFIG_NET_WIRELESS) += wireless
14758 subdir-$(CONFIG_TULIP) += tulip
14759 @@ -69,6 +74,16 @@
14760 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
14761 obj-$(CONFIG_SUNGEM) += sungem.o
14762
14763 +ifeq ($(CONFIG_HND),y)
14764 + obj-y += hnd/hnd.o
14765 +endif
14766 +ifeq ($(CONFIG_ET),y)
14767 + obj-y += et/et.o
14768 +endif
14769 +ifeq ($(CONFIG_WL),y)
14770 + obj-y += wl/wl.o
14771 +endif
14772 +
14773 obj-$(CONFIG_MACE) += mace.o
14774 obj-$(CONFIG_BMAC) += bmac.o
14775 obj-$(CONFIG_GMAC) += gmac.o
14776 @@ -266,6 +281,7 @@
14777 endif
14778 endif
14779
14780 +
14781 include $(TOPDIR)/Rules.make
14782
14783 clean:
14784 diff -urN linux.old/drivers/net/et/Makefile linux.dev/drivers/net/et/Makefile
14785 --- linux.old/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
14786 +++ linux.dev/drivers/net/et/Makefile 2005-11-07 21:57:07.905589500 +0100
14787 @@ -0,0 +1,21 @@
14788 +#
14789 +# Makefile for the Broadcom et driver
14790 +#
14791 +# Copyright 2004, Broadcom Corporation
14792 +# All Rights Reserved.
14793 +#
14794 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14795 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14796 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14797 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14798 +#
14799 +# $Id: Makefile,v 1.1 2005/03/16 13:50:00 wbx Exp $
14800 +#
14801 +
14802 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCM47XX_CHOPS -DDMA -DBCMDRIVER
14803 +
14804 +O_TARGET := et.o
14805 +obj-y := et_linux.o etc.o etc47xx.o etc_robo.o etc_adm.o
14806 +obj-m := $(O_TARGET)
14807 +
14808 +include $(TOPDIR)/Rules.make
14809 diff -urN linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
14810 --- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
14811 +++ linux.dev/drivers/net/hnd/Makefile 2005-11-07 21:57:07.905589500 +0100
14812 @@ -0,0 +1,19 @@
14813 +#
14814 +# Makefile for the BCM47xx specific kernel interface routines
14815 +# under Linux.
14816 +#
14817 +
14818 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
14819 +
14820 +O_TARGET := hnd.o
14821 +
14822 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
14823 +
14824 +export-objs := shared_ksyms.o
14825 +obj-y := shared_ksyms.o $(HND_OBJS)
14826 +obj-m := $(O_TARGET)
14827 +
14828 +include $(TOPDIR)/Rules.make
14829 +
14830 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
14831 + sh -e $< $(HND_OBJS) > $@
14832 diff -urN linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
14833 --- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
14834 +++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-11-07 22:28:05.077337250 +0100
14835 @@ -0,0 +1,936 @@
14836 +/*
14837 + * Misc useful routines to access NIC SROM/OTP .
14838 + *
14839 + * Copyright 2005, Broadcom Corporation
14840 + * All Rights Reserved.
14841 + *
14842 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14843 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14844 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14845 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14846 + * $Id$
14847 + */
14848 +
14849 +#include <typedefs.h>
14850 +#include <osl.h>
14851 +#include <bcmutils.h>
14852 +#include <bcmsrom.h>
14853 +#include <bcmdevs.h>
14854 +#include <bcmendian.h>
14855 +#include <sbpcmcia.h>
14856 +#include <pcicfg.h>
14857 +#include <sbutils.h>
14858 +#include <bcmnvram.h>
14859 +
14860 +#include <proto/ethernet.h> /* for sprom content groking */
14861 +
14862 +#define VARS_MAX 4096 /* should be reduced */
14863 +
14864 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
14865 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
14866 +
14867 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
14868 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
14869 +static int initvars_flash_sb(void *sbh, char **vars, int *count);
14870 +static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
14871 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
14872 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
14873 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
14874 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
14875 +
14876 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
14877 +static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
14878 +
14879 +/*
14880 + * Initialize local vars from the right source for this platform.
14881 + * Return 0 on success, nonzero on error.
14882 + */
14883 +int
14884 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
14885 +{
14886 + ASSERT(bustype == BUSTYPE(bustype));
14887 + if (vars == NULL || count == NULL)
14888 + return (0);
14889 +
14890 + switch (BUSTYPE(bustype)) {
14891 + case SB_BUS:
14892 + case JTAG_BUS:
14893 + return initvars_flash_sb(sbh, vars, count);
14894 +
14895 + case PCI_BUS:
14896 + ASSERT(curmap); /* can not be NULL */
14897 + return initvars_srom_pci(sbh, curmap, vars, count);
14898 +
14899 + case PCMCIA_BUS:
14900 + return initvars_cis_pcmcia(sbh, osh, vars, count);
14901 +
14902 +
14903 + default:
14904 + ASSERT(0);
14905 + }
14906 + return (-1);
14907 +}
14908 +
14909 +/* support only 16-bit word read from srom */
14910 +int
14911 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
14912 +{
14913 + void *srom;
14914 + uint i, off, nw;
14915 +
14916 + ASSERT(bustype == BUSTYPE(bustype));
14917 +
14918 + /* check input - 16-bit access only */
14919 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
14920 + return 1;
14921 +
14922 + off = byteoff / 2;
14923 + nw = nbytes / 2;
14924 +
14925 + if (BUSTYPE(bustype) == PCI_BUS) {
14926 + if (!curmap)
14927 + return 1;
14928 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
14929 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
14930 + return 1;
14931 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
14932 + for (i = 0; i < nw; i++) {
14933 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
14934 + return 1;
14935 + }
14936 + } else {
14937 + return 1;
14938 + }
14939 +
14940 + return 0;
14941 +}
14942 +
14943 +/* support only 16-bit word write into srom */
14944 +int
14945 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
14946 +{
14947 + uint16 *srom;
14948 + uint i, off, nw, crc_range;
14949 + uint16 image[SPROM_SIZE], *p;
14950 + uint8 crc;
14951 + volatile uint32 val32;
14952 +
14953 + ASSERT(bustype == BUSTYPE(bustype));
14954 +
14955 + /* check input - 16-bit access only */
14956 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
14957 + return 1;
14958 +
14959 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
14960 +
14961 + /* if changes made inside crc cover range */
14962 + if (byteoff < crc_range) {
14963 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
14964 + /* read data including entire first 64 words from srom */
14965 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
14966 + return 1;
14967 + /* make changes */
14968 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
14969 + /* calculate crc */
14970 + htol16_buf(image, crc_range);
14971 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
14972 + ltoh16_buf(image, crc_range);
14973 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
14974 + p = image;
14975 + off = 0;
14976 + } else {
14977 + p = buf;
14978 + off = byteoff / 2;
14979 + nw = nbytes / 2;
14980 + }
14981 +
14982 + if (BUSTYPE(bustype) == PCI_BUS) {
14983 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
14984 + /* enable writes to the SPROM */
14985 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
14986 + val32 |= SPROM_WRITEEN;
14987 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
14988 + bcm_mdelay(WRITE_ENABLE_DELAY);
14989 + /* write srom */
14990 + for (i = 0; i < nw; i++) {
14991 + W_REG(&srom[off + i], p[i]);
14992 + bcm_mdelay(WRITE_WORD_DELAY);
14993 + }
14994 + /* disable writes to the SPROM */
14995 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
14996 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
14997 + /* enable writes to the SPROM */
14998 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
14999 + return 1;
15000 + bcm_mdelay(WRITE_ENABLE_DELAY);
15001 + /* write srom */
15002 + for (i = 0; i < nw; i++) {
15003 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
15004 + bcm_mdelay(WRITE_WORD_DELAY);
15005 + }
15006 + /* disable writes to the SPROM */
15007 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
15008 + return 1;
15009 + } else {
15010 + return 1;
15011 + }
15012 +
15013 + bcm_mdelay(WRITE_ENABLE_DELAY);
15014 + return 0;
15015 +}
15016 +
15017 +
15018 +static int
15019 +srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
15020 +{
15021 + char eabuf[32];
15022 + char *vp, *base;
15023 + uint8 tup, tlen, sromrev = 1;
15024 + int i, j;
15025 + uint varsize;
15026 + bool ag_init = FALSE;
15027 + uint32 w32;
15028 +
15029 + ASSERT(vars);
15030 + ASSERT(count);
15031 +
15032 + base = vp = MALLOC(osh, VARS_MAX);
15033 + ASSERT(vp);
15034 + if (!vp)
15035 + return -2;
15036 +
15037 + i = 0;
15038 + do {
15039 + tup = cis[i++];
15040 + tlen = cis[i++];
15041 + if ((i + tlen) >= CIS_SIZE)
15042 + break;
15043 +
15044 + switch (tup) {
15045 + case CISTPL_MANFID:
15046 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
15047 + vp++;
15048 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
15049 + vp++;
15050 + break;
15051 +
15052 + case CISTPL_FUNCE:
15053 + if (cis[i] == LAN_NID) {
15054 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
15055 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
15056 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15057 + vp++;
15058 + }
15059 + break;
15060 +
15061 + case CISTPL_CFTABLE:
15062 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
15063 + vp++;
15064 + break;
15065 +
15066 + case CISTPL_BRCM_HNBU:
15067 + switch (cis[i]) {
15068 + case HNBU_SROMREV:
15069 + sromrev = cis[i + 1];
15070 + break;
15071 +
15072 + case HNBU_CHIPID:
15073 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
15074 + vp++;
15075 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
15076 + vp++;
15077 + if (tlen == 7) {
15078 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
15079 + vp++;
15080 + }
15081 + break;
15082 +
15083 + case HNBU_BOARDREV:
15084 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
15085 + vp++;
15086 + break;
15087 +
15088 + case HNBU_AA:
15089 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
15090 + vp++;
15091 + break;
15092 +
15093 + case HNBU_AG:
15094 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
15095 + vp++;
15096 + ag_init = TRUE;
15097 + break;
15098 +
15099 + case HNBU_CC:
15100 + ASSERT(sromrev > 1);
15101 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
15102 + vp++;
15103 + break;
15104 +
15105 + case HNBU_PAPARMS:
15106 + if (tlen == 2) {
15107 + ASSERT(sromrev == 1);
15108 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
15109 + vp++;
15110 + } else if (tlen >= 9) {
15111 + if (tlen == 10) {
15112 + ASSERT(sromrev == 2);
15113 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
15114 + vp++;
15115 + } else
15116 + ASSERT(tlen == 9);
15117 +
15118 + for (j = 0; j < 3; j++) {
15119 + vp += sprintf(vp, "pa0b%d=%d", j,
15120 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
15121 + vp++;
15122 + }
15123 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
15124 + vp++;
15125 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
15126 + vp++;
15127 + } else
15128 + ASSERT(tlen >= 9);
15129 + break;
15130 +
15131 + case HNBU_OEM:
15132 + ASSERT(sromrev == 1);
15133 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15134 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
15135 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
15136 + vp++;
15137 + break;
15138 +
15139 + case HNBU_BOARDFLAGS:
15140 + w32 = (cis[i + 2] << 8) + cis[i + 1];
15141 + if (tlen == 5)
15142 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
15143 + vp += sprintf(vp, "boardflags=0x%x", w32);
15144 + vp++;
15145 + break;
15146 +
15147 + case HNBU_LEDS:
15148 + if (cis[i + 1] != 0xff) {
15149 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
15150 + vp++;
15151 + }
15152 + if (cis[i + 2] != 0xff) {
15153 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
15154 + vp++;
15155 + }
15156 + if (cis[i + 3] != 0xff) {
15157 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
15158 + vp++;
15159 + }
15160 + if (cis[i + 4] != 0xff) {
15161 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
15162 + vp++;
15163 + }
15164 + break;
15165 +
15166 + case HNBU_CCODE:
15167 + ASSERT(sromrev > 1);
15168 + vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
15169 + vp++;
15170 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
15171 + vp++;
15172 + break;
15173 +
15174 + case HNBU_CCKPO:
15175 + ASSERT(sromrev > 2);
15176 + vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
15177 + vp++;
15178 + break;
15179 +
15180 + case HNBU_OFDMPO:
15181 + ASSERT(sromrev > 2);
15182 + vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
15183 + (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
15184 + vp++;
15185 + break;
15186 + }
15187 + break;
15188 +
15189 + }
15190 + i += tlen;
15191 + } while (tup != 0xff);
15192 +
15193 + /* Set the srom version */
15194 + vp += sprintf(vp, "sromrev=%d", sromrev);
15195 + vp++;
15196 +
15197 + /* if there is no antenna gain field, set default */
15198 + if (ag_init == FALSE) {
15199 + ASSERT(sromrev == 1);
15200 + vp += sprintf(vp, "ag0=%d", 0xff);
15201 + vp++;
15202 + }
15203 +
15204 + /* final nullbyte terminator */
15205 + *vp++ = '\0';
15206 + varsize = (uint)(vp - base);
15207 +
15208 + ASSERT((vp - base) < VARS_MAX);
15209 +
15210 + if (varsize == VARS_MAX) {
15211 + *vars = base;
15212 + } else {
15213 + vp = MALLOC(osh, varsize);
15214 + ASSERT(vp);
15215 + if (vp)
15216 + bcopy(base, vp, varsize);
15217 + MFREE(osh, base, VARS_MAX);
15218 + *vars = vp;
15219 + if (!vp) {
15220 + *count = 0;
15221 + return -2;
15222 + }
15223 + }
15224 + *count = varsize;
15225 +
15226 + return (0);
15227 +}
15228 +
15229 +
15230 +/* set PCMCIA sprom command register */
15231 +static int
15232 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
15233 +{
15234 + uint8 status = 0;
15235 + uint wait_cnt = 1000;
15236 +
15237 + /* write sprom command register */
15238 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
15239 +
15240 + /* wait status */
15241 + while (wait_cnt--) {
15242 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
15243 + if (status & SROM_DONE)
15244 + return 0;
15245 + }
15246 +
15247 + return 1;
15248 +}
15249 +
15250 +/* read a word from the PCMCIA srom */
15251 +static int
15252 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
15253 +{
15254 + uint8 addr_l, addr_h, data_l, data_h;
15255 +
15256 + addr_l = (uint8)((addr * 2) & 0xff);
15257 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15258 +
15259 + /* set address */
15260 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15261 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15262 +
15263 + /* do read */
15264 + if (sprom_cmd_pcmcia(osh, SROM_READ))
15265 + return 1;
15266 +
15267 + /* read data */
15268 + data_h = data_l = 0;
15269 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
15270 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
15271 +
15272 + *data = (data_h << 8) | data_l;
15273 + return 0;
15274 +}
15275 +
15276 +/* write a word to the PCMCIA srom */
15277 +static int
15278 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
15279 +{
15280 + uint8 addr_l, addr_h, data_l, data_h;
15281 +
15282 + addr_l = (uint8)((addr * 2) & 0xff);
15283 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15284 + data_l = (uint8)(data & 0xff);
15285 + data_h = (uint8)((data >> 8) & 0xff);
15286 +
15287 + /* set address */
15288 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15289 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15290 +
15291 + /* write data */
15292 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
15293 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
15294 +
15295 + /* do write */
15296 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
15297 +}
15298 +
15299 +/*
15300 + * Read in and validate sprom.
15301 + * Return 0 on success, nonzero on error.
15302 + */
15303 +static int
15304 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
15305 +{
15306 + int err = 0;
15307 + uint i;
15308 +
15309 + /* read the sprom */
15310 + for (i = 0; i < nwords; i++)
15311 + buf[i] = R_REG(&sprom[wordoff + i]);
15312 +
15313 + if (check_crc) {
15314 + /* fixup the endianness so crc8 will pass */
15315 + htol16_buf(buf, nwords * 2);
15316 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
15317 + err = 1;
15318 + /* now correct the endianness of the byte array */
15319 + ltoh16_buf(buf, nwords * 2);
15320 + }
15321 +
15322 + return err;
15323 +}
15324 +
15325 +/*
15326 +* Create variable table from memory.
15327 +* Return 0 on success, nonzero on error.
15328 +*/
15329 +static int
15330 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
15331 +{
15332 + int c = (int)(end - start);
15333 +
15334 + /* do it only when there is more than just the null string */
15335 + if (c > 1) {
15336 + char *vp = MALLOC(osh, c);
15337 + ASSERT(vp);
15338 + if (!vp)
15339 + return BCME_NOMEM;
15340 + bcopy(start, vp, c);
15341 + *vars = vp;
15342 + *count = c;
15343 + }
15344 + else {
15345 + *vars = NULL;
15346 + *count = 0;
15347 + }
15348 +
15349 + return 0;
15350 +}
15351 +
15352 +/*
15353 +* Find variables with <devpath> from flash. 'base' points to the beginning
15354 +* of the table upon enter and to the end of the table upon exit when success.
15355 +* Return 0 on success, nonzero on error.
15356 +*/
15357 +static int
15358 +initvars_flash(osl_t *osh, char **base, int size, char *devpath)
15359 +{
15360 + char *vp = *base;
15361 + char *flash;
15362 + int err;
15363 + char *s;
15364 + uint l, dl, copy_len;
15365 +
15366 + /* allocate memory and read in flash */
15367 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
15368 + return BCME_NOMEM;
15369 + if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
15370 + goto exit;
15371 +
15372 + /* grab vars with the <devpath> prefix in name */
15373 + dl = strlen(devpath);
15374 + for (s = flash; s && *s; s += l + 1) {
15375 + l = strlen(s);
15376 +
15377 + /* skip non-matching variable */
15378 + if (strncmp(s, devpath, dl))
15379 + continue;
15380 +
15381 + /* is there enough room to copy? */
15382 + copy_len = l - dl + 1;
15383 + if (size < (int)copy_len) {
15384 + err = BCME_BUFTOOSHORT;
15385 + goto exit;
15386 + }
15387 +
15388 + /* no prefix, just the name=value */
15389 + strcpy(vp, &s[dl]);
15390 + vp += copy_len;
15391 + size -= copy_len;
15392 + }
15393 +
15394 + /* add null string as terminator */
15395 + if (size < 1) {
15396 + err = BCME_BUFTOOSHORT;
15397 + goto exit;
15398 + }
15399 + *vp++ = '\0';
15400 +
15401 + *base = vp;
15402 +
15403 +exit: MFREE(osh, flash, NVRAM_SPACE);
15404 + return err;
15405 +}
15406 +
15407 +/*
15408 + * Initialize nonvolatile variable table from flash.
15409 + * Return 0 on success, nonzero on error.
15410 + */
15411 +static int
15412 +initvars_flash_sb(void *sbh, char **vars, int *count)
15413 +{
15414 + osl_t *osh = sb_osh(sbh);
15415 + char devpath[SB_DEVPATH_BUFSZ];
15416 + char *vp, *base;
15417 + int err;
15418 +
15419 + ASSERT(vars);
15420 + ASSERT(count);
15421 +
15422 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15423 + return err;
15424 +
15425 + base = vp = MALLOC(osh, VARS_MAX);
15426 + ASSERT(vp);
15427 + if (!vp)
15428 + return BCME_NOMEM;
15429 +
15430 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15431 + goto err;
15432 +
15433 + err = initvars_table(osh, base, vp, vars, count);
15434 +
15435 +err: MFREE(osh, base, VARS_MAX);
15436 + return err;
15437 +}
15438 +
15439 +/*
15440 + * Initialize nonvolatile variable table from sprom.
15441 + * Return 0 on success, nonzero on error.
15442 + */
15443 +static int
15444 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
15445 +{
15446 + uint16 w, b[64];
15447 + uint8 sromrev;
15448 + struct ether_addr ea;
15449 + char eabuf[32];
15450 + uint32 w32;
15451 + int woff, i;
15452 + char *vp, *base;
15453 + osl_t *osh = sb_osh(sbh);
15454 + bool flash = FALSE;
15455 + char name[SB_DEVPATH_BUFSZ+16], *value;
15456 + char devpath[SB_DEVPATH_BUFSZ];
15457 + int err;
15458 +
15459 + /*
15460 + * Apply CRC over SROM content regardless SROM is present or not,
15461 + * and use variable <devpath>sromrev's existance in flash to decide
15462 + * if we should return an error when CRC fails or read SROM variables
15463 + * from flash.
15464 + */
15465 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
15466 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15467 + return err;
15468 + sprintf(name, "%ssromrev", devpath);
15469 + if (!(value = getvar(NULL, name)))
15470 + return (-1);
15471 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
15472 + flash = TRUE;
15473 + }
15474 + /* srom is good */
15475 + else {
15476 + /* top word of sprom contains version and crc8 */
15477 + sromrev = b[63] & 0xff;
15478 + /* bcm4401 sroms misprogrammed */
15479 + if (sromrev == 0x10)
15480 + sromrev = 1;
15481 + }
15482 +
15483 + /* srom version check */
15484 + if (sromrev > 3)
15485 + return (-2);
15486 +
15487 + ASSERT(vars);
15488 + ASSERT(count);
15489 +
15490 + base = vp = MALLOC(osh, VARS_MAX);
15491 + ASSERT(vp);
15492 + if (!vp)
15493 + return -2;
15494 +
15495 + /* read variables from flash */
15496 + if (flash) {
15497 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15498 + goto err;
15499 + goto done;
15500 + }
15501 +
15502 + vp += sprintf(vp, "sromrev=%d", sromrev);
15503 + vp++;
15504 +
15505 + if (sromrev >= 3) {
15506 + /* New section takes over the 3th hardware function space */
15507 +
15508 + /* Words 22+23 are 11a (mid) ofdm power offsets */
15509 + w32 = ((uint32)b[23] << 16) | b[22];
15510 + vp += sprintf(vp, "ofdmapo=%d", w32);
15511 + vp++;
15512 +
15513 + /* Words 24+25 are 11a (low) ofdm power offsets */
15514 + w32 = ((uint32)b[25] << 16) | b[24];
15515 + vp += sprintf(vp, "ofdmalpo=%d", w32);
15516 + vp++;
15517 +
15518 + /* Words 26+27 are 11a (high) ofdm power offsets */
15519 + w32 = ((uint32)b[27] << 16) | b[26];
15520 + vp += sprintf(vp, "ofdmahpo=%d", w32);
15521 + vp++;
15522 +
15523 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15524 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
15525 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15526 +
15527 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15528 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
15529 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
15530 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15531 +
15532 + vp++;
15533 + }
15534 +
15535 + if (sromrev >= 2) {
15536 + /* New section takes over the 4th hardware function space */
15537 +
15538 + /* Word 29 is max power 11a high/low */
15539 + w = b[29];
15540 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
15541 + vp++;
15542 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
15543 + vp++;
15544 +
15545 + /* Words 30-32 set the 11alow pa settings,
15546 + * 33-35 are the 11ahigh ones.
15547 + */
15548 + for (i = 0; i < 3; i++) {
15549 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
15550 + vp++;
15551 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
15552 + vp++;
15553 + }
15554 + w = b[59];
15555 + if (w == 0)
15556 + vp += sprintf(vp, "ccode=");
15557 + else
15558 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
15559 + vp++;
15560 +
15561 + }
15562 +
15563 + /* parameter section of sprom starts at byte offset 72 */
15564 + woff = 72/2;
15565 +
15566 + /* first 6 bytes are il0macaddr */
15567 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15568 + ea.octet[1] = b[woff] & 0xff;
15569 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15570 + ea.octet[3] = b[woff+1] & 0xff;
15571 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15572 + ea.octet[5] = b[woff+2] & 0xff;
15573 + woff += ETHER_ADDR_LEN/2 ;
15574 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15575 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15576 + vp++;
15577 +
15578 + /* next 6 bytes are et0macaddr */
15579 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15580 + ea.octet[1] = b[woff] & 0xff;
15581 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15582 + ea.octet[3] = b[woff+1] & 0xff;
15583 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15584 + ea.octet[5] = b[woff+2] & 0xff;
15585 + woff += ETHER_ADDR_LEN/2 ;
15586 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15587 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
15588 + vp++;
15589 +
15590 + /* next 6 bytes are et1macaddr */
15591 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15592 + ea.octet[1] = b[woff] & 0xff;
15593 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15594 + ea.octet[3] = b[woff+1] & 0xff;
15595 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15596 + ea.octet[5] = b[woff+2] & 0xff;
15597 + woff += ETHER_ADDR_LEN/2 ;
15598 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15599 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
15600 + vp++;
15601 +
15602 + /*
15603 + * Enet phy settings one or two singles or a dual
15604 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
15605 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
15606 + * Bit 14 : Mdio for enet0
15607 + * Bit 15 : Mdio for enet1
15608 + */
15609 + w = b[woff];
15610 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
15611 + vp++;
15612 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
15613 + vp++;
15614 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
15615 + vp++;
15616 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
15617 + vp++;
15618 +
15619 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
15620 + w = b[46];
15621 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
15622 + vp++;
15623 +
15624 + if (sromrev > 1)
15625 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
15626 + else
15627 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
15628 + vp++;
15629 +
15630 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
15631 + vp++;
15632 +
15633 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
15634 + vp++;
15635 +
15636 + /* Words 47-49 set the (wl) pa settings */
15637 + woff = 47;
15638 +
15639 + for (i = 0; i < 3; i++) {
15640 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
15641 + vp++;
15642 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
15643 + vp++;
15644 + }
15645 +
15646 + /*
15647 + * Words 50-51 set the customer-configured wl led behavior.
15648 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
15649 + * LED behavior values defined in wlioctl.h .
15650 + */
15651 + w = b[50];
15652 + if ((w != 0) && (w != 0xffff)) {
15653 + /* gpio0 */
15654 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
15655 + vp++;
15656 +
15657 + /* gpio1 */
15658 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
15659 + vp++;
15660 + }
15661 + w = b[51];
15662 + if ((w != 0) && (w != 0xffff)) {
15663 + /* gpio2 */
15664 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
15665 + vp++;
15666 +
15667 + /* gpio3 */
15668 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
15669 + vp++;
15670 + }
15671 +
15672 + /* Word 52 is max power 0/1 */
15673 + w = b[52];
15674 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
15675 + vp++;
15676 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
15677 + vp++;
15678 +
15679 + /* Word 56 is idle tssi target 0/1 */
15680 + w = b[56];
15681 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
15682 + vp++;
15683 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
15684 + vp++;
15685 +
15686 + /* Word 57 is boardflags, if not programmed make it zero */
15687 + w32 = (uint32)b[57];
15688 + if (w32 == 0xffff) w32 = 0;
15689 + if (sromrev > 1) {
15690 + /* Word 28 is the high bits of boardflags */
15691 + w32 |= (uint32)b[28] << 16;
15692 + }
15693 + vp += sprintf(vp, "boardflags=%d", w32);
15694 + vp++;
15695 +
15696 + /* Word 58 is antenna gain 0/1 */
15697 + w = b[58];
15698 + vp += sprintf(vp, "ag0=%d", w & 0xff);
15699 + vp++;
15700 +
15701 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
15702 + vp++;
15703 +
15704 + if (sromrev == 1) {
15705 + /* set the oem string */
15706 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15707 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
15708 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
15709 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
15710 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
15711 + vp++;
15712 + } else if (sromrev == 2) {
15713 + /* Word 60 OFDM tx power offset from CCK level */
15714 + /* OFDM Power Offset - opo */
15715 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
15716 + vp++;
15717 + } else {
15718 + /* Word 60: cck power offsets */
15719 + vp += sprintf(vp, "cckpo=%d", b[60]);
15720 + vp++;
15721 +
15722 + /* Words 61+62: 11g ofdm power offsets */
15723 + w32 = ((uint32)b[62] << 16) | b[61];
15724 + vp += sprintf(vp, "ofdmgpo=%d", w32);
15725 + vp++;
15726 + }
15727 +
15728 + /* final nullbyte terminator */
15729 + *vp++ = '\0';
15730 +
15731 + ASSERT((vp - base) <= VARS_MAX);
15732 +
15733 +done: err = initvars_table(osh, base, vp, vars, count);
15734 +
15735 +err: MFREE(osh, base, VARS_MAX);
15736 + return err;
15737 +}
15738 +
15739 +/*
15740 + * Read the cis and call parsecis to initialize the vars.
15741 + * Return 0 on success, nonzero on error.
15742 + */
15743 +static int
15744 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
15745 +{
15746 + uint8 *cis = NULL;
15747 + int rc;
15748 + uint data_sz;
15749 +
15750 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
15751 +
15752 + if ((cis = MALLOC(osh, data_sz)) == NULL)
15753 + return (-2);
15754 +
15755 + if (sb_pcmciarev(sbh) == 1) {
15756 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
15757 + MFREE(osh, cis, data_sz);
15758 + return (-1);
15759 + }
15760 + /* fix up endianess for 16-bit data vs 8-bit parsing */
15761 + ltoh16_buf((uint16 *)cis, data_sz);
15762 + } else
15763 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
15764 +
15765 + rc = srom_parsecis(osh, cis, vars, count);
15766 +
15767 + MFREE(osh, cis, data_sz);
15768 +
15769 + return (rc);
15770 +}
15771 +
15772 diff -urN linux.old/drivers/net/hnd/bcmutils.c linux.dev/drivers/net/hnd/bcmutils.c
15773 --- linux.old/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
15774 +++ linux.dev/drivers/net/hnd/bcmutils.c 2005-11-08 12:52:21.836276500 +0100
15775 @@ -0,0 +1,1081 @@
15776 +/*
15777 + * Misc useful OS-independent routines.
15778 + *
15779 + * Copyright 2005, Broadcom Corporation
15780 + * All Rights Reserved.
15781 + *
15782 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15783 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15784 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15785 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15786 + * $Id$
15787 + */
15788 +
15789 +#include <typedefs.h>
15790 +#ifdef BCMDRIVER
15791 +#include <osl.h>
15792 +#include <sbutils.h>
15793 +#include <bcmnvram.h>
15794 +#else
15795 +#include <stdio.h>
15796 +#include <string.h>
15797 +#endif
15798 +#include <bcmutils.h>
15799 +#include <bcmendian.h>
15800 +#include <bcmdevs.h>
15801 +
15802 +#ifdef BCMDRIVER
15803 +/* copy a pkt buffer chain into a buffer */
15804 +uint
15805 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
15806 +{
15807 + uint n, ret = 0;
15808 +
15809 + if (len < 0)
15810 + len = 4096; /* "infinite" */
15811 +
15812 + /* skip 'offset' bytes */
15813 + for (; p && offset; p = PKTNEXT(osh, p)) {
15814 + if (offset < (uint)PKTLEN(osh, p))
15815 + break;
15816 + offset -= PKTLEN(osh, p);
15817 + }
15818 +
15819 + if (!p)
15820 + return 0;
15821 +
15822 + /* copy the data */
15823 + for (; p && len; p = PKTNEXT(osh, p)) {
15824 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
15825 + bcopy(PKTDATA(osh, p) + offset, buf, n);
15826 + buf += n;
15827 + len -= n;
15828 + ret += n;
15829 + offset = 0;
15830 + }
15831 +
15832 + return ret;
15833 +}
15834 +
15835 +/* return total length of buffer chain */
15836 +uint
15837 +pkttotlen(osl_t *osh, void *p)
15838 +{
15839 + uint total;
15840 +
15841 + total = 0;
15842 + for (; p; p = PKTNEXT(osh, p))
15843 + total += PKTLEN(osh, p);
15844 + return (total);
15845 +}
15846 +
15847 +void
15848 +pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
15849 +{
15850 + q->head = q->tail = NULL;
15851 + q->maxlen = maxlen;
15852 + q->len = 0;
15853 + if (prio_map) {
15854 + q->priority = TRUE;
15855 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
15856 + }
15857 + else
15858 + q->priority = FALSE;
15859 +}
15860 +
15861 +/* should always check pktq_full before calling pktenq */
15862 +void
15863 +pktenq(struct pktq *q, void *p, bool lifo)
15864 +{
15865 + void *next, *prev;
15866 +
15867 + /* allow 10 pkts slack */
15868 + ASSERT(q->len < (q->maxlen + 10));
15869 +
15870 + /* Queueing chains not allowed */
15871 + ASSERT(PKTLINK(p) == NULL);
15872 +
15873 + /* Queue is empty */
15874 + if (q->tail == NULL) {
15875 + ASSERT(q->head == NULL);
15876 + q->head = q->tail = p;
15877 + }
15878 +
15879 + /* Insert at head or tail */
15880 + else if (q->priority == FALSE) {
15881 + /* Insert at head (LIFO) */
15882 + if (lifo) {
15883 + PKTSETLINK(p, q->head);
15884 + q->head = p;
15885 + }
15886 + /* Insert at tail (FIFO) */
15887 + else {
15888 + ASSERT(PKTLINK(q->tail) == NULL);
15889 + PKTSETLINK(q->tail, p);
15890 + PKTSETLINK(p, NULL);
15891 + q->tail = p;
15892 + }
15893 + }
15894 +
15895 + /* Insert by priority */
15896 + else {
15897 + /* legal priorities 0-7 */
15898 + ASSERT(PKTPRIO(p) <= MAXPRIO);
15899 +
15900 + ASSERT(q->head);
15901 + ASSERT(q->tail);
15902 + /* Shortcut to insertion at tail */
15903 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
15904 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
15905 + prev = q->tail;
15906 + next = NULL;
15907 + }
15908 + /* Insert at head or in the middle */
15909 + else {
15910 + prev = NULL;
15911 + next = q->head;
15912 + }
15913 + /* Walk the queue */
15914 + for (; next; prev = next, next = PKTLINK(next)) {
15915 + /* Priority queue invariant */
15916 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
15917 + /* Insert at head of string of packets of same priority (LIFO) */
15918 + if (lifo) {
15919 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
15920 + break;
15921 + }
15922 + /* Insert at tail of string of packets of same priority (FIFO) */
15923 + else {
15924 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
15925 + break;
15926 + }
15927 + }
15928 + /* Insert at tail */
15929 + if (next == NULL) {
15930 + ASSERT(PKTLINK(q->tail) == NULL);
15931 + PKTSETLINK(q->tail, p);
15932 + PKTSETLINK(p, NULL);
15933 + q->tail = p;
15934 + }
15935 + /* Insert in the middle */
15936 + else if (prev) {
15937 + PKTSETLINK(prev, p);
15938 + PKTSETLINK(p, next);
15939 + }
15940 + /* Insert at head */
15941 + else {
15942 + PKTSETLINK(p, q->head);
15943 + q->head = p;
15944 + }
15945 + }
15946 +
15947 + /* List invariants after insertion */
15948 + ASSERT(q->head);
15949 + ASSERT(PKTLINK(q->tail) == NULL);
15950 +
15951 + q->len++;
15952 +}
15953 +
15954 +/* dequeue packet at head */
15955 +void*
15956 +pktdeq(struct pktq *q)
15957 +{
15958 + void *p;
15959 +
15960 + if ((p = q->head)) {
15961 + ASSERT(q->tail);
15962 + q->head = PKTLINK(p);
15963 + PKTSETLINK(p, NULL);
15964 + q->len--;
15965 + if (q->head == NULL)
15966 + q->tail = NULL;
15967 + }
15968 + else {
15969 + ASSERT(q->tail == NULL);
15970 + }
15971 +
15972 + return (p);
15973 +}
15974 +
15975 +/* dequeue packet at tail */
15976 +void*
15977 +pktdeqtail(struct pktq *q)
15978 +{
15979 + void *p;
15980 + void *next, *prev;
15981 +
15982 + if (q->head == q->tail) { /* last packet on queue or queue empty */
15983 + p = q->head;
15984 + q->head = q->tail = NULL;
15985 + q->len = 0;
15986 + return(p);
15987 + }
15988 +
15989 + /* start walk at head */
15990 + prev = NULL;
15991 + next = q->head;
15992 +
15993 + /* Walk the queue to find prev of q->tail */
15994 + for (; next; prev = next, next = PKTLINK(next)) {
15995 + if (next == q->tail)
15996 + break;
15997 + }
15998 +
15999 + ASSERT(prev);
16000 +
16001 + PKTSETLINK(prev, NULL);
16002 + q->tail = prev;
16003 + q->len--;
16004 + p = next;
16005 +
16006 + return (p);
16007 +}
16008 +
16009 +unsigned char bcm_ctype[] = {
16010 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
16011 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
16012 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
16013 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
16014 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
16015 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
16016 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
16017 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
16018 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
16019 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
16020 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
16021 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
16022 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
16023 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
16024 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
16025 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
16026 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
16027 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
16028 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
16029 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
16030 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
16031 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
16032 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
16033 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
16034 +};
16035 +
16036 +uchar
16037 +bcm_toupper(uchar c)
16038 +{
16039 + if (bcm_islower(c))
16040 + c -= 'a'-'A';
16041 + return (c);
16042 +}
16043 +
16044 +ulong
16045 +bcm_strtoul(char *cp, char **endp, uint base)
16046 +{
16047 + ulong result, value;
16048 + bool minus;
16049 +
16050 + minus = FALSE;
16051 +
16052 + while (bcm_isspace(*cp))
16053 + cp++;
16054 +
16055 + if (cp[0] == '+')
16056 + cp++;
16057 + else if (cp[0] == '-') {
16058 + minus = TRUE;
16059 + cp++;
16060 + }
16061 +
16062 + if (base == 0) {
16063 + if (cp[0] == '0') {
16064 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
16065 + base = 16;
16066 + cp = &cp[2];
16067 + } else {
16068 + base = 8;
16069 + cp = &cp[1];
16070 + }
16071 + } else
16072 + base = 10;
16073 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
16074 + cp = &cp[2];
16075 + }
16076 +
16077 + result = 0;
16078 +
16079 + while (bcm_isxdigit(*cp) &&
16080 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
16081 + result = result*base + value;
16082 + cp++;
16083 + }
16084 +
16085 + if (minus)
16086 + result = (ulong)(result * -1);
16087 +
16088 + if (endp)
16089 + *endp = (char *)cp;
16090 +
16091 + return (result);
16092 +}
16093 +
16094 +uint
16095 +bcm_atoi(char *s)
16096 +{
16097 + uint n;
16098 +
16099 + n = 0;
16100 +
16101 + while (bcm_isdigit(*s))
16102 + n = (n * 10) + *s++ - '0';
16103 + return (n);
16104 +}
16105 +
16106 +/* return pointer to location of substring 'needle' in 'haystack' */
16107 +char*
16108 +bcmstrstr(char *haystack, char *needle)
16109 +{
16110 + int len, nlen;
16111 + int i;
16112 +
16113 + if ((haystack == NULL) || (needle == NULL))
16114 + return (haystack);
16115 +
16116 + nlen = strlen(needle);
16117 + len = strlen(haystack) - nlen + 1;
16118 +
16119 + for (i = 0; i < len; i++)
16120 + if (bcmp(needle, &haystack[i], nlen) == 0)
16121 + return (&haystack[i]);
16122 + return (NULL);
16123 +}
16124 +
16125 +char*
16126 +bcmstrcat(char *dest, const char *src)
16127 +{
16128 + strcpy(&dest[strlen(dest)], src);
16129 + return (dest);
16130 +}
16131 +
16132 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
16133 +/* registry routine buffer preparation utility functions:
16134 + * parameter order is like strncpy, but returns count
16135 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
16136 + */
16137 +ulong
16138 +wchar2ascii(
16139 + char *abuf,
16140 + ushort *wbuf,
16141 + ushort wbuflen,
16142 + ulong abuflen
16143 +)
16144 +{
16145 + ulong copyct = 1;
16146 + ushort i;
16147 +
16148 + if (abuflen == 0)
16149 + return 0;
16150 +
16151 + /* wbuflen is in bytes */
16152 + wbuflen /= sizeof(ushort);
16153 +
16154 + for (i = 0; i < wbuflen; ++i) {
16155 + if (--abuflen == 0)
16156 + break;
16157 + *abuf++ = (char) *wbuf++;
16158 + ++copyct;
16159 + }
16160 + *abuf = '\0';
16161 +
16162 + return copyct;
16163 +}
16164 +#endif
16165 +
16166 +char*
16167 +bcm_ether_ntoa(char *ea, char *buf)
16168 +{
16169 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
16170 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
16171 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
16172 + return (buf);
16173 +}
16174 +
16175 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
16176 +int
16177 +bcm_ether_atoe(char *p, char *ea)
16178 +{
16179 + int i = 0;
16180 +
16181 + for (;;) {
16182 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
16183 + if (!*p++ || i == 6)
16184 + break;
16185 + }
16186 +
16187 + return (i == 6);
16188 +}
16189 +
16190 +void
16191 +bcm_mdelay(uint ms)
16192 +{
16193 + uint i;
16194 +
16195 + for (i = 0; i < ms; i++) {
16196 + OSL_DELAY(1000);
16197 + }
16198 +}
16199 +
16200 +/*
16201 + * Search the name=value vars for a specific one and return its value.
16202 + * Returns NULL if not found.
16203 + */
16204 +char*
16205 +getvar(char *vars, char *name)
16206 +{
16207 + char *s;
16208 + int len;
16209 +
16210 + len = strlen(name);
16211 +
16212 + /* first look in vars[] */
16213 + for (s = vars; s && *s; ) {
16214 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
16215 + return (&s[len+1]);
16216 +
16217 + while (*s++)
16218 + ;
16219 + }
16220 +
16221 + /* then query nvram */
16222 + return (BCMINIT(nvram_get)(name));
16223 +}
16224 +
16225 +/*
16226 + * Search the vars for a specific one and return its value as
16227 + * an integer. Returns 0 if not found.
16228 + */
16229 +int
16230 +getintvar(char *vars, char *name)
16231 +{
16232 + char *val;
16233 +
16234 + if ((val = getvar(vars, name)) == NULL)
16235 + return (0);
16236 +
16237 + return (bcm_strtoul(val, NULL, 0));
16238 +}
16239 +
16240 +
16241 +/* Search for token in comma separated token-string */
16242 +static int
16243 +findmatch(char *string, char *name)
16244 +{
16245 + uint len;
16246 + char *c;
16247 +
16248 + len = strlen(name);
16249 + while ((c = strchr(string, ',')) != NULL) {
16250 + if (len == (uint)(c - string) && !strncmp(string, name, len))
16251 + return 1;
16252 + string = c + 1;
16253 + }
16254 +
16255 + return (!strcmp(string, name));
16256 +}
16257 +
16258 +/* Return gpio pin number assigned to the named pin */
16259 +/*
16260 +* Variable should be in format:
16261 +*
16262 +* gpio<N>=pin_name,pin_name
16263 +*
16264 +* This format allows multiple features to share the gpio with mutual
16265 +* understanding.
16266 +*
16267 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
16268 +* and if def_pin is not used by others.
16269 +*/
16270 +uint
16271 +getgpiopin(char *vars, char *pin_name, uint def_pin)
16272 +{
16273 + char name[] = "gpioXXXX";
16274 + char *val;
16275 + uint pin;
16276 +
16277 + /* Go thru all possibilities till a match in pin name */
16278 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
16279 + sprintf(name, "gpio%d", pin);
16280 + val = getvar(vars, name);
16281 + if (val && findmatch(val, pin_name))
16282 + return pin;
16283 + }
16284 +
16285 + if (def_pin != GPIO_PIN_NOTDEFINED) {
16286 + /* make sure the default pin is not used by someone else */
16287 + sprintf(name, "gpio%d", def_pin);
16288 + if (getvar(vars, name)) {
16289 + def_pin = GPIO_PIN_NOTDEFINED;
16290 + }
16291 + }
16292 +
16293 + return def_pin;
16294 +}
16295 +
16296 +
16297 +static char bcm_undeferrstr[BCME_STRLEN];
16298 +
16299 +static const char *bcmerrorstrtable[] = \
16300 +{ "OK", /* 0 */
16301 + "Undefined error", /* BCME_ERROR */
16302 + "Bad Argument", /* BCME_BADARG*/
16303 + "Bad Option", /* BCME_BADOPTION*/
16304 + "Not up", /* BCME_NOTUP */
16305 + "Not down", /* BCME_NOTDOWN */
16306 + "Not AP", /* BCME_NOTAP */
16307 + "Not STA", /* BCME_NOTSTA */
16308 + "Bad Key Index", /* BCME_BADKEYIDX */
16309 + "Radio Off", /* BCME_RADIOOFF */
16310 + "Not band locked", /* BCME_NOTBANDLOCKED */
16311 + "No clock", /* BCME_NOCLK */
16312 + "Bad Rate valueset", /* BCME_BADRATESET */
16313 + "Bad Band", /* BCME_BADBAND */
16314 + "Buffer too short", /* BCME_BUFTOOSHORT */
16315 + "Buffer too length", /* BCME_BUFTOOLONG */
16316 + "Busy", /* BCME_BUSY */
16317 + "Not Associated", /* BCME_NOTASSOCIATED */
16318 + "Bad SSID len", /* BCME_BADSSIDLEN */
16319 + "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
16320 + "Bad Channel", /* BCME_BADCHAN */
16321 + "Bad Address", /* BCME_BADADDR */
16322 + "Not Enough Resources", /* BCME_NORESOURCE */
16323 + "Unsupported", /* BCME_UNSUPPORTED */
16324 + "Bad length", /* BCME_BADLENGTH */
16325 + "Not Ready", /* BCME_NOTREADY */
16326 + "Not Permitted", /* BCME_EPERM */
16327 + "No Memory", /* BCME_NOMEM */
16328 + "Associated", /* BCME_ASSOCIATED */
16329 + "Not In Range", /* BCME_RANGE */
16330 + "Not Found" /* BCME_NOTFOUND */
16331 + };
16332 +
16333 +/* Convert the Error codes into related Error strings */
16334 +const char *
16335 +bcmerrorstr(int bcmerror)
16336 +{
16337 + int abs_bcmerror;
16338 +
16339 + abs_bcmerror = ABS(bcmerror);
16340 +
16341 + /* check if someone added a bcmerror code but forgot to add errorstring */
16342 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
16343 + if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
16344 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
16345 + return bcm_undeferrstr;
16346 + }
16347 +
16348 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
16349 +
16350 + return bcmerrorstrtable[abs_bcmerror];
16351 +}
16352 +#endif /* #ifdef BCMDRIVER */
16353 +
16354 +
16355 +/*******************************************************************************
16356 + * crc8
16357 + *
16358 + * Computes a crc8 over the input data using the polynomial:
16359 + *
16360 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
16361 + *
16362 + * The caller provides the initial value (either CRC8_INIT_VALUE
16363 + * or the previous returned value) to allow for processing of
16364 + * discontiguous blocks of data. When generating the CRC the
16365 + * caller is responsible for complementing the final return value
16366 + * and inserting it into the byte stream. When checking, a final
16367 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
16368 + *
16369 + * Reference: Dallas Semiconductor Application Note 27
16370 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16371 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16372 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16373 + *
16374 + ******************************************************************************/
16375 +
16376 +static uint8 crc8_table[256] = {
16377 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
16378 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
16379 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
16380 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
16381 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
16382 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
16383 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
16384 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
16385 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
16386 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
16387 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
16388 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
16389 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
16390 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
16391 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
16392 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
16393 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
16394 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
16395 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
16396 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
16397 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
16398 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
16399 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
16400 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
16401 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
16402 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
16403 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
16404 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
16405 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
16406 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
16407 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
16408 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
16409 +};
16410 +
16411 +#define CRC_INNER_LOOP(n, c, x) \
16412 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
16413 +
16414 +uint8
16415 +hndcrc8(
16416 + uint8 *pdata, /* pointer to array of data to process */
16417 + uint nbytes, /* number of input data bytes to process */
16418 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
16419 +)
16420 +{
16421 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
16422 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
16423 + while (nbytes-- > 0)
16424 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
16425 +
16426 + return crc;
16427 +}
16428 +
16429 +/*******************************************************************************
16430 + * crc16
16431 + *
16432 + * Computes a crc16 over the input data using the polynomial:
16433 + *
16434 + * x^16 + x^12 +x^5 + 1
16435 + *
16436 + * The caller provides the initial value (either CRC16_INIT_VALUE
16437 + * or the previous returned value) to allow for processing of
16438 + * discontiguous blocks of data. When generating the CRC the
16439 + * caller is responsible for complementing the final return value
16440 + * and inserting it into the byte stream. When checking, a final
16441 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
16442 + *
16443 + * Reference: Dallas Semiconductor Application Note 27
16444 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16445 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16446 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16447 + *
16448 + ******************************************************************************/
16449 +
16450 +static uint16 crc16_table[256] = {
16451 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
16452 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
16453 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
16454 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
16455 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
16456 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
16457 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
16458 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
16459 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
16460 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
16461 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
16462 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
16463 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
16464 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
16465 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
16466 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
16467 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
16468 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
16469 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
16470 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
16471 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
16472 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
16473 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
16474 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
16475 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
16476 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
16477 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
16478 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
16479 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
16480 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
16481 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
16482 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
16483 +};
16484 +
16485 +uint16
16486 +hndcrc16(
16487 + uint8 *pdata, /* pointer to array of data to process */
16488 + uint nbytes, /* number of input data bytes to process */
16489 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
16490 +)
16491 +{
16492 + while (nbytes-- > 0)
16493 + CRC_INNER_LOOP(16, crc, *pdata++);
16494 + return crc;
16495 +}
16496 +
16497 +static uint32 crc32_table[256] = {
16498 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
16499 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
16500 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
16501 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
16502 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
16503 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
16504 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
16505 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
16506 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
16507 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
16508 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
16509 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
16510 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
16511 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
16512 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
16513 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
16514 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
16515 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
16516 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
16517 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
16518 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
16519 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
16520 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
16521 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
16522 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
16523 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
16524 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
16525 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
16526 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
16527 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
16528 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
16529 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
16530 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
16531 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
16532 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
16533 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
16534 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
16535 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
16536 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
16537 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
16538 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
16539 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
16540 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
16541 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
16542 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
16543 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
16544 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
16545 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
16546 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
16547 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
16548 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
16549 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
16550 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
16551 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
16552 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
16553 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
16554 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
16555 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
16556 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
16557 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
16558 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
16559 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
16560 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
16561 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
16562 +};
16563 +
16564 +uint32
16565 +hndcrc32(
16566 + uint8 *pdata, /* pointer to array of data to process */
16567 + uint nbytes, /* number of input data bytes to process */
16568 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
16569 +)
16570 +{
16571 + uint8 *pend;
16572 +#ifdef __mips__
16573 + uint8 tmp[4];
16574 + ulong *tptr = (ulong *)tmp;
16575 +
16576 + /* in case the beginning of the buffer isn't aligned */
16577 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
16578 + nbytes -= (pend - pdata);
16579 + while (pdata < pend)
16580 + CRC_INNER_LOOP(32, crc, *pdata++);
16581 +
16582 + /* handle bulk of data as 32-bit words */
16583 + pend = pdata + (nbytes & 0xfffffffc);
16584 + while (pdata < pend) {
16585 + tptr = *((ulong *) pdata);
16586 + *((ulong *) pdata) += 1;
16587 + CRC_INNER_LOOP(32, crc, tmp[0]);
16588 + CRC_INNER_LOOP(32, crc, tmp[1]);
16589 + CRC_INNER_LOOP(32, crc, tmp[2]);
16590 + CRC_INNER_LOOP(32, crc, tmp[3]);
16591 + }
16592 +
16593 + /* 1-3 bytes at end of buffer */
16594 + pend = pdata + (nbytes & 0x03);
16595 + while (pdata < pend)
16596 + CRC_INNER_LOOP(32, crc, *pdata++);
16597 +#else
16598 + pend = pdata + nbytes;
16599 + while (pdata < pend)
16600 + CRC_INNER_LOOP(32, crc, *pdata++);
16601 +#endif
16602 +
16603 + return crc;
16604 +}
16605 +
16606 +#ifdef notdef
16607 +#define CLEN 1499
16608 +#define CBUFSIZ (CLEN+4)
16609 +#define CNBUFS 5
16610 +
16611 +void testcrc32(void)
16612 +{
16613 + uint j,k,l;
16614 + uint8 *buf;
16615 + uint len[CNBUFS];
16616 + uint32 crcr;
16617 + uint32 crc32tv[CNBUFS] =
16618 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
16619 +
16620 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
16621 +
16622 + /* step through all possible alignments */
16623 + for (l=0;l<=4;l++) {
16624 + for (j=0; j<CNBUFS; j++) {
16625 + len[j] = CLEN;
16626 + for (k=0; k<len[j]; k++)
16627 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
16628 + }
16629 +
16630 + for (j=0; j<CNBUFS; j++) {
16631 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
16632 + ASSERT(crcr == crc32tv[j]);
16633 + }
16634 + }
16635 +
16636 + MFREE(buf, CBUFSIZ*CNBUFS);
16637 + return;
16638 +}
16639 +#endif
16640 +
16641 +
16642 +/*
16643 + * Advance from the current 1-byte tag/1-byte length/variable-length value
16644 + * triple, to the next, returning a pointer to the next.
16645 + * If the current or next TLV is invalid (does not fit in given buffer length),
16646 + * NULL is returned.
16647 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
16648 + * by the TLV paramter's length if it is valid.
16649 + */
16650 +bcm_tlv_t *
16651 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
16652 +{
16653 + int len;
16654 +
16655 + /* validate current elt */
16656 + if (!bcm_valid_tlv(elt, *buflen))
16657 + return NULL;
16658 +
16659 + /* advance to next elt */
16660 + len = elt->len;
16661 + elt = (bcm_tlv_t*)(elt->data + len);
16662 + *buflen -= (2 + len);
16663 +
16664 + /* validate next elt */
16665 + if (!bcm_valid_tlv(elt, *buflen))
16666 + return NULL;
16667 +
16668 + return elt;
16669 +}
16670 +
16671 +/*
16672 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16673 + * triples, returning a pointer to the substring whose first element
16674 + * matches tag
16675 + */
16676 +bcm_tlv_t *
16677 +bcm_parse_tlvs(void *buf, int buflen, uint key)
16678 +{
16679 + bcm_tlv_t *elt;
16680 + int totlen;
16681 +
16682 + elt = (bcm_tlv_t*)buf;
16683 + totlen = buflen;
16684 +
16685 + /* find tagged parameter */
16686 + while (totlen >= 2) {
16687 + int len = elt->len;
16688 +
16689 + /* validate remaining totlen */
16690 + if ((elt->id == key) && (totlen >= (len + 2)))
16691 + return (elt);
16692 +
16693 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16694 + totlen -= (len + 2);
16695 + }
16696 +
16697 + return NULL;
16698 +}
16699 +
16700 +/*
16701 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16702 + * triples, returning a pointer to the substring whose first element
16703 + * matches tag. Stop parsing when we see an element whose ID is greater
16704 + * than the target key.
16705 + */
16706 +bcm_tlv_t *
16707 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
16708 +{
16709 + bcm_tlv_t *elt;
16710 + int totlen;
16711 +
16712 + elt = (bcm_tlv_t*)buf;
16713 + totlen = buflen;
16714 +
16715 + /* find tagged parameter */
16716 + while (totlen >= 2) {
16717 + uint id = elt->id;
16718 + int len = elt->len;
16719 +
16720 + /* Punt if we start seeing IDs > than target key */
16721 + if (id > key)
16722 + return(NULL);
16723 +
16724 + /* validate remaining totlen */
16725 + if ((id == key) && (totlen >= (len + 2)))
16726 + return (elt);
16727 +
16728 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16729 + totlen -= (len + 2);
16730 + }
16731 + return NULL;
16732 +}
16733 +/* routine to dump fields in a fileddesc structure */
16734 +
16735 +uint
16736 +bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
16737 +{
16738 + uint filled_len;
16739 + uint len;
16740 + struct fielddesc *cur_ptr;
16741 +
16742 + filled_len = 0;
16743 + cur_ptr = fielddesc_array;
16744 +
16745 + while (bufsize > (filled_len + 64)) {
16746 + if (cur_ptr->nameandfmt == NULL)
16747 + break;
16748 + len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
16749 + buf += len;
16750 + filled_len += len;
16751 + cur_ptr++;
16752 + }
16753 + return filled_len;
16754 +}
16755 +
16756 +uint
16757 +bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
16758 +{
16759 + uint len;
16760 +
16761 + len = strlen(name) + 1;
16762 +
16763 + if ((len + datalen) > buflen)
16764 + return 0;
16765 +
16766 + strcpy(buf, name);
16767 +
16768 + /* append data onto the end of the name string */
16769 + memcpy(&buf[len], data, datalen);
16770 + len += datalen;
16771 +
16772 + return len;
16773 +}
16774 +
16775 +/* Quarter dBm units to mW
16776 + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
16777 + * Table is offset so the last entry is largest mW value that fits in
16778 + * a uint16.
16779 + */
16780 +
16781 +#define QDBM_OFFSET 153
16782 +#define QDBM_TABLE_LEN 40
16783 +
16784 +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
16785 + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
16786 + */
16787 +#define QDBM_TABLE_LOW_BOUND 6493
16788 +
16789 +/* Largest mW value that will round down to the last table entry,
16790 + * QDBM_OFFSET + QDBM_TABLE_LEN-1.
16791 + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
16792 + */
16793 +#define QDBM_TABLE_HIGH_BOUND 64938
16794 +
16795 +static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
16796 +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
16797 +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
16798 +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
16799 +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
16800 +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
16801 +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
16802 +};
16803 +
16804 +uint16
16805 +bcm_qdbm_to_mw(uint8 qdbm)
16806 +{
16807 + uint factor = 1;
16808 + int idx = qdbm - QDBM_OFFSET;
16809 +
16810 + if (idx > QDBM_TABLE_LEN) {
16811 + /* clamp to max uint16 mW value */
16812 + return 0xFFFF;
16813 + }
16814 +
16815 + /* scale the qdBm index up to the range of the table 0-40
16816 + * where an offset of 40 qdBm equals a factor of 10 mW.
16817 + */
16818 + while (idx < 0) {
16819 + idx += 40;
16820 + factor *= 10;
16821 + }
16822 +
16823 + /* return the mW value scaled down to the correct factor of 10,
16824 + * adding in factor/2 to get proper rounding. */
16825 + return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
16826 +}
16827 +
16828 +uint8
16829 +bcm_mw_to_qdbm(uint16 mw)
16830 +{
16831 + uint8 qdbm;
16832 + int offset;
16833 + uint mw_uint = mw;
16834 + uint boundary;
16835 +
16836 + /* handle boundary case */
16837 + if (mw_uint <= 1)
16838 + return 0;
16839 +
16840 + offset = QDBM_OFFSET;
16841 +
16842 + /* move mw into the range of the table */
16843 + while (mw_uint < QDBM_TABLE_LOW_BOUND) {
16844 + mw_uint *= 10;
16845 + offset -= 40;
16846 + }
16847 +
16848 + for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
16849 + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
16850 + if (mw_uint < boundary) break;
16851 + }
16852 +
16853 + qdbm += (uint8)offset;
16854 +
16855 + return(qdbm);
16856 +}
16857 diff -urN linux.old/drivers/net/hnd/hnddma.c linux.dev/drivers/net/hnd/hnddma.c
16858 --- linux.old/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
16859 +++ linux.dev/drivers/net/hnd/hnddma.c 2005-11-08 16:07:38.846817500 +0100
16860 @@ -0,0 +1,1527 @@
16861 +/*
16862 + * Generic Broadcom Home Networking Division (HND) DMA module.
16863 + * This supports the following chips: BCM42xx, 44xx, 47xx .
16864 + *
16865 + * Copyright 2005, Broadcom Corporation
16866 + * All Rights Reserved.
16867 + *
16868 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16869 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16870 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16871 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16872 + *
16873 + * $Id$
16874 + */
16875 +
16876 +#include <typedefs.h>
16877 +#include <osl.h>
16878 +#include <bcmendian.h>
16879 +#include <sbconfig.h>
16880 +#include <bcmutils.h>
16881 +#include <bcmdevs.h>
16882 +#include <sbutils.h>
16883 +
16884 +struct dma_info; /* forward declaration */
16885 +#define di_t struct dma_info
16886 +
16887 +#include <sbhnddma.h>
16888 +#include <hnddma.h>
16889 +
16890 +/* debug/trace */
16891 +#define DMA_ERROR(args)
16892 +#define DMA_TRACE(args)
16893 +
16894 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
16895 +static uint dma_msg_level =
16896 + 0;
16897 +
16898 +#define MAXNAMEL 8
16899 +
16900 +/* dma engine software state */
16901 +typedef struct dma_info {
16902 + hnddma_t hnddma; /* exported structure */
16903 + uint *msg_level; /* message level pointer */
16904 + char name[MAXNAMEL]; /* callers name for diag msgs */
16905 +
16906 + void *osh; /* os handle */
16907 + sb_t *sbh; /* sb handle */
16908 +
16909 + bool dma64; /* dma64 enabled */
16910 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
16911 +
16912 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
16913 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
16914 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
16915 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
16916 +
16917 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
16918 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
16919 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
16920 + uint ntxd; /* # tx descriptors tunable */
16921 + uint txin; /* index of next descriptor to reclaim */
16922 + uint txout; /* index of next descriptor to post */
16923 + uint txavail; /* # free tx descriptors */
16924 + void **txp; /* pointer to parallel array of pointers to packets */
16925 + ulong txdpa; /* physical address of descriptor ring */
16926 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
16927 + uint txdalloc; /* #bytes allocated for the ring */
16928 +
16929 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
16930 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
16931 + uint nrxd; /* # rx descriptors tunable */
16932 + uint rxin; /* index of next descriptor to reclaim */
16933 + uint rxout; /* index of next descriptor to post */
16934 + void **rxp; /* pointer to parallel array of pointers to packets */
16935 + ulong rxdpa; /* physical address of descriptor ring */
16936 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
16937 + uint rxdalloc; /* #bytes allocated for the ring */
16938 +
16939 + /* tunables */
16940 + uint rxbufsize; /* rx buffer size in bytes */
16941 + uint nrxpost; /* # rx buffers to keep posted */
16942 + uint rxoffset; /* rxcontrol offset */
16943 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
16944 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
16945 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
16946 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
16947 +} dma_info_t;
16948 +
16949 +#ifdef BCMDMA64
16950 +#define DMA64_ENAB(di) ((di)->dma64)
16951 +#else
16952 +#define DMA64_ENAB(di) (0)
16953 +#endif
16954 +
16955 +/* descriptor bumping macros */
16956 +#define XXD(x, n) ((x) & ((n) - 1))
16957 +#define TXD(x) XXD((x), di->ntxd)
16958 +#define RXD(x) XXD((x), di->nrxd)
16959 +#define NEXTTXD(i) TXD(i + 1)
16960 +#define PREVTXD(i) TXD(i - 1)
16961 +#define NEXTRXD(i) RXD(i + 1)
16962 +#define NTXDACTIVE(h, t) TXD(t - h)
16963 +#define NRXDACTIVE(h, t) RXD(t - h)
16964 +
16965 +/* macros to convert between byte offsets and indexes */
16966 +#define B2I(bytes, type) ((bytes) / sizeof(type))
16967 +#define I2B(index, type) ((index) * sizeof(type))
16968 +
16969 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
16970 +#define PCI32ADDR_HIGH_SHIFT 30
16971 +
16972 +
16973 +/* prototypes */
16974 +static bool dma_isaddrext(dma_info_t *di);
16975 +static bool dma_alloc(dma_info_t *di, uint direction);
16976 +
16977 +static bool dma32_alloc(dma_info_t *di, uint direction);
16978 +static void dma32_txreset(dma_info_t *di);
16979 +static void dma32_rxreset(dma_info_t *di);
16980 +static bool dma32_txsuspendedidle(dma_info_t *di);
16981 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16982 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
16983 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
16984 +static void dma32_txrotate(di_t *di);
16985 +
16986 +/* prototype or stubs */
16987 +#ifdef BCMDMA64
16988 +static bool dma64_alloc(dma_info_t *di, uint direction);
16989 +static void dma64_txreset(dma_info_t *di);
16990 +static void dma64_rxreset(dma_info_t *di);
16991 +static bool dma64_txsuspendedidle(dma_info_t *di);
16992 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16993 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
16994 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
16995 +static void dma64_txrotate(di_t *di);
16996 +#else
16997 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
16998 +static void dma64_txreset(dma_info_t *di) {}
16999 +static void dma64_rxreset(dma_info_t *di) {}
17000 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
17001 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
17002 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
17003 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
17004 +static void dma64_txrotate(di_t *di) { return; }
17005 +#endif
17006 +
17007 +/* old dmaregs struct for compatibility */
17008 +typedef volatile struct {
17009 + /* transmit channel */
17010 + uint32 xmtcontrol; /* enable, et al */
17011 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
17012 + uint32 xmtptr; /* last descriptor posted to chip */
17013 + uint32 xmtstatus; /* current active descriptor, et al */
17014 +
17015 + /* receive channel */
17016 + uint32 rcvcontrol; /* enable, et al */
17017 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
17018 + uint32 rcvptr; /* last descriptor posted to chip */
17019 + uint32 rcvstatus; /* current active descriptor, et al */
17020 +} dmaregs_t;
17021 +
17022 +typedef struct {
17023 + uint ddoffset;
17024 + uint dataoffset;
17025 +} compat_data;
17026 +
17027 +static compat_data *ugly_hack = NULL;
17028 +
17029 +void*
17030 +dma_attold(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
17031 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
17032 +{
17033 + dma32regs_t *dtx = regs;
17034 + dma32regs_t *drx = dtx + 1;
17035 +
17036 + ugly_hack = kmalloc(sizeof(ugly_hack), GFP_KERNEL);
17037 + ugly_hack->ddoffset = ddoffset;
17038 + ugly_hack->dataoffset = dataoffset;
17039 + dma_attach((osl_t *) osh, name, NULL, dtx, drx, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, msg_level);
17040 + ugly_hack = NULL;
17041 +}
17042 +
17043 +
17044 +void*
17045 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
17046 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
17047 +{
17048 + dma_info_t *di;
17049 + uint size;
17050 +
17051 + /* allocate private info structure */
17052 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
17053 + return (NULL);
17054 + }
17055 + bzero((char*)di, sizeof (dma_info_t));
17056 +
17057 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
17058 +
17059 + if (sbh != NULL)
17060 + di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
17061 +
17062 +#ifndef BCMDMA64
17063 + if (di->dma64) {
17064 + DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
17065 + goto fail;
17066 + }
17067 +#endif
17068 +
17069 + /* check arguments */
17070 + ASSERT(ISPOWEROF2(ntxd));
17071 + ASSERT(ISPOWEROF2(nrxd));
17072 + if (nrxd == 0)
17073 + ASSERT(dmaregsrx == NULL);
17074 + if (ntxd == 0)
17075 + ASSERT(dmaregstx == NULL);
17076 +
17077 +
17078 + /* init dma reg pointer */
17079 + if (di->dma64) {
17080 + ASSERT(ntxd <= D64MAXDD);
17081 + ASSERT(nrxd <= D64MAXDD);
17082 + di->d64txregs = (dma64regs_t *)dmaregstx;
17083 + di->d64rxregs = (dma64regs_t *)dmaregsrx;
17084 +
17085 + di->dma64align = D64RINGALIGN;
17086 + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
17087 + /* for smaller dd table, HW relax the alignment requirement */
17088 + di->dma64align = D64RINGALIGN / 2;
17089 + }
17090 + } else {
17091 + ASSERT(ntxd <= D32MAXDD);
17092 + ASSERT(nrxd <= D32MAXDD);
17093 + di->d32txregs = (dma32regs_t *)dmaregstx;
17094 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
17095 + }
17096 +
17097 +
17098 + /* make a private copy of our callers name */
17099 + strncpy(di->name, name, MAXNAMEL);
17100 + di->name[MAXNAMEL-1] = '\0';
17101 +
17102 + di->osh = osh;
17103 + di->sbh = sbh;
17104 +
17105 + /* save tunables */
17106 + di->ntxd = ntxd;
17107 + di->nrxd = nrxd;
17108 + di->rxbufsize = rxbufsize;
17109 + di->nrxpost = nrxpost;
17110 + di->rxoffset = rxoffset;
17111 +
17112 + /*
17113 + * figure out the DMA physical address offset for dd and data
17114 + * for old chips w/o sb, use zero
17115 + * for new chips w sb,
17116 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
17117 + * Other bus: use zero
17118 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
17119 + */
17120 + di->ddoffsetlow = 0;
17121 + di->dataoffsetlow = 0;
17122 + if (ugly_hack != NULL) {
17123 + di->ddoffsetlow = ugly_hack->ddoffset;
17124 + di->dataoffsetlow = ugly_hack->dataoffset;
17125 + di->ddoffsethigh = 0;
17126 + di->dataoffsethigh = 0;
17127 + } else if (sbh != NULL) {
17128 + if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
17129 + if ((sbh->buscoretype == SB_PCIE) && di->dma64){
17130 + di->ddoffsetlow = 0;
17131 + di->ddoffsethigh = SB_PCIE_DMA_H32;
17132 + } else {
17133 + di->ddoffsetlow = SB_PCI_DMA;
17134 + di->ddoffsethigh = 0;
17135 + }
17136 + di->dataoffsetlow = di->ddoffsetlow;
17137 + di->dataoffsethigh = di->ddoffsethigh;
17138 + }
17139 +#if defined(__mips__) && defined(IL_BIGENDIAN)
17140 + /* use sdram swapped region for data buffers but not dma descriptors */
17141 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
17142 +#endif
17143 + }
17144 +
17145 + di->addrext = ((ugly_hack == NULL) ? dma_isaddrext(di) : 0);
17146 +
17147 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
17148 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
17149 +
17150 + /* allocate tx packet pointer vector */
17151 + if (ntxd) {
17152 + size = ntxd * sizeof (void*);
17153 + if ((di->txp = MALLOC(osh, size)) == NULL) {
17154 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17155 + goto fail;
17156 + }
17157 + bzero((char*)di->txp, size);
17158 + }
17159 +
17160 + /* allocate rx packet pointer vector */
17161 + if (nrxd) {
17162 + size = nrxd * sizeof (void*);
17163 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
17164 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17165 + goto fail;
17166 + }
17167 + bzero((char*)di->rxp, size);
17168 + }
17169 +
17170 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
17171 + if (ntxd) {
17172 + if (!dma_alloc(di, DMA_TX))
17173 + goto fail;
17174 + }
17175 +
17176 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
17177 + if (nrxd) {
17178 + if (!dma_alloc(di, DMA_RX))
17179 + goto fail;
17180 + }
17181 +
17182 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17183 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
17184 + goto fail;
17185 + }
17186 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17187 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
17188 + goto fail;
17189 + }
17190 +
17191 + return ((void*)di);
17192 +
17193 +fail:
17194 + dma_detach((void*)di);
17195 + return (NULL);
17196 +}
17197 +
17198 +static bool
17199 +dma_alloc(dma_info_t *di, uint direction)
17200 +{
17201 + if (DMA64_ENAB(di)) {
17202 + return dma64_alloc(di, direction);
17203 + } else {
17204 + return dma32_alloc(di, direction);
17205 + }
17206 +}
17207 +
17208 +/* may be called with core in reset */
17209 +void
17210 +dma_detach(dma_info_t *di)
17211 +{
17212 + if (di == NULL)
17213 + return;
17214 +
17215 + DMA_TRACE(("%s: dma_detach\n", di->name));
17216 +
17217 + /* shouldn't be here if descriptors are unreclaimed */
17218 + ASSERT(di->txin == di->txout);
17219 + ASSERT(di->rxin == di->rxout);
17220 +
17221 + /* free dma descriptor rings */
17222 + if (di->txd32)
17223 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
17224 + if (di->rxd32)
17225 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
17226 +
17227 + /* free packet pointer vectors */
17228 + if (di->txp)
17229 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
17230 + if (di->rxp)
17231 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
17232 +
17233 + /* free our private info structure */
17234 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
17235 +}
17236 +
17237 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
17238 +static bool
17239 +dma_isaddrext(dma_info_t *di)
17240 +{
17241 + uint32 w;
17242 +
17243 + if (DMA64_ENAB(di)) {
17244 + OR_REG(&di->d64txregs->control, D64_XC_AE);
17245 + w = R_REG(&di->d32txregs->control);
17246 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
17247 + return ((w & XC_AE) == D64_XC_AE);
17248 + } else {
17249 + OR_REG(&di->d32txregs->control, XC_AE);
17250 + w = R_REG(&di->d32txregs->control);
17251 + AND_REG(&di->d32txregs->control, ~XC_AE);
17252 + return ((w & XC_AE) == XC_AE);
17253 + }
17254 +}
17255 +
17256 +void
17257 +dma_txreset(dma_info_t *di)
17258 +{
17259 + DMA_TRACE(("%s: dma_txreset\n", di->name));
17260 +
17261 + if (DMA64_ENAB(di))
17262 + dma64_txreset(di);
17263 + else
17264 + dma32_txreset(di);
17265 +}
17266 +
17267 +void
17268 +dma_rxreset(dma_info_t *di)
17269 +{
17270 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
17271 +
17272 + if (DMA64_ENAB(di))
17273 + dma64_rxreset(di);
17274 + else
17275 + dma32_rxreset(di);
17276 +}
17277 +
17278 +/* initialize descriptor table base address */
17279 +static void
17280 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
17281 +{
17282 + if (DMA64_ENAB(di)) {
17283 + if (direction == DMA_TX) {
17284 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
17285 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
17286 + } else {
17287 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
17288 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
17289 + }
17290 + } else {
17291 + uint32 offset = di->ddoffsetlow;
17292 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17293 + if (direction == DMA_TX)
17294 + W_REG(&di->d32txregs->addr, (pa + offset));
17295 + else
17296 + W_REG(&di->d32rxregs->addr, (pa + offset));
17297 + } else {
17298 + /* dma32 address extension */
17299 + uint32 ae;
17300 + ASSERT(di->addrext);
17301 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17302 +
17303 + if (direction == DMA_TX) {
17304 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17305 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
17306 + } else {
17307 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17308 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
17309 + }
17310 + }
17311 + }
17312 +}
17313 +
17314 +/* init the tx or rx descriptor */
17315 +static INLINE void
17316 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
17317 +{
17318 + uint offset = di->dataoffsetlow;
17319 +
17320 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17321 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
17322 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17323 + } else {
17324 + /* address extension */
17325 + uint32 ae;
17326 + ASSERT(di->addrext);
17327 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17328 +
17329 + *ctrl |= (ae << CTRL_AE_SHIFT);
17330 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
17331 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17332 + }
17333 +}
17334 +
17335 +/* init the tx or rx descriptor */
17336 +static INLINE void
17337 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
17338 +{
17339 + uint32 bufaddr_low = pa + di->dataoffsetlow;
17340 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
17341 +
17342 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
17343 +
17344 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
17345 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
17346 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
17347 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
17348 +}
17349 +
17350 +void
17351 +dma_txinit(dma_info_t *di)
17352 +{
17353 + DMA_TRACE(("%s: dma_txinit\n", di->name));
17354 +
17355 + di->txin = di->txout = 0;
17356 + di->txavail = di->ntxd - 1;
17357 +
17358 + /* clear tx descriptor ring */
17359 + if (DMA64_ENAB(di)) {
17360 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
17361 + W_REG(&di->d64txregs->control, XC_XE);
17362 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17363 + } else {
17364 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
17365 + W_REG(&di->d32txregs->control, XC_XE);
17366 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17367 + }
17368 +}
17369 +
17370 +bool
17371 +dma_txenabled(dma_info_t *di)
17372 +{
17373 + uint32 xc;
17374 +
17375 + /* If the chip is dead, it is not enabled :-) */
17376 + if (DMA64_ENAB(di)) {
17377 + xc = R_REG(&di->d64txregs->control);
17378 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
17379 + } else {
17380 + xc = R_REG(&di->d32txregs->control);
17381 + return ((xc != 0xffffffff) && (xc & XC_XE));
17382 + }
17383 +}
17384 +
17385 +void
17386 +dma_txsuspend(dma_info_t *di)
17387 +{
17388 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
17389 + if (DMA64_ENAB(di))
17390 + OR_REG(&di->d64txregs->control, D64_XC_SE);
17391 + else
17392 + OR_REG(&di->d32txregs->control, XC_SE);
17393 +}
17394 +
17395 +void
17396 +dma_txresume(dma_info_t *di)
17397 +{
17398 + DMA_TRACE(("%s: dma_txresume\n", di->name));
17399 + if (DMA64_ENAB(di))
17400 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
17401 + else
17402 + AND_REG(&di->d32txregs->control, ~XC_SE);
17403 +}
17404 +
17405 +bool
17406 +dma_txsuspendedidle(dma_info_t *di)
17407 +{
17408 + if (DMA64_ENAB(di))
17409 + return dma64_txsuspendedidle(di);
17410 + else
17411 + return dma32_txsuspendedidle(di);
17412 +}
17413 +
17414 +bool
17415 +dma_txsuspended(dma_info_t *di)
17416 +{
17417 + if (DMA64_ENAB(di))
17418 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
17419 + else
17420 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
17421 +}
17422 +
17423 +bool
17424 +dma_txstopped(dma_info_t *di)
17425 +{
17426 + if (DMA64_ENAB(di))
17427 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
17428 + else
17429 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
17430 +}
17431 +
17432 +bool
17433 +dma_rxstopped(dma_info_t *di)
17434 +{
17435 + if (DMA64_ENAB(di))
17436 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
17437 + else
17438 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
17439 +}
17440 +
17441 +void
17442 +dma_fifoloopbackenable(dma_info_t *di)
17443 +{
17444 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
17445 + if (DMA64_ENAB(di))
17446 + OR_REG(&di->d64txregs->control, D64_XC_LE);
17447 + else
17448 + OR_REG(&di->d32txregs->control, XC_LE);
17449 +}
17450 +
17451 +void
17452 +dma_rxinit(dma_info_t *di)
17453 +{
17454 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
17455 +
17456 + di->rxin = di->rxout = 0;
17457 +
17458 + /* clear rx descriptor ring */
17459 + if (DMA64_ENAB(di)) {
17460 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
17461 + dma_rxenable(di);
17462 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17463 + } else {
17464 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
17465 + dma_rxenable(di);
17466 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17467 + }
17468 +}
17469 +
17470 +void
17471 +dma_rxenable(dma_info_t *di)
17472 +{
17473 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
17474 + if (DMA64_ENAB(di))
17475 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
17476 + else
17477 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
17478 +}
17479 +
17480 +bool
17481 +dma_rxenabled(dma_info_t *di)
17482 +{
17483 + uint32 rc;
17484 +
17485 + if (DMA64_ENAB(di)) {
17486 + rc = R_REG(&di->d64rxregs->control);
17487 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
17488 + } else {
17489 + rc = R_REG(&di->d32rxregs->control);
17490 + return ((rc != 0xffffffff) && (rc & RC_RE));
17491 + }
17492 +}
17493 +
17494 +
17495 +/* !! tx entry routine */
17496 +int
17497 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17498 +{
17499 + if (DMA64_ENAB(di)) {
17500 + return dma64_txfast(di, p0, coreflags);
17501 + } else {
17502 + return dma32_txfast(di, p0, coreflags);
17503 + }
17504 +}
17505 +
17506 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
17507 +void*
17508 +dma_rx(dma_info_t *di)
17509 +{
17510 + void *p;
17511 + uint len;
17512 + int skiplen = 0;
17513 +
17514 + while ((p = dma_getnextrxp(di, FALSE))) {
17515 + /* skip giant packets which span multiple rx descriptors */
17516 + if (skiplen > 0) {
17517 + skiplen -= di->rxbufsize;
17518 + if (skiplen < 0)
17519 + skiplen = 0;
17520 + PKTFREE(di->osh, p, FALSE);
17521 + continue;
17522 + }
17523 +
17524 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
17525 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
17526 +
17527 + /* bad frame length check */
17528 + if (len > (di->rxbufsize - di->rxoffset)) {
17529 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
17530 + if (len > 0)
17531 + skiplen = len - (di->rxbufsize - di->rxoffset);
17532 + PKTFREE(di->osh, p, FALSE);
17533 + di->hnddma.rxgiants++;
17534 + continue;
17535 + }
17536 +
17537 + /* set actual length */
17538 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
17539 +
17540 + break;
17541 + }
17542 +
17543 + return (p);
17544 +}
17545 +
17546 +/* post receive buffers */
17547 +void
17548 +dma_rxfill(dma_info_t *di)
17549 +{
17550 + void *p;
17551 + uint rxin, rxout;
17552 + uint32 ctrl;
17553 + uint n;
17554 + uint i;
17555 + uint32 pa;
17556 + uint rxbufsize;
17557 +
17558 + /*
17559 + * Determine how many receive buffers we're lacking
17560 + * from the full complement, allocate, initialize,
17561 + * and post them, then update the chip rx lastdscr.
17562 + */
17563 +
17564 + rxin = di->rxin;
17565 + rxout = di->rxout;
17566 + rxbufsize = di->rxbufsize;
17567 +
17568 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
17569 +
17570 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
17571 +
17572 + for (i = 0; i < n; i++) {
17573 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
17574 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
17575 + di->hnddma.rxnobuf++;
17576 + break;
17577 + }
17578 +
17579 + /* Do a cached write instead of uncached write since DMA_MAP
17580 + * will flush the cache. */
17581 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
17582 +
17583 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
17584 + ASSERT(ISALIGNED(pa, 4));
17585 +
17586 + /* save the free packet pointer */
17587 + ASSERT(di->rxp[rxout] == NULL);
17588 + di->rxp[rxout] = p;
17589 +
17590 + if (DMA64_ENAB(di)) {
17591 + /* prep the descriptor control value */
17592 + if (rxout == (di->nrxd - 1))
17593 + ctrl = CTRL_EOT;
17594 +
17595 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
17596 + } else {
17597 + /* prep the descriptor control value */
17598 + ctrl = rxbufsize;
17599 + if (rxout == (di->nrxd - 1))
17600 + ctrl |= CTRL_EOT;
17601 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
17602 + }
17603 +
17604 + rxout = NEXTRXD(rxout);
17605 + }
17606 +
17607 + di->rxout = rxout;
17608 +
17609 + /* update the chip lastdscr pointer */
17610 + if (DMA64_ENAB(di)) {
17611 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
17612 + } else {
17613 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
17614 + }
17615 +}
17616 +
17617 +void
17618 +dma_txreclaim(dma_info_t *di, bool forceall)
17619 +{
17620 + void *p;
17621 +
17622 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
17623 +
17624 + while ((p = dma_getnexttxp(di, forceall)))
17625 + PKTFREE(di->osh, p, TRUE);
17626 +}
17627 +
17628 +/*
17629 + * Reclaim next completed txd (txds if using chained buffers) and
17630 + * return associated packet.
17631 + * If 'force' is true, reclaim txd(s) and return associated packet
17632 + * regardless of the value of the hardware "curr" pointer.
17633 + */
17634 +void*
17635 +dma_getnexttxp(dma_info_t *di, bool forceall)
17636 +{
17637 + if (DMA64_ENAB(di)) {
17638 + return dma64_getnexttxp(di, forceall);
17639 + } else {
17640 + return dma32_getnexttxp(di, forceall);
17641 + }
17642 +}
17643 +
17644 +/* like getnexttxp but no reclaim */
17645 +void*
17646 +dma_peeknexttxp(dma_info_t *di)
17647 +{
17648 + uint end, i;
17649 +
17650 + if (DMA64_ENAB(di)) {
17651 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
17652 + } else {
17653 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17654 + }
17655 +
17656 + for (i = di->txin; i != end; i = NEXTTXD(i))
17657 + if (di->txp[i])
17658 + return (di->txp[i]);
17659 +
17660 + return (NULL);
17661 +}
17662 +
17663 +/*
17664 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
17665 + */
17666 +void
17667 +dma_txrotate(di_t *di)
17668 +{
17669 + if (DMA64_ENAB(di)) {
17670 + dma64_txrotate(di);
17671 + } else {
17672 + dma32_txrotate(di);
17673 + }
17674 +}
17675 +
17676 +void
17677 +dma_rxreclaim(dma_info_t *di)
17678 +{
17679 + void *p;
17680 +
17681 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
17682 +
17683 + while ((p = dma_getnextrxp(di, TRUE)))
17684 + PKTFREE(di->osh, p, FALSE);
17685 +}
17686 +
17687 +void *
17688 +dma_getnextrxp(dma_info_t *di, bool forceall)
17689 +{
17690 + if (DMA64_ENAB(di)) {
17691 + return dma64_getnextrxp(di, forceall);
17692 + } else {
17693 + return dma32_getnextrxp(di, forceall);
17694 + }
17695 +}
17696 +
17697 +uintptr
17698 +dma_getvar(dma_info_t *di, char *name)
17699 +{
17700 + if (!strcmp(name, "&txavail"))
17701 + return ((uintptr) &di->txavail);
17702 + else {
17703 + ASSERT(0);
17704 + }
17705 + return (0);
17706 +}
17707 +
17708 +void
17709 +dma_txblock(dma_info_t *di)
17710 +{
17711 + di->txavail = 0;
17712 +}
17713 +
17714 +void
17715 +dma_txunblock(dma_info_t *di)
17716 +{
17717 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17718 +}
17719 +
17720 +uint
17721 +dma_txactive(dma_info_t *di)
17722 +{
17723 + return (NTXDACTIVE(di->txin, di->txout));
17724 +}
17725 +
17726 +void
17727 +dma_rxpiomode(dma32regs_t *regs)
17728 +{
17729 + W_REG(&regs->control, RC_FM);
17730 +}
17731 +
17732 +void
17733 +dma_txpioloopback(dma32regs_t *regs)
17734 +{
17735 + OR_REG(&regs->control, XC_LE);
17736 +}
17737 +
17738 +
17739 +
17740 +
17741 +/*** 32 bits DMA non-inline functions ***/
17742 +static bool
17743 +dma32_alloc(dma_info_t *di, uint direction)
17744 +{
17745 + uint size;
17746 + uint ddlen;
17747 + void *va;
17748 +
17749 + ddlen = sizeof (dma32dd_t);
17750 +
17751 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17752 +
17753 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
17754 + size += D32RINGALIGN;
17755 +
17756 +
17757 + if (direction == DMA_TX) {
17758 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17759 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17760 + return FALSE;
17761 + }
17762 +
17763 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17764 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
17765 + di->txdpa += di->txdalign;
17766 + di->txdalloc = size;
17767 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
17768 + } else {
17769 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17770 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17771 + return FALSE;
17772 + }
17773 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17774 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
17775 + di->rxdpa += di->rxdalign;
17776 + di->rxdalloc = size;
17777 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
17778 + }
17779 +
17780 + return TRUE;
17781 +}
17782 +
17783 +static void
17784 +dma32_txreset(dma_info_t *di)
17785 +{
17786 + uint32 status;
17787 +
17788 + /* suspend tx DMA first */
17789 + W_REG(&di->d32txregs->control, XC_SE);
17790 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
17791 + status != XS_XS_IDLE &&
17792 + status != XS_XS_STOPPED,
17793 + 10000);
17794 +
17795 + W_REG(&di->d32txregs->control, 0);
17796 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
17797 + 10000);
17798 +
17799 + if (status != XS_XS_DISABLED) {
17800 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17801 + }
17802 +
17803 + /* wait for the last transaction to complete */
17804 + OSL_DELAY(300);
17805 +}
17806 +
17807 +static void
17808 +dma32_rxreset(dma_info_t *di)
17809 +{
17810 + uint32 status;
17811 +
17812 + W_REG(&di->d32rxregs->control, 0);
17813 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
17814 + 10000);
17815 +
17816 + if (status != RS_RS_DISABLED) {
17817 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17818 + }
17819 +}
17820 +
17821 +static bool
17822 +dma32_txsuspendedidle(dma_info_t *di)
17823 +{
17824 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
17825 + return 0;
17826 +
17827 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
17828 + return 0;
17829 +
17830 + OSL_DELAY(2);
17831 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
17832 +}
17833 +
17834 +/*
17835 + * supports full 32bit dma engine buffer addressing so
17836 + * dma buffers can cross 4 Kbyte page boundaries.
17837 + */
17838 +static int
17839 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17840 +{
17841 + void *p, *next;
17842 + uchar *data;
17843 + uint len;
17844 + uint txout;
17845 + uint32 ctrl;
17846 + uint32 pa;
17847 +
17848 + DMA_TRACE(("%s: dma_txfast\n", di->name));
17849 +
17850 + txout = di->txout;
17851 + ctrl = 0;
17852 +
17853 + /*
17854 + * Walk the chain of packet buffers
17855 + * allocating and initializing transmit descriptor entries.
17856 + */
17857 + for (p = p0; p; p = next) {
17858 + data = PKTDATA(di->osh, p);
17859 + len = PKTLEN(di->osh, p);
17860 + next = PKTNEXT(di->osh, p);
17861 +
17862 + /* return nonzero if out of tx descriptors */
17863 + if (NEXTTXD(txout) == di->txin)
17864 + goto outoftxd;
17865 +
17866 + if (len == 0)
17867 + continue;
17868 +
17869 + /* get physical address of buffer start */
17870 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
17871 +
17872 + /* build the descriptor control value */
17873 + ctrl = len & CTRL_BC_MASK;
17874 +
17875 + ctrl |= coreflags;
17876 +
17877 + if (p == p0)
17878 + ctrl |= CTRL_SOF;
17879 + if (next == NULL)
17880 + ctrl |= (CTRL_IOC | CTRL_EOF);
17881 + if (txout == (di->ntxd - 1))
17882 + ctrl |= CTRL_EOT;
17883 +
17884 + if (DMA64_ENAB(di)) {
17885 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
17886 + } else {
17887 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
17888 + }
17889 +
17890 + ASSERT(di->txp[txout] == NULL);
17891 +
17892 + txout = NEXTTXD(txout);
17893 + }
17894 +
17895 + /* if last txd eof not set, fix it */
17896 + if (!(ctrl & CTRL_EOF))
17897 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
17898 +
17899 + /* save the packet */
17900 + di->txp[PREVTXD(txout)] = p0;
17901 +
17902 + /* bump the tx descriptor index */
17903 + di->txout = txout;
17904 +
17905 + /* kick the chip */
17906 + if (DMA64_ENAB(di)) {
17907 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
17908 + } else {
17909 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
17910 + }
17911 +
17912 + /* tx flow control */
17913 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17914 +
17915 + return (0);
17916 +
17917 + outoftxd:
17918 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
17919 + PKTFREE(di->osh, p0, TRUE);
17920 + di->txavail = 0;
17921 + di->hnddma.txnobuf++;
17922 + return (-1);
17923 +}
17924 +
17925 +static void*
17926 +dma32_getnexttxp(dma_info_t *di, bool forceall)
17927 +{
17928 + uint start, end, i;
17929 + void *txp;
17930 +
17931 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
17932 +
17933 + txp = NULL;
17934 +
17935 + start = di->txin;
17936 + if (forceall)
17937 + end = di->txout;
17938 + else
17939 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17940 +
17941 + if ((start == 0) && (end > di->txout))
17942 + goto bogus;
17943 +
17944 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
17945 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
17946 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
17947 +
17948 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
17949 + txp = di->txp[i];
17950 + di->txp[i] = NULL;
17951 + }
17952 +
17953 + di->txin = i;
17954 +
17955 + /* tx flow control */
17956 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17957 +
17958 + return (txp);
17959 +
17960 +bogus:
17961 +/*
17962 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
17963 + start, end, di->txout, forceall));
17964 +*/
17965 + return (NULL);
17966 +}
17967 +
17968 +static void *
17969 +dma32_getnextrxp(dma_info_t *di, bool forceall)
17970 +{
17971 + uint i;
17972 + void *rxp;
17973 +
17974 + /* if forcing, dma engine must be disabled */
17975 + ASSERT(!forceall || !dma_rxenabled(di));
17976 +
17977 + i = di->rxin;
17978 +
17979 + /* return if no packets posted */
17980 + if (i == di->rxout)
17981 + return (NULL);
17982 +
17983 + /* ignore curr if forceall */
17984 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
17985 + return (NULL);
17986 +
17987 + /* get the packet pointer that corresponds to the rx descriptor */
17988 + rxp = di->rxp[i];
17989 + ASSERT(rxp);
17990 + di->rxp[i] = NULL;
17991 +
17992 + /* clear this packet from the descriptor ring */
17993 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
17994 + di->rxbufsize, DMA_RX, rxp);
17995 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
17996 +
17997 + di->rxin = NEXTRXD(i);
17998 +
17999 + return (rxp);
18000 +}
18001 +
18002 +static void
18003 +dma32_txrotate(di_t *di)
18004 +{
18005 + uint ad;
18006 + uint nactive;
18007 + uint rot;
18008 + uint old, new;
18009 + uint32 w;
18010 + uint first, last;
18011 +
18012 + ASSERT(dma_txsuspendedidle(di));
18013 +
18014 + nactive = dma_txactive(di);
18015 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
18016 + rot = TXD(ad - di->txin);
18017 +
18018 + ASSERT(rot < di->ntxd);
18019 +
18020 + /* full-ring case is a lot harder - don't worry about this */
18021 + if (rot >= (di->ntxd - nactive)) {
18022 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18023 + return;
18024 + }
18025 +
18026 + first = di->txin;
18027 + last = PREVTXD(di->txout);
18028 +
18029 + /* move entries starting at last and moving backwards to first */
18030 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18031 + new = TXD(old + rot);
18032 +
18033 + /*
18034 + * Move the tx dma descriptor.
18035 + * EOT is set only in the last entry in the ring.
18036 + */
18037 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
18038 + if (new == (di->ntxd - 1))
18039 + w |= CTRL_EOT;
18040 + W_SM(&di->txd32[new].ctrl, w);
18041 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
18042 +
18043 + /* zap the old tx dma descriptor address field */
18044 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
18045 +
18046 + /* move the corresponding txp[] entry */
18047 + ASSERT(di->txp[new] == NULL);
18048 + di->txp[new] = di->txp[old];
18049 + di->txp[old] = NULL;
18050 + }
18051 +
18052 + /* update txin and txout */
18053 + di->txin = ad;
18054 + di->txout = TXD(di->txout + rot);
18055 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18056 +
18057 + /* kick the chip */
18058 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
18059 +}
18060 +
18061 +/*** 64 bits DMA non-inline functions ***/
18062 +
18063 +#ifdef BCMDMA64
18064 +
18065 +static bool
18066 +dma64_alloc(dma_info_t *di, uint direction)
18067 +{
18068 + uint size;
18069 + uint ddlen;
18070 + uint32 alignbytes;
18071 + void *va;
18072 +
18073 + ddlen = sizeof (dma64dd_t);
18074 +
18075 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
18076 +
18077 + alignbytes = di->dma64align;
18078 +
18079 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
18080 + size += alignbytes;
18081 +
18082 +
18083 + if (direction == DMA_TX) {
18084 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
18085 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
18086 + return FALSE;
18087 + }
18088 +
18089 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18090 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
18091 + di->txdpa += di->txdalign;
18092 + di->txdalloc = size;
18093 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
18094 + } else {
18095 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
18096 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
18097 + return FALSE;
18098 + }
18099 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18100 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
18101 + di->rxdpa += di->rxdalign;
18102 + di->rxdalloc = size;
18103 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
18104 + }
18105 +
18106 + return TRUE;
18107 +}
18108 +
18109 +static void
18110 +dma64_txreset(dma_info_t *di)
18111 +{
18112 + uint32 status;
18113 +
18114 + /* suspend tx DMA first */
18115 + W_REG(&di->d64txregs->control, D64_XC_SE);
18116 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
18117 + status != D64_XS0_XS_IDLE &&
18118 + status != D64_XS0_XS_STOPPED,
18119 + 10000);
18120 +
18121 + W_REG(&di->d64txregs->control, 0);
18122 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
18123 + 10000);
18124 +
18125 + if (status != D64_XS0_XS_DISABLED) {
18126 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
18127 + }
18128 +
18129 + /* wait for the last transaction to complete */
18130 + OSL_DELAY(300);
18131 +}
18132 +
18133 +static void
18134 +dma64_rxreset(dma_info_t *di)
18135 +{
18136 + uint32 status;
18137 +
18138 + W_REG(&di->d64rxregs->control, 0);
18139 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
18140 + 10000);
18141 +
18142 + if (status != D64_RS0_RS_DISABLED) {
18143 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
18144 + }
18145 +}
18146 +
18147 +static bool
18148 +dma64_txsuspendedidle(dma_info_t *di)
18149 +{
18150 +
18151 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
18152 + return 0;
18153 +
18154 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
18155 + return 1;
18156 +
18157 + return 0;
18158 +}
18159 +
18160 +/*
18161 + * supports full 32bit dma engine buffer addressing so
18162 + * dma buffers can cross 4 Kbyte page boundaries.
18163 + */
18164 +static int
18165 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
18166 +{
18167 + void *p, *next;
18168 + uchar *data;
18169 + uint len;
18170 + uint txout;
18171 + uint32 flags;
18172 + uint32 pa;
18173 +
18174 + DMA_TRACE(("%s: dma_txfast\n", di->name));
18175 +
18176 + txout = di->txout;
18177 + flags = 0;
18178 +
18179 + /*
18180 + * Walk the chain of packet buffers
18181 + * allocating and initializing transmit descriptor entries.
18182 + */
18183 + for (p = p0; p; p = next) {
18184 + data = PKTDATA(di->osh, p);
18185 + len = PKTLEN(di->osh, p);
18186 + next = PKTNEXT(di->osh, p);
18187 +
18188 + /* return nonzero if out of tx descriptors */
18189 + if (NEXTTXD(txout) == di->txin)
18190 + goto outoftxd;
18191 +
18192 + if (len == 0)
18193 + continue;
18194 +
18195 + /* get physical address of buffer start */
18196 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
18197 +
18198 + flags = coreflags;
18199 +
18200 + if (p == p0)
18201 + flags |= D64_CTRL1_SOF;
18202 + if (next == NULL)
18203 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
18204 + if (txout == (di->ntxd - 1))
18205 + flags |= D64_CTRL1_EOT;
18206 +
18207 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
18208 +
18209 + ASSERT(di->txp[txout] == NULL);
18210 +
18211 + txout = NEXTTXD(txout);
18212 + }
18213 +
18214 + /* if last txd eof not set, fix it */
18215 + if (!(flags & D64_CTRL1_EOF))
18216 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
18217 +
18218 + /* save the packet */
18219 + di->txp[PREVTXD(txout)] = p0;
18220 +
18221 + /* bump the tx descriptor index */
18222 + di->txout = txout;
18223 +
18224 + /* kick the chip */
18225 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18226 +
18227 + /* tx flow control */
18228 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18229 +
18230 + return (0);
18231 +
18232 +outoftxd:
18233 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18234 + PKTFREE(di->osh, p0, TRUE);
18235 + di->txavail = 0;
18236 + di->hnddma.txnobuf++;
18237 + return (-1);
18238 +}
18239 +
18240 +static void*
18241 +dma64_getnexttxp(dma_info_t *di, bool forceall)
18242 +{
18243 + uint start, end, i;
18244 + void *txp;
18245 +
18246 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18247 +
18248 + txp = NULL;
18249 +
18250 + start = di->txin;
18251 + if (forceall)
18252 + end = di->txout;
18253 + else
18254 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
18255 +
18256 + if ((start == 0) && (end > di->txout))
18257 + goto bogus;
18258 +
18259 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18260 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
18261 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
18262 +
18263 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
18264 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
18265 +
18266 + txp = di->txp[i];
18267 + di->txp[i] = NULL;
18268 + }
18269 +
18270 + di->txin = i;
18271 +
18272 + /* tx flow control */
18273 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18274 +
18275 + return (txp);
18276 +
18277 +bogus:
18278 +/*
18279 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18280 + start, end, di->txout, forceall));
18281 +*/
18282 + return (NULL);
18283 +}
18284 +
18285 +static void *
18286 +dma64_getnextrxp(dma_info_t *di, bool forceall)
18287 +{
18288 + uint i;
18289 + void *rxp;
18290 +
18291 + /* if forcing, dma engine must be disabled */
18292 + ASSERT(!forceall || !dma_rxenabled(di));
18293 +
18294 + i = di->rxin;
18295 +
18296 + /* return if no packets posted */
18297 + if (i == di->rxout)
18298 + return (NULL);
18299 +
18300 + /* ignore curr if forceall */
18301 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
18302 + return (NULL);
18303 +
18304 + /* get the packet pointer that corresponds to the rx descriptor */
18305 + rxp = di->rxp[i];
18306 + ASSERT(rxp);
18307 + di->rxp[i] = NULL;
18308 +
18309 + /* clear this packet from the descriptor ring */
18310 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
18311 + di->rxbufsize, DMA_RX, rxp);
18312 +
18313 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
18314 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
18315 +
18316 + di->rxin = NEXTRXD(i);
18317 +
18318 + return (rxp);
18319 +}
18320 +
18321 +static void
18322 +dma64_txrotate(di_t *di)
18323 +{
18324 + uint ad;
18325 + uint nactive;
18326 + uint rot;
18327 + uint old, new;
18328 + uint32 w;
18329 + uint first, last;
18330 +
18331 + ASSERT(dma_txsuspendedidle(di));
18332 +
18333 + nactive = dma_txactive(di);
18334 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
18335 + rot = TXD(ad - di->txin);
18336 +
18337 + ASSERT(rot < di->ntxd);
18338 +
18339 + /* full-ring case is a lot harder - don't worry about this */
18340 + if (rot >= (di->ntxd - nactive)) {
18341 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18342 + return;
18343 + }
18344 +
18345 + first = di->txin;
18346 + last = PREVTXD(di->txout);
18347 +
18348 + /* move entries starting at last and moving backwards to first */
18349 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18350 + new = TXD(old + rot);
18351 +
18352 + /*
18353 + * Move the tx dma descriptor.
18354 + * EOT is set only in the last entry in the ring.
18355 + */
18356 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
18357 + if (new == (di->ntxd - 1))
18358 + w |= D64_CTRL1_EOT;
18359 + W_SM(&di->txd64[new].ctrl1, w);
18360 +
18361 + w = R_SM(&di->txd64[old].ctrl2);
18362 + W_SM(&di->txd64[new].ctrl2, w);
18363 +
18364 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
18365 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
18366 +
18367 + /* zap the old tx dma descriptor address field */
18368 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
18369 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
18370 +
18371 + /* move the corresponding txp[] entry */
18372 + ASSERT(di->txp[new] == NULL);
18373 + di->txp[new] = di->txp[old];
18374 + di->txp[old] = NULL;
18375 + }
18376 +
18377 + /* update txin and txout */
18378 + di->txin = ad;
18379 + di->txout = TXD(di->txout + rot);
18380 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18381 +
18382 + /* kick the chip */
18383 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
18384 +}
18385 +
18386 +#endif
18387 +
18388 diff -urN linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
18389 --- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
18390 +++ linux.dev/drivers/net/hnd/linux_osl.c 2005-11-07 23:38:26.782893500 +0100
18391 @@ -0,0 +1,708 @@
18392 +/*
18393 + * Linux OS Independent Layer
18394 + *
18395 + * Copyright 2005, Broadcom Corporation
18396 + * All Rights Reserved.
18397 + *
18398 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18399 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18400 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18401 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18402 + *
18403 + * $Id$
18404 + */
18405 +
18406 +#define LINUX_OSL
18407 +
18408 +#include <typedefs.h>
18409 +#include <bcmendian.h>
18410 +#include <linux/module.h>
18411 +#include <linuxver.h>
18412 +#include <osl.h>
18413 +#include <bcmutils.h>
18414 +#include <linux/delay.h>
18415 +#ifdef mips
18416 +#include <asm/paccess.h>
18417 +#endif
18418 +#include <pcicfg.h>
18419 +
18420 +#define PCI_CFG_RETRY 10
18421 +
18422 +#define OS_HANDLE_MAGIC 0x1234abcd
18423 +#define BCM_MEM_FILENAME_LEN 24
18424 +
18425 +typedef struct bcm_mem_link {
18426 + struct bcm_mem_link *prev;
18427 + struct bcm_mem_link *next;
18428 + uint size;
18429 + int line;
18430 + char file[BCM_MEM_FILENAME_LEN];
18431 +} bcm_mem_link_t;
18432 +
18433 +struct os_handle {
18434 + uint magic;
18435 + void *pdev;
18436 + uint malloced;
18437 + uint failed;
18438 + bcm_mem_link_t *dbgmem_list;
18439 +};
18440 +
18441 +static int16 linuxbcmerrormap[] = \
18442 +{ 0, /* 0 */
18443 + -EINVAL, /* BCME_ERROR */
18444 + -EINVAL, /* BCME_BADARG*/
18445 + -EINVAL, /* BCME_BADOPTION*/
18446 + -EINVAL, /* BCME_NOTUP */
18447 + -EINVAL, /* BCME_NOTDOWN */
18448 + -EINVAL, /* BCME_NOTAP */
18449 + -EINVAL, /* BCME_NOTSTA */
18450 + -EINVAL, /* BCME_BADKEYIDX */
18451 + -EINVAL, /* BCME_RADIOOFF */
18452 + -EINVAL, /* BCME_NOTBANDLOCKED */
18453 + -EINVAL, /* BCME_NOCLK */
18454 + -EINVAL, /* BCME_BADRATESET */
18455 + -EINVAL, /* BCME_BADBAND */
18456 + -E2BIG, /* BCME_BUFTOOSHORT */
18457 + -E2BIG, /* BCME_BUFTOOLONG */
18458 + -EBUSY, /* BCME_BUSY */
18459 + -EINVAL, /* BCME_NOTASSOCIATED */
18460 + -EINVAL, /* BCME_BADSSIDLEN */
18461 + -EINVAL, /* BCME_OUTOFRANGECHAN */
18462 + -EINVAL, /* BCME_BADCHAN */
18463 + -EFAULT, /* BCME_BADADDR */
18464 + -ENOMEM, /* BCME_NORESOURCE */
18465 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
18466 + -EMSGSIZE, /* BCME_BADLENGTH */
18467 + -EINVAL, /* BCME_NOTREADY */
18468 + -EPERM, /* BCME_NOTPERMITTED */
18469 + -ENOMEM, /* BCME_NOMEM */
18470 + -EINVAL, /* BCME_ASSOCIATED */
18471 + -ERANGE, /* BCME_RANGE */
18472 + -EINVAL /* BCME_NOTFOUND */
18473 +};
18474 +
18475 +/* translate bcmerrors into linux errors*/
18476 +int
18477 +osl_error(int bcmerror)
18478 +{
18479 + int abs_bcmerror;
18480 + int array_size = ARRAYSIZE(linuxbcmerrormap);
18481 +
18482 + abs_bcmerror = ABS(bcmerror);
18483 +
18484 + if (bcmerror > 0)
18485 + abs_bcmerror = 0;
18486 +
18487 + else if (abs_bcmerror >= array_size)
18488 + abs_bcmerror = BCME_ERROR;
18489 +
18490 + return linuxbcmerrormap[abs_bcmerror];
18491 +}
18492 +
18493 +osl_t *
18494 +osl_attach(void *pdev)
18495 +{
18496 + osl_t *osh;
18497 +
18498 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
18499 + ASSERT(osh);
18500 +
18501 + /*
18502 + * check the cases where
18503 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
18504 + * dependent error code
18505 + * 2. Error code is added to the bcmerror table, but forgot to add the
18506 + * corresponding errorstring(dummy call to bcmerrorstr)
18507 + */
18508 + bcmerrorstr(0);
18509 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
18510 +
18511 + osh->magic = OS_HANDLE_MAGIC;
18512 + osh->malloced = 0;
18513 + osh->failed = 0;
18514 + osh->dbgmem_list = NULL;
18515 + osh->pdev = pdev;
18516 +
18517 + return osh;
18518 +}
18519 +
18520 +void
18521 +osl_detach(osl_t *osh)
18522 +{
18523 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
18524 + kfree(osh);
18525 +}
18526 +
18527 +void*
18528 +osl_pktget(osl_t *osh, uint len, bool send)
18529 +{
18530 + struct sk_buff *skb;
18531 +
18532 + if ((skb = dev_alloc_skb(len)) == NULL)
18533 + return (NULL);
18534 +
18535 + skb_put(skb, len);
18536 +
18537 + /* ensure the cookie field is cleared */
18538 + PKTSETCOOKIE(skb, NULL);
18539 +
18540 + return ((void*) skb);
18541 +}
18542 +
18543 +void
18544 +osl_pktfree(void *p)
18545 +{
18546 + struct sk_buff *skb, *nskb;
18547 +
18548 + skb = (struct sk_buff*) p;
18549 +
18550 + /* perversion: we use skb->next to chain multi-skb packets */
18551 + while (skb) {
18552 + nskb = skb->next;
18553 + skb->next = NULL;
18554 + if (skb->destructor) {
18555 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
18556 + dev_kfree_skb_any(skb);
18557 + } else {
18558 + /* can free immediately (even in_irq()) if destructor does not exist */
18559 + dev_kfree_skb(skb);
18560 + }
18561 + skb = nskb;
18562 + }
18563 +}
18564 +
18565 +uint32
18566 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
18567 +{
18568 + uint val;
18569 + uint retry=PCI_CFG_RETRY;
18570 +
18571 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18572 +
18573 + /* only 4byte access supported */
18574 + ASSERT(size == 4);
18575 +
18576 + do {
18577 + pci_read_config_dword(osh->pdev, offset, &val);
18578 + if (val != 0xffffffff)
18579 + break;
18580 + } while (retry--);
18581 +
18582 +
18583 + return (val);
18584 +}
18585 +
18586 +void
18587 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
18588 +{
18589 + uint retry=PCI_CFG_RETRY;
18590 +
18591 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18592 +
18593 + /* only 4byte access supported */
18594 + ASSERT(size == 4);
18595 +
18596 + do {
18597 + pci_write_config_dword(osh->pdev, offset, val);
18598 + if (offset!=PCI_BAR0_WIN)
18599 + break;
18600 + if (osl_pci_read_config(osh,offset,size) == val)
18601 + break;
18602 + } while (retry--);
18603 +
18604 +}
18605 +
18606 +/* return bus # for the pci device pointed by osh->pdev */
18607 +uint
18608 +osl_pci_bus(osl_t *osh)
18609 +{
18610 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18611 +
18612 + return ((struct pci_dev *)osh->pdev)->bus->number;
18613 +}
18614 +
18615 +/* return slot # for the pci device pointed by osh->pdev */
18616 +uint
18617 +osl_pci_slot(osl_t *osh)
18618 +{
18619 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18620 +
18621 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
18622 +}
18623 +
18624 +static void
18625 +osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
18626 +{
18627 +}
18628 +
18629 +void
18630 +osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
18631 +{
18632 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
18633 +}
18634 +
18635 +void
18636 +osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
18637 +{
18638 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
18639 +}
18640 +
18641 +
18642 +#ifdef BCMDBG_MEM
18643 +
18644 +void*
18645 +osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
18646 +{
18647 + bcm_mem_link_t *p;
18648 + char* basename;
18649 +
18650 + ASSERT(size);
18651 +
18652 + if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
18653 + return (NULL);
18654 +
18655 + p->size = size;
18656 + p->line = line;
18657 +
18658 + basename = strrchr(file, '/');
18659 + /* skip the '/' */
18660 + if (basename)
18661 + basename++;
18662 +
18663 + if (!basename)
18664 + basename = file;
18665 +
18666 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
18667 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
18668 +
18669 + /* link this block */
18670 + p->prev = NULL;
18671 + p->next = osh->dbgmem_list;
18672 + if (p->next)
18673 + p->next->prev = p;
18674 + osh->dbgmem_list = p;
18675 +
18676 + return p + 1;
18677 +}
18678 +
18679 +void
18680 +osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
18681 +{
18682 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
18683 +
18684 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18685 +
18686 + if (p->size == 0) {
18687 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
18688 + (uint)addr, size, line, file);
18689 + ASSERT(p->size);
18690 + return;
18691 + }
18692 +
18693 + if (p->size != size) {
18694 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
18695 + size, p->size, (uint)addr, line, file);
18696 + ASSERT(p->size == size);
18697 + return;
18698 + }
18699 +
18700 + /* unlink this block */
18701 + if (p->prev)
18702 + p->prev->next = p->next;
18703 + if (p->next)
18704 + p->next->prev = p->prev;
18705 + if (osh->dbgmem_list == p)
18706 + osh->dbgmem_list = p->next;
18707 + p->next = p->prev = NULL;
18708 +
18709 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
18710 +}
18711 +
18712 +char*
18713 +osl_debug_memdump(osl_t *osh, char *buf, uint sz)
18714 +{
18715 + bcm_mem_link_t *p;
18716 + char *obuf;
18717 +
18718 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18719 + obuf = buf;
18720 +
18721 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
18722 + for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
18723 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
18724 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
18725 +
18726 + return (obuf);
18727 +}
18728 +
18729 +#endif /* BCMDBG_MEM */
18730 +
18731 +void*
18732 +osl_malloc(osl_t *osh, uint size)
18733 +{
18734 + void *addr;
18735 +
18736 + /* only ASSERT if osh is defined */
18737 + if (osh)
18738 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18739 +
18740 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
18741 + if(osh)
18742 + osh->failed++;
18743 + return (NULL);
18744 + }
18745 + if (osh)
18746 + osh->malloced += size;
18747 +
18748 + return (addr);
18749 +}
18750 +
18751 +void
18752 +osl_mfree(osl_t *osh, void *addr, uint size)
18753 +{
18754 + if (osh) {
18755 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18756 + osh->malloced -= size;
18757 + }
18758 + kfree(addr);
18759 +}
18760 +
18761 +uint
18762 +osl_malloced(osl_t *osh)
18763 +{
18764 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18765 + return (osh->malloced);
18766 +}
18767 +
18768 +uint osl_malloc_failed(osl_t *osh)
18769 +{
18770 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18771 + return (osh->failed);
18772 +}
18773 +
18774 +void*
18775 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
18776 +{
18777 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18778 +
18779 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
18780 +}
18781 +
18782 +void
18783 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
18784 +{
18785 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18786 +
18787 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
18788 +}
18789 +
18790 +uint
18791 +osl_dma_map(osl_t *osh, void *va, uint size, int direction)
18792 +{
18793 + int dir;
18794 +
18795 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18796 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18797 + return (pci_map_single(osh->pdev, va, size, dir));
18798 +}
18799 +
18800 +void
18801 +osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
18802 +{
18803 + int dir;
18804 +
18805 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18806 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18807 + pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
18808 +}
18809 +
18810 +#if defined(BINOSL)
18811 +void
18812 +osl_assert(char *exp, char *file, int line)
18813 +{
18814 + char tempbuf[255];
18815 +
18816 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
18817 + panic(tempbuf);
18818 +}
18819 +#endif /* BCMDBG || BINOSL */
18820 +
18821 +void
18822 +osl_delay(uint usec)
18823 +{
18824 + uint d;
18825 +
18826 + while (usec > 0) {
18827 + d = MIN(usec, 1000);
18828 + udelay(d);
18829 + usec -= d;
18830 + }
18831 +}
18832 +
18833 +/*
18834 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
18835 + */
18836 +#ifdef BINOSL
18837 +
18838 +int
18839 +osl_printf(const char *format, ...)
18840 +{
18841 + va_list args;
18842 + char buf[1024];
18843 + int len;
18844 +
18845 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
18846 + va_start(args, format);
18847 + len = vsprintf(buf, format, args);
18848 + va_end(args);
18849 +
18850 + if (len > sizeof (buf)) {
18851 + printk("osl_printf: buffer overrun\n");
18852 + return (0);
18853 + }
18854 +
18855 + return (printk(buf));
18856 +}
18857 +
18858 +int
18859 +osl_sprintf(char *buf, const char *format, ...)
18860 +{
18861 + va_list args;
18862 + int rc;
18863 +
18864 + va_start(args, format);
18865 + rc = vsprintf(buf, format, args);
18866 + va_end(args);
18867 + return (rc);
18868 +}
18869 +
18870 +int
18871 +osl_strcmp(const char *s1, const char *s2)
18872 +{
18873 + return (strcmp(s1, s2));
18874 +}
18875 +
18876 +int
18877 +osl_strncmp(const char *s1, const char *s2, uint n)
18878 +{
18879 + return (strncmp(s1, s2, n));
18880 +}
18881 +
18882 +int
18883 +osl_strlen(const char *s)
18884 +{
18885 + return (strlen(s));
18886 +}
18887 +
18888 +char*
18889 +osl_strcpy(char *d, const char *s)
18890 +{
18891 + return (strcpy(d, s));
18892 +}
18893 +
18894 +char*
18895 +osl_strncpy(char *d, const char *s, uint n)
18896 +{
18897 + return (strncpy(d, s, n));
18898 +}
18899 +
18900 +void
18901 +bcopy(const void *src, void *dst, int len)
18902 +{
18903 + memcpy(dst, src, len);
18904 +}
18905 +
18906 +int
18907 +bcmp(const void *b1, const void *b2, int len)
18908 +{
18909 + return (memcmp(b1, b2, len));
18910 +}
18911 +
18912 +void
18913 +bzero(void *b, int len)
18914 +{
18915 + memset(b, '\0', len);
18916 +}
18917 +
18918 +uint32
18919 +osl_readl(volatile uint32 *r)
18920 +{
18921 + return (readl(r));
18922 +}
18923 +
18924 +uint16
18925 +osl_readw(volatile uint16 *r)
18926 +{
18927 + return (readw(r));
18928 +}
18929 +
18930 +uint8
18931 +osl_readb(volatile uint8 *r)
18932 +{
18933 + return (readb(r));
18934 +}
18935 +
18936 +void
18937 +osl_writel(uint32 v, volatile uint32 *r)
18938 +{
18939 + writel(v, r);
18940 +}
18941 +
18942 +void
18943 +osl_writew(uint16 v, volatile uint16 *r)
18944 +{
18945 + writew(v, r);
18946 +}
18947 +
18948 +void
18949 +osl_writeb(uint8 v, volatile uint8 *r)
18950 +{
18951 + writeb(v, r);
18952 +}
18953 +
18954 +void *
18955 +osl_uncached(void *va)
18956 +{
18957 +#ifdef mips
18958 + return ((void*)KSEG1ADDR(va));
18959 +#else
18960 + return ((void*)va);
18961 +#endif
18962 +}
18963 +
18964 +uint
18965 +osl_getcycles(void)
18966 +{
18967 + uint cycles;
18968 +
18969 +#if defined(mips)
18970 + cycles = read_c0_count() * 2;
18971 +#elif defined(__i386__)
18972 + rdtscl(cycles);
18973 +#else
18974 + cycles = 0;
18975 +#endif
18976 + return cycles;
18977 +}
18978 +
18979 +void *
18980 +osl_reg_map(uint32 pa, uint size)
18981 +{
18982 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
18983 +}
18984 +
18985 +void
18986 +osl_reg_unmap(void *va)
18987 +{
18988 + iounmap(va);
18989 +}
18990 +
18991 +int
18992 +osl_busprobe(uint32 *val, uint32 addr)
18993 +{
18994 +#ifdef mips
18995 + return get_dbe(*val, (uint32*)addr);
18996 +#else
18997 + *val = readl(addr);
18998 + return 0;
18999 +#endif
19000 +}
19001 +
19002 +uchar*
19003 +osl_pktdata(osl_t *osh, void *skb)
19004 +{
19005 + return (((struct sk_buff*)skb)->data);
19006 +}
19007 +
19008 +uint
19009 +osl_pktlen(osl_t *osh, void *skb)
19010 +{
19011 + return (((struct sk_buff*)skb)->len);
19012 +}
19013 +
19014 +uint
19015 +osl_pktheadroom(osl_t *osh, void *skb)
19016 +{
19017 + return (uint) skb_headroom((struct sk_buff *) skb);
19018 +}
19019 +
19020 +uint
19021 +osl_pkttailroom(osl_t *osh, void *skb)
19022 +{
19023 + return (uint) skb_tailroom((struct sk_buff *) skb);
19024 +}
19025 +
19026 +void*
19027 +osl_pktnext(osl_t *osh, void *skb)
19028 +{
19029 + return (((struct sk_buff*)skb)->next);
19030 +}
19031 +
19032 +void
19033 +osl_pktsetnext(void *skb, void *x)
19034 +{
19035 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
19036 +}
19037 +
19038 +void
19039 +osl_pktsetlen(osl_t *osh, void *skb, uint len)
19040 +{
19041 + __skb_trim((struct sk_buff*)skb, len);
19042 +}
19043 +
19044 +uchar*
19045 +osl_pktpush(osl_t *osh, void *skb, int bytes)
19046 +{
19047 + return (skb_push((struct sk_buff*)skb, bytes));
19048 +}
19049 +
19050 +uchar*
19051 +osl_pktpull(osl_t *osh, void *skb, int bytes)
19052 +{
19053 + return (skb_pull((struct sk_buff*)skb, bytes));
19054 +}
19055 +
19056 +void*
19057 +osl_pktdup(osl_t *osh, void *skb)
19058 +{
19059 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
19060 +}
19061 +
19062 +void*
19063 +osl_pktcookie(void *skb)
19064 +{
19065 + return ((void*)((struct sk_buff*)skb)->csum);
19066 +}
19067 +
19068 +void
19069 +osl_pktsetcookie(void *skb, void *x)
19070 +{
19071 + ((struct sk_buff*)skb)->csum = (uint)x;
19072 +}
19073 +
19074 +void*
19075 +osl_pktlink(void *skb)
19076 +{
19077 + return (((struct sk_buff*)skb)->prev);
19078 +}
19079 +
19080 +void
19081 +osl_pktsetlink(void *skb, void *x)
19082 +{
19083 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
19084 +}
19085 +
19086 +uint
19087 +osl_pktprio(void *skb)
19088 +{
19089 + return (((struct sk_buff*)skb)->priority);
19090 +}
19091 +
19092 +void
19093 +osl_pktsetprio(void *skb, uint x)
19094 +{
19095 + ((struct sk_buff*)skb)->priority = x;
19096 +}
19097 +
19098 +
19099 +#endif /* BINOSL */
19100 diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
19101 --- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
19102 +++ linux.dev/drivers/net/hnd/sbutils.c 2005-11-08 17:58:18.918914500 +0100
19103 @@ -0,0 +1,2837 @@
19104 +/*
19105 + * Misc utility routines for accessing chip-specific features
19106 + * of the SiliconBackplane-based Broadcom chips.
19107 + *
19108 + * Copyright 2005, Broadcom Corporation
19109 + * All Rights Reserved.
19110 + *
19111 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19112 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19113 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19114 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19115 + * $Id$
19116 + */
19117 +
19118 +#include <typedefs.h>
19119 +#include <osl.h>
19120 +#include <sbutils.h>
19121 +#include <bcmutils.h>
19122 +#include <bcmdevs.h>
19123 +#include <sbconfig.h>
19124 +#include <sbchipc.h>
19125 +#include <sbpci.h>
19126 +#include <sbpcie.h>
19127 +#include <pcicfg.h>
19128 +#include <sbpcmcia.h>
19129 +#include <sbextif.h>
19130 +#include <bcmsrom.h>
19131 +
19132 +/* debug/trace */
19133 +#define SB_ERROR(args)
19134 +
19135 +
19136 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
19137 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
19138 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
19139 +
19140 +/* misc sb info needed by some of the routines */
19141 +typedef struct sb_info {
19142 +
19143 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
19144 +
19145 + void *osh; /* osl os handle */
19146 + void *sdh; /* bcmsdh handle */
19147 +
19148 + void *curmap; /* current regs va */
19149 + void *regs[SB_MAXCORES]; /* other regs va */
19150 +
19151 + uint curidx; /* current core index */
19152 + uint dev_coreid; /* the core provides driver functions */
19153 +
19154 + bool memseg; /* flag to toggle MEM_SEG register */
19155 +
19156 + uint gpioidx; /* gpio control core index */
19157 + uint gpioid; /* gpio control coretype */
19158 +
19159 + uint numcores; /* # discovered cores */
19160 + uint coreid[SB_MAXCORES]; /* id of each core */
19161 +
19162 + void *intr_arg; /* interrupt callback function arg */
19163 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
19164 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
19165 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
19166 +
19167 +} sb_info_t;
19168 +
19169 +/* local prototypes */
19170 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19171 + uint bustype, void *sdh, char **vars, int *varsz);
19172 +static void BCMINIT(sb_scan)(sb_info_t *si);
19173 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
19174 +static uint _sb_coreidx(sb_info_t *si);
19175 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
19176 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
19177 +static uint BCMINIT(sb_chip2numcores)(uint chip);
19178 +static bool sb_ispcie(sb_info_t *si);
19179 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
19180 +static int sb_pci_fixcfg(sb_info_t *si);
19181 +
19182 +/* routines to access mdio slave device registers */
19183 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
19184 +static void BCMINIT(sb_war30841)(sb_info_t *si);
19185 +
19186 +/* delay needed between the mdio control/ mdiodata register data access */
19187 +#define PR28829_DELAY() OSL_DELAY(10)
19188 +
19189 +
19190 +/* global variable to indicate reservation/release of gpio's*/
19191 +static uint32 sb_gpioreservation = 0;
19192 +
19193 +#define SB_INFO(sbh) (sb_info_t*)sbh
19194 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
19195 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
19196 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
19197 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
19198 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
19199 +#define BADIDX (SB_MAXCORES+1)
19200 +#define NOREV -1
19201 +
19202 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
19203 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
19204 +
19205 +/* sonicsrev */
19206 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
19207 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
19208 +
19209 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
19210 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
19211 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
19212 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
19213 +
19214 +/*
19215 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
19216 + * after core switching to avoid invalid register accesss inside ISR.
19217 + */
19218 +#define INTR_OFF(si, intr_val) \
19219 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19220 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
19221 +#define INTR_RESTORE(si, intr_val) \
19222 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19223 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
19224 +
19225 +/* dynamic clock control defines */
19226 +#define LPOMINFREQ 25000 /* low power oscillator min */
19227 +#define LPOMAXFREQ 43000 /* low power oscillator max */
19228 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
19229 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
19230 +#define PCIMINFREQ 25000000 /* 25 MHz */
19231 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
19232 +
19233 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
19234 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
19235 +
19236 +#define MIN_DUMPBUFLEN 32 /* debug */
19237 +
19238 +/* different register spaces to access thr'u pcie indirect access*/
19239 +#define PCIE_CONFIGREGS 1
19240 +#define PCIE_PCIEREGS 2
19241 +
19242 +/* GPIO Based LED powersave defines */
19243 +#define DEFAULT_GPIO_ONTIME 10
19244 +#define DEFAULT_GPIO_OFFTIME 90
19245 +
19246 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
19247 +
19248 +static uint32
19249 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
19250 +{
19251 + uint8 tmp;
19252 + uint32 val, intr_val = 0;
19253 +
19254 +
19255 + /*
19256 + * compact flash only has 11 bits address, while we needs 12 bits address.
19257 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19258 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19259 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19260 + */
19261 + if(si->memseg) {
19262 + INTR_OFF(si, intr_val);
19263 + tmp = 1;
19264 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19265 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19266 + }
19267 +
19268 + val = R_REG(sbr);
19269 +
19270 + if(si->memseg) {
19271 + tmp = 0;
19272 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19273 + INTR_RESTORE(si, intr_val);
19274 + }
19275 +
19276 + return (val);
19277 +}
19278 +
19279 +static void
19280 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
19281 +{
19282 + uint8 tmp;
19283 + volatile uint32 dummy;
19284 + uint32 intr_val = 0;
19285 +
19286 +
19287 + /*
19288 + * compact flash only has 11 bits address, while we needs 12 bits address.
19289 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19290 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19291 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19292 + */
19293 + if(si->memseg) {
19294 + INTR_OFF(si, intr_val);
19295 + tmp = 1;
19296 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19297 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19298 + }
19299 +
19300 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19301 +#ifdef IL_BIGENDIAN
19302 + dummy = R_REG(sbr);
19303 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19304 + dummy = R_REG(sbr);
19305 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19306 +#else
19307 + dummy = R_REG(sbr);
19308 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19309 + dummy = R_REG(sbr);
19310 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19311 +#endif
19312 + } else
19313 + W_REG(sbr, v);
19314 +
19315 + if(si->memseg) {
19316 + tmp = 0;
19317 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19318 + INTR_RESTORE(si, intr_val);
19319 + }
19320 +}
19321 +
19322 +/*
19323 + * Allocate a sb handle.
19324 + * devid - pci device id (used to determine chip#)
19325 + * osh - opaque OS handle
19326 + * regs - virtual address of initial core registers
19327 + * bustype - pci/pcmcia/sb/sdio/etc
19328 + * vars - pointer to a pointer area for "environment" variables
19329 + * varsz - pointer to int to return the size of the vars
19330 + */
19331 +sb_t *
19332 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
19333 + uint bustype, void *sdh, char **vars, int *varsz)
19334 +{
19335 + sb_info_t *si;
19336 +
19337 + /* alloc sb_info_t */
19338 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
19339 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
19340 + return (NULL);
19341 + }
19342 +
19343 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
19344 + MFREE(osh, si, sizeof (sb_info_t));
19345 + return (NULL);
19346 + }
19347 + return (sb_t *)si;
19348 +}
19349 +
19350 +/* Using sb_kattach depends on SB_BUS support, either implicit */
19351 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
19352 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
19353 +
19354 +/* global kernel resource */
19355 +static sb_info_t ksi;
19356 +
19357 +/* generic kernel variant of sb_attach() */
19358 +sb_t *
19359 +BCMINITFN(sb_kattach)()
19360 +{
19361 + uint32 *regs;
19362 +
19363 + if (ksi.curmap == NULL) {
19364 + uint32 cid;
19365 +
19366 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
19367 + cid = R_REG((uint32 *)regs);
19368 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
19369 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
19370 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
19371 + uint32 *scc, val;
19372 +
19373 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
19374 + val = R_REG(scc);
19375 + SB_ERROR((" initial scc = 0x%x\n", val));
19376 + val |= SCC_SS_XTAL;
19377 + W_REG(scc, val);
19378 + }
19379 +
19380 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
19381 + SB_BUS, NULL, NULL, NULL) == NULL) {
19382 + return NULL;
19383 + }
19384 + }
19385 +
19386 + return (sb_t *)&ksi;
19387 +}
19388 +#endif
19389 +
19390 +static sb_info_t *
19391 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19392 + uint bustype, void *sdh, char **vars, int *varsz)
19393 +{
19394 + uint origidx;
19395 + chipcregs_t *cc;
19396 + sbconfig_t *sb;
19397 + uint32 w;
19398 +
19399 + ASSERT(GOODREGS(regs));
19400 +
19401 + bzero((uchar*)si, sizeof (sb_info_t));
19402 +
19403 + si->sb.buscoreidx = si->gpioidx = BADIDX;
19404 +
19405 + si->osh = osh;
19406 + si->curmap = regs;
19407 + si->sdh = sdh;
19408 +
19409 + /* check to see if we are a sb core mimic'ing a pci core */
19410 + if (bustype == PCI_BUS) {
19411 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
19412 + bustype = SB_BUS;
19413 + else
19414 + bustype = PCI_BUS;
19415 + }
19416 +
19417 + si->sb.bustype = bustype;
19418 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
19419 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
19420 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
19421 + return NULL;
19422 + }
19423 +
19424 + /* need to set memseg flag for CF card first before any sb registers access */
19425 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19426 + si->memseg = TRUE;
19427 +
19428 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
19429 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
19430 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
19431 +
19432 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19433 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
19434 + if (!GOODCOREADDR(w))
19435 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
19436 + }
19437 +
19438 + /* initialize current core index value */
19439 + si->curidx = _sb_coreidx(si);
19440 +
19441 + if (si->curidx == BADIDX) {
19442 + SB_ERROR(("sb_doattach: bad core index\n"));
19443 + return NULL;
19444 + }
19445 +
19446 + /* get sonics backplane revision */
19447 + sb = REGS2SB(si->curmap);
19448 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
19449 +
19450 + /* keep and reuse the initial register mapping */
19451 + origidx = si->curidx;
19452 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
19453 + si->regs[origidx] = regs;
19454 +
19455 + /* is core-0 a chipcommon core? */
19456 + si->numcores = 1;
19457 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
19458 + if (sb_coreid(&si->sb) != SB_CC)
19459 + cc = NULL;
19460 +
19461 + /* determine chip id and rev */
19462 + if (cc) {
19463 + /* chip common core found! */
19464 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
19465 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
19466 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
19467 + } else {
19468 + /* The only pcmcia chip without a chipcommon core is a 4301 */
19469 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19470 + devid = BCM4301_DEVICE_ID;
19471 +
19472 + /* no chip common core -- must convert device id to chip id */
19473 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
19474 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
19475 + sb_setcoreidx(&si->sb, origidx);
19476 + return NULL;
19477 + }
19478 + }
19479 +
19480 + /* get chipcommon rev */
19481 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
19482 +
19483 + /* determine numcores */
19484 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
19485 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
19486 + else
19487 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
19488 +
19489 + /* return to original core */
19490 + sb_setcoreidx(&si->sb, origidx);
19491 +
19492 + /* sanity checks */
19493 + ASSERT(si->sb.chip);
19494 +
19495 + /* scan for cores */
19496 + BCMINIT(sb_scan)(si);
19497 +
19498 + /* fixup necessary chip/core configurations */
19499 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19500 + if (sb_pci_fixcfg(si)) {
19501 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
19502 + return NULL;
19503 + }
19504 + }
19505 +
19506 + /* srom_var_init() depends on sb_scan() info */
19507 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
19508 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
19509 + return (NULL);
19510 + }
19511 +
19512 + if (cc == NULL) {
19513 + /*
19514 + * The chip revision number is hardwired into all
19515 + * of the pci function config rev fields and is
19516 + * independent from the individual core revision numbers.
19517 + * For example, the "A0" silicon of each chip is chip rev 0.
19518 + * For PCMCIA we get it from the CIS instead.
19519 + */
19520 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19521 + ASSERT(vars);
19522 + si->sb.chiprev = getintvar(*vars, "chiprev");
19523 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19524 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
19525 + si->sb.chiprev = w & 0xff;
19526 + } else
19527 + si->sb.chiprev = 0;
19528 + }
19529 +
19530 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19531 + w = getintvar(*vars, "regwindowsz");
19532 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
19533 + }
19534 +
19535 + /* gpio control core is required */
19536 + if (!GOODIDX(si->gpioidx)) {
19537 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
19538 + return NULL;
19539 + }
19540 +
19541 + /* get boardtype and boardrev */
19542 + switch (BUSTYPE(si->sb.bustype)) {
19543 + case PCI_BUS:
19544 + /* do a pci config read to get subsystem id and subvendor id */
19545 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
19546 + si->sb.boardvendor = w & 0xffff;
19547 + si->sb.boardtype = (w >> 16) & 0xffff;
19548 + break;
19549 +
19550 + case PCMCIA_BUS:
19551 + case SDIO_BUS:
19552 + si->sb.boardvendor = getintvar(*vars, "manfid");
19553 + si->sb.boardtype = getintvar(*vars, "prodid");
19554 + break;
19555 +
19556 + case SB_BUS:
19557 + case JTAG_BUS:
19558 + si->sb.boardvendor = VENDOR_BROADCOM;
19559 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
19560 + si->sb.boardtype = 0xffff;
19561 + break;
19562 + }
19563 +
19564 + if (si->sb.boardtype == 0) {
19565 + SB_ERROR(("sb_doattach: unknown board type\n"));
19566 + ASSERT(si->sb.boardtype);
19567 + }
19568 +
19569 + /* setup the GPIO based LED powersave register */
19570 + if (si->sb.ccrev >= 16) {
19571 + w = getintvar(*vars, "gpiotimerval");
19572 + if (!w)
19573 + w = DEFAULT_GPIOTIMERVAL;
19574 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
19575 + }
19576 +
19577 +
19578 + return (si);
19579 +}
19580 +
19581 +uint
19582 +sb_coreid(sb_t *sbh)
19583 +{
19584 + sb_info_t *si;
19585 + sbconfig_t *sb;
19586 +
19587 + si = SB_INFO(sbh);
19588 + sb = REGS2SB(si->curmap);
19589 +
19590 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
19591 +}
19592 +
19593 +uint
19594 +sb_coreidx(sb_t *sbh)
19595 +{
19596 + sb_info_t *si;
19597 +
19598 + si = SB_INFO(sbh);
19599 + return (si->curidx);
19600 +}
19601 +
19602 +/* return current index of core */
19603 +static uint
19604 +_sb_coreidx(sb_info_t *si)
19605 +{
19606 + sbconfig_t *sb;
19607 + uint32 sbaddr = 0;
19608 +
19609 + ASSERT(si);
19610 +
19611 + switch (BUSTYPE(si->sb.bustype)) {
19612 + case SB_BUS:
19613 + sb = REGS2SB(si->curmap);
19614 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
19615 + break;
19616 +
19617 + case PCI_BUS:
19618 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
19619 + break;
19620 +
19621 + case PCMCIA_BUS: {
19622 + uint8 tmp = 0;
19623 +
19624 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
19625 + sbaddr = (uint)tmp << 12;
19626 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
19627 + sbaddr |= (uint)tmp << 16;
19628 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
19629 + sbaddr |= (uint)tmp << 24;
19630 + break;
19631 + }
19632 +
19633 +#ifdef BCMJTAG
19634 + case JTAG_BUS:
19635 + sbaddr = (uint32)si->curmap;
19636 + break;
19637 +#endif /* BCMJTAG */
19638 +
19639 + default:
19640 + ASSERT(0);
19641 + }
19642 +
19643 + if (!GOODCOREADDR(sbaddr))
19644 + return BADIDX;
19645 +
19646 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
19647 +}
19648 +
19649 +uint
19650 +sb_corevendor(sb_t *sbh)
19651 +{
19652 + sb_info_t *si;
19653 + sbconfig_t *sb;
19654 +
19655 + si = SB_INFO(sbh);
19656 + sb = REGS2SB(si->curmap);
19657 +
19658 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
19659 +}
19660 +
19661 +uint
19662 +sb_corerev(sb_t *sbh)
19663 +{
19664 + sb_info_t *si;
19665 + sbconfig_t *sb;
19666 + uint sbidh;
19667 +
19668 + si = SB_INFO(sbh);
19669 + sb = REGS2SB(si->curmap);
19670 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
19671 +
19672 + return (SBCOREREV(sbidh));
19673 +}
19674 +
19675 +void *
19676 +sb_osh(sb_t *sbh)
19677 +{
19678 + sb_info_t *si;
19679 +
19680 + si = SB_INFO(sbh);
19681 + return si->osh;
19682 +}
19683 +
19684 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
19685 +
19686 +/* set/clear sbtmstatelow core-specific flags */
19687 +uint32
19688 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
19689 +{
19690 + sb_info_t *si;
19691 + sbconfig_t *sb;
19692 + uint32 w;
19693 +
19694 + si = SB_INFO(sbh);
19695 + sb = REGS2SB(si->curmap);
19696 +
19697 + ASSERT((val & ~mask) == 0);
19698 + ASSERT((mask & ~SBTML_ALLOW) == 0);
19699 +
19700 + /* mask and set */
19701 + if (mask || val) {
19702 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
19703 + W_SBREG(si, &sb->sbtmstatelow, w);
19704 + }
19705 +
19706 + /* return the new value */
19707 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
19708 +}
19709 +
19710 +/* set/clear sbtmstatehigh core-specific flags */
19711 +uint32
19712 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
19713 +{
19714 + sb_info_t *si;
19715 + sbconfig_t *sb;
19716 + uint32 w;
19717 +
19718 + si = SB_INFO(sbh);
19719 + sb = REGS2SB(si->curmap);
19720 +
19721 + ASSERT((val & ~mask) == 0);
19722 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
19723 +
19724 + /* mask and set */
19725 + if (mask || val) {
19726 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
19727 + W_SBREG(si, &sb->sbtmstatehigh, w);
19728 + }
19729 +
19730 + /* return the new value */
19731 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
19732 +}
19733 +
19734 +/* caller needs to take care of core-specific bist hazards */
19735 +int
19736 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
19737 +{
19738 + uint32 sblo;
19739 + uint coreidx;
19740 + sb_info_t *si;
19741 + int result = 0;
19742 +
19743 + si = SB_INFO(sbh);
19744 +
19745 + coreidx = sb_findcoreidx(si, coreid, coreunit);
19746 + if (!GOODIDX(coreidx))
19747 + result = BCME_ERROR;
19748 + else {
19749 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
19750 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
19751 +
19752 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
19753 +
19754 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
19755 + result = BCME_ERROR;
19756 +
19757 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
19758 + }
19759 +
19760 + return result;
19761 +}
19762 +
19763 +bool
19764 +sb_iscoreup(sb_t *sbh)
19765 +{
19766 + sb_info_t *si;
19767 + sbconfig_t *sb;
19768 +
19769 + si = SB_INFO(sbh);
19770 + sb = REGS2SB(si->curmap);
19771 +
19772 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
19773 +}
19774 +
19775 +/*
19776 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
19777 + * switch back to the original core, and return the new value.
19778 + */
19779 +static uint
19780 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
19781 +{
19782 + uint origidx;
19783 + uint32 *r;
19784 + uint w;
19785 + uint intr_val = 0;
19786 +
19787 + ASSERT(GOODIDX(coreidx));
19788 + ASSERT(regoff < SB_CORE_SIZE);
19789 + ASSERT((val & ~mask) == 0);
19790 +
19791 + INTR_OFF(si, intr_val);
19792 +
19793 + /* save current core index */
19794 + origidx = sb_coreidx(&si->sb);
19795 +
19796 + /* switch core */
19797 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
19798 +
19799 + /* mask and set */
19800 + if (mask || val) {
19801 + if (regoff >= SBCONFIGOFF) {
19802 + w = (R_SBREG(si, r) & ~mask) | val;
19803 + W_SBREG(si, r, w);
19804 + } else {
19805 + w = (R_REG(r) & ~mask) | val;
19806 + W_REG(r, w);
19807 + }
19808 + }
19809 +
19810 + /* readback */
19811 + if (regoff >= SBCONFIGOFF)
19812 + w = R_SBREG(si, r);
19813 + else
19814 + w = R_REG(r);
19815 +
19816 + /* restore core index */
19817 + if (origidx != coreidx)
19818 + sb_setcoreidx(&si->sb, origidx);
19819 +
19820 + INTR_RESTORE(si, intr_val);
19821 + return (w);
19822 +}
19823 +
19824 +#define DWORD_ALIGN(x) (x & ~(0x03))
19825 +#define BYTE_POS(x) (x & 0x3)
19826 +#define WORD_POS(x) (x & 0x1)
19827 +
19828 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
19829 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
19830 +
19831 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
19832 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
19833 +
19834 +#define read_pci_cfg_byte(a) \
19835 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
19836 +
19837 +#define read_pci_cfg_write(a) \
19838 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
19839 +
19840 +
19841 +/* return TRUE if requested capability exists in the PCI config space */
19842 +static bool
19843 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
19844 +{
19845 + uint8 cap_id;
19846 + uint8 cap_ptr;
19847 + uint32 bufsize;
19848 + uint8 byte_val;
19849 +
19850 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
19851 + return FALSE;
19852 +
19853 + /* check for Header type 0*/
19854 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
19855 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
19856 + return FALSE;
19857 +
19858 + /* check if the capability pointer field exists */
19859 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
19860 + if (!(byte_val & PCI_CAPPTR_PRESENT))
19861 + return FALSE;
19862 +
19863 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
19864 + /* check if the capability pointer is 0x00 */
19865 + if (cap_ptr == 0x00)
19866 + return FALSE;
19867 +
19868 +
19869 + /* loop thr'u the capability list and see if the pcie capabilty exists */
19870 +
19871 + cap_id = read_pci_cfg_byte(cap_ptr);
19872 +
19873 + while (cap_id != req_cap_id) {
19874 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
19875 + if (cap_ptr == 0x00) break;
19876 + cap_id = read_pci_cfg_byte(cap_ptr);
19877 + }
19878 + if (cap_id != req_cap_id) {
19879 + return FALSE;
19880 + }
19881 + /* found the caller requested capability */
19882 + if ((buf != NULL) && (buflen != NULL)) {
19883 + bufsize = *buflen;
19884 + if (!bufsize) goto end;
19885 + *buflen = 0;
19886 + /* copy the cpability data excluding cap ID and next ptr */
19887 + cap_ptr += 2;
19888 + if ((bufsize + cap_ptr) > SZPCR)
19889 + bufsize = SZPCR - cap_ptr;
19890 + *buflen = bufsize;
19891 + while (bufsize--) {
19892 + *buf = read_pci_cfg_byte(cap_ptr);
19893 + cap_ptr++;
19894 + buf++;
19895 + }
19896 + }
19897 +end:
19898 + return TRUE;
19899 +}
19900 +
19901 +/* return TRUE if PCIE capability exists the pci config space */
19902 +static bool
19903 +sb_ispcie(sb_info_t *si)
19904 +{
19905 + return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
19906 +}
19907 +
19908 +/* scan the sb enumerated space to identify all cores */
19909 +static void
19910 +BCMINITFN(sb_scan)(sb_info_t *si)
19911 +{
19912 + uint origidx;
19913 + uint i;
19914 + bool pci;
19915 + bool pcie;
19916 + uint pciidx;
19917 + uint pcieidx;
19918 + uint pcirev;
19919 + uint pcierev;
19920 +
19921 +
19922 +
19923 + /* numcores should already be set */
19924 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
19925 +
19926 + /* save current core index */
19927 + origidx = sb_coreidx(&si->sb);
19928 +
19929 + si->sb.buscorerev = NOREV;
19930 + si->sb.buscoreidx = BADIDX;
19931 +
19932 + si->gpioidx = BADIDX;
19933 +
19934 + pci = pcie = FALSE;
19935 + pcirev = pcierev = NOREV;
19936 + pciidx = pcieidx = BADIDX;
19937 +
19938 + for (i = 0; i < si->numcores; i++) {
19939 + sb_setcoreidx(&si->sb, i);
19940 + si->coreid[i] = sb_coreid(&si->sb);
19941 +
19942 + if (si->coreid[i] == SB_PCI) {
19943 + pciidx = i;
19944 + pcirev = sb_corerev(&si->sb);
19945 + pci = TRUE;
19946 + } else if (si->coreid[i] == SB_PCIE) {
19947 + pcieidx = i;
19948 + pcierev = sb_corerev(&si->sb);
19949 + pcie = TRUE;
19950 + } else if (si->coreid[i] == SB_PCMCIA) {
19951 + si->sb.buscorerev = sb_corerev(&si->sb);
19952 + si->sb.buscoretype = si->coreid[i];
19953 + si->sb.buscoreidx = i;
19954 + }
19955 + }
19956 + if (pci && pcie) {
19957 + if (sb_ispcie(si))
19958 + pci = FALSE;
19959 + else
19960 + pcie = FALSE;
19961 + }
19962 + if (pci) {
19963 + si->sb.buscoretype = SB_PCI;
19964 + si->sb.buscorerev = pcirev;
19965 + si->sb.buscoreidx = pciidx;
19966 + }
19967 + else if (pcie) {
19968 + si->sb.buscoretype = SB_PCIE;
19969 + si->sb.buscorerev = pcierev;
19970 + si->sb.buscoreidx = pcieidx;
19971 + }
19972 +
19973 + /*
19974 + * Find the gpio "controlling core" type and index.
19975 + * Precedence:
19976 + * - if there's a chip common core - use that
19977 + * - else if there's a pci core (rev >= 2) - use that
19978 + * - else there had better be an extif core (4710 only)
19979 + */
19980 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
19981 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
19982 + si->gpioid = SB_CC;
19983 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
19984 + si->gpioidx = si->sb.buscoreidx;
19985 + si->gpioid = SB_PCI;
19986 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
19987 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
19988 + si->gpioid = SB_EXTIF;
19989 + } else
19990 + ASSERT(si->gpioidx != BADIDX);
19991 +
19992 + /* return to original core index */
19993 + sb_setcoreidx(&si->sb, origidx);
19994 +}
19995 +
19996 +/* may be called with core in reset */
19997 +void
19998 +sb_detach(sb_t *sbh)
19999 +{
20000 + sb_info_t *si;
20001 + uint idx;
20002 +
20003 + si = SB_INFO(sbh);
20004 +
20005 + if (si == NULL)
20006 + return;
20007 +
20008 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
20009 + for (idx = 0; idx < SB_MAXCORES; idx++)
20010 + if (si->regs[idx]) {
20011 + REG_UNMAP(si->regs[idx]);
20012 + si->regs[idx] = NULL;
20013 + }
20014 +
20015 + if (si != &ksi)
20016 + MFREE(si->osh, si, sizeof (sb_info_t));
20017 +}
20018 +
20019 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
20020 +static uint
20021 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
20022 +{
20023 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
20024 + return (BCM4710_DEVICE_ID);
20025 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
20026 + return (BCM4402_DEVICE_ID);
20027 + if (pcidev == BCM4401_ENET_ID)
20028 + return (BCM4402_DEVICE_ID);
20029 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
20030 + return (BCM4307_DEVICE_ID);
20031 + if (pcidev == BCM4301_DEVICE_ID)
20032 + return (BCM4301_DEVICE_ID);
20033 +
20034 + return (0);
20035 +}
20036 +
20037 +/* convert chip number to number of i/o cores */
20038 +static uint
20039 +BCMINITFN(sb_chip2numcores)(uint chip)
20040 +{
20041 + if (chip == BCM4710_DEVICE_ID)
20042 + return (9);
20043 + if (chip == BCM4402_DEVICE_ID)
20044 + return (3);
20045 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
20046 + return (5);
20047 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
20048 + return (6);
20049 + if (chip == BCM4704_DEVICE_ID)
20050 + return (9);
20051 + if (chip == BCM5365_DEVICE_ID)
20052 + return (7);
20053 +
20054 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
20055 + ASSERT(0);
20056 + return (1);
20057 +}
20058 +
20059 +/* return index of coreid or BADIDX if not found */
20060 +static uint
20061 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
20062 +{
20063 + uint found;
20064 + uint i;
20065 +
20066 + found = 0;
20067 +
20068 + for (i = 0; i < si->numcores; i++)
20069 + if (si->coreid[i] == coreid) {
20070 + if (found == coreunit)
20071 + return (i);
20072 + found++;
20073 + }
20074 +
20075 + return (BADIDX);
20076 +}
20077 +
20078 +/*
20079 + * this function changes logical "focus" to the indiciated core,
20080 + * must be called with interrupt off.
20081 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20082 + */
20083 +void*
20084 +sb_setcoreidx(sb_t *sbh, uint coreidx)
20085 +{
20086 + sb_info_t *si;
20087 + uint32 sbaddr;
20088 + uint8 tmp;
20089 +
20090 + si = SB_INFO(sbh);
20091 +
20092 + if (coreidx >= si->numcores)
20093 + return (NULL);
20094 +
20095 + /*
20096 + * If the user has provided an interrupt mask enabled function,
20097 + * then assert interrupts are disabled before switching the core.
20098 + */
20099 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
20100 +
20101 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
20102 +
20103 + switch (BUSTYPE(si->sb.bustype)) {
20104 + case SB_BUS:
20105 + /* map new one */
20106 + if (!si->regs[coreidx]) {
20107 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
20108 + ASSERT(GOODREGS(si->regs[coreidx]));
20109 + }
20110 + si->curmap = si->regs[coreidx];
20111 + break;
20112 +
20113 + case PCI_BUS:
20114 + /* point bar0 window */
20115 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
20116 + break;
20117 +
20118 + case PCMCIA_BUS:
20119 + tmp = (sbaddr >> 12) & 0x0f;
20120 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
20121 + tmp = (sbaddr >> 16) & 0xff;
20122 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
20123 + tmp = (sbaddr >> 24) & 0xff;
20124 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
20125 + break;
20126 +#ifdef BCMJTAG
20127 + case JTAG_BUS:
20128 + /* map new one */
20129 + if (!si->regs[coreidx]) {
20130 + si->regs[coreidx] = (void *)sbaddr;
20131 + ASSERT(GOODREGS(si->regs[coreidx]));
20132 + }
20133 + si->curmap = si->regs[coreidx];
20134 + break;
20135 +#endif /* BCMJTAG */
20136 + }
20137 +
20138 + si->curidx = coreidx;
20139 +
20140 + return (si->curmap);
20141 +}
20142 +
20143 +/*
20144 + * this function changes logical "focus" to the indiciated core,
20145 + * must be called with interrupt off.
20146 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20147 + */
20148 +void*
20149 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
20150 +{
20151 + sb_info_t *si;
20152 + uint idx;
20153 +
20154 + si = SB_INFO(sbh);
20155 + idx = sb_findcoreidx(si, coreid, coreunit);
20156 + if (!GOODIDX(idx))
20157 + return (NULL);
20158 +
20159 + return (sb_setcoreidx(sbh, idx));
20160 +}
20161 +
20162 +/* return chip number */
20163 +uint
20164 +BCMINITFN(sb_chip)(sb_t *sbh)
20165 +{
20166 + sb_info_t *si;
20167 +
20168 + si = SB_INFO(sbh);
20169 + return (si->sb.chip);
20170 +}
20171 +
20172 +/* return chip revision number */
20173 +uint
20174 +BCMINITFN(sb_chiprev)(sb_t *sbh)
20175 +{
20176 + sb_info_t *si;
20177 +
20178 + si = SB_INFO(sbh);
20179 + return (si->sb.chiprev);
20180 +}
20181 +
20182 +/* return chip common revision number */
20183 +uint
20184 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
20185 +{
20186 + sb_info_t *si;
20187 +
20188 + si = SB_INFO(sbh);
20189 + return (si->sb.ccrev);
20190 +}
20191 +
20192 +/* return chip package option */
20193 +uint
20194 +BCMINITFN(sb_chippkg)(sb_t *sbh)
20195 +{
20196 + sb_info_t *si;
20197 +
20198 + si = SB_INFO(sbh);
20199 + return (si->sb.chippkg);
20200 +}
20201 +
20202 +/* return PCI core rev. */
20203 +uint
20204 +BCMINITFN(sb_pcirev)(sb_t *sbh)
20205 +{
20206 + sb_info_t *si;
20207 +
20208 + si = SB_INFO(sbh);
20209 + return (si->sb.buscorerev);
20210 +}
20211 +
20212 +bool
20213 +BCMINITFN(sb_war16165)(sb_t *sbh)
20214 +{
20215 + sb_info_t *si;
20216 +
20217 + si = SB_INFO(sbh);
20218 +
20219 + return (PCI(si) && (si->sb.buscorerev <= 10));
20220 +}
20221 +
20222 +static void
20223 +BCMINITFN(sb_war30841)(sb_info_t *si)
20224 +{
20225 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
20226 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
20227 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
20228 +}
20229 +
20230 +/* return PCMCIA core rev. */
20231 +uint
20232 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
20233 +{
20234 + sb_info_t *si;
20235 +
20236 + si = SB_INFO(sbh);
20237 + return (si->sb.buscorerev);
20238 +}
20239 +
20240 +/* return board vendor id */
20241 +uint
20242 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
20243 +{
20244 + sb_info_t *si;
20245 +
20246 + si = SB_INFO(sbh);
20247 + return (si->sb.boardvendor);
20248 +}
20249 +
20250 +/* return boardtype */
20251 +uint
20252 +BCMINITFN(sb_boardtype)(sb_t *sbh)
20253 +{
20254 + sb_info_t *si;
20255 + char *var;
20256 +
20257 + si = SB_INFO(sbh);
20258 +
20259 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
20260 + /* boardtype format is a hex string */
20261 + si->sb.boardtype = getintvar(NULL, "boardtype");
20262 +
20263 + /* backward compatibility for older boardtype string format */
20264 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
20265 + if (!strcmp(var, "bcm94710dev"))
20266 + si->sb.boardtype = BCM94710D_BOARD;
20267 + else if (!strcmp(var, "bcm94710ap"))
20268 + si->sb.boardtype = BCM94710AP_BOARD;
20269 + else if (!strcmp(var, "bu4710"))
20270 + si->sb.boardtype = BU4710_BOARD;
20271 + else if (!strcmp(var, "bcm94702mn"))
20272 + si->sb.boardtype = BCM94702MN_BOARD;
20273 + else if (!strcmp(var, "bcm94710r1"))
20274 + si->sb.boardtype = BCM94710R1_BOARD;
20275 + else if (!strcmp(var, "bcm94710r4"))
20276 + si->sb.boardtype = BCM94710R4_BOARD;
20277 + else if (!strcmp(var, "bcm94702cpci"))
20278 + si->sb.boardtype = BCM94702CPCI_BOARD;
20279 + else if (!strcmp(var, "bcm95380_rr"))
20280 + si->sb.boardtype = BCM95380RR_BOARD;
20281 + }
20282 + }
20283 +
20284 + return (si->sb.boardtype);
20285 +}
20286 +
20287 +/* return bus type of sbh device */
20288 +uint
20289 +sb_bus(sb_t *sbh)
20290 +{
20291 + sb_info_t *si;
20292 +
20293 + si = SB_INFO(sbh);
20294 + return (si->sb.bustype);
20295 +}
20296 +
20297 +/* return bus core type */
20298 +uint
20299 +sb_buscoretype(sb_t *sbh)
20300 +{
20301 + sb_info_t *si;
20302 +
20303 + si = SB_INFO(sbh);
20304 +
20305 + return (si->sb.buscoretype);
20306 +}
20307 +
20308 +/* return bus core revision */
20309 +uint
20310 +sb_buscorerev(sb_t *sbh)
20311 +{
20312 + sb_info_t *si;
20313 + si = SB_INFO(sbh);
20314 +
20315 + return (si->sb.buscorerev);
20316 +}
20317 +
20318 +/* return list of found cores */
20319 +uint
20320 +sb_corelist(sb_t *sbh, uint coreid[])
20321 +{
20322 + sb_info_t *si;
20323 +
20324 + si = SB_INFO(sbh);
20325 +
20326 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
20327 + return (si->numcores);
20328 +}
20329 +
20330 +/* return current register mapping */
20331 +void *
20332 +sb_coreregs(sb_t *sbh)
20333 +{
20334 + sb_info_t *si;
20335 +
20336 + si = SB_INFO(sbh);
20337 + ASSERT(GOODREGS(si->curmap));
20338 +
20339 + return (si->curmap);
20340 +}
20341 +
20342 +
20343 +/* do buffered registers update */
20344 +void
20345 +sb_commit(sb_t *sbh)
20346 +{
20347 + sb_info_t *si;
20348 + uint origidx;
20349 + uint intr_val = 0;
20350 +
20351 + si = SB_INFO(sbh);
20352 +
20353 + origidx = si->curidx;
20354 + ASSERT(GOODIDX(origidx));
20355 +
20356 + INTR_OFF(si, intr_val);
20357 +
20358 + /* switch over to chipcommon core if there is one, else use pci */
20359 + if (si->sb.ccrev != NOREV) {
20360 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
20361 +
20362 + /* do the buffer registers update */
20363 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
20364 + W_REG(&ccregs->broadcastdata, 0x0);
20365 + } else if (PCI(si)) {
20366 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
20367 +
20368 + /* do the buffer registers update */
20369 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
20370 + W_REG(&pciregs->bcastdata, 0x0);
20371 + } else
20372 + ASSERT(0);
20373 +
20374 + /* restore core index */
20375 + sb_setcoreidx(sbh, origidx);
20376 + INTR_RESTORE(si, intr_val);
20377 +}
20378 +
20379 +/* reset and re-enable a core */
20380 +void
20381 +sb_core_reset(sb_t *sbh, uint32 bits)
20382 +{
20383 + sb_info_t *si;
20384 + sbconfig_t *sb;
20385 + volatile uint32 dummy;
20386 +
20387 + si = SB_INFO(sbh);
20388 + ASSERT(GOODREGS(si->curmap));
20389 + sb = REGS2SB(si->curmap);
20390 +
20391 + /*
20392 + * Must do the disable sequence first to work for arbitrary current core state.
20393 + */
20394 + sb_core_disable(sbh, bits);
20395 +
20396 + /*
20397 + * Now do the initialization sequence.
20398 + */
20399 +
20400 + /* set reset while enabling the clock and forcing them on throughout the core */
20401 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
20402 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20403 + OSL_DELAY(1);
20404 +
20405 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
20406 + W_SBREG(si, &sb->sbtmstatehigh, 0);
20407 + }
20408 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
20409 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
20410 + }
20411 +
20412 + /* clear reset and allow it to propagate throughout the core */
20413 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
20414 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20415 + OSL_DELAY(1);
20416 +
20417 + /* leave clock enabled */
20418 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
20419 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20420 + OSL_DELAY(1);
20421 +}
20422 +
20423 +void
20424 +sb_core_tofixup(sb_t *sbh)
20425 +{
20426 + sb_info_t *si;
20427 + sbconfig_t *sb;
20428 +
20429 + si = SB_INFO(sbh);
20430 +
20431 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
20432 + return;
20433 +
20434 + ASSERT(GOODREGS(si->curmap));
20435 + sb = REGS2SB(si->curmap);
20436 +
20437 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
20438 + SET_SBREG(si, &sb->sbimconfiglow,
20439 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20440 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
20441 + } else {
20442 + if (sb_coreid(sbh) == SB_PCI) {
20443 + SET_SBREG(si, &sb->sbimconfiglow,
20444 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20445 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20446 + } else {
20447 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
20448 + }
20449 + }
20450 +
20451 + sb_commit(sbh);
20452 +}
20453 +
20454 +/*
20455 + * Set the initiator timeout for the "master core".
20456 + * The master core is defined to be the core in control
20457 + * of the chip and so it issues accesses to non-memory
20458 + * locations (Because of dma *any* core can access memeory).
20459 + *
20460 + * The routine uses the bus to decide who is the master:
20461 + * SB_BUS => mips
20462 + * JTAG_BUS => chipc
20463 + * PCI_BUS => pci or pcie
20464 + * PCMCIA_BUS => pcmcia
20465 + * SDIO_BUS => pcmcia
20466 + *
20467 + * This routine exists so callers can disable initiator
20468 + * timeouts so accesses to very slow devices like otp
20469 + * won't cause an abort. The routine allows arbitrary
20470 + * settings of the service and request timeouts, though.
20471 + *
20472 + * Returns the timeout state before changing it or -1
20473 + * on error.
20474 + */
20475 +
20476 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
20477 +
20478 +uint32
20479 +sb_set_initiator_to(sb_t *sbh, uint32 to)
20480 +{
20481 + sb_info_t *si;
20482 + uint origidx, idx;
20483 + uint intr_val = 0;
20484 + uint32 tmp, ret = 0xffffffff;
20485 + sbconfig_t *sb;
20486 +
20487 + si = SB_INFO(sbh);
20488 +
20489 + if ((to & ~TO_MASK) != 0)
20490 + return ret;
20491 +
20492 + /* Figure out the master core */
20493 + idx = BADIDX;
20494 + switch (BUSTYPE(si->sb.bustype)) {
20495 + case PCI_BUS:
20496 + idx = si->sb.buscoreidx;
20497 + break;
20498 + case JTAG_BUS:
20499 + idx = SB_CC_IDX;
20500 + break;
20501 + case PCMCIA_BUS:
20502 + case SDIO_BUS:
20503 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
20504 + break;
20505 + case SB_BUS:
20506 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
20507 + idx = sb_findcoreidx(si, SB_MIPS, 0);
20508 + break;
20509 + default:
20510 + ASSERT(0);
20511 + }
20512 + if (idx == BADIDX)
20513 + return ret;
20514 +
20515 + INTR_OFF(si, intr_val);
20516 + origidx = sb_coreidx(sbh);
20517 +
20518 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
20519 +
20520 + tmp = R_SBREG(si, &sb->sbimconfiglow);
20521 + ret = tmp & TO_MASK;
20522 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
20523 +
20524 + sb_commit(sbh);
20525 + sb_setcoreidx(sbh, origidx);
20526 + INTR_RESTORE(si, intr_val);
20527 + return ret;
20528 +}
20529 +
20530 +void
20531 +sb_core_disable(sb_t *sbh, uint32 bits)
20532 +{
20533 + sb_info_t *si;
20534 + volatile uint32 dummy;
20535 + uint32 rej;
20536 + sbconfig_t *sb;
20537 +
20538 + si = SB_INFO(sbh);
20539 +
20540 + ASSERT(GOODREGS(si->curmap));
20541 + sb = REGS2SB(si->curmap);
20542 +
20543 + /* if core is already in reset, just return */
20544 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
20545 + return;
20546 +
20547 + /* reject value changed between sonics 2.2 and 2.3 */
20548 + if (si->sb.sonicsrev == SONICS_2_2)
20549 + rej = (1 << SBTML_REJ_SHIFT);
20550 + else
20551 + rej = (2 << SBTML_REJ_SHIFT);
20552 +
20553 + /* if clocks are not enabled, put into reset and return */
20554 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
20555 + goto disable;
20556 +
20557 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
20558 + OR_SBREG(si, &sb->sbtmstatelow, rej);
20559 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20560 + OSL_DELAY(1);
20561 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
20562 +
20563 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
20564 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
20565 + dummy = R_SBREG(si, &sb->sbimstate);
20566 + OSL_DELAY(1);
20567 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
20568 + }
20569 +
20570 + /* set reset and reject while enabling the clocks */
20571 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
20572 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20573 + OSL_DELAY(10);
20574 +
20575 + /* don't forget to clear the initiator reject bit */
20576 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
20577 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
20578 +
20579 +disable:
20580 + /* leave reset and reject asserted */
20581 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
20582 + OSL_DELAY(1);
20583 +}
20584 +
20585 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
20586 +void
20587 +sb_watchdog(sb_t *sbh, uint ticks)
20588 +{
20589 + sb_info_t *si = SB_INFO(sbh);
20590 +
20591 + /* instant NMI */
20592 + switch (si->gpioid) {
20593 + case SB_CC:
20594 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
20595 + break;
20596 + case SB_EXTIF:
20597 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
20598 + break;
20599 + }
20600 +}
20601 +
20602 +/* initialize the pcmcia core */
20603 +void
20604 +sb_pcmcia_init(sb_t *sbh)
20605 +{
20606 + sb_info_t *si;
20607 + uint8 cor;
20608 +
20609 + si = SB_INFO(sbh);
20610 +
20611 + /* enable d11 mac interrupts */
20612 + if (si->sb.chip == BCM4301_DEVICE_ID) {
20613 + /* Have to use FCR2 in 4301 */
20614 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20615 + cor |= COR_IRQEN | COR_FUNEN;
20616 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20617 + } else {
20618 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20619 + cor |= COR_IRQEN | COR_FUNEN;
20620 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20621 + }
20622 +
20623 +}
20624 +
20625 +
20626 +/*
20627 + * Configure the pci core for pci client (NIC) action
20628 + * coremask is the bitvec of cores by index to be enabled.
20629 + */
20630 +void
20631 +sb_pci_setup(sb_t *sbh, uint coremask)
20632 +{
20633 + sb_info_t *si;
20634 + sbconfig_t *sb;
20635 + sbpciregs_t *pciregs;
20636 + uint32 sbflag;
20637 + uint32 w;
20638 + uint idx;
20639 + int reg_val;
20640 +
20641 + si = SB_INFO(sbh);
20642 +
20643 + /* if not pci bus, we're done */
20644 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
20645 + return;
20646 +
20647 + ASSERT(PCI(si) || PCIE(si));
20648 + ASSERT(si->sb.buscoreidx != BADIDX);
20649 +
20650 + /* get current core index */
20651 + idx = si->curidx;
20652 +
20653 + /* we interrupt on this backplane flag number */
20654 + ASSERT(GOODREGS(si->curmap));
20655 + sb = REGS2SB(si->curmap);
20656 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
20657 +
20658 + /* switch over to pci core */
20659 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
20660 + sb = REGS2SB(pciregs);
20661 +
20662 + /*
20663 + * Enable sb->pci interrupts. Assume
20664 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
20665 + */
20666 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
20667 + /* pci config write to set this core bit in PCIIntMask */
20668 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
20669 + w |= (coremask << PCI_SBIM_SHIFT);
20670 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
20671 + } else {
20672 + /* set sbintvec bit for our flag number */
20673 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
20674 + }
20675 +
20676 + if (PCI(si)) {
20677 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
20678 + if (si->sb.buscorerev >= 11)
20679 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
20680 + if (si->sb.buscorerev < 5) {
20681 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20682 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20683 + sb_commit(sbh);
20684 + }
20685 + }
20686 +
20687 + if (PCIE(si) && (si->sb.buscorerev == 0)) {
20688 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
20689 + reg_val |= 0x8;
20690 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
20691 +
20692 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
20693 + reg_val &= ~(0x40);
20694 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
20695 +
20696 + BCMINIT(sb_war30841)(si);
20697 + }
20698 +
20699 + /* switch back to previous core */
20700 + sb_setcoreidx(sbh, idx);
20701 +}
20702 +
20703 +uint32
20704 +sb_base(uint32 admatch)
20705 +{
20706 + uint32 base;
20707 + uint type;
20708 +
20709 + type = admatch & SBAM_TYPE_MASK;
20710 + ASSERT(type < 3);
20711 +
20712 + base = 0;
20713 +
20714 + if (type == 0) {
20715 + base = admatch & SBAM_BASE0_MASK;
20716 + } else if (type == 1) {
20717 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20718 + base = admatch & SBAM_BASE1_MASK;
20719 + } else if (type == 2) {
20720 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20721 + base = admatch & SBAM_BASE2_MASK;
20722 + }
20723 +
20724 + return (base);
20725 +}
20726 +
20727 +uint32
20728 +sb_size(uint32 admatch)
20729 +{
20730 + uint32 size;
20731 + uint type;
20732 +
20733 + type = admatch & SBAM_TYPE_MASK;
20734 + ASSERT(type < 3);
20735 +
20736 + size = 0;
20737 +
20738 + if (type == 0) {
20739 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
20740 + } else if (type == 1) {
20741 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20742 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
20743 + } else if (type == 2) {
20744 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20745 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
20746 + }
20747 +
20748 + return (size);
20749 +}
20750 +
20751 +/* return the core-type instantiation # of the current core */
20752 +uint
20753 +sb_coreunit(sb_t *sbh)
20754 +{
20755 + sb_info_t *si;
20756 + uint idx;
20757 + uint coreid;
20758 + uint coreunit;
20759 + uint i;
20760 +
20761 + si = SB_INFO(sbh);
20762 + coreunit = 0;
20763 +
20764 + idx = si->curidx;
20765 +
20766 + ASSERT(GOODREGS(si->curmap));
20767 + coreid = sb_coreid(sbh);
20768 +
20769 + /* count the cores of our type */
20770 + for (i = 0; i < idx; i++)
20771 + if (si->coreid[i] == coreid)
20772 + coreunit++;
20773 +
20774 + return (coreunit);
20775 +}
20776 +
20777 +static INLINE uint32
20778 +factor6(uint32 x)
20779 +{
20780 + switch (x) {
20781 + case CC_F6_2: return 2;
20782 + case CC_F6_3: return 3;
20783 + case CC_F6_4: return 4;
20784 + case CC_F6_5: return 5;
20785 + case CC_F6_6: return 6;
20786 + case CC_F6_7: return 7;
20787 + default: return 0;
20788 + }
20789 +}
20790 +
20791 +/* calculate the speed the SB would run at given a set of clockcontrol values */
20792 +uint32
20793 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
20794 +{
20795 + uint32 n1, n2, clock, m1, m2, m3, mc;
20796 +
20797 + n1 = n & CN_N1_MASK;
20798 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
20799 +
20800 + if (pll_type == PLL_TYPE6) {
20801 + if (m & CC_T6_MMASK)
20802 + return CC_T6_M1;
20803 + else
20804 + return CC_T6_M0;
20805 + } else if ((pll_type == PLL_TYPE1) ||
20806 + (pll_type == PLL_TYPE3) ||
20807 + (pll_type == PLL_TYPE4) ||
20808 + (pll_type == PLL_TYPE7)) {
20809 + n1 = factor6(n1);
20810 + n2 += CC_F5_BIAS;
20811 + } else if (pll_type == PLL_TYPE2) {
20812 + n1 += CC_T2_BIAS;
20813 + n2 += CC_T2_BIAS;
20814 + ASSERT((n1 >= 2) && (n1 <= 7));
20815 + ASSERT((n2 >= 5) && (n2 <= 23));
20816 + } else if (pll_type == PLL_TYPE5) {
20817 + return (100000000);
20818 + } else
20819 + ASSERT(0);
20820 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
20821 + if ((pll_type == PLL_TYPE3) ||
20822 + (pll_type == PLL_TYPE7)) {
20823 + clock = CC_CLOCK_BASE2 * n1 * n2;
20824 + }
20825 + else
20826 + clock = CC_CLOCK_BASE1 * n1 * n2;
20827 +
20828 + if (clock == 0)
20829 + return 0;
20830 +
20831 + m1 = m & CC_M1_MASK;
20832 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
20833 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
20834 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
20835 +
20836 + if ((pll_type == PLL_TYPE1) ||
20837 + (pll_type == PLL_TYPE3) ||
20838 + (pll_type == PLL_TYPE4) ||
20839 + (pll_type == PLL_TYPE7)) {
20840 + m1 = factor6(m1);
20841 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
20842 + m2 += CC_F5_BIAS;
20843 + else
20844 + m2 = factor6(m2);
20845 + m3 = factor6(m3);
20846 +
20847 + switch (mc) {
20848 + case CC_MC_BYPASS: return (clock);
20849 + case CC_MC_M1: return (clock / m1);
20850 + case CC_MC_M1M2: return (clock / (m1 * m2));
20851 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
20852 + case CC_MC_M1M3: return (clock / (m1 * m3));
20853 + default: return (0);
20854 + }
20855 + } else {
20856 + ASSERT(pll_type == PLL_TYPE2);
20857 +
20858 + m1 += CC_T2_BIAS;
20859 + m2 += CC_T2M2_BIAS;
20860 + m3 += CC_T2_BIAS;
20861 + ASSERT((m1 >= 2) && (m1 <= 7));
20862 + ASSERT((m2 >= 3) && (m2 <= 10));
20863 + ASSERT((m3 >= 2) && (m3 <= 7));
20864 +
20865 + if ((mc & CC_T2MC_M1BYP) == 0)
20866 + clock /= m1;
20867 + if ((mc & CC_T2MC_M2BYP) == 0)
20868 + clock /= m2;
20869 + if ((mc & CC_T2MC_M3BYP) == 0)
20870 + clock /= m3;
20871 +
20872 + return(clock);
20873 + }
20874 +}
20875 +
20876 +/* returns the current speed the SB is running at */
20877 +uint32
20878 +sb_clock(sb_t *sbh)
20879 +{
20880 + sb_info_t *si;
20881 + extifregs_t *eir;
20882 + chipcregs_t *cc;
20883 + uint32 n, m;
20884 + uint idx;
20885 + uint32 pll_type, rate;
20886 + uint intr_val = 0;
20887 +
20888 + si = SB_INFO(sbh);
20889 + idx = si->curidx;
20890 + pll_type = PLL_TYPE1;
20891 +
20892 + INTR_OFF(si, intr_val);
20893 +
20894 + /* switch to extif or chipc core */
20895 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
20896 + n = R_REG(&eir->clockcontrol_n);
20897 + m = R_REG(&eir->clockcontrol_sb);
20898 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
20899 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
20900 + n = R_REG(&cc->clockcontrol_n);
20901 + if (pll_type == PLL_TYPE6)
20902 + m = R_REG(&cc->clockcontrol_mips);
20903 + else if (pll_type == PLL_TYPE3)
20904 + {
20905 + // Added by Chen-I for 5365
20906 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
20907 + m = R_REG(&cc->clockcontrol_sb);
20908 + else
20909 + m = R_REG(&cc->clockcontrol_m2);
20910 + }
20911 + else
20912 + m = R_REG(&cc->clockcontrol_sb);
20913 + } else {
20914 + INTR_RESTORE(si, intr_val);
20915 + return 0;
20916 + }
20917 +
20918 + // Added by Chen-I for 5365
20919 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
20920 + {
20921 + rate = 100000000;
20922 + }
20923 + else
20924 + {
20925 + /* calculate rate */
20926 + rate = sb_clock_rate(pll_type, n, m);
20927 + if (pll_type == PLL_TYPE3)
20928 + rate = rate / 2;
20929 + }
20930 +
20931 + /* switch back to previous core */
20932 + sb_setcoreidx(sbh, idx);
20933 +
20934 + INTR_RESTORE(si, intr_val);
20935 +
20936 + return rate;
20937 +}
20938 +
20939 +/* change logical "focus" to the gpio core for optimized access */
20940 +void*
20941 +sb_gpiosetcore(sb_t *sbh)
20942 +{
20943 + sb_info_t *si;
20944 +
20945 + si = SB_INFO(sbh);
20946 +
20947 + return (sb_setcoreidx(sbh, si->gpioidx));
20948 +}
20949 +
20950 +/* mask&set gpiocontrol bits */
20951 +uint32
20952 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
20953 +{
20954 + sb_info_t *si;
20955 + uint regoff;
20956 +
20957 + si = SB_INFO(sbh);
20958 + regoff = 0;
20959 +
20960 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20961 +
20962 + /* gpios could be shared on router platforms */
20963 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
20964 + mask = priority ? (sb_gpioreservation & mask) :
20965 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
20966 + val &= mask;
20967 + }
20968 +
20969 + switch (si->gpioid) {
20970 + case SB_CC:
20971 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
20972 + break;
20973 +
20974 + case SB_PCI:
20975 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
20976 + break;
20977 +
20978 + case SB_EXTIF:
20979 + return (0);
20980 + }
20981 +
20982 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
20983 +}
20984 +
20985 +/* mask&set gpio output enable bits */
20986 +uint32
20987 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
20988 +{
20989 + sb_info_t *si;
20990 + uint regoff;
20991 +
20992 + si = SB_INFO(sbh);
20993 + regoff = 0;
20994 +
20995 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20996 +
20997 + /* gpios could be shared on router platforms */
20998 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
20999 + mask = priority ? (sb_gpioreservation & mask) :
21000 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21001 + val &= mask;
21002 + }
21003 +
21004 + switch (si->gpioid) {
21005 + case SB_CC:
21006 + regoff = OFFSETOF(chipcregs_t, gpioouten);
21007 + break;
21008 +
21009 + case SB_PCI:
21010 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
21011 + break;
21012 +
21013 + case SB_EXTIF:
21014 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
21015 + break;
21016 + }
21017 +
21018 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21019 +}
21020 +
21021 +/* mask&set gpio output bits */
21022 +uint32
21023 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21024 +{
21025 + sb_info_t *si;
21026 + uint regoff;
21027 +
21028 + si = SB_INFO(sbh);
21029 + regoff = 0;
21030 +
21031 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21032 +
21033 + /* gpios could be shared on router platforms */
21034 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21035 + mask = priority ? (sb_gpioreservation & mask) :
21036 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21037 + val &= mask;
21038 + }
21039 +
21040 + switch (si->gpioid) {
21041 + case SB_CC:
21042 + regoff = OFFSETOF(chipcregs_t, gpioout);
21043 + break;
21044 +
21045 + case SB_PCI:
21046 + regoff = OFFSETOF(sbpciregs_t, gpioout);
21047 + break;
21048 +
21049 + case SB_EXTIF:
21050 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
21051 + break;
21052 + }
21053 +
21054 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21055 +}
21056 +
21057 +/* reserve one gpio */
21058 +uint32
21059 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21060 +{
21061 + sb_info_t *si;
21062 +
21063 + si = SB_INFO(sbh);
21064 +
21065 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21066 +
21067 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21068 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21069 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21070 + return -1;
21071 + }
21072 + /* make sure only one bit is set */
21073 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21074 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21075 + return -1;
21076 + }
21077 +
21078 + /* already reserved */
21079 + if (sb_gpioreservation & gpio_bitmask)
21080 + return -1;
21081 + /* set reservation */
21082 + sb_gpioreservation |= gpio_bitmask;
21083 +
21084 + return sb_gpioreservation;
21085 +}
21086 +
21087 +/* release one gpio */
21088 +/*
21089 + * releasing the gpio doesn't change the current value on the GPIO last write value
21090 + * persists till some one overwrites it
21091 +*/
21092 +
21093 +uint32
21094 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21095 +{
21096 + sb_info_t *si;
21097 +
21098 + si = SB_INFO(sbh);
21099 +
21100 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21101 +
21102 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21103 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21104 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21105 + return -1;
21106 + }
21107 + /* make sure only one bit is set */
21108 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21109 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21110 + return -1;
21111 + }
21112 +
21113 + /* already released */
21114 + if (!(sb_gpioreservation & gpio_bitmask))
21115 + return -1;
21116 +
21117 + /* clear reservation */
21118 + sb_gpioreservation &= ~gpio_bitmask;
21119 +
21120 + return sb_gpioreservation;
21121 +}
21122 +
21123 +/* return the current gpioin register value */
21124 +uint32
21125 +sb_gpioin(sb_t *sbh)
21126 +{
21127 + sb_info_t *si;
21128 + uint regoff;
21129 +
21130 + si = SB_INFO(sbh);
21131 + regoff = 0;
21132 +
21133 + switch (si->gpioid) {
21134 + case SB_CC:
21135 + regoff = OFFSETOF(chipcregs_t, gpioin);
21136 + break;
21137 +
21138 + case SB_PCI:
21139 + regoff = OFFSETOF(sbpciregs_t, gpioin);
21140 + break;
21141 +
21142 + case SB_EXTIF:
21143 + regoff = OFFSETOF(extifregs_t, gpioin);
21144 + break;
21145 + }
21146 +
21147 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
21148 +}
21149 +
21150 +/* mask&set gpio interrupt polarity bits */
21151 +uint32
21152 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21153 +{
21154 + sb_info_t *si;
21155 + uint regoff;
21156 +
21157 + si = SB_INFO(sbh);
21158 + regoff = 0;
21159 +
21160 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21161 +
21162 + /* gpios could be shared on router platforms */
21163 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21164 + mask = priority ? (sb_gpioreservation & mask) :
21165 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21166 + val &= mask;
21167 + }
21168 +
21169 + switch (si->gpioid) {
21170 + case SB_CC:
21171 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
21172 + break;
21173 +
21174 + case SB_PCI:
21175 + /* pci gpio implementation does not support interrupt polarity */
21176 + ASSERT(0);
21177 + break;
21178 +
21179 + case SB_EXTIF:
21180 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
21181 + break;
21182 + }
21183 +
21184 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21185 +}
21186 +
21187 +/* mask&set gpio interrupt mask bits */
21188 +uint32
21189 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21190 +{
21191 + sb_info_t *si;
21192 + uint regoff;
21193 +
21194 + si = SB_INFO(sbh);
21195 + regoff = 0;
21196 +
21197 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21198 +
21199 + /* gpios could be shared on router platforms */
21200 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21201 + mask = priority ? (sb_gpioreservation & mask) :
21202 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21203 + val &= mask;
21204 + }
21205 +
21206 + switch (si->gpioid) {
21207 + case SB_CC:
21208 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
21209 + break;
21210 +
21211 + case SB_PCI:
21212 + /* pci gpio implementation does not support interrupt mask */
21213 + ASSERT(0);
21214 + break;
21215 +
21216 + case SB_EXTIF:
21217 + regoff = OFFSETOF(extifregs_t, gpiointmask);
21218 + break;
21219 + }
21220 +
21221 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21222 +}
21223 +
21224 +/* assign the gpio to an led */
21225 +uint32
21226 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
21227 +{
21228 + sb_info_t *si;
21229 +
21230 + si = SB_INFO(sbh);
21231 + if (si->sb.ccrev < 16)
21232 + return -1;
21233 +
21234 + /* gpio led powersave reg */
21235 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
21236 +}
21237 +
21238 +/* mask&set gpio timer val */
21239 +uint32
21240 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
21241 +{
21242 + sb_info_t *si;
21243 + si = SB_INFO(sbh);
21244 +
21245 + if (si->sb.ccrev < 16)
21246 + return -1;
21247 +
21248 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
21249 +}
21250 +
21251 +
21252 +/* return the slow clock source - LPO, XTAL, or PCI */
21253 +static uint
21254 +sb_slowclk_src(sb_info_t *si)
21255 +{
21256 + chipcregs_t *cc;
21257 +
21258 +
21259 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21260 +
21261 + if (si->sb.ccrev < 6) {
21262 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
21263 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
21264 + return (SCC_SS_PCI);
21265 + else
21266 + return (SCC_SS_XTAL);
21267 + } else if (si->sb.ccrev < 10) {
21268 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21269 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
21270 + } else /* Insta-clock */
21271 + return (SCC_SS_XTAL);
21272 +}
21273 +
21274 +/* return the ILP (slowclock) min or max frequency */
21275 +static uint
21276 +sb_slowclk_freq(sb_info_t *si, bool max)
21277 +{
21278 + chipcregs_t *cc;
21279 + uint32 slowclk;
21280 + uint div;
21281 +
21282 +
21283 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21284 +
21285 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21286 +
21287 + /* shouldn't be here unless we've established the chip has dynamic clk control */
21288 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
21289 +
21290 + slowclk = sb_slowclk_src(si);
21291 + if (si->sb.ccrev < 6) {
21292 + if (slowclk == SCC_SS_PCI)
21293 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
21294 + else
21295 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
21296 + } else if (si->sb.ccrev < 10) {
21297 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21298 + if (slowclk == SCC_SS_LPO)
21299 + return (max? LPOMAXFREQ : LPOMINFREQ);
21300 + else if (slowclk == SCC_SS_XTAL)
21301 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
21302 + else if (slowclk == SCC_SS_PCI)
21303 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
21304 + else
21305 + ASSERT(0);
21306 + } else {
21307 + /* Chipc rev 10 is InstaClock */
21308 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
21309 + div = 4 * (div + 1);
21310 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
21311 + }
21312 + return (0);
21313 +}
21314 +
21315 +static void
21316 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
21317 +{
21318 + chipcregs_t * cc;
21319 + uint slowmaxfreq, pll_delay, slowclk;
21320 + uint pll_on_delay, fref_sel_delay;
21321 +
21322 + pll_delay = PLL_DELAY;
21323 +
21324 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
21325 + * since the xtal will also be powered down by dynamic clk control logic.
21326 + */
21327 + slowclk = sb_slowclk_src(si);
21328 + if (slowclk != SCC_SS_XTAL)
21329 + pll_delay += XTAL_ON_DELAY;
21330 +
21331 + /* Starting with 4318 it is ILP that is used for the delays */
21332 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
21333 +
21334 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
21335 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
21336 +
21337 + cc = (chipcregs_t *)chipcregs;
21338 + W_REG(&cc->pll_on_delay, pll_on_delay);
21339 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
21340 +}
21341 +
21342 +int
21343 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
21344 +{
21345 + sb_info_t *si;
21346 + uint origidx;
21347 + chipcregs_t *cc;
21348 + uint intr_val = 0;
21349 + uint err = 0;
21350 +
21351 + si = SB_INFO(sbh);
21352 +
21353 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
21354 + if (si->sb.ccrev < 6)
21355 + return 1;
21356 +
21357 + /* chipcommon cores rev10 are a whole new ball game */
21358 + if (si->sb.ccrev >= 10)
21359 + return 1;
21360 +
21361 + if (set && ((*div % 4) || (*div < 4)))
21362 + return 2;
21363 +
21364 + INTR_OFF(si, intr_val);
21365 + origidx = si->curidx;
21366 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21367 + ASSERT(cc != NULL);
21368 +
21369 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
21370 + err = 3;
21371 + goto done;
21372 + }
21373 +
21374 + if (set) {
21375 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
21376 + sb_clkctl_setdelay(sbh, (void *)cc);
21377 + } else
21378 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21379 +
21380 +done:
21381 + sb_setcoreidx(sbh, origidx);
21382 + INTR_RESTORE(si, intr_val);
21383 + return err;
21384 +}
21385 +
21386 +/* initialize power control delay registers */
21387 +void sb_clkctl_init(sb_t *sbh)
21388 +{
21389 + sb_info_t *si;
21390 + uint origidx;
21391 + chipcregs_t *cc;
21392 +
21393 + si = SB_INFO(sbh);
21394 +
21395 + origidx = si->curidx;
21396 +
21397 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21398 + return;
21399 +
21400 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21401 + goto done;
21402 +
21403 + /* 4317pc does not work with SlowClock less than 5 MHz */
21404 + if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
21405 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
21406 +
21407 + /* set all Instaclk chip ILP to 1 MHz */
21408 + else if (si->sb.ccrev >= 10)
21409 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
21410 +
21411 + sb_clkctl_setdelay(si, (void *)cc);
21412 +
21413 +done:
21414 + sb_setcoreidx(sbh, origidx);
21415 +}
21416 +void sb_pwrctl_init(sb_t *sbh)
21417 +{
21418 +sb_clkctl_init(sbh);
21419 +}
21420 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
21421 +uint16
21422 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
21423 +{
21424 + sb_info_t *si;
21425 + uint origidx;
21426 + chipcregs_t *cc;
21427 + uint slowminfreq;
21428 + uint16 fpdelay;
21429 + uint intr_val = 0;
21430 +
21431 + si = SB_INFO(sbh);
21432 + fpdelay = 0;
21433 + origidx = si->curidx;
21434 +
21435 + INTR_OFF(si, intr_val);
21436 +
21437 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21438 + goto done;
21439 +
21440 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21441 + goto done;
21442 +
21443 + slowminfreq = sb_slowclk_freq(si, FALSE);
21444 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
21445 +
21446 +done:
21447 + sb_setcoreidx(sbh, origidx);
21448 + INTR_RESTORE(si, intr_val);
21449 + return (fpdelay);
21450 +}
21451 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
21452 +{
21453 +return sb_clkctl_fast_pwrup_delay(sbh);
21454 +}
21455 +/* turn primary xtal and/or pll off/on */
21456 +int
21457 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
21458 +{
21459 + sb_info_t *si;
21460 + uint32 in, out, outen;
21461 +
21462 + si = SB_INFO(sbh);
21463 +
21464 + switch (BUSTYPE(si->sb.bustype)) {
21465 +
21466 +
21467 + case PCMCIA_BUS:
21468 + return (0);
21469 +
21470 +
21471 + case PCI_BUS:
21472 +
21473 + /* pcie core doesn't have any mapping to control the xtal pu */
21474 + if (PCIE(si))
21475 + return -1;
21476 +
21477 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
21478 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
21479 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
21480 +
21481 + /*
21482 + * Avoid glitching the clock if GPRS is already using it.
21483 + * We can't actually read the state of the PLLPD so we infer it
21484 + * by the value of XTAL_PU which *is* readable via gpioin.
21485 + */
21486 + if (on && (in & PCI_CFG_GPIO_XTAL))
21487 + return (0);
21488 +
21489 + if (what & XTAL)
21490 + outen |= PCI_CFG_GPIO_XTAL;
21491 + if (what & PLL)
21492 + outen |= PCI_CFG_GPIO_PLL;
21493 +
21494 + if (on) {
21495 + /* turn primary xtal on */
21496 + if (what & XTAL) {
21497 + out |= PCI_CFG_GPIO_XTAL;
21498 + if (what & PLL)
21499 + out |= PCI_CFG_GPIO_PLL;
21500 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21501 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21502 + OSL_DELAY(XTAL_ON_DELAY);
21503 + }
21504 +
21505 + /* turn pll on */
21506 + if (what & PLL) {
21507 + out &= ~PCI_CFG_GPIO_PLL;
21508 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21509 + OSL_DELAY(2000);
21510 + }
21511 + } else {
21512 + if (what & XTAL)
21513 + out &= ~PCI_CFG_GPIO_XTAL;
21514 + if (what & PLL)
21515 + out |= PCI_CFG_GPIO_PLL;
21516 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21517 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21518 + }
21519 +
21520 + default:
21521 + return (-1);
21522 + }
21523 +
21524 + return (0);
21525 +}
21526 +
21527 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
21528 +{
21529 +return sb_clkctl_xtal(sbh,what,on);
21530 +}
21531 +
21532 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
21533 +/* returns true if ignore pll off is set and false if it is not */
21534 +bool
21535 +sb_clkctl_clk(sb_t *sbh, uint mode)
21536 +{
21537 + sb_info_t *si;
21538 + uint origidx;
21539 + chipcregs_t *cc;
21540 + uint32 scc;
21541 + bool forcefastclk=FALSE;
21542 + uint intr_val = 0;
21543 +
21544 + si = SB_INFO(sbh);
21545 +
21546 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
21547 + if (si->sb.ccrev < 6)
21548 + return (FALSE);
21549 +
21550 + /* chipcommon cores rev10 are a whole new ball game */
21551 + if (si->sb.ccrev >= 10)
21552 + return (FALSE);
21553 +
21554 + INTR_OFF(si, intr_val);
21555 +
21556 + origidx = si->curidx;
21557 +
21558 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21559 + ASSERT(cc != NULL);
21560 +
21561 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21562 + goto done;
21563 +
21564 + switch (mode) {
21565 + case CLK_FAST: /* force fast (pll) clock */
21566 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
21567 + sb_clkctl_xtal(&si->sb, XTAL, ON);
21568 +
21569 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
21570 + break;
21571 +
21572 + case CLK_DYNAMIC: /* enable dynamic clock control */
21573 + scc = R_REG(&cc->slow_clk_ctl);
21574 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
21575 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
21576 + scc |= SCC_XC;
21577 + W_REG(&cc->slow_clk_ctl, scc);
21578 +
21579 + /* for dynamic control, we have to release our xtal_pu "force on" */
21580 + if (scc & SCC_XC)
21581 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
21582 + break;
21583 +
21584 + default:
21585 + ASSERT(0);
21586 + }
21587 +
21588 + /* Is the h/w forcing the use of the fast clk */
21589 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
21590 +
21591 +done:
21592 + sb_setcoreidx(sbh, origidx);
21593 + INTR_RESTORE(si, intr_val);
21594 + return (forcefastclk);
21595 +}
21596 +
21597 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
21598 +{
21599 +return sb_clkctl_clk(sbh, mode);
21600 +}
21601 +/* register driver interrupt disabling and restoring callback functions */
21602 +void
21603 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
21604 +{
21605 + sb_info_t *si;
21606 +
21607 + si = SB_INFO(sbh);
21608 + si->intr_arg = intr_arg;
21609 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
21610 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
21611 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
21612 + /* save current core id. when this function called, the current core
21613 + * must be the core which provides driver functions(il, et, wl, etc.)
21614 + */
21615 + si->dev_coreid = si->coreid[si->curidx];
21616 +}
21617 +
21618 +
21619 +void
21620 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
21621 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
21622 +{
21623 + uint vendor, core, unit;
21624 + uint chip, chippkg;
21625 + char varname[8];
21626 + uint8 class, subclass, progif;
21627 +
21628 + vendor = sb_corevendor(sbh);
21629 + core = sb_coreid(sbh);
21630 + unit = sb_coreunit(sbh);
21631 +
21632 + chip = BCMINIT(sb_chip)(sbh);
21633 + chippkg = BCMINIT(sb_chippkg)(sbh);
21634 +
21635 + progif = 0;
21636 +
21637 + /* Known vendor translations */
21638 + switch (vendor) {
21639 + case SB_VEND_BCM:
21640 + vendor = VENDOR_BROADCOM;
21641 + break;
21642 + }
21643 +
21644 + /* Determine class based on known core codes */
21645 + switch (core) {
21646 + case SB_ILINE20:
21647 + class = PCI_CLASS_NET;
21648 + subclass = PCI_NET_ETHER;
21649 + core = BCM47XX_ILINE_ID;
21650 + break;
21651 + case SB_ENET:
21652 + class = PCI_CLASS_NET;
21653 + subclass = PCI_NET_ETHER;
21654 + core = BCM47XX_ENET_ID;
21655 + break;
21656 + case SB_SDRAM:
21657 + case SB_MEMC:
21658 + class = PCI_CLASS_MEMORY;
21659 + subclass = PCI_MEMORY_RAM;
21660 + break;
21661 + case SB_PCI:
21662 + case SB_PCIE:
21663 + class = PCI_CLASS_BRIDGE;
21664 + subclass = PCI_BRIDGE_PCI;
21665 + break;
21666 + case SB_MIPS:
21667 + case SB_MIPS33:
21668 + class = PCI_CLASS_CPU;
21669 + subclass = PCI_CPU_MIPS;
21670 + break;
21671 + case SB_CODEC:
21672 + class = PCI_CLASS_COMM;
21673 + subclass = PCI_COMM_MODEM;
21674 + core = BCM47XX_V90_ID;
21675 + break;
21676 + case SB_USB:
21677 + class = PCI_CLASS_SERIAL;
21678 + subclass = PCI_SERIAL_USB;
21679 + progif = 0x10; /* OHCI */
21680 + core = BCM47XX_USB_ID;
21681 + break;
21682 + case SB_USB11H:
21683 + class = PCI_CLASS_SERIAL;
21684 + subclass = PCI_SERIAL_USB;
21685 + progif = 0x10; /* OHCI */
21686 + core = BCM47XX_USBH_ID;
21687 + break;
21688 + case SB_USB11D:
21689 + class = PCI_CLASS_SERIAL;
21690 + subclass = PCI_SERIAL_USB;
21691 + core = BCM47XX_USBD_ID;
21692 + break;
21693 + case SB_IPSEC:
21694 + class = PCI_CLASS_CRYPT;
21695 + subclass = PCI_CRYPT_NETWORK;
21696 + core = BCM47XX_IPSEC_ID;
21697 + break;
21698 + case SB_ROBO:
21699 + class = PCI_CLASS_NET;
21700 + subclass = PCI_NET_OTHER;
21701 + core = BCM47XX_ROBO_ID;
21702 + break;
21703 + case SB_EXTIF:
21704 + case SB_CC:
21705 + class = PCI_CLASS_MEMORY;
21706 + subclass = PCI_MEMORY_FLASH;
21707 + break;
21708 + case SB_D11:
21709 + class = PCI_CLASS_NET;
21710 + subclass = PCI_NET_OTHER;
21711 + /* Let an nvram variable override this */
21712 + sprintf(varname, "wl%did", unit);
21713 + if ((core = getintvar(NULL, varname)) == 0) {
21714 + if (chip == BCM4712_DEVICE_ID) {
21715 + if (chippkg == BCM4712SMALL_PKG_ID)
21716 + core = BCM4306_D11G_ID;
21717 + else
21718 + core = BCM4306_D11DUAL_ID;
21719 + }
21720 + }
21721 + break;
21722 +
21723 + default:
21724 + class = subclass = progif = 0xff;
21725 + break;
21726 + }
21727 +
21728 + *pcivendor = (uint16)vendor;
21729 + *pcidevice = (uint16)core;
21730 + *pciclass = class;
21731 + *pcisubclass = subclass;
21732 + *pciprogif = progif;
21733 +}
21734 +
21735 +
21736 +
21737 +
21738 +/* use the mdio interface to write to mdio slaves */
21739 +static int
21740 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
21741 +{
21742 + uint mdiodata;
21743 + uint i = 0;
21744 + sbpcieregs_t *pcieregs;
21745 +
21746 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
21747 + ASSERT (pcieregs);
21748 +
21749 + /* enable mdio access to SERDES */
21750 + W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
21751 +
21752 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
21753 + (physmedia << MDIODATA_DEVADDR_SHF) |
21754 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
21755 +
21756 + W_REG((&pcieregs->mdiodata), mdiodata);
21757 +
21758 + PR28829_DELAY();
21759 +
21760 + /* retry till the transaction is complete */
21761 + while ( i < 10 ) {
21762 + if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
21763 + /* Disable mdio access to SERDES */
21764 + W_REG((&pcieregs->mdiocontrol), 0);
21765 + return 0;
21766 + }
21767 + OSL_DELAY(1000);
21768 + i++;
21769 + }
21770 +
21771 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
21772 + /* Disable mdio access to SERDES */
21773 + W_REG((&pcieregs->mdiocontrol), 0);
21774 + ASSERT(0);
21775 + return 1;
21776 +
21777 +}
21778 +
21779 +/* indirect way to read pcie config regs*/
21780 +uint
21781 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
21782 +{
21783 + sb_info_t *si;
21784 + sb_t *sbh;
21785 + uint retval = 0xFFFFFFFF;
21786 + sbpcieregs_t *pcieregs;
21787 + uint addrtype;
21788 +
21789 + sbh = (sb_t *)sb;
21790 + si = SB_INFO(sbh);
21791 + ASSERT (PCIE(si));
21792 +
21793 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21794 + ASSERT (pcieregs);
21795 +
21796 + addrtype = (uint)((uintptr)arg1);
21797 + switch(addrtype) {
21798 + case PCIE_CONFIGREGS:
21799 + W_REG((&pcieregs->configaddr),offset);
21800 + retval = R_REG(&(pcieregs->configdata));
21801 + break;
21802 + case PCIE_PCIEREGS:
21803 + W_REG(&(pcieregs->pcieaddr),offset);
21804 + retval = R_REG(&(pcieregs->pciedata));
21805 + break;
21806 + default:
21807 + ASSERT(0);
21808 + break;
21809 + }
21810 + return retval;
21811 +}
21812 +
21813 +/* indirect way to write pcie config/mdio/pciecore regs*/
21814 +uint
21815 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
21816 +{
21817 + sb_info_t *si;
21818 + sbpcieregs_t *pcieregs;
21819 + uint addrtype;
21820 +
21821 + si = SB_INFO(sbh);
21822 + ASSERT (PCIE(si));
21823 +
21824 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21825 + ASSERT (pcieregs);
21826 +
21827 + addrtype = (uint)((uintptr)arg1);
21828 +
21829 + switch(addrtype) {
21830 + case PCIE_CONFIGREGS:
21831 + W_REG((&pcieregs->configaddr),offset);
21832 + W_REG((&pcieregs->configdata),val);
21833 + break;
21834 + case PCIE_PCIEREGS:
21835 + W_REG((&pcieregs->pcieaddr),offset);
21836 + W_REG((&pcieregs->pciedata),val);
21837 + break;
21838 + default:
21839 + ASSERT(0);
21840 + break;
21841 + }
21842 + return 0;
21843 +}
21844 +
21845 +
21846 +/* Build device path. Support SB, PCI, and JTAG for now. */
21847 +int
21848 +sb_devpath(sb_t *sbh, char *path, int size)
21849 +{
21850 + ASSERT(path);
21851 + ASSERT(size >= SB_DEVPATH_BUFSZ);
21852 +
21853 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
21854 + case SB_BUS:
21855 + case JTAG_BUS:
21856 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
21857 + break;
21858 + case PCI_BUS:
21859 + ASSERT((SB_INFO(sbh))->osh);
21860 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
21861 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
21862 + break;
21863 + case PCMCIA_BUS:
21864 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
21865 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
21866 + sprintf(path, "pc/%u/%u/", 1, 1);
21867 + break;
21868 + case SDIO_BUS:
21869 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
21870 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
21871 + break;
21872 + default:
21873 + ASSERT(0);
21874 + break;
21875 + }
21876 +
21877 + return 0;
21878 +}
21879 +
21880 +/* Fix chip's configuration. The current core may be changed upon return */
21881 +static int
21882 +sb_pci_fixcfg(sb_info_t *si)
21883 +{
21884 + uint origidx, pciidx;
21885 + sbpciregs_t *pciregs;
21886 + sbpcieregs_t *pcieregs;
21887 + uint16 val16, *reg16;
21888 + char name[SB_DEVPATH_BUFSZ+16], *value;
21889 + char devpath[SB_DEVPATH_BUFSZ];
21890 +
21891 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
21892 +
21893 + /* Fix PCI(e) SROM shadow area */
21894 + /* save the current index */
21895 + origidx = sb_coreidx(&si->sb);
21896 +
21897 + /* check 'pi' is correct and fix it if not */
21898 + if (si->sb.buscoretype == SB_PCIE) {
21899 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
21900 + ASSERT(pcieregs);
21901 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
21902 + }
21903 + else if (si->sb.buscoretype == SB_PCI) {
21904 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
21905 + ASSERT(pciregs);
21906 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
21907 + }
21908 + else {
21909 + ASSERT(0);
21910 + return -1;
21911 + }
21912 + pciidx = sb_coreidx(&si->sb);
21913 + val16 = R_REG(reg16);
21914 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
21915 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
21916 + W_REG(reg16, val16);
21917 + }
21918 +
21919 + /* restore the original index */
21920 + sb_setcoreidx(&si->sb, origidx);
21921 +
21922 + /* Fix bar0window */
21923 + /* !do it last, it changes the current core! */
21924 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
21925 + return -1;
21926 + sprintf(name, "%sb0w", devpath);
21927 + if ((value = getvar(NULL, name))) {
21928 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
21929 + bcm_strtoul(value, NULL, 16));
21930 + /* update curidx since the current core is changed */
21931 + si->curidx = _sb_coreidx(si);
21932 + if (si->curidx == BADIDX) {
21933 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
21934 + return -1;
21935 + }
21936 + }
21937 +
21938 + return 0;
21939 +}
21940 +
21941 diff -urN linux.old/drivers/net/hnd/shared_ksyms.sh linux.dev/drivers/net/hnd/shared_ksyms.sh
21942 --- linux.old/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
21943 +++ linux.dev/drivers/net/hnd/shared_ksyms.sh 2005-11-07 21:57:07.917590250 +0100
21944 @@ -0,0 +1,21 @@
21945 +#!/bin/sh
21946 +#
21947 +# Copyright 2004, Broadcom Corporation
21948 +# All Rights Reserved.
21949 +#
21950 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21951 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21952 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21953 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21954 +#
21955 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
21956 +#
21957 +
21958 +cat <<EOF
21959 +#include <linux/config.h>
21960 +#include <linux/module.h>
21961 +EOF
21962 +
21963 +for file in $* ; do
21964 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
21965 +done
21966 diff -urN linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
21967 --- linux.old/drivers/net/wireless/Config.in 2005-11-07 23:12:51.258929250 +0100
21968 +++ linux.dev/drivers/net/wireless/Config.in 2005-11-07 21:57:07.941591750 +0100
21969 @@ -13,6 +13,7 @@
21970 fi
21971
21972 if [ "$CONFIG_PCI" = "y" ]; then
21973 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
21974 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21975 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21976 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21977 diff -urN linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
21978 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
21979 +++ linux.dev/drivers/net/wl/Makefile 2005-11-07 21:57:07.941591750 +0100
21980 @@ -0,0 +1,26 @@
21981 +#
21982 +# Makefile for the Broadcom wl driver
21983 +#
21984 +# Copyright 2004, Broadcom Corporation
21985 +# All Rights Reserved.
21986 +#
21987 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21988 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21989 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21990 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21991 +#
21992 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
21993 +
21994 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
21995 +
21996 +O_TARGET := wl.o
21997 +
21998 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
21999 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
22000 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
22001 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
22002 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
22003 +
22004 +obj-m := $(O_TARGET)
22005 +
22006 +include $(TOPDIR)/Rules.make
22007 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
22008 --- linux.old/drivers/parport/Config.in 2005-11-07 23:12:51.306932250 +0100
22009 +++ linux.dev/drivers/parport/Config.in 2005-11-07 21:57:07.941591750 +0100
22010 @@ -11,6 +11,7 @@
22011 tristate 'Parallel port support' CONFIG_PARPORT
22012 if [ "$CONFIG_PARPORT" != "n" ]; then
22013 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
22014 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
22015 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
22016 if [ "$CONFIG_SERIAL" = "m" ]; then
22017 define_tristate CONFIG_PARPORT_PC_CML1 m
22018 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
22019 --- linux.old/drivers/parport/Makefile 2005-11-07 23:12:51.318933000 +0100
22020 +++ linux.dev/drivers/parport/Makefile 2005-11-07 21:57:07.941591750 +0100
22021 @@ -22,6 +22,7 @@
22022
22023 obj-$(CONFIG_PARPORT) += parport.o
22024 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
22025 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
22026 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
22027 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
22028 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
22029 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
22030 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
22031 +++ linux.dev/drivers/parport/parport_splink.c 2005-11-07 21:57:07.941591750 +0100
22032 @@ -0,0 +1,345 @@
22033 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
22034 + *
22035 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
22036 + * Based on parport_pc source
22037 + */
22038 +
22039 +#include <linux/config.h>
22040 +#include <linux/module.h>
22041 +#include <linux/init.h>
22042 +#include <linux/ioport.h>
22043 +#include <linux/kernel.h>
22044 +#include <linux/slab.h>
22045 +#include <linux/parport.h>
22046 +#include <linux/parport_pc.h>
22047 +
22048 +#define SPLINK_ADDRESS 0xBF800010
22049 +
22050 +#undef DEBUG
22051 +
22052 +#ifdef DEBUG
22053 +#define DPRINTK printk
22054 +#else
22055 +#define DPRINTK(stuff...)
22056 +#endif
22057 +
22058 +
22059 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
22060 + * it doesn't do any extra masking. */
22061 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
22062 + unsigned char mask,
22063 + unsigned char val)
22064 +{
22065 + struct parport_pc_private *priv = p->physport->private_data;
22066 + unsigned char *io = (unsigned char *) p->base;
22067 + unsigned char ctr = priv->ctr;
22068 +#ifdef DEBUG_PARPORT
22069 + printk (KERN_DEBUG
22070 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
22071 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
22072 +#endif
22073 + ctr = (ctr & ~mask) ^ val;
22074 + ctr &= priv->ctr_writable; /* only write writable bits. */
22075 + *(io+2) = ctr;
22076 + priv->ctr = ctr; /* Update soft copy */
22077 + return ctr;
22078 +}
22079 +
22080 +
22081 +
22082 +static void parport_splink_data_forward (struct parport *p)
22083 +{
22084 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22085 + __parport_splink_frob_control (p, 0x20, 0);
22086 +}
22087 +
22088 +static void parport_splink_data_reverse (struct parport *p)
22089 +{
22090 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22091 + __parport_splink_frob_control (p, 0x20, 0x20);
22092 +}
22093 +
22094 +/*
22095 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
22096 +{
22097 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
22098 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
22099 +}
22100 +*/
22101 +
22102 +static void parport_splink_enable_irq(struct parport *p)
22103 +{
22104 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
22105 + __parport_splink_frob_control (p, 0x10, 0x10);
22106 +}
22107 +
22108 +static void parport_splink_disable_irq(struct parport *p)
22109 +{
22110 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
22111 + __parport_splink_frob_control (p, 0x10, 0);
22112 +}
22113 +
22114 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
22115 +{
22116 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
22117 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
22118 + if (dev->irq_func &&
22119 + dev->port->irq != PARPORT_IRQ_NONE)
22120 + /* Set ackIntEn */
22121 + s->u.pc.ctr |= 0x10;
22122 +}
22123 +
22124 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
22125 +{
22126 + const struct parport_pc_private *priv = p->physport->private_data;
22127 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
22128 + s->u.pc.ctr = priv->ctr;
22129 +}
22130 +
22131 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
22132 +{
22133 + struct parport_pc_private *priv = p->physport->private_data;
22134 + unsigned char *io = (unsigned char *) p->base;
22135 + unsigned char ctr = s->u.pc.ctr;
22136 +
22137 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
22138 + *(io+2) = ctr;
22139 + priv->ctr = ctr;
22140 +}
22141 +
22142 +static void parport_splink_setup_interrupt(void) {
22143 + return;
22144 +}
22145 +
22146 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
22147 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
22148 + unsigned char *io = (unsigned char *) p->base;
22149 + *io = d;
22150 +}
22151 +
22152 +static unsigned char parport_splink_read_data(struct parport *p) {
22153 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
22154 + unsigned char *io = (unsigned char *) p->base;
22155 + return *io;
22156 +}
22157 +
22158 +static void parport_splink_write_control(struct parport *p, unsigned char d)
22159 +{
22160 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22161 + PARPORT_CONTROL_AUTOFD |
22162 + PARPORT_CONTROL_INIT |
22163 + PARPORT_CONTROL_SELECT);
22164 +
22165 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
22166 + /* Take this out when drivers have adapted to the newer interface. */
22167 + if (d & 0x20) {
22168 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
22169 + p->name, p->cad->name);
22170 + parport_splink_data_reverse (p);
22171 + }
22172 +
22173 + __parport_splink_frob_control (p, wm, d & wm);
22174 +}
22175 +
22176 +static unsigned char parport_splink_read_control(struct parport *p)
22177 +{
22178 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22179 + PARPORT_CONTROL_AUTOFD |
22180 + PARPORT_CONTROL_INIT |
22181 + PARPORT_CONTROL_SELECT);
22182 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
22183 + const struct parport_pc_private *priv = p->physport->private_data;
22184 + return priv->ctr & wm; /* Use soft copy */
22185 +}
22186 +
22187 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
22188 + unsigned char val)
22189 +{
22190 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22191 + PARPORT_CONTROL_AUTOFD |
22192 + PARPORT_CONTROL_INIT |
22193 + PARPORT_CONTROL_SELECT);
22194 +
22195 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
22196 + /* Take this out when drivers have adapted to the newer interface. */
22197 + if (mask & 0x20) {
22198 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
22199 + p->name, p->cad->name,
22200 + (val & 0x20) ? "reverse" : "forward");
22201 + if (val & 0x20)
22202 + parport_splink_data_reverse (p);
22203 + else
22204 + parport_splink_data_forward (p);
22205 + }
22206 +
22207 + /* Restrict mask and val to control lines. */
22208 + mask &= wm;
22209 + val &= wm;
22210 +
22211 + return __parport_splink_frob_control (p, mask, val);
22212 +}
22213 +
22214 +static unsigned char parport_splink_read_status(struct parport *p)
22215 +{
22216 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
22217 + unsigned char *io = (unsigned char *) p->base;
22218 + return *(io+1);
22219 +}
22220 +
22221 +static void parport_splink_inc_use_count(void)
22222 +{
22223 +#ifdef MODULE
22224 + MOD_INC_USE_COUNT;
22225 +#endif
22226 +}
22227 +
22228 +static void parport_splink_dec_use_count(void)
22229 +{
22230 +#ifdef MODULE
22231 + MOD_DEC_USE_COUNT;
22232 +#endif
22233 +}
22234 +
22235 +static struct parport_operations parport_splink_ops =
22236 +{
22237 + parport_splink_write_data,
22238 + parport_splink_read_data,
22239 +
22240 + parport_splink_write_control,
22241 + parport_splink_read_control,
22242 + parport_splink_frob_control,
22243 +
22244 + parport_splink_read_status,
22245 +
22246 + parport_splink_enable_irq,
22247 + parport_splink_disable_irq,
22248 +
22249 + parport_splink_data_forward,
22250 + parport_splink_data_reverse,
22251 +
22252 + parport_splink_init_state,
22253 + parport_splink_save_state,
22254 + parport_splink_restore_state,
22255 +
22256 + parport_splink_inc_use_count,
22257 + parport_splink_dec_use_count,
22258 +
22259 + parport_ieee1284_epp_write_data,
22260 + parport_ieee1284_epp_read_data,
22261 + parport_ieee1284_epp_write_addr,
22262 + parport_ieee1284_epp_read_addr,
22263 +
22264 + parport_ieee1284_ecp_write_data,
22265 + parport_ieee1284_ecp_read_data,
22266 + parport_ieee1284_ecp_write_addr,
22267 +
22268 + parport_ieee1284_write_compat,
22269 + parport_ieee1284_read_nibble,
22270 + parport_ieee1284_read_byte,
22271 +};
22272 +
22273 +/* --- Initialisation code -------------------------------- */
22274 +
22275 +static struct parport *parport_splink_probe_port (unsigned long int base)
22276 +{
22277 + struct parport_pc_private *priv;
22278 + struct parport_operations *ops;
22279 + struct parport *p;
22280 +
22281 + if (check_mem_region(base, 3)) {
22282 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
22283 + return NULL;
22284 + }
22285 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
22286 + if (!priv) {
22287 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
22288 + return NULL;
22289 + }
22290 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
22291 + if (!ops) {
22292 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
22293 + base);
22294 + kfree (priv);
22295 + return NULL;
22296 + }
22297 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
22298 + priv->ctr = 0xc;
22299 + priv->ctr_writable = 0xff;
22300 +
22301 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
22302 + PARPORT_DMA_NONE, ops))) {
22303 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
22304 + base);
22305 + kfree (priv);
22306 + kfree (ops);
22307 + return NULL;
22308 + }
22309 +
22310 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
22311 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
22312 + p->private_data = priv;
22313 +
22314 + parport_proc_register(p);
22315 + request_mem_region (p->base, 3, p->name);
22316 +
22317 + /* Done probing. Now put the port into a sensible start-up state. */
22318 + parport_splink_write_data(p, 0);
22319 + parport_splink_data_forward (p);
22320 +
22321 + /* Now that we've told the sharing engine about the port, and
22322 + found out its characteristics, let the high-level drivers
22323 + know about it. */
22324 + parport_announce_port (p);
22325 +
22326 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
22327 + base);
22328 + return p;
22329 +}
22330 +
22331 +static void parport_splink_unregister_port(struct parport *p) {
22332 + struct parport_pc_private *priv = p->private_data;
22333 + struct parport_operations *ops = p->ops;
22334 +
22335 + if (p->irq != PARPORT_IRQ_NONE)
22336 + free_irq(p->irq, p);
22337 + release_mem_region(p->base, 3);
22338 + parport_proc_unregister(p);
22339 + kfree (priv);
22340 + parport_unregister_port(p);
22341 + kfree (ops);
22342 +}
22343 +
22344 +
22345 +int parport_splink_init(void)
22346 +{
22347 + int ret;
22348 +
22349 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
22350 + parport_splink_setup_interrupt();
22351 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
22352 +
22353 + return ret;
22354 +}
22355 +
22356 +void parport_splink_cleanup(void) {
22357 + struct parport *p = parport_enumerate(), *tmp;
22358 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
22359 + if (p->size) {
22360 + if (p->modes & PARPORT_MODE_PCSPP) {
22361 + while(p) {
22362 + tmp = p->next;
22363 + parport_splink_unregister_port(p);
22364 + p = tmp;
22365 + }
22366 + }
22367 + }
22368 +}
22369 +
22370 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
22371 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
22372 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
22373 +MODULE_LICENSE("GPL");
22374 +
22375 +module_init(parport_splink_init)
22376 +module_exit(parport_splink_cleanup)
22377 +
22378 diff -urN linux.old/drivers/pcmcia/Makefile linux.dev/drivers/pcmcia/Makefile
22379 --- linux.old/drivers/pcmcia/Makefile 2005-11-07 23:12:51.350935000 +0100
22380 +++ linux.dev/drivers/pcmcia/Makefile 2005-11-07 21:57:07.941591750 +0100
22381 @@ -74,6 +74,10 @@
22382 au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o
22383 au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
22384
22385 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
22386 +bcm4710_ss-objs := bcm4710_generic.o
22387 +bcm4710_ss-objs += bcm4710_pcmcia.o
22388 +
22389 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
22390 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
22391 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
22392 @@ -112,5 +116,8 @@
22393 au1x00_ss.o: $(au1000_ss-objs-y)
22394 $(LD) -r -o $@ $(au1000_ss-objs-y)
22395
22396 +bcm4710_ss.o: $(bcm4710_ss-objs)
22397 + $(LD) -r -o $@ $(bcm4710_ss-objs)
22398 +
22399 yenta_socket.o: $(yenta_socket-objs)
22400 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
22401 diff -urN linux.old/drivers/pcmcia/bcm4710_generic.c linux.dev/drivers/pcmcia/bcm4710_generic.c
22402 --- linux.old/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
22403 +++ linux.dev/drivers/pcmcia/bcm4710_generic.c 2005-11-07 21:57:07.945592000 +0100
22404 @@ -0,0 +1,912 @@
22405 +/*
22406 + *
22407 + * bcm47xx pcmcia driver
22408 + *
22409 + * Copyright 2004, Broadcom Corporation
22410 + * All Rights Reserved.
22411 + *
22412 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22413 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22414 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22415 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22416 + *
22417 + * Based on sa1100_generic.c from www.handhelds.org,
22418 + * and au1000_generic.c from oss.sgi.com.
22419 + *
22420 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
22421 + */
22422 +#include <linux/module.h>
22423 +#include <linux/init.h>
22424 +#include <linux/config.h>
22425 +#include <linux/delay.h>
22426 +#include <linux/ioport.h>
22427 +#include <linux/kernel.h>
22428 +#include <linux/tqueue.h>
22429 +#include <linux/timer.h>
22430 +#include <linux/mm.h>
22431 +#include <linux/proc_fs.h>
22432 +#include <linux/version.h>
22433 +#include <linux/types.h>
22434 +#include <linux/vmalloc.h>
22435 +
22436 +#include <pcmcia/version.h>
22437 +#include <pcmcia/cs_types.h>
22438 +#include <pcmcia/cs.h>
22439 +#include <pcmcia/ss.h>
22440 +#include <pcmcia/bulkmem.h>
22441 +#include <pcmcia/cistpl.h>
22442 +#include <pcmcia/bus_ops.h>
22443 +#include "cs_internal.h"
22444 +
22445 +#include <asm/io.h>
22446 +#include <asm/irq.h>
22447 +#include <asm/system.h>
22448 +
22449 +#include <typedefs.h>
22450 +#include <bcm4710.h>
22451 +#include <sbextif.h>
22452 +
22453 +#include "bcm4710pcmcia.h"
22454 +
22455 +#ifdef PCMCIA_DEBUG
22456 +static int pc_debug = PCMCIA_DEBUG;
22457 +#endif
22458 +
22459 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
22460 +
22461 +/* This structure maintains housekeeping state for each socket, such
22462 + * as the last known values of the card detect pins, or the Card Services
22463 + * callback value associated with the socket:
22464 + */
22465 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
22466 +static int socket_count;
22467 +
22468 +
22469 +/* Returned by the low-level PCMCIA interface: */
22470 +static struct pcmcia_low_level *pcmcia_low_level;
22471 +
22472 +/* Event poll timer structure */
22473 +static struct timer_list poll_timer;
22474 +
22475 +
22476 +/* Prototypes for routines which are used internally: */
22477 +
22478 +static int bcm47xx_pcmcia_driver_init(void);
22479 +static void bcm47xx_pcmcia_driver_shutdown(void);
22480 +static void bcm47xx_pcmcia_task_handler(void *data);
22481 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
22482 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
22483 +static struct tq_struct bcm47xx_pcmcia_task;
22484 +
22485 +#ifdef CONFIG_PROC_FS
22486 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
22487 + off_t pos, int count, int *eof, void *data);
22488 +#endif
22489 +
22490 +
22491 +/* Prototypes for operations which are exported to the
22492 + * in-kernel PCMCIA core:
22493 + */
22494 +
22495 +static int bcm47xx_pcmcia_init(unsigned int sock);
22496 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
22497 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
22498 + void (*handler)(void *, unsigned int), void *info);
22499 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
22500 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
22501 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
22502 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
22503 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
22504 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
22505 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22506 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22507 +#ifdef CONFIG_PROC_FS
22508 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
22509 +#endif
22510 +
22511 +static struct pccard_operations bcm47xx_pcmcia_operations = {
22512 + bcm47xx_pcmcia_init,
22513 + bcm47xx_pcmcia_suspend,
22514 + bcm47xx_pcmcia_register_callback,
22515 + bcm47xx_pcmcia_inquire_socket,
22516 + bcm47xx_pcmcia_get_status,
22517 + bcm47xx_pcmcia_get_socket,
22518 + bcm47xx_pcmcia_set_socket,
22519 + bcm47xx_pcmcia_get_io_map,
22520 + bcm47xx_pcmcia_set_io_map,
22521 + bcm47xx_pcmcia_get_mem_map,
22522 + bcm47xx_pcmcia_set_mem_map,
22523 +#ifdef CONFIG_PROC_FS
22524 + bcm47xx_pcmcia_proc_setup
22525 +#endif
22526 +};
22527 +
22528 +
22529 +/*
22530 + * bcm47xx_pcmcia_driver_init()
22531 + *
22532 + * This routine performs a basic sanity check to ensure that this
22533 + * kernel has been built with the appropriate board-specific low-level
22534 + * PCMCIA support, performs low-level PCMCIA initialization, registers
22535 + * this socket driver with Card Services, and then spawns the daemon
22536 + * thread which is the real workhorse of the socket driver.
22537 + *
22538 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
22539 + * on the low-level kernel interface.
22540 + *
22541 + * Returns: 0 on success, -1 on error
22542 + */
22543 +static int __init bcm47xx_pcmcia_driver_init(void)
22544 +{
22545 + servinfo_t info;
22546 + struct pcmcia_init pcmcia_init;
22547 + struct pcmcia_state state;
22548 + unsigned int i;
22549 + unsigned long tmp;
22550 +
22551 +
22552 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
22553 +
22554 + CardServices(GetCardServicesInfo, &info);
22555 +
22556 + if (info.Revision != CS_RELEASE_CODE) {
22557 + printk(KERN_ERR "Card Services release codes do not match\n");
22558 + return -1;
22559 + }
22560 +
22561 +#ifdef CONFIG_BCM4710
22562 + pcmcia_low_level=&bcm4710_pcmcia_ops;
22563 +#else
22564 +#error Unsupported Broadcom BCM47XX board.
22565 +#endif
22566 +
22567 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
22568 +
22569 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
22570 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
22571 + return -EIO;
22572 + } else {
22573 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
22574 + }
22575 +
22576 + pcmcia_socket =
22577 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
22578 + GFP_KERNEL);
22579 + memset(pcmcia_socket, 0,
22580 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
22581 + if (!pcmcia_socket) {
22582 + printk(KERN_ERR "Card Services can't get memory \n");
22583 + return -1;
22584 + }
22585 +
22586 + for (i = 0; i < socket_count; i++) {
22587 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
22588 + printk(KERN_ERR "Unable to get PCMCIA status\n");
22589 + return -EIO;
22590 + }
22591 + pcmcia_socket[i].k_state = state;
22592 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
22593 +
22594 + if (i == 0) {
22595 + pcmcia_socket[i].virt_io =
22596 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
22597 + /* Substract ioport base which gets added by in/out */
22598 + pcmcia_socket[i].virt_io -= mips_io_port_base;
22599 + pcmcia_socket[i].phys_attr =
22600 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
22601 + pcmcia_socket[i].phys_mem =
22602 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
22603 + } else {
22604 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
22605 + return 1;
22606 + }
22607 + }
22608 +
22609 + /* Only advertise as many sockets as we can detect: */
22610 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
22611 + printk(KERN_ERR "Unable to register socket service routine\n");
22612 + return -ENXIO;
22613 + }
22614 +
22615 + /* Start the event poll timer.
22616 + * It will reschedule by itself afterwards.
22617 + */
22618 + bcm47xx_pcmcia_poll_event(0);
22619 +
22620 + DEBUG(1, "bcm4710: initialization complete\n");
22621 + return 0;
22622 +
22623 +}
22624 +
22625 +module_init(bcm47xx_pcmcia_driver_init);
22626 +
22627 +
22628 +/*
22629 + * bcm47xx_pcmcia_driver_shutdown()
22630 + *
22631 + * Invokes the low-level kernel service to free IRQs associated with this
22632 + * socket controller and reset GPIO edge detection.
22633 + */
22634 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
22635 +{
22636 + int i;
22637 +
22638 + del_timer_sync(&poll_timer);
22639 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
22640 + pcmcia_low_level->shutdown();
22641 + flush_scheduled_tasks();
22642 + for (i = 0; i < socket_count; i++) {
22643 + if (pcmcia_socket[i].virt_io)
22644 + iounmap((void *)pcmcia_socket[i].virt_io);
22645 + if (pcmcia_socket[i].phys_attr)
22646 + iounmap((void *)pcmcia_socket[i].phys_attr);
22647 + if (pcmcia_socket[i].phys_mem)
22648 + iounmap((void *)pcmcia_socket[i].phys_mem);
22649 + }
22650 + DEBUG(1, "bcm4710: shutdown complete\n");
22651 +}
22652 +
22653 +module_exit(bcm47xx_pcmcia_driver_shutdown);
22654 +
22655 +/*
22656 + * bcm47xx_pcmcia_init()
22657 + * We perform all of the interesting initialization tasks in
22658 + * bcm47xx_pcmcia_driver_init().
22659 + *
22660 + * Returns: 0
22661 + */
22662 +static int bcm47xx_pcmcia_init(unsigned int sock)
22663 +{
22664 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
22665 +
22666 + return 0;
22667 +}
22668 +
22669 +/*
22670 + * bcm47xx_pcmcia_suspend()
22671 + *
22672 + * We don't currently perform any actions on a suspend.
22673 + *
22674 + * Returns: 0
22675 + */
22676 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
22677 +{
22678 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
22679 +
22680 + return 0;
22681 +}
22682 +
22683 +
22684 +/*
22685 + * bcm47xx_pcmcia_events()
22686 + *
22687 + * Helper routine to generate a Card Services event mask based on
22688 + * state information obtained from the kernel low-level PCMCIA layer
22689 + * in a recent (and previous) sampling. Updates `prev_state'.
22690 + *
22691 + * Returns: an event mask for the given socket state.
22692 + */
22693 +static inline unsigned
22694 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
22695 + struct pcmcia_state *prev_state,
22696 + unsigned int mask, unsigned int flags)
22697 +{
22698 + unsigned int events=0;
22699 +
22700 + if (state->bvd1 != prev_state->bvd1) {
22701 +
22702 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
22703 +
22704 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
22705 + }
22706 +
22707 + if (state->bvd2 != prev_state->bvd2) {
22708 +
22709 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
22710 +
22711 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
22712 + }
22713 +
22714 + if (state->detect != prev_state->detect) {
22715 +
22716 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
22717 +
22718 + events |= mask & SS_DETECT;
22719 + }
22720 +
22721 +
22722 + if (state->ready != prev_state->ready) {
22723 +
22724 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
22725 +
22726 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
22727 + }
22728 +
22729 + if (events != 0) {
22730 + DEBUG(2, "events: %s%s%s%s%s\n",
22731 + (events & SS_DETECT) ? "DETECT " : "",
22732 + (events & SS_READY) ? "READY " : "",
22733 + (events & SS_BATDEAD) ? "BATDEAD " : "",
22734 + (events & SS_BATWARN) ? "BATWARN " : "",
22735 + (events & SS_STSCHG) ? "STSCHG " : "");
22736 + }
22737 +
22738 + *prev_state=*state;
22739 + return events;
22740 +}
22741 +
22742 +
22743 +/*
22744 + * bcm47xx_pcmcia_task_handler()
22745 + *
22746 + * Processes serviceable socket events using the "eventd" thread context.
22747 + *
22748 + * Event processing (specifically, the invocation of the Card Services event
22749 + * callback) occurs in this thread rather than in the actual interrupt
22750 + * handler due to the use of scheduling operations in the PCMCIA core.
22751 + */
22752 +static void bcm47xx_pcmcia_task_handler(void *data)
22753 +{
22754 + struct pcmcia_state state;
22755 + int i, events, irq_status;
22756 +
22757 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
22758 +
22759 + for (i = 0; i < socket_count; i++) {
22760 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
22761 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
22762 +
22763 + events = bcm47xx_pcmcia_events(&state,
22764 + &pcmcia_socket[i].k_state,
22765 + pcmcia_socket[i].cs_state.csc_mask,
22766 + pcmcia_socket[i].cs_state.flags);
22767 +
22768 + if (pcmcia_socket[i].handler != NULL) {
22769 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
22770 + events);
22771 + }
22772 + }
22773 +}
22774 +
22775 +static struct tq_struct bcm47xx_pcmcia_task = {
22776 + routine: bcm47xx_pcmcia_task_handler
22777 +};
22778 +
22779 +
22780 +/*
22781 + * bcm47xx_pcmcia_poll_event()
22782 + *
22783 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
22784 + */
22785 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
22786 +{
22787 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
22788 +
22789 + poll_timer.function = bcm47xx_pcmcia_poll_event;
22790 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
22791 + add_timer(&poll_timer);
22792 + schedule_task(&bcm47xx_pcmcia_task);
22793 +}
22794 +
22795 +
22796 +/*
22797 + * bcm47xx_pcmcia_interrupt()
22798 + *
22799 + * Service routine for socket driver interrupts (requested by the
22800 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
22801 + *
22802 + * The actual interrupt-servicing work is performed by
22803 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
22804 + * handling code performs scheduling operations which cannot be
22805 + * executed from within an interrupt context.
22806 + */
22807 +static void
22808 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
22809 +{
22810 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
22811 + schedule_task(&bcm47xx_pcmcia_task);
22812 +}
22813 +
22814 +
22815 +/*
22816 + * bcm47xx_pcmcia_register_callback()
22817 + *
22818 + * Implements the register_callback() operation for the in-kernel
22819 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
22820 + * the function pointer `handler' is not NULL, remember the callback
22821 + * location in the state for `sock', and increment the usage counter
22822 + * for the driver module. (The callback is invoked from the interrupt
22823 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
22824 + * of interesting events.) Otherwise, clear the callback pointer in the
22825 + * socket state and decrement the module usage count.
22826 + *
22827 + * Returns: 0
22828 + */
22829 +static int
22830 +bcm47xx_pcmcia_register_callback(unsigned int sock,
22831 + void (*handler)(void *, unsigned int), void *info)
22832 +{
22833 + if (handler == NULL) {
22834 + pcmcia_socket[sock].handler = NULL;
22835 + MOD_DEC_USE_COUNT;
22836 + } else {
22837 + MOD_INC_USE_COUNT;
22838 + pcmcia_socket[sock].handler = handler;
22839 + pcmcia_socket[sock].handler_info = info;
22840 + }
22841 + return 0;
22842 +}
22843 +
22844 +
22845 +/*
22846 + * bcm47xx_pcmcia_inquire_socket()
22847 + *
22848 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
22849 + * service (formerly SS_InquireSocket in Card Services). Of note is
22850 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
22851 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
22852 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
22853 + * resource database check. (Mapped memory is set up within the socket
22854 + * driver itself.)
22855 + *
22856 + * In conjunction with the STATIC_MAP capability is a new field,
22857 + * `io_offset', recommended by David Hinds. Rather than go through
22858 + * the SetIOMap interface (which is not quite suited for communicating
22859 + * window locations up from the socket driver), we just pass up
22860 + * an offset which is applied to client-requested base I/O addresses
22861 + * in alloc_io_space().
22862 + *
22863 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
22864 + */
22865 +static int
22866 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
22867 +{
22868 + struct pcmcia_irq_info irq_info;
22869 +
22870 + if (sock >= socket_count) {
22871 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
22872 + return -1;
22873 + }
22874 +
22875 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
22876 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
22877 + * general, the mapped * addresses of the PCMCIA memory regions
22878 + * will not be within 0xffff, setting force_low would be
22879 + * undesirable.
22880 + *
22881 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
22882 + * resource database; we instead pass up physical address ranges
22883 + * and allow other parts of Card Services to deal with remapping.
22884 + *
22885 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
22886 + * not 32-bit CardBus devices.
22887 + */
22888 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
22889 +
22890 + irq_info.sock = sock;
22891 + irq_info.irq = -1;
22892 +
22893 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
22894 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
22895 + return -1;
22896 + }
22897 +
22898 + cap->irq_mask = 0;
22899 + cap->map_size = PAGE_SIZE;
22900 + cap->pci_irq = irq_info.irq;
22901 + cap->io_offset = pcmcia_socket[sock].virt_io;
22902 +
22903 + return 0;
22904 +}
22905 +
22906 +
22907 +/*
22908 + * bcm47xx_pcmcia_get_status()
22909 + *
22910 + * Implements the get_status() operation for the in-kernel PCMCIA
22911 + * service (formerly SS_GetStatus in Card Services). Essentially just
22912 + * fills in bits in `status' according to internal driver state or
22913 + * the value of the voltage detect chipselect register.
22914 + *
22915 + * As a debugging note, during card startup, the PCMCIA core issues
22916 + * three set_socket() commands in a row the first with RESET deasserted,
22917 + * the second with RESET asserted, and the last with RESET deasserted
22918 + * again. Following the third set_socket(), a get_status() command will
22919 + * be issued. The kernel is looking for the SS_READY flag (see
22920 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
22921 + *
22922 + * Returns: 0
22923 + */
22924 +static int
22925 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
22926 +{
22927 + struct pcmcia_state state;
22928 +
22929 +
22930 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
22931 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
22932 + return -1;
22933 + }
22934 +
22935 + pcmcia_socket[sock].k_state = state;
22936 +
22937 + *status = state.detect ? SS_DETECT : 0;
22938 +
22939 + *status |= state.ready ? SS_READY : 0;
22940 +
22941 + /* The power status of individual sockets is not available
22942 + * explicitly from the hardware, so we just remember the state
22943 + * and regurgitate it upon request:
22944 + */
22945 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
22946 +
22947 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
22948 + *status |= state.bvd1 ? SS_STSCHG : 0;
22949 + else {
22950 + if (state.bvd1 == 0)
22951 + *status |= SS_BATDEAD;
22952 + else if (state.bvd2 == 0)
22953 + *status |= SS_BATWARN;
22954 + }
22955 +
22956 + *status |= state.vs_3v ? SS_3VCARD : 0;
22957 +
22958 + *status |= state.vs_Xv ? SS_XVCARD : 0;
22959 +
22960 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
22961 + (*status&SS_DETECT)?"DETECT ":"",
22962 + (*status&SS_READY)?"READY ":"",
22963 + (*status&SS_BATDEAD)?"BATDEAD ":"",
22964 + (*status&SS_BATWARN)?"BATWARN ":"",
22965 + (*status&SS_POWERON)?"POWERON ":"",
22966 + (*status&SS_STSCHG)?"STSCHG ":"",
22967 + (*status&SS_3VCARD)?"3VCARD ":"",
22968 + (*status&SS_XVCARD)?"XVCARD ":"");
22969 +
22970 + return 0;
22971 +}
22972 +
22973 +
22974 +/*
22975 + * bcm47xx_pcmcia_get_socket()
22976 + *
22977 + * Implements the get_socket() operation for the in-kernel PCMCIA
22978 + * service (formerly SS_GetSocket in Card Services). Not a very
22979 + * exciting routine.
22980 + *
22981 + * Returns: 0
22982 + */
22983 +static int
22984 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
22985 +{
22986 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
22987 +
22988 + /* This information was given to us in an earlier call to set_socket(),
22989 + * so we're just regurgitating it here:
22990 + */
22991 + *state = pcmcia_socket[sock].cs_state;
22992 + return 0;
22993 +}
22994 +
22995 +
22996 +/*
22997 + * bcm47xx_pcmcia_set_socket()
22998 + *
22999 + * Implements the set_socket() operation for the in-kernel PCMCIA
23000 + * service (formerly SS_SetSocket in Card Services). We more or
23001 + * less punt all of this work and let the kernel handle the details
23002 + * of power configuration, reset, &c. We also record the value of
23003 + * `state' in order to regurgitate it to the PCMCIA core later.
23004 + *
23005 + * Returns: 0
23006 + */
23007 +static int
23008 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
23009 +{
23010 + struct pcmcia_configure configure;
23011 +
23012 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
23013 + "\tVcc %d Vpp %d irq %d\n",
23014 + (state->csc_mask == 0) ? "<NONE>" : "",
23015 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
23016 + (state->csc_mask & SS_READY) ? "READY " : "",
23017 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
23018 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
23019 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
23020 + (state->flags == 0) ? "<NONE>" : "",
23021 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
23022 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
23023 + (state->flags & SS_RESET) ? "RESET " : "",
23024 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
23025 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
23026 + state->Vcc, state->Vpp, state->io_irq);
23027 +
23028 + configure.sock = sock;
23029 + configure.vcc = state->Vcc;
23030 + configure.vpp = state->Vpp;
23031 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
23032 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
23033 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
23034 +
23035 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
23036 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
23037 + return -1;
23038 + }
23039 +
23040 + pcmcia_socket[sock].cs_state = *state;
23041 + return 0;
23042 +}
23043 +
23044 +
23045 +/*
23046 + * bcm47xx_pcmcia_get_io_map()
23047 + *
23048 + * Implements the get_io_map() operation for the in-kernel PCMCIA
23049 + * service (formerly SS_GetIOMap in Card Services). Just returns an
23050 + * I/O map descriptor which was assigned earlier by a set_io_map().
23051 + *
23052 + * Returns: 0 on success, -1 if the map index was out of range
23053 + */
23054 +static int
23055 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
23056 +{
23057 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
23058 +
23059 + if (map->map >= MAX_IO_WIN) {
23060 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23061 + __FUNCTION__, map->map);
23062 + return -1;
23063 + }
23064 +
23065 + *map = pcmcia_socket[sock].io_map[map->map];
23066 + return 0;
23067 +}
23068 +
23069 +
23070 +/*
23071 + * bcm47xx_pcmcia_set_io_map()
23072 + *
23073 + * Implements the set_io_map() operation for the in-kernel PCMCIA
23074 + * service (formerly SS_SetIOMap in Card Services). We configure
23075 + * the map speed as requested, but override the address ranges
23076 + * supplied by Card Services.
23077 + *
23078 + * Returns: 0 on success, -1 on error
23079 + */
23080 +int
23081 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
23082 +{
23083 + unsigned int speed;
23084 + unsigned long start;
23085 +
23086 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
23087 + "\tflags: %s%s%s%s%s%s%s%s\n",
23088 + map->map, map->speed, map->start, map->stop,
23089 + (map->flags == 0) ? "<NONE>" : "",
23090 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23091 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23092 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23093 + (map->flags & MAP_0WS) ? "0WS " : "",
23094 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23095 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
23096 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
23097 +
23098 + if (map->map >= MAX_IO_WIN) {
23099 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23100 + __FUNCTION__, map->map);
23101 + return -1;
23102 + }
23103 +
23104 + if (map->flags & MAP_ACTIVE) {
23105 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
23106 + pcmcia_socket[sock].speed_io = speed;
23107 + }
23108 +
23109 + start = map->start;
23110 +
23111 + if (map->stop == 1) {
23112 + map->stop = PAGE_SIZE - 1;
23113 + }
23114 +
23115 + map->start = pcmcia_socket[sock].virt_io;
23116 + map->stop = map->start + (map->stop - start);
23117 + pcmcia_socket[sock].io_map[map->map] = *map;
23118 + DEBUG(2, "set_io_map %d start %x stop %x\n",
23119 + map->map, map->start, map->stop);
23120 + return 0;
23121 +}
23122 +
23123 +
23124 +/*
23125 + * bcm47xx_pcmcia_get_mem_map()
23126 + *
23127 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
23128 + * service (formerly SS_GetMemMap in Card Services). Just returns a
23129 + * memory map descriptor which was assigned earlier by a
23130 + * set_mem_map() request.
23131 + *
23132 + * Returns: 0 on success, -1 if the map index was out of range
23133 + */
23134 +static int
23135 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
23136 +{
23137 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23138 +
23139 + if (map->map >= MAX_WIN) {
23140 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23141 + __FUNCTION__, map->map);
23142 + return -1;
23143 + }
23144 +
23145 + *map = pcmcia_socket[sock].mem_map[map->map];
23146 + return 0;
23147 +}
23148 +
23149 +
23150 +/*
23151 + * bcm47xx_pcmcia_set_mem_map()
23152 + *
23153 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
23154 + * service (formerly SS_SetMemMap in Card Services). We configure
23155 + * the map speed as requested, but override the address ranges
23156 + * supplied by Card Services.
23157 + *
23158 + * Returns: 0 on success, -1 on error
23159 + */
23160 +static int
23161 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
23162 +{
23163 + unsigned int speed;
23164 + unsigned long start;
23165 + u_long flags;
23166 +
23167 + if (map->map >= MAX_WIN) {
23168 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23169 + __FUNCTION__, map->map);
23170 + return -1;
23171 + }
23172 +
23173 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
23174 + "\tsys_stop %#lx\n\tcard_start %#x\n"
23175 + "\tflags: %s%s%s%s%s%s%s%s\n",
23176 + map->map, map->speed, map->sys_start, map->sys_stop,
23177 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
23178 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23179 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23180 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23181 + (map->flags & MAP_0WS) ? "0WS " : "",
23182 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23183 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
23184 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
23185 +
23186 + if (map->flags & MAP_ACTIVE) {
23187 + /* When clients issue RequestMap, the access speed is not always
23188 + * properly configured:
23189 + */
23190 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
23191 +
23192 + /* TBD */
23193 + if (map->flags & MAP_ATTRIB) {
23194 + pcmcia_socket[sock].speed_attr = speed;
23195 + } else {
23196 + pcmcia_socket[sock].speed_mem = speed;
23197 + }
23198 + }
23199 +
23200 + save_flags(flags);
23201 + cli();
23202 + start = map->sys_start;
23203 +
23204 + if (map->sys_stop == 0)
23205 + map->sys_stop = PAGE_SIZE - 1;
23206 +
23207 + if (map->flags & MAP_ATTRIB) {
23208 + map->sys_start = pcmcia_socket[sock].phys_attr +
23209 + map->card_start;
23210 + } else {
23211 + map->sys_start = pcmcia_socket[sock].phys_mem +
23212 + map->card_start;
23213 + }
23214 +
23215 + map->sys_stop = map->sys_start + (map->sys_stop - start);
23216 + pcmcia_socket[sock].mem_map[map->map] = *map;
23217 + restore_flags(flags);
23218 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
23219 + map->map, map->sys_start, map->sys_stop,
23220 + map->card_start);
23221 + return 0;
23222 +}
23223 +
23224 +
23225 +#if defined(CONFIG_PROC_FS)
23226 +
23227 +/*
23228 + * bcm47xx_pcmcia_proc_setup()
23229 + *
23230 + * Implements the proc_setup() operation for the in-kernel PCMCIA
23231 + * service (formerly SS_ProcSetup in Card Services).
23232 + *
23233 + * Returns: 0 on success, -1 on error
23234 + */
23235 +static void
23236 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
23237 +{
23238 + struct proc_dir_entry *entry;
23239 +
23240 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
23241 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
23242 + return;
23243 + }
23244 +
23245 + entry->read_proc = bcm47xx_pcmcia_proc_status;
23246 + entry->data = (void *)sock;
23247 +}
23248 +
23249 +
23250 +/*
23251 + * bcm47xx_pcmcia_proc_status()
23252 + *
23253 + * Implements the /proc/bus/pccard/??/status file.
23254 + *
23255 + * Returns: the number of characters added to the buffer
23256 + */
23257 +static int
23258 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
23259 + int count, int *eof, void *data)
23260 +{
23261 + char *p = buf;
23262 + unsigned int sock = (unsigned int)data;
23263 +
23264 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
23265 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
23266 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
23267 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
23268 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
23269 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
23270 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
23271 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
23272 +
23273 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
23274 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
23275 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
23276 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
23277 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
23278 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
23279 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
23280 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23281 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
23282 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23283 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
23284 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
23285 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
23286 +
23287 + p += sprintf(p, "mask : %s%s%s%s%s\n",
23288 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
23289 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
23290 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
23291 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
23292 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
23293 +
23294 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
23295 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
23296 + "SS_PWR_AUTO " : "",
23297 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
23298 + "SS_IOCARD " : "",
23299 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
23300 + "SS_RESET " : "",
23301 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
23302 + "SS_SPKR_ENA " : "",
23303 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
23304 + "SS_OUTPUT_ENA " : "");
23305 +
23306 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
23307 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
23308 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
23309 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
23310 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
23311 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
23312 + return p-buf;
23313 +}
23314 +
23315 +
23316 +#endif /* defined(CONFIG_PROC_FS) */
23317 diff -urN linux.old/drivers/pcmcia/bcm4710_pcmcia.c linux.dev/drivers/pcmcia/bcm4710_pcmcia.c
23318 --- linux.old/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
23319 +++ linux.dev/drivers/pcmcia/bcm4710_pcmcia.c 2005-11-07 21:57:07.945592000 +0100
23320 @@ -0,0 +1,266 @@
23321 +/*
23322 + * BCM4710 specific pcmcia routines.
23323 + *
23324 + * Copyright 2004, Broadcom Corporation
23325 + * All Rights Reserved.
23326 + *
23327 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23328 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23329 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23330 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23331 + *
23332 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
23333 + */
23334 +#include <linux/module.h>
23335 +#include <linux/init.h>
23336 +#include <linux/config.h>
23337 +#include <linux/delay.h>
23338 +#include <linux/ioport.h>
23339 +#include <linux/kernel.h>
23340 +#include <linux/tqueue.h>
23341 +#include <linux/timer.h>
23342 +#include <linux/mm.h>
23343 +#include <linux/proc_fs.h>
23344 +#include <linux/version.h>
23345 +#include <linux/types.h>
23346 +#include <linux/pci.h>
23347 +
23348 +#include <pcmcia/version.h>
23349 +#include <pcmcia/cs_types.h>
23350 +#include <pcmcia/cs.h>
23351 +#include <pcmcia/ss.h>
23352 +#include <pcmcia/bulkmem.h>
23353 +#include <pcmcia/cistpl.h>
23354 +#include <pcmcia/bus_ops.h>
23355 +#include "cs_internal.h"
23356 +
23357 +#include <asm/io.h>
23358 +#include <asm/irq.h>
23359 +#include <asm/system.h>
23360 +
23361 +
23362 +#include <typedefs.h>
23363 +#include <bcmdevs.h>
23364 +#include <bcm4710.h>
23365 +#include <sbconfig.h>
23366 +#include <sbextif.h>
23367 +
23368 +#include "bcm4710pcmcia.h"
23369 +
23370 +/* Use a static var for irq dev_id */
23371 +static int bcm47xx_pcmcia_dev_id;
23372 +
23373 +/* Do we think we have a card or not? */
23374 +static int bcm47xx_pcmcia_present = 0;
23375 +
23376 +
23377 +static void bcm4710_pcmcia_reset(void)
23378 +{
23379 + extifregs_t *eir;
23380 + unsigned long s;
23381 + uint32 out0, out1, outen;
23382 +
23383 +
23384 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23385 +
23386 + save_and_cli(s);
23387 +
23388 + /* Use gpio7 to reset the pcmcia slot */
23389 + outen = readl(&eir->gpio[0].outen);
23390 + outen |= BCM47XX_PCMCIA_RESET;
23391 + out0 = readl(&eir->gpio[0].out);
23392 + out0 &= ~(BCM47XX_PCMCIA_RESET);
23393 + out1 = out0 | BCM47XX_PCMCIA_RESET;
23394 +
23395 + writel(out0, &eir->gpio[0].out);
23396 + writel(outen, &eir->gpio[0].outen);
23397 + mdelay(1);
23398 + writel(out1, &eir->gpio[0].out);
23399 + mdelay(1);
23400 + writel(out0, &eir->gpio[0].out);
23401 +
23402 + restore_flags(s);
23403 +}
23404 +
23405 +
23406 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
23407 +{
23408 + struct pci_dev *pdev;
23409 + extifregs_t *eir;
23410 + uint32 outen, intp, intm, tmp;
23411 + uint16 *attrsp;
23412 + int rc = 0, i;
23413 + extern unsigned long bcm4710_cpu_cycle;
23414 +
23415 +
23416 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
23417 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
23418 + return -ENODEV;
23419 + }
23420 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
23421 +
23422 + /* Initialize the pcmcia i/f: 16bit no swap */
23423 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
23424 +
23425 +#ifdef notYet
23426 +
23427 + /* Set the timing for memory accesses */
23428 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23429 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23430 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23431 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23432 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
23433 +
23434 + /* Set the timing for I/O accesses */
23435 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23436 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23437 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23438 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23439 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
23440 +
23441 + /* Set the timing for attribute accesses */
23442 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23443 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23444 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23445 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23446 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
23447 +
23448 +#endif
23449 + /* Make sure gpio0 and gpio5 are inputs */
23450 + outen = readl(&eir->gpio[0].outen);
23451 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
23452 + writel(outen, &eir->gpio[0].outen);
23453 +
23454 + /* Issue a reset to the pcmcia socket */
23455 + bcm4710_pcmcia_reset();
23456 +
23457 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23458 + /* Setup gpio5 to be the STSCHG interrupt */
23459 + intp = readl(&eir->gpiointpolarity);
23460 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
23461 + intm = readl(&eir->gpiointmask);
23462 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
23463 +#endif
23464 +
23465 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
23466 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
23467 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
23468 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
23469 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
23470 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
23471 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
23472 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
23473 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
23474 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
23475 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
23476 +
23477 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23478 + /* Request pcmcia interrupt */
23479 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
23480 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
23481 +#endif
23482 +
23483 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
23484 + tmp = readw(&attrsp[0]);
23485 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
23486 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
23487 + bcm47xx_pcmcia_present = 0;
23488 + } else {
23489 + bcm47xx_pcmcia_present = 1;
23490 + }
23491 +
23492 + /* There's only one socket */
23493 + return 1;
23494 +}
23495 +
23496 +static int bcm4710_pcmcia_shutdown(void)
23497 +{
23498 + extifregs_t *eir;
23499 + uint32 intm;
23500 +
23501 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23502 +
23503 + /* Disable the pcmcia i/f */
23504 + writel(0, &eir->pcmcia_config);
23505 +
23506 + /* Reset gpio's */
23507 + intm = readl(&eir->gpiointmask);
23508 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
23509 +
23510 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
23511 +
23512 + return 0;
23513 +}
23514 +
23515 +static int
23516 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
23517 +{
23518 + extifregs_t *eir;
23519 +
23520 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23521 +
23522 +
23523 + if (sock != 0) {
23524 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
23525 + return -1;
23526 + }
23527 +
23528 + if (bcm47xx_pcmcia_present) {
23529 + state->detect = 1;
23530 + state->ready = 1;
23531 + state->bvd1 = 1;
23532 + state->bvd2 = 1;
23533 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
23534 + state->vs_3v = 0;
23535 + state->vs_Xv = 0;
23536 + } else {
23537 + state->detect = 0;
23538 + state->ready = 0;
23539 + }
23540 +
23541 + return 1;
23542 +}
23543 +
23544 +
23545 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
23546 +{
23547 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23548 +
23549 + info->irq = BCM47XX_PCMCIA_IRQ;
23550 +
23551 + return 0;
23552 +}
23553 +
23554 +
23555 +static int
23556 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
23557 +{
23558 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23559 +
23560 +
23561 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
23562 + configure->vpp, configure->output, configure->speaker, configure->reset);
23563 +
23564 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
23565 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
23566 + configure->vpp);
23567 + }
23568 +
23569 + if (configure->reset) {
23570 + /* Issue a reset to the pcmcia socket */
23571 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
23572 + bcm4710_pcmcia_reset();
23573 + }
23574 +
23575 +
23576 + return 0;
23577 +}
23578 +
23579 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
23580 + bcm4710_pcmcia_init,
23581 + bcm4710_pcmcia_shutdown,
23582 + bcm4710_pcmcia_socket_state,
23583 + bcm4710_pcmcia_get_irq_info,
23584 + bcm4710_pcmcia_configure_socket
23585 +};
23586 +
23587 diff -urN linux.old/drivers/pcmcia/bcm4710pcmcia.h linux.dev/drivers/pcmcia/bcm4710pcmcia.h
23588 --- linux.old/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
23589 +++ linux.dev/drivers/pcmcia/bcm4710pcmcia.h 2005-11-07 21:57:07.945592000 +0100
23590 @@ -0,0 +1,118 @@
23591 +/*
23592 + *
23593 + * bcm47xx pcmcia driver
23594 + *
23595 + * Copyright 2004, Broadcom Corporation
23596 + * All Rights Reserved.
23597 + *
23598 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23599 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23600 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23601 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23602 + *
23603 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
23604 + * from www.handhelds.org,
23605 + * and au1000_generic.c from oss.sgi.com.
23606 + *
23607 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
23608 + */
23609 +
23610 +#if !defined(_BCM4710PCMCIA_H)
23611 +#define _BCM4710PCMCIA_H
23612 +
23613 +#include <pcmcia/cs_types.h>
23614 +#include <pcmcia/ss.h>
23615 +#include <pcmcia/bulkmem.h>
23616 +#include <pcmcia/cistpl.h>
23617 +#include "cs_internal.h"
23618 +
23619 +
23620 +/* The 47xx can only support one socket */
23621 +#define BCM47XX_PCMCIA_MAX_SOCK 1
23622 +
23623 +/* In the bcm947xx gpio's are used for some pcmcia functions */
23624 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
23625 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
23626 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
23627 +
23628 +#define BCM47XX_PCMCIA_IRQ 2
23629 +
23630 +/* The socket driver actually works nicely in interrupt-driven form,
23631 + * so the (relatively infrequent) polling is "just to be sure."
23632 + */
23633 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
23634 +
23635 +#define BCM47XX_PCMCIA_IO_SPEED (255)
23636 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
23637 +
23638 +
23639 +struct pcmcia_state {
23640 + unsigned detect: 1,
23641 + ready: 1,
23642 + bvd1: 1,
23643 + bvd2: 1,
23644 + wrprot: 1,
23645 + vs_3v: 1,
23646 + vs_Xv: 1;
23647 +};
23648 +
23649 +
23650 +struct pcmcia_configure {
23651 + unsigned sock: 8,
23652 + vcc: 8,
23653 + vpp: 8,
23654 + output: 1,
23655 + speaker: 1,
23656 + reset: 1;
23657 +};
23658 +
23659 +struct pcmcia_irq_info {
23660 + unsigned int sock;
23661 + unsigned int irq;
23662 +};
23663 +
23664 +/* This structure encapsulates per-socket state which we might need to
23665 + * use when responding to a Card Services query of some kind.
23666 + */
23667 +struct bcm47xx_pcmcia_socket {
23668 + socket_state_t cs_state;
23669 + struct pcmcia_state k_state;
23670 + unsigned int irq;
23671 + void (*handler)(void *, unsigned int);
23672 + void *handler_info;
23673 + pccard_io_map io_map[MAX_IO_WIN];
23674 + pccard_mem_map mem_map[MAX_WIN];
23675 + ioaddr_t virt_io, phys_attr, phys_mem;
23676 + unsigned short speed_io, speed_attr, speed_mem;
23677 +};
23678 +
23679 +struct pcmcia_init {
23680 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
23681 +};
23682 +
23683 +struct pcmcia_low_level {
23684 + int (*init)(struct pcmcia_init *);
23685 + int (*shutdown)(void);
23686 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
23687 + int (*get_irq_info)(struct pcmcia_irq_info *);
23688 + int (*configure_socket)(const struct pcmcia_configure *);
23689 +};
23690 +
23691 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
23692 +
23693 +/* I/O pins replacing memory pins
23694 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
23695 + *
23696 + * These signals change meaning when going from memory-only to
23697 + * memory-or-I/O interface:
23698 + */
23699 +#define iostschg bvd1
23700 +#define iospkr bvd2
23701 +
23702 +
23703 +/*
23704 + * Declaration for implementation specific low_level operations.
23705 + */
23706 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
23707 +
23708 +#endif /* !defined(_BCM4710PCMCIA_H) */
23709 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
23710 --- linux.old/include/asm-mips/bootinfo.h 2005-11-07 23:12:51.434940250 +0100
23711 +++ linux.dev/include/asm-mips/bootinfo.h 2005-11-07 21:57:07.945592000 +0100
23712 @@ -37,6 +37,7 @@
23713 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
23714 #define MACH_GROUP_LASAT 21
23715 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
23716 +#define MACH_GROUP_BRCM 23 /* Broadcom */
23717
23718 /*
23719 * Valid machtype values for group unknown (low order halfword of mips_machtype)
23720 @@ -197,6 +198,15 @@
23721 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
23722
23723 /*
23724 + * Valid machtypes for group Broadcom
23725 + */
23726 +#define MACH_BCM93725 0
23727 +#define MACH_BCM93725_VJ 1
23728 +#define MACH_BCM93730 2
23729 +#define MACH_BCM947XX 3
23730 +#define MACH_BCM933XX 4
23731 +
23732 +/*
23733 * Valid machtype for group TITAN
23734 */
23735 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
23736 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
23737 --- linux.old/include/asm-mips/cpu.h 2005-11-07 23:12:51.434940250 +0100
23738 +++ linux.dev/include/asm-mips/cpu.h 2005-11-07 21:57:07.965593250 +0100
23739 @@ -22,6 +22,11 @@
23740 spec.
23741 */
23742
23743 +#define PRID_COPT_MASK 0xff000000
23744 +#define PRID_COMP_MASK 0x00ff0000
23745 +#define PRID_IMP_MASK 0x0000ff00
23746 +#define PRID_REV_MASK 0x000000ff
23747 +
23748 #define PRID_COMP_LEGACY 0x000000
23749 #define PRID_COMP_MIPS 0x010000
23750 #define PRID_COMP_BROADCOM 0x020000
23751 @@ -58,6 +63,7 @@
23752 #define PRID_IMP_RM7000 0x2700
23753 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
23754 #define PRID_IMP_RM9000 0x3400
23755 +#define PRID_IMP_BCM4710 0x4000
23756 #define PRID_IMP_R5432 0x5400
23757 #define PRID_IMP_R5500 0x5500
23758 #define PRID_IMP_4KC 0x8000
23759 @@ -66,10 +72,16 @@
23760 #define PRID_IMP_4KEC 0x8400
23761 #define PRID_IMP_4KSC 0x8600
23762 #define PRID_IMP_25KF 0x8800
23763 +#define PRID_IMP_BCM3302 0x9000
23764 +#define PRID_IMP_BCM3303 0x9100
23765 #define PRID_IMP_24K 0x9300
23766
23767 #define PRID_IMP_UNKNOWN 0xff00
23768
23769 +#define BCM330X(id) \
23770 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
23771 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
23772 +
23773 /*
23774 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
23775 */
23776 @@ -174,7 +186,9 @@
23777 #define CPU_AU1550 57
23778 #define CPU_24K 58
23779 #define CPU_AU1200 59
23780 -#define CPU_LAST 59
23781 +#define CPU_BCM4710 60
23782 +#define CPU_BCM3302 61
23783 +#define CPU_LAST 61
23784
23785 /*
23786 * ISA Level encodings
23787 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
23788 --- linux.old/include/asm-mips/r4kcache.h 2005-11-07 23:12:51.438940500 +0100
23789 +++ linux.dev/include/asm-mips/r4kcache.h 2005-11-07 21:57:08.161605500 +0100
23790 @@ -658,4 +658,17 @@
23791 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
23792 }
23793
23794 +extern inline void fill_icache_line(unsigned long addr)
23795 +{
23796 + __asm__ __volatile__(
23797 + ".set noreorder\n\t"
23798 + ".set mips3\n\t"
23799 + "cache %1, (%0)\n\t"
23800 + ".set mips0\n\t"
23801 + ".set reorder"
23802 + :
23803 + : "r" (addr),
23804 + "i" (Fill));
23805 +}
23806 +
23807 #endif /* __ASM_R4KCACHE_H */
23808 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
23809 --- linux.old/include/asm-mips/serial.h 2005-11-07 23:12:51.442940750 +0100
23810 +++ linux.dev/include/asm-mips/serial.h 2005-11-07 21:57:07.993595000 +0100
23811 @@ -223,6 +223,13 @@
23812 #define TXX927_SERIAL_PORT_DEFNS
23813 #endif
23814
23815 +#ifdef CONFIG_BCM947XX
23816 +/* reserve 4 ports to be configured at runtime */
23817 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
23818 +#else
23819 +#define BCM947XX_SERIAL_PORT_DEFNS
23820 +#endif
23821 +
23822 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
23823 #define STD_SERIAL_PORT_DEFNS \
23824 /* UART CLK PORT IRQ FLAGS */ \
23825 @@ -470,6 +477,7 @@
23826 #define SERIAL_PORT_DFNS \
23827 ATLAS_SERIAL_PORT_DEFNS \
23828 AU1000_SERIAL_PORT_DEFNS \
23829 + BCM947XX_SERIAL_PORT_DEFNS \
23830 COBALT_SERIAL_PORT_DEFNS \
23831 DDB5477_SERIAL_PORT_DEFNS \
23832 EV96100_SERIAL_PORT_DEFNS \
23833 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
23834 --- linux.old/init/do_mounts.c 2005-11-07 23:12:51.458941750 +0100
23835 +++ linux.dev/init/do_mounts.c 2005-11-07 21:57:07.993595000 +0100
23836 @@ -254,7 +254,13 @@
23837 { "ftlb", 0x2c08 },
23838 { "ftlc", 0x2c10 },
23839 { "ftld", 0x2c18 },
23840 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
23841 { "mtdblock", 0x1f00 },
23842 + { "mtdblock0",0x1f00 },
23843 + { "mtdblock1",0x1f01 },
23844 + { "mtdblock2",0x1f02 },
23845 + { "mtdblock3",0x1f03 },
23846 +#endif
23847 { "nb", 0x2b00 },
23848 { NULL, 0 }
23849 };
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