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add my 2.6.15-rc5 port (yay) with devfs. The PCI subsystem is broken on Broadcom...
[openwrt.git] / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/bcmsrom.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/bcmsrom.c
2 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-12-13 14:59:52.000000000 +0100
4 @@ -0,0 +1,685 @@
5 +/*
6 + * Misc useful routines to access NIC SROM
7 + *
8 + * Copyright 2001-2003, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <osl.h>
20 +#include <bcmutils.h>
21 +#include <bcmsrom.h>
22 +#include <bcmdevs.h>
23 +#include <bcmendian.h>
24 +#include <sbpcmcia.h>
25 +#include <pcicfg.h>
26 +
27 +#include <proto/ethernet.h> /* for sprom content groking */
28 +
29 +#define VARS_MAX 4096 /* should be reduced */
30 +
31 +static int initvars_srom_pci(void *curmap, char **vars, int *count);
32 +static int initvars_cis_pcmcia(void *osh, char **vars, int *count);
33 +static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
34 +static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
35 +static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
36 +static int sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc);
37 +
38 +/*
39 + * Initialize the vars from the right source for this platform.
40 + * Return 0 on success, nonzero on error.
41 + */
42 +int
43 +srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count)
44 +{
45 + if (vars == NULL)
46 + return (0);
47 +
48 + switch (bus) {
49 + case SB_BUS:
50 + /* These two could be asserts ... */
51 + *vars = NULL;
52 + *count = 0;
53 + return(0);
54 +
55 + case PCI_BUS:
56 + ASSERT(curmap); /* can not be NULL */
57 + return(initvars_srom_pci(curmap, vars, count));
58 +
59 + case PCMCIA_BUS:
60 + return(initvars_cis_pcmcia(osh, vars, count));
61 +
62 +
63 + default:
64 + ASSERT(0);
65 + }
66 + return (-1);
67 +}
68 +
69 +
70 +/* support only 16-bit word read from srom */
71 +int
72 +srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
73 +{
74 + void *srom;
75 + uint i, off, nw;
76 +
77 + /* check input - 16-bit access only */
78 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
79 + return 1;
80 +
81 + if (bus == PCI_BUS) {
82 + if (!curmap)
83 + return 1;
84 + srom = (void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
85 + if (sprom_read_pci(srom, byteoff, buf, nbytes, FALSE))
86 + return 1;
87 + } else if (bus == PCMCIA_BUS) {
88 + off = byteoff / 2;
89 + nw = nbytes / 2;
90 + for (i = 0; i < nw; i++) {
91 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
92 + return 1;
93 + }
94 + } else {
95 + return 1;
96 + }
97 +
98 + return 0;
99 +}
100 +
101 +/* support only 16-bit word write into srom */
102 +int
103 +srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
104 +{
105 + uint16 *srom;
106 + uint i, off, nw, crc_range;
107 + uint16 image[SPROM_SIZE], *p;
108 + uint8 crc;
109 + volatile uint32 val32;
110 +
111 + /* check input - 16-bit access only */
112 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
113 + return 1;
114 +
115 + crc_range = ((bus == PCMCIA_BUS) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
116 +
117 + /* if changes made inside crc cover range */
118 + if (byteoff < crc_range) {
119 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
120 + /* read data including entire first 64 words from srom */
121 + if (srom_read(bus, curmap, osh, 0, nw * 2, image))
122 + return 1;
123 + /* make changes */
124 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
125 + /* calculate crc */
126 + htol16_buf(image, crc_range);
127 + crc = ~crc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
128 + ltoh16_buf(image, crc_range);
129 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
130 + p = image;
131 + off = 0;
132 + } else {
133 + p = buf;
134 + off = byteoff / 2;
135 + nw = nbytes / 2;
136 + }
137 +
138 + if (bus == PCI_BUS) {
139 + srom = (uint16*)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
140 + /* enable writes to the SPROM */
141 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
142 + val32 |= SPROM_WRITEEN;
143 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
144 + bcm_mdelay(500);
145 + /* write srom */
146 + for (i = 0; i < nw; i++) {
147 + W_REG(&srom[off + i], p[i]);
148 + bcm_mdelay(20);
149 + }
150 + /* disable writes to the SPROM */
151 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
152 + } else if (bus == PCMCIA_BUS) {
153 + /* enable writes to the SPROM */
154 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
155 + return 1;
156 + bcm_mdelay(500);
157 + /* write srom */
158 + for (i = 0; i < nw; i++) {
159 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
160 + bcm_mdelay(20);
161 + }
162 + /* disable writes to the SPROM */
163 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
164 + return 1;
165 + } else {
166 + return 1;
167 + }
168 +
169 + bcm_mdelay(500);
170 + return 0;
171 +}
172 +
173 +
174 +int
175 +srom_parsecis(uint8 *cis, char **vars, int *count)
176 +{
177 + char eabuf[32];
178 + char *vp, *base;
179 + uint8 tup, tlen, sromrev = 1;
180 + int i, j;
181 + uint varsize;
182 + bool ag_init = FALSE;
183 + uint16 w;
184 +
185 + ASSERT(vars);
186 + ASSERT(count);
187 +
188 + base = vp = MALLOC(VARS_MAX);
189 + ASSERT(vp);
190 +
191 + i = 0;
192 + do {
193 + tup = cis[i++];
194 + tlen = cis[i++];
195 +
196 + switch (tup) {
197 + case CISTPL_MANFID:
198 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
199 + vp++;
200 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
201 + vp++;
202 + break;
203 +
204 + case CISTPL_FUNCE:
205 + if (cis[i] == LAN_NID) {
206 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
207 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
208 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
209 + vp++;
210 + }
211 + break;
212 +
213 + case CISTPL_CFTABLE:
214 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
215 + vp++;
216 + break;
217 +
218 + case CISTPL_BRCM_HNBU:
219 + switch (cis[i]) {
220 + case HNBU_CHIPID:
221 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
222 + vp++;
223 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
224 + vp++;
225 + if (tlen == 7) {
226 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
227 + vp++;
228 + }
229 + break;
230 +
231 + case HNBU_BOARDREV:
232 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
233 + vp++;
234 + break;
235 +
236 + case HNBU_AA:
237 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
238 + vp++;
239 + break;
240 +
241 + case HNBU_AG:
242 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
243 + vp++;
244 + ag_init = TRUE;
245 + break;
246 +
247 + case HNBU_CC:
248 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
249 + vp++;
250 + break;
251 +
252 + case HNBU_PAPARMS:
253 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
254 + vp++;
255 + if (tlen == 9) {
256 + /* New version */
257 + for (j = 0; j < 3; j++) {
258 + vp += sprintf(vp, "pa0b%d=%d", j,
259 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
260 + vp++;
261 + }
262 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
263 + vp++;
264 + }
265 + break;
266 +
267 + case HNBU_OEM:
268 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
269 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
270 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
271 + vp++;
272 + break;
273 + case HNBU_BOARDFLAGS:
274 + w = (cis[i + 2] << 8) + cis[i + 1];
275 + if (w == 0xffff) w = 0;
276 + vp += sprintf(vp, "boardflags=%d", w);
277 + vp++;
278 + break;
279 + case HNBU_LED:
280 + if (cis[i + 1] != 0xff) {
281 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
282 + vp++;
283 + }
284 + if (cis[i + 2] != 0xff) {
285 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
286 + vp++;
287 + }
288 + if (cis[i + 3] != 0xff) {
289 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
290 + vp++;
291 + }
292 + if (cis[i + 4] != 0xff) {
293 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
294 + vp++;
295 + }
296 + break;
297 + }
298 + break;
299 +
300 + }
301 + i += tlen;
302 + } while (tup != 0xff);
303 +
304 + /* Set the srom version */
305 + vp += sprintf(vp, "sromrev=%d", sromrev);
306 + vp++;
307 +
308 + /* For now just set boardflags2 to zero */
309 + vp += sprintf(vp, "boardflags2=0");
310 + vp++;
311 +
312 + /* if there is no antenna gain field, set default */
313 + if (ag_init == FALSE) {
314 + vp += sprintf(vp, "ag0=%d", 0xff);
315 + vp++;
316 + }
317 +
318 + /* final nullbyte terminator */
319 + *vp++ = '\0';
320 + varsize = (uint)vp - (uint)base;
321 +
322 + ASSERT(varsize < VARS_MAX);
323 +
324 + if (varsize == VARS_MAX) {
325 + *vars = base;
326 + } else {
327 + vp = MALLOC(varsize);
328 + ASSERT(vp);
329 + bcopy(base, vp, varsize);
330 + MFREE(base, VARS_MAX);
331 + *vars = vp;
332 + }
333 + *count = varsize;
334 +
335 + return (0);
336 +}
337 +
338 +
339 +/* set PCMCIA sprom command register */
340 +static int
341 +sprom_cmd_pcmcia(void *osh, uint8 cmd)
342 +{
343 + uint8 status;
344 + uint wait_cnt = 1000;
345 +
346 + /* write sprom command register */
347 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
348 +
349 + /* wait status */
350 + while (wait_cnt--) {
351 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
352 + if (status & SROM_DONE)
353 + return 0;
354 + }
355 + return 1;
356 +}
357 +
358 +/* read a word from the PCMCIA srom */
359 +static int
360 +sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
361 +{
362 + uint8 addr_l, addr_h, data_l, data_h;
363 +
364 + addr_l = (uint8)((addr * 2) & 0xff);
365 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
366 +
367 + /* set address */
368 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
369 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
370 +
371 + /* do read */
372 + if (sprom_cmd_pcmcia(osh, SROM_READ))
373 + return 1;
374 +
375 + /* read data */
376 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
377 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
378 +
379 + *data = (data_h << 8) | data_l;
380 + return 0;
381 +}
382 +
383 +/* write a word to the PCMCIA srom */
384 +static int
385 +sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
386 +{
387 + uint8 addr_l, addr_h, data_l, data_h;
388 +
389 + addr_l = (uint8)((addr * 2) & 0xff);
390 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
391 + data_l = (uint8)(data & 0xff);
392 + data_h = (uint8)((data >> 8) & 0xff);
393 +
394 + /* set address */
395 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
396 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
397 +
398 + /* write data */
399 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
400 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
401 +
402 + /* do write */
403 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
404 +}
405 +
406 +/*
407 + * Read in and validate sprom.
408 + * Return 0 on success, nonzero on error.
409 + */
410 +static int
411 +sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc)
412 +{
413 + int off, nw;
414 + uint8 chk8;
415 + int i;
416 +
417 + off = byteoff / 2;
418 + nw = ROUNDUP(nbytes, 2) / 2;
419 +
420 + /* read the sprom */
421 + for (i = 0; i < nw; i++)
422 + buf[i] = R_REG(&sprom[off + i]);
423 +
424 + if (check_crc) {
425 + /* fixup the endianness so crc8 will pass */
426 + htol16_buf(buf, nw * 2);
427 + if ((chk8 = crc8((uchar*)buf, nbytes, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
428 + return (1);
429 + /* now correct the endianness of the byte array */
430 + ltoh16_buf(buf, nw * 2);
431 + }
432 +
433 + return (0);
434 +}
435 +
436 +/*
437 + * Initialize nonvolatile variable table from sprom.
438 + * Return 0 on success, nonzero on error.
439 + */
440 +
441 +static int
442 +initvars_srom_pci(void *curmap, char **vars, int *count)
443 +{
444 + uint16 w, b[64];
445 + uint8 sromrev;
446 + struct ether_addr ea;
447 + char eabuf[32];
448 + int c, woff, i;
449 + char *vp, *base;
450 +
451 + if (sprom_read_pci((void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof (b), TRUE))
452 + return (-1);
453 +
454 + /* top word of sprom contains version and crc8 */
455 + sromrev = b[63] & 0xff;
456 + if ((sromrev != 1) && (sromrev != 2)) {
457 + return (-2);
458 + }
459 +
460 + ASSERT(vars);
461 + ASSERT(count);
462 +
463 + base = vp = MALLOC(VARS_MAX);
464 + ASSERT(vp);
465 +
466 + vp += sprintf(vp, "sromrev=%d", sromrev);
467 + vp++;
468 +
469 + if (sromrev >= 2) {
470 + /* New section takes over the 4th hardware function space */
471 +
472 + /* Word 28 is boardflags2 */
473 + vp += sprintf(vp, "boardflags2=%d", b[28]);
474 + vp++;
475 +
476 + /* Word 29 is max power 11a high/low */
477 + w = b[29];
478 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
479 + vp++;
480 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
481 + vp++;
482 +
483 + /* Words 30-32 set the 11alow pa settings,
484 + * 33-35 are the 11ahigh ones.
485 + */
486 + for (i = 0; i < 3; i++) {
487 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
488 + vp++;
489 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
490 + vp++;
491 + }
492 + w = b[59];
493 + if (w == 0)
494 + vp += sprintf(vp, "ccode=");
495 + else
496 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
497 + vp++;
498 +
499 + }
500 +
501 + /* parameter section of sprom starts at byte offset 72 */
502 + woff = 72/2;
503 +
504 + /* first 6 bytes are il0macaddr */
505 + ea.octet[0] = (b[woff] >> 8) & 0xff;
506 + ea.octet[1] = b[woff] & 0xff;
507 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
508 + ea.octet[3] = b[woff+1] & 0xff;
509 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
510 + ea.octet[5] = b[woff+2] & 0xff;
511 + woff += ETHER_ADDR_LEN/2 ;
512 + bcm_ether_ntoa((uchar*)&ea, eabuf);
513 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
514 + vp++;
515 +
516 + /* next 6 bytes are et0macaddr */
517 + ea.octet[0] = (b[woff] >> 8) & 0xff;
518 + ea.octet[1] = b[woff] & 0xff;
519 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
520 + ea.octet[3] = b[woff+1] & 0xff;
521 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
522 + ea.octet[5] = b[woff+2] & 0xff;
523 + woff += ETHER_ADDR_LEN/2 ;
524 + bcm_ether_ntoa((uchar*)&ea, eabuf);
525 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
526 + vp++;
527 +
528 + /* next 6 bytes are et1macaddr */
529 + ea.octet[0] = (b[woff] >> 8) & 0xff;
530 + ea.octet[1] = b[woff] & 0xff;
531 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
532 + ea.octet[3] = b[woff+1] & 0xff;
533 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
534 + ea.octet[5] = b[woff+2] & 0xff;
535 + woff += ETHER_ADDR_LEN/2 ;
536 + bcm_ether_ntoa((uchar*)&ea, eabuf);
537 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
538 + vp++;
539 +
540 + /*
541 + * Enet phy settings one or two singles or a dual
542 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
543 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
544 + * Bit 14 : Mdio for enet0
545 + * Bit 15 : Mdio for enet1
546 + */
547 + w = b[woff];
548 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
549 + vp++;
550 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
551 + vp++;
552 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
553 + vp++;
554 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
555 + vp++;
556 +
557 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
558 + w = b[46];
559 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
560 + vp++;
561 +
562 + if (sromrev > 1)
563 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
564 + else
565 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
566 + vp++;
567 +
568 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
569 + vp++;
570 +
571 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
572 + vp++;
573 +
574 + /* Words 47-49 set the (wl) pa settings */
575 + woff = 47;
576 +
577 + for (i = 0; i < 3; i++) {
578 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
579 + vp++;
580 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
581 + vp++;
582 + }
583 +
584 + /*
585 + * Words 50-51 set the customer-configured wl led behavior.
586 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
587 + * LED behavior values defined in wlioctl.h .
588 + */
589 + w = b[50];
590 + if ((w != 0) && (w != 0xffff)) {
591 + /* gpio0 */
592 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
593 + vp++;
594 +
595 + /* gpio1 */
596 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
597 + vp++;
598 + }
599 + w = b[51];
600 + if ((w != 0) && (w != 0xffff)) {
601 + /* gpio2 */
602 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
603 + vp++;
604 +
605 + /* gpio3 */
606 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
607 + vp++;
608 + }
609 +
610 + /* Word 52 is max power 0/1 */
611 + w = b[52];
612 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
613 + vp++;
614 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
615 + vp++;
616 +
617 + /* Word 56 is idle tssi target 0/1 */
618 + w = b[56];
619 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
620 + vp++;
621 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
622 + vp++;
623 +
624 + /* Word 57 is boardflags, if not programmed make it zero */
625 + w = b[57];
626 + if (w == 0xffff) w = 0;
627 + vp += sprintf(vp, "boardflags=%d", w);
628 + vp++;
629 +
630 + /* Word 58 is antenna gain 0/1 */
631 + w = b[58];
632 + vp += sprintf(vp, "ag0=%d", w & 0xff);
633 + vp++;
634 +
635 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
636 + vp++;
637 +
638 + if (sromrev == 1) {
639 + /* set the oem string */
640 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
641 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
642 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
643 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
644 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
645 + vp++;
646 + }
647 +
648 + /* final nullbyte terminator */
649 + *vp++ = '\0';
650 +
651 + c = vp - base;
652 + ASSERT(c <= VARS_MAX);
653 +
654 + if (c == VARS_MAX) {
655 + *vars = base;
656 + } else {
657 + vp = MALLOC(c);
658 + ASSERT(vp);
659 + bcopy(base, vp, c);
660 + MFREE(base, VARS_MAX);
661 + *vars = vp;
662 + }
663 + *count = c;
664 +
665 + return (0);
666 +}
667 +
668 +/*
669 + * Read the cis and call parsecis to initialize the vars.
670 + * Return 0 on success, nonzero on error.
671 + */
672 +static int
673 +initvars_cis_pcmcia(void *osh, char **vars, int *count)
674 +{
675 + uint8 *cis = NULL;
676 + int rc;
677 +
678 + if ((cis = MALLOC(CIS_SIZE)) == NULL)
679 + return (-1);
680 +
681 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, CIS_SIZE);
682 +
683 + rc = srom_parsecis(cis, vars, count);
684 +
685 + MFREE(cis, CIS_SIZE);
686 +
687 + return (rc);
688 +}
689 +
690 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/bcmutils.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/bcmutils.c
691 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
692 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-12-13 14:59:52.000000000 +0100
693 @@ -0,0 +1,691 @@
694 +/*
695 + * Misc useful OS-independent routines.
696 + *
697 + * Copyright 2001-2003, Broadcom Corporation
698 + * All Rights Reserved.
699 + *
700 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
701 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
702 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
703 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
704 + * $Id: bcmutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
705 + */
706 +
707 +#include <typedefs.h>
708 +#include <osl.h>
709 +#include <bcmutils.h>
710 +#include <bcmendian.h>
711 +#include <bcmnvram.h>
712 +
713 +unsigned char bcm_ctype[] = {
714 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
715 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
716 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
717 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
718 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
719 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
720 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
721 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
722 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
723 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
724 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
725 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
726 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
727 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
728 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
729 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
730 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
731 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
732 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
733 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
734 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
735 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
736 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
737 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
738 +};
739 +
740 +uchar
741 +bcm_toupper(uchar c)
742 +{
743 + if (bcm_islower(c))
744 + c -= 'a'-'A';
745 + return (c);
746 +}
747 +
748 +ulong
749 +bcm_strtoul(char *cp, char **endp, uint base)
750 +{
751 + ulong result, value;
752 + bool minus;
753 +
754 + minus = FALSE;
755 +
756 + while (bcm_isspace(*cp))
757 + cp++;
758 +
759 + if (cp[0] == '+')
760 + cp++;
761 + else if (cp[0] == '-') {
762 + minus = TRUE;
763 + cp++;
764 + }
765 +
766 + if (base == 0) {
767 + if (cp[0] == '0') {
768 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
769 + base = 16;
770 + cp = &cp[2];
771 + } else {
772 + base = 8;
773 + cp = &cp[1];
774 + }
775 + } else
776 + base = 10;
777 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
778 + cp = &cp[2];
779 + }
780 +
781 + result = 0;
782 +
783 + while (bcm_isxdigit(*cp) &&
784 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
785 + result = result*base + value;
786 + cp++;
787 + }
788 +
789 + if (minus)
790 + result = (ulong)(result * -1);
791 +
792 + if (endp)
793 + *endp = (char *)cp;
794 +
795 + return (result);
796 +}
797 +
798 +uint
799 +bcm_atoi(char *s)
800 +{
801 + uint n;
802 +
803 + n = 0;
804 +
805 + while (bcm_isdigit(*s))
806 + n = (n * 10) + *s++ - '0';
807 + return (n);
808 +}
809 +
810 +void
811 +deadbeef(char *p, uint len)
812 +{
813 + static uchar meat[] = { 0xde, 0xad, 0xbe, 0xef };
814 +
815 + while (len-- > 0) {
816 + *p = meat[((uint)p) & 3];
817 + p++;
818 + }
819 +}
820 +
821 +/* pretty hex print a contiguous buffer */
822 +void
823 +prhex(char *msg, uchar *buf, uint nbytes)
824 +{
825 + char line[256];
826 + char* p;
827 + uint i;
828 +
829 + if (msg && (msg[0] != '\0'))
830 + printf("%s: ", msg);
831 +
832 + p = line;
833 + for (i = 0; i < nbytes; i++) {
834 + if (i % 16 == 0) {
835 + p += sprintf(p, "%04d: ", i); /* line prefix */
836 + }
837 + p += sprintf(p, "%02x ", buf[i]);
838 + if (i % 16 == 15) {
839 + printf("%s\n", line); /* flush line */
840 + p = line;
841 + }
842 + }
843 +
844 + /* flush last partial line */
845 + if (p != line)
846 + printf("%s\n", line);
847 +}
848 +
849 +/* pretty hex print a pkt buffer chain */
850 +void
851 +prpkt(char *msg, void *drv, void *p0)
852 +{
853 + void *p;
854 +
855 + if (msg && (msg[0] != '\0'))
856 + printf("%s: ", msg);
857 +
858 + for (p = p0; p; p = PKTNEXT(drv, p))
859 + prhex(NULL, PKTDATA(drv, p), PKTLEN(drv, p));
860 +}
861 +
862 +/* copy a pkt buffer chain into a buffer */
863 +uint
864 +pktcopy(void *drv, void *p, uint offset, int len, uchar *buf)
865 +{
866 + uint n, ret = 0;
867 +
868 + if (len < 0)
869 + len = 4096; /* "infinite" */
870 +
871 + /* skip 'offset' bytes */
872 + for (; p && offset; p = PKTNEXT(drv, p)) {
873 + if (offset < (uint)PKTLEN(drv, p))
874 + break;
875 + offset -= PKTLEN(drv, p);
876 + }
877 +
878 + if (!p)
879 + return 0;
880 +
881 + /* copy the data */
882 + for (; p && len; p = PKTNEXT(drv, p)) {
883 + n = MIN((uint)PKTLEN(drv, p) - offset, (uint)len);
884 + bcopy(PKTDATA(drv, p) + offset, buf, n);
885 + buf += n;
886 + len -= n;
887 + ret += n;
888 + offset = 0;
889 + }
890 +
891 + return ret;
892 +}
893 +
894 +/* return total length of buffer chain */
895 +uint
896 +pkttotlen(void *drv, void *p)
897 +{
898 + uint total;
899 +
900 + total = 0;
901 + for (; p; p = PKTNEXT(drv, p))
902 + total += PKTLEN(drv, p);
903 + return (total);
904 +}
905 +
906 +
907 +uchar*
908 +bcm_ether_ntoa(char *ea, char *buf)
909 +{
910 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
911 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
912 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
913 + return (buf);
914 +}
915 +
916 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
917 +int
918 +bcm_ether_atoe(char *p, char *ea)
919 +{
920 + int i = 0;
921 +
922 + for (;;) {
923 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
924 + if (!*p++ || i == 6)
925 + break;
926 + }
927 +
928 + return (i == 6);
929 +}
930 +
931 +/*
932 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
933 + * triples, returning a pointer to the substring whose first element
934 + * matches tag. Stop parsing when we see an element whose ID is greater
935 + * than the target key.
936 + */
937 +bcm_tlv_t *
938 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
939 +{
940 + bcm_tlv_t *elt;
941 + int totlen;
942 +
943 + elt = (bcm_tlv_t*)buf;
944 + totlen = buflen;
945 +
946 + /* find tagged parameter */
947 + while (totlen >= 2) {
948 + uint id = elt->id;
949 + int len = elt->len;
950 +
951 + /* Punt if we start seeing IDs > than target key */
952 + if (id > key)
953 + return(NULL);
954 +
955 + /* validate remaining totlen */
956 + if ((id == key) && (totlen >= (len + 2)))
957 + return (elt);
958 +
959 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
960 + totlen -= (len + 2);
961 + }
962 + return NULL;
963 +}
964 +
965 +
966 +/*
967 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
968 + * triples, returning a pointer to the substring whose first element
969 + * matches tag
970 + */
971 +bcm_tlv_t *
972 +bcm_parse_tlvs(void *buf, int buflen, uint key)
973 +{
974 + bcm_tlv_t *elt;
975 + int totlen;
976 +
977 + elt = (bcm_tlv_t*)buf;
978 + totlen = buflen;
979 +
980 + /* find tagged parameter */
981 + while (totlen >= 2) {
982 + int len = elt->len;
983 +
984 + /* validate remaining totlen */
985 + if ((elt->id == key) && (totlen >= (len + 2)))
986 + return (elt);
987 +
988 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
989 + totlen -= (len + 2);
990 + }
991 +
992 + return NULL;
993 +}
994 +
995 +void
996 +pktqinit(struct pktq *q, int maxlen)
997 +{
998 + q->head = q->tail = NULL;
999 + q->maxlen = maxlen;
1000 + q->len = 0;
1001 +}
1002 +
1003 +void
1004 +pktenq(struct pktq *q, void *p, bool lifo)
1005 +{
1006 + ASSERT(PKTLINK(p) == NULL);
1007 +
1008 + PKTSETLINK(p, NULL);
1009 +
1010 + if (q->tail == NULL) {
1011 + ASSERT(q->head == NULL);
1012 + q->head = q->tail = p;
1013 + }
1014 + else {
1015 + ASSERT(q->head);
1016 + ASSERT(PKTLINK(q->tail) == NULL);
1017 + if (lifo) {
1018 + PKTSETLINK(p, q->head);
1019 + q->head = p;
1020 + } else {
1021 + PKTSETLINK(q->tail, p);
1022 + q->tail = p;
1023 + }
1024 + }
1025 + q->len++;
1026 +}
1027 +
1028 +void*
1029 +pktdeq(struct pktq *q)
1030 +{
1031 + void *p;
1032 +
1033 + if ((p = q->head)) {
1034 + ASSERT(q->tail);
1035 + q->head = PKTLINK(p);
1036 + PKTSETLINK(p, NULL);
1037 + q->len--;
1038 + if (q->head == NULL)
1039 + q->tail = NULL;
1040 + }
1041 + else {
1042 + ASSERT(q->tail == NULL);
1043 + }
1044 +
1045 + return (p);
1046 +}
1047 +
1048 +/*******************************************************************************
1049 + * crc8
1050 + *
1051 + * Computes a crc8 over the input data using the polynomial:
1052 + *
1053 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1054 + *
1055 + * The caller provides the initial value (either CRC8_INIT_VALUE
1056 + * or the previous returned value) to allow for processing of
1057 + * discontiguous blocks of data. When generating the CRC the
1058 + * caller is responsible for complementing the final return value
1059 + * and inserting it into the byte stream. When checking, a final
1060 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1061 + *
1062 + * Reference: Dallas Semiconductor Application Note 27
1063 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1064 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1065 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1066 + *
1067 + ******************************************************************************/
1068 +
1069 +static uint8 crc8_table[256] = {
1070 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1071 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1072 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1073 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1074 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1075 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1076 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1077 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1078 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1079 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1080 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1081 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1082 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1083 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1084 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1085 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1086 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1087 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1088 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1089 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1090 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1091 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1092 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1093 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1094 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1095 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1096 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1097 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1098 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1099 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1100 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1101 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1102 +};
1103 +
1104 +/*
1105 + * Search the name=value vars for a specific one and return its value.
1106 + * Returns NULL if not found.
1107 + */
1108 +char*
1109 +getvar(char *vars, char *name)
1110 +{
1111 + char *s;
1112 + int len;
1113 +
1114 + len = strlen(name);
1115 +
1116 + /* first look in vars[] */
1117 + for (s = vars; s && *s; ) {
1118 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
1119 + return (&s[len+1]);
1120 +
1121 + while (*s++)
1122 + ;
1123 + }
1124 +
1125 + /* then query nvram */
1126 + return (nvram_get(name));
1127 +}
1128 +
1129 +/*
1130 + * Search the vars for a specific one and return its value as
1131 + * an integer. Returns 0 if not found.
1132 + */
1133 +int
1134 +getintvar(char *vars, char *name)
1135 +{
1136 + char *val;
1137 +
1138 + if ((val = getvar(vars, name)) == NULL)
1139 + return (0);
1140 +
1141 + return (bcm_strtoul(val, NULL, 0));
1142 +}
1143 +
1144 +void
1145 +bcm_mdelay(uint ms)
1146 +{
1147 + uint i;
1148 +
1149 + for (i = 0; i < ms; i++) {
1150 + OSL_DELAY(1000);
1151 + }
1152 +}
1153 +
1154 +#define CRC_INNER_LOOP(n, c, x) \
1155 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1156 +
1157 +uint8
1158 +crc8(
1159 + uint8 *pdata, /* pointer to array of data to process */
1160 + uint nbytes, /* number of input data bytes to process */
1161 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1162 +)
1163 +{
1164 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1165 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
1166 + while (nbytes-- > 0)
1167 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1168 +
1169 + return crc;
1170 +}
1171 +
1172 +/*******************************************************************************
1173 + * crc16
1174 + *
1175 + * Computes a crc16 over the input data using the polynomial:
1176 + *
1177 + * x^16 + x^12 +x^5 + 1
1178 + *
1179 + * The caller provides the initial value (either CRC16_INIT_VALUE
1180 + * or the previous returned value) to allow for processing of
1181 + * discontiguous blocks of data. When generating the CRC the
1182 + * caller is responsible for complementing the final return value
1183 + * and inserting it into the byte stream. When checking, a final
1184 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
1185 + *
1186 + * Reference: Dallas Semiconductor Application Note 27
1187 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1188 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1189 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1190 + *
1191 + ******************************************************************************/
1192 +
1193 +static uint16 crc16_table[256] = {
1194 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
1195 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
1196 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
1197 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
1198 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
1199 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
1200 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
1201 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
1202 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
1203 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
1204 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
1205 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
1206 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
1207 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
1208 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
1209 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
1210 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
1211 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
1212 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
1213 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
1214 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
1215 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
1216 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
1217 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
1218 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
1219 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
1220 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
1221 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
1222 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
1223 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
1224 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
1225 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
1226 +};
1227 +
1228 +uint16
1229 +crc16(
1230 + uint8 *pdata, /* pointer to array of data to process */
1231 + uint nbytes, /* number of input data bytes to process */
1232 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
1233 +)
1234 +{
1235 + while (nbytes-- > 0)
1236 + CRC_INNER_LOOP(16, crc, *pdata++);
1237 + return crc;
1238 +}
1239 +
1240 +static uint32 crc32_table[256] = {
1241 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
1242 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
1243 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
1244 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
1245 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
1246 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
1247 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
1248 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
1249 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
1250 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
1251 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
1252 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
1253 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
1254 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
1255 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
1256 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
1257 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
1258 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
1259 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
1260 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
1261 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
1262 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
1263 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
1264 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
1265 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
1266 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
1267 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
1268 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
1269 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
1270 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
1271 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
1272 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
1273 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
1274 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
1275 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
1276 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
1277 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
1278 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
1279 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
1280 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
1281 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
1282 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
1283 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
1284 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
1285 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
1286 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
1287 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
1288 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
1289 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
1290 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
1291 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
1292 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
1293 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
1294 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
1295 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
1296 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
1297 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
1298 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
1299 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
1300 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
1301 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
1302 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
1303 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
1304 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
1305 +};
1306 +
1307 +uint32
1308 +crc32(
1309 + uint8 *pdata, /* pointer to array of data to process */
1310 + uint nbytes, /* number of input data bytes to process */
1311 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
1312 +)
1313 +{
1314 + uint8 *pend;
1315 +#ifdef __mips__
1316 + uint8 tmp[4];
1317 + ulong *tptr = (ulong *)tmp;
1318 +
1319 + /* in case the beginning of the buffer isn't aligned */
1320 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
1321 + nbytes -= (pend - pdata);
1322 + while (pdata < pend)
1323 + CRC_INNER_LOOP(32, crc, *pdata++);
1324 +
1325 + /* handle bulk of data as 32-bit words */
1326 + pend = pdata + (nbytes & 0xfffffffc);
1327 + while (pdata < pend) {
1328 + *tptr = *((ulong *)pdata)++;
1329 + CRC_INNER_LOOP(32, crc, tmp[0]);
1330 + CRC_INNER_LOOP(32, crc, tmp[1]);
1331 + CRC_INNER_LOOP(32, crc, tmp[2]);
1332 + CRC_INNER_LOOP(32, crc, tmp[3]);
1333 + }
1334 +
1335 + /* 1-3 bytes at end of buffer */
1336 + pend = pdata + (nbytes & 0x03);
1337 + while (pdata < pend)
1338 + CRC_INNER_LOOP(32, crc, *pdata++);
1339 +#else
1340 + pend = pdata + nbytes;
1341 + while (pdata < pend)
1342 + CRC_INNER_LOOP(32, crc, *pdata++);
1343 +#endif
1344 +
1345 + return crc;
1346 +}
1347 +
1348 +#ifdef notdef
1349 +#define CLEN 1499
1350 +#define CBUFSIZ (CLEN+4)
1351 +#define CNBUFS 5
1352 +
1353 +void testcrc32(void)
1354 +{
1355 + uint j,k,l;
1356 + uint8 *buf;
1357 + uint len[CNBUFS];
1358 + uint32 crcr;
1359 + uint32 crc32tv[CNBUFS] =
1360 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
1361 +
1362 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
1363 +
1364 + /* step through all possible alignments */
1365 + for (l=0;l<=4;l++) {
1366 + for (j=0; j<CNBUFS; j++) {
1367 + len[j] = CLEN;
1368 + for (k=0; k<len[j]; k++)
1369 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
1370 + }
1371 +
1372 + for (j=0; j<CNBUFS; j++) {
1373 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
1374 + ASSERT(crcr == crc32tv[j]);
1375 + }
1376 + }
1377 +
1378 + MFREE(buf, CBUFSIZ*CNBUFS);
1379 + return;
1380 +}
1381 +#endif
1382 +
1383 +
1384 +
1385 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/hnddma.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/hnddma.c
1386 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/hnddma.c 1970-01-01 01:00:00.000000000 +0100
1387 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/hnddma.c 2005-12-13 14:59:52.000000000 +0100
1388 @@ -0,0 +1,763 @@
1389 +/*
1390 + * Generic Broadcom Home Networking Division (HND) DMA module.
1391 + * This supports the following chips: BCM42xx, 44xx, 47xx .
1392 + *
1393 + * Copyright 2001-2003, Broadcom Corporation
1394 + * All Rights Reserved.
1395 + *
1396 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1397 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1398 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1399 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1400 + *
1401 + * $Id: hnddma.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
1402 + */
1403 +
1404 +#include <typedefs.h>
1405 +#include <osl.h>
1406 +#include <bcmendian.h>
1407 +#include <bcmutils.h>
1408 +
1409 +struct dma_info; /* forward declaration */
1410 +#define di_t struct dma_info
1411 +#include <hnddma.h>
1412 +
1413 +/* debug/trace */
1414 +#define DMA_ERROR(args)
1415 +#define DMA_TRACE(args)
1416 +
1417 +/* default dma message level(if input msg_level pointer is null in dma_attach()) */
1418 +static uint dma_msg_level = 0;
1419 +
1420 +#define MAXNAMEL 8
1421 +#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
1422 +
1423 +/* dma engine software state */
1424 +typedef struct dma_info {
1425 + hnddma_t hnddma; /* exported structure */
1426 + uint *msg_level; /* message level pointer */
1427 +
1428 + char name[MAXNAMEL]; /* callers name for diag msgs */
1429 + void *drv; /* driver handle */
1430 + void *dev; /* device handle */
1431 + dmaregs_t *regs; /* dma engine registers */
1432 +
1433 + dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
1434 + uint txin; /* index of next descriptor to reclaim */
1435 + uint txout; /* index of next descriptor to post */
1436 + uint txavail; /* # free tx descriptors */
1437 + void *txp[MAXDD]; /* parallel array of pointers to packets */
1438 + ulong txdpa; /* physical address of descriptor ring */
1439 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
1440 +
1441 + dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
1442 + uint rxin; /* index of next descriptor to reclaim */
1443 + uint rxout; /* index of next descriptor to post */
1444 + void *rxp[MAXDD]; /* parallel array of pointers to packets */
1445 + ulong rxdpa; /* physical address of descriptor ring */
1446 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
1447 +
1448 + /* tunables */
1449 + uint ntxd; /* # tx descriptors */
1450 + uint nrxd; /* # rx descriptors */
1451 + uint rxbufsize; /* rx buffer size in bytes */
1452 + uint nrxpost; /* # rx buffers to keep posted */
1453 + uint rxoffset; /* rxcontrol offset */
1454 + uint ddoffset; /* add to get dma address of descriptor ring */
1455 + uint dataoffset; /* add to get dma address of data buffer */
1456 +} dma_info_t;
1457 +
1458 +/* descriptor bumping macros */
1459 +#define NEXTTXD(i) ((i + 1) & (di->ntxd - 1))
1460 +#define PREVTXD(i) ((i - 1) & (di->ntxd - 1))
1461 +#define NEXTRXD(i) ((i + 1) & (di->nrxd - 1))
1462 +#define NTXDACTIVE(h, t) ((t - h) & (di->ntxd - 1))
1463 +#define NRXDACTIVE(h, t) ((t - h) & (di->nrxd - 1))
1464 +
1465 +/* macros to convert between byte offsets and indexes */
1466 +#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
1467 +#define I2B(index) ((index) * sizeof (dmadd_t))
1468 +
1469 +void*
1470 +dma_attach(void *drv, void *dev, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
1471 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
1472 +{
1473 + dma_info_t *di;
1474 + void *va;
1475 +
1476 + ASSERT(ntxd <= MAXDD);
1477 + ASSERT(nrxd <= MAXDD);
1478 +
1479 + /* allocate private info structure */
1480 + if ((di = MALLOC(sizeof (dma_info_t))) == NULL)
1481 + return (NULL);
1482 + bzero((char*)di, sizeof (dma_info_t));
1483 +
1484 + /* set message level */
1485 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
1486 +
1487 + DMA_TRACE(("%s: dma_attach: drv 0x%x dev 0x%x regs 0x%x ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, (uint)drv, (uint)dev, (uint)regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
1488 +
1489 + /* make a private copy of our callers name */
1490 + strncpy(di->name, name, MAXNAMEL);
1491 + di->name[MAXNAMEL-1] = '\0';
1492 +
1493 + di->drv = drv;
1494 + di->dev = dev;
1495 + di->regs = regs;
1496 +
1497 + /* allocate transmit descriptor ring */
1498 + if (ntxd) {
1499 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->txdpa)) == NULL)
1500 + goto fail;
1501 + di->txd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1502 + di->txdalign = ((uint)di->txd - (uint)va);
1503 + di->txdpa = di->txdpa + di->txdalign;
1504 + ASSERT(ISALIGNED(di->txd, DMARINGALIGN));
1505 + }
1506 +
1507 + /* allocate receive descriptor ring */
1508 + if (nrxd) {
1509 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->rxdpa)) == NULL)
1510 + goto fail;
1511 + di->rxd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1512 + di->rxdalign = ((uint)di->rxd - (uint)va);
1513 + di->rxdpa = di->rxdpa + di->rxdalign;
1514 + ASSERT(ISALIGNED(di->rxd, DMARINGALIGN));
1515 + }
1516 +
1517 + /* save tunables */
1518 + di->ntxd = ntxd;
1519 + di->nrxd = nrxd;
1520 + di->rxbufsize = rxbufsize;
1521 + di->nrxpost = nrxpost;
1522 + di->rxoffset = rxoffset;
1523 + di->ddoffset = ddoffset;
1524 + di->dataoffset = dataoffset;
1525 +
1526 + return ((void*)di);
1527 +
1528 +fail:
1529 + dma_detach((void*)di);
1530 + return (NULL);
1531 +}
1532 +
1533 +/* may be called with core in reset */
1534 +void
1535 +dma_detach(dma_info_t *di)
1536 +{
1537 + if (di == NULL)
1538 + return;
1539 +
1540 + DMA_TRACE(("%s: dma_detach\n", di->name));
1541 +
1542 + /* shouldn't be here if descriptors are unreclaimed */
1543 + ASSERT(di->txin == di->txout);
1544 + ASSERT(di->rxin == di->rxout);
1545 +
1546 + /* free dma descriptor rings */
1547 + if (di->txd)
1548 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->txd - di->txdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->txdpa);
1549 + if (di->rxd)
1550 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->rxd - di->rxdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->rxdpa);
1551 +
1552 + /* free our private info structure */
1553 + MFREE((void*)di, sizeof (dma_info_t));
1554 +}
1555 +
1556 +
1557 +void
1558 +dma_txreset(dma_info_t *di)
1559 +{
1560 + uint32 status;
1561 +
1562 + DMA_TRACE(("%s: dma_txreset\n", di->name));
1563 +
1564 + /* suspend tx DMA first */
1565 + W_REG(&di->regs->xmtcontrol, XC_SE);
1566 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
1567 + status != XS_XS_IDLE &&
1568 + status != XS_XS_STOPPED,
1569 + 10000);
1570 +
1571 + W_REG(&di->regs->xmtcontrol, 0);
1572 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
1573 + 10000);
1574 +
1575 + if (status != XS_XS_DISABLED) {
1576 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
1577 + }
1578 +
1579 + /* wait for the last transaction to complete */
1580 + OSL_DELAY(300);
1581 +}
1582 +
1583 +void
1584 +dma_rxreset(dma_info_t *di)
1585 +{
1586 + uint32 status;
1587 +
1588 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
1589 +
1590 + W_REG(&di->regs->rcvcontrol, 0);
1591 + SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
1592 + 10000);
1593 +
1594 + if (status != RS_RS_DISABLED) {
1595 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
1596 + }
1597 +}
1598 +
1599 +void
1600 +dma_txinit(dma_info_t *di)
1601 +{
1602 + DMA_TRACE(("%s: dma_txinit\n", di->name));
1603 +
1604 + di->txin = di->txout = 0;
1605 + di->txavail = di->ntxd - 1;
1606 +
1607 + /* clear tx descriptor ring */
1608 + BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
1609 +
1610 + W_REG(&di->regs->xmtcontrol, XC_XE);
1611 + W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
1612 +}
1613 +
1614 +bool
1615 +dma_txenabled(dma_info_t *di)
1616 +{
1617 + uint32 xc;
1618 +
1619 + /* If the chip is dead, it is not enabled :-) */
1620 + xc = R_REG(&di->regs->xmtcontrol);
1621 + return ((xc != 0xffffffff) && (xc & XC_XE));
1622 +}
1623 +
1624 +void
1625 +dma_txsuspend(dma_info_t *di)
1626 +{
1627 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1628 + OR_REG(&di->regs->xmtcontrol, XC_SE);
1629 +}
1630 +
1631 +void
1632 +dma_txresume(dma_info_t *di)
1633 +{
1634 + DMA_TRACE(("%s: dma_txresume\n", di->name));
1635 + AND_REG(&di->regs->xmtcontrol, ~XC_SE);
1636 +}
1637 +
1638 +bool
1639 +dma_txsuspended(dma_info_t *di)
1640 +{
1641 + uint32 xc;
1642 + uint32 xs;
1643 +
1644 + xc = R_REG(&di->regs->xmtcontrol);
1645 + if (xc & XC_SE) {
1646 + xs = R_REG(&di->regs->xmtstatus);
1647 + return ((xs & XS_XS_MASK) == XS_XS_IDLE);
1648 + }
1649 + return 0;
1650 +}
1651 +
1652 +bool
1653 +dma_txstopped(dma_info_t *di)
1654 +{
1655 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
1656 +}
1657 +
1658 +bool
1659 +dma_rxstopped(dma_info_t *di)
1660 +{
1661 + return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
1662 +}
1663 +
1664 +void
1665 +dma_fifoloopbackenable(dma_info_t *di)
1666 +{
1667 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
1668 + OR_REG(&di->regs->xmtcontrol, XC_LE);
1669 +}
1670 +
1671 +void
1672 +dma_rxinit(dma_info_t *di)
1673 +{
1674 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
1675 +
1676 + di->rxin = di->rxout = 0;
1677 +
1678 + /* clear rx descriptor ring */
1679 + BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
1680 +
1681 + dma_rxenable(di);
1682 + W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
1683 +}
1684 +
1685 +void
1686 +dma_rxenable(dma_info_t *di)
1687 +{
1688 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
1689 + W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
1690 +}
1691 +
1692 +bool
1693 +dma_rxenabled(dma_info_t *di)
1694 +{
1695 + uint32 rc;
1696 +
1697 + rc = R_REG(&di->regs->rcvcontrol);
1698 + return ((rc != 0xffffffff) && (rc & RC_RE));
1699 +}
1700 +
1701 +/*
1702 + * The BCM47XX family supports full 32bit dma engine buffer addressing so
1703 + * dma buffers can cross 4 Kbyte page boundaries.
1704 + */
1705 +int
1706 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
1707 +{
1708 + void *p, *next;
1709 + uchar *data;
1710 + uint len;
1711 + uint txout;
1712 + uint32 ctrl;
1713 + uint32 pa;
1714 +
1715 + DMA_TRACE(("%s: dma_txfast\n", di->name));
1716 +
1717 + txout = di->txout;
1718 + ctrl = 0;
1719 +
1720 + /*
1721 + * Walk the chain of packet buffers
1722 + * allocating and initializing transmit descriptor entries.
1723 + */
1724 + for (p = p0; p; p = next) {
1725 + data = PKTDATA(di->drv, p);
1726 + len = PKTLEN(di->drv, p);
1727 + next = PKTNEXT(di->drv, p);
1728 +
1729 + /* return nonzero if out of tx descriptors */
1730 + if (NEXTTXD(txout) == di->txin)
1731 + goto outoftxd;
1732 +
1733 + if (len == 0)
1734 + continue;
1735 +
1736 + /* get physical address of buffer start */
1737 + pa = (uint32) DMA_MAP(di->dev, data, len, DMA_TX, p);
1738 +
1739 + /* build the descriptor control value */
1740 + ctrl = len & CTRL_BC_MASK;
1741 +
1742 + ctrl |= coreflags;
1743 +
1744 + if (p == p0)
1745 + ctrl |= CTRL_SOF;
1746 + if (next == NULL)
1747 + ctrl |= (CTRL_IOC | CTRL_EOF);
1748 + if (txout == (di->ntxd - 1))
1749 + ctrl |= CTRL_EOT;
1750 +
1751 + /* init the tx descriptor */
1752 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1753 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1754 +
1755 + ASSERT(di->txp[txout] == NULL);
1756 +
1757 + txout = NEXTTXD(txout);
1758 + }
1759 +
1760 + /* if last txd eof not set, fix it */
1761 + if (!(ctrl & CTRL_EOF))
1762 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1763 +
1764 + /* save the packet */
1765 + di->txp[PREVTXD(txout)] = p0;
1766 +
1767 + /* bump the tx descriptor index */
1768 + di->txout = txout;
1769 +
1770 + /* kick the chip */
1771 + W_REG(&di->regs->xmtptr, I2B(txout));
1772 +
1773 + /* tx flow control */
1774 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1775 +
1776 + return (0);
1777 +
1778 +outoftxd:
1779 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
1780 + PKTFREE(di->drv, p0, TRUE);
1781 + di->txavail = 0;
1782 + di->hnddma.txnobuf++;
1783 + return (-1);
1784 +}
1785 +
1786 +#define PAGESZ 4096
1787 +#define PAGEBASE(x) ((uint)(x) & ~4095)
1788 +
1789 +/*
1790 + * Just like above except go through the extra effort of splitting
1791 + * buffers that cross 4Kbyte boundaries into multiple tx descriptors.
1792 + */
1793 +int
1794 +dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
1795 +{
1796 + void *p, *next;
1797 + uchar *data;
1798 + uint plen, len;
1799 + uchar *page, *start, *end;
1800 + uint txout;
1801 + uint32 ctrl;
1802 + uint32 pa;
1803 +
1804 + DMA_TRACE(("%s: dma_tx\n", di->name));
1805 +
1806 + txout = di->txout;
1807 + ctrl = 0;
1808 +
1809 + /*
1810 + * Walk the chain of packet buffers
1811 + * splitting those that cross 4 Kbyte boundaries
1812 + * allocating and initializing transmit descriptor entries.
1813 + */
1814 + for (p = p0; p; p = next) {
1815 + data = PKTDATA(di->drv, p);
1816 + plen = PKTLEN(di->drv, p);
1817 + next = PKTNEXT(di->drv, p);
1818 +
1819 + if (plen == 0)
1820 + continue;
1821 +
1822 + for (page = (uchar*)PAGEBASE(data);
1823 + page <= (uchar*)PAGEBASE(data + plen - 1);
1824 + page += PAGESZ) {
1825 +
1826 + /* return nonzero if out of tx descriptors */
1827 + if (NEXTTXD(txout) == di->txin)
1828 + goto outoftxd;
1829 +
1830 + start = (page == (uchar*)PAGEBASE(data))? data: page;
1831 + end = (page == (uchar*)PAGEBASE(data + plen))?
1832 + (data + plen): (page + PAGESZ);
1833 + len = end - start;
1834 +
1835 + /* build the descriptor control value */
1836 + ctrl = len & CTRL_BC_MASK;
1837 +
1838 + ctrl |= coreflags;
1839 +
1840 + if ((p == p0) && (start == data))
1841 + ctrl |= CTRL_SOF;
1842 + if ((next == NULL) && (end == (data + plen)))
1843 + ctrl |= (CTRL_IOC | CTRL_EOF);
1844 + if (txout == (di->ntxd - 1))
1845 + ctrl |= CTRL_EOT;
1846 +
1847 + /* get physical address of buffer start */
1848 + pa = (uint32) DMA_MAP(di->dev, start, len, DMA_TX, p);
1849 +
1850 + /* init the tx descriptor */
1851 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1852 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1853 +
1854 + ASSERT(di->txp[txout] == NULL);
1855 +
1856 + txout = NEXTTXD(txout);
1857 + }
1858 + }
1859 +
1860 + /* if last txd eof not set, fix it */
1861 + if (!(ctrl & CTRL_EOF))
1862 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1863 +
1864 + /* save the packet */
1865 + di->txp[PREVTXD(txout)] = p0;
1866 +
1867 + /* bump the tx descriptor index */
1868 + di->txout = txout;
1869 +
1870 + /* kick the chip */
1871 + W_REG(&di->regs->xmtptr, I2B(txout));
1872 +
1873 + /* tx flow control */
1874 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1875 +
1876 + return (0);
1877 +
1878 +outoftxd:
1879 + DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
1880 + PKTFREE(di->drv, p0, TRUE);
1881 + di->txavail = 0;
1882 + di->hnddma.txnobuf++;
1883 + return (-1);
1884 +}
1885 +
1886 +/* returns a pointer to the next frame received, or NULL if there are no more */
1887 +void*
1888 +dma_rx(dma_info_t *di)
1889 +{
1890 + void *p;
1891 + uint len;
1892 + int skiplen = 0;
1893 +
1894 + while ((p = dma_getnextrxp(di, FALSE))) {
1895 + /* skip giant packets which span multiple rx descriptors */
1896 + if (skiplen > 0) {
1897 + skiplen -= di->rxbufsize;
1898 + if (skiplen < 0)
1899 + skiplen = 0;
1900 + PKTFREE(di->drv, p, FALSE);
1901 + continue;
1902 + }
1903 +
1904 + len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
1905 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
1906 +
1907 + /* bad frame length check */
1908 + if (len > (di->rxbufsize - di->rxoffset)) {
1909 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
1910 + if (len > 0)
1911 + skiplen = len - (di->rxbufsize - di->rxoffset);
1912 + PKTFREE(di->drv, p, FALSE);
1913 + di->hnddma.rxgiants++;
1914 + continue;
1915 + }
1916 +
1917 + /* set actual length */
1918 + PKTSETLEN(di->drv, p, (di->rxoffset + len));
1919 +
1920 + break;
1921 + }
1922 +
1923 + return (p);
1924 +}
1925 +
1926 +/* post receive buffers */
1927 +void
1928 +dma_rxfill(dma_info_t *di)
1929 +{
1930 + void *p;
1931 + uint rxin, rxout;
1932 + uint ctrl;
1933 + uint n;
1934 + uint i;
1935 + uint32 pa;
1936 + uint rxbufsize;
1937 +
1938 + /*
1939 + * Determine how many receive buffers we're lacking
1940 + * from the full complement, allocate, initialize,
1941 + * and post them, then update the chip rx lastdscr.
1942 + */
1943 +
1944 + rxin = di->rxin;
1945 + rxout = di->rxout;
1946 + rxbufsize = di->rxbufsize;
1947 +
1948 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
1949 +
1950 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
1951 +
1952 + for (i = 0; i < n; i++) {
1953 + if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
1954 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
1955 + di->hnddma.rxnobuf++;
1956 + break;
1957 + }
1958 +
1959 + *(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
1960 +
1961 + pa = (uint32) DMA_MAP(di->dev, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
1962 + ASSERT(ISALIGNED(pa, 4));
1963 +
1964 + /* save the free packet pointer */
1965 + ASSERT(di->rxp[rxout] == NULL);
1966 + di->rxp[rxout] = p;
1967 +
1968 + /* prep the descriptor control value */
1969 + ctrl = rxbufsize;
1970 + if (rxout == (di->nrxd - 1))
1971 + ctrl |= CTRL_EOT;
1972 +
1973 + /* init the rx descriptor */
1974 + W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
1975 + W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
1976 +
1977 + rxout = NEXTRXD(rxout);
1978 + }
1979 +
1980 + di->rxout = rxout;
1981 +
1982 + /* update the chip lastdscr pointer */
1983 + W_REG(&di->regs->rcvptr, I2B(rxout));
1984 +}
1985 +
1986 +void
1987 +dma_txreclaim(dma_info_t *di, bool forceall)
1988 +{
1989 + void *p;
1990 +
1991 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
1992 +
1993 + while ((p = dma_getnexttxp(di, forceall)))
1994 + PKTFREE(di->drv, p, TRUE);
1995 +}
1996 +
1997 +/*
1998 + * Reclaim next completed txd (txds if using chained buffers) and
1999 + * return associated packet.
2000 + * If 'force' is true, reclaim txd(s) and return associated packet
2001 + * regardless of the value of the hardware "curr" pointer.
2002 + */
2003 +void*
2004 +dma_getnexttxp(dma_info_t *di, bool forceall)
2005 +{
2006 + uint start, end, i;
2007 + void *txp;
2008 +
2009 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
2010 +
2011 + txp = NULL;
2012 +
2013 + start = di->txin;
2014 + if (forceall)
2015 + end = di->txout;
2016 + else
2017 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
2018 +
2019 + if ((start == 0) && (end > di->txout))
2020 + goto bogus;
2021 +
2022 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
2023 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
2024 + (BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
2025 + W_SM(&di->txd[i].addr, 0xdeadbeef);
2026 + txp = di->txp[i];
2027 + di->txp[i] = NULL;
2028 + }
2029 +
2030 + di->txin = i;
2031 +
2032 + /* tx flow control */
2033 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2034 +
2035 + return (txp);
2036 +
2037 +bogus:
2038 +/*
2039 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
2040 + start, end, di->txout, forceall));
2041 +*/
2042 + return (NULL);
2043 +}
2044 +
2045 +void
2046 +dma_rxreclaim(dma_info_t *di)
2047 +{
2048 + void *p;
2049 +
2050 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
2051 +
2052 + while ((p = dma_getnextrxp(di, TRUE)))
2053 + PKTFREE(di->drv, p, FALSE);
2054 +}
2055 +
2056 +void *
2057 +dma_getnextrxp(dma_info_t *di, bool forceall)
2058 +{
2059 + uint i;
2060 + void *rxp;
2061 +
2062 + /* if forcing, dma engine must be disabled */
2063 + ASSERT(!forceall || !dma_rxenabled(di));
2064 +
2065 + i = di->rxin;
2066 +
2067 + /* return if no packets posted */
2068 + if (i == di->rxout)
2069 + return (NULL);
2070 +
2071 + /* ignore curr if forceall */
2072 + if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
2073 + return (NULL);
2074 +
2075 + /* get the packet pointer that corresponds to the rx descriptor */
2076 + rxp = di->rxp[i];
2077 + ASSERT(rxp);
2078 + di->rxp[i] = NULL;
2079 +
2080 + /* clear this packet from the descriptor ring */
2081 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
2082 + di->rxbufsize, DMA_RX, rxp);
2083 + W_SM(&di->rxd[i].addr, 0xdeadbeef);
2084 +
2085 + di->rxin = NEXTRXD(i);
2086 +
2087 + return (rxp);
2088 +}
2089 +
2090 +char*
2091 +dma_dumptx(dma_info_t *di, char *buf)
2092 +{
2093 + buf += sprintf(buf, "txd 0x%lx txdpa 0x%lx txp 0x%lx txin %d txout %d txavail %d\n",
2094 + (ulong)di->txd, di->txdpa, (ulong)di->txp, di->txin, di->txout, di->txavail);
2095 + buf += sprintf(buf, "xmtcontrol 0x%x xmtaddr 0x%x xmtptr 0x%x xmtstatus 0x%x\n",
2096 + R_REG(&di->regs->xmtcontrol),
2097 + R_REG(&di->regs->xmtaddr),
2098 + R_REG(&di->regs->xmtptr),
2099 + R_REG(&di->regs->xmtstatus));
2100 + return (buf);
2101 +}
2102 +
2103 +char*
2104 +dma_dumprx(dma_info_t *di, char *buf)
2105 +{
2106 + buf += sprintf(buf, "rxd 0x%lx rxdpa 0x%lx rxp 0x%lx rxin %d rxout %d\n",
2107 + (ulong)di->rxd, di->rxdpa, (ulong)di->rxp, di->rxin, di->rxout);
2108 + buf += sprintf(buf, "rcvcontrol 0x%x rcvaddr 0x%x rcvptr 0x%x rcvstatus 0x%x\n",
2109 + R_REG(&di->regs->rcvcontrol),
2110 + R_REG(&di->regs->rcvaddr),
2111 + R_REG(&di->regs->rcvptr),
2112 + R_REG(&di->regs->rcvstatus));
2113 + return (buf);
2114 +}
2115 +
2116 +char*
2117 +dma_dump(dma_info_t *di, char *buf)
2118 +{
2119 + buf = dma_dumptx(di, buf);
2120 + buf = dma_dumprx(di, buf);
2121 + return (buf);
2122 +}
2123 +
2124 +uint
2125 +dma_getvar(dma_info_t *di, char *name)
2126 +{
2127 + if (!strcmp(name, "&txavail"))
2128 + return ((uint) &di->txavail);
2129 + else {
2130 + ASSERT(0);
2131 + }
2132 + return (0);
2133 +}
2134 +
2135 +void
2136 +dma_txblock(dma_info_t *di)
2137 +{
2138 + di->txavail = 0;
2139 +}
2140 +
2141 +void
2142 +dma_txunblock(dma_info_t *di)
2143 +{
2144 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2145 +}
2146 +
2147 +uint
2148 +dma_txactive(dma_info_t *di)
2149 +{
2150 + return (NTXDACTIVE(di->txin, di->txout));
2151 +}
2152 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/linux_osl.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/linux_osl.c
2153 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
2154 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-12-13 14:59:52.000000000 +0100
2155 @@ -0,0 +1,420 @@
2156 +/*
2157 + * Linux OS Independent Layer
2158 + *
2159 + * Copyright 2001-2003, Broadcom Corporation
2160 + * All Rights Reserved.
2161 + *
2162 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2163 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2164 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2165 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2166 + *
2167 + * $Id: linux_osl.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
2168 + */
2169 +
2170 +#define LINUX_OSL
2171 +
2172 +#include <typedefs.h>
2173 +#include <bcmendian.h>
2174 +#include <linuxver.h>
2175 +#include <linux_osl.h>
2176 +#include <bcmutils.h>
2177 +#include <linux/delay.h>
2178 +#ifdef mips
2179 +#include <asm/paccess.h>
2180 +#endif
2181 +#include <pcicfg.h>
2182 +
2183 +#define PCI_CFG_RETRY 10
2184 +
2185 +void*
2186 +osl_pktget(void *drv, uint len, bool send)
2187 +{
2188 + struct sk_buff *skb;
2189 +
2190 + if ((skb = dev_alloc_skb(len)) == NULL)
2191 + return (NULL);
2192 +
2193 + skb_put(skb, len);
2194 +
2195 + /* ensure the cookie field is cleared */
2196 + PKTSETCOOKIE(skb, NULL);
2197 +
2198 + return ((void*) skb);
2199 +}
2200 +
2201 +void
2202 +osl_pktfree(void *p)
2203 +{
2204 + struct sk_buff *skb, *nskb;
2205 +
2206 + skb = (struct sk_buff*) p;
2207 +
2208 + /* perversion: we use skb->next to chain multi-skb packets */
2209 + while (skb) {
2210 + nskb = skb->next;
2211 + skb->next = NULL;
2212 + if (skb->destructor) {
2213 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
2214 + dev_kfree_skb_any(skb);
2215 + } else {
2216 + /* can free immediately (even in_irq()) if destructor does not exist */
2217 + dev_kfree_skb(skb);
2218 + }
2219 + skb = nskb;
2220 + }
2221 +}
2222 +
2223 +uint32
2224 +osl_pci_read_config(void *loc, uint offset, uint size)
2225 +{
2226 + struct pci_dev *pdev;
2227 + uint val;
2228 + uint retry=PCI_CFG_RETRY;
2229 +
2230 + /* only 4byte access supported */
2231 + ASSERT(size == 4);
2232 +
2233 + pdev = (struct pci_dev*)loc;
2234 + do {
2235 + pci_read_config_dword(pdev, offset, &val);
2236 + if (val != 0xffffffff)
2237 + break;
2238 + } while (retry--);
2239 +
2240 +
2241 + return (val);
2242 +}
2243 +
2244 +void
2245 +osl_pci_write_config(void *loc, uint offset, uint size, uint val)
2246 +{
2247 + struct pci_dev *pdev;
2248 + uint retry=PCI_CFG_RETRY;
2249 +
2250 + /* only 4byte access supported */
2251 + ASSERT(size == 4);
2252 +
2253 + pdev = (struct pci_dev*)loc;
2254 +
2255 + do {
2256 + pci_write_config_dword(pdev, offset, val);
2257 + if (offset!=PCI_BAR0_WIN)
2258 + break;
2259 + if (osl_pci_read_config(loc,offset,size) == val)
2260 + break;
2261 + } while (retry--);
2262 +
2263 +}
2264 +
2265 +void
2266 +osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size)
2267 +{
2268 + ASSERT(0);
2269 +}
2270 +
2271 +void
2272 +osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size)
2273 +{
2274 + ASSERT(0);
2275 +}
2276 +
2277 +void
2278 +osl_assert(char *exp, char *file, int line)
2279 +{
2280 + char tempbuf[255];
2281 +
2282 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
2283 + panic(tempbuf);
2284 +}
2285 +
2286 +/*
2287 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2288 + */
2289 +#ifdef BINOSL
2290 +
2291 +int
2292 +osl_printf(const char *format, ...)
2293 +{
2294 + va_list args;
2295 + char buf[1024];
2296 + int len;
2297 +
2298 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
2299 + va_start(args, format);
2300 + len = vsprintf(buf, format, args);
2301 + va_end(args);
2302 +
2303 + if (len > sizeof (buf)) {
2304 + printk("osl_printf: buffer overrun\n");
2305 + return (0);
2306 + }
2307 +
2308 + return (printk(buf));
2309 +}
2310 +
2311 +int
2312 +osl_sprintf(char *buf, const char *format, ...)
2313 +{
2314 + va_list args;
2315 + int rc;
2316 +
2317 + va_start(args, format);
2318 + rc = vsprintf(buf, format, args);
2319 + va_end(args);
2320 + return (rc);
2321 +}
2322 +
2323 +int
2324 +osl_strcmp(const char *s1, const char *s2)
2325 +{
2326 + return (strcmp(s1, s2));
2327 +}
2328 +
2329 +int
2330 +osl_strncmp(const char *s1, const char *s2, uint n)
2331 +{
2332 + return (strncmp(s1, s2, n));
2333 +}
2334 +
2335 +int
2336 +osl_strlen(char *s)
2337 +{
2338 + return (strlen(s));
2339 +}
2340 +
2341 +char*
2342 +osl_strcpy(char *d, const char *s)
2343 +{
2344 + return (strcpy(d, s));
2345 +}
2346 +
2347 +char*
2348 +osl_strncpy(char *d, const char *s, uint n)
2349 +{
2350 + return (strncpy(d, s, n));
2351 +}
2352 +
2353 +void
2354 +bcopy(const void *src, void *dst, int len)
2355 +{
2356 + memcpy(dst, src, len);
2357 +}
2358 +
2359 +int
2360 +bcmp(const void *b1, const void *b2, int len)
2361 +{
2362 + return (memcmp(b1, b2, len));
2363 +}
2364 +
2365 +void
2366 +bzero(void *b, int len)
2367 +{
2368 + memset(b, '\0', len);
2369 +}
2370 +
2371 +void*
2372 +osl_malloc(uint size)
2373 +{
2374 + return (kmalloc(size, GFP_ATOMIC));
2375 +}
2376 +
2377 +void
2378 +osl_mfree(void *addr, uint size)
2379 +{
2380 + kfree(addr);
2381 +}
2382 +
2383 +uint32
2384 +osl_readl(volatile uint32 *r)
2385 +{
2386 + return (readl(r));
2387 +}
2388 +
2389 +uint16
2390 +osl_readw(volatile uint16 *r)
2391 +{
2392 + return (readw(r));
2393 +}
2394 +
2395 +uint8
2396 +osl_readb(volatile uint8 *r)
2397 +{
2398 + return (readb(r));
2399 +}
2400 +
2401 +void
2402 +osl_writel(uint32 v, volatile uint32 *r)
2403 +{
2404 + writel(v, r);
2405 +}
2406 +
2407 +void
2408 +osl_writew(uint16 v, volatile uint16 *r)
2409 +{
2410 + writew(v, r);
2411 +}
2412 +
2413 +void
2414 +osl_writeb(uint8 v, volatile uint8 *r)
2415 +{
2416 + writeb(v, r);
2417 +}
2418 +
2419 +void *
2420 +osl_uncached(void *va)
2421 +{
2422 +#ifdef mips
2423 + return ((void*)KSEG1ADDR(va));
2424 +#else
2425 + return ((void*)va);
2426 +#endif
2427 +}
2428 +
2429 +uint
2430 +osl_getcycles(void)
2431 +{
2432 + uint cycles;
2433 +
2434 +#if defined(mips)
2435 + cycles = read_c0_count() * 2;
2436 +#elif defined(__i386__)
2437 + rdtscl(cycles);
2438 +#else
2439 + cycles = 0;
2440 +#endif
2441 + return cycles;
2442 +}
2443 +
2444 +void *
2445 +osl_reg_map(uint32 pa, uint size)
2446 +{
2447 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
2448 +}
2449 +
2450 +void
2451 +osl_reg_unmap(void *va)
2452 +{
2453 + iounmap(va);
2454 +}
2455 +
2456 +int
2457 +osl_busprobe(uint32 *val, uint32 addr)
2458 +{
2459 +#ifdef mips
2460 + return get_dbe(*val, (uint32*)addr);
2461 +#else
2462 + *val = readl(addr);
2463 + return 0;
2464 +#endif
2465 +}
2466 +
2467 +void*
2468 +osl_dma_alloc_consistent(void *dev, uint size, ulong *pap)
2469 +{
2470 + return (pci_alloc_consistent((struct pci_dev*)dev, size, (dma_addr_t*)pap));
2471 +}
2472 +
2473 +void
2474 +osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa)
2475 +{
2476 + pci_free_consistent((struct pci_dev*)dev, size, va, (dma_addr_t)pa);
2477 +}
2478 +
2479 +uint
2480 +osl_dma_map(void *dev, void *va, uint size, int direction)
2481 +{
2482 + int dir;
2483 +
2484 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2485 + return (pci_map_single(dev, va, size, dir));
2486 +}
2487 +
2488 +void
2489 +osl_dma_unmap(void *dev, uint pa, uint size, int direction)
2490 +{
2491 + int dir;
2492 +
2493 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2494 + pci_unmap_single(dev, (uint32)pa, size, dir);
2495 +}
2496 +
2497 +void
2498 +osl_delay(uint usec)
2499 +{
2500 + udelay(usec);
2501 +}
2502 +
2503 +uchar*
2504 +osl_pktdata(void *drv, void *skb)
2505 +{
2506 + return (((struct sk_buff*)skb)->data);
2507 +}
2508 +
2509 +uint
2510 +osl_pktlen(void *drv, void *skb)
2511 +{
2512 + return (((struct sk_buff*)skb)->len);
2513 +}
2514 +
2515 +void*
2516 +osl_pktnext(void *drv, void *skb)
2517 +{
2518 + return (((struct sk_buff*)skb)->next);
2519 +}
2520 +
2521 +void
2522 +osl_pktsetnext(void *skb, void *x)
2523 +{
2524 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
2525 +}
2526 +
2527 +void
2528 +osl_pktsetlen(void *drv, void *skb, uint len)
2529 +{
2530 + __skb_trim((struct sk_buff*)skb, len);
2531 +}
2532 +
2533 +uchar*
2534 +osl_pktpush(void *drv, void *skb, int bytes)
2535 +{
2536 + return (skb_push((struct sk_buff*)skb, bytes));
2537 +}
2538 +
2539 +uchar*
2540 +osl_pktpull(void *drv, void *skb, int bytes)
2541 +{
2542 + return (skb_pull((struct sk_buff*)skb, bytes));
2543 +}
2544 +
2545 +void*
2546 +osl_pktdup(void *drv, void *skb)
2547 +{
2548 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
2549 +}
2550 +
2551 +void*
2552 +osl_pktcookie(void *skb)
2553 +{
2554 + return ((void*)((struct sk_buff*)skb)->csum);
2555 +}
2556 +
2557 +void
2558 +osl_pktsetcookie(void *skb, void *x)
2559 +{
2560 + ((struct sk_buff*)skb)->csum = (uint)x;
2561 +}
2562 +
2563 +void*
2564 +osl_pktlink(void *skb)
2565 +{
2566 + return (((struct sk_buff*)skb)->prev);
2567 +}
2568 +
2569 +void
2570 +osl_pktsetlink(void *skb, void *x)
2571 +{
2572 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
2573 +}
2574 +
2575 +#endif
2576 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/Makefile linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/Makefile
2577 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
2578 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/Makefile 2005-12-13 14:59:52.000000000 +0100
2579 @@ -0,0 +1,7 @@
2580 +#
2581 +# Makefile for the BCM47xx specific kernel interface routines
2582 +# under Linux.
2583 +#
2584 +
2585 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o hnddma.o
2586 +#obj-y := nvram.o nvram_linux.o
2587 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/nvram.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/nvram.c
2588 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
2589 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/nvram.c 2005-12-13 14:59:52.000000000 +0100
2590 @@ -0,0 +1,321 @@
2591 +/*
2592 + * NVRAM variable manipulation (common)
2593 + *
2594 + * Copyright 2004, Broadcom Corporation
2595 + * All Rights Reserved.
2596 + *
2597 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2598 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2599 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2600 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2601 + *
2602 + * $Id$
2603 + */
2604 +
2605 +#include <typedefs.h>
2606 +#include <osl.h>
2607 +#include <bcmendian.h>
2608 +#include <bcmnvram.h>
2609 +#include <bcmutils.h>
2610 +#include <sbsdram.h>
2611 +
2612 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
2613 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
2614 +extern int BCMINIT(_nvram_read)(void *buf);
2615 +
2616 +char * BCMINIT(_nvram_get)(const char *name);
2617 +int BCMINIT(_nvram_set)(const char *name, const char *value);
2618 +int BCMINIT(_nvram_unset)(const char *name);
2619 +int BCMINIT(_nvram_getall)(char *buf, int count);
2620 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
2621 +int BCMINIT(_nvram_init)(void);
2622 +void BCMINIT(_nvram_exit)(void);
2623 +
2624 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
2625 +static struct nvram_tuple * nvram_dead;
2626 +
2627 +/* Free all tuples. Should be locked. */
2628 +static void
2629 +BCMINITFN(nvram_free)(void)
2630 +{
2631 + uint i;
2632 + struct nvram_tuple *t, *next;
2633 +
2634 + /* Free hash table */
2635 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
2636 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
2637 + next = t->next;
2638 + BCMINIT(_nvram_free)(t);
2639 + }
2640 + BCMINIT(nvram_hash)[i] = NULL;
2641 + }
2642 +
2643 + /* Free dead table */
2644 + for (t = nvram_dead; t; t = next) {
2645 + next = t->next;
2646 + BCMINIT(_nvram_free)(t);
2647 + }
2648 + nvram_dead = NULL;
2649 +
2650 + /* Indicate to per-port code that all tuples have been freed */
2651 + BCMINIT(_nvram_free)(NULL);
2652 +}
2653 +
2654 +/* String hash */
2655 +static INLINE uint
2656 +hash(const char *s)
2657 +{
2658 + uint hash = 0;
2659 +
2660 + while (*s)
2661 + hash = 31 * hash + *s++;
2662 +
2663 + return hash;
2664 +}
2665 +
2666 +/* (Re)initialize the hash table. Should be locked. */
2667 +static int
2668 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
2669 +{
2670 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
2671 +
2672 + /* (Re)initialize hash table */
2673 + BCMINIT(nvram_free)();
2674 +
2675 + /* Parse and set "name=value\0 ... \0\0" */
2676 + name = (char *) &header[1];
2677 + end = (char *) header + NVRAM_SPACE - 2;
2678 + end[0] = end[1] = '\0';
2679 + for (; *name; name = value + strlen(value) + 1) {
2680 + if (!(eq = strchr(name, '=')))
2681 + break;
2682 + *eq = '\0';
2683 + value = eq + 1;
2684 + BCMINIT(_nvram_set)(name, value);
2685 + *eq = '=';
2686 + }
2687 +
2688 + /* Set special SDRAM parameters */
2689 + if (!BCMINIT(_nvram_get)("sdram_init")) {
2690 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
2691 + BCMINIT(_nvram_set)("sdram_init", buf);
2692 + }
2693 + if (!BCMINIT(_nvram_get)("sdram_config")) {
2694 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
2695 + BCMINIT(_nvram_set)("sdram_config", buf);
2696 + }
2697 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
2698 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
2699 + BCMINIT(_nvram_set)("sdram_refresh", buf);
2700 + }
2701 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
2702 + sprintf(buf, "0x%08X", header->config_ncdl);
2703 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
2704 + }
2705 +
2706 + return 0;
2707 +}
2708 +
2709 +/* Get the value of an NVRAM variable. Should be locked. */
2710 +char *
2711 +BCMINITFN(_nvram_get)(const char *name)
2712 +{
2713 + uint i;
2714 + struct nvram_tuple *t;
2715 + char *value;
2716 +
2717 + if (!name)
2718 + return NULL;
2719 +
2720 + /* Hash the name */
2721 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
2722 +
2723 + /* Find the associated tuple in the hash table */
2724 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
2725 +
2726 + value = t ? t->value : NULL;
2727 +
2728 + return value;
2729 +}
2730 +
2731 +/* Get the value of an NVRAM variable. Should be locked. */
2732 +int
2733 +BCMINITFN(_nvram_set)(const char *name, const char *value)
2734 +{
2735 + uint i;
2736 + struct nvram_tuple *t, *u, **prev;
2737 +
2738 + /* Hash the name */
2739 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
2740 +
2741 + /* Find the associated tuple in the hash table */
2742 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
2743 +
2744 + /* (Re)allocate tuple */
2745 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
2746 + return -12; /* -ENOMEM */
2747 +
2748 + /* Value reallocated */
2749 + if (t && t == u)
2750 + return 0;
2751 +
2752 + /* Move old tuple to the dead table */
2753 + if (t) {
2754 + *prev = t->next;
2755 + t->next = nvram_dead;
2756 + nvram_dead = t;
2757 + }
2758 +
2759 + /* Add new tuple to the hash table */
2760 + u->next = BCMINIT(nvram_hash)[i];
2761 + BCMINIT(nvram_hash)[i] = u;
2762 +
2763 + return 0;
2764 +}
2765 +
2766 +/* Unset the value of an NVRAM variable. Should be locked. */
2767 +int
2768 +BCMINITFN(_nvram_unset)(const char *name)
2769 +{
2770 + uint i;
2771 + struct nvram_tuple *t, **prev;
2772 +
2773 + if (!name)
2774 + return 0;
2775 +
2776 + /* Hash the name */
2777 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
2778 +
2779 + /* Find the associated tuple in the hash table */
2780 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
2781 +
2782 + /* Move it to the dead table */
2783 + if (t) {
2784 + *prev = t->next;
2785 + t->next = nvram_dead;
2786 + nvram_dead = t;
2787 + }
2788 +
2789 + return 0;
2790 +}
2791 +
2792 +/* Get all NVRAM variables. Should be locked. */
2793 +int
2794 +BCMINITFN(_nvram_getall)(char *buf, int count)
2795 +{
2796 + uint i;
2797 + struct nvram_tuple *t;
2798 + int len = 0;
2799 +
2800 + bzero(buf, count);
2801 +
2802 + /* Write name=value\0 ... \0\0 */
2803 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
2804 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
2805 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
2806 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
2807 + else
2808 + break;
2809 + }
2810 + }
2811 +
2812 + return 0;
2813 +}
2814 +
2815 +/* Regenerate NVRAM. Should be locked. */
2816 +int
2817 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
2818 +{
2819 + char *init, *config, *refresh, *ncdl;
2820 + char *ptr, *end;
2821 + int i;
2822 + struct nvram_tuple *t;
2823 + struct nvram_header tmp;
2824 + uint8 crc;
2825 +
2826 + /* Regenerate header */
2827 + header->magic = NVRAM_MAGIC;
2828 + header->crc_ver_init = (NVRAM_VERSION << 8);
2829 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
2830 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
2831 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
2832 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
2833 + header->crc_ver_init |= SDRAM_INIT << 16;
2834 + header->config_refresh = SDRAM_CONFIG;
2835 + header->config_refresh |= SDRAM_REFRESH << 16;
2836 + header->config_ncdl = 0;
2837 + } else {
2838 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
2839 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
2840 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
2841 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
2842 + }
2843 +
2844 + /* Clear data area */
2845 + ptr = (char *) header + sizeof(struct nvram_header);
2846 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
2847 +
2848 + /* Leave space for a double NUL at the end */
2849 + end = (char *) header + NVRAM_SPACE - 2;
2850 +
2851 + /* Write out all tuples */
2852 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
2853 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
2854 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
2855 + break;
2856 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
2857 + }
2858 + }
2859 +
2860 + /* End with a double NUL */
2861 + ptr += 2;
2862 +
2863 + /* Set new length */
2864 + header->len = ROUNDUP(ptr - (char *) header, 4);
2865 +
2866 + /* Little-endian CRC8 over the last 11 bytes of the header */
2867 + tmp.crc_ver_init = htol32(header->crc_ver_init);
2868 + tmp.config_refresh = htol32(header->config_refresh);
2869 + tmp.config_ncdl = htol32(header->config_ncdl);
2870 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
2871 +
2872 + /* Continue CRC8 over data bytes */
2873 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
2874 +
2875 + /* Set new CRC8 */
2876 + header->crc_ver_init |= crc;
2877 +
2878 + /* Reinitialize hash table */
2879 + return BCMINIT(nvram_rehash)(header);
2880 +}
2881 +
2882 +/* Initialize hash table. Should be locked. */
2883 +int
2884 +BCMINITFN(_nvram_init)(void)
2885 +{
2886 + struct nvram_header *header;
2887 + int ret;
2888 + void *osh;
2889 +
2890 + /* get kernel osl handler */
2891 + osh = osl_attach(NULL);
2892 +
2893 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
2894 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
2895 + return -12; /* -ENOMEM */
2896 + }
2897 +
2898 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
2899 + header->magic == NVRAM_MAGIC)
2900 + BCMINIT(nvram_rehash)(header);
2901 +
2902 + MFREE(osh, header, NVRAM_SPACE);
2903 + return ret;
2904 +}
2905 +
2906 +/* Free hash table. Should be locked. */
2907 +void
2908 +BCMINITFN(_nvram_exit)(void)
2909 +{
2910 + BCMINIT(nvram_free)();
2911 +}
2912 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/nvram_linux.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/nvram_linux.c
2913 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
2914 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/nvram_linux.c 2005-12-13 14:59:52.000000000 +0100
2915 @@ -0,0 +1,633 @@
2916 +/*
2917 + * NVRAM variable manipulation (Linux kernel half)
2918 + *
2919 + * Copyright 2005, Broadcom Corporation
2920 + * All Rights Reserved.
2921 + *
2922 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2923 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2924 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2925 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2926 + *
2927 + * $Id$
2928 + */
2929 +
2930 +#include <linux/config.h>
2931 +#include <linux/init.h>
2932 +#include <linux/module.h>
2933 +#include <linux/kernel.h>
2934 +#include <linux/string.h>
2935 +#include <linux/interrupt.h>
2936 +#include <linux/spinlock.h>
2937 +#include <linux/slab.h>
2938 +#include <linux/bootmem.h>
2939 +#include <linux/wrapper.h>
2940 +#include <linux/fs.h>
2941 +#include <linux/miscdevice.h>
2942 +#include <linux/mtd/mtd.h>
2943 +#include <asm/addrspace.h>
2944 +#include <asm/io.h>
2945 +#include <asm/uaccess.h>
2946 +
2947 +#include <typedefs.h>
2948 +#include <bcmendian.h>
2949 +#include <bcmnvram.h>
2950 +#include <bcmutils.h>
2951 +#include <sbconfig.h>
2952 +#include <sbchipc.h>
2953 +#include <sbutils.h>
2954 +#include <sbmips.h>
2955 +#include <sflash.h>
2956 +
2957 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
2958 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
2959 +
2960 +#ifdef MODULE
2961 +
2962 +#define early_nvram_get(name) nvram_get(name)
2963 +
2964 +#else /* !MODULE */
2965 +
2966 +/* Global SB handle */
2967 +extern void *bcm947xx_sbh;
2968 +extern spinlock_t bcm947xx_sbh_lock;
2969 +
2970 +/* Convenience */
2971 +#define sbh bcm947xx_sbh
2972 +#define sbh_lock bcm947xx_sbh_lock
2973 +#define KB * 1024
2974 +#define MB * 1024 * 1024
2975 +
2976 +/* Probe for NVRAM header */
2977 +static void __init
2978 +early_nvram_init(void)
2979 +{
2980 + struct nvram_header *header;
2981 + chipcregs_t *cc;
2982 + struct sflash *info = NULL;
2983 + int i;
2984 + uint32 base, off, lim;
2985 + u32 *src, *dst;
2986 +
2987 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
2988 + base = KSEG1ADDR(SB_FLASH2);
2989 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
2990 + case PFLASH:
2991 + lim = SB_FLASH2_SZ;
2992 + break;
2993 +
2994 + case SFLASH_ST:
2995 + case SFLASH_AT:
2996 + if ((info = sflash_init(cc)) == NULL)
2997 + return;
2998 + lim = info->size;
2999 + break;
3000 +
3001 + case FLASH_NONE:
3002 + default:
3003 + return;
3004 + }
3005 + } else {
3006 + /* extif assumed, Stop at 4 MB */
3007 + base = KSEG1ADDR(SB_FLASH1);
3008 + lim = SB_FLASH1_SZ;
3009 + }
3010 +
3011 + off = FLASH_MIN;
3012 + while (off <= lim) {
3013 + /* Windowed flash access */
3014 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
3015 + if (header->magic == NVRAM_MAGIC)
3016 + goto found;
3017 + off <<= 1;
3018 + }
3019 +
3020 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
3021 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
3022 + if (header->magic == NVRAM_MAGIC)
3023 + goto found;
3024 +
3025 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
3026 + if (header->magic == NVRAM_MAGIC)
3027 + goto found;
3028 +
3029 + printk("early_nvram_init: NVRAM not found\n");
3030 + return;
3031 +
3032 +found:
3033 + src = (u32 *) header;
3034 + dst = (u32 *) nvram_buf;
3035 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
3036 + *dst++ = *src++;
3037 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
3038 + *dst++ = ltoh32(*src++);
3039 +}
3040 +
3041 +/* Early (before mm or mtd) read-only access to NVRAM */
3042 +static char * __init
3043 +early_nvram_get(const char *name)
3044 +{
3045 + char *var, *value, *end, *eq;
3046 +
3047 + if (!name)
3048 + return NULL;
3049 +
3050 + /* Too early? */
3051 + if (sbh == NULL)
3052 + return NULL;
3053 +
3054 + if (!nvram_buf[0])
3055 + early_nvram_init();
3056 +
3057 + /* Look for name=value and return value */
3058 + var = &nvram_buf[sizeof(struct nvram_header)];
3059 + end = nvram_buf + sizeof(nvram_buf) - 2;
3060 + end[0] = end[1] = '\0';
3061 + for (; *var; var = value + strlen(value) + 1) {
3062 + if (!(eq = strchr(var, '=')))
3063 + break;
3064 + value = eq + 1;
3065 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
3066 + return value;
3067 + }
3068 +
3069 + return NULL;
3070 +}
3071 +
3072 +#endif /* !MODULE */
3073 +
3074 +extern char * _nvram_get(const char *name);
3075 +extern int _nvram_set(const char *name, const char *value);
3076 +extern int _nvram_unset(const char *name);
3077 +extern int _nvram_getall(char *buf, int count);
3078 +extern int _nvram_commit(struct nvram_header *header);
3079 +extern int _nvram_init(void);
3080 +extern void _nvram_exit(void);
3081 +
3082 +/* Globals */
3083 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
3084 +static struct semaphore nvram_sem;
3085 +static unsigned long nvram_offset = 0;
3086 +static int nvram_major = -1;
3087 +static devfs_handle_t nvram_handle = NULL;
3088 +static struct mtd_info *nvram_mtd = NULL;
3089 +
3090 +int
3091 +_nvram_read(char *buf)
3092 +{
3093 + struct nvram_header *header = (struct nvram_header *) buf;
3094 + size_t len;
3095 +
3096 + if (!nvram_mtd ||
3097 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
3098 + len != NVRAM_SPACE ||
3099 + header->magic != NVRAM_MAGIC) {
3100 + /* Maybe we can recover some data from early initialization */
3101 + memcpy(buf, nvram_buf, NVRAM_SPACE);
3102 + }
3103 +
3104 + return 0;
3105 +}
3106 +
3107 +struct nvram_tuple *
3108 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
3109 +{
3110 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
3111 + return NULL;
3112 +
3113 + if (!t) {
3114 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
3115 + return NULL;
3116 +
3117 + /* Copy name */
3118 + t->name = (char *) &t[1];
3119 + strcpy(t->name, name);
3120 +
3121 + t->value = NULL;
3122 + }
3123 +
3124 + /* Copy value */
3125 + if (!t->value || strcmp(t->value, value)) {
3126 + t->value = &nvram_buf[nvram_offset];
3127 + strcpy(t->value, value);
3128 + nvram_offset += strlen(value) + 1;
3129 + }
3130 +
3131 + return t;
3132 +}
3133 +
3134 +void
3135 +_nvram_free(struct nvram_tuple *t)
3136 +{
3137 + if (!t)
3138 + nvram_offset = 0;
3139 + else
3140 + kfree(t);
3141 +}
3142 +
3143 +int
3144 +nvram_set(const char *name, const char *value)
3145 +{
3146 + unsigned long flags;
3147 + int ret;
3148 + struct nvram_header *header;
3149 +
3150 + spin_lock_irqsave(&nvram_lock, flags);
3151 + if ((ret = _nvram_set(name, value))) {
3152 + /* Consolidate space and try again */
3153 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
3154 + if (_nvram_commit(header) == 0)
3155 + ret = _nvram_set(name, value);
3156 + kfree(header);
3157 + }
3158 + }
3159 + spin_unlock_irqrestore(&nvram_lock, flags);
3160 +
3161 + return ret;
3162 +}
3163 +
3164 +char *
3165 +real_nvram_get(const char *name)
3166 +{
3167 + unsigned long flags;
3168 + char *value;
3169 +
3170 + spin_lock_irqsave(&nvram_lock, flags);
3171 + value = _nvram_get(name);
3172 + spin_unlock_irqrestore(&nvram_lock, flags);
3173 +
3174 + return value;
3175 +}
3176 +
3177 +char *
3178 +nvram_get(const char *name)
3179 +{
3180 + if (nvram_major >= 0)
3181 + return real_nvram_get(name);
3182 + else
3183 + return early_nvram_get(name);
3184 +}
3185 +
3186 +int
3187 +nvram_unset(const char *name)
3188 +{
3189 + unsigned long flags;
3190 + int ret;
3191 +
3192 + spin_lock_irqsave(&nvram_lock, flags);
3193 + ret = _nvram_unset(name);
3194 + spin_unlock_irqrestore(&nvram_lock, flags);
3195 +
3196 + return ret;
3197 +}
3198 +
3199 +static void
3200 +erase_callback(struct erase_info *done)
3201 +{
3202 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
3203 + wake_up(wait_q);
3204 +}
3205 +
3206 +int
3207 +nvram_commit(void)
3208 +{
3209 + char *buf;
3210 + size_t erasesize, len;
3211 + unsigned int i;
3212 + int ret;
3213 + struct nvram_header *header;
3214 + unsigned long flags;
3215 + u_int32_t offset;
3216 + DECLARE_WAITQUEUE(wait, current);
3217 + wait_queue_head_t wait_q;
3218 + struct erase_info erase;
3219 +
3220 + if (!nvram_mtd) {
3221 + printk("nvram_commit: NVRAM not found\n");
3222 + return -ENODEV;
3223 + }
3224 +
3225 + if (in_interrupt()) {
3226 + printk("nvram_commit: not committing in interrupt\n");
3227 + return -EINVAL;
3228 + }
3229 +
3230 + /* Backup sector blocks to be erased */
3231 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
3232 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
3233 + printk("nvram_commit: out of memory\n");
3234 + return -ENOMEM;
3235 + }
3236 +
3237 + down(&nvram_sem);
3238 +
3239 + if ((i = erasesize - NVRAM_SPACE) > 0) {
3240 + offset = nvram_mtd->size - erasesize;
3241 + len = 0;
3242 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
3243 + if (ret || len != i) {
3244 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
3245 + ret = -EIO;
3246 + goto done;
3247 + }
3248 + header = (struct nvram_header *)(buf + i);
3249 + } else {
3250 + offset = nvram_mtd->size - NVRAM_SPACE;
3251 + header = (struct nvram_header *)buf;
3252 + }
3253 +
3254 + /* Regenerate NVRAM */
3255 + spin_lock_irqsave(&nvram_lock, flags);
3256 + ret = _nvram_commit(header);
3257 + spin_unlock_irqrestore(&nvram_lock, flags);
3258 + if (ret)
3259 + goto done;
3260 +
3261 + /* Erase sector blocks */
3262 + init_waitqueue_head(&wait_q);
3263 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
3264 + erase.mtd = nvram_mtd;
3265 + erase.addr = offset;
3266 + erase.len = nvram_mtd->erasesize;
3267 + erase.callback = erase_callback;
3268 + erase.priv = (u_long) &wait_q;
3269 +
3270 + set_current_state(TASK_INTERRUPTIBLE);
3271 + add_wait_queue(&wait_q, &wait);
3272 +
3273 + /* Unlock sector blocks */
3274 + if (nvram_mtd->unlock)
3275 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
3276 +
3277 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
3278 + set_current_state(TASK_RUNNING);
3279 + remove_wait_queue(&wait_q, &wait);
3280 + printk("nvram_commit: erase error\n");
3281 + goto done;
3282 + }
3283 +
3284 + /* Wait for erase to finish */
3285 + schedule();
3286 + remove_wait_queue(&wait_q, &wait);
3287 + }
3288 +
3289 + /* Write partition up to end of data area */
3290 + offset = nvram_mtd->size - erasesize;
3291 + i = erasesize - NVRAM_SPACE + header->len;
3292 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
3293 + if (ret || len != i) {
3294 + printk("nvram_commit: write error\n");
3295 + ret = -EIO;
3296 + goto done;
3297 + }
3298 +
3299 + offset = nvram_mtd->size - erasesize;
3300 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
3301 +
3302 + done:
3303 + up(&nvram_sem);
3304 + kfree(buf);
3305 + return ret;
3306 +}
3307 +
3308 +int
3309 +nvram_getall(char *buf, int count)
3310 +{
3311 + unsigned long flags;
3312 + int ret;
3313 +
3314 + spin_lock_irqsave(&nvram_lock, flags);
3315 + ret = _nvram_getall(buf, count);
3316 + spin_unlock_irqrestore(&nvram_lock, flags);
3317 +
3318 + return ret;
3319 +}
3320 +
3321 +EXPORT_SYMBOL(nvram_get);
3322 +EXPORT_SYMBOL(nvram_getall);
3323 +EXPORT_SYMBOL(nvram_set);
3324 +EXPORT_SYMBOL(nvram_unset);
3325 +EXPORT_SYMBOL(nvram_commit);
3326 +
3327 +/* User mode interface below */
3328 +
3329 +static ssize_t
3330 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
3331 +{
3332 + char tmp[100], *name = tmp, *value;
3333 + ssize_t ret;
3334 + unsigned long off;
3335 +
3336 + if (count > sizeof(tmp)) {
3337 + if (!(name = kmalloc(count, GFP_KERNEL)))
3338 + return -ENOMEM;
3339 + }
3340 +
3341 + if (copy_from_user(name, buf, count)) {
3342 + ret = -EFAULT;
3343 + goto done;
3344 + }
3345 +
3346 + if (*name == '\0') {
3347 + /* Get all variables */
3348 + ret = nvram_getall(name, count);
3349 + if (ret == 0) {
3350 + if (copy_to_user(buf, name, count)) {
3351 + ret = -EFAULT;
3352 + goto done;
3353 + }
3354 + ret = count;
3355 + }
3356 + } else {
3357 + if (!(value = nvram_get(name))) {
3358 + ret = 0;
3359 + goto done;
3360 + }
3361 +
3362 + /* Provide the offset into mmap() space */
3363 + off = (unsigned long) value - (unsigned long) nvram_buf;
3364 +
3365 + if (put_user(off, (unsigned long *) buf)) {
3366 + ret = -EFAULT;
3367 + goto done;
3368 + }
3369 +
3370 + ret = sizeof(unsigned long);
3371 + }
3372 +
3373 + flush_cache_all();
3374 +
3375 +done:
3376 + if (name != tmp)
3377 + kfree(name);
3378 +
3379 + return ret;
3380 +}
3381 +
3382 +static ssize_t
3383 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
3384 +{
3385 + char tmp[100], *name = tmp, *value;
3386 + ssize_t ret;
3387 +
3388 + if (count > sizeof(tmp)) {
3389 + if (!(name = kmalloc(count, GFP_KERNEL)))
3390 + return -ENOMEM;
3391 + }
3392 +
3393 + if (copy_from_user(name, buf, count)) {
3394 + ret = -EFAULT;
3395 + goto done;
3396 + }
3397 +
3398 + value = name;
3399 + name = strsep(&value, "=");
3400 + if (value)
3401 + ret = nvram_set(name, value) ? : count;
3402 + else
3403 + ret = nvram_unset(name) ? : count;
3404 +
3405 + done:
3406 + if (name != tmp)
3407 + kfree(name);
3408 +
3409 + return ret;
3410 +}
3411 +
3412 +static int
3413 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
3414 +{
3415 + if (cmd != NVRAM_MAGIC)
3416 + return -EINVAL;
3417 + return nvram_commit();
3418 +}
3419 +
3420 +static int
3421 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
3422 +{
3423 + unsigned long offset = virt_to_phys(nvram_buf);
3424 +
3425 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
3426 + vma->vm_page_prot))
3427 + return -EAGAIN;
3428 +
3429 + return 0;
3430 +}
3431 +
3432 +static int
3433 +dev_nvram_open(struct inode *inode, struct file * file)
3434 +{
3435 + MOD_INC_USE_COUNT;
3436 + return 0;
3437 +}
3438 +
3439 +static int
3440 +dev_nvram_release(struct inode *inode, struct file * file)
3441 +{
3442 + MOD_DEC_USE_COUNT;
3443 + return 0;
3444 +}
3445 +
3446 +static struct file_operations dev_nvram_fops = {
3447 + owner: THIS_MODULE,
3448 + open: dev_nvram_open,
3449 + release: dev_nvram_release,
3450 + read: dev_nvram_read,
3451 + write: dev_nvram_write,
3452 + ioctl: dev_nvram_ioctl,
3453 + mmap: dev_nvram_mmap,
3454 +};
3455 +
3456 +static void
3457 +dev_nvram_exit(void)
3458 +{
3459 + int order = 0;
3460 + struct page *page, *end;
3461 +
3462 + if (nvram_handle)
3463 + devfs_unregister(nvram_handle);
3464 +
3465 + if (nvram_major >= 0)
3466 + devfs_unregister_chrdev(nvram_major, "nvram");
3467 +
3468 + if (nvram_mtd)
3469 + put_mtd_device(nvram_mtd);
3470 +
3471 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
3472 + order++;
3473 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
3474 + for (page = virt_to_page(nvram_buf); page <= end; page++)
3475 + mem_map_unreserve(page);
3476 +
3477 + _nvram_exit();
3478 +}
3479 +
3480 +static int __init
3481 +dev_nvram_init(void)
3482 +{
3483 + int order = 0, ret = 0;
3484 + struct page *page, *end;
3485 + unsigned int i;
3486 +
3487 + /* Allocate and reserve memory to mmap() */
3488 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
3489 + order++;
3490 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
3491 + for (page = virt_to_page(nvram_buf); page <= end; page++)
3492 + mem_map_reserve(page);
3493 +
3494 +#ifdef CONFIG_MTD
3495 + /* Find associated MTD device */
3496 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
3497 + nvram_mtd = get_mtd_device(NULL, i);
3498 + if (nvram_mtd) {
3499 + if (!strcmp(nvram_mtd->name, "nvram") &&
3500 + nvram_mtd->size >= NVRAM_SPACE)
3501 + break;
3502 + put_mtd_device(nvram_mtd);
3503 + }
3504 + }
3505 + if (i >= MAX_MTD_DEVICES)
3506 + nvram_mtd = NULL;
3507 +#endif
3508 +
3509 + /* Initialize hash table lock */
3510 + spin_lock_init(&nvram_lock);
3511 +
3512 + /* Initialize commit semaphore */
3513 + init_MUTEX(&nvram_sem);
3514 +
3515 + /* Register char device */
3516 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
3517 + ret = nvram_major;
3518 + goto err;
3519 + }
3520 +
3521 + /* Initialize hash table */
3522 + _nvram_init();
3523 +
3524 + /* Create /dev/nvram handle */
3525 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
3526 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
3527 +
3528 + /* Set the SDRAM NCDL value into NVRAM if not already done */
3529 + if (getintvar(NULL, "sdram_ncdl") == 0) {
3530 + unsigned int ncdl;
3531 + char buf[] = "0x00000000";
3532 +
3533 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
3534 + sprintf(buf, "0x%08x", ncdl);
3535 + nvram_set("sdram_ncdl", buf);
3536 + nvram_commit();
3537 + }
3538 + }
3539 +
3540 + return 0;
3541 +
3542 + err:
3543 + dev_nvram_exit();
3544 + return ret;
3545 +}
3546 +
3547 +module_init(dev_nvram_init);
3548 +module_exit(dev_nvram_exit);
3549 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbmips.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbmips.c
3550 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
3551 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbmips.c 2005-12-13 14:59:52.000000000 +0100
3552 @@ -0,0 +1,950 @@
3553 +/*
3554 + * BCM47XX Sonics SiliconBackplane MIPS core routines
3555 + *
3556 + * Copyright 2001-2003, Broadcom Corporation
3557 + * All Rights Reserved.
3558 + *
3559 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3560 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3561 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3562 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3563 + *
3564 + * $Id: sbmips.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
3565 + */
3566 +
3567 +#include <typedefs.h>
3568 +#include <osl.h>
3569 +#include <sbutils.h>
3570 +#include <bcmdevs.h>
3571 +#include <bcmnvram.h>
3572 +#include <bcmutils.h>
3573 +#include <hndmips.h>
3574 +#include <sbconfig.h>
3575 +#include <sbextif.h>
3576 +#include <sbchipc.h>
3577 +#include <sbmemc.h>
3578 +
3579 +/*
3580 + * Memory segments (32bit kernel mode addresses)
3581 + */
3582 +#undef KUSEG
3583 +#undef KSEG0
3584 +#undef KSEG1
3585 +#undef KSEG2
3586 +#undef KSEG3
3587 +#define KUSEG 0x00000000
3588 +#define KSEG0 0x80000000
3589 +#define KSEG1 0xa0000000
3590 +#define KSEG2 0xc0000000
3591 +#define KSEG3 0xe0000000
3592 +
3593 +/*
3594 + * Map an address to a certain kernel segment
3595 + */
3596 +#undef KSEG0ADDR
3597 +#undef KSEG1ADDR
3598 +#undef KSEG2ADDR
3599 +#undef KSEG3ADDR
3600 +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
3601 +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
3602 +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
3603 +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
3604 +
3605 +/*
3606 + * The following macros are especially useful for __asm__
3607 + * inline assembler.
3608 + */
3609 +#ifndef __STR
3610 +#define __STR(x) #x
3611 +#endif
3612 +#ifndef STR
3613 +#define STR(x) __STR(x)
3614 +#endif
3615 +
3616 +/* *********************************************************************
3617 + * CP0 Registers
3618 + ********************************************************************* */
3619 +
3620 +#define C0_INX 0 /* CP0: TLB Index */
3621 +#define C0_RAND 1 /* CP0: TLB Random */
3622 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3623 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3624 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3625 +#define C0_CTEXT 4 /* CP0: Context */
3626 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3627 +#define C0_WIRED 6 /* CP0: TLB Wired */
3628 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3629 +#define C0_COUNT 9 /* CP0: Count */
3630 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3631 +#define C0_COMPARE 11 /* CP0: Compare */
3632 +#define C0_SR 12 /* CP0: Processor Status */
3633 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3634 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3635 +#define C0_EPC 14 /* CP0: Exception PC */
3636 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3637 +#define C0_CONFIG 16 /* CP0: Config */
3638 +#define C0_LLADDR 17 /* CP0: LLAddr */
3639 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3640 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3641 +#define C0_XCTEXT 20 /* CP0: XContext */
3642 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3643 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3644 +#define C0_ECC 26 /* CP0: ECC */
3645 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3646 +#define C0_TAGLO 28 /* CP0: TagLo */
3647 +#define C0_TAGHI 29 /* CP0: TagHi */
3648 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3649 +
3650 +/*
3651 + * Macros to access the system control coprocessor
3652 + */
3653 +
3654 +#define MFC0(source, sel) \
3655 +({ \
3656 + int __res; \
3657 + __asm__ __volatile__( \
3658 + ".set\tnoreorder\n\t" \
3659 + ".set\tnoat\n\t" \
3660 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
3661 + "move\t%0,$1\n\t" \
3662 + ".set\tat\n\t" \
3663 + ".set\treorder" \
3664 + :"=r" (__res) \
3665 + : \
3666 + :"$1"); \
3667 + __res; \
3668 +})
3669 +
3670 +#define MTC0(source, sel, value) \
3671 +do { \
3672 + __asm__ __volatile__( \
3673 + ".set\tnoreorder\n\t" \
3674 + ".set\tnoat\n\t" \
3675 + "move\t$1,%z0\n\t" \
3676 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
3677 + ".set\tat\n\t" \
3678 + ".set\treorder" \
3679 + : \
3680 + :"Jr" (value) \
3681 + :"$1"); \
3682 +} while (0)
3683 +
3684 +/*
3685 + * R4x00 interrupt enable / cause bits
3686 + */
3687 +#undef IE_SW0
3688 +#undef IE_SW1
3689 +#undef IE_IRQ0
3690 +#undef IE_IRQ1
3691 +#undef IE_IRQ2
3692 +#undef IE_IRQ3
3693 +#undef IE_IRQ4
3694 +#undef IE_IRQ5
3695 +#define IE_SW0 (1<< 8)
3696 +#define IE_SW1 (1<< 9)
3697 +#define IE_IRQ0 (1<<10)
3698 +#define IE_IRQ1 (1<<11)
3699 +#define IE_IRQ2 (1<<12)
3700 +#define IE_IRQ3 (1<<13)
3701 +#define IE_IRQ4 (1<<14)
3702 +#define IE_IRQ5 (1<<15)
3703 +
3704 +/*
3705 + * Bitfields in the R4xx0 cp0 status register
3706 + */
3707 +#define ST0_IE 0x00000001
3708 +#define ST0_EXL 0x00000002
3709 +#define ST0_ERL 0x00000004
3710 +#define ST0_KSU 0x00000018
3711 +# define KSU_USER 0x00000010
3712 +# define KSU_SUPERVISOR 0x00000008
3713 +# define KSU_KERNEL 0x00000000
3714 +#define ST0_UX 0x00000020
3715 +#define ST0_SX 0x00000040
3716 +#define ST0_KX 0x00000080
3717 +#define ST0_DE 0x00010000
3718 +#define ST0_CE 0x00020000
3719 +
3720 +/*
3721 + * Status register bits available in all MIPS CPUs.
3722 + */
3723 +#define ST0_IM 0x0000ff00
3724 +#define ST0_CH 0x00040000
3725 +#define ST0_SR 0x00100000
3726 +#define ST0_TS 0x00200000
3727 +#define ST0_BEV 0x00400000
3728 +#define ST0_RE 0x02000000
3729 +#define ST0_FR 0x04000000
3730 +#define ST0_CU 0xf0000000
3731 +#define ST0_CU0 0x10000000
3732 +#define ST0_CU1 0x20000000
3733 +#define ST0_CU2 0x40000000
3734 +#define ST0_CU3 0x80000000
3735 +#define ST0_XX 0x80000000 /* MIPS IV naming */
3736 +
3737 +/*
3738 + * Cache Operations
3739 + */
3740 +
3741 +#ifndef Fill_I
3742 +#define Fill_I 0x14
3743 +#endif
3744 +
3745 +#define cache_unroll(base,op) \
3746 + __asm__ __volatile__(" \
3747 + .set noreorder; \
3748 + .set mips3; \
3749 + cache %1, (%0); \
3750 + .set mips0; \
3751 + .set reorder" \
3752 + : \
3753 + : "r" (base), \
3754 + "i" (op));
3755 +
3756 +/*
3757 + * These are the UART port assignments, expressed as offsets from the base
3758 + * register. These assignments should hold for any serial port based on
3759 + * a 8250, 16450, or 16550(A).
3760 + */
3761 +
3762 +#define UART_MCR 4 /* Out: Modem Control Register */
3763 +#define UART_MSR 6 /* In: Modem Status Register */
3764 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
3765 +
3766 +/*
3767 + * Returns TRUE if an external UART exists at the given base
3768 + * register.
3769 + */
3770 +static bool
3771 +serial_exists(uint8 *regs)
3772 +{
3773 + uint8 save_mcr, status1;
3774 +
3775 + save_mcr = R_REG(&regs[UART_MCR]);
3776 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
3777 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
3778 + W_REG(&regs[UART_MCR], save_mcr);
3779 +
3780 + return (status1 == 0x90);
3781 +}
3782 +
3783 +/*
3784 + * Initializes UART access. The callback function will be called once
3785 + * per found UART.
3786 +*/
3787 +void
3788 +sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
3789 +{
3790 + void *regs;
3791 + ulong base;
3792 + uint irq;
3793 + int i, n;
3794 +
3795 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
3796 + extifregs_t *eir = (extifregs_t *) regs;
3797 + sbconfig_t *sb;
3798 +
3799 + /* Determine external UART register base */
3800 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
3801 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
3802 +
3803 + /* Determine IRQ */
3804 + irq = sb_irq(sbh);
3805 +
3806 + /* Disable GPIO interrupt initially */
3807 + W_REG(&eir->gpiointpolarity, 0);
3808 + W_REG(&eir->gpiointmask, 0);
3809 +
3810 + /* Search for external UARTs */
3811 + n = 2;
3812 + for (i = 0; i < 2; i++) {
3813 + regs = (void *) REG_MAP(base + (i * 8), 8);
3814 + if (serial_exists(regs)) {
3815 + /* Set GPIO 1 to be the external UART IRQ */
3816 + W_REG(&eir->gpiointmask, 2);
3817 + if (add)
3818 + add(regs, irq, 13500000, 0);
3819 + }
3820 + }
3821 +
3822 + /* Add internal UART if enabled */
3823 + if (R_REG(&eir->corecontrol) & CC_UE)
3824 + if (add)
3825 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
3826 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
3827 + chipcregs_t *cc = (chipcregs_t *) regs;
3828 + uint32 rev, cap, pll, baud_base, div;
3829 +
3830 + /* Determine core revision and capabilities */
3831 + rev = sb_corerev(sbh);
3832 + cap = R_REG(&cc->capabilities);
3833 + pll = cap & CAP_PLL_MASK;
3834 +
3835 + /* Determine IRQ */
3836 + irq = sb_irq(sbh);
3837 +
3838 + if (pll == PLL_TYPE1) {
3839 + /* PLL clock */
3840 + baud_base = sb_clock_rate(pll,
3841 + R_REG(&cc->clockcontrol_n),
3842 + R_REG(&cc->clockcontrol_m2));
3843 + div = 1;
3844 + } else if (rev >= 3) {
3845 + /* Internal backplane clock */
3846 + baud_base = sb_clock_rate(pll,
3847 + R_REG(&cc->clockcontrol_n),
3848 + R_REG(&cc->clockcontrol_sb));
3849 + div = 2; /* Minimum divisor */
3850 + W_REG(&cc->uart_clkdiv, div);
3851 + } else {
3852 + /* Fixed internal backplane clock */
3853 + baud_base = 88000000;
3854 + div = 48;
3855 + }
3856 +
3857 + /* Clock source depends on strapping if UartClkOverride is unset */
3858 + if ((rev > 0) && ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
3859 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
3860 + /* Internal divided backplane clock */
3861 + baud_base /= div;
3862 + } else {
3863 + /* Assume external clock of 1.8432 MHz */
3864 + baud_base = 1843200;
3865 + }
3866 + }
3867 +
3868 + /* Add internal UARTs */
3869 + n = cap & CAP_UARTS_MASK;
3870 + for (i = 0; i < n; i++) {
3871 + /* Register offset changed after revision 0 */
3872 + if (rev)
3873 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
3874 + else
3875 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
3876 +
3877 + if (add)
3878 + add(regs, irq, baud_base, 0);
3879 + }
3880 + }
3881 +}
3882 +
3883 +/* Returns the SB interrupt flag of the current core. */
3884 +uint32
3885 +sb_flag(void *sbh)
3886 +{
3887 + void *regs;
3888 + sbconfig_t *sb;
3889 +
3890 + regs = sb_coreregs(sbh);
3891 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3892 +
3893 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
3894 +}
3895 +
3896 +static const uint32 sbips_int_mask[] = {
3897 + 0,
3898 + SBIPS_INT1_MASK,
3899 + SBIPS_INT2_MASK,
3900 + SBIPS_INT3_MASK,
3901 + SBIPS_INT4_MASK
3902 +};
3903 +
3904 +static const uint32 sbips_int_shift[] = {
3905 + 0,
3906 + 0,
3907 + SBIPS_INT2_SHIFT,
3908 + SBIPS_INT3_SHIFT,
3909 + SBIPS_INT4_SHIFT
3910 +};
3911 +
3912 +/*
3913 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
3914 + * 0 is returned.
3915 + */
3916 +uint
3917 +sb_irq(void *sbh)
3918 +{
3919 + uint idx;
3920 + void *regs;
3921 + sbconfig_t *sb;
3922 + uint32 flag, sbipsflag;
3923 + uint irq = 0;
3924 +
3925 + flag = sb_flag(sbh);
3926 +
3927 + idx = sb_coreidx(sbh);
3928 +
3929 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3930 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3931 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3932 +
3933 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
3934 + sbipsflag = R_REG(&sb->sbipsflag);
3935 + for (irq = 1; irq <= 4; irq++) {
3936 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
3937 + break;
3938 + }
3939 + if (irq == 5)
3940 + irq = 0;
3941 + }
3942 +
3943 + sb_setcoreidx(sbh, idx);
3944 +
3945 + return irq;
3946 +}
3947 +
3948 +/* Clears the specified MIPS IRQ. */
3949 +static void
3950 +sb_clearirq(void *sbh, uint irq)
3951 +{
3952 + void *regs;
3953 + sbconfig_t *sb;
3954 +
3955 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3956 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3957 + ASSERT(regs);
3958 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3959 +
3960 + if (irq == 0)
3961 + W_REG(&sb->sbintvec, 0);
3962 + else
3963 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
3964 +}
3965 +
3966 +/*
3967 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
3968 + * IRQ 0 may be assigned more than once.
3969 + */
3970 +static void
3971 +sb_setirq(void *sbh, uint irq, uint coreid, uint coreunit)
3972 +{
3973 + void *regs;
3974 + sbconfig_t *sb;
3975 + uint32 flag;
3976 +
3977 + regs = sb_setcore(sbh, coreid, coreunit);
3978 + ASSERT(regs);
3979 + flag = sb_flag(sbh);
3980 +
3981 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3982 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3983 + ASSERT(regs);
3984 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3985 +
3986 + if (irq == 0)
3987 + OR_REG(&sb->sbintvec, 1 << flag);
3988 + else {
3989 + flag <<= sbips_int_shift[irq];
3990 + ASSERT(!(flag & ~sbips_int_mask[irq]));
3991 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
3992 + W_REG(&sb->sbipsflag, flag);
3993 + }
3994 +}
3995 +
3996 +/*
3997 + * Initializes clocks and interrupts. SB and NVRAM access must be
3998 + * initialized prior to calling.
3999 + */
4000 +void
4001 +sb_mips_init(void *sbh)
4002 +{
4003 + ulong hz, ns, tmp;
4004 + extifregs_t *eir;
4005 + chipcregs_t *cc;
4006 + char *value;
4007 + uint irq;
4008 +
4009 + /* Figure out current SB clock speed */
4010 + if ((hz = sb_clock(sbh)) == 0)
4011 + hz = 100000000;
4012 + ns = 1000000000 / hz;
4013 +
4014 + /* Setup external interface timing */
4015 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
4016 + /* Initialize extif so we can get to the LEDs and external UART */
4017 + W_REG(&eir->prog_config, CF_EN);
4018 +
4019 + /* Set timing for the flash */
4020 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
4021 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
4022 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
4023 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
4024 +
4025 + /* Set programmable interface timing for external uart */
4026 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
4027 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
4028 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
4029 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
4030 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
4031 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
4032 + /* Set timing for the flash */
4033 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
4034 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
4035 + tmp |= CEIL(120, ns); /* W0 = 120nS */
4036 + W_REG(&cc->parallelflashwaitcnt, tmp);
4037 +
4038 + W_REG(&cc->cs01memwaitcnt, tmp);
4039 + }
4040 +
4041 + /* Chip specific initialization */
4042 + switch (sb_chip(sbh)) {
4043 + case BCM4710_DEVICE_ID:
4044 + /* Clear interrupt map */
4045 + for (irq = 0; irq <= 4; irq++)
4046 + sb_clearirq(sbh, irq);
4047 + sb_setirq(sbh, 0, SB_CODEC, 0);
4048 + sb_setirq(sbh, 0, SB_EXTIF, 0);
4049 + sb_setirq(sbh, 2, SB_ENET, 1);
4050 + sb_setirq(sbh, 3, SB_ILINE20, 0);
4051 + sb_setirq(sbh, 4, SB_PCI, 0);
4052 + ASSERT(eir);
4053 + value = nvram_get("et0phyaddr");
4054 + if (value && !strcmp(value, "31")) {
4055 + /* Enable internal UART */
4056 + W_REG(&eir->corecontrol, CC_UE);
4057 + /* Give USB its own interrupt */
4058 + sb_setirq(sbh, 1, SB_USB, 0);
4059 + } else {
4060 + /* Disable internal UART */
4061 + W_REG(&eir->corecontrol, 0);
4062 + /* Give Ethernet its own interrupt */
4063 + sb_setirq(sbh, 1, SB_ENET, 0);
4064 + sb_setirq(sbh, 0, SB_USB, 0);
4065 + }
4066 + break;
4067 + case BCM4310_DEVICE_ID:
4068 + MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
4069 + break;
4070 + }
4071 +}
4072 +
4073 +uint32
4074 +sb_mips_clock(void *sbh)
4075 +{
4076 + extifregs_t *eir;
4077 + chipcregs_t *cc;
4078 + uint32 n, m;
4079 + uint idx;
4080 + uint32 pll_type, rate = 0;
4081 +
4082 + /* get index of the current core */
4083 + idx = sb_coreidx(sbh);
4084 + pll_type = PLL_TYPE1;
4085 +
4086 + /* switch to extif or chipc core */
4087 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4088 + n = R_REG(&eir->clockcontrol_n);
4089 + m = R_REG(&eir->clockcontrol_sb);
4090 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4091 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4092 + n = R_REG(&cc->clockcontrol_n);
4093 + if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4))
4094 + m = R_REG(&cc->clockcontrol_mips);
4095 + else if (pll_type == PLL_TYPE3) {
4096 + rate = 200000000;
4097 + goto out;
4098 + } else
4099 + m = R_REG(&cc->clockcontrol_sb);
4100 + } else
4101 + goto out;
4102 +
4103 + /* calculate rate */
4104 + rate = sb_clock_rate(pll_type, n, m);
4105 +
4106 +out:
4107 + /* switch back to previous core */
4108 + sb_setcoreidx(sbh, idx);
4109 +
4110 + return rate;
4111 +}
4112 +
4113 +static void
4114 +icache_probe(int *size, int *lsize)
4115 +{
4116 + uint32 config1;
4117 + uint sets, ways;
4118 +
4119 + config1 = MFC0(C0_CONFIG, 1);
4120 +
4121 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4122 + if ((*lsize = ((config1 >> 19) & 7)))
4123 + *lsize = 2 << *lsize;
4124 + sets = 64 << ((config1 >> 22) & 7);
4125 + ways = 1 + ((config1 >> 16) & 7);
4126 + *size = *lsize * sets * ways;
4127 +}
4128 +
4129 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
4130 +
4131 +static void
4132 +handler(void)
4133 +{
4134 + /* Step 11 */
4135 + __asm__ (
4136 + ".set\tmips32\n\t"
4137 + "ssnop\n\t"
4138 + "ssnop\n\t"
4139 + /* Disable interrupts */
4140 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
4141 + "mfc0 $15, $12\n\t"
4142 + "and $15, $15, -31746\n\t"
4143 + "mtc0 $15, $12\n\t"
4144 + "eret\n\t"
4145 + "nop\n\t"
4146 + "nop\n\t"
4147 + ".set\tmips0"
4148 + );
4149 +}
4150 +
4151 +/* The following MUST come right after handler() */
4152 +static void
4153 +afterhandler(void)
4154 +{
4155 +}
4156 +
4157 +/*
4158 + * Set the MIPS, backplane and PCI clocks as closely as possible.
4159 + */
4160 +bool
4161 +sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
4162 +{
4163 + extifregs_t *eir = NULL;
4164 + chipcregs_t *cc = NULL;
4165 + mipsregs_t *mipsr = NULL;
4166 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci;
4167 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, new_ratio;
4168 + uint32 pll_type, sync_mode;
4169 + uint idx, i;
4170 + struct {
4171 + uint32 mipsclock;
4172 + uint16 n;
4173 + uint32 sb;
4174 + uint32 pci33;
4175 + uint32 pci25;
4176 + } type1_table[] = {
4177 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
4178 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
4179 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
4180 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
4181 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
4182 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
4183 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
4184 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
4185 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
4186 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
4187 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
4188 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
4189 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
4190 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
4191 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
4192 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
4193 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
4194 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
4195 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
4196 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
4197 + };
4198 + typedef struct {
4199 + uint32 mipsclock;
4200 + uint32 sbclock;
4201 + uint16 n;
4202 + uint32 sb;
4203 + uint32 pci33;
4204 + uint32 m2;
4205 + uint32 m3;
4206 + uint32 ratio;
4207 + uint32 ratio_parm;
4208 + } n4m_table_t;
4209 +
4210 + n4m_table_t type2_table[] = {
4211 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4212 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
4213 + { 200000000, 100000000, 0x0303, 0x01000000, 0x01000600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
4214 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
4215 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
4216 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
4217 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4218 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
4219 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
4220 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
4221 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4222 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4223 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
4224 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4225 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
4226 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
4227 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 }
4228 + };
4229 +
4230 + n4m_table_t type4_table[] = {
4231 + { 192000000, 96000000, 0x0702, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
4232 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
4233 + { 216000000, 108000000, 0x0211, 0x11020005, 0x11030303, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
4234 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x11030305, 0x04000005, 0x94, 0x012a00a9 },
4235 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
4236 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 0x21, 0x0aaa0555 },
4237 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
4238 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
4239 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
4240 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
4241 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
4242 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 0x52, 0x02520129 }
4243 + };
4244 + uint icache_size, ic_lsize;
4245 + ulong start, end, dst;
4246 + bool ret = FALSE;
4247 +
4248 + /* get index of the current core */
4249 + idx = sb_coreidx(sbh);
4250 +
4251 + /* switch to extif or chipc core */
4252 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4253 + pll_type = PLL_TYPE1;
4254 + clockcontrol_n = &eir->clockcontrol_n;
4255 + clockcontrol_sb = &eir->clockcontrol_sb;
4256 + clockcontrol_pci = &eir->clockcontrol_pci;
4257 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4258 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4259 + clockcontrol_n = &cc->clockcontrol_n;
4260 + clockcontrol_sb = &cc->clockcontrol_sb;
4261 + clockcontrol_pci = &cc->clockcontrol_pci;
4262 + } else
4263 + goto done;
4264 +
4265 + /* Store the current clock register values */
4266 + orig_n = R_REG(clockcontrol_n);
4267 + orig_sb = R_REG(clockcontrol_sb);
4268 + orig_pci = R_REG(clockcontrol_pci);
4269 +
4270 + if (pll_type == PLL_TYPE1) {
4271 + /* Keep the current PCI clock if not specified */
4272 + if (pciclock == 0) {
4273 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
4274 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
4275 + }
4276 +
4277 + /* Search for the closest MIPS clock less than or equal to a preferred value */
4278 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
4279 + ASSERT(type1_table[i].mipsclock ==
4280 + sb_clock_rate(pll_type, type1_table[i].n, type1_table[i].sb));
4281 + if (type1_table[i].mipsclock > mipsclock)
4282 + break;
4283 + }
4284 + if (i == 0) {
4285 + ret = FALSE;
4286 + goto done;
4287 + } else {
4288 + ret = TRUE;
4289 + i--;
4290 + }
4291 + ASSERT(type1_table[i].mipsclock <= mipsclock);
4292 +
4293 + /* No PLL change */
4294 + if ((orig_n == type1_table[i].n) &&
4295 + (orig_sb == type1_table[i].sb) &&
4296 + (orig_pci == type1_table[i].pci33))
4297 + goto done;
4298 +
4299 + /* Set the PLL controls */
4300 + W_REG(clockcontrol_n, type1_table[i].n);
4301 + W_REG(clockcontrol_sb, type1_table[i].sb);
4302 + if (pciclock == 25000000)
4303 + W_REG(clockcontrol_pci, type1_table[i].pci25);
4304 + else
4305 + W_REG(clockcontrol_pci, type1_table[i].pci33);
4306 +
4307 + /* Reset */
4308 + sb_watchdog(sbh, 1);
4309 + while (1);
4310 + } else if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4)) {
4311 + n4m_table_t *table = (pll_type == PLL_TYPE2) ? type2_table : type4_table;
4312 + uint tabsz = (pll_type == PLL_TYPE2) ? ARRAYSIZE(type2_table) : ARRAYSIZE(type4_table);
4313 +
4314 + ASSERT(cc);
4315 +
4316 + /* Store the current clock register values */
4317 + orig_m2 = R_REG(&cc->clockcontrol_m2);
4318 + orig_mips = R_REG(&cc->clockcontrol_mips);
4319 + orig_ratio_parm = 0;
4320 +
4321 + /* Look up current ratio */
4322 + for (i = 0; i < tabsz; i++) {
4323 + if ((orig_n == table[i].n) &&
4324 + (orig_sb == table[i].sb) &&
4325 + (orig_pci == table[i].pci33) &&
4326 + (orig_m2 == table[i].m2) &&
4327 + (orig_mips == table[i].m3)) {
4328 + orig_ratio_parm = table[i].ratio_parm;
4329 + break;
4330 + }
4331 + }
4332 +
4333 + /* Search for the closest MIPS clock greater or equal to a preferred value */
4334 + for (i = 0; i < tabsz; i++) {
4335 + ASSERT(table[i].mipsclock ==
4336 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
4337 + if ((mipsclock <= table[i].mipsclock) &&
4338 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
4339 + break;
4340 + }
4341 + if (i == tabsz) {
4342 + ret = FALSE;
4343 + goto done;
4344 + } else {
4345 + ret = TRUE;
4346 + }
4347 +
4348 + /* No PLL change */
4349 + if ((orig_n == table[i].n) &&
4350 + (orig_sb == table[i].sb) &&
4351 + (orig_pci == table[i].pci33) &&
4352 + (orig_m2 == table[i].m2) &&
4353 + (orig_mips == table[i].m3))
4354 + goto done;
4355 +
4356 + /* Set the PLL controls */
4357 + W_REG(clockcontrol_n, table[i].n);
4358 + W_REG(clockcontrol_sb, table[i].sb);
4359 + W_REG(clockcontrol_pci, table[i].pci33);
4360 + W_REG(&cc->clockcontrol_m2, table[i].m2);
4361 + W_REG(&cc->clockcontrol_mips, table[i].m3);
4362 +
4363 + /* No ratio change */
4364 + if (orig_ratio_parm == table[i].ratio_parm)
4365 + goto end_fill;
4366 +
4367 + new_ratio = table[i].ratio_parm;
4368 +
4369 + icache_probe(&icache_size, &ic_lsize);
4370 +
4371 + /* Preload the code into the cache */
4372 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
4373 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
4374 + while (start < end) {
4375 + cache_unroll(start, Fill_I);
4376 + start += ic_lsize;
4377 + }
4378 +
4379 + /* Copy the handler */
4380 + start = (ulong) &handler;
4381 + end = (ulong) &afterhandler;
4382 + dst = KSEG1ADDR(0x180);
4383 + for (i = 0; i < (end - start); i += 4)
4384 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
4385 +
4386 + /* Preload handler into the cache one line at a time */
4387 + for (i = 0; i < (end - start); i += 4)
4388 + cache_unroll(dst + i, Fill_I);
4389 +
4390 + /* Clear BEV bit */
4391 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
4392 +
4393 + /* Enable interrupts */
4394 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
4395 +
4396 + /* Enable MIPS timer interrupt */
4397 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
4398 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
4399 + ASSERT(mipsr);
4400 + W_REG(&mipsr->intmask, 1);
4401 +
4402 + start_fill:
4403 + /* step 1, set clock ratios */
4404 + MTC0(C0_BROADCOM, 3, new_ratio);
4405 + MTC0(C0_BROADCOM, 1, 8);
4406 +
4407 + /* step 2: program timer intr */
4408 + W_REG(&mipsr->timer, 100);
4409 + (void) R_REG(&mipsr->timer);
4410 +
4411 + /* step 3, switch to async */
4412 + sync_mode = MFC0(C0_BROADCOM, 4);
4413 + MTC0(C0_BROADCOM, 4, 1 << 22);
4414 +
4415 + /* step 4, set cfg active */
4416 + MTC0(C0_BROADCOM, 2, 0x9);
4417 +
4418 +
4419 + /* steps 5 & 6 */
4420 + __asm__ __volatile__ (
4421 + ".set\tmips3\n\t"
4422 + "wait\n\t"
4423 + ".set\tmips0"
4424 + );
4425 +
4426 + /* step 7, clear cfg_active */
4427 + MTC0(C0_BROADCOM, 2, 0);
4428 +
4429 + /* Additional Step: set back to orig sync mode */
4430 + MTC0(C0_BROADCOM, 4, sync_mode);
4431 +
4432 + /* step 8, fake soft reset */
4433 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
4434 +
4435 + end_fill:
4436 + /* step 9 set watchdog timer */
4437 + sb_watchdog(sbh, 20);
4438 + (void) R_REG(&cc->chipid);
4439 +
4440 + /* step 11 */
4441 + __asm__ __volatile__ (
4442 + ".set\tmips3\n\t"
4443 + "sync\n\t"
4444 + "wait\n\t"
4445 + ".set\tmips0"
4446 + );
4447 + while (1);
4448 + }
4449 +
4450 +done:
4451 + /* switch back to previous core */
4452 + sb_setcoreidx(sbh, idx);
4453 +
4454 + return ret;
4455 +}
4456 +
4457 +
4458 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
4459 +uint32
4460 +sb_memc_get_ncdl(void *sbh)
4461 +{
4462 + sbmemcregs_t *memc;
4463 + uint32 ret = 0;
4464 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
4465 + uint idx, rev;
4466 +
4467 + idx = sb_coreidx(sbh);
4468 +
4469 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
4470 + if (memc == 0)
4471 + goto out;
4472 +
4473 + rev = sb_corerev(sbh);
4474 +
4475 + config = R_REG(&memc->config);
4476 + wr = R_REG(&memc->wrncdlcor);
4477 + rd = R_REG(&memc->rdncdlcor);
4478 + misc = R_REG(&memc->miscdlyctl);
4479 + dqsg = R_REG(&memc->dqsgatencdl);
4480 +
4481 + rd &= MEMC_RDNCDLCOR_RD_MASK;
4482 + wr &= MEMC_WRNCDLCOR_WR_MASK;
4483 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
4484 +
4485 + if (config & MEMC_CONFIG_DDR) {
4486 + ret = (wr << 16) | (rd << 8) | dqsg;
4487 + } else {
4488 + if (rev > 0)
4489 + cd = rd;
4490 + else
4491 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
4492 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
4493 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
4494 + ret = (sm << 16) | (sd << 8) | cd;
4495 + }
4496 +
4497 +out:
4498 + /* switch back to previous core */
4499 + sb_setcoreidx(sbh, idx);
4500 +
4501 + return ret;
4502 +}
4503 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbpci.c
4504 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
4505 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbpci.c 2005-12-13 14:59:52.000000000 +0100
4506 @@ -0,0 +1,530 @@
4507 +/*
4508 + * Low-Level PCI and SB support for BCM47xx
4509 + *
4510 + * Copyright 2001-2003, Broadcom Corporation
4511 + * All Rights Reserved.
4512 + *
4513 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4514 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4515 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4516 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4517 + *
4518 + * $Id: sbpci.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
4519 + */
4520 +
4521 +#include <typedefs.h>
4522 +#include <pcicfg.h>
4523 +#include <bcmdevs.h>
4524 +#include <sbconfig.h>
4525 +#include <sbpci.h>
4526 +#include <osl.h>
4527 +#include <bcmendian.h>
4528 +#include <bcmutils.h>
4529 +#include <sbutils.h>
4530 +#include <bcmnvram.h>
4531 +#include <hndmips.h>
4532 +
4533 +/* Can free sbpci_init() memory after boot */
4534 +#ifndef linux
4535 +#define __init
4536 +#endif
4537 +
4538 +/* Emulated configuration space */
4539 +static pci_config_regs sb_config_regs[SB_MAXCORES];
4540 +
4541 +/* Banned cores */
4542 +static uint16 pci_ban[32] = { 0 };
4543 +static uint pci_banned = 0;
4544 +
4545 +/* CardBus mode */
4546 +static bool cardbus = FALSE;
4547 +
4548 +/*
4549 + * Functions for accessing external PCI configuration space
4550 + */
4551 +
4552 +/* Assume one-hot slot wiring */
4553 +#define PCI_SLOT_MAX 16
4554 +
4555 +static uint32
4556 +config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
4557 +{
4558 + uint coreidx;
4559 + sbpciregs_t *regs;
4560 + uint32 addr = 0;
4561 +
4562 + /* CardBusMode supports only one device */
4563 + if (cardbus && dev > 1)
4564 + return 0;
4565 +
4566 + coreidx = sb_coreidx(sbh);
4567 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
4568 +
4569 + /* Type 0 transaction */
4570 + if (bus == 1) {
4571 + /* Skip unwired slots */
4572 + if (dev < PCI_SLOT_MAX) {
4573 + /* Slide the PCI window to the appropriate slot */
4574 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
4575 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
4576 + (func << 8) | (off & ~3);
4577 + }
4578 + }
4579 +
4580 + /* Type 1 transaction */
4581 + else {
4582 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
4583 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
4584 + }
4585 +
4586 + sb_setcoreidx(sbh, coreidx);
4587 +
4588 + return addr;
4589 +}
4590 +
4591 +static int
4592 +extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4593 +{
4594 + uint32 addr, *reg = NULL, val;
4595 + int ret = 0;
4596 +
4597 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
4598 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
4599 + BUSPROBE(val, reg))
4600 + val = 0xffffffff;
4601 +
4602 + val >>= 8 * (off & 3);
4603 + if (len == 4)
4604 + *((uint32 *) buf) = val;
4605 + else if (len == 2)
4606 + *((uint16 *) buf) = (uint16) val;
4607 + else if (len == 1)
4608 + *((uint8 *) buf) = (uint8) val;
4609 + else
4610 + ret = -1;
4611 +
4612 + if (reg)
4613 + REG_UNMAP(reg);
4614 +
4615 + return ret;
4616 +}
4617 +
4618 +static int
4619 +extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4620 +{
4621 + uint32 addr, *reg = NULL, val;
4622 + int ret = 0;
4623 +
4624 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
4625 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
4626 + BUSPROBE(val, reg))
4627 + goto done;
4628 +
4629 + if (len == 4)
4630 + val = *((uint32 *) buf);
4631 + else if (len == 2) {
4632 + val &= ~(0xffff << (8 * (off & 3)));
4633 + val |= *((uint16 *) buf) << (8 * (off & 3));
4634 + } else if (len == 1) {
4635 + val &= ~(0xff << (8 * (off & 3)));
4636 + val |= *((uint8 *) buf) << (8 * (off & 3));
4637 + } else
4638 + ret = -1;
4639 +
4640 + W_REG(reg, val);
4641 +
4642 + done:
4643 + if (reg)
4644 + REG_UNMAP(reg);
4645 +
4646 + return ret;
4647 +}
4648 +
4649 +/*
4650 + * Functions for accessing translated SB configuration space
4651 + */
4652 +
4653 +static int
4654 +sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4655 +{
4656 + pci_config_regs *cfg;
4657 +
4658 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
4659 + return -1;
4660 + cfg = &sb_config_regs[dev];
4661 +
4662 + ASSERT(ISALIGNED(off, len));
4663 + ASSERT(ISALIGNED(buf, len));
4664 +
4665 + if (len == 4)
4666 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
4667 + else if (len == 2)
4668 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
4669 + else if (len == 1)
4670 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
4671 + else
4672 + return -1;
4673 +
4674 + return 0;
4675 +}
4676 +
4677 +static int
4678 +sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4679 +{
4680 + uint coreidx, n;
4681 + void *regs;
4682 + sbconfig_t *sb;
4683 + pci_config_regs *cfg;
4684 +
4685 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
4686 + return -1;
4687 + cfg = &sb_config_regs[dev];
4688 +
4689 + ASSERT(ISALIGNED(off, len));
4690 + ASSERT(ISALIGNED(buf, len));
4691 +
4692 + /* Emulate BAR sizing */
4693 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
4694 + len == 4 && *((uint32 *) buf) == ~0) {
4695 + coreidx = sb_coreidx(sbh);
4696 + if ((regs = sb_setcoreidx(sbh, dev))) {
4697 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
4698 + /* Highest numbered address match register */
4699 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
4700 + if (off == OFFSETOF(pci_config_regs, base[0]))
4701 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
4702 + /*else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
4703 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
4704 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
4705 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
4706 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
4707 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);*/
4708 + }
4709 + sb_setcoreidx(sbh, coreidx);
4710 + return 0;
4711 + }
4712 +
4713 + if (len == 4)
4714 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
4715 + else if (len == 2)
4716 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
4717 + else if (len == 1)
4718 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
4719 + else
4720 + return -1;
4721 +
4722 + return 0;
4723 +}
4724 +
4725 +int
4726 +sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4727 +{
4728 + if (bus == 0)
4729 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
4730 + else
4731 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
4732 +}
4733 +
4734 +int
4735 +sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
4736 +{
4737 + if (bus == 0)
4738 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
4739 + else
4740 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
4741 +}
4742 +
4743 +void
4744 +sbpci_ban(uint16 core)
4745 +{
4746 + if (pci_banned < ARRAYSIZE(pci_ban))
4747 + pci_ban[pci_banned++] = core;
4748 +}
4749 +
4750 +int __init
4751 +sbpci_init(void *sbh)
4752 +{
4753 + uint chip, chiprev, chippkg, coreidx, host, i;
4754 + sbpciregs_t *pci;
4755 + sbconfig_t *sb;
4756 + pci_config_regs *cfg;
4757 + void *regs;
4758 + char varname[8];
4759 + uint wlidx = 0;
4760 + uint16 vendor, core;
4761 + uint8 class, subclass, progif;
4762 + uint32 val;
4763 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
4764 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
4765 +
4766 + chip = sb_chip(sbh);
4767 + chiprev = sb_chiprev(sbh);
4768 + chippkg = sb_chippkg(sbh);
4769 + coreidx = sb_coreidx(sbh);
4770 +
4771 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
4772 + return -1;
4773 + sb_core_reset(sbh, 0);
4774 +
4775 + if (((chip == BCM4310_DEVICE_ID) && (chiprev == 0)) ||
4776 + ((chip == BCM4712_DEVICE_ID) && (chippkg == BCM4712SMALL_PKG_ID)))
4777 + host = 0;
4778 + else
4779 + host = !BUSPROBE(val, &pci->control);
4780 +
4781 + if (!host) {
4782 + /* Disable PCI interrupts in client mode */
4783 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
4784 + W_REG(&sb->sbintvec, 0);
4785 +
4786 + /* Disable the PCI bridge in client mode */
4787 + sbpci_ban(SB_PCI);
4788 + printf("PCI: Disabled\n");
4789 + } else {
4790 + /* Reset the external PCI bus and enable the clock */
4791 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
4792 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
4793 + OSL_DELAY(100); /* delay 100 us */
4794 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
4795 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
4796 + OSL_DELAY(1); /* delay 1 us */
4797 +
4798 + /* Enable CardBusMode */
4799 + cardbus = nvram_match("cardbus", "1");
4800 + if (cardbus) {
4801 + printf("PCI: Enabling CardBus\n");
4802 + /* GPIO 1 resets the CardBus device on bcm94710ap */
4803 + sb_gpioout(sbh, 1, 1);
4804 + sb_gpioouten(sbh, 1, 1);
4805 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
4806 + }
4807 +
4808 + /* 64 MB I/O access window */
4809 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
4810 + /* 64 MB configuration access window */
4811 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
4812 + /* 1 GB memory access window */
4813 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
4814 +
4815 + /* Enable PCI bridge BAR0 prefetch and burst */
4816 + val = 6;
4817 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
4818 +
4819 + /* Enable PCI interrupts */
4820 + W_REG(&pci->intmask, PCI_INTA);
4821 + }
4822 +
4823 + /* Scan the SB bus */
4824 + bzero(sb_config_regs, sizeof(sb_config_regs));
4825 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
4826 + cfg->vendor = 0xffff;
4827 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
4828 + continue;
4829 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
4830 +
4831 + /* Read ID register and parse vendor and core */
4832 + val = R_REG(&sb->sbidhigh);
4833 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
4834 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4835 + progif = 0;
4836 +
4837 + /* Check if this core is banned */
4838 + for (i = 0; i < pci_banned; i++)
4839 + if (core == pci_ban[i])
4840 + break;
4841 + if (i < pci_banned)
4842 + continue;
4843 +
4844 + /* Known vendor translations */
4845 + switch (vendor) {
4846 + case SB_VEND_BCM:
4847 + vendor = VENDOR_BROADCOM;
4848 + break;
4849 + }
4850 +
4851 + /* Determine class based on known core codes */
4852 + switch (core) {
4853 + case SB_ILINE20:
4854 + class = PCI_CLASS_NET;
4855 + subclass = PCI_NET_ETHER;
4856 + core = BCM47XX_ILINE_ID;
4857 + break;
4858 + case SB_ILINE100:
4859 + class = PCI_CLASS_NET;
4860 + subclass = PCI_NET_ETHER;
4861 + core = BCM4610_ILINE_ID;
4862 + break;
4863 + case SB_ENET:
4864 + class = PCI_CLASS_NET;
4865 + subclass = PCI_NET_ETHER;
4866 + core = BCM47XX_ENET_ID;
4867 + break;
4868 + case SB_SDRAM:
4869 + case SB_MEMC:
4870 + class = PCI_CLASS_MEMORY;
4871 + subclass = PCI_MEMORY_RAM;
4872 + break;
4873 + case SB_PCI:
4874 + class = PCI_CLASS_BRIDGE;
4875 + subclass = PCI_BRIDGE_PCI;
4876 + //break;
4877 + case SB_MIPS:
4878 + case SB_MIPS33:
4879 + class = PCI_CLASS_CPU;
4880 + subclass = PCI_CPU_MIPS;
4881 + break;
4882 + case SB_CODEC:
4883 + class = PCI_CLASS_COMM;
4884 + subclass = PCI_COMM_MODEM;
4885 + core = BCM47XX_V90_ID;
4886 + break;
4887 + case SB_USB:
4888 + class = PCI_CLASS_SERIAL;
4889 + subclass = PCI_SERIAL_USB;
4890 + progif = 0x10; /* OHCI */
4891 + core = BCM47XX_USB_ID;
4892 + break;
4893 + case SB_USB11H:
4894 + class = PCI_CLASS_SERIAL;
4895 + subclass = PCI_SERIAL_USB;
4896 + progif = 0x10; /* OHCI */
4897 + core = BCM47XX_USBH_ID;
4898 + break;
4899 + case SB_USB11D:
4900 + class = PCI_CLASS_SERIAL;
4901 + subclass = PCI_SERIAL_USB;
4902 + core = BCM47XX_USBD_ID;
4903 + break;
4904 + case SB_IPSEC:
4905 + class = PCI_CLASS_CRYPT;
4906 + subclass = PCI_CRYPT_NETWORK;
4907 + core = BCM47XX_IPSEC_ID;
4908 + break;
4909 + case SB_EXTIF:
4910 + case SB_CC:
4911 + class = PCI_CLASS_MEMORY;
4912 + subclass = PCI_MEMORY_FLASH;
4913 + break;
4914 + case SB_D11:
4915 + class = PCI_CLASS_NET;
4916 + subclass = PCI_NET_OTHER;
4917 + /* Let an nvram variable override this */
4918 + sprintf(varname, "wl%did", wlidx);
4919 + wlidx++;
4920 + if ((core = getintvar(NULL, varname)) == 0) {
4921 + if (chip == BCM4712_DEVICE_ID) {
4922 + if (chippkg == BCM4712SMALL_PKG_ID)
4923 + core = BCM4306_D11G_ID;
4924 + else
4925 + core = BCM4306_D11DUAL_ID;
4926 + } else {
4927 + /* 4310 */
4928 + core = BCM4310_D11B_ID;
4929 + }
4930 + }
4931 + break;
4932 +
4933 + default:
4934 + class = subclass = progif = 0xff;
4935 + break;
4936 + }
4937 +
4938 + /* Supported translations */
4939 + cfg->vendor = htol16(vendor);
4940 + cfg->device = htol16(core);
4941 + cfg->rev_id = chiprev;
4942 + cfg->prog_if = progif;
4943 + cfg->sub_class = subclass;
4944 + cfg->base_class = class;
4945 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
4946 + cfg->base[1] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch1)))*/;
4947 + cfg->base[2] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch2)))*/;
4948 + cfg->base[3] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch3)))*/;
4949 + cfg->base[4] = 0;
4950 + cfg->base[5] = 0;
4951 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
4952 + cfg->header_type = PCI_HEADER_BRIDGE;
4953 + else
4954 + cfg->header_type = PCI_HEADER_NORMAL;
4955 + /* Save core interrupt flag */
4956 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
4957 + /* Default to MIPS shared interrupt 0 */
4958 + cfg->int_line = 0;
4959 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
4960 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
4961 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
4962 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
4963 + val = R_REG(&sb->sbipsflag);
4964 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
4965 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
4966 + break;
4967 + }
4968 + if (cfg->int_line > 4)
4969 + cfg->int_line = 0;
4970 + }
4971 + /* Emulated core */
4972 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
4973 + }
4974 +
4975 + sb_setcoreidx(sbh, coreidx);
4976 + return 0;
4977 +}
4978 +
4979 +void
4980 +sbpci_check(void *sbh)
4981 +{
4982 + uint coreidx;
4983 + sbpciregs_t *pci;
4984 + uint32 sbtopci1;
4985 + uint32 buf[64], *ptr, i;
4986 + ulong pa;
4987 + volatile uint j;
4988 +
4989 + coreidx = sb_coreidx(sbh);
4990 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
4991 +
4992 + /* Clear the test array */
4993 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
4994 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
4995 + memset(ptr, 0, sizeof(buf));
4996 +
4997 + /* Point PCI window 1 to memory */
4998 + sbtopci1 = R_REG(&pci->sbtopci1);
4999 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
5000 +
5001 + /* Fill the test array via PCI window 1 */
5002 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
5003 + for (i = 0; i < ARRAYSIZE(buf); i++) {
5004 + for (j = 0; j < 2; j++);
5005 + W_REG(&ptr[i], i);
5006 + }
5007 + REG_UNMAP(ptr);
5008 +
5009 + /* Restore PCI window 1 */
5010 + W_REG(&pci->sbtopci1, sbtopci1);
5011 +
5012 + /* Check the test array */
5013 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
5014 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
5015 + for (i = 0; i < ARRAYSIZE(buf); i++) {
5016 + if (ptr[i] != i)
5017 + break;
5018 + }
5019 +
5020 + /* Change the clock if the test fails */
5021 + if (i < ARRAYSIZE(buf)) {
5022 + uint32 req, cur;
5023 +
5024 + cur = sb_clock(sbh);
5025 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
5026 + for (req = 104000000; req < 176000000; req += 4000000) {
5027 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
5028 + /* This will only reset if the clocks are valid and have changed */
5029 + sb_mips_setclock(sbh, req, 0, 0);
5030 + }
5031 + /* Should not reach here */
5032 + ASSERT(0);
5033 + }
5034 +
5035 + sb_setcoreidx(sbh, coreidx);
5036 +}
5037 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbutils.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbutils.c
5038 --- linux-2.6.15-rc5/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
5039 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/broadcom/sbutils.c 2005-12-13 14:59:52.000000000 +0100
5040 @@ -0,0 +1,1895 @@
5041 +/*
5042 + * Misc utility routines for accessing chip-specific features
5043 + * of the SiliconBackplane-based Broadcom chips.
5044 + *
5045 + * Copyright 2001-2003, Broadcom Corporation
5046 + * All Rights Reserved.
5047 + *
5048 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5049 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5050 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5051 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5052 + *
5053 + * $Id: sbutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
5054 + */
5055 +
5056 +#include <typedefs.h>
5057 +#include <osl.h>
5058 +#include <bcmutils.h>
5059 +#include <bcmdevs.h>
5060 +#include <sbconfig.h>
5061 +#include <sbchipc.h>
5062 +#include <sbpci.h>
5063 +#include <pcicfg.h>
5064 +#include <sbpcmcia.h>
5065 +#include <sbextif.h>
5066 +#include <sbutils.h>
5067 +#include <bcmsrom.h>
5068 +
5069 +/* debug/trace */
5070 +#define SB_ERROR(args)
5071 +
5072 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
5073 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
5074 +
5075 +/* misc sb info needed by some of the routines */
5076 +typedef struct sb_info {
5077 + uint chip; /* chip number */
5078 + uint chiprev; /* chip revision */
5079 + uint chippkg; /* chip package option */
5080 + uint boardtype; /* board type */
5081 + uint boardvendor; /* board vendor id */
5082 + uint bus; /* what bus type we are going through */
5083 +
5084 + void *osh; /* osl os handle */
5085 + void *sdh; /* bcmsdh handle */
5086 +
5087 + void *curmap; /* current regs va */
5088 + void *regs[SB_MAXCORES]; /* other regs va */
5089 +
5090 + uint curidx; /* current core index */
5091 + uint dev_coreid; /* the core provides driver functions */
5092 + uint pciidx; /* pci core index */
5093 + uint pcirev; /* pci core rev */
5094 +
5095 + uint pcmciaidx; /* pcmcia core index */
5096 + uint pcmciarev; /* pcmcia core rev */
5097 + bool memseg; /* flag to toggle MEM_SEG register */
5098 +
5099 + uint ccrev; /* chipc core rev */
5100 +
5101 + uint gpioidx; /* gpio control core index */
5102 + uint gpioid; /* gpio control coretype */
5103 +
5104 + uint numcores; /* # discovered cores */
5105 + uint coreid[SB_MAXCORES]; /* id of each core */
5106 +
5107 + void *intr_arg; /* interrupt callback function arg */
5108 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
5109 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
5110 +} sb_info_t;
5111 +
5112 +/* local prototypes */
5113 +static void* sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
5114 +static void sb_scan(sb_info_t *si);
5115 +static uint sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val);
5116 +static uint _sb_coreidx(void *sbh);
5117 +static uint sb_findcoreidx(void *sbh, uint coreid, uint coreunit);
5118 +static uint sb_pcidev2chip(uint pcidev);
5119 +static uint sb_chip2numcores(uint chip);
5120 +
5121 +#define SB_INFO(sbh) (sb_info_t*)sbh
5122 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
5123 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) \
5124 + && ISALIGNED((x), SB_CORE_SIZE))
5125 +#define GOODREGS(regs) (regs && ISALIGNED(regs, SB_CORE_SIZE))
5126 +#define REGS2SB(va) (sbconfig_t*) ((uint)(va) + SBCONFIGOFF)
5127 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
5128 +#define BADIDX (SB_MAXCORES+1)
5129 +
5130 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
5131 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
5132 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
5133 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
5134 +
5135 +/*
5136 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
5137 + * after core switching to avoid invalid register accesss inside ISR.
5138 + */
5139 +#define INTR_OFF(si, intr_val) \
5140 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
5141 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
5142 +#define INTR_RESTORE(si, intr_val) \
5143 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
5144 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
5145 +
5146 +/* power control defines */
5147 +#define PLL_DELAY 150 /* 150us pll on delay */
5148 +#define FREF_DELAY 15 /* 15us fref change delay */
5149 +#define LPOMINFREQ 25000 /* low power oscillator min */
5150 +#define LPOMAXFREQ 43000 /* low power oscillator max */
5151 +#define XTALMINFREQ 19800000 /* 20mhz - 1% */
5152 +#define XTALMAXFREQ 20200000 /* 20mhz + 1% */
5153 +#define PCIMINFREQ 25000000 /* 25mhz */
5154 +#define PCIMAXFREQ 34000000 /* 33mhz + fudge */
5155 +
5156 +#define SCC_LOW2FAST_LIMIT 5000 /* turn on fast clock time, in unit of ms */
5157 +
5158 +
5159 +static uint32
5160 +sb_read_sbreg(void *sbh, volatile uint32 *sbr)
5161 +{
5162 + sb_info_t *si;
5163 + uint8 tmp;
5164 + uint32 val, intr_val = 0;
5165 +
5166 + si = SB_INFO(sbh);
5167 +
5168 + /*
5169 + * compact flash only has 11 bits address, while we needs 12 bits address.
5170 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
5171 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
5172 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
5173 + */
5174 + if(si->memseg) {
5175 + INTR_OFF(si, intr_val);
5176 + tmp = 1;
5177 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
5178 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11*/
5179 + }
5180 +
5181 + val = R_REG(sbr);
5182 +
5183 + if(si->memseg) {
5184 + tmp = 0;
5185 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
5186 + INTR_RESTORE(si, intr_val);
5187 + }
5188 +
5189 + return (val);
5190 +}
5191 +
5192 +static void
5193 +sb_write_sbreg(void *sbh, volatile uint32 *sbr, uint32 v)
5194 +{
5195 + sb_info_t *si;
5196 + uint8 tmp;
5197 + volatile uint32 dummy;
5198 + uint32 intr_val = 0;
5199 +
5200 + si = SB_INFO(sbh);
5201 +
5202 + /*
5203 + * compact flash only has 11 bits address, while we needs 12 bits address.
5204 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
5205 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
5206 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
5207 + */
5208 + if(si->memseg) {
5209 + INTR_OFF(si, intr_val);
5210 + tmp = 1;
5211 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
5212 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11 */
5213 + }
5214 +
5215 + if ((si->bus == PCMCIA_BUS) || (si->bus == PCI_BUS)) {
5216 +#ifdef IL_BIGENDIAN
5217 + dummy = R_REG(sbr);
5218 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
5219 + dummy = R_REG(sbr);
5220 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
5221 +#else
5222 + dummy = R_REG(sbr);
5223 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
5224 + dummy = R_REG(sbr);
5225 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
5226 +#endif
5227 + } else
5228 + W_REG(sbr, v);
5229 +
5230 + if(si->memseg) {
5231 + tmp = 0;
5232 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
5233 + INTR_RESTORE(si, intr_val);
5234 + }
5235 +}
5236 +
5237 +/*
5238 + * Allocate a sb handle.
5239 + * devid - pci device id (used to determine chip#)
5240 + * osh - opaque OS handle
5241 + * regs - virtual address of initial core registers
5242 + * bustype - pci/pcmcia/sb/sdio/etc
5243 + * vars - pointer to a pointer area for "environment" variables
5244 + * varsz - pointer to int to return the size of the vars
5245 + */
5246 +void*
5247 +sb_attach(uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
5248 +{
5249 + sb_info_t *si;
5250 +
5251 + /* alloc sb_info_t */
5252 + if ((si = MALLOC(sizeof (sb_info_t))) == NULL) {
5253 + SB_ERROR(("sb_attach: malloc failed!\n"));
5254 + return (NULL);
5255 + }
5256 +
5257 + return (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, varsz));
5258 +}
5259 +
5260 +/* global kernel resource */
5261 +static sb_info_t ksi;
5262 +
5263 +/* generic kernel variant of sb_attach() */
5264 +void*
5265 +sb_kattach()
5266 +{
5267 + uint32 *regs;
5268 + char *unused;
5269 + int varsz;
5270 +
5271 + if (ksi.curmap == NULL) {
5272 + uint32 cid;
5273 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
5274 + cid = R_REG((uint32 *)regs);
5275 + if ((cid == 0x08104712) || (cid == 0x08114712)) {
5276 + uint32 *scc, val;
5277 +
5278 + scc = (uint32 *)((uint32)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
5279 + val = R_REG(scc);
5280 + SB_ERROR((" initial scc = 0x%x\n", val));
5281 + val |= SCC_SS_XTAL;
5282 + W_REG(scc, val);
5283 + }
5284 +
5285 + sb_doattach(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
5286 + SB_BUS, NULL, &unused, &varsz);
5287 + }
5288 +
5289 + return &ksi;
5290 +}
5291 +
5292 +static void*
5293 +sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
5294 +{
5295 + uint origidx;
5296 + chipcregs_t *cc;
5297 + uint32 w;
5298 +
5299 + ASSERT(GOODREGS(regs));
5300 +
5301 + bzero((uchar*)si, sizeof (sb_info_t));
5302 +
5303 + si->pciidx = si->gpioidx = BADIDX;
5304 +
5305 + si->osh = osh;
5306 + si->curmap = regs;
5307 + si->sdh = sdh;
5308 +
5309 + /* 4317A0 PCMCIA is no longer supported */
5310 + if ((bustype == PCMCIA_BUS) && (R_REG((uint32 *)regs) == 0x04104317))
5311 + return NULL;
5312 +
5313 + /* check to see if we are a sb core mimic'ing a pci core */
5314 + if (bustype == PCI_BUS) {
5315 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
5316 + bustype = SB_BUS;
5317 + else
5318 + bustype = PCI_BUS;
5319 + }
5320 +
5321 + si->bus = bustype;
5322 +
5323 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
5324 + if (si->bus == PCI_BUS)
5325 + sb_pwrctl_xtal((void*)si, XTAL|PLL, ON);
5326 +
5327 + /* clear any previous epidiag-induced target abort */
5328 + sb_taclear((void*)si);
5329 +
5330 + /* initialize current core index value */
5331 + si->curidx = _sb_coreidx((void*)si);
5332 +
5333 + /* keep and reuse the initial register mapping */
5334 + origidx = si->curidx;
5335 + if (si->bus == SB_BUS)
5336 + si->regs[origidx] = regs;
5337 +
5338 + /* initialize the vars */
5339 + if (srom_var_init(si->bus, si->curmap, osh, vars, varsz)) {
5340 + SB_ERROR(("sb_attach: srom_var_init failed\n"));
5341 + goto bad;
5342 + }
5343 +
5344 + if (si->bus == PCMCIA_BUS) {
5345 + w = getintvar(*vars, "regwindowsz");
5346 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
5347 + }
5348 +
5349 + /* is core-0 a chipcommon core? */
5350 + si->numcores = 1;
5351 + cc = (chipcregs_t*) sb_setcoreidx((void*)si, 0);
5352 + if (sb_coreid((void*)si) != SB_CC)
5353 + cc = NULL;
5354 +
5355 + /* determine chip id and rev */
5356 + if (cc) {
5357 + /* chip common core found! */
5358 + si->chip = R_REG(&cc->chipid) & CID_ID_MASK;
5359 + si->chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
5360 + si->chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
5361 + } else {
5362 + /* without chip common core, get devid for PCMCIA */
5363 + if (si->bus == PCMCIA_BUS)
5364 + devid = getintvar(*vars, "devid");
5365 +
5366 + /* no chip common core -- must convert device id to chip id */
5367 + if ((si->chip = sb_pcidev2chip(devid)) == 0) {
5368 + SB_ERROR(("sb_attach: unrecognized device id 0x%04x\n", devid));
5369 + goto bad;
5370 + }
5371 +
5372 + /*
5373 + * The chip revision number is hardwired into all
5374 + * of the pci function config rev fields and is
5375 + * independent from the individual core revision numbers.
5376 + * For example, the "A0" silicon of each chip is chip rev 0.
5377 + * For PCMCIA we get it from the CIS instead.
5378 + */
5379 + if (si->bus == PCMCIA_BUS) {
5380 + ASSERT(vars);
5381 + si->chiprev = getintvar(*vars, "chiprev");
5382 + } else if (si->bus == PCI_BUS) {
5383 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
5384 + si->chiprev = w & 0xff;
5385 + } else
5386 + si->chiprev = 0;
5387 + }
5388 +
5389 + /* get chipcommon rev */
5390 + si->ccrev = cc? sb_corerev((void*)si) : 0;
5391 +
5392 + /* determine numcores */
5393 + if ((si->ccrev == 4) || (si->ccrev >= 6))
5394 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
5395 + else
5396 + si->numcores = sb_chip2numcores(si->chip);
5397 +
5398 + /* return to original core */
5399 + sb_setcoreidx((void*)si, origidx);
5400 +
5401 + /* sanity checks */
5402 + ASSERT(si->chip);
5403 + /* 4704A1 is chiprev 8 :-( */
5404 + ASSERT((si->chiprev < 8) ||
5405 + ((si->chip == BCM4704_DEVICE_ID) && ((si->chiprev == 8))));
5406 +
5407 + /* scan for cores */
5408 + sb_scan(si);
5409 +
5410 + /* pci core is required */
5411 + if (!GOODIDX(si->pciidx)) {
5412 + SB_ERROR(("sb_attach: pci core not found\n"));
5413 + goto bad;
5414 + }
5415 +
5416 + /* gpio control core is required */
5417 + if (!GOODIDX(si->gpioidx)) {
5418 + SB_ERROR(("sb_attach: gpio control core not found\n"));
5419 + goto bad;
5420 + }
5421 +
5422 + /* get boardtype and boardrev */
5423 + switch (si->bus) {
5424 + case PCI_BUS:
5425 + /* do a pci config read to get subsystem id and subvendor id */
5426 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
5427 + si->boardvendor = w & 0xffff;
5428 + si->boardtype = (w >> 16) & 0xffff;
5429 + break;
5430 +
5431 + case PCMCIA_BUS:
5432 + case SDIO_BUS:
5433 + si->boardvendor = getintvar(*vars, "manfid");
5434 + si->boardtype = getintvar(*vars, "prodid");
5435 + break;
5436 +
5437 + case SB_BUS:
5438 + si->boardvendor = VENDOR_BROADCOM;
5439 + si->boardtype = 0xffff;
5440 + break;
5441 + }
5442 +
5443 + if (si->boardtype == 0) {
5444 + SB_ERROR(("sb_attach: unknown board type\n"));
5445 + ASSERT(si->boardtype);
5446 + }
5447 +
5448 + return ((void*)si);
5449 +
5450 +bad:
5451 + MFREE(si, sizeof (sb_info_t));
5452 + return (NULL);
5453 +}
5454 +
5455 +uint
5456 +sb_coreid(void *sbh)
5457 +{
5458 + sb_info_t *si;
5459 + sbconfig_t *sb;
5460 +
5461 + si = SB_INFO(sbh);
5462 + sb = REGS2SB(si->curmap);
5463 +
5464 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
5465 +}
5466 +
5467 +uint
5468 +sb_coreidx(void *sbh)
5469 +{
5470 + sb_info_t *si;
5471 +
5472 + si = SB_INFO(sbh);
5473 + return (si->curidx);
5474 +}
5475 +
5476 +/* return current index of core */
5477 +static uint
5478 +_sb_coreidx(void *sbh)
5479 +{
5480 + sb_info_t *si;
5481 + sbconfig_t *sb;
5482 + uint32 sbaddr = 0;
5483 +
5484 + si = SB_INFO(sbh);
5485 + ASSERT(si);
5486 +
5487 + switch (si->bus) {
5488 + case SB_BUS:
5489 + sb = REGS2SB(si->curmap);
5490 + sbaddr = sb_base(R_SBREG(sbh, &sb->sbadmatch0));
5491 + break;
5492 +
5493 + case PCI_BUS:
5494 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
5495 + break;
5496 +
5497 + case PCMCIA_BUS: {
5498 + uint8 tmp;
5499 +
5500 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
5501 + sbaddr = (uint)tmp << 12;
5502 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
5503 + sbaddr |= (uint)tmp << 16;
5504 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
5505 + sbaddr |= (uint)tmp << 24;
5506 + break;
5507 + }
5508 + default:
5509 + ASSERT(0);
5510 + }
5511 +
5512 + ASSERT(GOODCOREADDR(sbaddr));
5513 + return ((sbaddr - SB_ENUM_BASE)/SB_CORE_SIZE);
5514 +}
5515 +
5516 +uint
5517 +sb_corevendor(void *sbh)
5518 +{
5519 + sb_info_t *si;
5520 + sbconfig_t *sb;
5521 +
5522 + si = SB_INFO(sbh);
5523 + sb = REGS2SB(si->curmap);
5524 +
5525 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
5526 +}
5527 +
5528 +uint
5529 +sb_corerev(void *sbh)
5530 +{
5531 + sb_info_t *si;
5532 + sbconfig_t *sb;
5533 +
5534 + si = SB_INFO(sbh);
5535 + sb = REGS2SB(si->curmap);
5536 +
5537 + return (R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_RC_MASK);
5538 +}
5539 +
5540 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
5541 +
5542 +/* set/clear sbtmstatelow core-specific flags */
5543 +uint32
5544 +sb_coreflags(void *sbh, uint32 mask, uint32 val)
5545 +{
5546 + sb_info_t *si;
5547 + sbconfig_t *sb;
5548 + uint32 w;
5549 +
5550 + si = SB_INFO(sbh);
5551 + sb = REGS2SB(si->curmap);
5552 +
5553 + ASSERT((val & ~mask) == 0);
5554 + ASSERT((mask & ~SBTML_ALLOW) == 0);
5555 +
5556 + /* mask and set */
5557 + if (mask || val) {
5558 + w = (R_SBREG(sbh, &sb->sbtmstatelow) & ~mask) | val;
5559 + W_SBREG(sbh, &sb->sbtmstatelow, w);
5560 + }
5561 +
5562 + /* return the new value */
5563 + return (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_ALLOW);
5564 +}
5565 +
5566 +/* set/clear sbtmstatehigh core-specific flags */
5567 +uint32
5568 +sb_coreflagshi(void *sbh, uint32 mask, uint32 val)
5569 +{
5570 + sb_info_t *si;
5571 + sbconfig_t *sb;
5572 + uint32 w;
5573 +
5574 + si = SB_INFO(sbh);
5575 + sb = REGS2SB(si->curmap);
5576 +
5577 + ASSERT((val & ~mask) == 0);
5578 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
5579 +
5580 + /* mask and set */
5581 + if (mask || val) {
5582 + w = (R_SBREG(sbh, &sb->sbtmstatehigh) & ~mask) | val;
5583 + W_SBREG(sbh, &sb->sbtmstatehigh, w);
5584 + }
5585 +
5586 + /* return the new value */
5587 + return (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
5588 +}
5589 +
5590 +bool
5591 +sb_iscoreup(void *sbh)
5592 +{
5593 + sb_info_t *si;
5594 + sbconfig_t *sb;
5595 +
5596 + si = SB_INFO(sbh);
5597 + sb = REGS2SB(si->curmap);
5598 +
5599 + return ((R_SBREG(sbh, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK);
5600 +}
5601 +
5602 +/*
5603 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
5604 + * switch back to the original core, and return the new value.
5605 + */
5606 +static uint
5607 +sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val)
5608 +{
5609 + sb_info_t *si;
5610 + uint origidx;
5611 + uint32 *r;
5612 + uint w;
5613 + uint intr_val = 0;
5614 +
5615 + ASSERT(GOODIDX(coreidx));
5616 + ASSERT(regoff < SB_CORE_SIZE);
5617 + ASSERT((val & ~mask) == 0);
5618 +
5619 + si = SB_INFO(sbh);
5620 +
5621 + /* save current core index */
5622 + origidx = sb_coreidx(sbh);
5623 +
5624 + /* switch core */
5625 + INTR_OFF(si, intr_val);
5626 + r = (uint32*) ((uint) sb_setcoreidx(sbh, coreidx) + regoff);
5627 +
5628 + /* mask and set */
5629 + if (mask || val) {
5630 + if (regoff >= SBCONFIGOFF) {
5631 + w = (R_SBREG(sbh, r) & ~mask) | val;
5632 + W_SBREG(sbh, r, w);
5633 + } else {
5634 + w = (R_REG(r) & ~mask) | val;
5635 + W_REG(r, w);
5636 + }
5637 + }
5638 +
5639 + /* readback */
5640 + w = R_SBREG(sbh, r);
5641 +
5642 + /* restore core index */
5643 + if (origidx != coreidx)
5644 + sb_setcoreidx(sbh, origidx);
5645 +
5646 + INTR_RESTORE(si, intr_val);
5647 + return (w);
5648 +}
5649 +
5650 +/* scan the sb enumerated space to identify all cores */
5651 +static void
5652 +sb_scan(sb_info_t *si)
5653 +{
5654 + void *sbh;
5655 + uint origidx;
5656 + uint i;
5657 +
5658 + sbh = (void*) si;
5659 +
5660 + /* numcores should already be set */
5661 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
5662 +
5663 + /* save current core index */
5664 + origidx = sb_coreidx(sbh);
5665 +
5666 + si->pciidx = si->gpioidx = BADIDX;
5667 +
5668 + for (i = 0; i < si->numcores; i++) {
5669 + sb_setcoreidx(sbh, i);
5670 + si->coreid[i] = sb_coreid(sbh);
5671 +
5672 + if (si->coreid[i] == SB_CC)
5673 + si->ccrev = sb_corerev(sbh);
5674 +
5675 + else if (si->coreid[i] == SB_PCI) {
5676 + si->pciidx = i;
5677 + si->pcirev = sb_corerev(sbh);
5678 +
5679 + }else if (si->coreid[i] == SB_PCMCIA){
5680 + si->pcmciaidx = i;
5681 + si->pcmciarev = sb_corerev(sbh);
5682 + }
5683 + }
5684 +
5685 + /*
5686 + * Find the gpio "controlling core" type and index.
5687 + * Precedence:
5688 + * - if there's a chip common core - use that
5689 + * - else if there's a pci core (rev >= 2) - use that
5690 + * - else there had better be an extif core (4710 only)
5691 + */
5692 + if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) {
5693 + si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0);
5694 + si->gpioid = SB_CC;
5695 + } else if (GOODIDX(si->pciidx) && (si->pcirev >= 2)) {
5696 + si->gpioidx = si->pciidx;
5697 + si->gpioid = SB_PCI;
5698 + } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) {
5699 + si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0);
5700 + si->gpioid = SB_EXTIF;
5701 + }
5702 +
5703 + /* return to original core index */
5704 + sb_setcoreidx(sbh, origidx);
5705 +}
5706 +
5707 +/* may be called with core in reset */
5708 +void
5709 +sb_detach(void *sbh)
5710 +{
5711 + sb_info_t *si;
5712 + uint idx;
5713 +
5714 + si = SB_INFO(sbh);
5715 +
5716 + if (si == NULL)
5717 + return;
5718 +
5719 + if (si->bus == SB_BUS)
5720 + for (idx = 0; idx < SB_MAXCORES; idx++)
5721 + if (si->regs[idx]) {
5722 + REG_UNMAP(si->regs[idx]);
5723 + si->regs[idx] = NULL;
5724 + }
5725 +
5726 + MFREE(si, sizeof (sb_info_t));
5727 +}
5728 +
5729 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
5730 +static uint
5731 +sb_pcidev2chip(uint pcidev)
5732 +{
5733 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
5734 + return (BCM4710_DEVICE_ID);
5735 + if ((pcidev >= BCM4610_DEVICE_ID) && (pcidev <= BCM4610_USB_ID))
5736 + return (BCM4610_DEVICE_ID);
5737 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
5738 + return (BCM4402_DEVICE_ID);
5739 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
5740 + return (BCM4307_DEVICE_ID);
5741 + if (pcidev == BCM4301_DEVICE_ID)
5742 + return (BCM4301_DEVICE_ID);
5743 +
5744 + return (0);
5745 +}
5746 +
5747 +/* convert chip number to number of i/o cores */
5748 +static uint
5749 +sb_chip2numcores(uint chip)
5750 +{
5751 + if (chip == 0x4710)
5752 + return (9);
5753 + if (chip == 0x4610)
5754 + return (9);
5755 + if (chip == 0x4402)
5756 + return (3);
5757 + if ((chip == 0x4307) || (chip == 0x4301))
5758 + return (5);
5759 + if (chip == 0x4310)
5760 + return (8);
5761 + if (chip == 0x4306) /* < 4306c0 */
5762 + return (6);
5763 + if (chip == 0x4704)
5764 + return (9);
5765 + if (chip == 0x5365)
5766 + return (7);
5767 +
5768 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
5769 + ASSERT(0);
5770 + return (1);
5771 +}
5772 +
5773 +/* return index of coreid or BADIDX if not found */
5774 +static uint
5775 +sb_findcoreidx(void *sbh, uint coreid, uint coreunit)
5776 +{
5777 + sb_info_t *si;
5778 + uint found;
5779 + uint i;
5780 +
5781 + si = SB_INFO(sbh);
5782 + found = 0;
5783 +
5784 + for (i = 0; i < si->numcores; i++)
5785 + if (si->coreid[i] == coreid) {
5786 + if (found == coreunit)
5787 + return (i);
5788 + found++;
5789 + }
5790 +
5791 + return (BADIDX);
5792 +}
5793 +
5794 +/* change logical "focus" to the indiciated core */
5795 +void*
5796 +sb_setcoreidx(void *sbh, uint coreidx)
5797 +{
5798 + sb_info_t *si;
5799 + uint32 sbaddr;
5800 + uint8 tmp;
5801 +
5802 + si = SB_INFO(sbh);
5803 +
5804 + if (coreidx >= si->numcores)
5805 + return (NULL);
5806 +
5807 + /*
5808 + * If the user has provided an interrupt mask enabled function,
5809 + * then assert interrupts are disabled before switching the core.
5810 + */
5811 + ASSERT((si->imf == NULL) || !(*si->imf)(si->imfarg));
5812 +
5813 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
5814 +
5815 + switch (si->bus) {
5816 + case SB_BUS:
5817 + /* map new one */
5818 + if (!si->regs[coreidx]) {
5819 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
5820 + ASSERT(GOODREGS(si->regs[coreidx]));
5821 + }
5822 + si->curmap = si->regs[coreidx];
5823 + break;
5824 +
5825 + case PCI_BUS:
5826 + /* point bar0 window */
5827 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
5828 + break;
5829 +
5830 + case PCMCIA_BUS:
5831 + tmp = (sbaddr >> 12) & 0x0f;
5832 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
5833 + tmp = (sbaddr >> 16) & 0xff;
5834 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
5835 + tmp = (sbaddr >> 24) & 0xff;
5836 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
5837 + break;
5838 + }
5839 +
5840 + si->curidx = coreidx;
5841 +
5842 + return (si->curmap);
5843 +}
5844 +
5845 +/* change logical "focus" to the indicated core */
5846 +void*
5847 +sb_setcore(void *sbh, uint coreid, uint coreunit)
5848 +{
5849 + sb_info_t *si;
5850 + uint idx;
5851 +
5852 + si = SB_INFO(sbh);
5853 +
5854 + idx = sb_findcoreidx(sbh, coreid, coreunit);
5855 + if (!GOODIDX(idx))
5856 + return (NULL);
5857 +
5858 + return (sb_setcoreidx(sbh, idx));
5859 +}
5860 +
5861 +/* return chip number */
5862 +uint
5863 +sb_chip(void *sbh)
5864 +{
5865 + sb_info_t *si;
5866 +
5867 + si = SB_INFO(sbh);
5868 + return (si->chip);
5869 +}
5870 +
5871 +/* return chip revision number */
5872 +uint
5873 +sb_chiprev(void *sbh)
5874 +{
5875 + sb_info_t *si;
5876 +
5877 + si = SB_INFO(sbh);
5878 + return (si->chiprev);
5879 +}
5880 +
5881 +/* return chip package option */
5882 +uint
5883 +sb_chippkg(void *sbh)
5884 +{
5885 + sb_info_t *si;
5886 +
5887 + si = SB_INFO(sbh);
5888 + return (si->chippkg);
5889 +}
5890 +
5891 +/* return board vendor id */
5892 +uint
5893 +sb_boardvendor(void *sbh)
5894 +{
5895 + sb_info_t *si;
5896 +
5897 + si = SB_INFO(sbh);
5898 + return (si->boardvendor);
5899 +}
5900 +
5901 +/* return boardtype */
5902 +uint
5903 +sb_boardtype(void *sbh)
5904 +{
5905 + sb_info_t *si;
5906 + char *var;
5907 +
5908 + si = SB_INFO(sbh);
5909 +
5910 + if (si->bus == SB_BUS && si->boardtype == 0xffff) {
5911 + /* boardtype format is a hex string */
5912 + si->boardtype = getintvar(NULL, "boardtype");
5913 +
5914 + /* backward compatibility for older boardtype string format */
5915 + if ((si->boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
5916 + if (!strcmp(var, "bcm94710dev"))
5917 + si->boardtype = BCM94710D_BOARD;
5918 + else if (!strcmp(var, "bcm94710ap"))
5919 + si->boardtype = BCM94710AP_BOARD;
5920 + else if (!strcmp(var, "bcm94310u"))
5921 + si->boardtype = BCM94310U_BOARD;
5922 + else if (!strcmp(var, "bu4711"))
5923 + si->boardtype = BU4711_BOARD;
5924 + else if (!strcmp(var, "bu4710"))
5925 + si->boardtype = BU4710_BOARD;
5926 + else if (!strcmp(var, "bcm94702mn"))
5927 + si->boardtype = BCM94702MN_BOARD;
5928 + else if (!strcmp(var, "bcm94710r1"))
5929 + si->boardtype = BCM94710R1_BOARD;
5930 + else if (!strcmp(var, "bcm94710r4"))
5931 + si->boardtype = BCM94710R4_BOARD;
5932 + else if (!strcmp(var, "bcm94702cpci"))
5933 + si->boardtype = BCM94702CPCI_BOARD;
5934 + else if (!strcmp(var, "bcm95380_rr"))
5935 + si->boardtype = BCM95380RR_BOARD;
5936 + }
5937 + }
5938 +
5939 + return (si->boardtype);
5940 +}
5941 +
5942 +/* return board bus style */
5943 +uint
5944 +sb_boardstyle(void *sbh)
5945 +{
5946 + sb_info_t *si;
5947 + uint16 w;
5948 +
5949 + si = SB_INFO(sbh);
5950 +
5951 + if (si->bus == PCMCIA_BUS)
5952 + return (BOARDSTYLE_PCMCIA);
5953 +
5954 + if (si->bus == SB_BUS)
5955 + return (BOARDSTYLE_SOC);
5956 +
5957 + /* bus is PCI */
5958 +
5959 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CIS, sizeof (uint32)) != 0)
5960 + return (BOARDSTYLE_CARDBUS);
5961 +
5962 + if ((srom_read(si->bus, si->curmap, si->osh, (SPROM_SIZE - 1) * 2, 2, &w) == 0) &&
5963 + (w == 0x0313))
5964 + return (BOARDSTYLE_CARDBUS);
5965 +
5966 + return (BOARDSTYLE_PCI);
5967 +}
5968 +
5969 +/* return boolean if sbh device is in pci hostmode or client mode */
5970 +uint
5971 +sb_bus(void *sbh)
5972 +{
5973 + sb_info_t *si;
5974 +
5975 + si = SB_INFO(sbh);
5976 + return (si->bus);
5977 +}
5978 +
5979 +/* return list of found cores */
5980 +uint
5981 +sb_corelist(void *sbh, uint coreid[])
5982 +{
5983 + sb_info_t *si;
5984 +
5985 + si = SB_INFO(sbh);
5986 +
5987 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
5988 + return (si->numcores);
5989 +}
5990 +
5991 +/* return current register mapping */
5992 +void *
5993 +sb_coreregs(void *sbh)
5994 +{
5995 + sb_info_t *si;
5996 +
5997 + si = SB_INFO(sbh);
5998 + ASSERT(GOODREGS(si->curmap));
5999 +
6000 + return (si->curmap);
6001 +}
6002 +
6003 +/* Check if a target abort has happened and clear it */
6004 +bool
6005 +sb_taclear(void *sbh)
6006 +{
6007 + sb_info_t *si;
6008 + bool rc = FALSE;
6009 + sbconfig_t *sb;
6010 +
6011 + si = SB_INFO(sbh);
6012 + sb = REGS2SB(si->curmap);
6013 +
6014 + if (si->bus == PCI_BUS) {
6015 + uint32 stcmd;
6016 +
6017 + stcmd = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd));
6018 + rc = (stcmd & 0x08000000) != 0;
6019 +
6020 + if (rc) {
6021 + /* Target abort bit is set, clear it */
6022 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd), stcmd);
6023 + }
6024 + } else if (si->bus == PCMCIA_BUS) {
6025 + rc = FALSE;
6026 + }
6027 + else if (si->bus == SDIO_BUS) {
6028 + /* due to 4317 A0 HW bug, sdio core wedged on target abort,
6029 + just clear SBSErr bit blindly */
6030 + if (0x0 != R_SBREG(sbh, &sb->sbtmerrlog)) {
6031 + SB_ERROR(("SDIO target abort, clean it"));
6032 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
6033 + }
6034 + rc = FALSE;
6035 + }
6036 +
6037 + return (rc);
6038 +}
6039 +
6040 +/* do buffered registers update */
6041 +void
6042 +sb_commit(void *sbh)
6043 +{
6044 + sb_info_t *si;
6045 + sbpciregs_t *pciregs;
6046 + uint origidx;
6047 + uint intr_val = 0;
6048 +
6049 + si = SB_INFO(sbh);
6050 +
6051 + origidx = si->curidx;
6052 + ASSERT(GOODIDX(origidx));
6053 +
6054 + INTR_OFF(si, intr_val);
6055 + /* switch over to pci core */
6056 + pciregs = (sbpciregs_t*) sb_setcore(sbh, SB_PCI, 0);
6057 +
6058 + /* do the buffer registers update */
6059 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
6060 + W_REG(&pciregs->bcastdata, 0x0);
6061 +
6062 + /* restore core index */
6063 + sb_setcoreidx(sbh, origidx);
6064 + INTR_RESTORE(si, intr_val);
6065 +}
6066 +
6067 +/* reset and re-enable a core */
6068 +void
6069 +sb_core_reset(void *sbh, uint32 bits)
6070 +{
6071 + sb_info_t *si;
6072 + sbconfig_t *sb;
6073 + volatile uint32 dummy;
6074 +
6075 + si = SB_INFO(sbh);
6076 + ASSERT(GOODREGS(si->curmap));
6077 + sb = REGS2SB(si->curmap);
6078 +
6079 + /*
6080 + * Must do the disable sequence first to work for arbitrary current core state.
6081 + */
6082 + sb_core_disable(sbh, bits);
6083 +
6084 + /*
6085 + * Now do the initialization sequence.
6086 + */
6087 +
6088 + /* set reset while enabling the clock and forcing them on throughout the core */
6089 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
6090 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
6091 +
6092 + if (sb_coreid(sbh) == SB_ILINE100) {
6093 + bcm_mdelay(50);
6094 + } else {
6095 + OSL_DELAY(1);
6096 + }
6097 +
6098 + if (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_SERR) {
6099 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
6100 + }
6101 + if ((dummy = R_SBREG(sbh, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
6102 + AND_SBREG(sbh, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
6103 + }
6104 +
6105 + /* clear reset and allow it to propagate throughout the core */
6106 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
6107 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
6108 + OSL_DELAY(1);
6109 +
6110 + /* leave clock enabled */
6111 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | bits));
6112 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
6113 + OSL_DELAY(1);
6114 +}
6115 +
6116 +void
6117 +sb_core_tofixup(void *sbh)
6118 +{
6119 + sb_info_t *si;
6120 + sbconfig_t *sb;
6121 +
6122 + si = SB_INFO(sbh);
6123 +
6124 + if (si->pcirev >= 5)
6125 + return;
6126 +
6127 + ASSERT(GOODREGS(si->curmap));
6128 + sb = REGS2SB(si->curmap);
6129 +
6130 + if (si->bus == SB_BUS) {
6131 + SET_SBREG(sbh, &sb->sbimconfiglow,
6132 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
6133 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
6134 + } else {
6135 + if (sb_coreid(sbh) == SB_PCI) {
6136 + SET_SBREG(sbh, &sb->sbimconfiglow,
6137 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
6138 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
6139 + } else {
6140 + SET_SBREG(sbh, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
6141 + }
6142 + }
6143 +
6144 + sb_commit(sbh);
6145 +}
6146 +
6147 +void
6148 +sb_core_disable(void *sbh, uint32 bits)
6149 +{
6150 + sb_info_t *si;
6151 + volatile uint32 dummy;
6152 + sbconfig_t *sb;
6153 +
6154 + si = SB_INFO(sbh);
6155 +
6156 + ASSERT(GOODREGS(si->curmap));
6157 + sb = REGS2SB(si->curmap);
6158 +
6159 + /* must return if core is already in reset */
6160 + if (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_RESET)
6161 + return;
6162 +
6163 + /* put into reset and return if clocks are not enabled */
6164 + if ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_CLK) == 0)
6165 + goto disable;
6166 +
6167 + /* set the reject bit */
6168 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | SBTML_REJ));
6169 +
6170 + /* spin until reject is set */
6171 + while ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_REJ) == 0)
6172 + OSL_DELAY(1);
6173 +
6174 + /* spin until sbtmstatehigh.busy is clear */
6175 + while (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_BUSY)
6176 + OSL_DELAY(1);
6177 +
6178 + /* set reset and reject while enabling the clocks */
6179 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET));
6180 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
6181 + OSL_DELAY(10);
6182 +
6183 + disable:
6184 + /* leave reset and reject asserted */
6185 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_REJ | SBTML_RESET));
6186 + OSL_DELAY(1);
6187 +}
6188 +
6189 +void
6190 +sb_watchdog(void *sbh, uint ticks)
6191 +{
6192 + sb_info_t *si = SB_INFO(sbh);
6193 +
6194 + /* instant NMI */
6195 + switch (si->gpioid) {
6196 + case SB_CC:
6197 + sb_corereg(sbh, si->gpioidx, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
6198 + break;
6199 + case SB_EXTIF:
6200 + sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
6201 + break;
6202 + }
6203 +}
6204 +
6205 +/* initialize the pcmcia core */
6206 +void
6207 +sb_pcmcia_init(void *sbh)
6208 +{
6209 + sb_info_t *si;
6210 + uint8 cor;
6211 +
6212 + si = SB_INFO(sbh);
6213 +
6214 + /* enable d11 mac interrupts */
6215 + if (si->chip == BCM4301_DEVICE_ID) {
6216 + /* Have to use FCR2 in 4301 */
6217 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
6218 + cor |= COR_IRQEN | COR_FUNEN;
6219 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
6220 + } else {
6221 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
6222 + cor |= COR_IRQEN | COR_FUNEN;
6223 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
6224 + }
6225 +
6226 +}
6227 +
6228 +
6229 +/*
6230 + * Configure the pci core for pci client (NIC) action
6231 + * and get appropriate dma offset value.
6232 + * coremask is the bitvec of cores by index to be enabled.
6233 + */
6234 +void
6235 +sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask)
6236 +{
6237 + sb_info_t *si;
6238 + sbconfig_t *sb;
6239 + sbpciregs_t *pciregs;
6240 + uint32 sbflag;
6241 + uint32 w;
6242 + uint idx;
6243 +
6244 + si = SB_INFO(sbh);
6245 +
6246 + if (dmaoffset)
6247 + *dmaoffset = 0;
6248 +
6249 + /* if not pci bus, we're done */
6250 + if (si->bus != PCI_BUS)
6251 + return;
6252 +
6253 + ASSERT(si->pciidx);
6254 +
6255 + /* get current core index */
6256 + idx = si->curidx;
6257 +
6258 + /* we interrupt on this backplane flag number */
6259 + ASSERT(GOODREGS(si->curmap));
6260 + sb = REGS2SB(si->curmap);
6261 + sbflag = R_SBREG(sbh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
6262 +
6263 + /* switch over to pci core */
6264 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->pciidx);
6265 + sb = REGS2SB(pciregs);
6266 +
6267 + /*
6268 + * Enable sb->pci interrupts. Assume
6269 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
6270 + */
6271 + if (si->pcirev < 6) {
6272 + /* set sbintvec bit for our flag number */
6273 + OR_SBREG(sbh, &sb->sbintvec, (1 << sbflag));
6274 + } else {
6275 + /* pci config write to set this core bit in PCIIntMask */
6276 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
6277 + w |= (coremask << PCI_SBIM_SHIFT);
6278 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
6279 + }
6280 +
6281 + /* enable prefetch and bursts for sonics-to-pci translation 2 */
6282 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
6283 +
6284 + if (si->pcirev < 5) {
6285 + SET_SBREG(sbh, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
6286 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
6287 + sb_commit(sbh);
6288 + }
6289 +
6290 + /* switch back to previous core */
6291 + sb_setcoreidx(sbh, idx);
6292 +
6293 + /* use large sb pci dma window */
6294 + if (dmaoffset)
6295 + *dmaoffset = SB_PCI_DMA;
6296 +}
6297 +
6298 +uint32
6299 +sb_base(uint32 admatch)
6300 +{
6301 + uint32 base;
6302 + uint type;
6303 +
6304 + type = admatch & SBAM_TYPE_MASK;
6305 + ASSERT(type < 3);
6306 +
6307 + base = 0;
6308 +
6309 + if (type == 0) {
6310 + base = admatch & SBAM_BASE0_MASK;
6311 + } else if (type == 1) {
6312 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
6313 + base = admatch & SBAM_BASE1_MASK;
6314 + } else if (type == 2) {
6315 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
6316 + base = admatch & SBAM_BASE2_MASK;
6317 + }
6318 +
6319 + return (base);
6320 +}
6321 +
6322 +uint32
6323 +sb_size(uint32 admatch)
6324 +{
6325 + uint32 size;
6326 + uint type;
6327 +
6328 + type = admatch & SBAM_TYPE_MASK;
6329 + ASSERT(type < 3);
6330 +
6331 + size = 0;
6332 +
6333 + if (type == 0) {
6334 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
6335 + } else if (type == 1) {
6336 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
6337 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
6338 + } else if (type == 2) {
6339 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
6340 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
6341 + }
6342 +
6343 + return (size);
6344 +}
6345 +
6346 +/* return the core-type instantiation # of the current core */
6347 +uint
6348 +sb_coreunit(void *sbh)
6349 +{
6350 + sb_info_t *si;
6351 + uint idx;
6352 + uint coreid;
6353 + uint coreunit;
6354 + uint i;
6355 +
6356 + si = SB_INFO(sbh);
6357 + coreunit = 0;
6358 +
6359 + idx = si->curidx;
6360 +
6361 + ASSERT(GOODREGS(si->curmap));
6362 + coreid = sb_coreid(sbh);
6363 +
6364 + /* count the cores of our type */
6365 + for (i = 0; i < idx; i++)
6366 + if (si->coreid[i] == coreid)
6367 + coreunit++;
6368 +
6369 + return (coreunit);
6370 +}
6371 +
6372 +static INLINE uint32
6373 +factor6(uint32 x)
6374 +{
6375 + switch (x) {
6376 + case CC_F6_2: return 2;
6377 + case CC_F6_3: return 3;
6378 + case CC_F6_4: return 4;
6379 + case CC_F6_5: return 5;
6380 + case CC_F6_6: return 6;
6381 + case CC_F6_7: return 7;
6382 + default: return 0;
6383 + }
6384 +}
6385 +
6386 +/* calculate the speed the SB would run at given a set of clockcontrol values */
6387 +uint32
6388 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
6389 +{
6390 + uint32 n1, n2, clock, m1, m2, m3, mc;
6391 +
6392 + n1 = n & CN_N1_MASK;
6393 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
6394 +
6395 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
6396 + n1 = factor6(n1);
6397 + n2 += CC_F5_BIAS;
6398 + } else if (pll_type == PLL_TYPE2) {
6399 + n1 += CC_T2_BIAS;
6400 + n2 += CC_T2_BIAS;
6401 + ASSERT((n1 >= 2) && (n1 <= 7));
6402 + ASSERT((n2 >= 5) && (n2 <= 23));
6403 + } else if (pll_type == PLL_TYPE3) {
6404 + return (100000000);
6405 + } else
6406 + ASSERT((pll_type >= PLL_TYPE1) && (pll_type <= PLL_TYPE4));
6407 +
6408 + clock = CC_CLOCK_BASE * n1 * n2;
6409 +
6410 + if (clock == 0)
6411 + return 0;
6412 +
6413 + m1 = m & CC_M1_MASK;
6414 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
6415 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
6416 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
6417 +
6418 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
6419 + m1 = factor6(m1);
6420 + if (pll_type == PLL_TYPE1)
6421 + m2 += CC_F5_BIAS;
6422 + else
6423 + m2 = factor6(m2);
6424 + m3 = factor6(m3);
6425 +
6426 + switch (mc) {
6427 + case CC_MC_BYPASS: return (clock);
6428 + case CC_MC_M1: return (clock / m1);
6429 + case CC_MC_M1M2: return (clock / (m1 * m2));
6430 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
6431 + case CC_MC_M1M3: return (clock / (m1 * m3));
6432 + default: return (0);
6433 + }
6434 + } else {
6435 + ASSERT(pll_type == PLL_TYPE2);
6436 +
6437 + m1 += CC_T2_BIAS;
6438 + m2 += CC_T2M2_BIAS;
6439 + m3 += CC_T2_BIAS;
6440 + ASSERT((m1 >= 2) && (m1 <= 7));
6441 + ASSERT((m2 >= 3) && (m2 <= 10));
6442 + ASSERT((m3 >= 2) && (m3 <= 7));
6443 +
6444 + if ((mc & CC_T2MC_M1BYP) == 0)
6445 + clock /= m1;
6446 + if ((mc & CC_T2MC_M2BYP) == 0)
6447 + clock /= m2;
6448 + if ((mc & CC_T2MC_M3BYP) == 0)
6449 + clock /= m3;
6450 +
6451 + return(clock);
6452 + }
6453 +}
6454 +
6455 +/* returns the current speed the SB is running at */
6456 +uint32
6457 +sb_clock(void *sbh)
6458 +{
6459 + sb_info_t *si;
6460 + extifregs_t *eir;
6461 + chipcregs_t *cc;
6462 + uint32 n, m;
6463 + uint idx;
6464 + uint32 pll_type, rate;
6465 + uint intr_val = 0;
6466 +
6467 + si = SB_INFO(sbh);
6468 + idx = si->curidx;
6469 + pll_type = PLL_TYPE1;
6470 +
6471 + INTR_OFF(si, intr_val);
6472 +
6473 + /* switch to extif or chipc core */
6474 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
6475 + n = R_REG(&eir->clockcontrol_n);
6476 + m = R_REG(&eir->clockcontrol_sb);
6477 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
6478 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
6479 + n = R_REG(&cc->clockcontrol_n);
6480 + m = R_REG(&cc->clockcontrol_sb);
6481 + } else {
6482 + INTR_RESTORE(si, intr_val);
6483 + return 0;
6484 + }
6485 +
6486 + /* calculate rate */
6487 + rate = sb_clock_rate(pll_type, n, m);
6488 +
6489 + /* switch back to previous core */
6490 + sb_setcoreidx(sbh, idx);
6491 +
6492 + INTR_RESTORE(si, intr_val);
6493 +
6494 + return rate;
6495 +}
6496 +
6497 +/* change logical "focus" to the gpio core for optimized access */
6498 +void*
6499 +sb_gpiosetcore(void *sbh)
6500 +{
6501 + sb_info_t *si;
6502 +
6503 + si = SB_INFO(sbh);
6504 +
6505 + return (sb_setcoreidx(sbh, si->gpioidx));
6506 +}
6507 +
6508 +/* mask&set gpiocontrol bits */
6509 +uint32
6510 +sb_gpiocontrol(void *sbh, uint32 mask, uint32 val)
6511 +{
6512 + sb_info_t *si;
6513 + uint regoff;
6514 +
6515 + si = SB_INFO(sbh);
6516 + regoff = 0;
6517 +
6518 + switch (si->gpioid) {
6519 + case SB_CC:
6520 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
6521 + break;
6522 +
6523 + case SB_PCI:
6524 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
6525 + break;
6526 +
6527 + case SB_EXTIF:
6528 + return (0);
6529 + }
6530 +
6531 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
6532 +}
6533 +
6534 +/* mask&set gpio output enable bits */
6535 +uint32
6536 +sb_gpioouten(void *sbh, uint32 mask, uint32 val)
6537 +{
6538 + sb_info_t *si;
6539 + uint regoff;
6540 +
6541 + si = SB_INFO(sbh);
6542 + regoff = 0;
6543 +
6544 + switch (si->gpioid) {
6545 + case SB_CC:
6546 + regoff = OFFSETOF(chipcregs_t, gpioouten);
6547 + break;
6548 +
6549 + case SB_PCI:
6550 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
6551 + break;
6552 +
6553 + case SB_EXTIF:
6554 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
6555 + break;
6556 + }
6557 +
6558 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
6559 +}
6560 +
6561 +/* mask&set gpio output bits */
6562 +uint32
6563 +sb_gpioout(void *sbh, uint32 mask, uint32 val)
6564 +{
6565 + sb_info_t *si;
6566 + uint regoff;
6567 +
6568 + si = SB_INFO(sbh);
6569 + regoff = 0;
6570 +
6571 + switch (si->gpioid) {
6572 + case SB_CC:
6573 + regoff = OFFSETOF(chipcregs_t, gpioout);
6574 + break;
6575 +
6576 + case SB_PCI:
6577 + regoff = OFFSETOF(sbpciregs_t, gpioout);
6578 + break;
6579 +
6580 + case SB_EXTIF:
6581 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
6582 + break;
6583 + }
6584 +
6585 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
6586 +}
6587 +
6588 +/* return the current gpioin register value */
6589 +uint32
6590 +sb_gpioin(void *sbh)
6591 +{
6592 + sb_info_t *si;
6593 + uint regoff;
6594 +
6595 + si = SB_INFO(sbh);
6596 + regoff = 0;
6597 +
6598 + switch (si->gpioid) {
6599 + case SB_CC:
6600 + regoff = OFFSETOF(chipcregs_t, gpioin);
6601 + break;
6602 +
6603 + case SB_PCI:
6604 + regoff = OFFSETOF(sbpciregs_t, gpioin);
6605 + break;
6606 +
6607 + case SB_EXTIF:
6608 + regoff = OFFSETOF(extifregs_t, gpioin);
6609 + break;
6610 + }
6611 +
6612 + return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0));
6613 +}
6614 +
6615 +/* mask&set gpio interrupt polarity bits */
6616 +uint32
6617 +sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val)
6618 +{
6619 + sb_info_t *si;
6620 + uint regoff;
6621 +
6622 + si = SB_INFO(sbh);
6623 + regoff = 0;
6624 +
6625 + switch (si->gpioid) {
6626 + case SB_CC:
6627 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
6628 + break;
6629 +
6630 + case SB_PCI:
6631 + /* pci gpio implementation does not support interrupt polarity */
6632 + ASSERT(0);
6633 + break;
6634 +
6635 + case SB_EXTIF:
6636 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
6637 + break;
6638 + }
6639 +
6640 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
6641 +}
6642 +
6643 +/* mask&set gpio interrupt mask bits */
6644 +uint32
6645 +sb_gpiointmask(void *sbh, uint32 mask, uint32 val)
6646 +{
6647 + sb_info_t *si;
6648 + uint regoff;
6649 +
6650 + si = SB_INFO(sbh);
6651 + regoff = 0;
6652 +
6653 + switch (si->gpioid) {
6654 + case SB_CC:
6655 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
6656 + break;
6657 +
6658 + case SB_PCI:
6659 + /* pci gpio implementation does not support interrupt mask */
6660 + ASSERT(0);
6661 + break;
6662 +
6663 + case SB_EXTIF:
6664 + regoff = OFFSETOF(extifregs_t, gpiointmask);
6665 + break;
6666 + }
6667 +
6668 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
6669 +}
6670 +
6671 +
6672 +/*
6673 + * Return the slowclock min or max frequency.
6674 + * Three sources of SLOW CLOCK:
6675 + * 1. On Chip LPO - 32khz or 160khz
6676 + * 2. On Chip Xtal OSC - 20mhz/4*(divider+1)
6677 + * 3. External PCI clock - 66mhz/4*(divider+1)
6678 + */
6679 +static uint
6680 +slowfreq(void *sbh, bool max)
6681 +{
6682 + sb_info_t *si;
6683 + chipcregs_t *cc;
6684 + uint32 v;
6685 + uint div;
6686 +
6687 + si = SB_INFO(sbh);
6688 +
6689 + ASSERT(sb_coreid(sbh) == SB_CC);
6690 +
6691 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
6692 +
6693 + /* shouldn't be here unless we've established the chip has dynamic power control */
6694 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
6695 +
6696 + if (si->ccrev < 6) {
6697 + v = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
6698 +
6699 + if (v & PCI_CFG_GPIO_SCS)
6700 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
6701 + else
6702 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
6703 + } else {
6704 + v = R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
6705 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
6706 + if (v == SCC_SS_LPO)
6707 + return (max? LPOMAXFREQ : LPOMINFREQ);
6708 + else if (v == SCC_SS_XTAL)
6709 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
6710 + else if (v == SCC_SS_PCI)
6711 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
6712 + else
6713 + ASSERT(0);
6714 + }
6715 + return (0);
6716 +}
6717 +
6718 +/* initialize power control delay registers */
6719 +void
6720 +sb_pwrctl_init(void *sbh)
6721 +{
6722 + sb_info_t *si;
6723 + uint origidx;
6724 + chipcregs_t *cc;
6725 + uint slowmaxfreq;
6726 + uint pll_on_delay, fref_sel_delay;
6727 +
6728 + si = SB_INFO(sbh);
6729 +
6730 + if (si->bus == SB_BUS)
6731 + return;
6732 +
6733 + origidx = si->curidx;
6734 +
6735 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
6736 + return;
6737 +
6738 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
6739 + goto done;
6740 +
6741 + slowmaxfreq = slowfreq(sbh, TRUE);
6742 + pll_on_delay = ((slowmaxfreq * PLL_DELAY) + 999999) / 1000000;
6743 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
6744 +
6745 + W_REG(&cc->pll_on_delay, pll_on_delay);
6746 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
6747 +
6748 + /* 4317pc does not work with SlowClock less than 5Mhz */
6749 + if (si->bus == PCMCIA_BUS)
6750 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (0 << SCC_CD_SHF));
6751 +
6752 +done:
6753 + sb_setcoreidx(sbh, origidx);
6754 +}
6755 +
6756 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
6757 +uint16
6758 +sb_pwrctl_fast_pwrup_delay(void *sbh)
6759 +{
6760 + sb_info_t *si;
6761 + uint origidx;
6762 + chipcregs_t *cc;
6763 + uint slowminfreq;
6764 + uint16 fpdelay;
6765 + uint intr_val = 0;
6766 +
6767 + si = SB_INFO(sbh);
6768 + fpdelay = 0;
6769 + origidx = si->curidx;
6770 +
6771 + if (si->bus == SB_BUS)
6772 + goto done;
6773 +
6774 + INTR_OFF(si, intr_val);
6775 +
6776 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
6777 + goto done;
6778 +
6779 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
6780 + goto done;
6781 +
6782 + slowminfreq = slowfreq(sbh, FALSE);
6783 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
6784 +
6785 +done:
6786 + sb_setcoreidx(sbh, origidx);
6787 + INTR_RESTORE(si, intr_val);
6788 + return (fpdelay);
6789 +}
6790 +
6791 +/* turn primary xtal and/or pll off/on */
6792 +int
6793 +sb_pwrctl_xtal(void *sbh, uint what, bool on)
6794 +{
6795 + sb_info_t *si;
6796 + uint32 in, out, outen;
6797 +
6798 + si = SB_INFO(sbh);
6799 +
6800 +
6801 + if (si->bus == PCMCIA_BUS) {
6802 + return (0);
6803 + }
6804 +
6805 + if (si->bus != PCI_BUS)
6806 + return (-1);
6807 +
6808 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
6809 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
6810 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
6811 +
6812 + /*
6813 + * We can't actually read the state of the PLLPD so we infer it
6814 + * by the value of XTAL_PU which *is* readable via gpioin.
6815 + */
6816 + if (on && (in & PCI_CFG_GPIO_XTAL))
6817 + return (0);
6818 +
6819 + if (what & XTAL)
6820 + outen |= PCI_CFG_GPIO_XTAL;
6821 + if (what & PLL)
6822 + outen |= PCI_CFG_GPIO_PLL;
6823 +
6824 + if (on) {
6825 + /* turn primary xtal on */
6826 + if (what & XTAL) {
6827 + out |= PCI_CFG_GPIO_XTAL;
6828 + if (what & PLL)
6829 + out |= PCI_CFG_GPIO_PLL;
6830 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
6831 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
6832 + OSL_DELAY(200);
6833 + }
6834 +
6835 + /* turn pll on */
6836 + if (what & PLL) {
6837 + out &= ~PCI_CFG_GPIO_PLL;
6838 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
6839 + OSL_DELAY(2000);
6840 + }
6841 + } else {
6842 + if (what & XTAL)
6843 + out &= ~PCI_CFG_GPIO_XTAL;
6844 + if (what & PLL)
6845 + out |= PCI_CFG_GPIO_PLL;
6846 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
6847 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
6848 + }
6849 +
6850 + return (0);
6851 +}
6852 +
6853 +/* set dynamic power control mode (forceslow, forcefast, dynamic) */
6854 +/* returns true if ignore pll off is set and false if it is not */
6855 +bool
6856 +sb_pwrctl_clk(void *sbh, uint mode)
6857 +{
6858 + sb_info_t *si;
6859 + uint origidx;
6860 + chipcregs_t *cc;
6861 + uint32 scc;
6862 + bool forcefastclk=FALSE;
6863 + uint intr_val = 0;
6864 +
6865 + si = SB_INFO(sbh);
6866 +
6867 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
6868 + if (si->ccrev < 6)
6869 + return (FALSE);
6870 +
6871 + INTR_OFF(si, intr_val);
6872 +
6873 + origidx = si->curidx;
6874 +
6875 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
6876 + ASSERT(cc != NULL);
6877 +
6878 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
6879 + goto done;
6880 +
6881 + switch (mode) {
6882 + case CLK_FAST: /* force fast (pll) clock */
6883 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
6884 + sb_pwrctl_xtal(sbh, XTAL, ON);
6885 +
6886 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
6887 + break;
6888 +
6889 + case CLK_SLOW: /* force slow clock */
6890 + if ((si->bus == SDIO_BUS) || (si->bus == PCMCIA_BUS))
6891 + return (-1);
6892 +
6893 + if (si->ccrev >= 6)
6894 + OR_REG(&cc->slow_clk_ctl, SCC_FS);
6895 + break;
6896 +
6897 + case CLK_DYNAMIC: /* enable dynamic power control */
6898 + scc = R_REG(&cc->slow_clk_ctl);
6899 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
6900 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
6901 + scc |= SCC_XC;
6902 + W_REG(&cc->slow_clk_ctl, scc);
6903 +
6904 + /* for dynamic control, we have to release our xtal_pu "force on" */
6905 + if (scc & SCC_XC)
6906 + sb_pwrctl_xtal(sbh, XTAL, OFF);
6907 + break;
6908 + }
6909 +
6910 + /* Is the h/w forcing the use of the fast clk */
6911 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
6912 +
6913 +done:
6914 + sb_setcoreidx(sbh, origidx);
6915 + INTR_RESTORE(si, intr_val);
6916 + return (forcefastclk);
6917 +}
6918 +
6919 +/* register driver interrupt disabling and restoring callback functions */
6920 +void
6921 +sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg)
6922 +{
6923 + sb_info_t *si;
6924 +
6925 + si = SB_INFO(sbh);
6926 + si->intr_arg = intr_arg;
6927 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
6928 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
6929 + /* save current core id. when this function called, the current core
6930 + * must be the core which provides driver functions(il, et, wl, etc.)
6931 + */
6932 + si->dev_coreid = si->coreid[si->curidx];
6933 +}
6934 +
6935 +
6936 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcm4710.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcm4710.h
6937 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
6938 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcm4710.h 2005-12-13 14:59:52.000000000 +0100
6939 @@ -0,0 +1,90 @@
6940 +/*
6941 + * BCM4710 address space map and definitions
6942 + * Think twice before adding to this file, this is not the kitchen sink
6943 + * These definitions are not guaranteed for all 47xx chips, only the 4710
6944 + *
6945 + * Copyright 2001-2003, Broadcom Corporation
6946 + * All Rights Reserved.
6947 + *
6948 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6949 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6950 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6951 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6952 + * $Id$
6953 + */
6954 +
6955 +#ifndef _bcm4710_h_
6956 +#define _bcm4710_h_
6957 +
6958 +/* Address map */
6959 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
6960 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
6961 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
6962 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
6963 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6964 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
6965 +
6966 +/* Core register space */
6967 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
6968 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
6969 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
6970 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
6971 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
6972 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
6973 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
6974 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
6975 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
6976 +
6977 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
6978 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
6979 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
6980 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
6981 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
6982 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
6983 +
6984 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6985 +
6986 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
6987 +
6988 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
6989 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
6990 +
6991 +#define SBFLAG_PCI 0
6992 +#define SBFLAG_ENET0 1
6993 +#define SBFLAG_ILINE20 2
6994 +#define SBFLAG_CODEC 3
6995 +#define SBFLAG_USB 4
6996 +#define SBFLAG_EXTIF 5
6997 +#define SBFLAG_ENET1 6
6998 +
6999 +#ifdef CONFIG_HWSIM
7000 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
7001 +#else
7002 +#define BCM4710_TRACE(trval)
7003 +#endif
7004 +
7005 +
7006 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
7007 +
7008 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
7009 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
7010 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
7011 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
7012 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
7013 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
7014 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
7015 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
7016 +
7017 +#define LED_REG(x) \
7018 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
7019 +
7020 +/*
7021 + * Reset function implemented in PLD. Read or write should trigger hard reset
7022 + */
7023 +#define SYS_HARD_RESET() \
7024 + { for (;;) \
7025 + *( (volatile unsigned char *)\
7026 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
7027 + }
7028 +
7029 +#endif /* _bcm4710_h_ */
7030 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmdevs.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmdevs.h
7031 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
7032 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-13 14:59:52.000000000 +0100
7033 @@ -0,0 +1,238 @@
7034 +/*
7035 + * Broadcom device-specific manifest constants.
7036 + *
7037 + * $Id$
7038 + * Copyright 2001-2003, Broadcom Corporation
7039 + * All Rights Reserved.
7040 + *
7041 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7042 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7043 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7044 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7045 + */
7046 +
7047 +#ifndef _BCMDEVS_H
7048 +#define _BCMDEVS_H
7049 +
7050 +
7051 +/* Known PCI vendor Id's */
7052 +#define VENDOR_EPIGRAM 0xfeda
7053 +#define VENDOR_BROADCOM 0x14e4
7054 +#define VENDOR_3COM 0x10b7
7055 +#define VENDOR_NETGEAR 0x1385
7056 +#define VENDOR_DIAMOND 0x1092
7057 +#define VENDOR_DELL 0x1028
7058 +#define VENDOR_HP 0x0e11
7059 +#define VENDOR_APPLE 0x106b
7060 +
7061 +/* PCI Device Id's */
7062 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
7063 +#define BCM4211_DEVICE_ID 0x4211
7064 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
7065 +#define BCM4231_DEVICE_ID 0x4231
7066 +
7067 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
7068 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
7069 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
7070 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
7071 +
7072 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
7073 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
7074 +
7075 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
7076 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
7077 +
7078 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
7079 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
7080 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
7081 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
7082 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
7083 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
7084 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
7085 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
7086 +
7087 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
7088 +
7089 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
7090 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
7091 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
7092 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
7093 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
7094 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
7095 +
7096 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
7097 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
7098 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
7099 +
7100 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
7101 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
7102 +
7103 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
7104 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
7105 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
7106 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
7107 +
7108 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
7109 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
7110 +#define BCM4306_D11G_ID2 0x4325
7111 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
7112 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
7113 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
7114 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
7115 +
7116 +#define BCM4309_PKG_ID 1 /* 4309 package id */
7117 +
7118 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
7119 +#define BCM4303_PKG_ID 2 /* 4303 package id */
7120 +
7121 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
7122 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
7123 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
7124 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
7125 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
7126 +
7127 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
7128 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
7129 +
7130 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
7131 +
7132 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
7133 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
7134 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
7135 +
7136 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
7137 +
7138 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
7139 +
7140 +
7141 +/* PCMCIA vendor Id's */
7142 +
7143 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
7144 +
7145 +/* SDIO vendor Id's */
7146 +#define VENDOR_BROADCOM_SDIO 0x00BF
7147 +
7148 +
7149 +/* boardflags */
7150 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
7151 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
7152 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
7153 +#define BFL_ENETSPI 0x0010 /* This board has ephy roboswitch spi */
7154 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
7155 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
7156 +#define BFL_ENETVLAN 0x0100 /* This board can do vlan */
7157 +
7158 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
7159 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
7160 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
7161 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
7162 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
7163 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
7164 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
7165 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
7166 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
7167 +
7168 +/* Bus types */
7169 +#define SB_BUS 0 /* Silicon Backplane */
7170 +#define PCI_BUS 1 /* PCI target */
7171 +#define PCMCIA_BUS 2 /* PCMCIA target */
7172 +#define SDIO_BUS 3 /* SDIO target */
7173 +
7174 +/* Reference Board Types */
7175 +
7176 +#define BU4710_BOARD 0x0400
7177 +#define VSIM4710_BOARD 0x0401
7178 +#define QT4710_BOARD 0x0402
7179 +
7180 +#define BU4610_BOARD 0x0403
7181 +#define VSIM4610_BOARD 0x0404
7182 +
7183 +#define BU4307_BOARD 0x0405
7184 +#define BCM94301CB_BOARD 0x0406
7185 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
7186 +#define BCM94301MP_BOARD 0x0407
7187 +#define BCM94307MP_BOARD 0x0408
7188 +#define BCMAP4307_BOARD 0x0409
7189 +
7190 +#define BU4309_BOARD 0x040a
7191 +#define BCM94309CB_BOARD 0x040b
7192 +#define BCM94309MP_BOARD 0x040c
7193 +#define BCM4309AP_BOARD 0x040d
7194 +
7195 +#define BCM94302MP_BOARD 0x040e
7196 +
7197 +#define VSIM4310_BOARD 0x040f
7198 +#define BU4711_BOARD 0x0410
7199 +#define BCM94310U_BOARD 0x0411
7200 +#define BCM94310AP_BOARD 0x0412
7201 +#define BCM94310MP_BOARD 0x0414
7202 +
7203 +#define BU4306_BOARD 0x0416
7204 +#define BCM94306CB_BOARD 0x0417
7205 +#define BCM94306MP_BOARD 0x0418
7206 +
7207 +#define BCM94710D_BOARD 0x041a
7208 +#define BCM94710R1_BOARD 0x041b
7209 +#define BCM94710R4_BOARD 0x041c
7210 +#define BCM94710AP_BOARD 0x041d
7211 +
7212 +
7213 +#define BU2050_BOARD 0x041f
7214 +
7215 +
7216 +#define BCM94309G_BOARD 0x0421
7217 +
7218 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
7219 +
7220 +#define BU4704_BOARD 0x0423
7221 +#define BU4702_BOARD 0x0424
7222 +
7223 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
7224 +
7225 +#define BU4317_BOARD 0x0426
7226 +
7227 +
7228 +#define BCM94702MN_BOARD 0x0428
7229 +
7230 +/* BCM4702 1U CompactPCI Board */
7231 +#define BCM94702CPCI_BOARD 0x0429
7232 +
7233 +/* BCM4702 with BCM95380 VLAN Router */
7234 +#define BCM95380RR_BOARD 0x042a
7235 +
7236 +/* cb4306 with SiGe PA */
7237 +#define BCM94306CBSG_BOARD 0x042b
7238 +
7239 +/* mp4301 with 2050 radio */
7240 +#define BCM94301MPL_BOARD 0x042c
7241 +
7242 +/* cb4306 with SiGe PA */
7243 +#define PCSG94306_BOARD 0x042d
7244 +
7245 +/* bu4704 with sdram */
7246 +#define BU4704SD_BOARD 0x042e
7247 +
7248 +/* Dual 11a/11g Router */
7249 +#define BCM94704AGR_BOARD 0x042f
7250 +
7251 +/* 11a-only minipci */
7252 +#define BCM94308MP_BOARD 0x0430
7253 +
7254 +
7255 +
7256 +/* BCM94317 boards */
7257 +#define BCM94317CB_BOARD 0x0440
7258 +#define BCM94317MP_BOARD 0x0441
7259 +#define BCM94317PCMCIA_BOARD 0x0442
7260 +#define BCM94317SDIO_BOARD 0x0443
7261 +
7262 +#define BU4712_BOARD 0x0444
7263 +
7264 +/* BCM4712 boards */
7265 +#define BCM94712AGR_BOARD 0x0445
7266 +#define BCM94712AP_BOARD 0x0446
7267 +
7268 +/* BCM4702 boards */
7269 +#define CT4702AP_BOARD 0x0447
7270 +
7271 +#endif /* _BCMDEVS_H */
7272 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmendian.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmendian.h
7273 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
7274 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmendian.h 2005-12-13 14:59:52.000000000 +0100
7275 @@ -0,0 +1,125 @@
7276 +/*******************************************************************************
7277 + * $Id$
7278 + * Copyright 2001-2003, Broadcom Corporation
7279 + * All Rights Reserved.
7280 + *
7281 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7282 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7283 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7284 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7285 + * local version of endian.h - byte order defines
7286 + ******************************************************************************/
7287 +
7288 +#ifndef _BCMENDIAN_H_
7289 +#define _BCMENDIAN_H_
7290 +
7291 +#include <typedefs.h>
7292 +
7293 +/* Byte swap a 16 bit value */
7294 +#define BCMSWAP16(val) \
7295 + ((uint16)( \
7296 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
7297 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
7298 +
7299 +/* Byte swap a 32 bit value */
7300 +#define BCMSWAP32(val) \
7301 + ((uint32)( \
7302 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
7303 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
7304 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
7305 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
7306 +
7307 +static INLINE uint16
7308 +bcmswap16(uint16 val)
7309 +{
7310 + return BCMSWAP16(val);
7311 +}
7312 +
7313 +static INLINE uint32
7314 +bcmswap32(uint32 val)
7315 +{
7316 + return BCMSWAP32(val);
7317 +}
7318 +
7319 +/* buf - start of buffer of shorts to swap */
7320 +/* len - byte length of buffer */
7321 +static INLINE void
7322 +bcmswap16_buf(uint16 *buf, uint len)
7323 +{
7324 + len = len/2;
7325 +
7326 + while(len--){
7327 + *buf = bcmswap16(*buf);
7328 + buf++;
7329 + }
7330 +}
7331 +
7332 +#ifndef hton16
7333 +#ifndef IL_BIGENDIAN
7334 +#define HTON16(i) BCMSWAP16(i)
7335 +#define hton16(i) bcmswap16(i)
7336 +#define hton32(i) bcmswap32(i)
7337 +#define ntoh16(i) bcmswap16(i)
7338 +#define ntoh32(i) bcmswap32(i)
7339 +#define ltoh16(i) (i)
7340 +#define ltoh32(i) (i)
7341 +#define htol16(i) (i)
7342 +#define htol32(i) (i)
7343 +#else
7344 +#define HTON16(i) (i)
7345 +#define hton16(i) (i)
7346 +#define hton32(i) (i)
7347 +#define ntoh16(i) (i)
7348 +#define ntoh32(i) (i)
7349 +#define ltoh16(i) bcmswap16(i)
7350 +#define ltoh32(i) bcmswap32(i)
7351 +#define htol16(i) bcmswap16(i)
7352 +#define htol32(i) bcmswap32(i)
7353 +#endif
7354 +#endif
7355 +
7356 +#ifndef IL_BIGENDIAN
7357 +#define ltoh16_buf(buf, i)
7358 +#define htol16_buf(buf, i)
7359 +#else
7360 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
7361 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
7362 +#endif
7363 +
7364 +/*
7365 +* load 16-bit value from unaligned little endian byte array.
7366 +*/
7367 +static INLINE uint16
7368 +ltoh16_ua(uint8 *bytes)
7369 +{
7370 + return (bytes[1]<<8)+bytes[0];
7371 +}
7372 +
7373 +/*
7374 +* load 32-bit value from unaligned little endian byte array.
7375 +*/
7376 +static INLINE uint32
7377 +ltoh32_ua(uint8 *bytes)
7378 +{
7379 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
7380 +}
7381 +
7382 +/*
7383 +* load 16-bit value from unaligned big(network) endian byte array.
7384 +*/
7385 +static INLINE uint16
7386 +ntoh16_ua(uint8 *bytes)
7387 +{
7388 + return (bytes[0]<<8)+bytes[1];
7389 +}
7390 +
7391 +/*
7392 +* load 32-bit value from unaligned big(network) endian byte array.
7393 +*/
7394 +static INLINE uint32
7395 +ntoh32_ua(uint8 *bytes)
7396 +{
7397 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
7398 +}
7399 +
7400 +#endif /* _BCMENDIAN_H_ */
7401 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenet47xx.h
7402 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
7403 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-12-13 14:59:52.000000000 +0100
7404 @@ -0,0 +1,229 @@
7405 +/*
7406 + * Hardware-specific definitions for
7407 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
7408 + *
7409 + * Copyright 2001-2003, Broadcom Corporation
7410 + * All Rights Reserved.
7411 + *
7412 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7413 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7414 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7415 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7416 + * $Id$
7417 + */
7418 +
7419 +#ifndef _bcmenet_47xx_h_
7420 +#define _bcmenet_47xx_h_
7421 +
7422 +#include <bcmdevs.h>
7423 +#include <hnddma.h>
7424 +
7425 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
7426 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
7427 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
7428 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
7429 +
7430 +/* power management event wakeup pattern constants */
7431 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
7432 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
7433 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
7434 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
7435 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
7436 +
7437 +/* cpp contortions to concatenate w/arg prescan */
7438 +#ifndef PAD
7439 +#define _PADLINE(line) pad ## line
7440 +#define _XSTR(line) _PADLINE(line)
7441 +#define PAD _XSTR(__LINE__)
7442 +#endif /* PAD */
7443 +
7444 +/* sometimes you just need the enet mib definitions */
7445 +#include <bcmenetmib.h>
7446 +
7447 +/*
7448 + * Host Interface Registers
7449 + */
7450 +typedef volatile struct _bcmenettregs {
7451 + /* Device and Power Control */
7452 + uint32 devcontrol;
7453 + uint32 PAD[2];
7454 + uint32 biststatus;
7455 + uint32 wakeuplength;
7456 + uint32 PAD[3];
7457 +
7458 + /* Interrupt Control */
7459 + uint32 intstatus;
7460 + uint32 intmask;
7461 + uint32 gptimer;
7462 + uint32 PAD[23];
7463 +
7464 + /* Ethernet MAC Address Filtering Control */
7465 + uint32 PAD[2];
7466 + uint32 enetftaddr;
7467 + uint32 enetftdata;
7468 + uint32 PAD[2];
7469 +
7470 + /* Ethernet MAC Control */
7471 + uint32 emactxmaxburstlen;
7472 + uint32 emacrxmaxburstlen;
7473 + uint32 emaccontrol;
7474 + uint32 emacflowcontrol;
7475 +
7476 + uint32 PAD[20];
7477 +
7478 + /* DMA Lazy Interrupt Control */
7479 + uint32 intrecvlazy;
7480 + uint32 PAD[63];
7481 +
7482 + /* DMA engine */
7483 + dmaregs_t dmaregs;
7484 + dmafifo_t dmafifo;
7485 + uint32 PAD[116];
7486 +
7487 + /* EMAC Registers */
7488 + uint32 rxconfig;
7489 + uint32 rxmaxlength;
7490 + uint32 txmaxlength;
7491 + uint32 PAD;
7492 + uint32 mdiocontrol;
7493 + uint32 mdiodata;
7494 + uint32 emacintmask;
7495 + uint32 emacintstatus;
7496 + uint32 camdatalo;
7497 + uint32 camdatahi;
7498 + uint32 camcontrol;
7499 + uint32 enetcontrol;
7500 + uint32 txcontrol;
7501 + uint32 txwatermark;
7502 + uint32 mibcontrol;
7503 + uint32 PAD[49];
7504 +
7505 + /* EMAC MIB counters */
7506 + bcmenetmib_t mib;
7507 +
7508 + uint32 PAD[585];
7509 +
7510 + /* Sonics SiliconBackplane config registers */
7511 + sbconfig_t sbconfig;
7512 +} bcmenetregs_t;
7513 +
7514 +/* device control */
7515 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
7516 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
7517 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
7518 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
7519 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
7520 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
7521 +#define DC_PA_SHIFT 18
7522 +
7523 +/* wakeup length */
7524 +#define WL_P0_MASK 0x7f /* pattern 0 */
7525 +#define WL_D0 ((uint32)1 << 7)
7526 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
7527 +#define WL_P1_SHIFT 8
7528 +#define WL_D1 ((uint32)1 << 15)
7529 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
7530 +#define WL_P2_SHIFT 16
7531 +#define WL_D2 ((uint32)1 << 23)
7532 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
7533 +#define WL_P3_SHIFT 24
7534 +#define WL_D3 ((uint32)1 << 31)
7535 +
7536 +/* intstatus and intmask */
7537 +#define I_PME ((uint32)1 << 6) /* power management event */
7538 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
7539 +#define I_PC ((uint32)1 << 10) /* descriptor error */
7540 +#define I_PD ((uint32)1 << 11) /* data error */
7541 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
7542 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
7543 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
7544 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
7545 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
7546 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
7547 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
7548 +#define I_MW ((uint32)1 << 27) /* mii write */
7549 +#define I_MR ((uint32)1 << 28) /* mii read */
7550 +
7551 +/* emaccontrol */
7552 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
7553 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
7554 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
7555 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
7556 +#define EMC_LC_SHIFT 5
7557 +
7558 +/* emacflowcontrol */
7559 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
7560 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
7561 +
7562 +/* interrupt receive lazy */
7563 +#define IRL_TO_MASK 0x00ffffff /* timeout */
7564 +#define IRL_FC_MASK 0xff000000 /* frame count */
7565 +#define IRL_FC_SHIFT 24 /* frame count */
7566 +
7567 +/* emac receive config */
7568 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
7569 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
7570 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
7571 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
7572 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
7573 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
7574 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
7575 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
7576 +
7577 +/* emac mdio control */
7578 +#define MC_MF_MASK 0x7f /* mdc frequency */
7579 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
7580 +
7581 +/* emac mdio data */
7582 +#define MD_DATA_MASK 0xffff /* r/w data */
7583 +#define MD_TA_MASK 0x30000 /* turnaround value */
7584 +#define MD_TA_SHIFT 16
7585 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
7586 +#define MD_RA_MASK 0x7c0000 /* register address */
7587 +#define MD_RA_SHIFT 18
7588 +#define MD_PMD_MASK 0xf800000 /* physical media device */
7589 +#define MD_PMD_SHIFT 23
7590 +#define MD_OP_MASK 0x30000000 /* opcode */
7591 +#define MD_OP_SHIFT 28
7592 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
7593 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
7594 +#define MD_SB_MASK 0xc0000000 /* start bits */
7595 +#define MD_SB_SHIFT 30
7596 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
7597 +
7598 +/* emac intstatus and intmask */
7599 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
7600 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
7601 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
7602 +
7603 +/* emac cam data high */
7604 +#define CD_V ((uint32)1 << 16) /* valid bit */
7605 +
7606 +/* emac cam control */
7607 +#define CC_CE ((uint32)1 << 0) /* cam enable */
7608 +#define CC_MS ((uint32)1 << 1) /* mask select */
7609 +#define CC_RD ((uint32)1 << 2) /* read */
7610 +#define CC_WR ((uint32)1 << 3) /* write */
7611 +#define CC_INDEX_MASK 0x3f0000 /* index */
7612 +#define CC_INDEX_SHIFT 16
7613 +#define CC_CB ((uint32)1 << 31) /* cam busy */
7614 +
7615 +/* emac ethernet control */
7616 +#define EC_EE ((uint32)1 << 0) /* emac enable */
7617 +#define EC_ED ((uint32)1 << 1) /* emac disable */
7618 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
7619 +#define EC_EP ((uint32)1 << 3) /* external phy select */
7620 +
7621 +/* emac transmit control */
7622 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
7623 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
7624 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
7625 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
7626 +
7627 +/* emac mib control */
7628 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
7629 +
7630 +/* sometimes you just need the enet rxheader definitions */
7631 +#include <bcmenetrxh.h>
7632 +
7633 +#endif /* _bcmenet_47xx_h_ */
7634 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenetmib.h
7635 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
7636 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenetmib.h 2005-12-13 14:59:52.000000000 +0100
7637 @@ -0,0 +1,81 @@
7638 +/*
7639 + * Hardware-specific MIB definition for
7640 + * Broadcom Home Networking Division
7641 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
7642 + *
7643 + * Copyright 2001-2003, Broadcom Corporation
7644 + * All Rights Reserved.
7645 + *
7646 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7647 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7648 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7649 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7650 + * $Id$
7651 + */
7652 +
7653 +#ifndef _bcmenetmib_h_
7654 +#define _bcmenetmib_h_
7655 +
7656 +/* cpp contortions to concatenate w/arg prescan */
7657 +#ifndef PAD
7658 +#define _PADLINE(line) pad ## line
7659 +#define _XSTR(line) _PADLINE(line)
7660 +#define PAD _XSTR(__LINE__)
7661 +#endif /* PAD */
7662 +
7663 +/*
7664 + * EMAC MIB Registers
7665 + */
7666 +typedef volatile struct {
7667 + uint32 tx_good_octets;
7668 + uint32 tx_good_pkts;
7669 + uint32 tx_octets;
7670 + uint32 tx_pkts;
7671 + uint32 tx_broadcast_pkts;
7672 + uint32 tx_multicast_pkts;
7673 + uint32 tx_len_64;
7674 + uint32 tx_len_65_to_127;
7675 + uint32 tx_len_128_to_255;
7676 + uint32 tx_len_256_to_511;
7677 + uint32 tx_len_512_to_1023;
7678 + uint32 tx_len_1024_to_max;
7679 + uint32 tx_jabber_pkts;
7680 + uint32 tx_oversize_pkts;
7681 + uint32 tx_fragment_pkts;
7682 + uint32 tx_underruns;
7683 + uint32 tx_total_cols;
7684 + uint32 tx_single_cols;
7685 + uint32 tx_multiple_cols;
7686 + uint32 tx_excessive_cols;
7687 + uint32 tx_late_cols;
7688 + uint32 tx_defered;
7689 + uint32 tx_carrier_lost;
7690 + uint32 tx_pause_pkts;
7691 + uint32 PAD[8];
7692 +
7693 + uint32 rx_good_octets;
7694 + uint32 rx_good_pkts;
7695 + uint32 rx_octets;
7696 + uint32 rx_pkts;
7697 + uint32 rx_broadcast_pkts;
7698 + uint32 rx_multicast_pkts;
7699 + uint32 rx_len_64;
7700 + uint32 rx_len_65_to_127;
7701 + uint32 rx_len_128_to_255;
7702 + uint32 rx_len_256_to_511;
7703 + uint32 rx_len_512_to_1023;
7704 + uint32 rx_len_1024_to_max;
7705 + uint32 rx_jabber_pkts;
7706 + uint32 rx_oversize_pkts;
7707 + uint32 rx_fragment_pkts;
7708 + uint32 rx_missed_pkts;
7709 + uint32 rx_crc_align_errs;
7710 + uint32 rx_undersize;
7711 + uint32 rx_crc_errs;
7712 + uint32 rx_align_errs;
7713 + uint32 rx_symbol_errs;
7714 + uint32 rx_pause_pkts;
7715 + uint32 rx_nonpause_pkts;
7716 +} bcmenetmib_t;
7717 +
7718 +#endif /* _bcmenetmib_h_ */
7719 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenetrxh.h
7720 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
7721 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-12-13 14:59:52.000000000 +0100
7722 @@ -0,0 +1,43 @@
7723 +/*
7724 + * Hardware-specific Receive Data Header for the
7725 + * Broadcom Home Networking Division
7726 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
7727 + *
7728 + * Copyright 2001-2003, Broadcom Corporation
7729 + * All Rights Reserved.
7730 + *
7731 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7732 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7733 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7734 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7735 + * $Id$
7736 + */
7737 +
7738 +#ifndef _bcmenetrxh_h_
7739 +#define _bcmenetrxh_h_
7740 +
7741 +/*
7742 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
7743 + * with every frame consisting of
7744 + * 16bits of frame length, followed by
7745 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
7746 + */
7747 +typedef volatile struct {
7748 + uint16 len;
7749 + uint16 flags;
7750 + uint16 pad[12];
7751 +} bcmenetrxh_t;
7752 +
7753 +#define RXHDR_LEN 28
7754 +
7755 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
7756 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
7757 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
7758 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
7759 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
7760 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
7761 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
7762 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
7763 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
7764 +
7765 +#endif /* _bcmenetrxh_h_ */
7766 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmnvram.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmnvram.h
7767 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
7768 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-13 14:59:52.000000000 +0100
7769 @@ -0,0 +1,131 @@
7770 +/*
7771 + * NVRAM variable manipulation
7772 + *
7773 + * $Copyright Open Broadcom Corporation$
7774 + *
7775 + * $Id: bcmnvram.h,v 1.1.1.1 2004/01/21 03:50:44 gigis Exp $
7776 + */
7777 +
7778 +#ifndef _bcmnvram_h_
7779 +#define _bcmnvram_h_
7780 +
7781 +#ifndef _LANGUAGE_ASSEMBLY
7782 +
7783 +#include <typedefs.h>
7784 +
7785 +struct nvram_header {
7786 + uint32 magic;
7787 + uint32 len;
7788 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
7789 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
7790 + uint32 config_ncdl; /* ncdl values for memc */
7791 +};
7792 +
7793 +struct nvram_tuple {
7794 + char *name;
7795 + char *value;
7796 + struct nvram_tuple *next;
7797 +};
7798 +
7799 +/*
7800 + * Initialize NVRAM access. May be unnecessary or undefined on certain
7801 + * platforms.
7802 + */
7803 +extern int nvram_init(void *sbh);
7804 +
7805 +/*
7806 + * Disable NVRAM access. May be unnecessary or undefined on certain
7807 + * platforms.
7808 + */
7809 +extern void nvram_exit(void);
7810 +
7811 +/*
7812 + * Get the value of an NVRAM variable. The pointer returned may be
7813 + * invalid after a set.
7814 + * @param name name of variable to get
7815 + * @return value of variable or NULL if undefined
7816 + */
7817 +extern char * nvram_get(const char *name);
7818 +
7819 +/*
7820 + * Get the value of an NVRAM variable.
7821 + * @param name name of variable to get
7822 + * @return value of variable or NUL if undefined
7823 + */
7824 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
7825 +
7826 +/*
7827 + * Match an NVRAM variable.
7828 + * @param name name of variable to match
7829 + * @param match value to compare against value of variable
7830 + * @return TRUE if variable is defined and its value is string equal
7831 + * to match or FALSE otherwise
7832 + */
7833 +static INLINE int
7834 +nvram_match(char *name, char *match) {
7835 + const char *value = nvram_get(name);
7836 + return (value && !strcmp(value, match));
7837 +}
7838 +
7839 +/*
7840 + * Inversely match an NVRAM variable.
7841 + * @param name name of variable to match
7842 + * @param match value to compare against value of variable
7843 + * @return TRUE if variable is defined and its value is not string
7844 + * equal to invmatch or FALSE otherwise
7845 + */
7846 +static INLINE int
7847 +nvram_invmatch(char *name, char *invmatch) {
7848 + const char *value = nvram_get(name);
7849 + return (value && strcmp(value, invmatch));
7850 +}
7851 +
7852 +/*
7853 + * Set the value of an NVRAM variable. The name and value strings are
7854 + * copied into private storage. Pointers to previously set values
7855 + * may become invalid. The new value may be immediately
7856 + * retrieved but will not be permanently stored until a commit.
7857 + * @param name name of variable to set
7858 + * @param value value of variable
7859 + * @return 0 on success and errno on failure
7860 + */
7861 +extern int nvram_set(const char *name, const char *value);
7862 +
7863 +/*
7864 + * Unset an NVRAM variable. Pointers to previously set values
7865 + * remain valid until a set.
7866 + * @param name name of variable to unset
7867 + * @return 0 on success and errno on failure
7868 + * NOTE: use nvram_commit to commit this change to flash.
7869 + */
7870 +extern int nvram_unset(const char *name);
7871 +
7872 +/*
7873 + * Commit NVRAM variables to permanent storage. All pointers to values
7874 + * may be invalid after a commit.
7875 + * NVRAM values are undefined after a commit.
7876 + * @return 0 on success and errno on failure
7877 + */
7878 +extern int nvram_commit(void);
7879 +
7880 +/*
7881 + * Get all NVRAM variables (format name=value\0 ... \0\0).
7882 + * @param buf buffer to store variables
7883 + * @param count size of buffer in bytes
7884 + * @return 0 on success and errno on failure
7885 + */
7886 +extern int nvram_getall(char *buf, int count);
7887 +
7888 +extern int kernel_write(unsigned char *buffer, int offset, int length);
7889 +
7890 +#endif /* _LANGUAGE_ASSEMBLY */
7891 +
7892 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
7893 +#define NVRAM_VERSION 1
7894 +#define NVRAM_HEADER_SIZE 20
7895 +#define NVRAM_LOC_GAP 0x100000
7896 +#define NVRAM_SPACE 0x2000
7897 +#define NVRAM_FIRST_LOC (0xbfd00000 - NVRAM_SPACE)
7898 +#define NVRAM_LAST_LOC (0xc0000000 - NVRAM_SPACE)
7899 +
7900 +#endif /* _bcmnvram_h_ */
7901 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmsrom.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmsrom.h
7902 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
7903 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-13 14:59:52.000000000 +0100
7904 @@ -0,0 +1,24 @@
7905 +/*
7906 + * Misc useful routines to access NIC srom
7907 + *
7908 + * Copyright 2001-2003, Broadcom Corporation
7909 + * All Rights Reserved.
7910 + *
7911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7915 + *
7916 + * $Id$
7917 + */
7918 +
7919 +#ifndef _bcmsrom_h_
7920 +#define _bcmsrom_h_
7921 +
7922 +extern int srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count);
7923 +
7924 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7925 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7926 +extern int srom_parsecis(uint8 *cis, char **vars, int *count);
7927 +
7928 +#endif /* _bcmsrom_h_ */
7929 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmutils.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmutils.h
7930 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
7931 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bcmutils.h 2005-12-13 14:59:52.000000000 +0100
7932 @@ -0,0 +1,136 @@
7933 +/*
7934 + * Misc useful os-independent macros and functions.
7935 + *
7936 + * Copyright 2001-2003, Broadcom Corporation
7937 + * All Rights Reserved.
7938 + *
7939 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7940 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7941 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7942 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7943 + * $Id$
7944 + */
7945 +
7946 +#ifndef _bcmutils_h_
7947 +#define _bcmutils_h_
7948 +
7949 +#ifndef MIN
7950 +#define MIN(a, b) (((a)<(b))?(a):(b))
7951 +#endif
7952 +
7953 +#ifndef MAX
7954 +#define MAX(a, b) (((a)>(b))?(a):(b))
7955 +#endif
7956 +
7957 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
7958 +#define ROUNDUP(x, y) ((((ulong)(x)+((y)-1))/(y))*(y))
7959 +#define ISALIGNED(a, x) (((uint)(a) & ((x)-1)) == 0)
7960 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
7961 +#define OFFSETOF(type, member) ((uint) &((type *)0)->member)
7962 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
7963 +
7964 +/* bit map related macros */
7965 +#ifndef setbit
7966 +#define NBBY 8 /* 8 bits per byte */
7967 +#define setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY))
7968 +#define clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
7969 +#define isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY)))
7970 +#define isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
7971 +#endif
7972 +
7973 +#define NBITS(type) (sizeof (type) * 8)
7974 +
7975 +#define _BCM_U 0x01 /* upper */
7976 +#define _BCM_L 0x02 /* lower */
7977 +#define _BCM_D 0x04 /* digit */
7978 +#define _BCM_C 0x08 /* cntrl */
7979 +#define _BCM_P 0x10 /* punct */
7980 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
7981 +#define _BCM_X 0x40 /* hex digit */
7982 +#define _BCM_SP 0x80 /* hard space (0x20) */
7983 +
7984 +extern unsigned char bcm_ctype[];
7985 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
7986 +
7987 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
7988 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
7989 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
7990 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
7991 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
7992 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
7993 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
7994 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
7995 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
7996 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
7997 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
7998 +
7999 +/*
8000 + * Spin at most 'us' microseconds while 'exp' is true.
8001 + * Caller should explicitly test 'exp' when this completes
8002 + * and take appropriate error action if 'exp' is still true.
8003 + */
8004 +#define SPINWAIT(exp, us) { \
8005 + uint countdown = (us) + 9; \
8006 + while ((exp) && (countdown >= 10)) {\
8007 + OSL_DELAY(10); \
8008 + countdown -= 10; \
8009 + } \
8010 +}
8011 +
8012 +/* generic osl packet queue */
8013 +struct pktq {
8014 + void *head;
8015 + void *tail;
8016 + uint len;
8017 + uint maxlen;
8018 +};
8019 +#define DEFAULT_QLEN 128
8020 +
8021 +#define pktq_len(q) ((q)->len)
8022 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
8023 +#define pktq_head(q) ((q)->head)
8024 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
8025 +
8026 +/* crc defines */
8027 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
8028 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
8029 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
8030 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
8031 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
8032 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
8033 +
8034 +/* tag_ID/length/value_buffer tuple */
8035 +typedef struct bcm_tlv {
8036 + uint8 id;
8037 + uint8 len;
8038 + uint8 data[1];
8039 +} bcm_tlv_t;
8040 +
8041 +/* externs */
8042 +extern uint bcm_atoi(char *s);
8043 +extern uchar bcm_toupper(uchar c);
8044 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
8045 +extern void deadbeef(char *p, uint len);
8046 +extern void prhex(char *msg, uchar *buf, uint len);
8047 +extern void prpkt(char *msg, void *drv, void *p0);
8048 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
8049 +extern uint pkttotlen(void *drv, void *);
8050 +extern uchar *bcm_ether_ntoa(char *ea, char *buf);
8051 +extern int bcm_ether_atoe(char *p, char *ea);
8052 +extern void bcm_mdelay(uint ms);
8053 +extern char *getvar(char *vars, char *name);
8054 +extern int getintvar(char *vars, char *name);
8055 +
8056 +extern uint8 crc8(uint8 *p, uint nbytes, uint8 crc);
8057 +extern uint16 crc16(uint8 *p, uint nbytes, uint16 crc);
8058 +extern uint32 crc32(uint8 *p, uint nbytes, uint32 crc);
8059 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
8060 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
8061 +extern void pktqinit(struct pktq *q, int maxlen);
8062 +extern void pktenq(struct pktq *q, void *p, bool lifo);
8063 +extern void *pktdeq(struct pktq *q);
8064 +
8065 +#define bcmlog(fmt, a1, a2)
8066 +#define bcmdumplog(buf, size) *buf = '\0'
8067 +
8068 +#endif /* _bcmutils_h_ */
8069 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/bitfuncs.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bitfuncs.h
8070 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
8071 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-13 14:59:52.000000000 +0100
8072 @@ -0,0 +1,85 @@
8073 +/*
8074 + * bit manipulation utility functions
8075 + *
8076 + * Copyright 2001-2003, Broadcom Corporation
8077 + * All Rights Reserved.
8078 + *
8079 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8080 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8081 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8082 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8083 + * $Id$
8084 + */
8085 +
8086 +#ifndef _BITFUNCS_H
8087 +#define _BITFUNCS_H
8088 +
8089 +#include <typedefs.h>
8090 +
8091 +/* local prototypes */
8092 +static INLINE uint32 find_msbit(uint32 x);
8093 +
8094 +
8095 +/*
8096 + * find_msbit: returns index of most significant set bit in x, with index
8097 + * range defined as 0-31. NOTE: returns zero if input is zero.
8098 + */
8099 +
8100 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
8101 +
8102 +/*
8103 + * Implementation for Pentium processors and gcc. Note that this
8104 + * instruction is actually very slow on some processors (e.g., family 5,
8105 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
8106 + * implementation instead.
8107 + */
8108 +static INLINE uint32 find_msbit(uint32 x)
8109 +{
8110 + uint msbit;
8111 + __asm__("bsrl %1,%0"
8112 + :"=r" (msbit)
8113 + :"r" (x));
8114 + return msbit;
8115 +}
8116 +
8117 +#else
8118 +
8119 +/*
8120 + * Generic Implementation
8121 + */
8122 +
8123 +#define DB_POW_MASK16 0xffff0000
8124 +#define DB_POW_MASK8 0x0000ff00
8125 +#define DB_POW_MASK4 0x000000f0
8126 +#define DB_POW_MASK2 0x0000000c
8127 +#define DB_POW_MASK1 0x00000002
8128 +
8129 +static INLINE uint32 find_msbit(uint32 x)
8130 +{
8131 + uint32 temp_x = x;
8132 + uint msbit = 0;
8133 + if (temp_x & DB_POW_MASK16) {
8134 + temp_x >>= 16;
8135 + msbit = 16;
8136 + }
8137 + if (temp_x & DB_POW_MASK8) {
8138 + temp_x >>= 8;
8139 + msbit += 8;
8140 + }
8141 + if (temp_x & DB_POW_MASK4) {
8142 + temp_x >>= 4;
8143 + msbit += 4;
8144 + }
8145 + if (temp_x & DB_POW_MASK2) {
8146 + temp_x >>= 2;
8147 + msbit += 2;
8148 + }
8149 + if (temp_x & DB_POW_MASK1) {
8150 + msbit += 1;
8151 + }
8152 + return(msbit);
8153 +}
8154 +
8155 +#endif
8156 +
8157 +#endif /* _BITFUNCS_H */
8158 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/epivers.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/epivers.h
8159 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
8160 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/epivers.h 2005-12-13 14:59:52.000000000 +0100
8161 @@ -0,0 +1,69 @@
8162 +/*
8163 + * Copyright 2001-2003, Broadcom Corporation
8164 + * All Rights Reserved.
8165 + *
8166 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8167 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8168 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8169 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8170 + *
8171 + * $Id$
8172 + *
8173 +*/
8174 +
8175 +#ifndef _epivers_h_
8176 +#define _epivers_h_
8177 +
8178 +#ifdef linux
8179 +#include <linux/config.h>
8180 +#endif
8181 +
8182 +/* Vendor Name, ASCII, 32 chars max */
8183 +#ifdef COMPANYNAME
8184 +#define HPNA_VENDOR COMPANYNAME
8185 +#else
8186 +#define HPNA_VENDOR "Broadcom Corporation"
8187 +#endif
8188 +
8189 +/* Driver Date, ASCII, 32 chars max */
8190 +#define HPNA_DRV_BUILD_DATE __DATE__
8191 +
8192 +/* Hardware Manufacture Date, ASCII, 32 chars max */
8193 +#define HPNA_HW_MFG_DATE "Not Specified"
8194 +
8195 +/* See documentation for Device Type values, 32 values max */
8196 +#ifndef HPNA_DEV_TYPE
8197 +
8198 +#if defined(CONFIG_BRCM_VJ)
8199 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
8200 +
8201 +#elif defined(CONFIG_BCRM_93725)
8202 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
8203 +
8204 +#else
8205 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
8206 +
8207 +#endif
8208 +
8209 +#endif /* !HPNA_DEV_TYPE */
8210 +
8211 +
8212 +#define EPI_MAJOR_VERSION 1
8213 +
8214 +#define EPI_MINOR_VERSION 1
8215 +
8216 +#define EPI_RC_NUMBER 2
8217 +
8218 +#define EPI_INCREMENTAL_NUMBER 0
8219 +
8220 +#define EPI_BUILD_NUMBER 0
8221 +
8222 +#define EPI_VERSION 1,1,2,0
8223 +
8224 +#define EPI_VERSION_NUM 0x01010200
8225 +
8226 +/* Driver Version String, ASCII, 32 chars max */
8227 +#define EPI_VERSION_STR "1.1.2.0"
8228 +#define EPI_ROUTER_VERSION_STR "1.1.2.0"
8229 +
8230 +#endif /* _epivers_h_ */
8231 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/epivers.h.in linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/epivers.h.in
8232 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
8233 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/epivers.h.in 2005-12-13 14:59:52.000000000 +0100
8234 @@ -0,0 +1,69 @@
8235 +/*
8236 + * Copyright 2001-2003, Broadcom Corporation
8237 + * All Rights Reserved.
8238 + *
8239 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8240 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8241 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8242 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8243 + *
8244 + * $Id$
8245 + *
8246 +*/
8247 +
8248 +#ifndef _epivers_h_
8249 +#define _epivers_h_
8250 +
8251 +#ifdef linux
8252 +#include <linux/config.h>
8253 +#endif
8254 +
8255 +/* Vendor Name, ASCII, 32 chars max */
8256 +#ifdef COMPANYNAME
8257 +#define HPNA_VENDOR COMPANYNAME
8258 +#else
8259 +#define HPNA_VENDOR "Broadcom Corporation"
8260 +#endif
8261 +
8262 +/* Driver Date, ASCII, 32 chars max */
8263 +#define HPNA_DRV_BUILD_DATE __DATE__
8264 +
8265 +/* Hardware Manufacture Date, ASCII, 32 chars max */
8266 +#define HPNA_HW_MFG_DATE "Not Specified"
8267 +
8268 +/* See documentation for Device Type values, 32 values max */
8269 +#ifndef HPNA_DEV_TYPE
8270 +
8271 +#if defined(CONFIG_BRCM_VJ)
8272 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
8273 +
8274 +#elif defined(CONFIG_BCRM_93725)
8275 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
8276 +
8277 +#else
8278 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
8279 +
8280 +#endif
8281 +
8282 +#endif /* !HPNA_DEV_TYPE */
8283 +
8284 +
8285 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
8286 +
8287 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
8288 +
8289 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
8290 +
8291 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
8292 +
8293 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
8294 +
8295 +#define EPI_VERSION @EPI_VERSION@
8296 +
8297 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
8298 +
8299 +/* Driver Version String, ASCII, 32 chars max */
8300 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
8301 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
8302 +
8303 +#endif /* _epivers_h_ */
8304 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/etsockio.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/etsockio.h
8305 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
8306 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/etsockio.h 2005-12-13 14:59:52.000000000 +0100
8307 @@ -0,0 +1,60 @@
8308 +/*
8309 + * Driver-specific socket ioctls
8310 + * used by BSD, Linux, and PSOS
8311 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
8312 + *
8313 + * Copyright 2001-2003, Broadcom Corporation
8314 + * All Rights Reserved.
8315 + *
8316 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8317 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8318 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8319 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8320 + *
8321 + * $Id$
8322 + */
8323 +
8324 +#ifndef _etsockio_h_
8325 +#define _etsockio_h_
8326 +
8327 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
8328 +
8329 +
8330 +#if defined(linux)
8331 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
8332 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
8333 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
8334 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
8335 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
8336 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
8337 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
8338 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
8339 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
8340 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
8341 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
8342 +#define SIOCPERF (SIOCDEVPRIVATE + 11)
8343 +#define SIOCPERFDMA (SIOCDEVPRIVATE + 12)
8344 +
8345 +#else /* !linux */
8346 +
8347 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
8348 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
8349 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
8350 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
8351 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
8352 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
8353 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
8354 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
8355 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
8356 +
8357 +#endif
8358 +
8359 +/* arg to SIOCTXGEN */
8360 +struct txg {
8361 + uint32 num; /* number of frames to send */
8362 + uint32 delay; /* delay in microseconds between sending each */
8363 + uint32 size; /* size of ether frame to send */
8364 + uchar buf[1514]; /* starting ether frame data */
8365 +};
8366 +
8367 +#endif
8368 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/flash.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/flash.h
8369 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
8370 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/flash.h 2005-12-13 14:59:52.000000000 +0100
8371 @@ -0,0 +1,184 @@
8372 +/*
8373 + * flash.h: Common definitions for flash access.
8374 + *
8375 + * Copyright 2001-2003, Broadcom Corporation
8376 + * All Rights Reserved.
8377 + *
8378 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8379 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8380 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8381 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8382 + *
8383 + * $Id$
8384 + */
8385 +
8386 +/* Types of flashes we know about */
8387 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST} flash_type_t;
8388 +
8389 +/* Commands to write/erase the flases */
8390 +typedef struct _flash_cmds{
8391 + flash_type_t type;
8392 + bool need_unlock;
8393 + uint16 pre_erase;
8394 + uint16 erase_block;
8395 + uint16 erase_chip;
8396 + uint16 write_word;
8397 + uint16 write_buf;
8398 + uint16 clear_csr;
8399 + uint16 read_csr;
8400 + uint16 read_id;
8401 + uint16 confirm;
8402 + uint16 read_array;
8403 +} flash_cmds_t;
8404 +
8405 +#define UNLOCK_CMD_WORDS 2
8406 +
8407 +typedef struct _unlock_cmd {
8408 + uint addr[UNLOCK_CMD_WORDS];
8409 + uint16 cmd[UNLOCK_CMD_WORDS];
8410 +} unlock_cmd_t;
8411 +
8412 +/* Flash descriptors */
8413 +typedef struct _flash_desc {
8414 + uint16 mfgid; /* Manufacturer Id */
8415 + uint16 devid; /* Device Id */
8416 + uint size; /* Total size in bytes */
8417 + uint width; /* Device width in bytes */
8418 + flash_type_t type; /* Device type old, S, J */
8419 + uint bsize; /* Block size */
8420 + uint nb; /* Number of blocks */
8421 + uint ff; /* First full block */
8422 + uint lf; /* Last full block */
8423 + uint nsub; /* Number of subblocks */
8424 + uint *subblocks; /* Offsets for subblocks */
8425 + char *desc; /* Description */
8426 +} flash_desc_t;
8427 +
8428 +
8429 +#ifdef DECLARE_FLASHES
8430 +
8431 +flash_cmds_t flash_cmds[] = {
8432 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
8433 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
8434 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
8435 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
8436 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
8437 + { 0 }
8438 +};
8439 +
8440 +unlock_cmd_t unlock_cmd_amd = {
8441 +#ifdef MIPSEB
8442 +/* addr: */ { 0x0aa8, 0x0556},
8443 +#else
8444 +/* addr: */ { 0x0aaa, 0x0554},
8445 +#endif
8446 +/* data: */ { 0xaa, 0x55}
8447 +};
8448 +
8449 +unlock_cmd_t unlock_cmd_sst = {
8450 +#ifdef MIPSEB
8451 +/* addr: */ { 0xaaa8, 0x5556},
8452 +#else
8453 +/* addr: */ { 0xaaaa, 0x5554},
8454 +#endif
8455 +/* data: */ { 0xaa, 0x55}
8456 +};
8457 +
8458 +#define AMD_CMD 0xaaa
8459 +#define SST_CMD 0xaaaa
8460 +
8461 +/* intel unlock block cmds */
8462 +#define INTEL_UNLOCK1 0x60
8463 +#define INTEL_UNLOCK2 0xD0
8464 +
8465 +/* Just eight blocks of 8KB byte each */
8466 +
8467 +uint blk8x8k[] = { 0x00000000,
8468 + 0x00002000,
8469 + 0x00004000,
8470 + 0x00006000,
8471 + 0x00008000,
8472 + 0x0000a000,
8473 + 0x0000c000,
8474 + 0x0000e000,
8475 + 0x00010000
8476 +};
8477 +
8478 +/* Funky AMD arrangement for 29xx800's */
8479 +uint amd800[] = { 0x00000000, /* 16KB */
8480 + 0x00004000, /* 32KB */
8481 + 0x0000c000, /* 8KB */
8482 + 0x0000e000, /* 8KB */
8483 + 0x00010000, /* 8KB */
8484 + 0x00012000, /* 8KB */
8485 + 0x00014000, /* 32KB */
8486 + 0x0001c000, /* 16KB */
8487 + 0x00020000
8488 +};
8489 +
8490 +/* AMD arrangement for 29xx160's */
8491 +uint amd4112[] = { 0x00000000, /* 32KB */
8492 + 0x00008000, /* 8KB */
8493 + 0x0000a000, /* 8KB */
8494 + 0x0000c000, /* 16KB */
8495 + 0x00010000
8496 +};
8497 +uint amd2114[] = { 0x00000000, /* 16KB */
8498 + 0x00004000, /* 8KB */
8499 + 0x00006000, /* 8KB */
8500 + 0x00008000, /* 32KB */
8501 + 0x00010000
8502 +};
8503 +
8504 +
8505 +
8506 +flash_desc_t flashes[] = {
8507 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
8508 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
8509 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
8510 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
8511 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
8512 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
8513 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
8514 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
8515 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
8516 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
8517 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
8518 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
8519 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
8520 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
8521 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
8522 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
8523 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
8524 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
8525 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
8526 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
8527 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
8528 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
8529 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
8530 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
8531 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
8532 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
8533 + { 0x0001, 0x2201, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
8534 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
8535 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
8536 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
8537 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
8538 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
8539 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
8540 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
8541 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
8542 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
8543 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
8544 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
8545 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
8546 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
8547 +};
8548 +
8549 +#else
8550 +
8551 +extern flash_cmds_t flash_cmds[];
8552 +extern unlock_cmd_t unlock_cmd;
8553 +extern flash_desc_t flashes[];
8554 +
8555 +#endif
8556 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/flashutl.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/flashutl.h
8557 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
8558 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/flashutl.h 2005-12-13 14:59:52.000000000 +0100
8559 @@ -0,0 +1,34 @@
8560 +/*
8561 + * BCM47XX FLASH driver interface
8562 + *
8563 + * Copyright 2001-2003, Broadcom Corporation
8564 + * All Rights Reserved.
8565 + *
8566 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8567 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8568 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8569 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8570 + * $Id$
8571 + */
8572 +
8573 +#ifndef _flashutl_h_
8574 +#define _flashutl_h_
8575 +
8576 +#define FLASH_BASE 0xbfc00000 /* BCM4710 */
8577 +
8578 +int flash_init(void* base_addr, char *flash_str);
8579 +int flash_erase(void);
8580 +int flash_eraseblk(unsigned long off);
8581 +int flash_write(unsigned long off, uint16 *src, uint nbytes);
8582 +unsigned long flash_block_base(unsigned long off);
8583 +unsigned long flash_block_lim(unsigned long off);
8584 +int FlashWriteRange(unsigned short* dst, unsigned short* src, unsigned int numbytes);
8585 +
8586 +void nvWrite(unsigned short *data, unsigned int len);
8587 +
8588 +/* Global vars */
8589 +extern char* flashutl_base;
8590 +extern flash_desc_t* flashutl_desc;
8591 +extern flash_cmds_t* flashutl_cmd;
8592 +
8593 +#endif /* _flashutl_h_ */
8594 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/hnddma.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/hnddma.h
8595 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
8596 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/hnddma.h 2005-12-13 14:59:52.000000000 +0100
8597 @@ -0,0 +1,181 @@
8598 +/*
8599 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
8600 + * This supports the following chips: BCM42xx, 44xx, 47xx .
8601 + *
8602 + * $Id$
8603 + * Copyright 2001-2003, Broadcom Corporation
8604 + * All Rights Reserved.
8605 + *
8606 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8607 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8608 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8609 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8610 + */
8611 +
8612 +#ifndef _hnddma_h_
8613 +#define _hnddma_h_
8614 +
8615 +/*
8616 + * Each DMA processor consists of a transmit channel and a receive channel.
8617 + */
8618 +typedef volatile struct {
8619 + /* transmit channel */
8620 + uint32 xmtcontrol; /* enable, et al */
8621 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
8622 + uint32 xmtptr; /* last descriptor posted to chip */
8623 + uint32 xmtstatus; /* current active descriptor, et al */
8624 +
8625 + /* receive channel */
8626 + uint32 rcvcontrol; /* enable, et al */
8627 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
8628 + uint32 rcvptr; /* last descriptor posted to chip */
8629 + uint32 rcvstatus; /* current active descriptor, et al */
8630 +} dmaregs_t;
8631 +
8632 +typedef volatile struct {
8633 + /* diag access */
8634 + uint32 fifoaddr; /* diag address */
8635 + uint32 fifodatalow; /* low 32bits of data */
8636 + uint32 fifodatahigh; /* high 32bits of data */
8637 + uint32 pad; /* reserved */
8638 +} dmafifo_t;
8639 +
8640 +/* transmit channel control */
8641 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
8642 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
8643 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
8644 +#define XC_FL ((uint32)1 << 4) /* flush request */
8645 +
8646 +/* transmit descriptor table pointer */
8647 +#define XP_LD_MASK 0xfff /* last valid descriptor */
8648 +
8649 +/* transmit channel status */
8650 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
8651 +#define XS_XS_MASK 0xf000 /* transmit state */
8652 +#define XS_XS_SHIFT 12
8653 +#define XS_XS_DISABLED 0x0000 /* disabled */
8654 +#define XS_XS_ACTIVE 0x1000 /* active */
8655 +#define XS_XS_IDLE 0x2000 /* idle wait */
8656 +#define XS_XS_STOPPED 0x3000 /* stopped */
8657 +#define XS_XS_SUSP 0x4000 /* suspend pending */
8658 +#define XS_XE_MASK 0xf0000 /* transmit errors */
8659 +#define XS_XE_SHIFT 16
8660 +#define XS_XE_NOERR 0x00000 /* no error */
8661 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
8662 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
8663 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
8664 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
8665 +#define XS_FL ((uint32)1 << 20) /* flushed */
8666 +
8667 +/* receive channel control */
8668 +#define RC_RE ((uint32)1 << 0) /* receive enable */
8669 +#define RC_RO_MASK 0xfe /* receive frame offset */
8670 +#define RC_RO_SHIFT 1
8671 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
8672 +
8673 +/* receive descriptor table pointer */
8674 +#define RP_LD_MASK 0xfff /* last valid descriptor */
8675 +
8676 +/* receive channel status */
8677 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
8678 +#define RS_RS_MASK 0xf000 /* receive state */
8679 +#define RS_RS_SHIFT 12
8680 +#define RS_RS_DISABLED 0x0000 /* disabled */
8681 +#define RS_RS_ACTIVE 0x1000 /* active */
8682 +#define RS_RS_IDLE 0x2000 /* idle wait */
8683 +#define RS_RS_STOPPED 0x3000 /* reserved */
8684 +#define RS_RE_MASK 0xf0000 /* receive errors */
8685 +#define RS_RE_SHIFT 16
8686 +#define RS_RE_NOERR 0x00000 /* no error */
8687 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
8688 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
8689 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
8690 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
8691 +
8692 +/* fifoaddr */
8693 +#define FA_OFF_MASK 0xffff /* offset */
8694 +#define FA_SEL_MASK 0xf0000 /* select */
8695 +#define FA_SEL_SHIFT 16
8696 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
8697 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
8698 +#define FA_SEL_RDD 0x40000 /* receive dma data */
8699 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
8700 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
8701 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
8702 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
8703 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
8704 +
8705 +/*
8706 + * DMA Descriptor
8707 + * Descriptors are only read by the hardware, never written back.
8708 + */
8709 +typedef volatile struct {
8710 + uint32 ctrl; /* misc control bits & bufcount */
8711 + uint32 addr; /* data buffer address */
8712 +} dmadd_t;
8713 +
8714 +/*
8715 + * Each descriptor ring must be 4096byte aligned
8716 + * and fit within a single 4096byte page.
8717 + */
8718 +#define DMAMAXRINGSZ 4096
8719 +#define DMARINGALIGN 4096
8720 +
8721 +/* control flags */
8722 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
8723 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
8724 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
8725 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
8726 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
8727 +
8728 +/* control flags in the range [27:20] are core-specific and not defined here */
8729 +#define CTRL_CORE_MASK 0x0ff00000
8730 +
8731 +/* export structure */
8732 +typedef volatile struct {
8733 + /* rx error counters */
8734 + uint rxgiants; /* rx giant frames */
8735 + uint rxnobuf; /* rx out of dma descriptors */
8736 + /* tx error counters */
8737 + uint txnobuf; /* tx out of dma descriptors */
8738 +} hnddma_t;
8739 +
8740 +#ifndef di_t
8741 +#define di_t void
8742 +#endif
8743 +
8744 +/* externs */
8745 +extern void *dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
8746 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
8747 + uint ddoffset, uint dataoffset, uint *msg_level);
8748 +extern void dma_detach(di_t *di);
8749 +extern void dma_txreset(di_t *di);
8750 +extern void dma_rxreset(di_t *di);
8751 +extern void dma_txinit(di_t *di);
8752 +extern bool dma_txenabled(di_t *di);
8753 +extern void dma_rxinit(di_t *di);
8754 +extern void dma_rxenable(di_t *di);
8755 +extern bool dma_rxenabled(di_t *di);
8756 +extern void dma_txsuspend(di_t *di);
8757 +extern void dma_txresume(di_t *di);
8758 +extern bool dma_txsuspended(di_t *di);
8759 +extern bool dma_txstopped(di_t *di);
8760 +extern bool dma_rxstopped(di_t *di);
8761 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
8762 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
8763 +extern void dma_fifoloopbackenable(di_t *di);
8764 +extern void *dma_rx(di_t *di);
8765 +extern void dma_rxfill(di_t *di);
8766 +extern void dma_txreclaim(di_t *di, bool forceall);
8767 +extern void dma_rxreclaim(di_t *di);
8768 +extern char *dma_dump(di_t *di, char *buf);
8769 +extern char *dma_dumptx(di_t *di, char *buf);
8770 +extern char *dma_dumprx(di_t *di, char *buf);
8771 +extern uint dma_getvar(di_t *di, char *name);
8772 +extern void *dma_getnexttxp(di_t *di, bool forceall);
8773 +extern void *dma_getnextrxp(di_t *di, bool forceall);
8774 +extern void dma_txblock(di_t *di);
8775 +extern void dma_txunblock(di_t *di);
8776 +extern uint dma_txactive(di_t *di);
8777 +
8778 +#endif /* _hnddma_h_ */
8779 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/hndmips.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/hndmips.h
8780 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
8781 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/hndmips.h 2005-12-13 14:59:52.000000000 +0100
8782 @@ -0,0 +1,16 @@
8783 +/*
8784 + * Alternate include file for HND sbmips.h since CFE also ships with
8785 + * a sbmips.h.
8786 + *
8787 + * Copyright 2001-2003, Broadcom Corporation
8788 + * All Rights Reserved.
8789 + *
8790 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8791 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8792 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8793 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8794 + *
8795 + * $Id$
8796 + */
8797 +
8798 +#include "sbmips.h"
8799 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/linux_osl.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/linux_osl.h
8800 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
8801 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/linux_osl.h 2005-12-13 14:59:52.000000000 +0100
8802 @@ -0,0 +1,313 @@
8803 +/*
8804 + * Linux OS Independent Layer
8805 + *
8806 + * Copyright 2001-2003, Broadcom Corporation
8807 + * All Rights Reserved.
8808 + *
8809 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8810 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8811 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8812 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8813 + *
8814 + * $Id$
8815 + */
8816 +
8817 +#ifndef _linux_osl_h_
8818 +#define _linux_osl_h_
8819 +
8820 +#include <typedefs.h>
8821 +
8822 +/* use current 2.4.x calling conventions */
8823 +#include <linuxver.h>
8824 +
8825 +/* assert and panic */
8826 +#define ASSERT(exp) do {} while (0)
8827 +
8828 +/* PCMCIA attribute space access macros */
8829 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
8830 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
8831 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
8832 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
8833 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
8834 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
8835 +
8836 +/* PCI configuration space access macros */
8837 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
8838 + osl_pci_read_config((loc), (offset), (size))
8839 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
8840 + osl_pci_write_config((loc), (offset), (size), (val))
8841 +extern uint32 osl_pci_read_config(void *loc, uint size, uint offset);
8842 +extern void osl_pci_write_config(void *loc, uint offset, uint size, uint val);
8843 +
8844 +/* OSL initialization */
8845 +#define osl_init() do {} while (0)
8846 +
8847 +/* host/bus architecture-specific byte swap */
8848 +#define BUS_SWAP32(v) (v)
8849 +
8850 +/*
8851 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
8852 + * Macros expand to calls to functions defined in linux_osl.c .
8853 + */
8854 +#ifndef BINOSL
8855 +
8856 +/* string library, kernel mode */
8857 +#define printf(fmt, args...) printk(fmt, ## args)
8858 +#include <linux/kernel.h>
8859 +#include <linux/string.h>
8860 +
8861 +/* register access macros */
8862 +#define R_REG(r) ({ \
8863 + __typeof(*(r)) __osl_v; \
8864 + switch (sizeof(*(r))) { \
8865 + case sizeof(uint8): __osl_v = readb((volatile uint8*)(r)); break; \
8866 + case sizeof(uint16): __osl_v = readw((volatile uint16*)(r)); break; \
8867 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
8868 + } \
8869 + __osl_v; \
8870 +})
8871 +#define W_REG(r, v) do { \
8872 + switch (sizeof(*(r))) { \
8873 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
8874 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
8875 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
8876 + } \
8877 +} while (0)
8878 +
8879 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
8880 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
8881 +
8882 +/* bcopy, bcmp, and bzero */
8883 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
8884 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
8885 +#define bzero(b, len) memset((b), '\0', (len))
8886 +
8887 +/* general purpose memory allocation */
8888 +#define MALLOC(size) kmalloc((size), GFP_ATOMIC)
8889 +#define MFREE(addr, size) kfree((addr))
8890 +
8891 +/* uncached virtual address */
8892 +#ifdef mips
8893 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
8894 +#include <asm/addrspace.h>
8895 +#else
8896 +#define OSL_UNCACHED(va) (va)
8897 +#endif
8898 +
8899 +/* get processor cycle count */
8900 +#if defined(mips)
8901 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
8902 +#elif defined(__i386__)
8903 +#define OSL_GETCYCLES(x) rdtscl((x))
8904 +#else
8905 +#define OSL_GETCYCLES(x) ((x) = 0)
8906 +#endif
8907 +
8908 +/* dereference an address that may cause a bus exception */
8909 +#ifdef mips
8910 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
8911 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
8912 +#else
8913 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
8914 +#include <asm/paccess.h>
8915 +#endif
8916 +#else
8917 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
8918 +#endif
8919 +
8920 +/* map/unmap physical to virtual I/O */
8921 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
8922 +#define REG_UNMAP(va) iounmap((void *)(va))
8923 +
8924 +/* allocate/free shared (dma-able) consistent (uncached) memory */
8925 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
8926 + pci_alloc_consistent((dev), (size), (dma_addr_t*)(pap))
8927 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
8928 + pci_free_consistent((dev), (size), (va), (dma_addr_t)(pa))
8929 +
8930 +/* map/unmap direction */
8931 +#define DMA_TX PCI_DMA_TODEVICE
8932 +#define DMA_RX PCI_DMA_FROMDEVICE
8933 +
8934 +/* map/unmap shared (dma-able) memory */
8935 +#define DMA_MAP(dev, va, size, direction, p) \
8936 + pci_map_single((dev), (va), (size), (direction))
8937 +#define DMA_UNMAP(dev, pa, size, direction, p) \
8938 + pci_unmap_single((dev), (dma_addr_t)(pa), (size), (direction))
8939 +
8940 +/* microsecond delay */
8941 +#define OSL_DELAY(usec) udelay(usec)
8942 +#include <linux/delay.h>
8943 +#define OSL_SLEEP(usec) set_current_state(TASK_INTERRUPTIBLE); \
8944 + schedule_timeout((usec*HZ)/1000000);
8945 +#define OSL_IN_INTERRUPT() in_interrupt()
8946 +
8947 +/* shared (dma-able) memory access macros */
8948 +#define R_SM(r) *(r)
8949 +#define W_SM(r, v) (*(r) = (v))
8950 +#define BZERO_SM(r, len) memset((r), '\0', (len))
8951 +
8952 +/* packet primitives */
8953 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
8954 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
8955 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
8956 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
8957 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
8958 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
8959 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
8960 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
8961 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
8962 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
8963 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
8964 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
8965 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
8966 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
8967 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
8968 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
8969 +extern void *osl_pktget(void *drv, uint len, bool send);
8970 +extern void osl_pktfree(void *skb);
8971 +
8972 +#else /* BINOSL */
8973 +
8974 +/* string library */
8975 +#ifndef LINUX_OSL
8976 +#undef printf
8977 +#define printf(fmt, args...) osl_printf((fmt), ## args)
8978 +#undef sprintf
8979 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
8980 +#undef strcmp
8981 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
8982 +#undef strncmp
8983 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
8984 +#undef strlen
8985 +#define strlen(s) osl_strlen((s))
8986 +#undef strcpy
8987 +#define strcpy(d, s) osl_strcpy((d), (s))
8988 +#undef strncpy
8989 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
8990 +#endif
8991 +extern int osl_printf(const char *format, ...);
8992 +extern int osl_sprintf(char *buf, const char *format, ...);
8993 +extern int osl_strcmp(const char *s1, const char *s2);
8994 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
8995 +extern int osl_strlen(char *s);
8996 +extern char* osl_strcpy(char *d, const char *s);
8997 +extern char* osl_strncpy(char *d, const char *s, uint n);
8998 +
8999 +/* register access macros */
9000 +#define R_REG(r) ({ \
9001 + __typeof(*(r)) __osl_v; \
9002 + switch (sizeof(*(r))) { \
9003 + case sizeof(uint8): __osl_v = osl_readb((volatile uint8*)(r)); break; \
9004 + case sizeof(uint16): __osl_v = osl_readw((volatile uint16*)(r)); break; \
9005 + case sizeof(uint32): __osl_v = osl_readl((volatile uint32*)(r)); break; \
9006 + } \
9007 + __osl_v; \
9008 +})
9009 +#define W_REG(r, v) do { \
9010 + switch (sizeof(*(r))) { \
9011 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
9012 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
9013 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
9014 + } \
9015 +} while (0)
9016 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
9017 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
9018 +extern uint8 osl_readb(volatile uint8 *r);
9019 +extern uint16 osl_readw(volatile uint16 *r);
9020 +extern uint32 osl_readl(volatile uint32 *r);
9021 +extern void osl_writeb(uint8 v, volatile uint8 *r);
9022 +extern void osl_writew(uint16 v, volatile uint16 *r);
9023 +extern void osl_writel(uint32 v, volatile uint32 *r);
9024 +
9025 +/* bcopy, bcmp, and bzero */
9026 +extern void bcopy(const void *src, void *dst, int len);
9027 +extern int bcmp(const void *b1, const void *b2, int len);
9028 +extern void bzero(void *b, int len);
9029 +
9030 +/* general purpose memory allocation */
9031 +#define MALLOC(size) osl_malloc((size))
9032 +#define MFREE(addr, size) osl_mfree((char*)(addr), (size))
9033 +extern void *osl_malloc(uint size);
9034 +extern void osl_mfree(void *addr, uint size);
9035 +
9036 +/* uncached virtual address */
9037 +#define OSL_UNCACHED(va) osl_uncached((va))
9038 +extern void *osl_uncached(void *va);
9039 +
9040 +/* get processor cycle count */
9041 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
9042 +extern uint osl_getcycles(void);
9043 +
9044 +/* dereference an address that may target abort */
9045 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
9046 +extern int osl_busprobe(uint32 *val, uint32 addr);
9047 +
9048 +/* map/unmap physical to virtual */
9049 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
9050 +#define REG_UNMAP(va) osl_reg_unmap((va))
9051 +extern void *osl_reg_map(uint32 pa, uint size);
9052 +extern void osl_reg_unmap(void *va);
9053 +
9054 +/* allocate/free shared (dma-able) consistent (uncached) memory */
9055 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
9056 + osl_dma_alloc_consistent((dev), (size), (pap))
9057 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
9058 + osl_dma_free_consistent((dev), (void*)(va), (size), (pa))
9059 +extern void *osl_dma_alloc_consistent(void *dev, uint size, ulong *pap);
9060 +extern void osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa);
9061 +
9062 +/* map/unmap direction */
9063 +#define DMA_TX 1
9064 +#define DMA_RX 2
9065 +
9066 +/* map/unmap shared (dma-able) memory */
9067 +#define DMA_MAP(dev, va, size, direction, p) \
9068 + osl_dma_map((dev), (va), (size), (direction))
9069 +#define DMA_UNMAP(dev, pa, size, direction, p) \
9070 + osl_dma_unmap((dev), (pa), (size), (direction))
9071 +extern uint osl_dma_map(void *dev, void *va, uint size, int direction);
9072 +extern void osl_dma_unmap(void *dev, uint pa, uint size, int direction);
9073 +
9074 +/* microsecond delay */
9075 +#define OSL_DELAY(usec) osl_delay((usec))
9076 +extern void osl_delay(uint usec);
9077 +
9078 +/* shared (dma-able) memory access macros */
9079 +#define R_SM(r) *(r)
9080 +#define W_SM(r, v) (*(r) = (v))
9081 +#define BZERO_SM(r, len) bzero((r), (len))
9082 +
9083 +/* packet primitives */
9084 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
9085 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
9086 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
9087 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
9088 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
9089 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
9090 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
9091 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
9092 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
9093 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
9094 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
9095 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
9096 +#define PKTLINK(skb) osl_pktlink((skb))
9097 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
9098 +extern void *osl_pktget(void *drv, uint len, bool send);
9099 +extern void osl_pktfree(void *skb);
9100 +extern uchar *osl_pktdata(void *drv, void *skb);
9101 +extern uint osl_pktlen(void *drv, void *skb);
9102 +extern void *osl_pktnext(void *drv, void *skb);
9103 +extern void osl_pktsetnext(void *skb, void *x);
9104 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
9105 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
9106 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
9107 +extern void *osl_pktdup(void *drv, void *skb);
9108 +extern void *osl_pktcookie(void *skb);
9109 +extern void osl_pktsetcookie(void *skb, void *x);
9110 +extern void *osl_pktlink(void *skb);
9111 +extern void osl_pktsetlink(void *skb, void *x);
9112 +
9113 +#endif /* BINOSL */
9114 +
9115 +#endif /* _linux_osl_h_ */
9116 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/linuxver.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/linuxver.h
9117 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
9118 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/linuxver.h 2005-12-13 14:59:52.000000000 +0100
9119 @@ -0,0 +1,326 @@
9120 +/*
9121 + * Linux-specific abstractions to gain some independence from linux kernel versions.
9122 + * Pave over some 2.2 versus 2.4 kernel differences.
9123 + *
9124 + * Copyright 2001-2003, Broadcom Corporation
9125 + * All Rights Reserved.
9126 + *
9127 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9128 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9129 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9130 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9131 + * $Id$
9132 + */
9133 +
9134 +#ifndef _linuxver_h_
9135 +#define _linuxver_h_
9136 +
9137 +#include <linux/config.h>
9138 +#include <linux/version.h>
9139 +
9140 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
9141 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
9142 +#ifdef __UNDEF_NO_VERSION__
9143 +#undef __NO_VERSION__
9144 +#else
9145 +#define __NO_VERSION__
9146 +#endif
9147 +#endif
9148 +
9149 +#if defined(MODULE) && defined(MODVERSIONS)
9150 +#include <linux/modversions.h>
9151 +#endif
9152 +
9153 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
9154 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
9155 +#include <linux/malloc.h>
9156 +#else
9157 +#include <linux/slab.h>
9158 +#endif
9159 +
9160 +#include <linux/types.h>
9161 +#include <linux/init.h>
9162 +#include <linux/module.h>
9163 +#include <linux/mm.h>
9164 +#include <linux/string.h>
9165 +#include <linux/pci.h>
9166 +#include <linux/interrupt.h>
9167 +#include <linux/netdevice.h>
9168 +#include <asm/io.h>
9169 +
9170 +#ifndef __exit
9171 +#define __exit
9172 +#endif
9173 +#ifndef __devexit
9174 +#define __devexit
9175 +#endif
9176 +#ifndef __devinit
9177 +#define __devinit __init
9178 +#endif
9179 +#ifndef __devinitdata
9180 +#define __devinitdata
9181 +#endif
9182 +#ifndef __devexit_p
9183 +#define __devexit_p(x) x
9184 +#endif
9185 +
9186 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
9187 +
9188 +#define pci_get_drvdata(dev) (dev)->sysdata
9189 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
9190 +
9191 +/*
9192 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
9193 + */
9194 +
9195 +struct pci_device_id {
9196 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
9197 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
9198 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
9199 + unsigned long driver_data; /* Data private to the driver */
9200 +};
9201 +
9202 +struct pci_driver {
9203 + struct list_head node;
9204 + char *name;
9205 + const struct pci_device_id *id_table; /* NULL if wants all devices */
9206 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
9207 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
9208 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
9209 + void (*resume)(struct pci_dev *dev); /* Device woken up */
9210 +};
9211 +
9212 +#define MODULE_DEVICE_TABLE(type, name)
9213 +#define PCI_ANY_ID (~0)
9214 +
9215 +/* compatpci.c */
9216 +#define pci_module_init pci_register_driver
9217 +extern int pci_register_driver(struct pci_driver *drv);
9218 +extern void pci_unregister_driver(struct pci_driver *drv);
9219 +
9220 +#endif /* PCI registration */
9221 +
9222 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
9223 +#ifdef MODULE
9224 +#define module_init(x) int init_module(void) { return x(); }
9225 +#define module_exit(x) void cleanup_module(void) { x(); }
9226 +#else
9227 +#define module_init(x) __initcall(x);
9228 +#define module_exit(x) __exitcall(x);
9229 +#endif
9230 +#endif
9231 +
9232 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
9233 +#define list_for_each(pos, head) \
9234 + for (pos = (head)->next; pos != (head); pos = pos->next)
9235 +#endif
9236 +
9237 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
9238 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
9239 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
9240 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
9241 +#endif
9242 +
9243 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
9244 +#define pci_enable_device(dev) do { } while (0)
9245 +#endif
9246 +
9247 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
9248 +#define net_device device
9249 +#endif
9250 +
9251 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
9252 +
9253 +/*
9254 + * DMA mapping
9255 + *
9256 + * See linux/Documentation/DMA-mapping.txt
9257 + */
9258 +
9259 +#ifndef PCI_DMA_TODEVICE
9260 +#define PCI_DMA_TODEVICE 1
9261 +#define PCI_DMA_FROMDEVICE 2
9262 +#endif
9263 +
9264 +typedef u32 dma_addr_t;
9265 +
9266 +/* Pure 2^n version of get_order */
9267 +static inline int get_order(unsigned long size)
9268 +{
9269 + int order;
9270 +
9271 + size = (size-1) >> (PAGE_SHIFT-1);
9272 + order = -1;
9273 + do {
9274 + size >>= 1;
9275 + order++;
9276 + } while (size);
9277 + return order;
9278 +}
9279 +
9280 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
9281 + dma_addr_t *dma_handle)
9282 +{
9283 + void *ret;
9284 + int gfp = GFP_ATOMIC | GFP_DMA;
9285 +
9286 + ret = (void *)__get_free_pages(gfp, get_order(size));
9287 +
9288 + if (ret != NULL) {
9289 + memset(ret, 0, size);
9290 + *dma_handle = virt_to_bus(ret);
9291 + }
9292 + return ret;
9293 +}
9294 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
9295 + void *vaddr, dma_addr_t dma_handle)
9296 +{
9297 + free_pages((unsigned long)vaddr, get_order(size));
9298 +}
9299 +#ifdef ILSIM
9300 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
9301 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
9302 +#else
9303 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
9304 +#define pci_unmap_single(cookie, address, size, dir)
9305 +#endif
9306 +
9307 +#endif /* DMA mapping */
9308 +
9309 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
9310 +
9311 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
9312 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
9313 +
9314 +/* pcmcia-cs provides its own netdevice compatibility layer */
9315 +#ifndef _COMPAT_NETDEVICE_H
9316 +
9317 +/*
9318 + * SoftNet
9319 + *
9320 + * For pre-softnet kernels we need to tell the upper layer not to
9321 + * re-enter start_xmit() while we are in there. However softnet
9322 + * guarantees not to enter while we are in there so there is no need
9323 + * to do the netif_stop_queue() dance unless the transmit queue really
9324 + * gets stuck. This should also improve performance according to tests
9325 + * done by Aman Singla.
9326 + */
9327 +
9328 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
9329 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
9330 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
9331 +
9332 +static inline void netif_start_queue(struct net_device *dev)
9333 +{
9334 + dev->tbusy = 0;
9335 + dev->interrupt = 0;
9336 + dev->start = 1;
9337 +}
9338 +
9339 +#define netif_queue_stopped(dev) (dev)->tbusy
9340 +#define netif_running(dev) (dev)->start
9341 +
9342 +#endif /* _COMPAT_NETDEVICE_H */
9343 +
9344 +#define netif_device_attach(dev) netif_start_queue(dev)
9345 +#define netif_device_detach(dev) netif_stop_queue(dev)
9346 +
9347 +/* 2.4.x renamed bottom halves to tasklets */
9348 +#define tasklet_struct tq_struct
9349 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
9350 +{
9351 + queue_task(tasklet, &tq_immediate);
9352 + mark_bh(IMMEDIATE_BH);
9353 +}
9354 +
9355 +static inline void tasklet_init(struct tasklet_struct *tasklet,
9356 + void (*func)(unsigned long),
9357 + unsigned long data)
9358 +{
9359 + tasklet->next = NULL;
9360 + tasklet->sync = 0;
9361 + tasklet->routine = (void (*)(void *))func;
9362 + tasklet->data = (void *)data;
9363 +}
9364 +#define tasklet_kill(tasklet) {do{} while(0);}
9365 +
9366 +/* 2.4.x introduced del_timer_sync() */
9367 +#define del_timer_sync(timer) del_timer(timer)
9368 +
9369 +#else
9370 +
9371 +#define netif_down(dev)
9372 +
9373 +#endif /* SoftNet */
9374 +
9375 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
9376 +
9377 +/*
9378 + * Emit code to initialise a tq_struct's routine and data pointers
9379 + */
9380 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
9381 + do { \
9382 + (_tq)->routine = _routine; \
9383 + (_tq)->data = _data; \
9384 + } while (0)
9385 +
9386 +/*
9387 + * Emit code to initialise all of a tq_struct
9388 + */
9389 +#define INIT_TQUEUE(_tq, _routine, _data) \
9390 + do { \
9391 + INIT_LIST_HEAD(&(_tq)->list); \
9392 + (_tq)->sync = 0; \
9393 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
9394 + } while (0)
9395 +
9396 +#endif
9397 +
9398 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
9399 +
9400 +/* Power management related routines */
9401 +
9402 +static inline int
9403 +pci_save_state(struct pci_dev *dev, u32 *buffer)
9404 +{
9405 + int i;
9406 + if (buffer) {
9407 + for (i = 0; i < 16; i++)
9408 + pci_read_config_dword(dev, i * 4,&buffer[i]);
9409 + }
9410 + return 0;
9411 +}
9412 +
9413 +static inline int
9414 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
9415 +{
9416 + int i;
9417 +
9418 + if (buffer) {
9419 + for (i = 0; i < 16; i++)
9420 + pci_write_config_dword(dev,i * 4, buffer[i]);
9421 + }
9422 + /*
9423 + * otherwise, write the context information we know from bootup.
9424 + * This works around a problem where warm-booting from Windows
9425 + * combined with a D3(hot)->D0 transition causes PCI config
9426 + * header data to be forgotten.
9427 + */
9428 + else {
9429 + for (i = 0; i < 6; i ++)
9430 + pci_write_config_dword(dev,
9431 + PCI_BASE_ADDRESS_0 + (i * 4),
9432 + pci_resource_start(dev, i));
9433 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
9434 + }
9435 + return 0;
9436 +}
9437 +
9438 +#endif /* PCI power management */
9439 +
9440 +/* Old cp0 access macros deprecated in 2.4.19 */
9441 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
9442 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
9443 +#endif
9444 +
9445 +#endif /* _linuxver_h_ */
9446 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/nvports.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/nvports.h
9447 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
9448 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/nvports.h 2005-12-13 14:59:52.000000000 +0100
9449 @@ -0,0 +1,62 @@
9450 +/*
9451 + * Broadcom Home Gateway Reference Design
9452 + * Ports Web Page Configuration Support Routines
9453 + *
9454 + * Copyright 2001-2003, Broadcom Corporation
9455 + * All Rights Reserved.
9456 + *
9457 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9458 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9459 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9460 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9461 + * $Id$
9462 + */
9463 +
9464 +#ifndef _nvports_h_
9465 +#define _nvports_h_
9466 +
9467 +#define uint32 unsigned long
9468 +#define uint16 unsigned short
9469 +#define uint unsigned int
9470 +#define uint8 unsigned char
9471 +#define uint64 unsigned long long
9472 +
9473 +enum FORCE_PORT {
9474 + FORCE_OFF,
9475 + FORCE_10H,
9476 + FORCE_10F,
9477 + FORCE_100H,
9478 + FORCE_100F,
9479 + FORCE_DOWN,
9480 + POWER_OFF
9481 +};
9482 +
9483 +typedef struct _PORT_ATTRIBS
9484 +{
9485 + uint autoneg;
9486 + uint force;
9487 + uint native;
9488 +} PORT_ATTRIBS;
9489 +
9490 +extern uint
9491 +nvExistsPortAttrib(char *attrib, uint portno);
9492 +
9493 +extern int
9494 +nvExistsAnyForcePortAttrib(uint portno);
9495 +
9496 +extern void
9497 +nvSetPortAttrib(char *attrib, uint portno);
9498 +
9499 +extern void
9500 +nvUnsetPortAttrib(char *attrib, uint portno);
9501 +
9502 +extern void
9503 +nvUnsetAllForcePortAttrib(uint portno);
9504 +
9505 +extern PORT_ATTRIBS
9506 +nvGetSwitchPortAttribs(uint portno);
9507 +
9508 +#endif /* _nvports_h_ */
9509 +
9510 +
9511 +
9512 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/osl.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/osl.h
9513 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
9514 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/osl.h 2005-12-13 14:59:52.000000000 +0100
9515 @@ -0,0 +1,38 @@
9516 +/*
9517 + * OS Independent Layer
9518 + *
9519 + * Copyright 2001-2003, Broadcom Corporation
9520 + * All Rights Reserved.
9521 + *
9522 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9523 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9524 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9525 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9526 + * $Id$
9527 + */
9528 +
9529 +#ifndef _osl_h_
9530 +#define _osl_h_
9531 +
9532 +#ifdef V2_HAL
9533 +#include <v2hal_osl.h>
9534 +#elif defined(linux)
9535 +#include <linux_osl.h>
9536 +#elif PMON
9537 +#include <pmon_osl.h>
9538 +#elif defined(NDIS)
9539 +#include <ndis_osl.h>
9540 +#elif defined(_CFE_)
9541 +#include <cfe_osl.h>
9542 +#elif defined(MACOS9)
9543 +#include <macos9_osl.h>
9544 +#elif defined(MACOSX)
9545 +#include <macosx_osl.h>
9546 +#else
9547 +#error "Unsupported OSL requested"
9548 +#endif
9549 +
9550 +/* handy */
9551 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
9552 +
9553 +#endif /* _osl_h_ */
9554 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/pcicfg.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/pcicfg.h
9555 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
9556 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/pcicfg.h 2005-12-13 14:59:52.000000000 +0100
9557 @@ -0,0 +1,362 @@
9558 +/*
9559 + * pcicfg.h: PCI configuration constants and structures.
9560 + *
9561 + * Copyright 2001-2003, Broadcom Corporation
9562 + * All Rights Reserved.
9563 + *
9564 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9565 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9566 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9567 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9568 + *
9569 + * $Id$
9570 + */
9571 +
9572 +#ifndef _h_pci_
9573 +#define _h_pci_
9574 +
9575 +/* The following inside ifndef's so we don't collide with NTDDK.H */
9576 +#ifndef PCI_MAX_BUS
9577 +#define PCI_MAX_BUS 0x100
9578 +#endif
9579 +#ifndef PCI_MAX_DEVICES
9580 +#define PCI_MAX_DEVICES 0x20
9581 +#endif
9582 +#ifndef PCI_MAX_FUNCTION
9583 +#define PCI_MAX_FUNCTION 0x8
9584 +#endif
9585 +
9586 +#ifndef PCI_INVALID_VENDORID
9587 +#define PCI_INVALID_VENDORID 0xffff
9588 +#endif
9589 +#ifndef PCI_INVALID_DEVICEID
9590 +#define PCI_INVALID_DEVICEID 0xffff
9591 +#endif
9592 +
9593 +
9594 +/* Convert between bus-slot-function-register and config addresses */
9595 +
9596 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
9597 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
9598 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
9599 +#define PCICFG_OFF_SHIFT 0 /* Bus shift */
9600 +
9601 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
9602 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
9603 +#define PCICFG_FUN_MASK 7 /* Function mask */
9604 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
9605 +
9606 +#define PCI_CONFIG_ADDR(b, s, f, o) \
9607 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
9608 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
9609 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
9610 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
9611 +
9612 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
9613 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
9614 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
9615 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
9616 +
9617 +
9618 +/* The actual config space */
9619 +
9620 +#define PCI_BAR_MAX 6
9621 +
9622 +#define PCI_ROM_BAR 8
9623 +
9624 +#define PCR_RSVDA_MAX 2
9625 +
9626 +typedef struct _pci_config_regs {
9627 + unsigned short vendor;
9628 + unsigned short device;
9629 + unsigned short command;
9630 + unsigned short status;
9631 + unsigned char rev_id;
9632 + unsigned char prog_if;
9633 + unsigned char sub_class;
9634 + unsigned char base_class;
9635 + unsigned char cache_line_size;
9636 + unsigned char latency_timer;
9637 + unsigned char header_type;
9638 + unsigned char bist;
9639 + unsigned long base[PCI_BAR_MAX];
9640 + unsigned long cardbus_cis;
9641 + unsigned short subsys_vendor;
9642 + unsigned short subsys_id;
9643 + unsigned long baserom;
9644 + unsigned long rsvd_a[PCR_RSVDA_MAX];
9645 + unsigned char int_line;
9646 + unsigned char int_pin;
9647 + unsigned char min_gnt;
9648 + unsigned char max_lat;
9649 + unsigned char dev_dep[192];
9650 +} pci_config_regs;
9651 +
9652 +#define SZPCR (sizeof (pci_config_regs))
9653 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
9654 +
9655 +/* A structure for the config registers is nice, but in most
9656 + * systems the config space is not memory mapped, so we need
9657 + * filed offsetts. :-(
9658 + */
9659 +#define PCI_CFG_VID 0
9660 +#define PCI_CFG_DID 2
9661 +#define PCI_CFG_CMD 4
9662 +#define PCI_CFG_STAT 6
9663 +#define PCI_CFG_REV 8
9664 +#define PCI_CFG_PROGIF 9
9665 +#define PCI_CFG_SUBCL 0xa
9666 +#define PCI_CFG_BASECL 0xb
9667 +#define PCI_CFG_CLSZ 0xc
9668 +#define PCI_CFG_LATTIM 0xd
9669 +#define PCI_CFG_HDR 0xe
9670 +#define PCI_CFG_BIST 0xf
9671 +#define PCI_CFG_BAR0 0x10
9672 +#define PCI_CFG_BAR1 0x14
9673 +#define PCI_CFG_BAR2 0x18
9674 +#define PCI_CFG_BAR3 0x1c
9675 +#define PCI_CFG_BAR4 0x20
9676 +#define PCI_CFG_BAR5 0x24
9677 +#define PCI_CFG_CIS 0x28
9678 +#define PCI_CFG_SVID 0x2c
9679 +#define PCI_CFG_SSID 0x2e
9680 +#define PCI_CFG_ROMBAR 0x30
9681 +#define PCI_CFG_INT 0x3c
9682 +#define PCI_CFG_PIN 0x3d
9683 +#define PCI_CFG_MINGNT 0x3e
9684 +#define PCI_CFG_MAXLAT 0x3f
9685 +
9686 +/* Classes and subclasses */
9687 +
9688 +typedef enum {
9689 + PCI_CLASS_OLD = 0,
9690 + PCI_CLASS_DASDI,
9691 + PCI_CLASS_NET,
9692 + PCI_CLASS_DISPLAY,
9693 + PCI_CLASS_MMEDIA,
9694 + PCI_CLASS_MEMORY,
9695 + PCI_CLASS_BRIDGE,
9696 + PCI_CLASS_COMM,
9697 + PCI_CLASS_BASE,
9698 + PCI_CLASS_INPUT,
9699 + PCI_CLASS_DOCK,
9700 + PCI_CLASS_CPU,
9701 + PCI_CLASS_SERIAL,
9702 + PCI_CLASS_INTELLIGENT = 0xe,
9703 + PCI_CLASS_SATELLITE,
9704 + PCI_CLASS_CRYPT,
9705 + PCI_CLASS_DSP,
9706 + PCI_CLASS_MAX
9707 +} pci_classes;
9708 +
9709 +typedef enum {
9710 + PCI_DASDI_SCSI,
9711 + PCI_DASDI_IDE,
9712 + PCI_DASDI_FLOPPY,
9713 + PCI_DASDI_IPI,
9714 + PCI_DASDI_RAID,
9715 + PCI_DASDI_OTHER = 0x80
9716 +} pci_dasdi_subclasses;
9717 +
9718 +typedef enum {
9719 + PCI_NET_ETHER,
9720 + PCI_NET_TOKEN,
9721 + PCI_NET_FDDI,
9722 + PCI_NET_ATM,
9723 + PCI_NET_OTHER = 0x80
9724 +} pci_net_subclasses;
9725 +
9726 +typedef enum {
9727 + PCI_DISPLAY_VGA,
9728 + PCI_DISPLAY_XGA,
9729 + PCI_DISPLAY_3D,
9730 + PCI_DISPLAY_OTHER = 0x80
9731 +} pci_display_subclasses;
9732 +
9733 +typedef enum {
9734 + PCI_MMEDIA_VIDEO,
9735 + PCI_MMEDIA_AUDIO,
9736 + PCI_MMEDIA_PHONE,
9737 + PCI_MEDIA_OTHER = 0x80
9738 +} pci_mmedia_subclasses;
9739 +
9740 +typedef enum {
9741 + PCI_MEMORY_RAM,
9742 + PCI_MEMORY_FLASH,
9743 + PCI_MEMORY_OTHER = 0x80
9744 +} pci_memory_subclasses;
9745 +
9746 +typedef enum {
9747 + PCI_BRIDGE_HOST,
9748 + PCI_BRIDGE_ISA,
9749 + PCI_BRIDGE_EISA,
9750 + PCI_BRIDGE_MC,
9751 + PCI_BRIDGE_PCI,
9752 + PCI_BRIDGE_PCMCIA,
9753 + PCI_BRIDGE_NUBUS,
9754 + PCI_BRIDGE_CARDBUS,
9755 + PCI_BRIDGE_RACEWAY,
9756 + PCI_BRIDGE_OTHER = 0x80
9757 +} pci_bridge_subclasses;
9758 +
9759 +typedef enum {
9760 + PCI_COMM_UART,
9761 + PCI_COMM_PARALLEL,
9762 + PCI_COMM_MULTIUART,
9763 + PCI_COMM_MODEM,
9764 + PCI_COMM_OTHER = 0x80
9765 +} pci_comm_subclasses;
9766 +
9767 +typedef enum {
9768 + PCI_BASE_PIC,
9769 + PCI_BASE_DMA,
9770 + PCI_BASE_TIMER,
9771 + PCI_BASE_RTC,
9772 + PCI_BASE_PCI_HOTPLUG,
9773 + PCI_BASE_OTHER = 0x80
9774 +} pci_base_subclasses;
9775 +
9776 +typedef enum {
9777 + PCI_INPUT_KBD,
9778 + PCI_INPUT_PEN,
9779 + PCI_INPUT_MOUSE,
9780 + PCI_INPUT_SCANNER,
9781 + PCI_INPUT_GAMEPORT,
9782 + PCI_INPUT_OTHER = 0x80
9783 +} pci_input_subclasses;
9784 +
9785 +typedef enum {
9786 + PCI_DOCK_GENERIC,
9787 + PCI_DOCK_OTHER = 0x80
9788 +} pci_dock_subclasses;
9789 +
9790 +typedef enum {
9791 + PCI_CPU_386,
9792 + PCI_CPU_486,
9793 + PCI_CPU_PENTIUM,
9794 + PCI_CPU_ALPHA = 0x10,
9795 + PCI_CPU_POWERPC = 0x20,
9796 + PCI_CPU_MIPS = 0x30,
9797 + PCI_CPU_COPROC = 0x40,
9798 + PCI_CPU_OTHER = 0x80
9799 +} pci_cpu_subclasses;
9800 +
9801 +typedef enum {
9802 + PCI_SERIAL_IEEE1394,
9803 + PCI_SERIAL_ACCESS,
9804 + PCI_SERIAL_SSA,
9805 + PCI_SERIAL_USB,
9806 + PCI_SERIAL_FIBER,
9807 + PCI_SERIAL_SMBUS,
9808 + PCI_SERIAL_OTHER = 0x80
9809 +} pci_serial_subclasses;
9810 +
9811 +typedef enum {
9812 + PCI_INTELLIGENT_I2O,
9813 +} pci_intelligent_subclasses;
9814 +
9815 +typedef enum {
9816 + PCI_SATELLITE_TV,
9817 + PCI_SATELLITE_AUDIO,
9818 + PCI_SATELLITE_VOICE,
9819 + PCI_SATELLITE_DATA,
9820 + PCI_SATELLITE_OTHER = 0x80
9821 +} pci_satellite_subclasses;
9822 +
9823 +typedef enum {
9824 + PCI_CRYPT_NETWORK,
9825 + PCI_CRYPT_ENTERTAINMENT,
9826 + PCI_CRYPT_OTHER = 0x80
9827 +} pci_crypt_subclasses;
9828 +
9829 +typedef enum {
9830 + PCI_DSP_DPIO,
9831 + PCI_DSP_OTHER = 0x80
9832 +} pci_dsp_subclasses;
9833 +
9834 +/* Header types */
9835 +typedef enum {
9836 + PCI_HEADER_NORMAL,
9837 + PCI_HEADER_BRIDGE,
9838 + PCI_HEADER_CARDBUS
9839 +} pci_header_types;
9840 +
9841 +
9842 +/* Overlay for a PCI-to-PCI bridge */
9843 +
9844 +#define PPB_RSVDA_MAX 2
9845 +#define PPB_RSVDD_MAX 8
9846 +
9847 +typedef struct _ppb_config_regs {
9848 + unsigned short vendor;
9849 + unsigned short device;
9850 + unsigned short command;
9851 + unsigned short status;
9852 + unsigned char rev_id;
9853 + unsigned char prog_if;
9854 + unsigned char sub_class;
9855 + unsigned char base_class;
9856 + unsigned char cache_line_size;
9857 + unsigned char latency_timer;
9858 + unsigned char header_type;
9859 + unsigned char bist;
9860 + unsigned long rsvd_a[PPB_RSVDA_MAX];
9861 + unsigned char prim_bus;
9862 + unsigned char sec_bus;
9863 + unsigned char sub_bus;
9864 + unsigned char sec_lat;
9865 + unsigned char io_base;
9866 + unsigned char io_lim;
9867 + unsigned short sec_status;
9868 + unsigned short mem_base;
9869 + unsigned short mem_lim;
9870 + unsigned short pf_mem_base;
9871 + unsigned short pf_mem_lim;
9872 + unsigned long pf_mem_base_hi;
9873 + unsigned long pf_mem_lim_hi;
9874 + unsigned short io_base_hi;
9875 + unsigned short io_lim_hi;
9876 + unsigned short subsys_vendor;
9877 + unsigned short subsys_id;
9878 + unsigned long rsvd_b;
9879 + unsigned char rsvd_c;
9880 + unsigned char int_pin;
9881 + unsigned short bridge_ctrl;
9882 + unsigned char chip_ctrl;
9883 + unsigned char diag_ctrl;
9884 + unsigned short arb_ctrl;
9885 + unsigned long rsvd_d[PPB_RSVDD_MAX];
9886 + unsigned char dev_dep[192];
9887 +} ppb_config_regs;
9888 +
9889 +/* Eveything below is BRCM HND proprietary */
9890 +
9891 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
9892 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
9893 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
9894 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
9895 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
9896 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
9897 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
9898 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
9899 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
9900 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
9901 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
9902 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
9903 +
9904 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
9905 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
9906 +
9907 +/* PCI_INT_MASK */
9908 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
9909 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
9910 +
9911 +/* PCI_SPROM_CONTROL */
9912 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
9913 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
9914 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
9915 +
9916 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
9917 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
9918 +
9919 +#endif
9920 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/proto/802.11.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/proto/802.11.h
9921 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
9922 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/proto/802.11.h 2005-12-13 14:59:52.000000000 +0100
9923 @@ -0,0 +1,679 @@
9924 +/*
9925 + * Copyright 2001-2003, Broadcom Corporation
9926 + * All Rights Reserved.
9927 + *
9928 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9929 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9930 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9931 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9932 + *
9933 + * Fundamental types and constants relating to 802.11
9934 + *
9935 + * $Id$
9936 + */
9937 +
9938 +#ifndef _802_11_H_
9939 +#define _802_11_H_
9940 +
9941 +#ifndef _TYPEDEFS_H_
9942 +#include <typedefs.h>
9943 +#endif
9944 +
9945 +#ifndef _NET_ETHERNET_H_
9946 +#include <proto/ethernet.h>
9947 +#endif
9948 +
9949 +/* enable structure packing */
9950 +#if !defined(__GNUC__)
9951 +#pragma pack(1)
9952 +#endif
9953 +
9954 +/* some platforms require stronger medicine */
9955 +#if defined(__GNUC__)
9956 +#define PACKED __attribute__((packed))
9957 +#else
9958 +#define PACKED
9959 +#endif
9960 +
9961 +
9962 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
9963 +
9964 +/* Generic 802.11 frame constants */
9965 +#define DOT11_A3_HDR_LEN 24
9966 +#define DOT11_A4_HDR_LEN 30
9967 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
9968 +#define DOT11_FCS_LEN 4
9969 +#define DOT11_ICV_LEN 4
9970 +#define DOT11_ICV_AES_LEN 8
9971 +
9972 +
9973 +#define DOT11_KEY_INDEX_SHIFT 6
9974 +#define DOT11_IV_LEN 4
9975 +#define DOT11_IV_TKIP_LEN 8
9976 +#define DOT11_IV_AES_OCB_LEN 4
9977 +#define DOT11_IV_AES_CCM_LEN 8
9978 +
9979 +#define DOT11_MAX_MPDU_BODY_LEN 2312
9980 +#define DOT11_MAX_MPDU_LEN 2346 /* body len + A4 hdr + FCS */
9981 +#define DOT11_MAX_SSID_LEN 32
9982 +
9983 +/* dot11RTSThreshold */
9984 +#define DOT11_DEFAULT_RTS_LEN 2347
9985 +#define DOT11_MAX_RTS_LEN 2347
9986 +
9987 +/* dot11FragmentationThreshold */
9988 +#define DOT11_MIN_FRAG_LEN 256
9989 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
9990 +#define DOT11_DEFAULT_FRAG_LEN 2346
9991 +
9992 +/* dot11BeaconPeriod */
9993 +#define DOT11_MIN_BEACON_PERIOD 1
9994 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
9995 +
9996 +/* dot11DTIMPeriod */
9997 +#define DOT11_MIN_DTIM_PERIOD 1
9998 +#define DOT11_MAX_DTIM_PERIOD 0xFF
9999 +
10000 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
10001 +#define DOT11_LLC_SNAP_HDR_LEN 8
10002 +#define DOT11_OUI_LEN 3
10003 +struct dot11_llc_snap_header {
10004 + uint8 dsap; /* always 0xAA */
10005 + uint8 ssap; /* always 0xAA */
10006 + uint8 ctl; /* always 0x03 */
10007 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
10008 + Bridge-Tunnel: 0x00 0x00 0xF8 */
10009 + uint16 type; /* ethertype */
10010 +} PACKED;
10011 +
10012 +/* RFC1042 header used by 802.11 per 802.1H */
10013 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
10014 +
10015 +/* Generic 802.11 MAC header */
10016 +/*
10017 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
10018 + * The fields are defined such that the shorter 1, 2, and 3
10019 + * address headers just use the first k fields.
10020 + */
10021 +struct dot11_header {
10022 + uint16 fc; /* frame control */
10023 + uint16 durid; /* duration/ID */
10024 + struct ether_addr a1; /* address 1 */
10025 + struct ether_addr a2; /* address 2 */
10026 + struct ether_addr a3; /* address 3 */
10027 + uint16 seq; /* sequence control */
10028 + struct ether_addr a4; /* address 4 */
10029 +} PACKED;
10030 +
10031 +/* Control frames */
10032 +
10033 +struct dot11_rts_frame {
10034 + uint16 fc; /* frame control */
10035 + uint16 durid; /* duration/ID */
10036 + struct ether_addr ra; /* receiver address */
10037 + struct ether_addr ta; /* transmitter address */
10038 +} PACKED;
10039 +#define DOT11_RTS_LEN 16
10040 +
10041 +struct dot11_cts_frame {
10042 + uint16 fc; /* frame control */
10043 + uint16 durid; /* duration/ID */
10044 + struct ether_addr ra; /* receiver address */
10045 +} PACKED;
10046 +#define DOT11_CTS_LEN 10
10047 +
10048 +struct dot11_ack_frame {
10049 + uint16 fc; /* frame control */
10050 + uint16 durid; /* duration/ID */
10051 + struct ether_addr ra; /* receiver address */
10052 +} PACKED;
10053 +#define DOT11_ACK_LEN 10
10054 +
10055 +struct dot11_ps_poll_frame {
10056 + uint16 fc; /* frame control */
10057 + uint16 durid; /* AID */
10058 + struct ether_addr bssid; /* receiver address, STA in AP */
10059 + struct ether_addr ta; /* transmitter address */
10060 +} PACKED;
10061 +#define DOT11_PS_POLL_LEN 16
10062 +
10063 +struct dot11_cf_end_frame {
10064 + uint16 fc; /* frame control */
10065 + uint16 durid; /* duration/ID */
10066 + struct ether_addr ra; /* receiver address */
10067 + struct ether_addr bssid; /* transmitter address, STA in AP */
10068 +} PACKED;
10069 +#define DOT11_CS_END_LEN 16
10070 +
10071 +/* Management frame header */
10072 +struct dot11_management_header {
10073 + uint16 fc; /* frame control */
10074 + uint16 durid; /* duration/ID */
10075 + struct ether_addr da; /* receiver address */
10076 + struct ether_addr sa; /* transmitter address */
10077 + struct ether_addr bssid; /* BSS ID */
10078 + uint16 seq; /* sequence control */
10079 +} PACKED;
10080 +#define DOT11_MGMT_HDR_LEN 24
10081 +
10082 +/* Management frame payloads */
10083 +
10084 +struct dot11_bcn_prb {
10085 + uint32 timestamp[2];
10086 + uint16 beacon_interval;
10087 + uint16 capability;
10088 +} PACKED;
10089 +#define DOT11_BCN_PRB_LEN 12
10090 +
10091 +struct dot11_auth {
10092 + uint16 alg; /* algorithm */
10093 + uint16 seq; /* sequence control */
10094 + uint16 status; /* status code */
10095 +} PACKED;
10096 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
10097 +
10098 +struct dot11_assoc_req {
10099 + uint16 capability; /* capability information */
10100 + uint16 listen; /* listen interval */
10101 +} PACKED;
10102 +
10103 +struct dot11_assoc_resp {
10104 + uint16 capability; /* capability information */
10105 + uint16 status; /* status code */
10106 + uint16 aid; /* association ID */
10107 +} PACKED;
10108 +
10109 +struct dot11_action_measure {
10110 + uint8 category;
10111 + uint8 action;
10112 + uint8 token;
10113 + uint8 data[1];
10114 +} PACKED;
10115 +#define DOT11_ACTION_MEASURE_LEN 3
10116 +
10117 +/**************
10118 + 802.11h related definitions.
10119 +**************/
10120 +typedef struct {
10121 + uint8 id;
10122 + uint8 len;
10123 + uint8 power;
10124 +} dot11_power_cnst_t;
10125 +
10126 +typedef struct {
10127 + uint8 min;
10128 + uint8 max;
10129 +} dot11_power_cap_t;
10130 +
10131 +typedef struct {
10132 + uint8 id;
10133 + uint8 len;
10134 + uint8 tx_pwr;
10135 + uint8 margin;
10136 +} dot11_tpc_rep_t;
10137 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
10138 +
10139 +typedef struct {
10140 + uint8 id;
10141 + uint8 len;
10142 + uint8 first_channel;
10143 + uint8 num_channels;
10144 +} dot11_supp_channels_t;
10145 +
10146 +struct dot11_channel_switch {
10147 + uint8 id;
10148 + uint8 len;
10149 + uint8 mode;
10150 + uint8 channel;
10151 + uint8 count;
10152 +} PACKED;
10153 +typedef struct dot11_channel_switch dot11_channel_switch_t;
10154 +
10155 +/* 802.11h Measurement Request/Report IEs */
10156 +/* Measurement Type field */
10157 +#define DOT11_MEASURE_TYPE_BASIC 0
10158 +#define DOT11_MEASURE_TYPE_CCA 1
10159 +#define DOT11_MEASURE_TYPE_RPI 2
10160 +
10161 +/* Measurement Mode field */
10162 +
10163 +/* Measurement Request Modes */
10164 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
10165 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
10166 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
10167 +/* Measurement Report Modes */
10168 +#define DOT11_MEASURE_MODE_LATE (1<<0)
10169 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
10170 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
10171 +/* Basic Measurement Map bits */
10172 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
10173 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
10174 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
10175 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
10176 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
10177 +
10178 +typedef struct {
10179 + uint8 id;
10180 + uint8 len;
10181 + uint8 token;
10182 + uint8 mode;
10183 + uint8 type;
10184 + uint8 channel;
10185 + uint8 start_time[8];
10186 + uint16 duration;
10187 +} dot11_meas_req_t;
10188 +#define DOT11_MNG_IE_MREQ_LEN 14
10189 +/* length of Measure Request IE data not including variable len */
10190 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
10191 +
10192 +struct dot11_meas_rep {
10193 + uint8 id;
10194 + uint8 len;
10195 + uint8 token;
10196 + uint8 mode;
10197 + uint8 type;
10198 + union
10199 + {
10200 + struct {
10201 + uint8 channel;
10202 + uint8 start_time[8];
10203 + uint16 duration;
10204 + uint8 map;
10205 + } PACKED basic;
10206 + uint8 data[1];
10207 + } PACKED rep;
10208 +} PACKED;
10209 +typedef struct dot11_meas_rep dot11_meas_rep_t;
10210 +
10211 +/* length of Measure Report IE data not including variable len */
10212 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
10213 +
10214 +struct dot11_meas_rep_basic {
10215 + uint8 channel;
10216 + uint8 start_time[8];
10217 + uint16 duration;
10218 + uint8 map;
10219 +} PACKED;
10220 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
10221 +#define DOT11_MEASURE_BASIC_REP_LEN 12
10222 +
10223 +struct dot11_quiet {
10224 + uint8 id;
10225 + uint8 len;
10226 + uint8 count; /* TBTTs until beacon interval in quiet starts */
10227 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
10228 + uint16 duration;/* Length of quiet period, in TU's */
10229 + uint16 offset; /* TU's offset from TBTT in Count field */
10230 +} PACKED;
10231 +typedef struct dot11_quiet dot11_quiet_t;
10232 +
10233 +typedef struct {
10234 + uint8 channel;
10235 + uint8 map;
10236 +} chan_map_tuple_t;
10237 +
10238 +typedef struct {
10239 + uint8 id;
10240 + uint8 len;
10241 + uint8 eaddr[ETHER_ADDR_LEN];
10242 + uint8 interval;
10243 + chan_map_tuple_t map[1];
10244 +} dot11_ibss_dfs_t;
10245 +
10246 +
10247 +/* Macro to take a pointer to a beacon or probe response
10248 + * header and return the char* pointer to the SSID info element
10249 + */
10250 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
10251 +
10252 +/* Authentication frame payload constants */
10253 +#define DOT11_OPEN_SYSTEM 0
10254 +#define DOT11_SHARED_KEY 1
10255 +#define DOT11_CHALLENGE_LEN 128
10256 +
10257 +/* Frame control macros */
10258 +#define FC_PVER_MASK 0x3
10259 +#define FC_PVER_SHIFT 0
10260 +#define FC_TYPE_MASK 0xC
10261 +#define FC_TYPE_SHIFT 2
10262 +#define FC_SUBTYPE_MASK 0xF0
10263 +#define FC_SUBTYPE_SHIFT 4
10264 +#define FC_TODS 0x100
10265 +#define FC_TODS_SHIFT 8
10266 +#define FC_FROMDS 0x200
10267 +#define FC_FROMDS_SHIFT 9
10268 +#define FC_MOREFRAG 0x400
10269 +#define FC_MOREFRAG_SHIFT 10
10270 +#define FC_RETRY 0x800
10271 +#define FC_RETRY_SHIFT 11
10272 +#define FC_PM 0x1000
10273 +#define FC_PM_SHIFT 12
10274 +#define FC_MOREDATA 0x2000
10275 +#define FC_MOREDATA_SHIFT 13
10276 +#define FC_WEP 0x4000
10277 +#define FC_WEP_SHIFT 14
10278 +#define FC_ORDER 0x8000
10279 +#define FC_ORDER_SHIFT 15
10280 +
10281 +/* sequence control macros */
10282 +#define SEQNUM_SHIFT 4
10283 +#define FRAGNUM_MASK 0xF
10284 +
10285 +/* Frame Control type/subtype defs */
10286 +
10287 +/* FC Types */
10288 +#define FC_TYPE_MNG 0
10289 +#define FC_TYPE_CTL 1
10290 +#define FC_TYPE_DATA 2
10291 +
10292 +/* Management Subtypes */
10293 +#define FC_SUBTYPE_ASSOC_REQ 0
10294 +#define FC_SUBTYPE_ASSOC_RESP 1
10295 +#define FC_SUBTYPE_REASSOC_REQ 2
10296 +#define FC_SUBTYPE_REASSOC_RESP 3
10297 +#define FC_SUBTYPE_PROBE_REQ 4
10298 +#define FC_SUBTYPE_PROBE_RESP 5
10299 +#define FC_SUBTYPE_BEACON 8
10300 +#define FC_SUBTYPE_ATIM 9
10301 +#define FC_SUBTYPE_DISASSOC 10
10302 +#define FC_SUBTYPE_AUTH 11
10303 +#define FC_SUBTYPE_DEAUTH 12
10304 +#define FC_SUBTYPE_ACTION 13
10305 +
10306 +/* Control Subtypes */
10307 +#define FC_SUBTYPE_PS_POLL 10
10308 +#define FC_SUBTYPE_RTS 11
10309 +#define FC_SUBTYPE_CTS 12
10310 +#define FC_SUBTYPE_ACK 13
10311 +#define FC_SUBTYPE_CF_END 14
10312 +#define FC_SUBTYPE_CF_END_ACK 15
10313 +
10314 +/* Data Subtypes */
10315 +#define FC_SUBTYPE_DATA 0
10316 +#define FC_SUBTYPE_DATA_CF_ACK 1
10317 +#define FC_SUBTYPE_DATA_CF_POLL 2
10318 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
10319 +#define FC_SUBTYPE_NULL 4
10320 +#define FC_SUBTYPE_CF_ACK 5
10321 +#define FC_SUBTYPE_CF_POLL 6
10322 +#define FC_SUBTYPE_CF_ACK_POLL 7
10323 +
10324 +/* type-subtype combos */
10325 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
10326 +
10327 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
10328 +
10329 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
10330 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
10331 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
10332 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
10333 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
10334 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
10335 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
10336 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
10337 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
10338 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
10339 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
10340 +
10341 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
10342 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
10343 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
10344 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
10345 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
10346 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
10347 +
10348 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
10349 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
10350 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
10351 +
10352 +/* Management Frames */
10353 +
10354 +/* Management Frame Constants */
10355 +
10356 +/* Fixed fields */
10357 +#define DOT11_MNG_AUTH_ALGO_LEN 2
10358 +#define DOT11_MNG_AUTH_SEQ_LEN 2
10359 +#define DOT11_MNG_BEACON_INT_LEN 2
10360 +#define DOT11_MNG_CAP_LEN 2
10361 +#define DOT11_MNG_AP_ADDR_LEN 6
10362 +#define DOT11_MNG_LISTEN_INT_LEN 2
10363 +#define DOT11_MNG_REASON_LEN 2
10364 +#define DOT11_MNG_AID_LEN 2
10365 +#define DOT11_MNG_STATUS_LEN 2
10366 +#define DOT11_MNG_TIMESTAMP_LEN 8
10367 +
10368 +/* DUR/ID field in assoc resp is 0xc000 | AID */
10369 +#define DOT11_AID_MASK 0x3fff
10370 +
10371 +/* Reason Codes */
10372 +#define DOT11_RC_RESERVED 0
10373 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
10374 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
10375 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
10376 + leaving (or has left) IBSS or ESS */
10377 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
10378 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
10379 + all currently associated stations */
10380 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
10381 + nonauthenticated station */
10382 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
10383 + nonassociated station */
10384 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
10385 + leaving (or has left) BSS */
10386 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
10387 + not authenticated with responding station */
10388 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
10389 +
10390 +/* Status Codes */
10391 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
10392 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
10393 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
10394 + in the Capability Information field */
10395 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
10396 + confirm that association exists */
10397 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
10398 + the scope of this standard */
10399 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
10400 + specified authentication algorithm */
10401 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
10402 + authentication transaction sequence number
10403 + out of expected sequence */
10404 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
10405 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
10406 + for next frame in sequence */
10407 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
10408 + handle additional associated stations */
10409 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
10410 + not supporting all of the data rates in the
10411 + BSSBasicRateSet parameter */
10412 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
10413 + not supporting the Short Preamble option */
10414 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
10415 + not supporting the PBCC Modulation option */
10416 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
10417 + not supporting the Channel Agility option */
10418 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
10419 + capability is required. */
10420 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
10421 + Power Cap element is unacceptable. */
10422 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
10423 + Supported Channel element is unacceptable */
10424 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
10425 + not supporting the Short Slot Time option */
10426 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
10427 + not supporting the ER-PBCC Modulation option */
10428 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
10429 + not supporting the DSS-OFDM option */
10430 +
10431 +/* Info Elts, length of INFORMATION portion of Info Elts */
10432 +#define DOT11_MNG_DS_PARAM_LEN 1
10433 +#define DOT11_MNG_IBSS_PARAM_LEN 2
10434 +
10435 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
10436 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
10437 +#define DOT11_MNG_TIM_FIXED_LEN 3
10438 +#define DOT11_MNG_TIM_DTIM_COUNT 0
10439 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
10440 +#define DOT11_MNG_TIM_BITMAP_CTL 2
10441 +#define DOT11_MNG_TIM_PVB 3
10442 +
10443 +/* TLV defines */
10444 +#define TLV_TAG_OFF 0
10445 +#define TLV_LEN_OFF 1
10446 +#define TLV_HDR_LEN 2
10447 +#define TLV_BODY_OFF 2
10448 +
10449 +/* Management Frame Information Element IDs */
10450 +#define DOT11_MNG_SSID_ID 0
10451 +#define DOT11_MNG_RATES_ID 1
10452 +#define DOT11_MNG_FH_PARMS_ID 2
10453 +#define DOT11_MNG_DS_PARMS_ID 3
10454 +#define DOT11_MNG_CF_PARMS_ID 4
10455 +#define DOT11_MNG_TIM_ID 5
10456 +#define DOT11_MNG_IBSS_PARMS_ID 6
10457 +#define DOT11_MNG_COUNTRY_ID 7
10458 +#define DOT11_MNG_HOPPING_PARMS_ID 8
10459 +#define DOT11_MNG_HOPPING_TABLE_ID 9
10460 +#define DOT11_MNG_REQUEST_ID 10
10461 +#define DOT11_MNG_CHALLENGE_ID 16
10462 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
10463 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
10464 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
10465 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
10466 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
10467 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
10468 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
10469 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
10470 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
10471 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
10472 +#define DOT11_MNG_ERP_ID 42
10473 +#define DOT11_MNG_NONERP_ID 47
10474 +#define DOT11_MNG_EXT_RATES_ID 50
10475 +#define DOT11_MNG_WPA_ID 221
10476 +#define DOT11_MNG_PROPR_ID 221
10477 +
10478 +/* ERP info element bit values */
10479 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
10480 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
10481 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
10482 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
10483 +
10484 +/* Capability Information Field */
10485 +#define DOT11_CAP_ESS 0x0001
10486 +#define DOT11_CAP_IBSS 0x0002
10487 +#define DOT11_CAP_POLLABLE 0x0004
10488 +#define DOT11_CAP_POLL_RQ 0x0008
10489 +#define DOT11_CAP_PRIVACY 0x0010
10490 +#define DOT11_CAP_SHORT 0x0020
10491 +#define DOT11_CAP_PBCC 0x0040
10492 +#define DOT11_CAP_AGILITY 0x0080
10493 +#define DOT11_CAP_SPECTRUM 0x0100
10494 +#define DOT11_CAP_SHORTSLOT 0x0400
10495 +#define DOT11_CAP_CCK_OFDM 0x2000
10496 +
10497 +/* Action Frame Constants */
10498 +#define DOT11_ACTION_CAT_ERR_MASK 0x10
10499 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
10500 +
10501 +#define DOT11_ACTION_ID_M_REQ 0
10502 +#define DOT11_ACTION_ID_M_REP 1
10503 +#define DOT11_ACTION_ID_TPC_REQ 2
10504 +#define DOT11_ACTION_ID_TPC_REP 3
10505 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
10506 +
10507 +/* MLME Enumerations */
10508 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
10509 +#define DOT11_BSSTYPE_INDEPENDENT 1
10510 +#define DOT11_BSSTYPE_ANY 2
10511 +#define DOT11_SCANTYPE_ACTIVE 0
10512 +#define DOT11_SCANTYPE_PASSIVE 1
10513 +
10514 +/* 802.11 A PHY constants */
10515 +#define APHY_SLOT_TIME 9
10516 +#define APHY_SIFS_TIME 16
10517 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
10518 +#define APHY_PREAMBLE_TIME 16
10519 +#define APHY_SIGNAL_TIME 4
10520 +#define APHY_SYMBOL_TIME 4
10521 +#define APHY_SERVICE_NBITS 16
10522 +#define APHY_TAIL_NBITS 6
10523 +#define APHY_CWMIN 15
10524 +
10525 +/* 802.11 B PHY constants */
10526 +#define BPHY_SLOT_TIME 20
10527 +#define BPHY_SIFS_TIME 10
10528 +#define BPHY_DIFS_TIME 50
10529 +#define BPHY_PLCP_TIME 192
10530 +#define BPHY_PLCP_SHORT_TIME 96
10531 +#define BPHY_CWMIN 31
10532 +
10533 +/* 802.11 G constants */
10534 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
10535 +
10536 +#define PHY_CWMAX 1023
10537 +
10538 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
10539 +
10540 +/* dot11Counters Table - 802.11 spec., Annex D */
10541 +typedef struct d11cnt {
10542 + uint32 txfrag; /* dot11TransmittedFragmentCount */
10543 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
10544 + uint32 txfail; /* dot11FailedCount */
10545 + uint32 txretry; /* dot11RetryCount */
10546 + uint32 txretrie; /* dot11MultipleRetryCount */
10547 + uint32 rxdup; /* dot11FrameduplicateCount */
10548 + uint32 txrts; /* dot11RTSSuccessCount */
10549 + uint32 txnocts; /* dot11RTSFailureCount */
10550 + uint32 txnoack; /* dot11ACKFailureCount */
10551 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
10552 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
10553 + uint32 rxcrc; /* dot11FCSErrorCount */
10554 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
10555 + uint32 rxundec; /* dot11WEPUndecryptableCount */
10556 +} d11cnt_t;
10557 +
10558 +/* BRCM OUI */
10559 +#define BRCM_OUI "\x00\x10\x18"
10560 +
10561 +/* WPA definitions */
10562 +#define WPA_VERSION 1
10563 +#define WPA_OUI "\x00\x50\xF2"
10564 +
10565 +#define WPA_OUI_LEN 3
10566 +
10567 +/* WPA authentication modes */
10568 +#define WPA_AUTH_NONE 0 /* None */
10569 +#define WPA_AUTH_UNSPECIFIED 1 /* Unspecified authentication over 802.1X: default for WPA */
10570 +#define WPA_AUTH_PSK 2 /* Pre-shared Key over 802.1X */
10571 +#define WPA_AUTH_DISABLED 255 /* Legacy (i.e., non-WPA) */
10572 +
10573 +#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
10574 + (auth) == WPA_AUTH_UNSPECIFIED || \
10575 + (auth) == WPA_AUTH_PSK)
10576 +
10577 +
10578 +/* Key related defines */
10579 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
10580 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
10581 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
10582 +
10583 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
10584 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
10585 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
10586 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
10587 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
10588 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
10589 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
10590 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
10591 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
10592 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
10593 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
10594 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
10595 +#define AES_KEY_SIZE 16 /* size of AES key */
10596 +
10597 +#undef PACKED
10598 +#if !defined(__GNUC__)
10599 +#pragma pack()
10600 +#endif
10601 +
10602 +#endif /* _802_11_H_ */
10603 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/proto/ethernet.h
10604 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
10605 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-13 14:59:52.000000000 +0100
10606 @@ -0,0 +1,145 @@
10607 +/*******************************************************************************
10608 + * $Id$
10609 + * Copyright 2001-2003, Broadcom Corporation
10610 + * All Rights Reserved.
10611 + *
10612 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10613 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10614 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10615 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10616 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
10617 + ******************************************************************************/
10618 +
10619 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
10620 +#define _NET_ETHERNET_H_
10621 +
10622 +#ifndef _TYPEDEFS_H_
10623 +#include "typedefs.h"
10624 +#endif
10625 +
10626 +#if defined(__GNUC__)
10627 +#define PACKED __attribute__((packed))
10628 +#else
10629 +#define PACKED
10630 +#endif
10631 +
10632 +/*
10633 + * The number of bytes in an ethernet (MAC) address.
10634 + */
10635 +#define ETHER_ADDR_LEN 6
10636 +
10637 +/*
10638 + * The number of bytes in the type field.
10639 + */
10640 +#define ETHER_TYPE_LEN 2
10641 +
10642 +/*
10643 + * The number of bytes in the trailing CRC field.
10644 + */
10645 +#define ETHER_CRC_LEN 4
10646 +
10647 +/*
10648 + * The length of the combined header.
10649 + */
10650 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
10651 +
10652 +/*
10653 + * The minimum packet length.
10654 + */
10655 +#define ETHER_MIN_LEN 64
10656 +
10657 +/*
10658 + * The minimum packet user data length.
10659 + */
10660 +#define ETHER_MIN_DATA 46
10661 +
10662 +/*
10663 + * The maximum packet length.
10664 + */
10665 +#define ETHER_MAX_LEN 1518
10666 +
10667 +/*
10668 + * The maximum packet user data length.
10669 + */
10670 +#define ETHER_MAX_DATA 1500
10671 +
10672 +/*
10673 + * Used to uniquely identify a 802.1q VLAN-tagged header.
10674 + */
10675 +#define VLAN_TAG 0x8100
10676 +
10677 +/*
10678 + * Located after dest & src address in ether header.
10679 + */
10680 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
10681 +
10682 +/*
10683 + * 4 bytes of vlan field info.
10684 + */
10685 +#define VLAN_FIELDS_SIZE 4
10686 +
10687 +/* location of pri bits in 16-bit vlan fields */
10688 +#define VLAN_PRI_SHIFT 13
10689 +
10690 +/* 3 bits of priority */
10691 +#define VLAN_PRI_MASK 7
10692 +
10693 +/* 802.1X ethertype */
10694 +#define ETHER_TYPE_802_1X 0x888e
10695 +
10696 +/*
10697 + * A macro to validate a length with
10698 + */
10699 +#define ETHER_IS_VALID_LEN(foo) \
10700 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
10701 +
10702 +
10703 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
10704 +/*
10705 + * Structure of a 10Mb/s Ethernet header.
10706 + */
10707 +struct ether_header {
10708 + uint8 ether_dhost[ETHER_ADDR_LEN];
10709 + uint8 ether_shost[ETHER_ADDR_LEN];
10710 + uint16 ether_type;
10711 +} PACKED ;
10712 +
10713 +/*
10714 + * Structure of a 48-bit Ethernet address.
10715 + */
10716 +struct ether_addr {
10717 + uint8 octet[ETHER_ADDR_LEN];
10718 +} PACKED ;
10719 +#endif
10720 +
10721 +/*
10722 + * Takes a pointer, returns true if a 48-bit multicast address
10723 + * (including broadcast, since it is all ones)
10724 + */
10725 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
10726 +
10727 +/*
10728 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
10729 + */
10730 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
10731 + ((uint8 *)(ea))[1] & \
10732 + ((uint8 *)(ea))[2] & \
10733 + ((uint8 *)(ea))[3] & \
10734 + ((uint8 *)(ea))[4] & \
10735 + ((uint8 *)(ea))[5]) == 0xff)
10736 +
10737 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
10738 +
10739 +/*
10740 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
10741 + */
10742 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
10743 + ((uint8 *)(ea))[1] | \
10744 + ((uint8 *)(ea))[2] | \
10745 + ((uint8 *)(ea))[3] | \
10746 + ((uint8 *)(ea))[4] | \
10747 + ((uint8 *)(ea))[5]) == 0)
10748 +
10749 +#undef PACKED
10750 +
10751 +#endif /* _NET_ETHERNET_H_ */
10752 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/rts/crc.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/rts/crc.h
10753 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
10754 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/rts/crc.h 2005-12-13 14:59:52.000000000 +0100
10755 @@ -0,0 +1,69 @@
10756 +/*******************************************************************************
10757 + * $Id$
10758 + * Copyright 2001-2003, Broadcom Corporation
10759 + * All Rights Reserved.
10760 + *
10761 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10762 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10763 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10764 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10765 + * crc.h - a function to compute crc for iLine10 headers
10766 + ******************************************************************************/
10767 +
10768 +#ifndef _RTS_CRC_H_
10769 +#define _RTS_CRC_H_ 1
10770 +
10771 +#include "typedefs.h"
10772 +
10773 +#ifdef __cplusplus
10774 +extern "C" {
10775 +#endif
10776 +
10777 +
10778 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
10779 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
10780 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
10781 +
10782 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
10783 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
10784 +
10785 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
10786 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
10787 +
10788 +void hcs(uint8 *, uint);
10789 +uint8 crc8(uint8 *, uint, uint8);
10790 +uint16 crc16(uint8 *, uint, uint16);
10791 +uint32 crc32(uint8 *, uint, uint32);
10792 +
10793 +/* macros for common usage */
10794 +
10795 +#define APPEND_CRC8(pbytes, nbytes) \
10796 +do { \
10797 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
10798 + (pbytes)[(nbytes)] = tmp; \
10799 + (nbytes) += 1; \
10800 +} while (0)
10801 +
10802 +#define APPEND_CRC16(pbytes, nbytes) \
10803 +do { \
10804 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
10805 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
10806 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
10807 + (nbytes) += 2; \
10808 +} while (0)
10809 +
10810 +#define APPEND_CRC32(pbytes, nbytes) \
10811 +do { \
10812 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
10813 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
10814 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
10815 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
10816 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
10817 + (nbytes) += 4; \
10818 +} while (0)
10819 +
10820 +#ifdef __cplusplus
10821 +}
10822 +#endif
10823 +
10824 +#endif /* _RTS_CRC_H_ */
10825 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/s5.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/s5.h
10826 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
10827 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/s5.h 2005-12-13 14:59:52.000000000 +0100
10828 @@ -0,0 +1,103 @@
10829 +#ifndef _S5_H_
10830 +#define _S5_H_
10831 +/*
10832 + * Copyright 2003, Broadcom Corporation
10833 + * All Rights Reserved.
10834 + *
10835 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
10836 + * and MIPS3301 (R4K) System Address Space
10837 + *
10838 + * This program is free software; you can redistribute it and/or
10839 + * modify it under the terms of the GNU General Public License as
10840 + * published by the Free Software Foundation, located in the file
10841 + * LICENSE.
10842 + *
10843 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
10844 + *
10845 + */
10846 +
10847 +/* BCM5365 Address map */
10848 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
10849 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
10850 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
10851 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
10852 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
10853 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
10854 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
10855 +
10856 +/* BCM5365 Core register space */
10857 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
10858 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
10859 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
10860 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
10861 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
10862 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
10863 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
10864 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
10865 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
10866 +
10867 +/* COM Ports 1/2 */
10868 +#define BCM5365_UART (BCM5365_REG_UARTS)
10869 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
10870 +
10871 +/* Registers common to MIPS33 Core used in 5365 */
10872 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
10873 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
10874 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
10875 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
10876 +
10877 +/* Internal Core Sonics Backplane Devices */
10878 +#define INTERNAL_UART_COM1 BCM5365_UART
10879 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
10880 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
10881 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
10882 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
10883 +#define SB_REG_USB BCM5365_REG_USB
10884 +#define SB_REG_PCI BCM5365_REG_PCI
10885 +#define SB_REG_MIPS BCM5365_REG_MIPS33
10886 +#define SB_REG_MEMC BCM5365_REG_MEMC
10887 +#define SB_REG_MEMC_OFF 0x6000
10888 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
10889 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
10890 +
10891 +/*
10892 + * XXX
10893 + * 5365-specific backplane interrupt flag numbers. This should be done
10894 + * dynamically instead.
10895 + */
10896 +#define SBFLAG_PCI 0
10897 +#define SBFLAG_ENET0 1
10898 +#define SBFLAG_ILINE20 2
10899 +#define SBFLAG_CODEC 3
10900 +#define SBFLAG_USB 4
10901 +#define SBFLAG_EXTIF 5
10902 +#define SBFLAG_ENET1 6
10903 +
10904 +/* BCM95365 Local Bus devices */
10905 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
10906 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
10907 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
10908 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
10909 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
10910 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
10911 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
10912 +
10913 +/* Write to DLR2416 VFD Display character RAM */
10914 +#define LED_REG(x) \
10915 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
10916 +
10917 +#ifdef CONFIG_VSIM
10918 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
10919 + } while (0)
10920 +#else
10921 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
10922 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
10923 + *((int *)0xa0002ff8) = (trval); } while (0)
10924 +#endif
10925 +
10926 +/* BCM9536R Local Bus devices */
10927 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
10928 +
10929 +
10930 +
10931 +#endif /*!_S5_H_ */
10932 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbchipc.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbchipc.h
10933 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
10934 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbchipc.h 2005-12-13 14:59:52.000000000 +0100
10935 @@ -0,0 +1,281 @@
10936 +/*
10937 + * SiliconBackplane Chipcommon core hardware definitions.
10938 + *
10939 + * The chipcommon core provides chip identification, SB control,
10940 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
10941 + * gpio interface, extbus, and support for serial and parallel flashes.
10942 + *
10943 + * Copyright 2001-2003, Broadcom Corporation
10944 + * All Rights Reserved.
10945 + *
10946 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10947 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10948 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10949 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10950 + *
10951 + * $Id$
10952 + */
10953 +
10954 +#ifndef _SBCHIPC_H
10955 +#define _SBCHIPC_H
10956 +
10957 +
10958 +/* cpp contortions to concatenate w/arg prescan */
10959 +#ifndef PAD
10960 +#define _PADLINE(line) pad ## line
10961 +#define _XSTR(line) _PADLINE(line)
10962 +#define PAD _XSTR(__LINE__)
10963 +#endif /* PAD */
10964 +
10965 +typedef volatile struct {
10966 + uint32 chipid; /* 0x0 */
10967 + uint32 capabilities;
10968 + uint32 corecontrol; /* corerev >= 1 */
10969 + uint32 PAD[5];
10970 +
10971 + /* Interrupt control */
10972 + uint32 intstatus; /* 0x20 */
10973 + uint32 intmask;
10974 + uint32 PAD[6];
10975 +
10976 + /* serial flash interface registers */
10977 + uint32 flashcontrol; /* 0x40 */
10978 + uint32 flashaddress;
10979 + uint32 flashdata;
10980 + uint32 PAD[1];
10981 +
10982 + /* Silicon backplane configuration broadcast control */
10983 + uint32 broadcastaddress;
10984 + uint32 broadcastdata;
10985 + uint32 PAD[2];
10986 +
10987 + /* gpio - cleared only by power-on-reset */
10988 + uint32 gpioin; /* 0x60 */
10989 + uint32 gpioout;
10990 + uint32 gpioouten;
10991 + uint32 gpiocontrol;
10992 + uint32 gpiointpolarity;
10993 + uint32 gpiointmask;
10994 + uint32 PAD[2];
10995 +
10996 + /* Watchdog timer */
10997 + uint32 watchdog; /* 0x80 */
10998 + uint32 PAD[3];
10999 +
11000 + /* clock control */
11001 + uint32 clockcontrol_n; /* 0x90 */
11002 + uint32 clockcontrol_sb; /* aka m0 */
11003 + uint32 clockcontrol_pci; /* aka m1 */
11004 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
11005 + uint32 clockcontrol_mips; /* aka m3 */
11006 + uint32 uart_clkdiv; /* corerev >= 3 */
11007 + uint32 PAD[2];
11008 +
11009 + /* pll delay registers (corerev >= 4) */
11010 + uint32 pll_on_delay; /* 0xb0 */
11011 + uint32 fref_sel_delay;
11012 + uint32 slow_clk_ctl;
11013 + uint32 PAD[17];
11014 +
11015 + /* ExtBus control registers (corerev >= 3) */
11016 + uint32 cs01config; /* 0x100 */
11017 + uint32 cs01memwaitcnt;
11018 + uint32 cs01attrwaitcnt;
11019 + uint32 cs01iowaitcnt;
11020 + uint32 cs23config;
11021 + uint32 cs23memwaitcnt;
11022 + uint32 cs23attrwaitcnt;
11023 + uint32 cs23iowaitcnt;
11024 + uint32 cs4config;
11025 + uint32 cs4waitcnt;
11026 + uint32 parallelflashconfig;
11027 + uint32 parallelflashwaitcnt;
11028 + uint32 PAD[116];
11029 +
11030 + /* uarts */
11031 + uint8 uart0data; /* 0x300 */
11032 + uint8 uart0imr;
11033 + uint8 uart0fcr;
11034 + uint8 uart0lcr;
11035 + uint8 uart0mcr;
11036 + uint8 uart0lsr;
11037 + uint8 uart0msr;
11038 + uint8 uart0scratch;
11039 + uint8 PAD[248]; /* corerev >= 1 */
11040 +
11041 + uint8 uart1data; /* 0x400 */
11042 + uint8 uart1imr;
11043 + uint8 uart1fcr;
11044 + uint8 uart1lcr;
11045 + uint8 uart1mcr;
11046 + uint8 uart1lsr;
11047 + uint8 uart1msr;
11048 + uint8 uart1scratch;
11049 +} chipcregs_t;
11050 +
11051 +/* chipid */
11052 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
11053 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
11054 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
11055 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
11056 +#define CID_PKG_SHIFT 20 /* Package Option shift */
11057 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
11058 +#define CID_CC_SHIFT 24
11059 +
11060 +/* capabilities */
11061 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
11062 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
11063 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
11064 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
11065 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
11066 +#define CAP_EXTBUS 0x00000040 /* External bus present */
11067 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
11068 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
11069 +#define CAP_PWR_CTL 0x00040000 /* Power control */
11070 +
11071 +/* PLL type */
11072 +#define PLL_NONE 0x00000000
11073 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
11074 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
11075 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
11076 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
11077 +
11078 +/* corecontrol */
11079 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
11080 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
11081 +
11082 +/* intstatus/intmask */
11083 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
11084 +
11085 +/* slow_clk_ctl */
11086 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
11087 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
11088 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
11089 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
11090 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
11091 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
11092 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
11093 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
11094 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
11095 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
11096 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
11097 +#define SCC_CD_SHF 16 /* CLockDivider shift */
11098 +
11099 +/* clockcontrol_n */
11100 +#define CN_N1_MASK 0x3f /* n1 control */
11101 +#define CN_N2_MASK 0x3f00 /* n2 control */
11102 +#define CN_N2_SHIFT 8
11103 +
11104 +/* clockcontrol_sb/pci/uart */
11105 +#define CC_M1_MASK 0x3f /* m1 control */
11106 +#define CC_M2_MASK 0x3f00 /* m2 control */
11107 +#define CC_M2_SHIFT 8
11108 +#define CC_M3_MASK 0x3f0000 /* m3 control */
11109 +#define CC_M3_SHIFT 16
11110 +#define CC_MC_MASK 0x1f000000 /* mux control */
11111 +#define CC_MC_SHIFT 24
11112 +
11113 +/* N3M Clock control values for 125Mhz */
11114 +#define CC_125_N 0x0802 /* Default values for bcm4310 */
11115 +#define CC_125_M 0x04020009
11116 +#define CC_125_M25 0x11090009
11117 +#define CC_125_M33 0x11090005
11118 +
11119 +/* N3M Clock control magic field values */
11120 +#define CC_F6_2 0x02 /* A factor of 2 in */
11121 +#define CC_F6_3 0x03 /* 6-bit fields like */
11122 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
11123 +#define CC_F6_5 0x09
11124 +#define CC_F6_6 0x11
11125 +#define CC_F6_7 0x21
11126 +
11127 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
11128 +
11129 +#define CC_MC_BYPASS 0x08
11130 +#define CC_MC_M1 0x04
11131 +#define CC_MC_M1M2 0x02
11132 +#define CC_MC_M1M2M3 0x01
11133 +#define CC_MC_M1M3 0x11
11134 +
11135 +/* Type 2 Clock control magic field values */
11136 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
11137 +#define CC_T2M2_BIAS 3 /* m2 bias */
11138 +
11139 +#define CC_T2MC_M1BYP 1
11140 +#define CC_T2MC_M2BYP 2
11141 +#define CC_T2MC_M3BYP 4
11142 +
11143 +/* Common clock base */
11144 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq */
11145 +
11146 +/* Flash types in the chipcommon capabilities register */
11147 +#define FLASH_NONE 0x000 /* No flash */
11148 +#define SFLASH_ST 0x100 /* ST serial flash */
11149 +#define SFLASH_AT 0x200 /* Atmel serial flash */
11150 +#define PFLASH 0x700 /* Parallel flash */
11151 +
11152 +/* Bits in the config registers */
11153 +#define CC_CFG_EN 0x0001 /* Enable */
11154 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
11155 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
11156 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
11157 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
11158 +#define CC_CFG_EM_IDE 0x000a /* IDE */
11159 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
11160 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
11161 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
11162 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
11163 +
11164 +/* Start/busy bit in flashcontrol */
11165 +#define SFLASH_START 0x80000000
11166 +#define SFLASH_BUSY SFLASH_START
11167 +
11168 +/* flashcontrol opcodes for ST flashes */
11169 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
11170 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
11171 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
11172 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
11173 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
11174 +#define SFLASH_ST_PP 0x0302 /* Page Program */
11175 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
11176 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
11177 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
11178 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
11179 +
11180 +/* Status register bits for ST flashes */
11181 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
11182 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
11183 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
11184 +#define SFLASH_ST_BP_SHIFT 2
11185 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
11186 +
11187 +/* flashcontrol opcodes for Atmel flashes */
11188 +#define SFLASH_AT_READ 0x07e8
11189 +#define SFLASH_AT_PAGE_READ 0x07d2
11190 +#define SFLASH_AT_BUF1_READ
11191 +#define SFLASH_AT_BUF2_READ
11192 +#define SFLASH_AT_STATUS 0x01d7
11193 +#define SFLASH_AT_BUF1_WRITE 0x0384
11194 +#define SFLASH_AT_BUF2_WRITE 0x0387
11195 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
11196 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
11197 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
11198 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
11199 +#define SFLASH_AT_PAGE_ERASE 0x0281
11200 +#define SFLASH_AT_BLOCK_ERASE 0x0250
11201 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
11202 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
11203 +#define SFLASH_AT_BUF1_LOAD 0x0253
11204 +#define SFLASH_AT_BUF2_LOAD 0x0255
11205 +#define SFLASH_AT_BUF1_COMPARE 0x0260
11206 +#define SFLASH_AT_BUF2_COMPARE 0x0261
11207 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
11208 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
11209 +
11210 +/* Status register bits for Atmel flashes */
11211 +#define SFLASH_AT_READY 0x80
11212 +#define SFLASH_AT_MISMATCH 0x40
11213 +#define SFLASH_AT_ID_MASK 0x38
11214 +#define SFLASH_AT_ID_SHIFT 3
11215 +
11216 +#endif /* _SBCHIPC_H */
11217 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbconfig.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbconfig.h
11218 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
11219 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbconfig.h 2005-12-13 14:59:52.000000000 +0100
11220 @@ -0,0 +1,296 @@
11221 +/*
11222 + * Broadcom SiliconBackplane hardware register definitions.
11223 + *
11224 + * Copyright 2001-2003, Broadcom Corporation
11225 + * All Rights Reserved.
11226 + *
11227 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11228 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11229 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11230 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11231 + * $Id$
11232 + */
11233 +
11234 +#ifndef _SBCONFIG_H
11235 +#define _SBCONFIG_H
11236 +
11237 +/* cpp contortions to concatenate w/arg prescan */
11238 +#ifndef PAD
11239 +#define _PADLINE(line) pad ## line
11240 +#define _XSTR(line) _PADLINE(line)
11241 +#define PAD _XSTR(__LINE__)
11242 +#endif
11243 +
11244 +/*
11245 + * SiliconBackplane Address Map.
11246 + * All regions may not exist on all chips.
11247 + */
11248 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
11249 +#define SB_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
11250 +#define SB_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
11251 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
11252 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
11253 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
11254 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
11255 +#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
11256 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
11257 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
11258 +
11259 +/* enumeration space related defs */
11260 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
11261 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
11262 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
11263 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
11264 +
11265 +/* mips address */
11266 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
11267 +
11268 +/*
11269 + * Sonics Configuration Space Registers.
11270 + */
11271 +#ifdef _LANGUAGE_ASSEMBLY
11272 +
11273 +#define SBIPSFLAG 0x08
11274 +#define SBTPSFLAG 0x18
11275 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
11276 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
11277 +#define SBADMATCH3 0x60
11278 +#define SBADMATCH2 0x68
11279 +#define SBADMATCH1 0x70
11280 +#define SBIMSTATE 0x90
11281 +#define SBINTVEC 0x94
11282 +#define SBTMSTATELOW 0x98
11283 +#define SBTMSTATEHIGH 0x9c
11284 +#define SBBWA0 0xa0
11285 +#define SBIMCONFIGLOW 0xa8
11286 +#define SBIMCONFIGHIGH 0xac
11287 +#define SBADMATCH0 0xb0
11288 +#define SBTMCONFIGLOW 0xb8
11289 +#define SBTMCONFIGHIGH 0xbc
11290 +#define SBBCONFIG 0xc0
11291 +#define SBBSTATE 0xc8
11292 +#define SBACTCNFG 0xd8
11293 +#define SBFLAGST 0xe8
11294 +#define SBIDLOW 0xf8
11295 +#define SBIDHIGH 0xfc
11296 +
11297 +
11298 +#else
11299 +
11300 +typedef volatile struct _sbconfig {
11301 + uint32 PAD[2];
11302 + uint32 sbipsflag; /* initiator port ocp slave flag */
11303 + uint32 PAD[3];
11304 + uint32 sbtpsflag; /* target port ocp slave flag */
11305 + uint32 PAD[11];
11306 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
11307 + uint32 PAD;
11308 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
11309 + uint32 PAD[3];
11310 + uint32 sbadmatch3; /* address match3 */
11311 + uint32 PAD;
11312 + uint32 sbadmatch2; /* address match2 */
11313 + uint32 PAD;
11314 + uint32 sbadmatch1; /* address match1 */
11315 + uint32 PAD[7];
11316 + uint32 sbimstate; /* initiator agent state */
11317 + uint32 sbintvec; /* interrupt mask */
11318 + uint32 sbtmstatelow; /* target state */
11319 + uint32 sbtmstatehigh; /* target state */
11320 + uint32 sbbwa0; /* bandwidth allocation table0 */
11321 + uint32 PAD;
11322 + uint32 sbimconfiglow; /* initiator configuration */
11323 + uint32 sbimconfighigh; /* initiator configuration */
11324 + uint32 sbadmatch0; /* address match0 */
11325 + uint32 PAD;
11326 + uint32 sbtmconfiglow; /* target configuration */
11327 + uint32 sbtmconfighigh; /* target configuration */
11328 + uint32 sbbconfig; /* broadcast configuration */
11329 + uint32 PAD;
11330 + uint32 sbbstate; /* broadcast state */
11331 + uint32 PAD[3];
11332 + uint32 sbactcnfg; /* activate configuration */
11333 + uint32 PAD[3];
11334 + uint32 sbflagst; /* current sbflags */
11335 + uint32 PAD[3];
11336 + uint32 sbidlow; /* identification */
11337 + uint32 sbidhigh; /* identification */
11338 +} sbconfig_t;
11339 +
11340 +#endif /* _LANGUAGE_ASSEMBLY */
11341 +
11342 +/* sbipsflag */
11343 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
11344 +#define SBIPS_INT1_SHIFT 0
11345 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
11346 +#define SBIPS_INT2_SHIFT 8
11347 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
11348 +#define SBIPS_INT3_SHIFT 16
11349 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
11350 +#define SBIPS_INT4_SHIFT 24
11351 +
11352 +/* sbtpsflag */
11353 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
11354 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
11355 +
11356 +/* sbtmerrlog */
11357 +#define SBTMEL_CM 0x00000007 /* command */
11358 +#define SBTMEL_CI 0x0000ff00 /* connection id */
11359 +#define SBTMEL_EC 0x0f000000 /* error code */
11360 +#define SBTMEL_ME 0x80000000 /* multiple error */
11361 +
11362 +/* sbimstate */
11363 +#define SBIM_PC 0xf /* pipecount */
11364 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
11365 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
11366 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
11367 +#define SBIM_AP_TK 0x20 /* use token only */
11368 +#define SBIM_AP_RSV 0x30 /* reserved */
11369 +#define SBIM_IBE 0x20000 /* inbanderror */
11370 +#define SBIM_TO 0x40000 /* timeout */
11371 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
11372 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
11373 +
11374 +/* sbtmstatelow */
11375 +#define SBTML_RESET 0x1 /* reset */
11376 +#define SBTML_REJ 0x2 /* reject */
11377 +#define SBTML_CLK 0x10000 /* clock enable */
11378 +#define SBTML_FGC 0x20000 /* force gated clocks on */
11379 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
11380 +#define SBTML_PE 0x40000000 /* pme enable */
11381 +#define SBTML_BE 0x80000000 /* bist enable */
11382 +
11383 +/* sbtmstatehigh */
11384 +#define SBTMH_SERR 0x1 /* serror */
11385 +#define SBTMH_INT 0x2 /* interrupt */
11386 +#define SBTMH_BUSY 0x4 /* busy */
11387 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
11388 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
11389 +#define SBTMH_GCR 0x20000000 /* gated clock request */
11390 +#define SBTMH_BISTF 0x40000000 /* bist failed */
11391 +#define SBTMH_BISTD 0x80000000 /* bist done */
11392 +
11393 +/* sbbwa0 */
11394 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
11395 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
11396 +#define SBBWA_TAB1_SHIFT 16
11397 +
11398 +/* sbimconfiglow */
11399 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
11400 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
11401 +#define SBIMCL_RTO_SHIFT 4
11402 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
11403 +#define SBIMCL_CID_SHIFT 16
11404 +
11405 +/* sbimconfighigh */
11406 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
11407 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
11408 +#define SBIMCH_TEM_SHIFT 4
11409 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
11410 +#define SBIMCH_BEM_SHIFT 6
11411 +
11412 +/* sbadmatch0 */
11413 +#define SBAM_TYPE_MASK 0x3 /* address type */
11414 +#define SBAM_AD64 0x4 /* reserved */
11415 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
11416 +#define SBAM_ADINT0_SHIFT 3
11417 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
11418 +#define SBAM_ADINT1_SHIFT 3
11419 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
11420 +#define SBAM_ADINT2_SHIFT 3
11421 +#define SBAM_ADEN 0x400 /* enable */
11422 +#define SBAM_ADNEG 0x800 /* negative decode */
11423 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
11424 +#define SBAM_BASE0_SHIFT 8
11425 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
11426 +#define SBAM_BASE1_SHIFT 12
11427 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
11428 +#define SBAM_BASE2_SHIFT 16
11429 +
11430 +/* sbtmconfiglow */
11431 +#define SBTMCL_CD_MASK 0xff /* clock divide */
11432 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
11433 +#define SBTMCL_CO_SHIFT 11
11434 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
11435 +#define SBTMCL_IF_SHIFT 18
11436 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
11437 +#define SBTMCL_IM_SHIFT 24
11438 +
11439 +/* sbtmconfighigh */
11440 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
11441 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
11442 +#define SBTMCH_RM_SHIFT 2
11443 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
11444 +#define SBTMCH_SM_SHIFT 4
11445 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
11446 +#define SBTMCH_EM_SHIFT 8
11447 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
11448 +#define SBTMCH_IM_SHIFT 10
11449 +
11450 +/* sbbconfig */
11451 +#define SBBC_LAT_MASK 0x3 /* sb latency */
11452 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
11453 +#define SBBC_MAX0_SHIFT 16
11454 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
11455 +#define SBBC_MAX1_SHIFT 20
11456 +
11457 +/* sbbstate */
11458 +#define SBBS_SRD 0x1 /* st reg disable */
11459 +#define SBBS_HRD 0x2 /* hold reg disable */
11460 +
11461 +/* sbidlow */
11462 +#define SBIDL_CS_MASK 0x3 /* config space */
11463 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
11464 +#define SBIDL_AR_SHIFT 3
11465 +#define SBIDL_SYNCH 0x40 /* sync */
11466 +#define SBIDL_INIT 0x80 /* initiator */
11467 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
11468 +#define SBIDL_MINLAT_SHIFT 8
11469 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
11470 +#define SBIDL_MAXLAT_SHIFT 12
11471 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
11472 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
11473 +#define SBIDL_CW_SHIFT 18
11474 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
11475 +#define SBIDL_TP_SHIFT 20
11476 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
11477 +#define SBIDL_IP_SHIFT 24
11478 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
11479 +#define SBIDL_RV_SHIFT 28
11480 +
11481 +/* sbidhigh */
11482 +#define SBIDH_RC_MASK 0xf /* revision code*/
11483 +#define SBIDH_CC_MASK 0xfff0 /* core code */
11484 +#define SBIDH_CC_SHIFT 4
11485 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
11486 +#define SBIDH_VC_SHIFT 16
11487 +
11488 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
11489 +
11490 +/* vendor codes */
11491 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
11492 +
11493 +/* core codes */
11494 +#define SB_CC 0x800 /* chipcommon core */
11495 +#define SB_ILINE20 0x801 /* iline20 core */
11496 +#define SB_SDRAM 0x803 /* sdram core */
11497 +#define SB_PCI 0x804 /* pci core */
11498 +#define SB_MIPS 0x805 /* mips core */
11499 +#define SB_ENET 0x806 /* enet mac core */
11500 +#define SB_CODEC 0x807 /* v90 codec core */
11501 +#define SB_USB 0x808 /* usb 1.1 host/device core */
11502 +#define SB_ILINE100 0x80a /* iline100 core */
11503 +#define SB_IPSEC 0x80b /* ipsec core */
11504 +#define SB_PCMCIA 0x80d /* pcmcia core */
11505 +#define SB_MEMC 0x80f /* memc sdram core */
11506 +#define SB_EXTIF 0x811 /* external interface core */
11507 +#define SB_D11 0x812 /* 802.11 MAC core */
11508 +#define SB_MIPS33 0x816 /* mips3302 core */
11509 +#define SB_USB11H 0x817 /* usb 1.1 host core */
11510 +#define SB_USB11D 0x818 /* usb 1.1 device core */
11511 +#define SB_USB20H 0x819 /* usb 2.0 host core */
11512 +#define SB_USB20D 0x81A /* usb 2.0 device core */
11513 +#define SB_SDIOH 0x81B /* sdio host core */
11514 +#define SB_ROBO 0x81C /* robo switch core */
11515 +
11516 +#endif /* _SBCONFIG_H */
11517 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbextif.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbextif.h
11518 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
11519 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbextif.h 2005-12-13 14:59:52.000000000 +0100
11520 @@ -0,0 +1,242 @@
11521 +/*
11522 + * Hardware-specific External Interface I/O core definitions
11523 + * for the BCM47xx family of SiliconBackplane-based chips.
11524 + *
11525 + * The External Interface core supports a total of three external chip selects
11526 + * supporting external interfaces. One of the external chip selects is
11527 + * used for Flash, one is used for PCMCIA, and the other may be
11528 + * programmed to support either a synchronous interface or an
11529 + * asynchronous interface. The asynchronous interface can be used to
11530 + * support external devices such as UARTs and the BCM2019 Bluetooth
11531 + * baseband processor.
11532 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
11533 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
11534 + *
11535 + * Copyright 2001-2003, Broadcom Corporation
11536 + * All Rights Reserved.
11537 + *
11538 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11539 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11540 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11541 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11542 + * $Id$
11543 + */
11544 +
11545 +#ifndef _SBEXTIF_H
11546 +#define _SBEXTIF_H
11547 +
11548 +/* external interface address space */
11549 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
11550 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
11551 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
11552 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
11553 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
11554 +
11555 +/* cpp contortions to concatenate w/arg prescan */
11556 +#ifndef PAD
11557 +#define _PADLINE(line) pad ## line
11558 +#define _XSTR(line) _PADLINE(line)
11559 +#define PAD _XSTR(__LINE__)
11560 +#endif /* PAD */
11561 +
11562 +/*
11563 + * The multiple instances of output and output enable registers
11564 + * are present to allow driver software for multiple cores to control
11565 + * gpio outputs without needing to share a single register pair.
11566 + */
11567 +struct gpiouser {
11568 + uint32 out;
11569 + uint32 outen;
11570 +};
11571 +#define NGPIOUSER 5
11572 +
11573 +typedef volatile struct {
11574 + uint32 corecontrol;
11575 + uint32 extstatus;
11576 + uint32 PAD[2];
11577 +
11578 + /* pcmcia control registers */
11579 + uint32 pcmcia_config;
11580 + uint32 pcmcia_memwait;
11581 + uint32 pcmcia_attrwait;
11582 + uint32 pcmcia_iowait;
11583 +
11584 + /* programmable interface control registers */
11585 + uint32 prog_config;
11586 + uint32 prog_waitcount;
11587 +
11588 + /* flash control registers */
11589 + uint32 flash_config;
11590 + uint32 flash_waitcount;
11591 + uint32 PAD[4];
11592 +
11593 + uint32 watchdog;
11594 +
11595 + /* clock control */
11596 + uint32 clockcontrol_n;
11597 + uint32 clockcontrol_sb;
11598 + uint32 clockcontrol_pci;
11599 + uint32 clockcontrol_mii;
11600 + uint32 PAD[3];
11601 +
11602 + /* gpio */
11603 + uint32 gpioin;
11604 + struct gpiouser gpio[NGPIOUSER];
11605 + uint32 PAD;
11606 + uint32 ejtagouten;
11607 + uint32 gpiointpolarity;
11608 + uint32 gpiointmask;
11609 + uint32 PAD[153];
11610 +
11611 + uint8 uartdata;
11612 + uint8 PAD[3];
11613 + uint8 uartimer;
11614 + uint8 PAD[3];
11615 + uint8 uartfcr;
11616 + uint8 PAD[3];
11617 + uint8 uartlcr;
11618 + uint8 PAD[3];
11619 + uint8 uartmcr;
11620 + uint8 PAD[3];
11621 + uint8 uartlsr;
11622 + uint8 PAD[3];
11623 + uint8 uartmsr;
11624 + uint8 PAD[3];
11625 + uint8 uartscratch;
11626 + uint8 PAD[3];
11627 +} extifregs_t;
11628 +
11629 +/* corecontrol */
11630 +#define CC_UE (1 << 0) /* uart enable */
11631 +
11632 +/* extstatus */
11633 +#define ES_EM (1 << 0) /* endian mode (ro) */
11634 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
11635 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
11636 +
11637 +/* gpio bit mask */
11638 +#define GPIO_BIT0 (1 << 0)
11639 +#define GPIO_BIT1 (1 << 1)
11640 +#define GPIO_BIT2 (1 << 2)
11641 +#define GPIO_BIT3 (1 << 3)
11642 +#define GPIO_BIT4 (1 << 4)
11643 +#define GPIO_BIT5 (1 << 5)
11644 +#define GPIO_BIT6 (1 << 6)
11645 +#define GPIO_BIT7 (1 << 7)
11646 +
11647 +
11648 +/* pcmcia/prog/flash_config */
11649 +#define CF_EN (1 << 0) /* enable */
11650 +#define CF_EM_MASK 0xe /* mode */
11651 +#define CF_EM_SHIFT 1
11652 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
11653 +#define CF_EM_SYNC 0x2 /* synchronous mode */
11654 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
11655 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
11656 +#define CF_BS (1 << 5) /* byteswap */
11657 +#define CF_CD_MASK 0xc0 /* clock divider */
11658 +#define CF_CD_SHIFT 6
11659 +#define CF_CD_DIV2 0x0 /* backplane/2 */
11660 +#define CF_CD_DIV3 0x40 /* backplane/3 */
11661 +#define CF_CD_DIV4 0x80 /* backplane/4 */
11662 +#define CF_CE (1 << 8) /* clock enable */
11663 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
11664 +
11665 +/* pcmcia_memwait */
11666 +#define PM_W0_MASK 0x3f /* waitcount0 */
11667 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
11668 +#define PM_W1_SHIFT 8
11669 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
11670 +#define PM_W2_SHIFT 16
11671 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
11672 +#define PM_W3_SHIFT 24
11673 +
11674 +/* pcmcia_attrwait */
11675 +#define PA_W0_MASK 0x3f /* waitcount0 */
11676 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
11677 +#define PA_W1_SHIFT 8
11678 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
11679 +#define PA_W2_SHIFT 16
11680 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
11681 +#define PA_W3_SHIFT 24
11682 +
11683 +/* pcmcia_iowait */
11684 +#define PI_W0_MASK 0x3f /* waitcount0 */
11685 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
11686 +#define PI_W1_SHIFT 8
11687 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
11688 +#define PI_W2_SHIFT 16
11689 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
11690 +#define PI_W3_SHIFT 24
11691 +
11692 +/* prog_waitcount */
11693 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
11694 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
11695 +#define PW_W1_SHIFT 8
11696 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
11697 +#define PW_W2_SHIFT 16
11698 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
11699 +#define PW_W3_SHIFT 24
11700 +
11701 +#define PW_W0 0x0000000c
11702 +#define PW_W1 0x00000a00
11703 +#define PW_W2 0x00020000
11704 +#define PW_W3 0x01000000
11705 +
11706 +/* flash_waitcount */
11707 +#define FW_W0_MASK 0x1f /* waitcount0 */
11708 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
11709 +#define FW_W1_SHIFT 8
11710 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
11711 +#define FW_W2_SHIFT 16
11712 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
11713 +#define FW_W3_SHIFT 24
11714 +
11715 +/* watchdog */
11716 +#define WATCHDOG_CLOCK 48000000 /* Hz */
11717 +
11718 +/* clockcontrol_n */
11719 +#define CN_N1_MASK 0x3f /* n1 control */
11720 +#define CN_N2_MASK 0x3f00 /* n2 control */
11721 +#define CN_N2_SHIFT 8
11722 +
11723 +/* clockcontrol_sb/pci/mii */
11724 +#define CC_M1_MASK 0x3f /* m1 control */
11725 +#define CC_M2_MASK 0x3f00 /* m2 control */
11726 +#define CC_M2_SHIFT 8
11727 +#define CC_M3_MASK 0x3f0000 /* m3 control */
11728 +#define CC_M3_SHIFT 16
11729 +#define CC_MC_MASK 0x1f000000 /* mux control */
11730 +#define CC_MC_SHIFT 24
11731 +
11732 +/* Clock control default values */
11733 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
11734 +#define CC_DEF_100 0x04020011
11735 +#define CC_DEF_33 0x11030011
11736 +#define CC_DEF_25 0x11050011
11737 +
11738 +/* Clock control values for 125Mhz */
11739 +#define CC_125_N 0x0802
11740 +#define CC_125_M 0x04020009
11741 +#define CC_125_M25 0x11090009
11742 +#define CC_125_M33 0x11090005
11743 +
11744 +/* Clock control magic field values */
11745 +#define CC_F6_2 0x02 /* A factor of 2 in */
11746 +#define CC_F6_3 0x03 /* 6-bit fields like */
11747 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
11748 +#define CC_F6_5 0x09
11749 +#define CC_F6_6 0x11
11750 +#define CC_F6_7 0x21
11751 +
11752 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
11753 +
11754 +#define CC_MC_BYPASS 0x08
11755 +#define CC_MC_M1 0x04
11756 +#define CC_MC_M1M2 0x02
11757 +#define CC_MC_M1M2M3 0x01
11758 +#define CC_MC_M1M3 0x11
11759 +
11760 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
11761 +
11762 +#endif /* _SBEXTIF_H */
11763 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbmemc.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbmemc.h
11764 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
11765 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbmemc.h 2005-12-13 14:59:52.000000000 +0100
11766 @@ -0,0 +1,144 @@
11767 +/*
11768 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
11769 + *
11770 + * Copyright 2001-2003, Broadcom Corporation
11771 + * All Rights Reserved.
11772 + *
11773 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11774 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11775 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11776 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11777 + * $Id$
11778 + */
11779 +
11780 +#ifndef _SBMEMC_H
11781 +#define _SBMEMC_H
11782 +
11783 +#ifdef _LANGUAGE_ASSEMBLY
11784 +
11785 +#define MEMC_CONTROL 0x00
11786 +#define MEMC_CONFIG 0x04
11787 +#define MEMC_REFRESH 0x08
11788 +#define MEMC_BISTSTAT 0x0c
11789 +#define MEMC_MODEBUF 0x10
11790 +#define MEMC_BKCLS 0x14
11791 +#define MEMC_PRIORINV 0x18
11792 +#define MEMC_DRAMTIM 0x1c
11793 +#define MEMC_INTSTAT 0x20
11794 +#define MEMC_INTMASK 0x24
11795 +#define MEMC_INTINFO 0x28
11796 +#define MEMC_NCDLCTL 0x30
11797 +#define MEMC_RDNCDLCOR 0x34
11798 +#define MEMC_WRNCDLCOR 0x38
11799 +#define MEMC_MISCDLYCTL 0x3c
11800 +#define MEMC_DQSGATENCDL 0x40
11801 +#define MEMC_SPARE 0x44
11802 +#define MEMC_TPADDR 0x48
11803 +#define MEMC_TPDATA 0x4c
11804 +#define MEMC_BARRIER 0x50
11805 +#define MEMC_CORE 0x54
11806 +
11807 +
11808 +#else
11809 +
11810 +/* Sonics side: MEMC core registers */
11811 +typedef volatile struct sbmemcregs {
11812 + uint32 control;
11813 + uint32 config;
11814 + uint32 refresh;
11815 + uint32 biststat;
11816 + uint32 modebuf;
11817 + uint32 bkcls;
11818 + uint32 priorinv;
11819 + uint32 dramtim;
11820 + uint32 intstat;
11821 + uint32 intmask;
11822 + uint32 intinfo;
11823 + uint32 reserved1;
11824 + uint32 ncdlctl;
11825 + uint32 rdncdlcor;
11826 + uint32 wrncdlcor;
11827 + uint32 miscdlyctl;
11828 + uint32 dqsgatencdl;
11829 + uint32 spare;
11830 + uint32 tpaddr;
11831 + uint32 tpdata;
11832 + uint32 barrier;
11833 + uint32 core;
11834 +} sbmemcregs_t;
11835 +
11836 +#endif
11837 +
11838 +/* MEMC Core Init values (OCP ID 0x80f) */
11839 +
11840 +/* For sdr: */
11841 +#define MEMC_SD_CONFIG_INIT 0x00048000
11842 +#define MEMC_SD_DRAMTIM_INIT 0x000754da
11843 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
11844 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
11845 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
11846 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
11847 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
11848 +#define MEMC_SD_CONTROL_INIT0 0x00000002
11849 +#define MEMC_SD_CONTROL_INIT1 0x00000008
11850 +#define MEMC_SD_CONTROL_INIT2 0x00000004
11851 +#define MEMC_SD_CONTROL_INIT3 0x00000010
11852 +#define MEMC_SD_CONTROL_INIT4 0x00000001
11853 +#define MEMC_SD_MODEBUF_INIT 0x00000000
11854 +#define MEMC_SD_REFRESH_INIT 0x0000840f
11855 +
11856 +
11857 +/* This is for SDRM8X8X4 */
11858 +#define MEMC_SDR_INIT 0x0008
11859 +#define MEMC_SDR_MODE 0x32
11860 +#define MEMC_SDR_NCDL 0x00020032
11861 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
11862 +
11863 +/* For ddr: */
11864 +#define MEMC_CONFIG_INIT 0x00048000
11865 +#define MEMC_DRAMTIM_INIT 0x000754d9
11866 +#define MEMC_RDNCDLCOR_INIT 0x00000000
11867 +#define MEMC_WRNCDLCOR_INIT 0x49351200
11868 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
11869 +#define MEMC_DQSGATENCDL_INIT 0x00030000
11870 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
11871 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
11872 +#define MEMC_NCDLCTL_INIT 0x00002001
11873 +#define MEMC_CONTROL_INIT0 0x00000002
11874 +#define MEMC_CONTROL_INIT1 0x00000008
11875 +#define MEMC_MODEBUF_INIT0 0x00004000
11876 +#define MEMC_CONTROL_INIT2 0x00000010
11877 +#define MEMC_MODEBUF_INIT1 0x00000100
11878 +#define MEMC_CONTROL_INIT3 0x00000010
11879 +#define MEMC_CONTROL_INIT4 0x00000008
11880 +#define MEMC_REFRESH_INIT 0x0000840f
11881 +#define MEMC_CONTROL_INIT5 0x00000004
11882 +#define MEMC_MODEBUF_INIT2 0x00000000
11883 +#define MEMC_CONTROL_INIT6 0x00000010
11884 +#define MEMC_CONTROL_INIT7 0x00000001
11885 +
11886 +
11887 +/* This is for DDRM16X16X2 */
11888 +#define MEMC_DDR_INIT 0x0009
11889 +#define MEMC_DDR_MODE 0x62
11890 +#define MEMC_DDR_NCDL 0x0005050a
11891 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
11892 +
11893 +/* mask for sdr/ddr calibration registers */
11894 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
11895 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
11896 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
11897 +
11898 +/* masks for miscdlyctl registers */
11899 +#define MEMC_MISC_SM_MASK 0x30000000
11900 +#define MEMC_MISC_SM_SHIFT 28
11901 +#define MEMC_MISC_SD_MASK 0x0f000000
11902 +#define MEMC_MISC_SD_SHIFT 24
11903 +
11904 +/* hw threshhold for calculating wr/rd for sdr memc */
11905 +#define MEMC_CD_THRESHOLD 128
11906 +
11907 +/* Low bit of init register says if memc is ddr or sdr */
11908 +#define MEMC_CONFIG_DDR 0x00000001
11909 +
11910 +#endif /* _SBMEMC_H */
11911 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbmips.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbmips.h
11912 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
11913 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbmips.h 2005-12-13 14:59:52.000000000 +0100
11914 @@ -0,0 +1,56 @@
11915 +/*
11916 + * Broadcom SiliconBackplane MIPS definitions
11917 + *
11918 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
11919 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
11920 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
11921 + * interface. The core revision is stored in the SB ID register in SB
11922 + * configuration space.
11923 + *
11924 + * Copyright 2001-2003, Broadcom Corporation
11925 + * All Rights Reserved.
11926 + *
11927 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11928 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11929 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11930 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11931 + *
11932 + * $Id$
11933 + */
11934 +
11935 +#ifndef _SBMIPS_H
11936 +#define _SBMIPS_H
11937 +
11938 +#ifndef _LANGUAGE_ASSEMBLY
11939 +
11940 +/* cpp contortions to concatenate w/arg prescan */
11941 +#ifndef PAD
11942 +#define _PADLINE(line) pad ## line
11943 +#define _XSTR(line) _PADLINE(line)
11944 +#define PAD _XSTR(__LINE__)
11945 +#endif /* PAD */
11946 +
11947 +typedef volatile struct {
11948 + uint32 corecontrol;
11949 + uint32 PAD[2];
11950 + uint32 biststatus;
11951 + uint32 PAD[4];
11952 + uint32 intstatus;
11953 + uint32 intmask;
11954 + uint32 timer;
11955 +} mipsregs_t;
11956 +
11957 +extern uint32 sb_flag(void *sbh);
11958 +extern uint sb_irq(void *sbh);
11959 +
11960 +extern void sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
11961 +
11962 +extern void sb_mips_init(void *sbh);
11963 +extern uint32 sb_mips_clock(void *sbh);
11964 +extern bool sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
11965 +
11966 +extern uint32 sb_memc_get_ncdl(void *sbh);
11967 +
11968 +#endif /* _LANGUAGE_ASSEMBLY */
11969 +
11970 +#endif /* _SBMIPS_H */
11971 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbpci.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbpci.h
11972 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
11973 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbpci.h 2005-12-13 14:59:52.000000000 +0100
11974 @@ -0,0 +1,113 @@
11975 +/*
11976 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
11977 + *
11978 + * $Id$
11979 + * Copyright 2001-2003, Broadcom Corporation
11980 + * All Rights Reserved.
11981 + *
11982 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11983 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11984 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11985 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11986 + */
11987 +
11988 +#ifndef _SBPCI_H
11989 +#define _SBPCI_H
11990 +
11991 +/* cpp contortions to concatenate w/arg prescan */
11992 +#ifndef PAD
11993 +#define _PADLINE(line) pad ## line
11994 +#define _XSTR(line) _PADLINE(line)
11995 +#define PAD _XSTR(__LINE__)
11996 +#endif
11997 +
11998 +/* Sonics side: PCI core and host control registers */
11999 +typedef struct sbpciregs {
12000 + uint32 control; /* PCI control */
12001 + uint32 PAD[3];
12002 + uint32 arbcontrol; /* PCI arbiter control */
12003 + uint32 PAD[3];
12004 + uint32 intstatus; /* Interrupt status */
12005 + uint32 intmask; /* Interrupt mask */
12006 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
12007 + uint32 PAD[9];
12008 + uint32 bcastaddr; /* Sonics broadcast address */
12009 + uint32 bcastdata; /* Sonics broadcast data */
12010 + uint32 PAD[2];
12011 + uint32 gpioin; /* ro: gpio input (>=rev2) */
12012 + uint32 gpioout; /* rw: gpio output (>=rev2) */
12013 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
12014 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
12015 + uint32 PAD[36];
12016 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
12017 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
12018 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
12019 + uint32 PAD[445];
12020 + uint16 sprom[36]; /* SPROM shadow Area */
12021 + uint32 PAD[46];
12022 +} sbpciregs_t;
12023 +
12024 +/* PCI control */
12025 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
12026 +#define PCI_RST 0x02 /* Value driven out to pin */
12027 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
12028 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
12029 +
12030 +/* PCI arbiter control */
12031 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
12032 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
12033 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
12034 +#define PCI_PARKID_SHIFT 1
12035 +#define PCI_PARKID_LAST 0 /* Last requestor */
12036 +#define PCI_PARKID_4710 1 /* 4710 */
12037 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
12038 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
12039 +
12040 +/* Interrupt status/mask */
12041 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
12042 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
12043 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
12044 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
12045 +#define PCI_PME 0x10 /* PCI PME# is asserted */
12046 +
12047 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
12048 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
12049 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
12050 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
12051 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
12052 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
12053 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
12054 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
12055 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
12056 +
12057 +/* Sonics broadcast address */
12058 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
12059 +
12060 +/* Sonics to PCI translation types */
12061 +#define SBTOPCI0_MASK 0xfc000000
12062 +#define SBTOPCI1_MASK 0xfc000000
12063 +#define SBTOPCI2_MASK 0xc0000000
12064 +#define SBTOPCI_MEM 0
12065 +#define SBTOPCI_IO 1
12066 +#define SBTOPCI_CFG0 2
12067 +#define SBTOPCI_CFG1 3
12068 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
12069 +#define SBTOPCI_BURST 0x8 /* burst enable */
12070 +
12071 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
12072 +#define cap_list rsvd_a[0]
12073 +#define bar0_window dev_dep[0x80 - 0x40]
12074 +#define bar1_window dev_dep[0x84 - 0x40]
12075 +#define sprom_control dev_dep[0x88 - 0x40]
12076 +
12077 +#ifndef _LANGUAGE_ASSEMBLY
12078 +
12079 +extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
12080 +extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
12081 +extern void sbpci_ban(uint16 core);
12082 +extern int sbpci_init(void *sbh);
12083 +extern void sbpci_check(void *sbh);
12084 +
12085 +#endif /* !_LANGUAGE_ASSEMBLY */
12086 +
12087 +#endif /* _SBPCI_H */
12088 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbpcmcia.h
12089 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
12090 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbpcmcia.h 2005-12-13 14:59:52.000000000 +0100
12091 @@ -0,0 +1,131 @@
12092 +/*
12093 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
12094 + *
12095 + * $Id$
12096 + * Copyright 2001-2003, Broadcom Corporation
12097 + * All Rights Reserved.
12098 + *
12099 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12100 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12101 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12102 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12103 + */
12104 +
12105 +#ifndef _SBPCMCIA_H
12106 +#define _SBPCMCIA_H
12107 +
12108 +
12109 +/* All the addresses that are offsets in attribute space are divided
12110 + * by two to account for the fact that odd bytes are invalid in
12111 + * attribute space and our read/write routines make the space appear
12112 + * as if they didn't exist. Still we want to show the original numbers
12113 + * as documented in the hnd_pcmcia core manual.
12114 + */
12115 +
12116 +/* PCMCIA Function Configuration Registers */
12117 +#define PCMCIA_FCR (0x700 / 2)
12118 +
12119 +#define FCR0_OFF 0
12120 +#define FCR1_OFF (0x40 / 2)
12121 +#define FCR2_OFF (0x80 / 2)
12122 +#define FCR3_OFF (0xc0 / 2)
12123 +
12124 +#define PCMCIA_FCR0 (0x700 / 2)
12125 +#define PCMCIA_FCR1 (0x740 / 2)
12126 +#define PCMCIA_FCR2 (0x780 / 2)
12127 +#define PCMCIA_FCR3 (0x7c0 / 2)
12128 +
12129 +/* Standard PCMCIA FCR registers */
12130 +
12131 +#define PCMCIA_COR 0
12132 +
12133 +#define COR_RST 0x80
12134 +#define COR_LEV 0x40
12135 +#define COR_IRQEN 0x04
12136 +#define COR_BLREN 0x01
12137 +#define COR_FUNEN 0x01
12138 +
12139 +
12140 +#define PCICIA_FCSR (2 / 2)
12141 +#define PCICIA_PRR (4 / 2)
12142 +#define PCICIA_SCR (6 / 2)
12143 +#define PCICIA_ESR (8 / 2)
12144 +
12145 +
12146 +#define PCM_MEMOFF 0x0000
12147 +#define F0_MEMOFF 0x1000
12148 +#define F1_MEMOFF 0x2000
12149 +#define F2_MEMOFF 0x3000
12150 +#define F3_MEMOFF 0x4000
12151 +
12152 +/* Memory base in the function fcr's */
12153 +#define MEM_ADDR0 (0x728 / 2)
12154 +#define MEM_ADDR1 (0x72a / 2)
12155 +#define MEM_ADDR2 (0x72c / 2)
12156 +
12157 +/* PCMCIA base plus Srom access in fcr0: */
12158 +#define PCMCIA_ADDR0 (0x072e / 2)
12159 +#define PCMCIA_ADDR1 (0x0730 / 2)
12160 +#define PCMCIA_ADDR2 (0x0732 / 2)
12161 +
12162 +#define MEM_SEG (0x0734 / 2)
12163 +#define SROM_CS (0x0736 / 2)
12164 +#define SROM_DATAL (0x0738 / 2)
12165 +#define SROM_DATAH (0x073a / 2)
12166 +#define SROM_ADDRL (0x073c / 2)
12167 +#define SROM_ADDRH (0x073e / 2)
12168 +
12169 +/* Values for srom_cs: */
12170 +#define SROM_IDLE 0
12171 +#define SROM_WRITE 1
12172 +#define SROM_READ 2
12173 +#define SROM_WEN 4
12174 +#define SROM_WDS 7
12175 +#define SROM_DONE 8
12176 +
12177 +/* CIS stuff */
12178 +
12179 +/* The CIS stops where the FCRs start */
12180 +#define CIS_SIZE PCMCIA_FCR
12181 +
12182 +/* Standard tuples we know about */
12183 +
12184 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
12185 +#define CISTPL_FUNCE 0x22 /* Function extensions */
12186 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
12187 +
12188 +/* Function extensions for LANs */
12189 +
12190 +#define LAN_TECH 1 /* Technology type */
12191 +#define LAN_SPEED 2 /* Raw bit rate */
12192 +#define LAN_MEDIA 3 /* Transmission media */
12193 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
12194 +#define LAN_CONN 5 /* Connector standard */
12195 +
12196 +
12197 +/* CFTable */
12198 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
12199 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
12200 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
12201 +
12202 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
12203 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
12204 + */
12205 +
12206 +#define CISTPL_BRCM_HNBU 0x80
12207 +
12208 +/* Subtypes of BRCM_HNBU: */
12209 +
12210 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
12211 + * device id and chiprev
12212 + */
12213 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
12214 +#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
12215 +#define HNBU_OEM 0x04 /* Eight bytes OEM data */
12216 +#define HNBU_CC 0x05 /* Default country code */
12217 +#define HNBU_AA 0x06 /* Antennas available */
12218 +#define HNBU_AG 0x07 /* Antenna gain */
12219 +#define HNBU_BOARDFLAGS 0x08 /* board flags */
12220 +#define HNBU_LED 0x09 /* LED set */
12221 +
12222 +#endif /* _SBPCMCIA_H */
12223 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbsdram.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbsdram.h
12224 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
12225 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbsdram.h 2005-12-13 14:59:52.000000000 +0100
12226 @@ -0,0 +1,75 @@
12227 +/*
12228 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
12229 + *
12230 + * Copyright 2001-2003, Broadcom Corporation
12231 + * All Rights Reserved.
12232 + *
12233 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12234 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12235 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12236 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12237 + * $Id$
12238 + */
12239 +
12240 +#ifndef _SBSDRAM_H
12241 +#define _SBSDRAM_H
12242 +
12243 +#ifndef _LANGUAGE_ASSEMBLY
12244 +
12245 +/* Sonics side: SDRAM core registers */
12246 +typedef volatile struct sbsdramregs {
12247 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
12248 + uint32 config; /* Initializes external SDRAM mode register */
12249 + uint32 refresh; /* Controls external SDRAM refresh rate */
12250 + uint32 pad1;
12251 + uint32 pad2;
12252 +} sbsdramregs_t;
12253 +
12254 +#endif
12255 +
12256 +/* SDRAM initialization control (initcontrol) register bits */
12257 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
12258 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
12259 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
12260 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
12261 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
12262 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
12263 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
12264 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
12265 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
12266 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
12267 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
12268 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
12269 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
12270 +
12271 +/* SDRAM configuration (config) register bits */
12272 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
12273 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
12274 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
12275 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
12276 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
12277 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
12278 +
12279 +/* SDRAM refresh control (refresh) register bits */
12280 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
12281 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
12282 +
12283 +/* SDRAM Core default Init values (OCP ID 0x803) */
12284 +#define SDRAM_INIT MEM4MX16X2
12285 +#define SDRAM_CONFIG SDRAM_BURSTFULL
12286 +#define SDRAM_REFRESH SDRAM_REF(0x40)
12287 +
12288 +#define MEM1MX16 0x009 /* 2 MB */
12289 +#define MEM1MX16X2 0x409 /* 4 MB */
12290 +#define MEM2MX8X2 0x809 /* 4 MB */
12291 +#define MEM2MX8X4 0xc09 /* 8 MB */
12292 +#define MEM2MX32 0x439 /* 8 MB */
12293 +#define MEM4MX16 0x019 /* 8 MB */
12294 +#define MEM4MX16X2 0x419 /* 16 MB */
12295 +#define MEM8MX8X2 0x819 /* 16 MB */
12296 +#define MEM8MX16 0x829 /* 16 MB */
12297 +#define MEM4MX32 0x429 /* 16 MB */
12298 +#define MEM8MX8X4 0xc19 /* 32 MB */
12299 +#define MEM8MX16X2 0xc29 /* 32 MB */
12300 +
12301 +#endif /* _SBSDRAM_H */
12302 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbutils.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbutils.h
12303 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
12304 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/sbutils.h 2005-12-13 14:59:52.000000000 +0100
12305 @@ -0,0 +1,90 @@
12306 +/*
12307 + * Misc utility routines for accessing chip-specific features
12308 + * of Broadcom HNBU SiliconBackplane-based chips.
12309 + *
12310 + * Copyright 2001-2003, Broadcom Corporation
12311 + * All Rights Reserved.
12312 + *
12313 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12314 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12315 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12316 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12317 + *
12318 + * $Id$
12319 + */
12320 +
12321 +#ifndef _sbutils_h_
12322 +#define _sbutils_h_
12323 +
12324 +/* Board styles (bustype) */
12325 +#define BOARDSTYLE_SOC 0 /* Silicon Backplane */
12326 +#define BOARDSTYLE_PCI 1 /* PCI/MiniPCI board */
12327 +#define BOARDSTYLE_PCMCIA 2 /* PCMCIA board */
12328 +#define BOARDSTYLE_CARDBUS 3 /* Cardbus board */
12329 +
12330 +/*
12331 + * Many of the routines below take an 'sbh' handle as their first arg.
12332 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
12333 + * At any one time, the sbh is logically focused on one particular sb core
12334 + * (the "current core").
12335 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
12336 + */
12337 +
12338 +/* exported externs */
12339 +extern void *sb_attach(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
12340 +extern void *sb_kattach(void);
12341 +extern void sb_detach(void *sbh);
12342 +extern uint sb_chip(void *sbh);
12343 +extern uint sb_chiprev(void *sbh);
12344 +extern uint sb_chippkg(void *sbh);
12345 +extern uint sb_boardvendor(void *sbh);
12346 +extern uint sb_boardtype(void *sbh);
12347 +extern uint sb_boardstyle(void *sbh);
12348 +extern uint sb_bus(void *sbh);
12349 +extern uint sb_corelist(void *sbh, uint coreid[]);
12350 +extern uint sb_coreid(void *sbh);
12351 +extern uint sb_coreidx(void *sbh);
12352 +extern uint sb_coreunit(void *sbh);
12353 +extern uint sb_corevendor(void *sbh);
12354 +extern uint sb_corerev(void *sbh);
12355 +extern void *sb_coreregs(void *sbh);
12356 +extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
12357 +extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
12358 +extern bool sb_iscoreup(void *sbh);
12359 +extern void *sb_setcoreidx(void *sbh, uint coreidx);
12360 +extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
12361 +extern void sb_commit(void *sbh);
12362 +extern uint32 sb_base(uint32 admatch);
12363 +extern uint32 sb_size(uint32 admatch);
12364 +extern void sb_core_reset(void *sbh, uint32 bits);
12365 +extern void sb_core_tofixup(void *sbh);
12366 +extern void sb_core_disable(void *sbh, uint32 bits);
12367 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
12368 +extern uint32 sb_clock(void *sbh);
12369 +extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
12370 +extern void sb_pcmcia_init(void *sbh);
12371 +extern void sb_watchdog(void *sbh, uint ticks);
12372 +extern void *sb_gpiosetcore(void *sbh);
12373 +extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
12374 +extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
12375 +extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
12376 +extern uint32 sb_gpioin(void *sbh);
12377 +extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
12378 +extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
12379 +extern bool sb_taclear(void *sbh);
12380 +extern void sb_pwrctl_init(void *sbh);
12381 +extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
12382 +extern bool sb_pwrctl_clk(void *sbh, uint mode);
12383 +extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
12384 +extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg);
12385 +
12386 +/* pwrctl xtal what flags */
12387 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
12388 +#define PLL 0x2 /* main chip pll */
12389 +
12390 +/* pwrctl clk mode */
12391 +#define CLK_FAST 0 /* force fast (pll) clock */
12392 +#define CLK_SLOW 1 /* force slow clock */
12393 +#define CLK_DYNAMIC 2 /* enable dynamic power control */
12394 +
12395 +#endif /* _sbutils_h_ */
12396 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/trxhdr.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/trxhdr.h
12397 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
12398 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/trxhdr.h 2005-12-13 14:59:52.000000000 +0100
12399 @@ -0,0 +1,31 @@
12400 +/*
12401 + * TRX image file header format.
12402 + *
12403 + * Copyright 2001-2003, Broadcom Corporation
12404 + * All Rights Reserved.
12405 + *
12406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12410 + *
12411 + * $Id$
12412 + */
12413 +
12414 +#include <typedefs.h>
12415 +
12416 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
12417 +#define TRX_VERSION 1
12418 +#define TRX_MAX_LEN 0x3A0000
12419 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
12420 +
12421 +struct trx_header {
12422 + uint32 magic; /* "HDR0" */
12423 + uint32 len; /* Length of file including header */
12424 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
12425 + uint32 flag_version; /* 0:15 flags, 16:31 version */
12426 + uint32 offsets[3]; /* Offsets of partitions from start of header */
12427 +};
12428 +
12429 +/* Compatibility */
12430 +typedef struct trx_header TRXHDR, *PTRXHDR;
12431 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/typedefs.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/typedefs.h
12432 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
12433 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/typedefs.h 2005-12-13 14:59:52.000000000 +0100
12434 @@ -0,0 +1,162 @@
12435 +/*
12436 + * Copyright 2001-2003, Broadcom Corporation
12437 + * All Rights Reserved.
12438 + *
12439 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12440 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12441 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12442 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12443 + * $Id$
12444 + */
12445 +
12446 +#ifndef _TYPEDEFS_H_
12447 +#define _TYPEDEFS_H_
12448 +
12449 +/*----------------------- define TRUE, FALSE, NULL, bool ----------------*/
12450 +#ifdef __cplusplus
12451 +
12452 +#ifndef FALSE
12453 +#define FALSE false
12454 +#endif
12455 +#ifndef TRUE
12456 +#define TRUE true
12457 +#endif
12458 +
12459 +#else /* !__cplusplus */
12460 +
12461 +#if defined(_WIN32)
12462 +
12463 +typedef unsigned char bool;
12464 +
12465 +#else
12466 +
12467 +#if defined(MACOSX) && defined(KERNEL)
12468 +#include <IOKit/IOTypes.h>
12469 +#else
12470 +typedef int bool;
12471 +#endif
12472 +
12473 +#endif
12474 +
12475 +#ifndef FALSE
12476 +#define FALSE 0
12477 +#endif
12478 +#ifndef TRUE
12479 +#define TRUE 1
12480 +
12481 +#ifndef NULL
12482 +#define NULL 0
12483 +#endif
12484 +
12485 +#endif
12486 +
12487 +#endif /* __cplusplus */
12488 +
12489 +#ifndef OFF
12490 +#define OFF 0
12491 +#endif
12492 +
12493 +#ifndef ON
12494 +#define ON 1
12495 +#endif
12496 +
12497 +/*----------------------- define uchar, ushort, uint, ulong ----------------*/
12498 +
12499 +typedef unsigned char uchar;
12500 +
12501 +#if defined(_WIN32) || defined(PMON) || defined(__MRC__) || defined(V2_HAL) || defined(_CFE_)
12502 +
12503 +#ifndef V2_HAL
12504 +typedef unsigned short ushort;
12505 +#endif
12506 +
12507 +typedef unsigned int uint;
12508 +typedef unsigned long ulong;
12509 +
12510 +#else
12511 +
12512 +/* pick up ushort & uint from standard types.h */
12513 +#if defined(linux) && defined(__KERNEL__)
12514 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
12515 +#else
12516 +#include <sys/types.h>
12517 +#if !defined(TARGETENV_sun4) && !defined(linux)
12518 +typedef unsigned long ulong;
12519 +#endif /* TARGETENV_sun4 */
12520 +#endif
12521 +#if defined(PMON)
12522 +typedef unsigned int uint;
12523 +typedef unsigned long long uint64;
12524 +#endif
12525 +
12526 +#endif /* WIN32 || PMON || .. */
12527 +
12528 +/*----------------------- define [u]int8/16/32/64 --------------------------*/
12529 +
12530 +
12531 +#ifdef V2_HAL
12532 +#include <bcmos.h>
12533 +#else
12534 +typedef signed char int8;
12535 +typedef signed short int16;
12536 +typedef signed int int32;
12537 +
12538 +typedef unsigned char uint8;
12539 +typedef unsigned short uint16;
12540 +typedef unsigned int uint32;
12541 +#endif /* V2_HAL */
12542 +
12543 +typedef float float32;
12544 +typedef double float64;
12545 +
12546 +/*
12547 + * abstracted floating point type allows for compile time selection of
12548 + * single or double precision arithmetic. Compiling with -DFLOAT32
12549 + * selects single precision; the default is double precision.
12550 + */
12551 +
12552 +#if defined(FLOAT32)
12553 +typedef float32 float_t;
12554 +#else /* default to double precision floating point */
12555 +typedef float64 float_t;
12556 +#endif /* FLOAT32 */
12557 +
12558 +#ifdef _MSC_VER /* Microsoft C */
12559 +typedef signed __int64 int64;
12560 +typedef unsigned __int64 uint64;
12561 +
12562 +#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
12563 +/* gcc understands signed/unsigned 64 bit types, but complains in ANSI mode */
12564 +typedef signed long long int64;
12565 +typedef unsigned long long uint64;
12566 +
12567 +#elif defined(__ICL) && !defined(__STDC__)
12568 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode */
12569 +typedef unsigned long long uint64;
12570 +
12571 +#endif /* _MSC_VER */
12572 +
12573 +
12574 +/*----------------------- define PTRSZ, INLINE --------------------------*/
12575 +
12576 +#define PTRSZ sizeof (char*)
12577 +
12578 +#ifndef INLINE
12579 +
12580 +#ifdef _MSC_VER
12581 +
12582 +#define INLINE __inline
12583 +
12584 +#elif __GNUC__
12585 +
12586 +#define INLINE __inline__
12587 +
12588 +#else
12589 +
12590 +#define INLINE
12591 +
12592 +#endif /* _MSC_VER */
12593 +
12594 +#endif /* INLINE */
12595 +
12596 +#endif /* _TYPEDEFS_H_ */
12597 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/include/wlioctl.h linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/wlioctl.h
12598 --- linux-2.6.15-rc5/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
12599 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/include/wlioctl.h 2005-12-13 14:59:52.000000000 +0100
12600 @@ -0,0 +1,690 @@
12601 +/*
12602 + * Custom OID/ioctl definitions for
12603 + * Broadcom 802.11abg Networking Device Driver
12604 + *
12605 + * Definitions subject to change without notice.
12606 + *
12607 + * Copyright 2001-2003, Broadcom Corporation
12608 + * All Rights Reserved.
12609 + *
12610 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12611 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12612 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12613 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12614 + *
12615 + * $Id$
12616 + */
12617 +
12618 +#ifndef _wlioctl_h_
12619 +#define _wlioctl_h_
12620 +
12621 +#include <typedefs.h>
12622 +#include <proto/ethernet.h>
12623 +#include <proto/802.11.h>
12624 +
12625 +#if defined(__GNUC__)
12626 +#define PACKED __attribute__((packed))
12627 +#else
12628 +#define PACKED
12629 +#endif
12630 +
12631 +/*
12632 + * Per-bss information structure.
12633 + */
12634 +
12635 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
12636 +
12637 +typedef struct wl_rateset {
12638 + uint32 count; /* # rates in this set */
12639 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
12640 +} wl_rateset_t;
12641 +
12642 +#define WL_LEGACY_BSS_INFO_VERSION 106 /* an older supported version of wl_bss_info struct */
12643 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
12644 +
12645 +typedef struct wl_bss_info106 {
12646 + uint version; /* version field */
12647 + struct ether_addr BSSID;
12648 + uint8 SSID_len;
12649 + uint8 SSID[32];
12650 + uint8 Privacy; /* 0=No WEP, 1=Use WEP */
12651 + int16 RSSI; /* receive signal strength (in dBm) */
12652 + uint16 beacon_period; /* units are Kusec */
12653 + uint16 atim_window; /* units are Kusec */
12654 + uint8 channel; /* Channel no. */
12655 + int8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
12656 + struct {
12657 + uint count; /* # rates in this set */
12658 + uint8 rates[12]; /* rates in 500kbps units w/hi bit set if basic */
12659 + } rateset; /* supported rates */
12660 + uint8 dtim_period; /* DTIM period */
12661 + int8 phy_noise; /* noise right after tx (in dBm) */
12662 + uint16 capability; /* Capability information */
12663 + struct dot11_bcn_prb *prb; /* probe response frame (ioctl na) */
12664 + uint16 prb_len; /* probe response frame length (ioctl na) */
12665 + struct {
12666 + uint8 supported; /* wpa supported */
12667 + uint8 multicast; /* multicast cipher */
12668 + uint8 ucount; /* count of unicast ciphers */
12669 + uint8 unicast[4]; /* unicast ciphers */
12670 + uint8 acount; /* count of auth modes */
12671 + uint8 auth[4]; /* Authentication modes */
12672 + } wpa;
12673 +} wl_bss_info106_t;
12674 +
12675 +typedef struct wl_bss_info {
12676 + uint32 version; /* version field */
12677 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
12678 + struct ether_addr BSSID;
12679 + uint16 beacon_period; /* units are Kusec */
12680 + uint16 capability; /* Capability information */
12681 + uint8 SSID_len;
12682 + uint8 SSID[32];
12683 + struct {
12684 + uint count; /* # rates in this set */
12685 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
12686 + } rateset; /* supported rates */
12687 + uint8 channel; /* Channel no. */
12688 + uint16 atim_window; /* units are Kusec */
12689 + uint8 dtim_period; /* DTIM period */
12690 + int16 RSSI; /* receive signal strength (in dBm) */
12691 + int8 phy_noise; /* noise (in dBm) */
12692 + uint32 ie_length; /* byte length of Information Elements */
12693 + /* variable length Information Elements */
12694 +} wl_bss_info_t;
12695 +
12696 +typedef struct wl_scan_results {
12697 + uint32 buflen;
12698 + uint32 version;
12699 + uint32 count;
12700 + wl_bss_info_t bss_info[1];
12701 +} wl_scan_results_t;
12702 +/* size of wl_scan_results not including variable length array */
12703 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
12704 +
12705 +/* uint32 list */
12706 +typedef struct wl_uint32_list {
12707 + /* in - # of elements, out - # of entries */
12708 + uint32 count;
12709 + /* variable length uint32 list */
12710 + uint32 element[1];
12711 +} wl_uint32_list_t;
12712 +
12713 +typedef struct wlc_ssid {
12714 + uint32 SSID_len;
12715 + uchar SSID[32];
12716 +} wlc_ssid_t;
12717 +
12718 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
12719 +
12720 +typedef struct wl_channels_in_country {
12721 + uint32 buflen;
12722 + uint32 band;
12723 + char country_abbrev[WLC_CNTRY_BUF_SZ];
12724 + uint32 count;
12725 + uint32 channel[1];
12726 +} wl_channels_in_country_t;
12727 +
12728 +typedef struct wl_country_list {
12729 + uint32 buflen;
12730 + uint32 band_set;
12731 + uint32 band;
12732 + uint32 count;
12733 + char country_abbrev[1];
12734 +} wl_country_list_t;
12735 +
12736 +
12737 +/*
12738 +* Maximum # of keys that wl driver supports in S/W. Keys supported
12739 +* in H/W is less than or equal to WSEC_MAX_KEYS.
12740 +*/
12741 +#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
12742 +#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
12743 +
12744 +/*
12745 +* Remove these two defines if access to crypto/tkhash.h
12746 +* is unconditionally permitted.
12747 +*/
12748 +#define TKHASH_P1_KEY_SIZE 10 /* size of TKHash Phase1 output, in bytes */
12749 +#define TKHASH_P2_KEY_SIZE 16 /* size of TKHash Phase2 output */
12750 +
12751 +/* Enumerate crypto algorithms */
12752 +#define CRYPTO_ALGO_OFF 0
12753 +#define CRYPTO_ALGO_WEP1 1
12754 +#define CRYPTO_ALGO_TKIP 2
12755 +#define CRYPTO_ALGO_WEP128 3
12756 +#define CRYPTO_ALGO_AES_CCM 4
12757 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
12758 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
12759 +#define CRYPTO_ALGO_NALG 7
12760 +
12761 +/* For use with wlc_wep_key.flags */
12762 +#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
12763 +#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
12764 +#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
12765 +
12766 +#define WSEC_GEN_MIC_ERROR 0x0001
12767 +#define WSEC_GEN_REPLAY 0x0002
12768 +
12769 +typedef struct tkip_info {
12770 + uint16 phase1[TKHASH_P1_KEY_SIZE/sizeof(uint16)]; /* tkhash phase1 result */
12771 + uint8 phase2[TKHASH_P2_KEY_SIZE]; /* tkhash phase2 result */
12772 + uint32 micl;
12773 + uint32 micr;
12774 +} tkip_info_t;
12775 +
12776 +typedef struct wsec_iv {
12777 + uint32 hi; /* upper 32 bits of IV */
12778 + uint16 lo; /* lower 16 bits of IV */
12779 +} wsec_iv_t;
12780 +
12781 +typedef struct wsec_key {
12782 + uint32 index; /* key index */
12783 + uint32 len; /* key length */
12784 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
12785 + tkip_info_t tkip_tx; /* tkip transmit state */
12786 + tkip_info_t tkip_rx; /* tkip receive state */
12787 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
12788 + uint32 flags; /* misc flags */
12789 + uint32 algo_hw; /* cache for hw register*/
12790 + uint32 aes_mode; /* cache for hw register*/
12791 + int iv_len; /* IV length */
12792 + int iv_initialized; /* has IV been initialized already? */
12793 + int icv_len; /* ICV length */
12794 + wsec_iv_t rxiv; /* Rx IV */
12795 + wsec_iv_t txiv; /* Tx IV */
12796 + struct ether_addr ea; /* per station */
12797 +} wsec_key_t;
12798 +
12799 +/* wireless security bitvec */
12800 +#define WEP_ENABLED 1
12801 +#define TKIP_ENABLED 2
12802 +#define AES_ENABLED 4
12803 +#define WSEC_SWFLAG 8
12804 +
12805 +#define WSEC_SW(wsec) ((wsec) & WSEC_SWFLAG)
12806 +#define WSEC_HW(wsec) (!WSEC_SW(wsec))
12807 +#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
12808 +#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
12809 +#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
12810 +#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
12811 +
12812 +/* wireless authentication bit vector */
12813 +#define WPA_ENABLED 1
12814 +#define PSK_ENABLED 2
12815 +
12816 +#define WAUTH_WPA_ENABLED(wauth) ((wauth) & WPA_ENABLED)
12817 +#define WAUTH_PSK_ENABLED(wauth) ((wauth) & PSK_ENABLED)
12818 +#define WAUTH_ENABLED(wauth) ((wauth) & (WPA_ENABLED | PSK_ENABLED))
12819 +
12820 +/* group/mcast cipher */
12821 +#define WPA_MCAST_CIPHER(wsec) (((wsec) & TKIP_ENABLED) ? WPA_CIPHER_TKIP : \
12822 + ((wsec) & AES_ENABLED) ? WPA_CIPHER_AES_CCM : \
12823 + WPA_CIPHER_NONE)
12824 +
12825 +typedef struct wl_led_info {
12826 + uint32 index; /* led index */
12827 + uint32 behavior;
12828 + bool activehi;
12829 +} wl_led_info_t;
12830 +
12831 +/*
12832 + * definitions for driver messages passed from WL to NAS.
12833 + */
12834 +/* Use this to recognize wpa and 802.1x driver messages. */
12835 +static const uint8 wl_wpa_snap_template[] =
12836 + { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
12837 +
12838 +#define WL_WPA_MSG_IFNAME_MAX 16
12839 +
12840 +/* WPA driver message */
12841 +typedef struct wl_wpa_header {
12842 + struct ether_header eth;
12843 + struct dot11_llc_snap_header snap;
12844 + uint8 version;
12845 + uint8 type;
12846 + /* version 2 additions */
12847 + char ifname[WL_WPA_MSG_IFNAME_MAX];
12848 + /* version specific data */
12849 + /* uint8 data[1]; */
12850 +} wl_wpa_header_t PACKED;
12851 +
12852 +#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
12853 +
12854 +/* WPA driver message ethertype - private between wlc and nas */
12855 +#define WL_WPA_ETHER_TYPE 0x9999
12856 +
12857 +/* WPA driver message current version */
12858 +#define WL_WPA_MSG_VERSION 2
12859 +
12860 +/* Type field values for the 802.2 driver messages for WPA. */
12861 +#define WLC_ASSOC_MSG 1
12862 +#define WLC_DISASSOC_MSG 2
12863 +#define WLC_PTK_MIC_MSG 3
12864 +#define WLC_GTK_MIC_MSG 4
12865 +
12866 +/* 802.1x driver message */
12867 +typedef struct wl_eapol_header {
12868 + struct ether_header eth;
12869 + struct dot11_llc_snap_header snap;
12870 + uint8 version;
12871 + uint8 reserved;
12872 + char ifname[WL_WPA_MSG_IFNAME_MAX];
12873 + /* version specific data */
12874 + /* uint8 802_1x_msg[1]; */
12875 +} wl_eapol_header_t PACKED;
12876 +
12877 +#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
12878 +
12879 +/* 802.1x driver message ethertype - private between wlc and nas */
12880 +#define WL_EAPOL_ETHER_TYPE 0x999A
12881 +
12882 +/* 802.1x driver message current version */
12883 +#define WL_EAPOL_MSG_VERSION 1
12884 +
12885 +/* srom read/write struct passed through ioctl */
12886 +typedef struct {
12887 + uint byteoff; /* byte offset */
12888 + uint nbytes; /* number of bytes */
12889 + uint16 buf[1];
12890 +} srom_rw_t;
12891 +
12892 +/* R_REG and W_REG struct passed through ioctl */
12893 +typedef struct {
12894 + uint32 byteoff; /* byte offset of the field in d11regs_t */
12895 + uint32 val; /* read/write value of the field */
12896 + uint32 size; /* sizeof the field */
12897 +} rw_reg_t;
12898 +
12899 +/* Structure used by GET/SET_ATTEN ioctls */
12900 +typedef struct {
12901 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
12902 + uint16 bb; /* Baseband attenuation */
12903 + uint16 radio; /* Radio attenuation */
12904 + uint16 txctl1; /* Radio TX_CTL1 value */
12905 +} atten_t;
12906 +
12907 +/* Used to get specific STA parameters */
12908 +typedef struct {
12909 + uint32 val;
12910 + struct ether_addr ea;
12911 +} scb_val_t;
12912 +
12913 +/* callback registration data types */
12914 +
12915 +typedef struct _mac_event_params {
12916 + uint msg;
12917 + struct ether_addr *addr;
12918 + uint result;
12919 + uint status;
12920 + uint auth_type;
12921 +} mac_event_params_t;
12922 +
12923 +typedef struct _mic_error_params {
12924 + struct ether_addr *ea;
12925 + bool group;
12926 + bool flush_txq;
12927 +} mic_error_params_t;
12928 +
12929 +typedef enum _wl_callback {
12930 + WL_MAC_EVENT_CALLBACK = 0,
12931 + WL_LINK_UP_CALLBACK,
12932 + WL_LINK_DOWN_CALLBACK,
12933 + WL_MIC_ERROR_CALLBACK,
12934 + WL_LAST_CALLBACK
12935 +} wl_callback_t;
12936 +
12937 +typedef struct _callback {
12938 + void (*fn)(void *, void *);
12939 + void *context;
12940 +} callback_t;
12941 +
12942 +typedef struct _scan_callback {
12943 + void (*fn)(void *);
12944 + void *context;
12945 +} scan_callback_t;
12946 +
12947 +/* used to register an arbitrary callback via the IOCTL interface */
12948 +typedef struct _set_callback {
12949 + int index;
12950 + callback_t callback;
12951 +} set_callback_t;
12952 +
12953 +/*
12954 + * Country locale determines which channels are available to us.
12955 + */
12956 +typedef enum _wlc_locale {
12957 + WLC_WW = 0, /* Worldwide */
12958 + WLC_THA, /* Thailand */
12959 + WLC_ISR, /* Israel */
12960 + WLC_JDN, /* Jordan */
12961 + WLC_PRC, /* China */
12962 + WLC_JPN, /* Japan */
12963 + WLC_FCC, /* USA */
12964 + WLC_EUR, /* Europe */
12965 + WLC_USL, /* US Low Band only */
12966 + WLC_JPH, /* Japan High Band only */
12967 + WLC_ALL, /* All the channels in this band */
12968 + WLC_11D, /* Represents locale recieved by 11d beacons */
12969 + WLC_LAST_LOCALE,
12970 + WLC_UNDEFINED_LOCALE = 0xf
12971 +} wlc_locale_t;
12972 +
12973 +/* channel encoding */
12974 +typedef struct channel_info {
12975 + int hw_channel;
12976 + int target_channel;
12977 + int scan_channel;
12978 +} channel_info_t;
12979 +
12980 +/* For ioctls that take a list of MAC addresses */
12981 +struct maclist {
12982 + uint count; /* number of MAC addresses */
12983 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
12984 +};
12985 +
12986 +/* get pkt count struct passed through ioctl */
12987 +typedef struct get_pktcnt {
12988 + uint rx_good_pkt;
12989 + uint rx_bad_pkt;
12990 + uint tx_good_pkt;
12991 + uint tx_bad_pkt;
12992 +} get_pktcnt_t;
12993 +
12994 +/* Linux network driver ioctl encoding */
12995 +typedef struct wl_ioctl {
12996 + int cmd; /* common ioctl definition */
12997 + void *buf; /* pointer to user buffer */
12998 + int len; /* length of user buffer */
12999 +} wl_ioctl_t;
13000 +
13001 +/*
13002 + * Structure for passing hardware and software
13003 + * revision info up from the driver.
13004 + */
13005 +typedef struct wlc_rev_info {
13006 + uint vendorid; /* PCI vendor id */
13007 + uint deviceid; /* device id of chip */
13008 + uint radiorev; /* radio revision */
13009 + uint chiprev; /* chip revision */
13010 + uint corerev; /* core revision */
13011 + uint boardid; /* board identifier (usu. PCI sub-device id) */
13012 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
13013 + uint boardrev; /* board revision */
13014 + uint driverrev; /* driver version */
13015 + uint ucoderev; /* microcode version */
13016 + uint bus; /* bus type */
13017 + uint chipnum; /* chip number */
13018 +} wlc_rev_info_t;
13019 +
13020 +/* check this magic number */
13021 +#define WLC_IOCTL_MAGIC 0x14e46c77
13022 +
13023 +/* bump this number if you change the ioctl interface */
13024 +#define WLC_IOCTL_VERSION 1
13025 +
13026 +/* maximum length buffer required */
13027 +#define WLC_IOCTL_MAXLEN 8192
13028 +
13029 +/* common ioctl definitions */
13030 +#define WLC_GET_MAGIC 0
13031 +#define WLC_GET_VERSION 1
13032 +#define WLC_UP 2
13033 +#define WLC_DOWN 3
13034 +#define WLC_DUMP 6
13035 +#define WLC_GET_MSGLEVEL 7
13036 +#define WLC_SET_MSGLEVEL 8
13037 +#define WLC_GET_PROMISC 9
13038 +#define WLC_SET_PROMISC 10
13039 +#define WLC_GET_RATE 12
13040 +#define WLC_SET_RATE 13
13041 +#define WLC_GET_INSTANCE 14
13042 +#define WLC_GET_FRAG 15
13043 +#define WLC_SET_FRAG 16
13044 +#define WLC_GET_RTS 17
13045 +#define WLC_SET_RTS 18
13046 +#define WLC_GET_INFRA 19
13047 +#define WLC_SET_INFRA 20
13048 +#define WLC_GET_AUTH 21
13049 +#define WLC_SET_AUTH 22
13050 +#define WLC_GET_BSSID 23
13051 +#define WLC_SET_BSSID 24
13052 +#define WLC_GET_SSID 25
13053 +#define WLC_SET_SSID 26
13054 +#define WLC_RESTART 27
13055 +#define WLC_GET_CHANNEL 29
13056 +#define WLC_SET_CHANNEL 30
13057 +#define WLC_GET_SRL 31
13058 +#define WLC_SET_SRL 32
13059 +#define WLC_GET_LRL 33
13060 +#define WLC_SET_LRL 34
13061 +#define WLC_GET_PLCPHDR 35
13062 +#define WLC_SET_PLCPHDR 36
13063 +#define WLC_GET_RADIO 37
13064 +#define WLC_SET_RADIO 38
13065 +#define WLC_GET_PHYTYPE 39
13066 +#define WLC_GET_WEP 42
13067 +#define WLC_SET_WEP 43
13068 +#define WLC_GET_KEY 44
13069 +#define WLC_SET_KEY 45
13070 +#define WLC_SCAN 50
13071 +#define WLC_SCAN_RESULTS 51
13072 +#define WLC_DISASSOC 52
13073 +#define WLC_REASSOC 53
13074 +#define WLC_GET_ROAM_TRIGGER 54
13075 +#define WLC_SET_ROAM_TRIGGER 55
13076 +#define WLC_GET_TXANT 61
13077 +#define WLC_SET_TXANT 62
13078 +#define WLC_GET_ANTDIV 63
13079 +#define WLC_SET_ANTDIV 64
13080 +#define WLC_GET_TXPWR 65
13081 +#define WLC_SET_TXPWR 66
13082 +#define WLC_GET_CLOSED 67
13083 +#define WLC_SET_CLOSED 68
13084 +#define WLC_GET_MACLIST 69
13085 +#define WLC_SET_MACLIST 70
13086 +#define WLC_GET_RATESET 71
13087 +#define WLC_SET_RATESET 72
13088 +#define WLC_GET_LOCALE 73
13089 +#define WLC_SET_LOCALE 74
13090 +#define WLC_GET_BCNPRD 75
13091 +#define WLC_SET_BCNPRD 76
13092 +#define WLC_GET_DTIMPRD 77
13093 +#define WLC_SET_DTIMPRD 78
13094 +#define WLC_GET_SROM 79
13095 +#define WLC_SET_SROM 80
13096 +#define WLC_GET_WEP_RESTRICT 81
13097 +#define WLC_SET_WEP_RESTRICT 82
13098 +#define WLC_GET_COUNTRY 83
13099 +#define WLC_SET_COUNTRY 84
13100 +#define WLC_GET_REVINFO 98
13101 +#define WLC_GET_MACMODE 105
13102 +#define WLC_SET_MACMODE 106
13103 +#define WLC_GET_GMODE 109
13104 +#define WLC_SET_GMODE 110
13105 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
13106 +#define WLC_GET_SCANSUPPRESS 115
13107 +#define WLC_SET_SCANSUPPRESS 116
13108 +#define WLC_GET_AP 117
13109 +#define WLC_SET_AP 118
13110 +#define WLC_GET_EAP_RESTRICT 119
13111 +#define WLC_SET_EAP_RESTRICT 120
13112 +#define WLC_GET_WDSLIST 123
13113 +#define WLC_SET_WDSLIST 124
13114 +#define WLC_GET_RSSI 127
13115 +#define WLC_GET_WSEC 133
13116 +#define WLC_SET_WSEC 134
13117 +#define WLC_GET_BSS_INFO 136
13118 +#define WLC_GET_LAZYWDS 138
13119 +#define WLC_SET_LAZYWDS 139
13120 +#define WLC_GET_BANDLIST 140
13121 +#define WLC_GET_BAND 141
13122 +#define WLC_SET_BAND 142
13123 +#define WLC_GET_SHORTSLOT 144
13124 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
13125 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
13126 +#define WLC_GET_SHORTSLOT_RESTRICT 147
13127 +#define WLC_SET_SHORTSLOT_RESTRICT 148
13128 +#define WLC_GET_GMODE_PROTECTION 149
13129 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
13130 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
13131 +#define WLC_UPGRADE 152
13132 +#define WLC_GET_ASSOCLIST 159
13133 +#define WLC_GET_CLK 160
13134 +#define WLC_SET_CLK 161
13135 +#define WLC_GET_UP 162
13136 +#define WLC_OUT 163
13137 +#define WLC_GET_WPA_AUTH 164
13138 +#define WLC_SET_WPA_AUTH 165
13139 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
13140 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
13141 +#define WLC_GET_PHYLIST 180
13142 +#define WLC_GET_GMODE_PROTECTION_CTS 198
13143 +#define WLC_SET_GMODE_PROTECTION_CTS 199
13144 +#define WLC_GET_PIOMODE 203
13145 +#define WLC_SET_PIOMODE 204
13146 +#define WLC_SET_LED 209
13147 +#define WLC_GET_LED 210
13148 +#define WLC_GET_CHANNEL_SEL 215
13149 +#define WLC_START_CHANNEL_SEL 216
13150 +#define WLC_GET_VALID_CHANNELS 217
13151 +#define WLC_GET_FAKEFRAG 218
13152 +#define WLC_SET_FAKEFRAG 219
13153 +#define WLC_GET_WET 230
13154 +#define WLC_SET_WET 231
13155 +#define WLC_GET_KEY_PRIMARY 235
13156 +#define WLC_SET_KEY_PRIMARY 236
13157 +#define WLC_SCAN_WITH_CALLBACK 240
13158 +#define WLC_SET_CS_SCAN_TIMER 248
13159 +#define WLC_GET_CS_SCAN_TIMER 249
13160 +#define WLC_CURRENT_PWR 256
13161 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
13162 +#define WLC_GET_COUNTRY_LIST 261
13163 +#define WLC_NVRAM_GET 264
13164 +#define WLC_NVRAM_SET 265
13165 +#define WLC_LAST 271 /* bump after adding */
13166 +
13167 +/*
13168 + * Minor kludge alert:
13169 + * Duplicate a few definitions that irelay requires from epiioctl.h here
13170 + * so caller doesn't have to include this file and epiioctl.h .
13171 + * If this grows any more, it would be time to move these irelay-specific
13172 + * definitions out of the epiioctl.h and into a separate driver common file.
13173 + */
13174 +#ifndef EPICTRL_COOKIE
13175 +#define EPICTRL_COOKIE 0xABADCEDE
13176 +#endif
13177 +
13178 +/* vx wlc ioctl's offset */
13179 +#define CMN_IOCTL_OFF 0x180
13180 +
13181 +/*
13182 + * custom OID support
13183 + *
13184 + * 0xFF - implementation specific OID
13185 + * 0xE4 - first byte of Broadcom PCI vendor ID
13186 + * 0x14 - second byte of Broadcom PCI vendor ID
13187 + * 0xXX - the custom OID number
13188 + */
13189 +
13190 +/* begin 0x1f values beyond the start of the ET driver range. */
13191 +#define WL_OID_BASE 0xFFE41420
13192 +
13193 +/* NDIS overrides */
13194 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
13195 +
13196 +#define WL_DECRYPT_STATUS_SUCCESS 1
13197 +#define WL_DECRYPT_STATUS_FAILURE 2
13198 +#define WL_DECRYPT_STATUS_UNKNOWN 3
13199 +
13200 +/* allows user-mode app to poll the status of USB image upgrade */
13201 +#define WLC_UPGRADE_SUCCESS 0
13202 +#define WLC_UPGRADE_PENDING 1
13203 +
13204 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
13205 +#define WL_RADIO_SW_DISABLE (1<<0)
13206 +#define WL_RADIO_HW_DISABLE (1<<1)
13207 +
13208 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
13209 +#define WL_TXPWR_OVERRIDE (1<<31)
13210 +
13211 +
13212 +/* Bus types */
13213 +#define WL_SB_BUS 0 /* Silicon Backplane */
13214 +#define WL_PCI_BUS 1 /* PCI target */
13215 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
13216 +
13217 +/* band types */
13218 +#define WLC_BAND_AUTO 0 /* auto-select */
13219 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
13220 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
13221 +
13222 +/* MAC list modes */
13223 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
13224 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
13225 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
13226 +
13227 +/*
13228 + *
13229 + */
13230 +#define GMODE_LEGACY_B 0
13231 +#define GMODE_AUTO 1
13232 +#define GMODE_ONLY 2
13233 +#define GMODE_B_DEFERRED 3
13234 +#define GMODE_PERFORMANCE 4
13235 +#define GMODE_LRS 5
13236 +#define GMODE_MAX 6
13237 +
13238 +/* values for PLCPHdr_override */
13239 +#define WLC_PLCP_AUTO -1
13240 +#define WLC_PLCP_SHORT 0
13241 +#define WLC_PLCP_LONG 1
13242 +
13243 +/* values for g_protection_override */
13244 +#define WLC_G_PROTECTION_AUTO -1
13245 +#define WLC_G_PROTECTION_OFF 0
13246 +#define WLC_G_PROTECTION_ON 1
13247 +
13248 +/* values for g_protection_control */
13249 +#define WLC_G_PROTECTION_CTL_OFF 0
13250 +#define WLC_G_PROTECTION_CTL_LOCAL 1
13251 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
13252 +
13253 +
13254 +
13255 +
13256 +
13257 +
13258 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
13259 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
13260 +
13261 +/* led per-pin behaviors */
13262 +#define WL_LED_OFF 0 /* always off */
13263 +#define WL_LED_ON 1 /* always on */
13264 +#define WL_LED_ACTIVITY 2 /* activity */
13265 +#define WL_LED_RADIO 3 /* radio enabled */
13266 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
13267 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
13268 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
13269 +#define WL_LED_WI1 7
13270 +#define WL_LED_WI2 8
13271 +#define WL_LED_WI3 9
13272 +#define WL_LED_ASSOC 10 /* associated state indicator */
13273 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
13274 +#define WL_LED_NUMBEHAVIOR 12
13275 +
13276 +/* led behavior numeric value format */
13277 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
13278 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
13279 +
13280 +
13281 +/* rate check */
13282 +#define WL_RATE_OFDM(r) (((r) & 0x7f) == 12 || ((r) & 0x7f) == 18 || \
13283 + ((r) & 0x7f) == 24 || ((r) & 0x7f) == 36 || \
13284 + ((r) & 0x7f) == 48 || ((r) & 0x7f) == 72 || \
13285 + ((r) & 0x7f) == 96 || ((r) & 0x7f) == 108)
13286 +
13287 +
13288 +#undef PACKED
13289 +
13290 +#endif /* _wlioctl_h_ */
13291 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/int-handler.S linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/int-handler.S
13292 --- linux-2.6.15-rc5/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
13293 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/int-handler.S 2005-12-13 14:59:52.000000000 +0100
13294 @@ -0,0 +1,48 @@
13295 +/*
13296 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13297 + *
13298 + * This program is free software; you can redistribute it and/or modify it
13299 + * under the terms of the GNU General Public License as published by the
13300 + * Free Software Foundation; either version 2 of the License, or (at your
13301 + * option) any later version.
13302 + *
13303 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13304 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13305 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13306 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13307 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13308 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13309 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13310 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13311 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13312 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13313 + *
13314 + * You should have received a copy of the GNU General Public License along
13315 + * with this program; if not, write to the Free Software Foundation, Inc.,
13316 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13317 + */
13318 +
13319 +#include <asm/asm.h>
13320 +#include <asm/mipsregs.h>
13321 +#include <asm/regdef.h>
13322 +#include <asm/stackframe.h>
13323 +
13324 + .text
13325 + .set noreorder
13326 + .set noat
13327 + .align 5
13328 +
13329 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
13330 + SAVE_ALL
13331 + CLI
13332 +
13333 + .set at
13334 + .set noreorder
13335 +
13336 + jal bcm47xx_irq_dispatch
13337 + move a0, sp
13338 +
13339 + j ret_from_irq
13340 + nop
13341 +
13342 + END(bcm47xx_irq_handler)
13343 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/irq.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/irq.c
13344 --- linux-2.6.15-rc5/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
13345 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/irq.c 2005-12-13 14:59:52.000000000 +0100
13346 @@ -0,0 +1,67 @@
13347 +/*
13348 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13349 + *
13350 + * This program is free software; you can redistribute it and/or modify it
13351 + * under the terms of the GNU General Public License as published by the
13352 + * Free Software Foundation; either version 2 of the License, or (at your
13353 + * option) any later version.
13354 + *
13355 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13356 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13357 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13358 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13359 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13360 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13361 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13362 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13363 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13364 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13365 + *
13366 + * You should have received a copy of the GNU General Public License along
13367 + * with this program; if not, write to the Free Software Foundation, Inc.,
13368 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13369 + */
13370 +
13371 +#include <linux/config.h>
13372 +#include <linux/errno.h>
13373 +#include <linux/init.h>
13374 +#include <linux/interrupt.h>
13375 +#include <linux/irq.h>
13376 +#include <linux/module.h>
13377 +#include <linux/smp.h>
13378 +#include <linux/types.h>
13379 +
13380 +#include <asm/cpu.h>
13381 +#include <asm/io.h>
13382 +#include <asm/irq.h>
13383 +#include <asm/irq_cpu.h>
13384 +
13385 +extern asmlinkage void bcm47xx_irq_handler(void);
13386 +
13387 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
13388 +{
13389 + u32 cause;
13390 +
13391 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
13392 +
13393 + clear_c0_status(cause);
13394 +
13395 + if (cause & CAUSEF_IP7)
13396 + do_IRQ(7, regs);
13397 + if (cause & CAUSEF_IP2)
13398 + do_IRQ(2, regs);
13399 + if (cause & CAUSEF_IP3)
13400 + do_IRQ(3, regs);
13401 + if (cause & CAUSEF_IP4)
13402 + do_IRQ(4, regs);
13403 + if (cause & CAUSEF_IP5)
13404 + do_IRQ(5, regs);
13405 + if (cause & CAUSEF_IP6)
13406 + do_IRQ(6, regs);
13407 +}
13408 +
13409 +void __init arch_init_irq(void)
13410 +{
13411 + set_except_vector(0, bcm47xx_irq_handler);
13412 + mips_cpu_irq_init(0);
13413 +}
13414 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/Makefile linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/Makefile
13415 --- linux-2.6.15-rc5/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
13416 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/Makefile 2005-12-13 14:59:52.000000000 +0100
13417 @@ -0,0 +1,6 @@
13418 +#
13419 +# Makefile for the BCM47xx specific kernel interface routines
13420 +# under Linux.
13421 +#
13422 +
13423 +obj-y := irq.o int-handler.o prom.o setup.o time.o
13424 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/prom.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/prom.c
13425 --- linux-2.6.15-rc5/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
13426 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/prom.c 2005-12-13 14:59:52.000000000 +0100
13427 @@ -0,0 +1,59 @@
13428 +/*
13429 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13430 + *
13431 + * This program is free software; you can redistribute it and/or modify it
13432 + * under the terms of the GNU General Public License as published by the
13433 + * Free Software Foundation; either version 2 of the License, or (at your
13434 + * option) any later version.
13435 + *
13436 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13437 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13438 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13439 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13440 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13441 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13442 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13443 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13444 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13445 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13446 + *
13447 + * You should have received a copy of the GNU General Public License along
13448 + * with this program; if not, write to the Free Software Foundation, Inc.,
13449 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13450 + */
13451 +
13452 +#include <linux/init.h>
13453 +#include <linux/mm.h>
13454 +#include <linux/sched.h>
13455 +#include <linux/bootmem.h>
13456 +
13457 +#include <asm/addrspace.h>
13458 +#include <asm/bootinfo.h>
13459 +#include <asm/pmon.h>
13460 +
13461 +const char *get_system_type(void)
13462 +{
13463 + return "Broadcom BCM47xx";
13464 +}
13465 +
13466 +void __init prom_init(void)
13467 +{
13468 + unsigned long mem;
13469 +
13470 + mips_machgroup = MACH_GROUP_BRCM;
13471 + mips_machtype = MACH_BCM47XX;
13472 +
13473 + /* Figure out memory size by finding aliases */
13474 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
13475 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
13476 + *(unsigned long *)(prom_init))
13477 + break;
13478 + }
13479 +
13480 + add_memory_region(0, mem, BOOT_MEM_RAM);
13481 +}
13482 +
13483 +unsigned long __init prom_free_prom_memory(void)
13484 +{
13485 + return 0;
13486 +}
13487 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/setup.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/setup.c
13488 --- linux-2.6.15-rc5/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
13489 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/setup.c 2005-12-13 15:47:49.000000000 +0100
13490 @@ -0,0 +1,108 @@
13491 +/*
13492 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13493 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
13494 + *
13495 + * This program is free software; you can redistribute it and/or modify it
13496 + * under the terms of the GNU General Public License as published by the
13497 + * Free Software Foundation; either version 2 of the License, or (at your
13498 + * option) any later version.
13499 + *
13500 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13501 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13502 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13503 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13504 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13505 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13506 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13507 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13508 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13509 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13510 + *
13511 + * You should have received a copy of the GNU General Public License along
13512 + * with this program; if not, write to the Free Software Foundation, Inc.,
13513 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13514 + */
13515 +
13516 +#include <linux/init.h>
13517 +#include <linux/types.h>
13518 +#include <linux/tty.h>
13519 +#include <linux/serial.h>
13520 +#include <linux/serial_core.h>
13521 +#include <linux/serial_reg.h>
13522 +#include <asm/bootinfo.h>
13523 +#include <asm/time.h>
13524 +#include <asm/reboot.h>
13525 +
13526 +#include <typedefs.h>
13527 +#include <sbutils.h>
13528 +#include <sbmips.h>
13529 +#include <sbpci.h>
13530 +#include <sbconfig.h>
13531 +#include <bcmdevs.h>
13532 +
13533 +extern void bcm47xx_time_init(void);
13534 +extern void bcm47xx_timer_setup(struct irqaction *irq);
13535 +void *sbh;
13536 +
13537 +static int ser_line = 0;
13538 +
13539 +static void
13540 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
13541 +{
13542 + struct uart_port s;
13543 +
13544 + memset(&s, 0, sizeof(s));
13545 +
13546 + s.line = ser_line++;
13547 + s.membase = regs;
13548 + s.irq = irq + 2;
13549 + s.uartclk = baud_base;
13550 + s.flags = ASYNC_BOOT_AUTOCONF;
13551 + s.iotype = SERIAL_IO_MEM;
13552 + s.regshift = reg_shift;
13553 +
13554 + if (early_serial_setup(&s) != 0) {
13555 + printk(KERN_ERR "Serial setup failed!\n");
13556 + }
13557 +}
13558 +
13559 +void *nvram_get(char *foo)
13560 +{
13561 + return NULL;
13562 +}
13563 +
13564 +
13565 +static void bcm47xx_machine_restart(char *command)
13566 +{
13567 + printk("Please stand by while rebooting the system...\n");
13568 +
13569 + /* Set the watchdog timer to reset immediately */
13570 + local_irq_disable();
13571 + sb_watchdog(sbh, 1);
13572 + while (1);
13573 +}
13574 +
13575 +static void bcm47xx_machine_halt(void)
13576 +{
13577 + /* Disable interrupts and watchdog and spin forever */
13578 + local_irq_disable();
13579 + sb_watchdog(sbh, 0);
13580 + while (1);
13581 +}
13582 +
13583 +void __init plat_setup(void)
13584 +{
13585 +
13586 + sbh = sb_kattach();
13587 + sb_mips_init(sbh);
13588 + sbpci_init(sbh);
13589 +
13590 + sb_serial_init(sbh, serial_add);
13591 +
13592 + _machine_restart = bcm47xx_machine_restart;
13593 + _machine_halt = bcm47xx_machine_halt;
13594 + _machine_power_off = bcm47xx_machine_halt;
13595 +
13596 + board_time_init = bcm47xx_time_init;
13597 + board_timer_setup = bcm47xx_timer_setup;
13598 +}
13599 diff -Nur linux-2.6.15-rc5/arch/mips/bcm947xx/time.c linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/time.c
13600 --- linux-2.6.15-rc5/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
13601 +++ linux-2.6.15-rc5-openwrt/arch/mips/bcm947xx/time.c 2005-12-13 14:59:52.000000000 +0100
13602 @@ -0,0 +1,59 @@
13603 +/*
13604 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13605 + *
13606 + * This program is free software; you can redistribute it and/or modify it
13607 + * under the terms of the GNU General Public License as published by the
13608 + * Free Software Foundation; either version 2 of the License, or (at your
13609 + * option) any later version.
13610 + *
13611 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13612 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13613 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13614 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13615 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13616 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13617 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13618 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13619 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13620 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13621 + *
13622 + * You should have received a copy of the GNU General Public License along
13623 + * with this program; if not, write to the Free Software Foundation, Inc.,
13624 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13625 + */
13626 +
13627 +#include <linux/config.h>
13628 +#include <linux/init.h>
13629 +#include <linux/kernel.h>
13630 +#include <linux/sched.h>
13631 +#include <linux/serial_reg.h>
13632 +#include <linux/interrupt.h>
13633 +#include <asm/addrspace.h>
13634 +#include <asm/io.h>
13635 +#include <asm/time.h>
13636 +
13637 +void __init
13638 +bcm47xx_time_init(void)
13639 +{
13640 + unsigned int hz;
13641 +
13642 + /*
13643 + * Use deterministic values for initial counter interrupt
13644 + * so that calibrate delay avoids encountering a counter wrap.
13645 + */
13646 + write_c0_count(0);
13647 + write_c0_compare(0xffff);
13648 +
13649 + hz = 200 * 1000 * 1000;
13650 +
13651 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
13652 + mips_hpt_frequency = hz / 2;
13653 +
13654 +}
13655 +
13656 +void __init
13657 +bcm47xx_timer_setup(struct irqaction *irq)
13658 +{
13659 + /* Enable the timer interrupt */
13660 + setup_irq(7, irq);
13661 +}
13662 diff -Nur linux-2.6.15-rc5/arch/mips/Kconfig linux-2.6.15-rc5-openwrt/arch/mips/Kconfig
13663 --- linux-2.6.15-rc5/arch/mips/Kconfig 2005-12-04 06:10:42.000000000 +0100
13664 +++ linux-2.6.15-rc5-openwrt/arch/mips/Kconfig 2005-12-13 14:59:52.000000000 +0100
13665 @@ -244,6 +244,17 @@
13666 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
13667 Olivetti M700-10 workstations.
13668
13669 +config BCM947XX
13670 + bool "Support for BCM947xx based boards"
13671 + select DMA_NONCOHERENT
13672 + select HW_HAS_PCI
13673 + select IRQ_CPU
13674 + select SYS_HAS_CPU_MIPS32_R1
13675 + select SYS_SUPPORTS_32BIT_KERNEL
13676 + select SYS_SUPPORTS_LITTLE_ENDIAN
13677 + help
13678 + Support for BCM947xx based boards
13679 +
13680 config LASAT
13681 bool "Support for LASAT Networks platforms"
13682 select DMA_NONCOHERENT
13683 diff -Nur linux-2.6.15-rc5/arch/mips/kernel/cpu-probe.c linux-2.6.15-rc5-openwrt/arch/mips/kernel/cpu-probe.c
13684 --- linux-2.6.15-rc5/arch/mips/kernel/cpu-probe.c 2005-12-04 06:10:42.000000000 +0100
13685 +++ linux-2.6.15-rc5-openwrt/arch/mips/kernel/cpu-probe.c 2005-12-13 14:59:52.000000000 +0100
13686 @@ -656,6 +656,28 @@
13687 }
13688
13689
13690 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
13691 +{
13692 + decode_config1(c);
13693 + switch (c->processor_id & 0xff00) {
13694 + case PRID_IMP_BCM3302:
13695 + c->cputype = CPU_BCM3302;
13696 + c->isa_level = MIPS_CPU_ISA_M32;
13697 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
13698 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
13699 + break;
13700 + case PRID_IMP_BCM4710:
13701 + c->cputype = CPU_BCM4710;
13702 + c->isa_level = MIPS_CPU_ISA_M32;
13703 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
13704 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
13705 + break;
13706 + default:
13707 + c->cputype = CPU_UNKNOWN;
13708 + break;
13709 + }
13710 +}
13711 +
13712 __init void cpu_probe(void)
13713 {
13714 struct cpuinfo_mips *c = &current_cpu_data;
13715 @@ -678,6 +700,9 @@
13716 case PRID_COMP_SIBYTE:
13717 cpu_probe_sibyte(c);
13718 break;
13719 + case PRID_COMP_BROADCOM:
13720 + cpu_probe_broadcom(c);
13721 + break;
13722 case PRID_COMP_SANDCRAFT:
13723 cpu_probe_sandcraft(c);
13724 break;
13725 diff -Nur linux-2.6.15-rc5/arch/mips/kernel/head.S linux-2.6.15-rc5-openwrt/arch/mips/kernel/head.S
13726 --- linux-2.6.15-rc5/arch/mips/kernel/head.S 2005-12-04 06:10:42.000000000 +0100
13727 +++ linux-2.6.15-rc5-openwrt/arch/mips/kernel/head.S 2005-12-13 14:59:52.000000000 +0100
13728 @@ -107,6 +107,14 @@
13729 #endif
13730 .endm
13731
13732 +#ifdef CONFIG_BCM4710
13733 +#undef eret
13734 +#define eret nop; nop; eret
13735 +#endif
13736 +
13737 + j kernel_entry
13738 + nop
13739 +
13740 /*
13741 * Reserved space for exception handlers.
13742 * Necessary for machines which link their kernels at KSEG0.
13743 diff -Nur linux-2.6.15-rc5/arch/mips/kernel/proc.c linux-2.6.15-rc5-openwrt/arch/mips/kernel/proc.c
13744 --- linux-2.6.15-rc5/arch/mips/kernel/proc.c 2005-12-04 06:10:42.000000000 +0100
13745 +++ linux-2.6.15-rc5-openwrt/arch/mips/kernel/proc.c 2005-12-13 14:59:52.000000000 +0100
13746 @@ -82,6 +82,8 @@
13747 [CPU_VR4181] = "NEC VR4181",
13748 [CPU_VR4181A] = "NEC VR4181A",
13749 [CPU_SR71000] = "Sandcraft SR71000",
13750 + [CPU_BCM3302] = "Broadcom BCM3302",
13751 + [CPU_BCM4710] = "Broadcom BCM4710",
13752 [CPU_PR4450] = "Philips PR4450",
13753 };
13754
13755 diff -Nur linux-2.6.15-rc5/arch/mips/Makefile linux-2.6.15-rc5-openwrt/arch/mips/Makefile
13756 --- linux-2.6.15-rc5/arch/mips/Makefile 2005-12-04 06:10:42.000000000 +0100
13757 +++ linux-2.6.15-rc5-openwrt/arch/mips/Makefile 2005-12-13 14:59:52.000000000 +0100
13758 @@ -689,6 +689,13 @@
13759 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
13760
13761 #
13762 +# Broadcom BCM47XX boards
13763 +#
13764 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
13765 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
13766 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
13767 +
13768 +#
13769 # SNI RM200 PCI
13770 #
13771 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
13772 diff -Nur linux-2.6.15-rc5/arch/mips/mm/tlbex.c linux-2.6.15-rc5-openwrt/arch/mips/mm/tlbex.c
13773 --- linux-2.6.15-rc5/arch/mips/mm/tlbex.c 2005-12-04 06:10:42.000000000 +0100
13774 +++ linux-2.6.15-rc5-openwrt/arch/mips/mm/tlbex.c 2005-12-13 14:59:52.000000000 +0100
13775 @@ -858,6 +858,8 @@
13776 case CPU_4KSC:
13777 case CPU_20KC:
13778 case CPU_25KF:
13779 + case CPU_BCM3302:
13780 + case CPU_BCM4710:
13781 tlbw(p);
13782 break;
13783
13784 diff -Nur linux-2.6.15-rc5/arch/mips/pci/fixup-bcm47xx.c linux-2.6.15-rc5-openwrt/arch/mips/pci/fixup-bcm47xx.c
13785 --- linux-2.6.15-rc5/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
13786 +++ linux-2.6.15-rc5-openwrt/arch/mips/pci/fixup-bcm47xx.c 2005-12-13 15:04:21.000000000 +0100
13787 @@ -0,0 +1,23 @@
13788 +#include <linux/init.h>
13789 +#include <linux/pci.h>
13790 +
13791 +/* Do platform specific device initialization at pci_enable_device() time */
13792 +int pcibios_plat_dev_init(struct pci_dev *dev)
13793 +{
13794 + return 0;
13795 +}
13796 +
13797 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
13798 +{
13799 + u8 irq;
13800 +
13801 + if (dev->bus->number == 1)
13802 + return 2;
13803 +
13804 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
13805 + return irq + 2;
13806 +}
13807 +
13808 +struct pci_fixup pcibios_fixups[] = {
13809 + { 0 }
13810 +};
13811 diff -Nur linux-2.6.15-rc5/arch/mips/pci/Makefile linux-2.6.15-rc5-openwrt/arch/mips/pci/Makefile
13812 --- linux-2.6.15-rc5/arch/mips/pci/Makefile 2005-12-04 06:10:42.000000000 +0100
13813 +++ linux-2.6.15-rc5-openwrt/arch/mips/pci/Makefile 2005-12-13 14:59:52.000000000 +0100
13814 @@ -18,6 +18,7 @@
13815 obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
13816 obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
13817 obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
13818 +obj-$(CONFIG_BCM947XX) += ops-sb.o fixup-bcm47xx.o pci-bcm47xx.o
13819
13820 #
13821 # These are still pretty much in the old state, watch, go blind.
13822 diff -Nur linux-2.6.15-rc5/arch/mips/pci/ops-sb.c linux-2.6.15-rc5-openwrt/arch/mips/pci/ops-sb.c
13823 --- linux-2.6.15-rc5/arch/mips/pci/ops-sb.c 1970-01-01 01:00:00.000000000 +0100
13824 +++ linux-2.6.15-rc5-openwrt/arch/mips/pci/ops-sb.c 2005-12-13 14:59:52.000000000 +0100
13825 @@ -0,0 +1,44 @@
13826 +#include <linux/kernel.h>
13827 +#include <linux/init.h>
13828 +#include <linux/pci.h>
13829 +#include <linux/types.h>
13830 +#include <asm/pci.h>
13831 +
13832 +#include <typedefs.h>
13833 +#include <sbpci.h>
13834 +
13835 +extern void *sbh;
13836 +//extern spinlock_t bcm47xx_sbh_lock;
13837 +
13838 +static int
13839 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
13840 + int reg, int size, u32 *val)
13841 +{
13842 + //unsigned long flags;
13843 + int ret;
13844 +
13845 +
13846 + //spin_lock_irqsave(&sbh_lock, flags);
13847 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
13848 + //spin_unlock_irqrestore(&sbh_lock, flags);
13849 +
13850 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
13851 +}
13852 +
13853 +static int
13854 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
13855 + int reg, int size, u32 val)
13856 +{
13857 +// unsigned long flags;
13858 + int ret;
13859 +
13860 +// spin_lock_irqsave(&sbh_lock, flags);
13861 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
13862 +// spin_unlock_irqrestore(&sbh_lock, flags);
13863 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
13864 +}
13865 +
13866 +struct pci_ops sb_pci_ops = {
13867 + .read = sb_pci_read_config,
13868 + .write = sb_pci_write_config,
13869 +};
13870 diff -Nur linux-2.6.15-rc5/arch/mips/pci/pci-bcm47xx.c linux-2.6.15-rc5-openwrt/arch/mips/pci/pci-bcm47xx.c
13871 --- linux-2.6.15-rc5/arch/mips/pci/pci-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
13872 +++ linux-2.6.15-rc5-openwrt/arch/mips/pci/pci-bcm47xx.c 2005-12-13 14:59:52.000000000 +0100
13873 @@ -0,0 +1,61 @@
13874 +#include <linux/init.h>
13875 +#include <linux/pci.h>
13876 +#include <linux/types.h>
13877 +
13878 +#include <asm/cpu.h>
13879 +#include <asm/io.h>
13880 +
13881 +#include <typedefs.h>
13882 +#include <sbconfig.h>
13883 +
13884 +extern struct pci_ops sb_pci_ops;
13885 +
13886 +static struct resource sb_pci_mem_resource = {
13887 + .name = "SB PCI Memory resources",
13888 + .start = SB_ENUM_BASE,
13889 + .end = SB_ENUM_LIM - 1,
13890 + .flags = IORESOURCE_MEM,
13891 +};
13892 +
13893 +static struct resource sb_pci_io_resource = {
13894 + .name = "SB PCI I/O resources",
13895 + .start = 0x100,
13896 + .end = 0x1FF,
13897 + .flags = IORESOURCE_IO,
13898 +};
13899 +
13900 +static struct pci_controller bcm47xx_sb_pci_controller = {
13901 + .pci_ops = &sb_pci_ops,
13902 + .mem_resource = &sb_pci_mem_resource,
13903 + .io_resource = &sb_pci_io_resource,
13904 +};
13905 +
13906 +static struct resource ext_pci_mem_resource = {
13907 + .name = "Ext PCI Memory resources",
13908 + .start = SB_PCI_DMA,
13909 +// .end = 0x7FFFFFFF,
13910 + .end = 0x40FFFFFF,
13911 + .flags = IORESOURCE_MEM,
13912 +};
13913 +
13914 +static struct resource ext_pci_io_resource = {
13915 + .name = "Ext PCI I/O resources",
13916 + .start = 0x200,
13917 + .end = 0x2FF,
13918 + .flags = IORESOURCE_IO,
13919 +};
13920 +
13921 +static struct pci_controller bcm47xx_ext_pci_controller = {
13922 + .pci_ops = &sb_pci_ops,
13923 + .mem_resource = &ext_pci_mem_resource,
13924 + .io_resource = &ext_pci_io_resource,
13925 +};
13926 +
13927 +static int __init bcm47xx_pci_init(void)
13928 +{
13929 + register_pci_controller(&bcm47xx_sb_pci_controller);
13930 + register_pci_controller(&bcm47xx_ext_pci_controller);
13931 + return 0;
13932 +}
13933 +
13934 +early_initcall(bcm47xx_pci_init);
13935 diff -Nur linux-2.6.15-rc5/arch/mips/pci/pci.c linux-2.6.15-rc5-openwrt/arch/mips/pci/pci.c
13936 --- linux-2.6.15-rc5/arch/mips/pci/pci.c 2005-12-04 06:10:42.000000000 +0100
13937 +++ linux-2.6.15-rc5-openwrt/arch/mips/pci/pci.c 2005-12-13 14:59:52.000000000 +0100
13938 @@ -243,7 +243,8 @@
13939 if (dev->resource[i].flags & IORESOURCE_IO)
13940 offset = hose->io_offset;
13941 else if (dev->resource[i].flags & IORESOURCE_MEM)
13942 - offset = hose->mem_offset;
13943 + offset = 0x26000000;
13944 + // offset = hose->mem_offset;
13945
13946 dev->resource[i].start += offset;
13947 dev->resource[i].end += offset;
13948 diff -Nur linux-2.6.15-rc5/include/asm-mips/bootinfo.h linux-2.6.15-rc5-openwrt/include/asm-mips/bootinfo.h
13949 --- linux-2.6.15-rc5/include/asm-mips/bootinfo.h 2005-12-04 06:10:42.000000000 +0100
13950 +++ linux-2.6.15-rc5-openwrt/include/asm-mips/bootinfo.h 2005-12-13 14:59:52.000000000 +0100
13951 @@ -218,6 +218,12 @@
13952 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
13953 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
13954
13955 +/*
13956 + * Valid machtype for group Broadcom
13957 + */
13958 +#define MACH_GROUP_BRCM 23 /* Broadcom */
13959 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
13960 +
13961 #define CL_SIZE COMMAND_LINE_SIZE
13962
13963 const char *get_system_type(void);
13964 diff -Nur linux-2.6.15-rc5/include/asm-mips/cpu.h linux-2.6.15-rc5-openwrt/include/asm-mips/cpu.h
13965 --- linux-2.6.15-rc5/include/asm-mips/cpu.h 2005-12-04 06:10:42.000000000 +0100
13966 +++ linux-2.6.15-rc5-openwrt/include/asm-mips/cpu.h 2005-12-13 14:59:52.000000000 +0100
13967 @@ -102,6 +102,13 @@
13968 #define PRID_IMP_SR71000 0x0400
13969
13970 /*
13971 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
13972 + */
13973 +
13974 +#define PRID_IMP_BCM4710 0x4000
13975 +#define PRID_IMP_BCM3302 0x9000
13976 +
13977 +/*
13978 * Definitions for 7:0 on legacy processors
13979 */
13980
13981 @@ -196,7 +203,9 @@
13982 #define CPU_34K 60
13983 #define CPU_PR4450 61
13984 #define CPU_SB1A 62
13985 -#define CPU_LAST 62
13986 +#define CPU_BCM3302 63
13987 +#define CPU_BCM4710 64
13988 +#define CPU_LAST 64
13989
13990 /*
13991 * ISA Level encodings
13992 diff -Nur linux-2.6.15-rc5/include/linux/init.h linux-2.6.15-rc5-openwrt/include/linux/init.h
13993 --- linux-2.6.15-rc5/include/linux/init.h 2005-12-04 06:10:42.000000000 +0100
13994 +++ linux-2.6.15-rc5-openwrt/include/linux/init.h 2005-12-13 14:59:52.000000000 +0100
13995 @@ -86,6 +86,8 @@
13996 static initcall_t __initcall_##fn __attribute_used__ \
13997 __attribute__((__section__(".initcall" level ".init"))) = fn
13998
13999 +#define early_initcall(fn) __define_initcall(".early1",fn)
14000 +
14001 #define core_initcall(fn) __define_initcall("1",fn)
14002 #define postcore_initcall(fn) __define_initcall("2",fn)
14003 #define arch_initcall(fn) __define_initcall("3",fn)
14004 diff -Nur linux-2.6.15-rc5/include/linux/pci_ids.h linux-2.6.15-rc5-openwrt/include/linux/pci_ids.h
14005 --- linux-2.6.15-rc5/include/linux/pci_ids.h 2005-12-04 06:10:42.000000000 +0100
14006 +++ linux-2.6.15-rc5-openwrt/include/linux/pci_ids.h 2005-12-13 14:59:52.000000000 +0100
14007 @@ -1835,6 +1835,7 @@
14008 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
14009 #define PCI_DEVICE_ID_BCM4401 0x4401
14010 #define PCI_DEVICE_ID_BCM4401B0 0x4402
14011 +#define PCI_DEVICE_ID_BCM4713 0x4713
14012
14013 #define PCI_VENDOR_ID_TOPIC 0x151f
14014 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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