target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

   1 /*
   2  * Ralink RT305x SoC specific setup
   3  *
   4  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  * Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17
  18 #include <asm/mach-ralink/common.h>
  19 #include <asm/mach-ralink/ramips_gpio.h>
  20 #include <asm/mach-ralink/rt305x.h>
  21 #include <asm/mach-ralink/rt305x_regs.h>
  22
  23 void __iomem * rt305x_sysc_base;
  24 void __iomem * rt305x_memc_base;
  25
  26 void __init rt305x_detect_sys_type(void)
  27 {
  28         u32 n0;
  29         u32 n1;
  30         u32 id;
  31
  32         n0 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME0);
  33         n1 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME1);
  34         id = rt305x_sysc_rr(SYSC_REG_CHIP_ID);
  35
  36         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  37                 "Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
  38                 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
  39                 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
  40                 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
  41                 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
  42                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  43                 (id & CHIP_ID_REV_MASK));
  44 }
  45
  46 static struct ramips_gpio_chip rt305x_gpio_chips[] = {
  47         {
  48                 .chip = {
  49                         .label  = "RT305X-GPIO0",
  50                         .base   = 0,
  51                         .ngpio  = 24,
  52                 },
  53                 .regs = {
  54                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  55                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  56                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  57                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  58                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  59                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  60                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  61                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  62                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  63                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  64                 },
  65                 .map_base = RT305X_PIO_BASE,
  66                 .map_size = RT305X_PIO_SIZE,
  67         },
  68         {
  69                 .chip = {
  70                         .label  = "RT305X-GPIO1",
  71                         .base   = 24,
  72                         .ngpio  = 16,
  73                 },
  74                 .regs = {
  75                         [RAMIPS_GPIO_REG_INT]   = 0x38,
  76                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
  77                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
  78                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
  79                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
  80                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
  81                         [RAMIPS_GPIO_REG_POL]   = 0x50,
  82                         [RAMIPS_GPIO_REG_SET]   = 0x54,
  83                         [RAMIPS_GPIO_REG_RESET] = 0x58,
  84                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
  85                 },
  86                 .map_base = RT305X_PIO_BASE,
  87                 .map_size = RT305X_PIO_SIZE,
  88         },
  89         {
  90                 .chip = {
  91                         .label  = "RT305X-GPIO2",
  92                         .base   = 40,
  93                         .ngpio  = 12,
  94                 },
  95                 .regs = {
  96                         [RAMIPS_GPIO_REG_INT]   = 0x60,
  97                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
  98                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
  99                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 100                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 101                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 102                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 103                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 104                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 105                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 106                 },
 107                 .map_base = RT305X_PIO_BASE,
 108                 .map_size = RT305X_PIO_SIZE,
 109         },
 110 };
 111
 112 static struct ramips_gpio_data rt305x_gpio_data = {
 113         .chips = rt305x_gpio_chips,
 114         .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
 115 };
 116
 117 static void rt305x_gpio_reserve(int first, int last)
 118 {
 119         for (; first <= last; first++)
 120                 gpio_request(first, "reserved");
 121 }
 122
 123 void __init rt305x_gpio_init(u32 mode)
 124 {
 125         u32 t;
 126
 127         rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 128
 129         ramips_gpio_init(&rt305x_gpio_data);
 130         if ((mode & RT305X_GPIO_MODE_I2C) == 0)
 131                 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
 132
 133         if ((mode & RT305X_GPIO_MODE_SPI) == 0)
 134                 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
 135
 136         t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
 137         t &= RT305X_GPIO_MODE_UART0_MASK;
 138         switch (t) {
 139         case RT305X_GPIO_MODE_UARTF:
 140         case RT305X_GPIO_MODE_PCM_UARTF:
 141         case RT305X_GPIO_MODE_PCM_I2S:
 142         case RT305X_GPIO_MODE_I2S_UARTF:
 143                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
 144                 break;
 145         case RT305X_GPIO_MODE_PCM_GPIO:
 146                 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
 147                 break;
 148         case RT305X_GPIO_MODE_GPIO_UARTF:
 149         case RT305X_GPIO_MODE_GPIO_I2S:
 150                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
 151                 break;
 152         }
 153
 154         if ((mode & RT305X_GPIO_MODE_UART1) == 0)
 155                 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
 156                                     RT305X_GPIO_UART1_RXD);
 157
 158         if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
 159                 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
 160
 161         if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
 162                 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
 163                                     RT305X_GPIO_MDIO_MDIO);
 164
 165         if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
 166                 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
 167                                     RT305X_GPIO_SDRAM_MD31);
 168
 169         if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
 170                 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
 171                                     RT305X_GPIO_GE0_RXCLK);
 172 }