target/linux/generic/patches-3.2/020-ssb_update.patch

   1 --- a/drivers/ssb/pci.c
   2 +++ b/drivers/ssb/pci.c
   3 @@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
   4         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
   5                sizeof(out->antenna_gain.ghz5));
   6
   7 +       /* Extract FEM info */
   8 +       SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
   9 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  10 +       SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
  11 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  12 +       SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
  13 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  14 +       SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
  15 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  16 +       SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
  17 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  18 +
  19 +       SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
  20 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  21 +       SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
  22 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  23 +       SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
  24 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  25 +       SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
  26 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  27 +       SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
  28 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  29 +
  30         sprom_extract_r458(out, in);
  31
  32         /* TODO - get remaining rev 8 stuff needed */
  33 --- a/include/linux/ssb/ssb.h
  34 +++ b/include/linux/ssb/ssb.h
  35 @@ -94,6 +94,15 @@ struct ssb_sprom {
  36                 } ghz5;         /* 5GHz band */
  37         } antenna_gain;
  38
  39 +       struct {
  40 +               struct {
  41 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
  42 +               } ghz2;
  43 +               struct {
  44 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
  45 +               } ghz5;
  46 +       } fem;
  47 +
  48         /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
  49  };
  50
  51 --- a/include/linux/ssb/ssb_regs.h
  52 +++ b/include/linux/ssb/ssb_regs.h
  53 @@ -432,6 +432,23 @@
  54  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
  55  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
  56  #define  SSB_SPROM8_RXPO5G_SHIFT       8
  57 +#define SSB_SPROM8_FEM2G               0x00AE
  58 +#define SSB_SPROM8_FEM5G               0x00B0
  59 +#define  SSB_SROM8_FEM_TSSIPOS         0x0001
  60 +#define  SSB_SROM8_FEM_TSSIPOS_SHIFT   0
  61 +#define  SSB_SROM8_FEM_EXTPA_GAIN      0x0006
  62 +#define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT        1
  63 +#define  SSB_SROM8_FEM_PDET_RANGE      0x00F8
  64 +#define  SSB_SROM8_FEM_PDET_RANGE_SHIFT        3
  65 +#define  SSB_SROM8_FEM_TR_ISO          0x0700
  66 +#define  SSB_SROM8_FEM_TR_ISO_SHIFT    8
  67 +#define  SSB_SROM8_FEM_ANTSWLUT                0xF800
  68 +#define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
  69 +#define SSB_SPROM8_THERMAL             0x00B2
  70 +#define SSB_SPROM8_MPWR_RAWTS          0x00B4
  71 +#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
  72 +#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
  73 +#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
  74  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
  75  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
  76  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
  77 @@ -464,6 +481,46 @@
  78
  79  /* Values for boardflags_lo read from SPROM */
  80  #define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
  81 +#define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
  82 +#define SSB_BFL_AIRLINEMODE            0x0004  /* implements GPIO 13 radio disable indication */
  83 +#define SSB_BFL_RSSI                   0x0008  /* software calculates nrssi slope. */
  84 +#define SSB_BFL_ENETSPI                        0x0010  /* has ephy roboswitch spi */
  85 +#define SSB_BFL_XTAL_NOSLOW            0x0020  /* no slow clock available */
  86 +#define SSB_BFL_CCKHIPWR               0x0040  /* can do high power CCK transmission */
  87 +#define SSB_BFL_ENETADM                        0x0080  /* has ADMtek switch */
  88 +#define SSB_BFL_ENETVLAN               0x0100  /* can do vlan */
  89 +#define SSB_BFL_AFTERBURNER            0x0200  /* supports Afterburner mode */
  90 +#define SSB_BFL_NOPCI                  0x0400  /* board leaves PCI floating */
  91 +#define SSB_BFL_FEM                    0x0800  /* supports the Front End Module */
  92 +#define SSB_BFL_EXTLNA                 0x1000  /* has an external LNA */
  93 +#define SSB_BFL_HGPA                   0x2000  /* had high gain PA */
  94 +#define SSB_BFL_BTCMOD                 0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
  95 +#define SSB_BFL_ALTIQ                  0x8000  /* alternate I/Q settings */
  96 +
  97 +/* Values for boardflags_hi read from SPROM */
  98 +#define SSB_BFH_NOPA                   0x0001  /* has no PA */
  99 +#define SSB_BFH_RSSIINV                        0x0002  /* RSSI uses positive slope (not TSSI) */
 100 +#define SSB_BFH_PAREF                  0x0004  /* uses the PARef LDO */
 101 +#define SSB_BFH_3TSWITCH               0x0008  /* uses a triple throw switch shared with bluetooth */
 102 +#define SSB_BFH_PHASESHIFT             0x0010  /* can support phase shifter */
 103 +#define SSB_BFH_BUCKBOOST              0x0020  /* has buck/booster */
 104 +#define SSB_BFH_FEM_BT                 0x0040  /* has FEM and switch to share antenna with bluetooth */
 105 +
 106 +/* Values for boardflags2_lo read from SPROM */
 107 +#define SSB_BFL2_RXBB_INT_REG_DIS      0x0001  /* external RX BB regulator present */
 108 +#define SSB_BFL2_APLL_WAR              0x0002  /* alternative A-band PLL settings implemented */
 109 +#define SSB_BFL2_TXPWRCTRL_EN          0x0004  /* permits enabling TX Power Control */
 110 +#define SSB_BFL2_2X4_DIV               0x0008  /* 2x4 diversity switch */
 111 +#define SSB_BFL2_5G_PWRGAIN            0x0010  /* supports 5G band power gain */
 112 +#define SSB_BFL2_PCIEWAR_OVR           0x0020  /* overrides ASPM and Clkreq settings */
 113 +#define SSB_BFL2_CAESERS_BRD           0x0040  /* is Caesers board (unused) */
 114 +#define SSB_BFL2_BTC3WIRE              0x0080  /* used 3-wire bluetooth coexist */
 115 +#define SSB_BFL2_SKWRKFEM_BRD          0x0100  /* 4321mcm93 uses Skyworks FEM */
 116 +#define SSB_BFL2_SPUR_WAR              0x0200  /* has a workaround for clock-harmonic spurs */
 117 +#define SSB_BFL2_GPLL_WAR              0x0400  /* altenative G-band PLL settings implemented */
 118 +
 119 +/* Values for boardflags_lo read from SPROM */
 120 +#define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
 121  #define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
 122  #define SSB_BFL_AIRLINEMODE            0x0004  /* implements GPIO 13 radio disable indication */
 123  #define SSB_BFL_RSSI                   0x0008  /* software calculates nrssi slope. */