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work around the remaining race condition in the tsc sched stuff
[openwrt.git] / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
3 +++ linux.dev/arch/mips/Makefile 2005-11-10 01:10:45.775570250 +0100
4 @@ -369,6 +369,16 @@
5 endif
6
7 #
8 +# Texas Instruments AR7
9 +#
10 +
11 +ifdef CONFIG_AR7
12 +LIBS += arch/mips/ar7/ar7.o
13 +SUBDIRS += arch/mips/ar7
14 +LOADADDR += 0x94020000
15 +endif
16 +
17 +#
18 # DECstation family
19 #
20 ifdef CONFIG_DECSTATION
21 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
22 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
23 +++ linux.dev/arch/mips/ar7/Makefile 2005-11-10 01:13:51.443173750 +0100
24 @@ -0,0 +1,14 @@
25 +.S.s:
26 + $(CPP) $(AFLAGS) $< -o $*.s
27 +
28 +.S.o:
29 + $(CC) $(AFLAGS) -c $< -o $*.o
30 +
31 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
32 +O_TARGET := ar7.o
33 +
34 +obj-y := tnetd73xx_misc.o misc.o
35 +export-objs := misc.o irq.o init.o
36 +obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
37 +
38 +include $(TOPDIR)/Rules.make
39 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
40 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-11-10 01:14:16.372731750 +0100
42 @@ -0,0 +1,88 @@
43 +/*
44 + * Carsten Langgaard, carstenl@mips.com
45 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
46 + *
47 + * This program is free software; you can distribute it and/or modify it
48 + * under the terms of the GNU General Public License (Version 2) as
49 + * published by the Free Software Foundation.
50 + *
51 + * This program is distributed in the hope it will be useful, but WITHOUT
52 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
53 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
54 + * for more details.
55 + *
56 + * You should have received a copy of the GNU General Public License along
57 + * with this program; if not, write to the Free Software Foundation, Inc.,
58 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
59 + *
60 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
61 + */
62 +#include <linux/init.h>
63 +#include <linux/string.h>
64 +
65 +#include <asm/bootinfo.h>
66 +
67 +extern int prom_argc;
68 +extern int *_prom_argv;
69 +
70 +/*
71 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
72 + * This macro take care of sign extension.
73 + */
74 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
75 +
76 +char arcs_cmdline[CL_SIZE];
77 +#ifdef CONFIG_CMDLINE_BOOL
78 +char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
79 +#endif
80 +
81 +char * __init prom_getcmdline(void)
82 +{
83 + return &(arcs_cmdline[0]);
84 +}
85 +
86 +
87 +void __init prom_init_cmdline(void)
88 +{
89 + char *cp, *end;
90 + int actr;
91 + char *env_cmdline = prom_getenv("kernel_args");
92 + size_t len;
93 +
94 + actr = 1; /* Always ignore argv[0] */
95 +
96 + cp = end = &(arcs_cmdline[0]);
97 + end += sizeof(arcs_cmdline);
98 +
99 + if (env_cmdline) {
100 + len = strlen(env_cmdline);
101 + if (len > end - cp - 1)
102 + len = end - cp - 1;
103 + strncpy(cp, env_cmdline, len);
104 + cp += len;
105 + *cp++ = ' ';
106 + }
107 +#ifdef CONFIG_CMDLINE_BOOL
108 + else {
109 + len = strlen(cfg_cmdline);
110 + if (len > end - cp - 1)
111 + len = end - cp - 1;
112 + strncpy(cp, cfg_cmdline, len);
113 + cp += len;
114 + *cp++ = ' ';
115 + }
116 +#endif
117 +
118 + while(actr < prom_argc) {
119 + len = strlen(prom_argv(actr));
120 + if (len > end - cp - 1)
121 + break;
122 + strncpy(cp, prom_argv(actr), len);
123 + cp += len;
124 + *cp++ = ' ';
125 + actr++;
126 + }
127 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
128 + --cp;
129 + *cp = '\0';
130 +}
131 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
132 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
133 +++ linux.dev/arch/mips/ar7/init.c 2005-11-10 01:10:45.795571500 +0100
134 @@ -0,0 +1,199 @@
135 +/*
136 + * Carsten Langgaard, carstenl@mips.com
137 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
138 + *
139 + * This program is free software; you can distribute it and/or modify it
140 + * under the terms of the GNU General Public License (Version 2) as
141 + * published by the Free Software Foundation.
142 + *
143 + * This program is distributed in the hope it will be useful, but WITHOUT
144 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
145 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
146 + * for more details.
147 + *
148 + * You should have received a copy of the GNU General Public License along
149 + * with this program; if not, write to the Free Software Foundation, Inc.,
150 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
151 + *
152 + * PROM library initialisation code.
153 + */
154 +#include <linux/config.h>
155 +#include <linux/init.h>
156 +#include <linux/string.h>
157 +#include <linux/kernel.h>
158 +#include <linux/module.h>
159 +
160 +#include <asm/io.h>
161 +#include <asm/mips-boards/prom.h>
162 +#include <asm/mips-boards/generic.h>
163 +
164 +#include <asm/ar7/adam2_env.h>
165 +
166 +int prom_argc;
167 +int *_prom_argv, *_prom_envp;
168 +
169 +/* max # of Adam2 environment variables */
170 +#define MAX_ENV_ENTRY 80
171 +
172 +static t_env_var local_envp[MAX_ENV_ENTRY];
173 +static int env_type = 0;
174 +int init_debug = 0;
175 +
176 +unsigned int max_env_entry;
177 +
178 +extern char *prom_psp_getenv(char *envname);
179 +
180 +static inline char *prom_adam2_getenv(char *envname)
181 +{
182 + /*
183 + * Return a pointer to the given environment variable.
184 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
185 + * in the PROM structures are only 32-bit, so we need some
186 + * workarounds, if we are running in 64-bit mode.
187 + */
188 + int i;
189 + t_env_var *env = (t_env_var *) local_envp;
190 +
191 + if (strcmp("bootloader", envname) == 0)
192 + return "Adam2";
193 +
194 + i = strlen(envname);
195 + while (env->name) {
196 + if(strncmp(envname, env->name, i) == 0) {
197 + return(env->val);
198 + }
199 + env++;
200 + }
201 +
202 + return NULL;
203 +}
204 +
205 +/* XXX "bootloader" won't be returned.
206 + * Better make it an element of local_envp */
207 +static inline t_env_var *
208 +prom_adam2_iterenv(t_env_var *env) {
209 + if (!env)
210 + env = local_envp;
211 + else
212 + env++;
213 + if (env - local_envp > MAX_ENV_ENTRY || !env->name)
214 + return 0;
215 + return env;
216 +}
217 +
218 +char *prom_getenv(char *envname)
219 +{
220 + if (env_type == 1)
221 + return prom_psp_getenv(envname);
222 + else
223 + return prom_adam2_getenv(envname);
224 +}
225 +
226 +t_env_var *
227 +prom_iterenv(t_env_var *last)
228 +{
229 + if (env_type == 1)
230 + return 0; /* not yet implemented */
231 + return prom_adam2_iterenv(last);
232 +}
233 +
234 +static inline unsigned char str2hexnum(unsigned char c)
235 +{
236 + if (c >= '0' && c <= '9')
237 + return c - '0';
238 + if (c >= 'a' && c <= 'f')
239 + return c - 'a' + 10;
240 + return 0; /* foo */
241 +}
242 +
243 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
244 +{
245 + int i;
246 +
247 + for (i = 0; i < 6; i++) {
248 + unsigned char num;
249 +
250 + if((*str == '.') || (*str == ':'))
251 + str++;
252 + num = str2hexnum(*str++) << 4;
253 + num |= (str2hexnum(*str++));
254 + ea[i] = num;
255 + }
256 +}
257 +
258 +int get_ethernet_addr(char *ethernet_addr)
259 +{
260 + char *ethaddr_str;
261 +
262 + ethaddr_str = prom_getenv("ethaddr");
263 + if (!ethaddr_str) {
264 + printk("ethaddr not set in boot prom\n");
265 + return -1;
266 + }
267 + str2eaddr(ethernet_addr, ethaddr_str);
268 +
269 + if (init_debug > 1) {
270 + int i;
271 + printk("get_ethernet_addr: ");
272 + for (i=0; i<5; i++)
273 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
274 + printk("%02x\n", *(ethernet_addr+i));
275 + }
276 +
277 + return 0;
278 +}
279 +
280 +struct psbl_rec {
281 + unsigned int psbl_size;
282 + unsigned int env_base;
283 + unsigned int env_size;
284 + unsigned int ffs_base;
285 + unsigned int ffs_size;
286 +};
287 +
288 +static const char psp_env_version[] = "TIENV0.8";
289 +
290 +int __init prom_init(int argc, char **argv, char **envp)
291 +{
292 + int i;
293 +
294 + t_env_var *env = (t_env_var *) envp;
295 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
296 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
297 +
298 + prom_argc = argc;
299 + _prom_argv = (int *)argv;
300 + _prom_envp = (int *)envp;
301 +
302 + if(strcmp(psp_env, psp_env_version) == 0) {
303 + /* PSPBOOT */
304 +
305 + env_type = 1;
306 + _prom_envp = psp_env;
307 + max_env_entry = (psbl->env_size / 16) - 1;
308 + } else {
309 + /* Copy what we need locally so we are not dependent on
310 + * bootloader RAM. In Adam2, the environment parameters
311 + * are in flash but the table that references them is in
312 + * RAM
313 + */
314 +
315 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
316 + if (env->name) {
317 + local_envp[i].name = env->name;
318 + local_envp[i].val = env->val;
319 + } else {
320 + local_envp[i].name = NULL;
321 + local_envp[i].val = NULL;
322 + }
323 + }
324 + }
325 +
326 + set_io_port_base(0);
327 +
328 + prom_printf("\nLINUX started...\n");
329 + prom_init_cmdline();
330 + prom_meminit();
331 +
332 + return 0;
333 +}
334 diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
335 --- linux.old/arch/mips/ar7/int-handler.S 1970-01-01 01:00:00.000000000 +0100
336 +++ linux.dev/arch/mips/ar7/int-handler.S 2005-11-10 01:12:43.938955000 +0100
337 @@ -0,0 +1,63 @@
338 +/*
339 + * Copyright 2004 PMC-Sierra Inc.
340 + * Author: Manish Lachwani (lachwani@pmc-sierra.com)
341 + * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
342 + *
343 + * First-level interrupt dispatcher for the TI AR7
344 + *
345 + * This program is free software; you can redistribute it and/or modify it
346 + * under the terms of the GNU General Public License as published by the
347 + * Free Software Foundation; either version 2 of the License, or (at your
348 + * option) any later version.
349 + */
350 +#define __ASSEMBLY__
351 +#include <linux/config.h>
352 +#include <asm/asm.h>
353 +#include <asm/mipsregs.h>
354 +#include <asm/addrspace.h>
355 +#include <asm/regdef.h>
356 +#include <asm/stackframe.h>
357 +
358 +/*
359 + * First level interrupt dispatcher for TI AR7 based boards
360 + */
361 +
362 + .align 5
363 + NESTED(ar7IRQ, PT_SIZE, sp)
364 + SAVE_ALL
365 + CLI
366 + .set at
367 +
368 + mfc0 t0, CP0_CAUSE
369 + mfc0 t2, CP0_STATUS
370 +
371 + and t0, t2
372 +
373 + andi t1, t0, STATUSF_IP2 /* hw0 hardware interrupt */
374 + bnez t1, ll_hw0_irq
375 +
376 + andi t1, t0, STATUSF_IP7 /* R4k CPU timer */
377 + bnez t1, ll_timer_irq
378 +
379 + .set reorder
380 +
381 + /* wrong alarm or masked ... */
382 + j spurious_interrupt
383 + nop
384 + END(ar7IRQ)
385 +
386 + .align 5
387 +
388 +ll_hw0_irq:
389 + li a0, 2
390 + move a1, sp
391 + jal do_IRQ
392 + j ret_from_irq
393 +
394 +ll_timer_irq:
395 + li a0, 7
396 + move a1, sp
397 + jal do_IRQ
398 + j ret_from_irq
399 +
400 +
401 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
402 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
403 +++ linux.dev/arch/mips/ar7/irq.c 2005-11-10 01:12:43.938955000 +0100
404 @@ -0,0 +1,427 @@
405 +/*
406 + * Nitin Dhingra, iamnd@ti.com
407 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
408 + *
409 + * ########################################################################
410 + *
411 + * This program is free software; you can distribute it and/or modify it
412 + * under the terms of the GNU General Public License (Version 2) as
413 + * published by the Free Software Foundation.
414 + *
415 + * This program is distributed in the hope it will be useful, but WITHOUT
416 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
417 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
418 + * for more details.
419 + *
420 + * You should have received a copy of the GNU General Public License along
421 + * with this program; if not, write to the Free Software Foundation, Inc.,
422 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
423 + *
424 + * ########################################################################
425 + *
426 + * Routines for generic manipulation of the interrupts found on the Texas
427 + * Instruments avalanche board
428 + *
429 + */
430 +
431 +#include <linux/init.h>
432 +#include <linux/interrupt.h>
433 +
434 +#include <asm/irq.h>
435 +#include <asm/mipsregs.h>
436 +#include <asm/ar7/ar7.h>
437 +#include <asm/ar7/avalanche_intc.h>
438 +
439 +#define shutdown_avalanche_irq disable_avalanche_irq
440 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
441 +
442 +static unsigned int startup_avalanche_irq(unsigned int irq);
443 +static void end_avalanche_irq(unsigned int irq);
444 +void enable_avalanche_irq(unsigned int irq_nr);
445 +void disable_avalanche_irq(unsigned int irq_nr);
446 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
447 +
448 +static struct hw_interrupt_type avalanche_irq_type = {
449 + "AR7",
450 + startup_avalanche_irq,
451 + shutdown_avalanche_irq,
452 + enable_avalanche_irq,
453 + disable_avalanche_irq,
454 + mask_and_ack_avalanche_irq,
455 + end_avalanche_irq,
456 + NULL
457 +};
458 +
459 +static int ar7_irq_base;
460 +
461 +static struct irqaction ar7_hw0_action = {
462 + ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
463 +};
464 +
465 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
466 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
467 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
468 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
469 +
470 +/*
471 + This remaps interrupts to exist on other channels than the default
472 + channels. essentially we can use the line # as the index for this
473 + array
474 + */
475 +
476 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
477 +unsigned long uni_secondary_interrupt = 0;
478 +
479 +static void end_avalanche_irq(unsigned int irq)
480 +{
481 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
482 + enable_avalanche_irq(irq);
483 +}
484 +
485 +void disable_avalanche_irq(unsigned int irq_nr)
486 +{
487 + unsigned long flags;
488 + unsigned long chan_nr=0;
489 +
490 + save_and_cli(flags);
491 +
492 + /* irq_nr represents the line number for the interrupt. We must
493 + * disable the channel number associated with that line number.
494 + */
495 +
496 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
497 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
498 + else
499 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
500 +
501 + /* disable the interrupt channel bit */
502 +
503 + /* primary interrupt #'s 0-31 */
504 +
505 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
506 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
507 +
508 + /* primary interrupt #'s 32-39 */
509 +
510 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
511 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
512 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
513 +
514 + else /* secondary interrupt #'s 0-31 */
515 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
516 +
517 + restore_flags(flags);
518 +}
519 +
520 +void enable_avalanche_irq(unsigned int irq_nr)
521 +{
522 + unsigned long flags;
523 + unsigned long chan_nr=0;
524 +
525 + save_and_cli(flags);
526 +
527 + /* irq_nr represents the line number for the interrupt. We must
528 + * disable the channel number associated with that line number.
529 + */
530 +
531 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
532 + chan_nr = AVINTNUM(irq_nr);
533 + else
534 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
535 +
536 + /* enable the interrupt channel bit */
537 +
538 + /* primary interrupt #'s 0-31 */
539 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
540 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
541 +
542 + /* primary interrupt #'s 32 throuth 39 */
543 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
544 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
545 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
546 +
547 + else /* secondary interrupt #'s 0-31 */
548 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
549 +
550 + restore_flags(flags);
551 +}
552 +
553 +static unsigned int startup_avalanche_irq(unsigned int irq)
554 +{
555 + enable_avalanche_irq(irq);
556 + return 0; /* never anything pending */
557 +}
558 +
559 +void __init ar7_irq_init(int base)
560 +{
561 + int i;
562 +
563 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
564 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
565 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
566 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
567 +
568 + /* Disable interrupts and clear pending
569 + */
570 +
571 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
572 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
573 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
574 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
575 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
576 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
577 +
578 +
579 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
580 + /* hack for speeding up the pacing. */
581 + printk("the pacing pre-scalar has been set as 600.\n");
582 + avalanche_hw0_ipaceregs->ipacep = 600;
583 + /* Channel to line mapping, Line to Channel mapping */
584 +
585 + for(i = 0; i < 40; i++)
586 + avalanche_int_set(i,i);
587 +
588 + ar7_irq_base = base;
589 + for (i = base; i <= base+40; i++)
590 + {
591 + irq_desc[i].status = IRQ_DISABLED;
592 + irq_desc[i].action = 0;
593 + irq_desc[i].depth = 1;
594 + irq_desc[i].handler = &avalanche_irq_type;
595 + }
596 +
597 + setup_irq(2, &ar7_hw0_action);
598 + set_c0_status(IE_IRQ0);
599 +
600 + return;
601 +}
602 +
603 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
604 +{
605 + int irq;
606 + unsigned long int_line_number, status;
607 + int i, chan_nr = 0;
608 +
609 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
610 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
611 +
612 + if(chan_nr < 32) /* primary 0-31 */
613 + {
614 + if( chan_nr != uni_secondary_interrupt)
615 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
616 +
617 + }
618 +
619 + if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
620 + {
621 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
622 + }
623 +
624 +
625 + /* If the Priority Interrupt Index Register returns 40 then no
626 + * interrupts are pending
627 + */
628 +
629 + if(chan_nr == 40)
630 + return;
631 +
632 + if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
633 + {
634 + status = avalanche_hw0_ecregs->exsr;
635 + for(i=0; i < 32; i++)
636 + {
637 + if (status & 1<<i)
638 + {
639 + /* clear secondary interrupt */
640 + avalanche_hw0_ecregs->excr = 1 << i;
641 + break;
642 + }
643 + }
644 + irq = i+40;
645 +
646 + /* clear the universal secondary interrupt */
647 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
648 +
649 + }
650 + else
651 + irq = chan_nr;
652 +
653 + do_IRQ(irq + ar7_irq_base, regs);
654 + return;
655 +}
656 +
657 +void avalanche_int_set(int channel, int line)
658 +{
659 + switch(channel)
660 + {
661 + case(0):
662 + avalanche_hw0_chregs->cintnr0 = line;
663 + break;
664 + case(1):
665 + avalanche_hw0_chregs->cintnr1 = line;
666 + break;
667 + case(2):
668 + avalanche_hw0_chregs->cintnr2 = line;
669 + break;
670 + case(3):
671 + avalanche_hw0_chregs->cintnr3 = line;
672 + break;
673 + case(4):
674 + avalanche_hw0_chregs->cintnr4 = line;
675 + break;
676 + case(5):
677 + avalanche_hw0_chregs->cintnr5 = line;
678 + break;
679 + case(6):
680 + avalanche_hw0_chregs->cintnr6 = line;
681 + break;
682 + case(7):
683 + avalanche_hw0_chregs->cintnr7 = line;
684 + break;
685 + case(8):
686 + avalanche_hw0_chregs->cintnr8 = line;
687 + break;
688 + case(9):
689 + avalanche_hw0_chregs->cintnr9 = line;
690 + break;
691 + case(10):
692 + avalanche_hw0_chregs->cintnr10 = line;
693 + break;
694 + case(11):
695 + avalanche_hw0_chregs->cintnr11 = line;
696 + break;
697 + case(12):
698 + avalanche_hw0_chregs->cintnr12 = line;
699 + break;
700 + case(13):
701 + avalanche_hw0_chregs->cintnr13 = line;
702 + break;
703 + case(14):
704 + avalanche_hw0_chregs->cintnr14 = line;
705 + break;
706 + case(15):
707 + avalanche_hw0_chregs->cintnr15 = line;
708 + break;
709 + case(16):
710 + avalanche_hw0_chregs->cintnr16 = line;
711 + break;
712 + case(17):
713 + avalanche_hw0_chregs->cintnr17 = line;
714 + break;
715 + case(18):
716 + avalanche_hw0_chregs->cintnr18 = line;
717 + break;
718 + case(19):
719 + avalanche_hw0_chregs->cintnr19 = line;
720 + break;
721 + case(20):
722 + avalanche_hw0_chregs->cintnr20 = line;
723 + break;
724 + case(21):
725 + avalanche_hw0_chregs->cintnr21 = line;
726 + break;
727 + case(22):
728 + avalanche_hw0_chregs->cintnr22 = line;
729 + break;
730 + case(23):
731 + avalanche_hw0_chregs->cintnr23 = line;
732 + break;
733 + case(24):
734 + avalanche_hw0_chregs->cintnr24 = line;
735 + break;
736 + case(25):
737 + avalanche_hw0_chregs->cintnr25 = line;
738 + break;
739 + case(26):
740 + avalanche_hw0_chregs->cintnr26 = line;
741 + break;
742 + case(27):
743 + avalanche_hw0_chregs->cintnr27 = line;
744 + break;
745 + case(28):
746 + avalanche_hw0_chregs->cintnr28 = line;
747 + break;
748 + case(29):
749 + avalanche_hw0_chregs->cintnr29 = line;
750 + break;
751 + case(30):
752 + avalanche_hw0_chregs->cintnr30 = line;
753 + break;
754 + case(31):
755 + avalanche_hw0_chregs->cintnr31 = line;
756 + break;
757 + case(32):
758 + avalanche_hw0_chregs->cintnr32 = line;
759 + break;
760 + case(33):
761 + avalanche_hw0_chregs->cintnr33 = line;
762 + break;
763 + case(34):
764 + avalanche_hw0_chregs->cintnr34 = line;
765 + break;
766 + case(35):
767 + avalanche_hw0_chregs->cintnr35 = line;
768 + break;
769 + case(36):
770 + avalanche_hw0_chregs->cintnr36 = line;
771 + break;
772 + case(37):
773 + avalanche_hw0_chregs->cintnr37 = line;
774 + break;
775 + case(38):
776 + avalanche_hw0_chregs->cintnr38 = line;
777 + break;
778 + case(39):
779 + avalanche_hw0_chregs->cintnr39 = line;
780 + break;
781 + default:
782 + printk("Error: Unknown Avalanche interrupt channel\n");
783 + }
784 +
785 + line_to_channel[line] = channel; /* Suraj check */
786 +
787 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
788 + uni_secondary_interrupt = line;
789 +
790 +}
791 +
792 +
793 +#define AVALANCHE_MAX_PACING_BLK 3
794 +#define AVALANCHE_PACING_LOW_VAL 2
795 +#define AVALANCHE_PACING_HIGH_VAL 63
796 +
797 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
798 + unsigned int pace_value)
799 +{
800 + unsigned int blk_offset;
801 + unsigned long flags;
802 +
803 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
804 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
805 + return (0);
806 +
807 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
808 + return(-1);
809 +
810 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
811 + pace_value < AVALANCHE_PACING_LOW_VAL)
812 + return(-1);
813 +
814 + blk_offset = blk_num*8;
815 +
816 + save_and_cli(flags);
817 +
818 + /* disable the interrupt pacing, if enabled previously */
819 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
820 +
821 + /* clear the pacing map */
822 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
823 +
824 + /* setup the new values */
825 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
826 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
827 +
828 + restore_flags(flags);
829 +
830 + return(0);
831 +}
832 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
833 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
834 +++ linux.dev/arch/mips/ar7/memory.c 2005-11-10 01:14:16.372731750 +0100
835 @@ -0,0 +1,103 @@
836 +/*
837 + * Carsten Langgaard, carstenl@mips.com
838 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
839 + *
840 + * ########################################################################
841 + *
842 + * This program is free software; you can distribute it and/or modify it
843 + * under the terms of the GNU General Public License (Version 2) as
844 + * published by the Free Software Foundation.
845 + *
846 + * This program is distributed in the hope it will be useful, but WITHOUT
847 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
848 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
849 + * for more details.
850 + *
851 + * You should have received a copy of the GNU General Public License along
852 + * with this program; if not, write to the Free Software Foundation, Inc.,
853 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
854 + *
855 + * ########################################################################
856 + *
857 + */
858 +
859 +#include <linux/config.h>
860 +#include <linux/init.h>
861 +#include <linux/mm.h>
862 +#include <linux/bootmem.h>
863 +
864 +#include <asm/bootinfo.h>
865 +#include <asm/page.h>
866 +#include <asm/mips-boards/prom.h>
867 +
868 +extern char _ftext;
869 +extern int preserve_adam2;
870 +
871 +void __init prom_meminit(void)
872 +{
873 + char *memsize_str;
874 + unsigned long memsize, adam2size;
875 +
876 + /* assume block before kernel is used by bootloader */
877 + adam2size = __pa(&_ftext) - PHYS_OFFSET;
878 +
879 + memsize_str = prom_getenv("memsize");
880 + if (!memsize_str) {
881 + memsize = 0x02000000;
882 + } else {
883 + memsize = simple_strtol(memsize_str, NULL, 0);
884 + }
885 +
886 +#if 0
887 + add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
888 +#endif
889 + add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
890 + add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
891 + BOOT_MEM_RAM);
892 +}
893 +
894 +unsigned long __init prom_free_prom_memory (void)
895 +{
896 + int i;
897 + unsigned long freed = 0;
898 + unsigned long addr;
899 +
900 + if (preserve_adam2) {
901 + char *firstfree_str = prom_getenv("firstfreeaddress");
902 + unsigned long firstfree = 0;
903 +
904 + if (firstfree_str)
905 + firstfree = simple_strtol(firstfree_str, NULL, 0);
906 +
907 + if (firstfree && firstfree < (unsigned long)&_ftext) {
908 + printk("Preserving ADAM2 memory.\n");
909 + } else if (firstfree) {
910 + printk("Can't preserve ADAM2 memory, "
911 + "firstfreeaddress = %08lx.\n", firstfree);
912 + preserve_adam2 = 0;
913 + } else {
914 + printk("Can't preserve ADAM2 memory, "
915 + "firstfreeaddress unknown!\n");
916 + preserve_adam2 = 0;
917 + }
918 + }
919 +
920 + if (!preserve_adam2) {
921 + for (i = 0; i < boot_mem_map.nr_map; i++) {
922 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
923 + continue;
924 +
925 + addr = boot_mem_map.map[i].addr;
926 + while (addr < boot_mem_map.map[i].addr
927 + + boot_mem_map.map[i].size) {
928 + ClearPageReserved(virt_to_page(__va(addr)));
929 + set_page_count(virt_to_page(__va(addr)), 1);
930 + free_page((unsigned long)__va(addr));
931 + addr += PAGE_SIZE;
932 + freed += PAGE_SIZE;
933 + }
934 + }
935 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
936 + }
937 + return freed >> PAGE_SHIFT;
938 +}
939 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
940 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
941 +++ linux.dev/arch/mips/ar7/misc.c 2005-11-10 01:12:43.946955500 +0100
942 @@ -0,0 +1,322 @@
943 +#include <asm/ar7/sangam.h>
944 +#include <asm/ar7/avalanche_misc.h>
945 +#include <linux/module.h>
946 +#include <linux/spinlock.h>
947 +
948 +#define TRUE 1
949 +
950 +static unsigned int avalanche_vbus_freq;
951 +
952 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
953 +
954 +/*****************************************************************************
955 + * Reset Control Module.
956 + *****************************************************************************/
957 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
958 + AVALANCHE_RESET_CTRL_T reset_ctrl)
959 +{
960 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
961 +
962 + if(module_reset_bit >= 32 && module_reset_bit < 64)
963 + return;
964 +
965 + if(module_reset_bit >= 64)
966 + {
967 + if(p_remote_vlynq_dev_reset_ctrl) {
968 + p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
969 + return;
970 + }
971 + else
972 + return;
973 + }
974 +
975 + if(reset_ctrl == OUT_OF_RESET)
976 + *reset_reg |= 1 << module_reset_bit;
977 + else
978 + *reset_reg &= ~(1 << module_reset_bit);
979 + return;
980 +}
981 +
982 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
983 +{
984 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
985 +
986 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
987 +}
988 +
989 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
990 +{
991 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
992 + *sw_reset_reg = mode;
993 +}
994 +
995 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
996 +
997 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
998 +{
999 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1000 +
1001 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1002 +}
1003 +
1004 +
1005 +/*****************************************************************************
1006 + * Power Control Module
1007 + *****************************************************************************/
1008 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1009 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1010 +
1011 +
1012 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1013 +{
1014 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1015 +
1016 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1017 + /* power down the module */
1018 + *power_reg |= (1 << module_power_bit);
1019 + else
1020 + /* power on the module */
1021 + *power_reg &= (~(1 << module_power_bit));
1022 +}
1023 +
1024 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1025 +{
1026 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1027 +
1028 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1029 +}
1030 +
1031 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1032 +{
1033 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1034 +
1035 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1036 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1037 +}
1038 +
1039 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1040 +{
1041 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1042 +
1043 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1044 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1045 +}
1046 +
1047 +/*****************************************************************************
1048 + * GPIO Control
1049 + *****************************************************************************/
1050 +
1051 +/****************************************************************************
1052 + * FUNCTION: avalanche_gpio_init
1053 + ***************************************************************************/
1054 +void avalanche_gpio_init(void)
1055 +{
1056 + spinlock_t closeLock;
1057 + unsigned int closeFlag;
1058 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1059 + spin_lock_irqsave(&closeLock, closeFlag);
1060 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1061 + spin_unlock_irqrestore(&closeLock, closeFlag);
1062 +}
1063 +
1064 +/****************************************************************************
1065 + * FUNCTION: avalanche_gpio_ctrl
1066 + ***************************************************************************/
1067 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1068 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1069 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1070 +{
1071 + spinlock_t closeLock;
1072 + unsigned int closeFlag;
1073 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1074 +
1075 + if(gpio_pin >= 32)
1076 + return(-1);
1077 +
1078 + spin_lock_irqsave(&closeLock, closeFlag);
1079 +
1080 + if(pin_mode == GPIO_PIN)
1081 + {
1082 + *gpio_ctrl |= (1 << gpio_pin);
1083 +
1084 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1085 +
1086 + if(pin_direction == GPIO_INPUT_PIN)
1087 + *gpio_ctrl |= (1 << gpio_pin);
1088 + else
1089 + *gpio_ctrl &= ~(1 << gpio_pin);
1090 + }
1091 + else /* FUNCTIONAL PIN */
1092 + {
1093 + *gpio_ctrl &= ~(1 << gpio_pin);
1094 + }
1095 +
1096 + spin_unlock_irqrestore(&closeLock, closeFlag);
1097 +
1098 + return (0);
1099 +}
1100 +
1101 +/****************************************************************************
1102 + * FUNCTION: avalanche_gpio_out
1103 + ***************************************************************************/
1104 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1105 +{
1106 + spinlock_t closeLock;
1107 + unsigned int closeFlag;
1108 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1109 +
1110 + if(gpio_pin >= 32)
1111 + return(-1);
1112 +
1113 + spin_lock_irqsave(&closeLock, closeFlag);
1114 + if(value == TRUE)
1115 + *gpio_out |= 1 << gpio_pin;
1116 + else
1117 + *gpio_out &= ~(1 << gpio_pin);
1118 + spin_unlock_irqrestore(&closeLock, closeFlag);
1119 +
1120 + return(0);
1121 +}
1122 +
1123 +/****************************************************************************
1124 + * FUNCTION: avalanche_gpio_in
1125 + ***************************************************************************/
1126 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1127 +{
1128 + spinlock_t closeLock;
1129 + unsigned int closeFlag;
1130 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1131 + int ret_val = 0;
1132 +
1133 + if(gpio_pin >= 32)
1134 + return(-1);
1135 +
1136 + spin_lock_irqsave(&closeLock, closeFlag);
1137 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1138 + spin_unlock_irqrestore(&closeLock, closeFlag);
1139 +
1140 + return (ret_val);
1141 +}
1142 +
1143 +/****************************************************************************
1144 + * FUNCTION: avalanche_gpio_out_val
1145 + ***************************************************************************/
1146 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1147 + unsigned int reg_index)
1148 +{
1149 + spinlock_t closeLock;
1150 + unsigned int closeFlag;
1151 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1152 +
1153 + if(reg_index > 0)
1154 + return(-1);
1155 +
1156 + spin_lock_irqsave(&closeLock, closeFlag);
1157 + *gpio_out &= ~out_mask;
1158 + *gpio_out |= out_val;
1159 + spin_unlock_irqrestore(&closeLock, closeFlag);
1160 +
1161 + return(0);
1162 +}
1163 +
1164 +/****************************************************************************
1165 + * FUNCTION: avalanche_gpio_in_value
1166 + ***************************************************************************/
1167 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1168 +{
1169 + spinlock_t closeLock;
1170 + unsigned int closeFlag;
1171 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1172 +
1173 + if(reg_index > 0)
1174 + return(-1);
1175 +
1176 + spin_lock_irqsave(&closeLock, closeFlag);
1177 + *in_val = *gpio_in;
1178 + spin_unlock_irqrestore(&closeLock, closeFlag);
1179 +
1180 + return (0);
1181 +}
1182 +
1183 +/***********************************************************************
1184 + *
1185 + * Wakeup Control Module for TNETV1050 Communication Processor
1186 + *
1187 + ***********************************************************************/
1188 +
1189 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1190 +
1191 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1192 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1193 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1194 +{
1195 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1196 +
1197 + /* enable/disable */
1198 + if (wakeup_ctrl == WAKEUP_ENABLED)
1199 + /* enable wakeup */
1200 + *wakeup_status_reg |= wakeup_int;
1201 + else
1202 + /* disable wakeup */
1203 + *wakeup_status_reg &= (~wakeup_int);
1204 +
1205 + /* set polarity */
1206 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1207 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1208 + else
1209 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1210 +}
1211 +
1212 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1213 +{
1214 + avalanche_vbus_freq = new_vbus_freq;
1215 +}
1216 +
1217 +unsigned int avalanche_get_vbus_freq()
1218 +{
1219 + return(avalanche_vbus_freq);
1220 +}
1221 +
1222 +unsigned int avalanche_get_chip_version_info()
1223 +{
1224 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1225 +}
1226 +
1227 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1228 +
1229 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1230 +{
1231 + if(p_set_mdix_on_chip_fn)
1232 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1233 + else
1234 + return(-1);
1235 +}
1236 +
1237 +unsigned int avalanche_is_mdix_on_chip(void)
1238 +{
1239 + return(p_set_mdix_on_chip_fn ? 1:0);
1240 +}
1241 +
1242 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1243 +EXPORT_SYMBOL(avalanche_get_reset_status);
1244 +EXPORT_SYMBOL(avalanche_sys_reset);
1245 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1246 +EXPORT_SYMBOL(avalanche_power_ctrl);
1247 +EXPORT_SYMBOL(avalanche_get_power_status);
1248 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1249 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1250 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1251 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1252 +
1253 +EXPORT_SYMBOL(avalanche_gpio_init);
1254 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1255 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1256 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1257 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1258 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1259 +
1260 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1261 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1262 +
1263 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1264 +
1265 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1266 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1267 +++ linux.dev/arch/mips/ar7/platform.h 2005-11-10 01:10:45.799571750 +0100
1268 @@ -0,0 +1,65 @@
1269 +#ifndef _PLATFORM_H_
1270 +#define _PLATFORM_H_
1271 +
1272 +#include <linux/config.h>
1273 +
1274 +
1275 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1276 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1277 + */
1278 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1279 +#define ENV_SPACE_SIZE (10 * 1024)
1280 +#endif
1281 +
1282 +#ifdef CONFIG_MIPS_TNETV1050SDB
1283 +#define TNETV1050SDB
1284 +#define DUAL_FLASH
1285 +#endif
1286 +
1287 +#ifdef CONFIG_MIPS_AR7DB
1288 +#define TNETD73XX_BOARD
1289 +#define AR7DB
1290 +#endif
1291 +
1292 +#ifdef CONFIG_MIPS_AR7RD
1293 +#define TNETD73XX_BOARD
1294 +#define AR7RD
1295 +#endif
1296 +
1297 +#ifdef CONFIG_AR7WRD
1298 +#define TNETD73XX_BOARD
1299 +#define AR7WRD
1300 +#endif
1301 +
1302 +#ifdef CONFIG_MIPS_AR7VWI
1303 +#define TNETD73XX_BOARD
1304 +#define AR7VWi
1305 +#endif
1306 +
1307 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1308 +#ifdef CONFIG_MIPS_AR7VW
1309 +#define TNETD73XX_BOARD
1310 +#define AR7WRD
1311 +#endif
1312 +
1313 +#ifdef CONFIG_MIPS_AR7WI
1314 +#define TNETD73XX_BOARD
1315 +#define AR7Wi
1316 +#endif
1317 +
1318 +#ifdef CONFIG_MIPS_AR7V
1319 +#define TNETD73XX_BOARD
1320 +#define AR7V
1321 +#endif
1322 +
1323 +#ifdef CONFIG_MIPS_AR7V
1324 +#define TNETD73XX_BOARD
1325 +#define AR7V
1326 +#endif
1327 +
1328 +#ifdef CONFIG_MIPS_WA1130
1329 +#define AVALANCHE
1330 +#define WLAN
1331 +#endif
1332 +
1333 +#endif
1334 diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
1335 --- linux.old/arch/mips/ar7/promlib.c 1970-01-01 01:00:00.000000000 +0100
1336 +++ linux.dev/arch/mips/ar7/promlib.c 2005-11-10 01:14:16.372731750 +0100
1337 @@ -0,0 +1,48 @@
1338 +/*
1339 + * Carsten Langgaard, carstenl@mips.com
1340 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1341 + *
1342 + * This program is free software; you can distribute it and/or modify it
1343 + * under the terms of the GNU General Public License (Version 2) as
1344 + * published by the Free Software Foundation.
1345 + *
1346 + * This program is distributed in the hope it will be useful, but WITHOUT
1347 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1348 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1349 + * for more details.
1350 + *
1351 + * You should have received a copy of the GNU General Public License along
1352 + * with this program; if not, write to the Free Software Foundation, Inc.,
1353 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1354 + *
1355 + * Putting things on the screen/serial line using Adam2 facilities.
1356 + */
1357 +
1358 +#include <linux/types.h>
1359 +#include <asm/addrspace.h>
1360 +
1361 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1362 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
1363 + (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
1364 +#define AVALANCHE_YAMON_PROM_EXIT \
1365 + (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
1366 +
1367 +void prom_putchar(char c)
1368 +{
1369 + static char buf[1];
1370 + void (*prom_print_str)(unsigned int dummy, char *s, int len) =
1371 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
1372 +
1373 + buf[0] = c;
1374 + prom_print_str(1, buf, 1);
1375 + return;
1376 +}
1377 +
1378 +void adam2_exit(int retval)
1379 +{
1380 + void (*yamon_exit)(int retval) =
1381 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
1382 +
1383 + yamon_exit(retval);
1384 + return;
1385 +}
1386 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1387 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1388 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-11-10 01:10:45.799571750 +0100
1389 @@ -0,0 +1,350 @@
1390 +#include <linux/config.h>
1391 +#include <linux/init.h>
1392 +#include <linux/string.h>
1393 +#include <linux/kernel.h>
1394 +#include <linux/module.h>
1395 +#include <asm/io.h>
1396 +
1397 +#include "platform.h"
1398 +
1399 +#define ENV_CELL_SIZE 16
1400 +
1401 +/* control field decode */
1402 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1403 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1404 +
1405 +#define ENV_CTRL_MASK 0x03
1406 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1407 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1408 +
1409 +struct env_variable {
1410 + unsigned char varNum;
1411 + unsigned char ctrl;
1412 + unsigned short chksum;
1413 + unsigned char numCells;
1414 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1415 + * here, continues for
1416 + * numCells.
1417 + */
1418 +};
1419 +
1420 +extern unsigned int max_env_entry;
1421 +
1422 +/* Internal macros */
1423 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1424 +
1425 +typedef enum ENV_VARS {
1426 + env_vars_start = 0,
1427 + CPUFREQ,
1428 + MEMSZ,
1429 + FLASHSZ,
1430 + MODETTY0,
1431 + MODETTY1,
1432 + PROMPT,
1433 + BOOTCFG,
1434 + HWA_0,
1435 +#if !defined (AVALANCHE) || defined(TNETC401B)
1436 + HWA_1,
1437 +#endif
1438 +#if !defined(TNETV1020_BOARD)
1439 + HWA_RNDIS,
1440 +#endif
1441 +#if defined (TNETD73XX_BOARD)
1442 + HWA_3,
1443 +#endif
1444 + IPA,
1445 + IPA_SVR,
1446 + BLINE_MAC0,
1447 +#if !defined (AVALANCHE) || defined(TNETC401B)
1448 + BLINE_MAC1,
1449 +#endif
1450 +#if !defined(TNETV1020_BOARD)
1451 + BLINE_RNDIS,
1452 +#endif
1453 +#if defined (TNETD73XX_BOARD)
1454 + BLINE_ATM,
1455 +#endif
1456 +#if !defined(TNETV1020_BOARD)
1457 + USB_PID,
1458 + USB_VID,
1459 + USB_EPPOLLI,
1460 +#endif
1461 + IPA_GATEWAY,
1462 + SUBNET_MASK,
1463 +#if defined (TNETV1050_BOARD)
1464 + BLINE_ESWITCH,
1465 +#endif
1466 +#if !defined(TNETV1020_BOARD)
1467 + USB_SERIAL,
1468 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
1469 +#endif
1470 + REMOTE_USER,
1471 + REMOTE_PASS,
1472 + REMOTE_DIR,
1473 + SYSFREQ,
1474 + LINK_TIMEOUT,
1475 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1476 + MAC_PORT,
1477 +#endif
1478 + PATH,
1479 + HOSTNAME,
1480 +#ifdef WLAN
1481 + HW_REV_MAJOR,
1482 + HW_REV_MINOR,
1483 + HW_PATCH,
1484 + SW_PATCH,
1485 + SERIAL_NUMBER,
1486 +#endif
1487 + TFTPCFG,
1488 +#if defined (TNETV1050_BOARD)
1489 + HWA_ESWITCH,
1490 +#endif
1491 + /*
1492 + * Add new env variables here.
1493 + * NOTE: New environment variables should always be placed at the end, ie
1494 + * just before env_vars_end.
1495 + */
1496 +
1497 + env_vars_end
1498 +} ENV_VARS;
1499 +
1500 +
1501 +struct env_description {
1502 + ENV_VARS idx;
1503 + char *nm;
1504 + char *alias;
1505 +};
1506 +
1507 +#define ENVSTR(x) #x
1508 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1509 +
1510 +struct env_description env_ns[] = {
1511 + _ENV_ENTRY(env_vars_start), /* start. */
1512 + _ENV_ENTRY(CPUFREQ),
1513 + _ENV_ENTRY(MEMSZ),
1514 + _ENV_ENTRY(FLASHSZ),
1515 + _ENV_ENTRY(MODETTY0),
1516 + _ENV_ENTRY(MODETTY1),
1517 + _ENV_ENTRY(PROMPT),
1518 + _ENV_ENTRY(BOOTCFG),
1519 + _ENV_ENTRY(HWA_0),
1520 +#if !defined (AVALANCHE) || defined(TNETC401B)
1521 + _ENV_ENTRY(HWA_1),
1522 +#endif
1523 +#if !defined(TNETV1020_BOARD)
1524 + _ENV_ENTRY(HWA_RNDIS),
1525 +#endif
1526 +#if defined (TNETD73XX_BOARD)
1527 + _ENV_ENTRY(HWA_3),
1528 +#endif
1529 + _ENV_ENTRY(IPA),
1530 + _ENV_ENTRY(IPA_SVR),
1531 + _ENV_ENTRY(IPA_GATEWAY),
1532 + _ENV_ENTRY(SUBNET_MASK),
1533 + _ENV_ENTRY(BLINE_MAC0),
1534 +#if !defined (AVALANCHE) || defined(TNETC401B)
1535 + _ENV_ENTRY(BLINE_MAC1),
1536 +#endif
1537 +#if !defined(TNETV1020_BOARD)
1538 + _ENV_ENTRY(BLINE_RNDIS),
1539 +#endif
1540 +#if defined (TNETD73XX_BOARD)
1541 + _ENV_ENTRY(BLINE_ATM),
1542 +#endif
1543 +#if !defined(TNETV1020_BOARD)
1544 + _ENV_ENTRY(USB_PID),
1545 + _ENV_ENTRY(USB_VID),
1546 + _ENV_ENTRY(USB_EPPOLLI),
1547 +#endif
1548 +#if defined (TNETV1050_BOARD)
1549 + _ENV_ENTRY(BLINE_ESWITCH),
1550 +#endif
1551 +#if !defined(TNETV1020_BOARD)
1552 + _ENV_ENTRY(USB_SERIAL),
1553 + _ENV_ENTRY(HWA_HRNDIS),
1554 +#endif
1555 + _ENV_ENTRY(REMOTE_USER),
1556 + _ENV_ENTRY(REMOTE_PASS),
1557 + _ENV_ENTRY(REMOTE_DIR),
1558 + _ENV_ENTRY(SYSFREQ),
1559 + _ENV_ENTRY(LINK_TIMEOUT),
1560 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1561 + _ENV_ENTRY(MAC_PORT),
1562 +#endif
1563 + _ENV_ENTRY(PATH),
1564 + _ENV_ENTRY(HOSTNAME),
1565 +#ifdef WLAN
1566 + _ENV_ENTRY(HW_REV_MAJOR),
1567 + _ENV_ENTRY(HW_REV_MINOR),
1568 + _ENV_ENTRY(HW_PATCH),
1569 + _ENV_ENTRY(SW_PATCH),
1570 + _ENV_ENTRY(SERIAL_NUMBER),
1571 +#endif
1572 + _ENV_ENTRY(TFTPCFG),
1573 +#if defined (TNETV1050_BOARD)
1574 + _ENV_ENTRY(HWA_ESWITCH),
1575 +#endif
1576 + /*
1577 + * Add new entries below this.
1578 + */
1579 + /* Adam2 environment name alias. */
1580 + { .idx = IPA, .nm = "my_ipaddress" },
1581 + { .idx = CPUFREQ, .nm = "cpufrequency" },
1582 + { .idx = SYSFREQ, .nm = "sysfrequency" },
1583 + { .idx = HWA_0, .nm = "maca" },
1584 +#ifndef AVALANCHE
1585 + { .idx = HWA_1, .nm = "macb" },
1586 +#endif
1587 + { .idx = MODETTY0, .nm = "modetty0" },
1588 + { .idx = MODETTY1, .nm = "modetty1" },
1589 + { .idx = MEMSZ, .nm = "memsize" },
1590 +
1591 + _ENV_ENTRY(env_vars_end) /* delimiter. */
1592 +};
1593 +
1594 +static inline int var_to_idx(const char* var)
1595 +{
1596 + int ii;
1597 +
1598 + /* go over the list of pre-defined environment variables */
1599 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1600 + /* check if the env variable is listed */
1601 + if (strcmp(env_ns[ii].nm, var) == 0) {
1602 + return env_ns[ii].idx;
1603 + }
1604 +
1605 + /* if an alias is present, check if the alias matches
1606 + * the description
1607 + */
1608 + if (env_ns[ii].alias != NULL) {
1609 + if (strcmp(env_ns[ii].alias, var) == 0) {
1610 + return env_ns[ii].idx;
1611 + }
1612 + }
1613 + }
1614 + return 0;
1615 +}
1616 +
1617 +extern int *_prom_envp;
1618 +
1619 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1620 + * the next read some seconds later is ok. It looks like something is hidding or
1621 + * overlay the flash address at 0xb0000000. Is this possible?
1622 + *
1623 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
1624 + */
1625 +
1626 +static inline struct env_variable* get_var_by_number(int index)
1627 +{
1628 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1629 + volatile unsigned char nr;
1630 + int i;
1631 +
1632 + env_var++; /* skip signature */
1633 +
1634 + i = 0;
1635 + nr = readb(&(env_var->varNum));
1636 +
1637 + while (i < max_env_entry && nr != 0xFF) {
1638 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1639 + if (nr == index) {
1640 + return env_var;
1641 + }
1642 + }
1643 + i++;
1644 + env_var = get_next_block(env_var);
1645 + nr = readb(&(env_var->varNum));
1646 + }
1647 +
1648 + return NULL;
1649 +}
1650 +
1651 +static inline struct env_variable* get_var_by_name(char *var)
1652 +{
1653 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1654 + volatile unsigned char nr;
1655 + int i;
1656 +
1657 + env_var++; /* skip signature */
1658 +
1659 + nr = readb(&(env_var->varNum));
1660 + i = 0;
1661 +
1662 + while (i < max_env_entry && nr != 0xFF) {
1663 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1664 + if (strcmp(var, env_var->data) == 0)
1665 + return env_var;
1666 + }
1667 + i++;
1668 + env_var = get_next_block(env_var);
1669 + nr = readb(&(env_var->varNum));
1670 + }
1671 + return NULL;
1672 +}
1673 +
1674 +static inline struct env_variable* get_var(char *var)
1675 +{
1676 + int index = var_to_idx(var);
1677 +
1678 + if (index)
1679 + return get_var_by_number(index);
1680 + else
1681 + return get_var_by_name(var);
1682 +
1683 + return NULL;
1684 +}
1685 +
1686 +static inline char *get_value(struct env_variable* env_var)
1687 +{
1688 + unsigned char *name;
1689 + unsigned char *value;
1690 + unsigned short chksum;
1691 + int i;
1692 +
1693 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
1694 +
1695 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1696 + name = env_var->data;
1697 + value = env_var->data + strlen(name) + 1;
1698 +
1699 + for(i = 0; i < strlen(name); i++)
1700 + chksum += name[i];
1701 + } else
1702 + value = env_var->data;
1703 +
1704 + for (i = 0; i < strlen(value); i++)
1705 + chksum += value[i];
1706 +
1707 + chksum += env_var->chksum;
1708 + chksum = ~(chksum);
1709 +
1710 + if(chksum != 0) {
1711 + return NULL;
1712 + }
1713 +
1714 + return value;
1715 +}
1716 +
1717 +struct psbl_rec {
1718 + unsigned int psbl_size;
1719 + unsigned int env_base;
1720 + unsigned int env_size;
1721 + unsigned int ffs_base;
1722 + unsigned int ffs_size;
1723 +};
1724 +
1725 +char *prom_psp_getenv(char *envname)
1726 +{
1727 + struct env_variable* env_var;
1728 + char *value;
1729 +
1730 + if (strcmp("bootloader", envname) == 0)
1731 + return "PSPBoot";
1732 +
1733 + if (!(env_var = get_var(envname)))
1734 + return NULL;
1735 +
1736 + value = get_value(env_var);
1737 +
1738 + return value;
1739 +}
1740 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1741 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1742 +++ linux.dev/arch/mips/ar7/reset.c 2005-11-10 01:14:16.372731750 +0100
1743 @@ -0,0 +1,98 @@
1744 +/*
1745 + * Carsten Langgaard, carstenl@mips.com
1746 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1747 + *
1748 + * ########################################################################
1749 + *
1750 + * This program is free software; you can distribute it and/or modify it
1751 + * under the terms of the GNU General Public License (Version 2) as
1752 + * published by the Free Software Foundation.
1753 + *
1754 + * This program is distributed in the hope it will be useful, but WITHOUT
1755 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1756 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1757 + * for more details.
1758 + *
1759 + * You should have received a copy of the GNU General Public License along
1760 + * with this program; if not, write to the Free Software Foundation, Inc.,
1761 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1762 + *
1763 + * ########################################################################
1764 + *
1765 + * Reset the AR7 boards.
1766 + *
1767 + */
1768 +
1769 +#include <linux/init.h>
1770 +#include <linux/kernel.h>
1771 +#include <linux/string.h>
1772 +#include <linux/types.h>
1773 +
1774 +#include <asm/mipsregs.h>
1775 +#include <asm/reboot.h>
1776 +#include <asm/addrspace.h>
1777 +
1778 +int preserve_adam2 = 1;
1779 +
1780 +extern void adam2_exit(int retval);
1781 +
1782 +static void ar7_machine_restart(char *command);
1783 +static void ar7_machine_halt(void);
1784 +static void ar7_machine_power_off(void);
1785 +
1786 +static void ar7_machine_restart(char *command)
1787 +{
1788 + volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
1789 +
1790 + *softres_reg = 1;
1791 +}
1792 +
1793 +static void ar7_machine_halt(void)
1794 +{
1795 +
1796 + if (preserve_adam2) {
1797 + set_c0_status(ST0_BEV);
1798 + adam2_exit(0);
1799 + } else {
1800 + /* I'd like to have Alt-SysRq-b work in this state.
1801 + * What's missing here? The timer interrupt is still running.
1802 + * Why doesn't the UART work anymore? */
1803 + while(1) {
1804 + __asm__(".set\tmips3\n\t"
1805 + "wait\n\t"
1806 + ".set\tmips0");
1807 + }
1808 + }
1809 +}
1810 +
1811 +static void ar7_machine_power_off(void)
1812 +{
1813 + volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
1814 + uint32_t power_state = *power_reg;
1815 +
1816 + /* add something to turn LEDs off? */
1817 +
1818 + power_state &= ~(3 << 30);
1819 + power_state |= (3 << 30); /* power down */
1820 + *power_reg = power_state;
1821 +
1822 + printk("after power down?\n");
1823 +}
1824 +
1825 +void ar7_reboot_setup(void)
1826 +{
1827 + _machine_restart = ar7_machine_restart;
1828 + _machine_halt = ar7_machine_halt;
1829 + _machine_power_off = ar7_machine_power_off;
1830 +}
1831 +
1832 +static int __init ar7_do_preserve_adam2(char *s)
1833 +{
1834 + if (!strcmp(s, "no") || !strcmp(s, "0"))
1835 + preserve_adam2 = 0;
1836 + else
1837 + preserve_adam2 = 1;
1838 + return 1;
1839 +}
1840 +
1841 +__setup("adam2=", ar7_do_preserve_adam2);
1842 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1843 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1844 +++ linux.dev/arch/mips/ar7/setup.c 2005-11-10 01:12:43.946955500 +0100
1845 @@ -0,0 +1,143 @@
1846 +/*
1847 + * Carsten Langgaard, carstenl@mips.com
1848 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1849 + *
1850 + * This program is free software; you can distribute it and/or modify it
1851 + * under the terms of the GNU General Public License (Version 2) as
1852 + * published by the Free Software Foundation.
1853 + *
1854 + * This program is distributed in the hope it will be useful, but WITHOUT
1855 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1856 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1857 + * for more details.
1858 + *
1859 + * You should have received a copy of the GNU General Public License along
1860 + * with this program; if not, write to the Free Software Foundation, Inc.,
1861 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1862 + */
1863 +
1864 +#include <linux/config.h>
1865 +#include <linux/init.h>
1866 +#include <linux/string.h>
1867 +#include <linux/irq.h>
1868 +
1869 +#include <asm/processor.h>
1870 +#include <asm/irq.h>
1871 +#include <asm/irq_cpu.h>
1872 +#include <asm/time.h>
1873 +#include <asm/mipsregs.h>
1874 +#include <asm/mips-boards/prom.h>
1875 +
1876 +#ifdef CONFIG_KGDB
1877 +extern void rs_kgdb_hook(int);
1878 +extern void breakpoint(void);
1879 +int remote_debug = 0;
1880 +#endif
1881 +
1882 +extern void ar7_reboot_setup(void);
1883 +extern void ar7_irq_init(int);
1884 +extern asmlinkage void ar7IRQ(void);
1885 +
1886 +void ar7_time_init(void)
1887 +{
1888 + /* XXX runtime */
1889 + mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
1890 +}
1891 +
1892 +void ar7_timer_setup(struct irqaction *irq)
1893 +{
1894 + setup_irq(7, irq);
1895 + set_c0_status(IE_IRQ5);
1896 +}
1897 +
1898 +void __init init_IRQ(void)
1899 +{
1900 + init_generic_irq();
1901 + mips_cpu_irq_init(0);
1902 + ar7_irq_init(8);
1903 +
1904 + /* Now safe to set the exception vector. */
1905 + set_except_vector(0, ar7IRQ);
1906 +
1907 +#ifdef CONFIG_KGDB
1908 + if (remote_debug)
1909 + {
1910 + set_debug_traps();
1911 + breakpoint();
1912 + }
1913 +#endif
1914 +}
1915 +
1916 +const char *get_system_type(void)
1917 +{
1918 + return "Texas Instruments AR7";
1919 +}
1920 +
1921 +void __init ar7_setup(void)
1922 +{
1923 +#ifdef CONFIG_KGDB
1924 + int rs_putDebugChar(char);
1925 + char rs_getDebugChar(void);
1926 + extern int (*generic_putDebugChar)(char);
1927 + extern char (*generic_getDebugChar)(void);
1928 +#endif
1929 + char *argptr;
1930 +#ifdef CONFIG_SERIAL_CONSOLE
1931 + argptr = prom_getcmdline();
1932 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1933 + char console[20];
1934 + char *s;
1935 + int i = 0;
1936 +
1937 + s = prom_getenv("modetty0");
1938 + strcpy(console, "38400");
1939 +
1940 + if (s != NULL) {
1941 + while (s[i] >= '0' && s[i] <= '9')
1942 + i++;
1943 +
1944 + if (i > 0) {
1945 + strncpy(console, s, i);
1946 + console[i] = 0;
1947 + }
1948 + }
1949 +
1950 + argptr = prom_getcmdline();
1951 + strcat(argptr, " console=ttyS0,");
1952 + strcat(argptr, console);
1953 + }
1954 +#endif
1955 +
1956 +#ifdef CONFIG_KGDB
1957 + argptr = prom_getcmdline();
1958 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1959 + int line;
1960 + argptr += strlen("kgdb=ttyS");
1961 + if (*argptr != '0' && *argptr != '1')
1962 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1963 + "falling back to /dev/ttyS1\n", *argptr);
1964 + line = *argptr == '0' ? 0 : 1;
1965 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1966 + line ? 1 : 0);
1967 +
1968 + rs_kgdb_hook(line);
1969 + generic_putDebugChar = rs_putDebugChar;
1970 + generic_getDebugChar = rs_getDebugChar;
1971 +
1972 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1973 + "please connect your debugger\n", line ? 1 : 0);
1974 +
1975 + remote_debug = 1;
1976 + /* Breakpoints are in init_IRQ() */
1977 + }
1978 +#endif
1979 +
1980 + argptr = prom_getcmdline();
1981 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1982 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1983 +
1984 + ar7_reboot_setup();
1985 +
1986 + board_time_init = ar7_time_init;
1987 + board_timer_setup = ar7_timer_setup;
1988 +}
1989 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
1990 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
1991 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-11-10 01:12:43.946955500 +0100
1992 @@ -0,0 +1,921 @@
1993 +/******************************************************************************
1994 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1995 + ******************************************************************************
1996 + * FILE NAME: tnetd73xx_misc.c
1997 + *
1998 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1999 + * FSER Modules API
2000 + * As per TNETD73xx specifications
2001 + *
2002 + * REVISION HISTORY:
2003 + * 27 Nov 02 - Sharath Kumar PSP TII
2004 + * 14 Feb 03 - Anant Gole PSP TII
2005 + *
2006 + * (C) Copyright 2002, Texas Instruments, Inc
2007 + *******************************************************************************/
2008 +
2009 +#include <linux/types.h>
2010 +#include <asm/ar7/tnetd73xx.h>
2011 +#include <asm/ar7/tnetd73xx_misc.h>
2012 +
2013 +/* TNETD73XX Revision */
2014 +u32 tnetd73xx_get_revision(void)
2015 +{
2016 + /* Read Chip revision register - This register is from GPIO module */
2017 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2018 +}
2019 +
2020 +/*****************************************************************************
2021 + * Reset Control Module
2022 + *****************************************************************************/
2023 +
2024 +
2025 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2026 +{
2027 + u32 reset_status;
2028 +
2029 + /* read current reset register */
2030 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2031 +
2032 + if (reset_ctrl == OUT_OF_RESET)
2033 + {
2034 + /* bring module out of reset */
2035 + reset_status |= (1 << reset_module);
2036 + }
2037 + else
2038 + {
2039 + /* put module in reset */
2040 + reset_status &= (~(1 << reset_module));
2041 + }
2042 +
2043 + /* write to the reset register */
2044 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2045 +}
2046 +
2047 +
2048 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2049 +{
2050 + u32 reset_status;
2051 +
2052 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2053 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2054 +}
2055 +
2056 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2057 +{
2058 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2059 +}
2060 +
2061 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2062 +
2063 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2064 +{
2065 + u32 sys_reset_status;
2066 +
2067 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2068 +
2069 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2070 +}
2071 +
2072 +
2073 +/*****************************************************************************
2074 + * Power Control Module
2075 + *****************************************************************************/
2076 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2077 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2078 +
2079 +
2080 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2081 +{
2082 + u32 power_status;
2083 +
2084 + /* read current power down control register */
2085 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2086 +
2087 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2088 + {
2089 + /* power down the module */
2090 + power_status |= (1 << power_module);
2091 + }
2092 + else
2093 + {
2094 + /* power on the module */
2095 + power_status &= (~(1 << power_module));
2096 + }
2097 +
2098 + /* write to the reset register */
2099 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2100 +}
2101 +
2102 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2103 +{
2104 + u32 power_status;
2105 +
2106 + /* read current power down control register */
2107 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2108 +
2109 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2110 +}
2111 +
2112 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2113 +{
2114 + u32 power_status;
2115 +
2116 + /* read current power down control register */
2117 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2118 +
2119 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2120 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2121 +
2122 + /* write to power down control register */
2123 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2124 +}
2125 +
2126 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2127 +{
2128 + u32 power_status;
2129 +
2130 + /* read current power down control register */
2131 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2132 +
2133 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2134 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2135 +
2136 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2137 +}
2138 +
2139 +
2140 +/*****************************************************************************
2141 + * Wakeup Control
2142 + *****************************************************************************/
2143 +
2144 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2145 +
2146 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2147 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2148 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2149 +{
2150 + u32 wakeup_status;
2151 +
2152 + /* read the wakeup control register */
2153 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2154 +
2155 + /* enable/disable */
2156 + if (wakeup_ctrl == WAKEUP_ENABLED)
2157 + {
2158 + /* enable wakeup */
2159 + wakeup_status |= wakeup_int;
2160 + }
2161 + else
2162 + {
2163 + /* disable wakeup */
2164 + wakeup_status &= (~wakeup_int);
2165 + }
2166 +
2167 + /* set polarity */
2168 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2169 + {
2170 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2171 + }
2172 + else
2173 + {
2174 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2175 + }
2176 +
2177 + /* write the wakeup control register */
2178 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2179 +}
2180 +
2181 +
2182 +/*****************************************************************************
2183 + * FSER Control
2184 + *****************************************************************************/
2185 +
2186 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2187 +{
2188 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2189 +}
2190 +
2191 +/*****************************************************************************
2192 + * Clock Control
2193 + *****************************************************************************/
2194 +
2195 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2196 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2197 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2198 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2199 +
2200 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2201 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2202 +
2203 +#define CLKC_PRE_DIVIDER 0x0000001F
2204 +#define CLKC_POST_DIVIDER 0x001F0000
2205 +
2206 +#define CLKC_PLL_STATUS 0x1
2207 +#define CLKC_PLL_FACTOR 0x0000F000
2208 +
2209 +#define BOOTCR_PLL_BYPASS (1 << 5)
2210 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2211 +
2212 +#define MIPS_PLL_SELECT 0x00030000
2213 +#define SYSTEM_PLL_SELECT 0x0000C000
2214 +#define USB_PLL_SELECT 0x000C0000
2215 +#define ADSLSS_PLL_SELECT 0x00C00000
2216 +
2217 +#define MIPS_AFECLKI_SELECT 0x00000000
2218 +#define MIPS_REFCLKI_SELECT 0x00010000
2219 +#define MIPS_XTAL3IN_SELECT 0x00020000
2220 +
2221 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2222 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2223 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2224 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2225 +
2226 +#define USB_SYSPLL_SELECT 0x00000000
2227 +#define USB_REFCLKI_SELECT 0x00040000
2228 +#define USB_XTAL3IN_SELECT 0x00080000
2229 +#define USB_MIPSPLL_SELECT 0x000C0000
2230 +
2231 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2232 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2233 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2234 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2235 +
2236 +#define SYS_MAX CLK_MHZ(150)
2237 +#define SYS_MIN CLK_MHZ(1)
2238 +
2239 +#define MIPS_SYNC_MAX SYS_MAX
2240 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2241 +#define MIPS_MIN CLK_MHZ(1)
2242 +
2243 +#define USB_MAX CLK_MHZ(100)
2244 +#define USB_MIN CLK_MHZ(1)
2245 +
2246 +#define ADSL_MAX CLK_MHZ(180)
2247 +#define ADSL_MIN CLK_MHZ(1)
2248 +
2249 +#define PLL_MUL_MAXFACTOR 15
2250 +#define MAX_DIV_VALUE 32
2251 +#define MIN_DIV_VALUE 1
2252 +
2253 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2254 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2255 +
2256 +#define DIVIDER_LOCK_TIME 10100
2257 +#define PLL_LOCK_TIME 10100 * 75
2258 +
2259 +
2260 +
2261 + /****************************************************************************
2262 + * DATA PURPOSE: PRIVATE Variables
2263 + **************************************************************************/
2264 + static u32 *clk_src[4];
2265 + static u32 mips_pll_out;
2266 + static u32 sys_pll_out;
2267 + static u32 afeclk_inp;
2268 + static u32 refclk_inp;
2269 + static u32 xtal_inp;
2270 + static u32 present_min;
2271 + static u32 present_max;
2272 +
2273 + /* Forward References */
2274 + static u32 find_gcd(u32 min, u32 max);
2275 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2276 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2277 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2278 + static void find_approx(u32 *,u32 *,u32);
2279 +
2280 + /****************************************************************************
2281 + * FUNCTION: tnetd73xx_clkc_init
2282 + ****************************************************************************
2283 + * Description: The routine initializes the internal variables depending on
2284 + * on the sources selected for different clocks.
2285 + ***************************************************************************/
2286 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2287 +{
2288 +
2289 + u32 choice;
2290 +
2291 + afeclk_inp = afeclk;
2292 + refclk_inp = refclk;
2293 + xtal_inp = xtal3in;
2294 +
2295 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2296 + switch(choice)
2297 + {
2298 + case MIPS_AFECLKI_SELECT:
2299 + clk_src[CLKC_MIPS] = &afeclk_inp;
2300 + break;
2301 +
2302 + case MIPS_REFCLKI_SELECT:
2303 + clk_src[CLKC_MIPS] = &refclk_inp;
2304 + break;
2305 +
2306 + case MIPS_XTAL3IN_SELECT:
2307 + clk_src[CLKC_MIPS] = &xtal_inp;
2308 + break;
2309 +
2310 + default :
2311 + clk_src[CLKC_MIPS] = 0;
2312 +
2313 + }
2314 +
2315 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2316 + switch(choice)
2317 + {
2318 + case SYSTEM_AFECLKI_SELECT:
2319 + clk_src[CLKC_SYS] = &afeclk_inp;
2320 + break;
2321 +
2322 + case SYSTEM_REFCLKI_SELECT:
2323 + clk_src[CLKC_SYS] = &refclk_inp;
2324 + break;
2325 +
2326 + case SYSTEM_XTAL3IN_SELECT:
2327 + clk_src[CLKC_SYS] = &xtal_inp;
2328 + break;
2329 +
2330 + case SYSTEM_MIPSPLL_SELECT:
2331 + clk_src[CLKC_SYS] = &mips_pll_out;
2332 + break;
2333 +
2334 + default :
2335 + clk_src[CLKC_SYS] = 0;
2336 +
2337 + }
2338 +
2339 +
2340 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2341 + switch(choice)
2342 + {
2343 + case ADSLSS_AFECLKI_SELECT:
2344 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2345 + break;
2346 +
2347 + case ADSLSS_REFCLKI_SELECT:
2348 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2349 + break;
2350 +
2351 + case ADSLSS_XTAL3IN_SELECT:
2352 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2353 + break;
2354 +
2355 + case ADSLSS_MIPSPLL_SELECT:
2356 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2357 + break;
2358 +
2359 + default :
2360 + clk_src[CLKC_ADSLSS] = 0;
2361 +
2362 + }
2363 +
2364 +
2365 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2366 + switch(choice)
2367 + {
2368 + case USB_SYSPLL_SELECT:
2369 + clk_src[CLKC_USB] = &sys_pll_out ;
2370 + break;
2371 +
2372 + case USB_REFCLKI_SELECT:
2373 + clk_src[CLKC_USB] = &refclk_inp;
2374 + break;
2375 +
2376 + case USB_XTAL3IN_SELECT:
2377 + clk_src[CLKC_USB] = &xtal_inp;
2378 + break;
2379 +
2380 + case USB_MIPSPLL_SELECT:
2381 + clk_src[CLKC_USB] = &mips_pll_out;
2382 + break;
2383 +
2384 + default :
2385 + clk_src[CLKC_USB] = 0;
2386 +
2387 + }
2388 +}
2389 +
2390 +
2391 +
2392 +/****************************************************************************
2393 + * FUNCTION: tnetd73xx_clkc_set_freq
2394 + ****************************************************************************
2395 + * Description: The above routine is called to set the output_frequency of the
2396 + * selected clock(using clk_id) to the required value given
2397 + * by the variable output_freq.
2398 + ***************************************************************************/
2399 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2400 +(
2401 + TNETD73XX_CLKC_ID_T clk_id,
2402 + u32 output_freq
2403 + )
2404 +{
2405 + u32 base_freq;
2406 + u32 multiplier;
2407 + u32 divider;
2408 + u32 min_prediv;
2409 + u32 max_prediv;
2410 + u32 prediv;
2411 + u32 postdiv;
2412 + u32 temp;
2413 +
2414 + /* check if PLLs are bypassed*/
2415 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2416 + {
2417 + return TNETD73XX_ERR_ERROR;
2418 + }
2419 +
2420 + /*check if the requested output_frequency is in valid range*/
2421 + switch( clk_id )
2422 + {
2423 + case CLKC_SYS:
2424 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2425 + {
2426 + return TNETD73XX_ERR_ERROR;
2427 + }
2428 + present_min = SYS_MIN;
2429 + present_max = SYS_MAX;
2430 + break;
2431 +
2432 + case CLKC_MIPS:
2433 + if((output_freq < MIPS_MIN) ||
2434 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2435 + {
2436 + return TNETD73XX_ERR_ERROR;
2437 + }
2438 + present_min = MIPS_MIN;
2439 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2440 + break;
2441 +
2442 + case CLKC_USB:
2443 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2444 + {
2445 + return TNETD73XX_ERR_ERROR;
2446 + }
2447 + present_min = USB_MIN;
2448 + present_max = USB_MAX;
2449 + break;
2450 +
2451 + case CLKC_ADSLSS:
2452 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2453 + {
2454 + return TNETD73XX_ERR_ERROR;
2455 + }
2456 + present_min = ADSL_MIN;
2457 + present_max = ADSL_MAX;
2458 + break;
2459 + }
2460 +
2461 +
2462 + base_freq = get_base_frequency(clk_id);
2463 +
2464 +
2465 + /* check for minimum base frequency value */
2466 + if( base_freq < MIN_PLL_INP_FREQ)
2467 + {
2468 + return TNETD73XX_ERR_ERROR;
2469 + }
2470 +
2471 + get_val(output_freq, base_freq, &multiplier, &divider);
2472 +
2473 + /* check multiplier range */
2474 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2475 + {
2476 + return TNETD73XX_ERR_ERROR;
2477 + }
2478 +
2479 + /* check divider value */
2480 + if( divider == 0 )
2481 + {
2482 + return TNETD73XX_ERR_ERROR;
2483 + }
2484 +
2485 + /*compute minimum and maximum predivider values */
2486 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2487 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2488 +
2489 + /*adjust the value of divider so that it not less than minimum predivider value*/
2490 + if (divider < min_prediv)
2491 + {
2492 + temp = CEIL(min_prediv, divider);
2493 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2494 + {
2495 + return TNETD73XX_ERR_ERROR ;
2496 + }
2497 + else
2498 + {
2499 + multiplier = temp * multiplier;
2500 + divider = min_prediv;
2501 + }
2502 +
2503 + }
2504 +
2505 + /* compute predivider and postdivider values */
2506 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2507 + postdiv = CEIL(divider,prediv);
2508 +
2509 + /*return fail if postdivider value falls out of range */
2510 + if(postdiv > MAX_DIV_VALUE)
2511 + {
2512 + return TNETD73XX_ERR_ERROR;
2513 + }
2514 +
2515 +
2516 + /*write predivider and postdivider values*/
2517 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2518 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2519 +
2520 + /*wait for divider output to stabilise*/
2521 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2522 +
2523 + /*write to PLL clock register*/
2524 +
2525 + if(clk_id == CLKC_SYS)
2526 + {
2527 + /* but before writing put DRAM to hold mode */
2528 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2529 + }
2530 + /*Bring PLL into div mode */
2531 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2532 +
2533 + /*compute the word to be written to PLLCR
2534 + *corresponding to multiplier value
2535 + */
2536 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2537 +
2538 + /* wait till PLL enters div mode */
2539 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2540 + /*nothing*/;
2541 +
2542 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2543 +
2544 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2545 + /*nothing*/;
2546 +
2547 +
2548 + /*wait for External pll to lock*/
2549 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2550 +
2551 + if(clk_id == CLKC_SYS)
2552 + {
2553 + /* Bring DRAM out of hold */
2554 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2555 + }
2556 +
2557 + return TNETD73XX_ERR_OK ;
2558 +}
2559 +
2560 +/****************************************************************************
2561 + * FUNCTION: tnetd73xx_clkc_get_freq
2562 + ****************************************************************************
2563 + * Description: The above routine is called to get the output_frequency of the
2564 + * selected clock( clk_id)
2565 + ***************************************************************************/
2566 +u32 tnetd73xx_clkc_get_freq
2567 +(
2568 + TNETD73XX_CLKC_ID_T clk_id
2569 + )
2570 +{
2571 +
2572 + u32 clk_ctrl_register;
2573 + u32 clk_pll_setting;
2574 + u32 clk_predivider;
2575 + u32 clk_postdivider;
2576 + u16 pll_factor;
2577 + u32 base_freq;
2578 + u32 divider;
2579 +
2580 + base_freq = get_base_frequency(clk_id);
2581 +
2582 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2583 +
2584 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2585 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2586 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2587 +
2588 + divider = clk_predivider * clk_postdivider;
2589 +
2590 +
2591 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2592 + {
2593 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2594 + }
2595 +
2596 +
2597 + else
2598 + {
2599 + /* return the current clock speed based upon the PLL setting */
2600 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2601 +
2602 + /* Get the PLL multiplication factor */
2603 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2604 +
2605 + /* Check if we're in divide mode or multiply mode */
2606 + if((clk_pll_setting & 0x1) == 0)
2607 + {
2608 + /* We're in divide mode */
2609 + if(pll_factor < 0x10)
2610 + return (CEIL(base_freq >> 1, divider));
2611 + else
2612 + return (CEIL(base_freq >> 2, divider));
2613 + }
2614 +
2615 + else /* We're in PLL mode */
2616 + {
2617 + /* See if PLLNDIV & PLLDIV are set */
2618 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2619 + {
2620 + if(clk_pll_setting & 0x1000)
2621 + {
2622 + /* clk = base_freq * k/2 */
2623 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2624 + }
2625 + else
2626 + {
2627 + /* clk = base_freq * (k-1) / 4)*/
2628 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2629 + }
2630 + }
2631 + else
2632 + {
2633 + if(pll_factor < 0x10)
2634 + {
2635 + /* clk = base_freq * k */
2636 + return(CEIL(base_freq * pll_factor, divider));
2637 + }
2638 +
2639 + else
2640 + {
2641 + /* clk = base_freq */
2642 + return(CEIL(base_freq, divider));
2643 + }
2644 + }
2645 + }
2646 + return(0); /* Should never reach here */
2647 +
2648 + }
2649 +
2650 +}
2651 +
2652 +
2653 +/* local helper functions */
2654 +
2655 +/****************************************************************************
2656 + * FUNCTION: get_base_frequency
2657 + ****************************************************************************
2658 + * Description: The above routine is called to get base frequency of the clocks.
2659 + ***************************************************************************/
2660 +
2661 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2662 +{
2663 + /* update the current MIPs PLL output value, if the required
2664 + * source is MIPS PLL
2665 + */
2666 + if ( clk_src[clk_id] == &mips_pll_out)
2667 + {
2668 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2669 + }
2670 +
2671 +
2672 + /* update the current System PLL output value, if the required
2673 + * source is system PLL
2674 + */
2675 + if ( clk_src[clk_id] == &sys_pll_out)
2676 + {
2677 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2678 + }
2679 +
2680 + return (*clk_src[clk_id]);
2681 +
2682 +}
2683 +
2684 +
2685 +
2686 +/****************************************************************************
2687 + * FUNCTION: find_gcd
2688 + ****************************************************************************
2689 + * Description: The above routine is called to find gcd of 2 numbers.
2690 + ***************************************************************************/
2691 +static u32 find_gcd
2692 +(
2693 + u32 min,
2694 + u32 max
2695 + )
2696 +{
2697 + if (max % min == 0)
2698 + {
2699 + return min;
2700 + }
2701 + else
2702 + {
2703 + return find_gcd(max % min, min);
2704 + }
2705 +}
2706 +
2707 +/****************************************************************************
2708 + * FUNCTION: compute_prediv
2709 + ****************************************************************************
2710 + * Description: The above routine is called to compute predivider value
2711 + ***************************************************************************/
2712 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2713 +{
2714 + u16 prediv;
2715 +
2716 + /* return the divider itself it it falls within the range of predivider*/
2717 + if (min <= divider && divider <= max)
2718 + {
2719 + return divider;
2720 + }
2721 +
2722 + /* find a value for prediv such that it is a factor of divider */
2723 + for (prediv = max; prediv >= min ; prediv--)
2724 + {
2725 + if ( (divider % prediv) == 0 )
2726 + {
2727 + return prediv;
2728 + }
2729 + }
2730 +
2731 + /* No such factor exists, return min as prediv */
2732 + return min;
2733 +}
2734 +
2735 +/****************************************************************************
2736 + * FUNCTION: get_val
2737 + ****************************************************************************
2738 + * Description: This routine is called to get values of divider and multiplier.
2739 + ***************************************************************************/
2740 +
2741 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2742 +{
2743 + u32 temp_mul;
2744 + u32 temp_div;
2745 + u32 gcd;
2746 + u32 min_freq;
2747 + u32 max_freq;
2748 +
2749 + /* find gcd of base_freq, output_freq */
2750 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2751 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2752 + gcd = find_gcd(min_freq , max_freq);
2753 +
2754 + if(gcd == 0)
2755 + return; /* ERROR */
2756 +
2757 + /* compute values of multiplier and divider */
2758 + temp_mul = output_freq / gcd;
2759 + temp_div = base_freq / gcd;
2760 +
2761 +
2762 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2763 + if( temp_mul > PLL_MUL_MAXFACTOR )
2764 + {
2765 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2766 + return;
2767 +
2768 + find_approx(&temp_mul,&temp_div,base_freq);
2769 + }
2770 +
2771 + *multiplier = temp_mul;
2772 + *divider = temp_div;
2773 +}
2774 +
2775 +/****************************************************************************
2776 + * FUNCTION: find_approx
2777 + ****************************************************************************
2778 + * Description: This function gets the approx value of num/denom.
2779 + ***************************************************************************/
2780 +
2781 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2782 +{
2783 + u32 num1;
2784 + u32 denom1;
2785 + u32 num2;
2786 + u32 denom2;
2787 + int32_t closest;
2788 + int32_t prev_closest;
2789 + u32 temp_num;
2790 + u32 temp_denom;
2791 + u32 normalize;
2792 + u32 gcd;
2793 + u32 output_freq;
2794 +
2795 + num1 = *num;
2796 + denom1 = *denom;
2797 +
2798 + prev_closest = 0x7fffffff; /* maximum possible value */
2799 + num2 = num1;
2800 + denom2 = denom1;
2801 +
2802 + /* start with max */
2803 + for(temp_num = 15; temp_num >=1; temp_num--)
2804 + {
2805 +
2806 + temp_denom = CEIL(temp_num * denom1, num1);
2807 + output_freq = (temp_num * base_freq) / temp_denom;
2808 +
2809 + if(temp_denom < 1)
2810 + {
2811 + break;
2812 + }
2813 + else
2814 + {
2815 + normalize = CEIL(num1,temp_num);
2816 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2817 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2818 + {
2819 + prev_closest = closest;
2820 + num2 = temp_num;
2821 + denom2 = temp_denom;
2822 + }
2823 +
2824 + }
2825 +
2826 + }
2827 +
2828 + gcd = find_gcd(num2,denom2);
2829 + num2 = num2 / gcd;
2830 + denom2 = denom2 /gcd;
2831 +
2832 + *num = num2;
2833 + *denom = denom2;
2834 +}
2835 +
2836 +
2837 +/*****************************************************************************
2838 + * GPIO Control
2839 + *****************************************************************************/
2840 +
2841 +/****************************************************************************
2842 + * FUNCTION: tnetd73xx_gpio_init
2843 + ***************************************************************************/
2844 +void tnetd73xx_gpio_init()
2845 +{
2846 + /* Bring module out of reset */
2847 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2848 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2849 +}
2850 +
2851 +/****************************************************************************
2852 + * FUNCTION: tnetd73xx_gpio_ctrl
2853 + ***************************************************************************/
2854 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2855 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2856 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2857 +{
2858 + u32 pin_status;
2859 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2860 + if (pin_mode == GPIO_PIN)
2861 + {
2862 + pin_status |= (1 << gpio_pin);
2863 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2864 +
2865 + /* Set pin direction */
2866 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2867 + if (pin_direction == GPIO_INPUT_PIN)
2868 + {
2869 + pin_status |= (1 << gpio_pin);
2870 + }
2871 + else /* GPIO_OUTPUT_PIN */
2872 + {
2873 + pin_status &= (~(1 << gpio_pin));
2874 + }
2875 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2876 + }
2877 + else /* FUNCTIONAL PIN */
2878 + {
2879 + pin_status &= (~(1 << gpio_pin));
2880 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2881 + }
2882 +
2883 +}
2884 +
2885 +/****************************************************************************
2886 + * FUNCTION: tnetd73xx_gpio_out
2887 + ***************************************************************************/
2888 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2889 +{
2890 + u32 pin_value;
2891 +
2892 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2893 + if (value == 1)
2894 + {
2895 + pin_value |= (1 << gpio_pin);
2896 + }
2897 + else
2898 + {
2899 + pin_value &= (~(1 << gpio_pin));
2900 + }
2901 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2902 +}
2903 +
2904 +/****************************************************************************
2905 + * FUNCTION: tnetd73xx_gpio_in
2906 + ***************************************************************************/
2907 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2908 +{
2909 + u32 pin_value;
2910 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2911 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2912 +}
2913 +
2914 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2915 --- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
2916 +++ linux.dev/arch/mips/config-shared.in 2005-11-10 01:12:43.950955750 +0100
2917 @@ -20,6 +20,16 @@
2918 mainmenu_option next_comment
2919 comment 'Machine selection'
2920 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2921 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2922 +if [ "$CONFIG_AR7" = "y" ]; then
2923 + choice 'Texas Instruments Reference Platform' \
2924 + "AR7DB CONFIG_AR7DB \
2925 + AR7RD CONFIG_AR7RD \
2926 + AR7WRD CONFIG_AR7WRD" AR7DB
2927 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
2928 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
2929 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2930 +fi
2931 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2932 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2933 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2934 @@ -239,6 +249,11 @@
2935 define_bool CONFIG_NONCOHERENT_IO y
2936 define_bool CONFIG_PC_KEYB y
2937 fi
2938 +if [ "$CONFIG_AR7" = "y" ]; then
2939 + define_bool CONFIG_IRQ_CPU y
2940 + define_bool CONFIG_NONCOHERENT_IO y
2941 + define_bool CONFIG_SWAP_IO_SPACE y
2942 +fi
2943 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2944 define_bool CONFIG_IRQ_CPU y
2945 define_bool CONFIG_NONCOHERENT_IO y
2946 @@ -736,6 +751,7 @@
2947 mainmenu_option next_comment
2948 comment 'General setup'
2949 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2950 + "$CONFIG_AR7" = "y" -o \
2951 "$CONFIG_CASIO_E55" = "y" -o \
2952 "$CONFIG_DDB5074" = "y" -o \
2953 "$CONFIG_DDB5476" = "y" -o \
2954 @@ -797,6 +813,7 @@
2955 bool 'Networking support' CONFIG_NET
2956
2957 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2958 + "$CONFIG_AR7" = "y" -o \
2959 "$CONFIG_CASIO_E55" = "y" -o \
2960 "$CONFIG_DECSTATION" = "y" -o \
2961 "$CONFIG_IBM_WORKPAD" = "y" -o \
2962 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
2963 --- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
2964 +++ linux.dev/arch/mips/kernel/head.S 2005-11-10 01:10:45.807572250 +0100
2965 @@ -75,11 +75,11 @@
2966 * size!
2967 */
2968 NESTED(except_vec4, 0, sp)
2969 - .set push
2970 - .set noreorder
2971 -1: j 1b /* Dummy, will be replaced */
2972 - nop
2973 - .set pop
2974 + .set mips2
2975 + lui k0, 0x9400
2976 + ori k0, 0x200
2977 + jr k0
2978 + nop
2979 END(except_vec4)
2980
2981 /*
2982 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
2983 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
2984 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-11-10 01:10:45.811572500 +0100
2985 @@ -40,6 +40,12 @@
2986 extern long __strnlen_user_nocheck_asm(const char *s);
2987 extern long __strnlen_user_asm(const char *s);
2988
2989 +#ifdef CONFIG_AR7
2990 +#include <asm/ar7/adam2_env.h>
2991 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
2992 +#endif
2993 +
2994 +
2995 EXPORT_SYMBOL(mips_machtype);
2996 #ifdef CONFIG_EISA
2997 EXPORT_SYMBOL(EISA_bus);
2998 @@ -103,3 +109,10 @@
2999 #endif
3000
3001 EXPORT_SYMBOL(get_wchan);
3002 +
3003 +#ifdef CONFIG_AR7
3004 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3005 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3006 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3007 +#endif
3008 +
3009 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3010 --- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
3011 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-10 01:14:16.376732000 +0100
3012 @@ -38,6 +38,7 @@
3013 #include <asm/io.h>
3014 #include <asm/ptrace.h>
3015 #include <asm/system.h>
3016 +#include <asm/addrspace.h>
3017
3018 struct cpuinfo_mips cpu_data[NR_CPUS];
3019 EXPORT_SYMBOL(cpu_data);
3020 @@ -88,7 +89,7 @@
3021 struct boot_mem_map boot_mem_map;
3022
3023 unsigned char aux_device_present;
3024 -extern char _ftext, _etext, _fdata, _edata, _end;
3025 +extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
3026
3027 static char command_line[CL_SIZE];
3028 char saved_command_line[CL_SIZE];
3029 @@ -116,6 +117,7 @@
3030
3031 static struct resource code_resource = { "Kernel code" };
3032 static struct resource data_resource = { "Kernel data" };
3033 +static struct resource bss_resource = { "Kernel bss" };
3034
3035 asmlinkage void __init
3036 init_arch(int argc, char **argv, char **envp, int *prom_vec)
3037 @@ -272,7 +274,7 @@
3038 for (i = 0; i < boot_mem_map.nr_map; i++) {
3039 unsigned long start, end;
3040
3041 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3042 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3043 continue;
3044
3045 start = PFN_UP(boot_mem_map.map[i].addr);
3046 @@ -320,7 +322,8 @@
3047 #endif
3048
3049 /* Initialize the boot-time allocator with low memory only. */
3050 - bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3051 + bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
3052 + PFN_UP(PHYS_OFFSET), max_low_pfn);
3053
3054 /*
3055 * Register fully available low RAM pages with the bootmem allocator.
3056 @@ -371,11 +374,12 @@
3057 continue;
3058
3059 /* Register lowmem ranges */
3060 - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
3061 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
3062 + size<<PAGE_SHIFT);
3063 }
3064
3065 /* Reserve the bootmap memory. */
3066 - reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3067 + reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
3068
3069 #ifdef CONFIG_BLK_DEV_INITRD
3070 /* Board specific code should have set up initrd_start and initrd_end */
3071 @@ -409,6 +413,8 @@
3072 code_resource.end = virt_to_bus(&_etext) - 1;
3073 data_resource.start = virt_to_bus(&_fdata);
3074 data_resource.end = virt_to_bus(&_edata) - 1;
3075 + bss_resource.start = virt_to_bus(&_fbss);
3076 + bss_resource.end = virt_to_bus(&_end) - 1;
3077
3078 /*
3079 * Request address space for all standard RAM.
3080 @@ -448,6 +454,7 @@
3081 */
3082 request_resource(res, &code_resource);
3083 request_resource(res, &data_resource);
3084 + request_resource(res, &bss_resource);
3085 }
3086 }
3087
3088 @@ -494,6 +501,7 @@
3089 void hp_setup(void);
3090 void au1x00_setup(void);
3091 void frame_info_init(void);
3092 + void ar7_setup(void);
3093
3094 frame_info_init();
3095 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3096 @@ -691,6 +699,11 @@
3097 pmc_yosemite_setup();
3098 break;
3099 #endif
3100 +#ifdef CONFIG_AR7
3101 + case MACH_GROUP_UNKNOWN:
3102 + ar7_setup();
3103 + break;
3104 +#endif
3105 default:
3106 panic("Unsupported architecture");
3107 }
3108 diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
3109 --- linux.old/arch/mips/kernel/time.c 2005-01-19 15:09:29.000000000 +0100
3110 +++ linux.dev/arch/mips/kernel/time.c 2005-11-10 01:12:43.950955750 +0100
3111 @@ -143,7 +143,6 @@
3112 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
3113 write_c0_count(expirelo - cycles_per_jiffy);
3114 write_c0_compare(expirelo);
3115 - write_c0_count(count);
3116 }
3117
3118 int (*mips_timer_state)(void);
3119 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3120 --- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
3121 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-10 01:13:28.301727500 +0100
3122 @@ -869,9 +869,24 @@
3123
3124 exception_handlers[n] = handler;
3125 if (n == 0 && cpu_has_divec) {
3126 + printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
3127 + __FUNCTION__, handler);
3128 + /* where does the 8 byte limit mentioned in head.S come from??? */
3129 + if (handler > 0x0fffffff) { /* maximum for single J instruction */
3130 + /* lui k0, 0x0000 */
3131 + *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
3132 + /* ori k0, 0x0000 */
3133 + *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
3134 + /* jr k0 */
3135 + *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
3136 + /* nop */
3137 + *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
3138 + flush_icache_range(KSEG0+0x200, KSEG0+0x210);
3139 + } else {
3140 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3141 (0x03ffffff & (handler >> 2));
3142 - flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3143 + flush_icache_range(KSEG0+0x200, KSEG0+0x204);
3144 + }
3145 }
3146 return (void *)old_handler;
3147 }
3148 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3149 --- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3150 +++ linux.dev/arch/mips/mm/init.c 2005-11-10 01:14:16.376732000 +0100
3151 @@ -235,10 +235,13 @@
3152 #endif
3153 }
3154
3155 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3156 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3157 +
3158 void __init paging_init(void)
3159 {
3160 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3161 - unsigned long max_dma, high, low;
3162 + unsigned long max_dma, high, low, start;
3163
3164 pagetable_init();
3165
3166 @@ -247,7 +250,8 @@
3167 #endif
3168
3169 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3170 - low = max_low_pfn;
3171 + start = START_PFN;
3172 + low = MAX_LOW_PFN - start;
3173 high = highend_pfn;
3174
3175 #ifdef CONFIG_ISA
3176 @@ -270,7 +274,8 @@
3177 zones_size[ZONE_HIGHMEM] = high - low;
3178 #endif
3179
3180 - free_area_init(zones_size);
3181 + free_area_init_node(0, NODE_DATA(0), 0, zones_size,
3182 + start << PAGE_SHIFT, 0);
3183 }
3184
3185 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3186 @@ -283,7 +288,7 @@
3187 for (i = 0; i < boot_mem_map.nr_map; i++) {
3188 unsigned long addr, end;
3189
3190 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3191 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3192 /* not usable memory */
3193 continue;
3194
3195 @@ -313,16 +318,17 @@
3196 max_mapnr = num_physpages = highend_pfn;
3197 num_mappedpages = max_low_pfn;
3198 #else
3199 - max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3200 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3201 #endif
3202 - high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3203 -
3204 - totalram_pages += free_all_bootmem();
3205 +
3206 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3207 +
3208 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3209 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3210
3211 reservedpages = ram = 0;
3212 - for (tmp = 0; tmp < max_low_pfn; tmp++)
3213 - if (page_is_ram(tmp)) {
3214 + for (tmp = 0; tmp < max_mapnr; tmp++)
3215 + if (page_is_ram(START_PFN + tmp)) {
3216 ram++;
3217 if (PageReserved(mem_map+tmp))
3218 reservedpages++;
3219 @@ -377,13 +383,13 @@
3220 #endif
3221
3222 extern char __init_begin, __init_end;
3223 -extern void prom_free_prom_memory(void) __init;
3224 +extern unsigned long prom_free_prom_memory(void) __init;
3225
3226 void free_initmem(void)
3227 {
3228 unsigned long addr;
3229
3230 - prom_free_prom_memory ();
3231 + totalram_pages += prom_free_prom_memory ();
3232
3233 addr = (unsigned long) &__init_begin;
3234 while (addr < (unsigned long) &__init_end) {
3235 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3236 --- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
3237 +++ linux.dev/drivers/char/Config.in 2005-11-10 01:10:45.843574500 +0100
3238 @@ -188,6 +188,14 @@
3239 tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3240 fi
3241
3242 +if [ "$CONFIG_AR7" = "y" ]; then
3243 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3244 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3245 +
3246 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3247 + tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3248 +fi
3249 +
3250 source drivers/i2c/Config.in
3251
3252 mainmenu_option next_comment
3253 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3254 --- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
3255 +++ linux.dev/drivers/char/Config.in.orig 2005-11-10 01:10:45.863575750 +0100
3256 @@ -0,0 +1,414 @@
3257 +#
3258 +# Character device configuration
3259 +#
3260 +mainmenu_option next_comment
3261 +comment 'Character devices'
3262 +
3263 +bool 'Virtual terminal' CONFIG_VT
3264 +if [ "$CONFIG_VT" = "y" ]; then
3265 + bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
3266 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3267 + bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3268 + fi
3269 +fi
3270 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3271 +if [ "$CONFIG_SERIAL" = "y" ]; then
3272 + bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
3273 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3274 + bool ' serial port on GSC support' CONFIG_SERIAL_GSC
3275 + fi
3276 + if [ "$CONFIG_IA64" = "y" ]; then
3277 + bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3278 + fi
3279 + if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3280 + tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3281 + tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
3282 + fi
3283 +fi
3284 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3285 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3286 + bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3287 + bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3288 + bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3289 + bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3290 + bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
3291 +fi
3292 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3293 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3294 + tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3295 + tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
3296 + tristate ' Cyclades async mux support' CONFIG_CYCLADES
3297 + if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3298 + bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3299 + fi
3300 + if [ "$CONFIG_X86_64" != "y" ]; then
3301 + tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3302 + if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3303 + tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
3304 + fi
3305 + fi
3306 + dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3307 + tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
3308 + tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3309 + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3310 + dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3311 + fi
3312 + tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
3313 + tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
3314 + tristate ' HDLC line discipline support' CONFIG_N_HDLC
3315 + tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
3316 + if [ "$CONFIG_X86_64" != "y" ]; then
3317 + tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
3318 + if [ "$CONFIG_SPECIALIX" != "n" ]; then
3319 + bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3320 + fi
3321 + tristate ' Specialix SX (and SI) card support' CONFIG_SX
3322 + tristate ' Specialix RIO system support' CONFIG_RIO
3323 + if [ "$CONFIG_RIO" != "n" ]; then
3324 + bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3325 + fi
3326 + fi
3327 + bool ' Stallion multiport serial support' CONFIG_STALDRV
3328 + if [ "$CONFIG_STALDRV" = "y" ]; then
3329 + tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3330 + tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3331 + fi
3332 + if [ "$CONFIG_PARISC" = "y" ]; then
3333 + if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3334 + bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3335 + fi
3336 + if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3337 + bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3338 + fi
3339 + fi
3340 + if [ "$CONFIG_MIPS" = "y" ]; then
3341 + bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3342 + dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3343 + bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3344 + dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3345 + if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3346 + bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3347 + if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3348 + bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3349 + fi
3350 + dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3351 + if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3352 + dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3353 + fi
3354 + if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3355 + "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3356 + define_bool CONFIG_AU1X00_USB_DEVICE y
3357 + fi
3358 + fi
3359 + bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
3360 + if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3361 + bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3362 + fi
3363 + if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3364 + bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3365 + if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3366 + bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3367 + if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3368 + define_bool CONFIG_SERIAL_CONSOLE y
3369 + fi
3370 + fi
3371 + fi
3372 + fi
3373 + if [ "$CONFIG_DECSTATION" = "y" ]; then
3374 + bool ' DECstation serial support' CONFIG_SERIAL_DEC
3375 + dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3376 + dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3377 + dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3378 + fi
3379 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3380 + bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
3381 + fi
3382 + if [ "$CONFIG_IA64" = "y" ]; then
3383 + bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
3384 + if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
3385 + bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
3386 + fi
3387 + if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
3388 + bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
3389 + fi
3390 + fi
3391 +fi
3392 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
3393 + tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
3394 +fi
3395 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3396 + bool 'DC21285 serial port support' CONFIG_SERIAL_21285
3397 + if [ "$CONFIG_SERIAL_21285" = "y" ]; then
3398 + if [ "$CONFIG_OBSOLETE" = "y" ]; then
3399 + bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
3400 + fi
3401 + bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
3402 + fi
3403 + if [ "$CONFIG_PARISC" = "y" ]; then
3404 + bool ' PDC software console support' CONFIG_PDC_CONSOLE
3405 + fi
3406 +fi
3407 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3408 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3409 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3410 + define_bool CONFIG_IT8172_CIR y
3411 + else
3412 + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
3413 + fi
3414 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3415 + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
3416 +fi
3417 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
3418 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3419 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3420 + define_bool CONFIG_IT8172_CIR y
3421 + fi
3422 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3423 +fi
3424 +if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
3425 + bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
3426 +fi
3427 +bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
3428 +if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
3429 + int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
3430 +fi
3431 +if [ "$CONFIG_PARPORT" != "n" ]; then
3432 + dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
3433 + if [ "$CONFIG_PRINTER" != "n" ]; then
3434 + bool ' Support for console on line printer' CONFIG_LP_CONSOLE
3435 + fi
3436 + dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
3437 + dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
3438 +fi
3439 +
3440 +if [ "$CONFIG_PPC64" = "y" ] ; then
3441 + bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
3442 +fi
3443 +if [ "$CONFIG_ALL_PPC" = "y" ]; then
3444 + tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3445 +fi
3446 +
3447 +if [ "$CONFIG_AR7" = "y" ]; then
3448 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3449 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3450 +
3451 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3452 +fi
3453 +
3454 +source drivers/i2c/Config.in
3455 +
3456 +mainmenu_option next_comment
3457 +comment 'Mice'
3458 +tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
3459 +if [ "$CONFIG_BUSMOUSE" != "n" ]; then
3460 + dep_tristate ' ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
3461 + dep_tristate ' Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
3462 + dep_tristate ' Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
3463 + if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
3464 + dep_tristate ' Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
3465 + fi
3466 +# if [ "$CONFIG_DECSTATION" = "y" ]; then
3467 +# dep_bool ' MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
3468 +# fi
3469 +fi
3470 +
3471 +tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
3472 +if [ "$CONFIG_MOUSE" != "n" ]; then
3473 + bool ' PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
3474 + tristate ' C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
3475 + tristate ' PC110 digitizer pad support' CONFIG_PC110_PAD
3476 + tristate ' MK712 touch screen support' CONFIG_MK712_MOUSE
3477 +fi
3478 +endmenu
3479 +
3480 +source drivers/char/joystick/Config.in
3481 +
3482 +tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
3483 +if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
3484 + bool ' Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
3485 + if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
3486 + comment ' Edit configuration parameters in ./include/linux/tpqic02.h!'
3487 + else
3488 + comment ' Setting runtime QIC-02 configuration is done with qic02conf'
3489 + comment ' from the tpqic02-support package. It is available at'
3490 + comment ' metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
3491 + fi
3492 +fi
3493 +
3494 +tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
3495 +dep_mbool ' Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
3496 +dep_tristate ' Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
3497 +dep_tristate ' IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
3498 +dep_tristate ' IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
3499 +
3500 +mainmenu_option next_comment
3501 +comment 'Watchdog Cards'
3502 +bool 'Watchdog Timer Support' CONFIG_WATCHDOG
3503 +if [ "$CONFIG_WATCHDOG" != "n" ]; then
3504 + bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
3505 + tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
3506 + tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
3507 + tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
3508 + tristate ' ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
3509 + tristate ' AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
3510 + tristate ' Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
3511 + if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3512 + tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG
3513 + if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3514 + tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
3515 + fi
3516 + fi
3517 + tristate ' Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
3518 + tristate ' IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
3519 + tristate ' ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
3520 + tristate ' Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
3521 + tristate ' Mixcom Watchdog' CONFIG_MIXCOMWD
3522 + tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
3523 + dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
3524 + tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
3525 + tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
3526 + tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
3527 + tristate ' WDT Watchdog timer' CONFIG_WDT
3528 + tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
3529 + if [ "$CONFIG_WDT" != "n" ]; then
3530 + bool ' WDT501 features' CONFIG_WDT_501
3531 + if [ "$CONFIG_WDT_501" = "y" ]; then
3532 + bool ' Fan Tachometer' CONFIG_WDT_501_FAN
3533 + fi
3534 + fi
3535 + tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
3536 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3537 + dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
3538 + fi
3539 + if [ "$CONFIG_8xx" = "y" ]; then
3540 + tristate ' MPC8xx Watchdog Timer' CONFIG_8xx_WDT
3541 + fi
3542 +fi
3543 +endmenu
3544 +
3545 +if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3546 + tristate 'NetWinder thermometer support' CONFIG_DS1620
3547 + tristate 'NetWinder Button' CONFIG_NWBUTTON
3548 + if [ "$CONFIG_NWBUTTON" != "n" ]; then
3549 + bool ' Reboot Using Button' CONFIG_NWBUTTON_REBOOT
3550 + fi
3551 + tristate 'NetWinder flash support' CONFIG_NWFLASH
3552 +fi
3553 +tristate 'NatSemi SCx200 Support' CONFIG_SCx200
3554 +dep_tristate ' NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
3555 +
3556 +if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
3557 + bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
3558 +fi
3559 +
3560 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
3561 + dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
3562 +fi
3563 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
3564 + dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
3565 +fi
3566 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
3567 + "$CONFIG_X86_64" = "y" ]; then
3568 + dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
3569 +fi
3570 +dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
3571 +tristate '/dev/nvram support' CONFIG_NVRAM
3572 +tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
3573 +if [ "$CONFIG_IA64" = "y" ]; then
3574 + bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
3575 +fi
3576 +if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
3577 + bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8
3578 +fi
3579 +if [ "$CONFIG_SGI_IP22" = "y" ]; then
3580 + tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
3581 +fi
3582 +if [ "$CONFIG_SGI_IP27" = "y" ]; then
3583 + tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
3584 +fi
3585 +if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
3586 + tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
3587 +fi
3588 +
3589 +tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
3590 +tristate 'Siemens R3964 line discipline' CONFIG_R3964
3591 +tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
3592 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
3593 + dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
3594 +fi
3595 +
3596 +mainmenu_option next_comment
3597 +comment 'Ftape, the floppy tape device driver'
3598 +tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
3599 +if [ "$CONFIG_FTAPE" != "n" ]; then
3600 + source drivers/char/ftape/Config.in
3601 +fi
3602 +
3603 +endmenu
3604 +
3605 +if [ "$CONFIG_GART_IOMMU" = "y" ]; then
3606 + bool '/dev/agpgart (AGP Support)' CONFIG_AGP
3607 + define_bool CONFIG_AGP_AMD_K8 y
3608 +else
3609 + tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
3610 +fi
3611 +if [ "$CONFIG_AGP" != "n" ]; then
3612 + bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
3613 + bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
3614 + bool ' VIA chipset support' CONFIG_AGP_VIA
3615 + bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
3616 + if [ "$CONFIG_GART_IOMMU" != "y" ]; then
3617 + bool ' AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
3618 + fi
3619 + bool ' Generic SiS support' CONFIG_AGP_SIS
3620 + bool ' ALI chipset support' CONFIG_AGP_ALI
3621 + bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
3622 + if [ "$CONFIG_X86" = "y" ]; then
3623 + bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
3624 + fi
3625 + if [ "$CONFIG_IA64" = "y" ]; then
3626 + bool ' Intel 460GX support' CONFIG_AGP_I460
3627 + bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
3628 + fi
3629 + bool ' ATI IGP chipset support' CONFIG_AGP_ATI
3630 +fi
3631 +
3632 +mainmenu_option next_comment
3633 +comment 'Direct Rendering Manager (XFree86 DRI support)'
3634 +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
3635 +if [ "$CONFIG_DRM" = "y" ]; then
3636 + bool ' Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
3637 + if [ "$CONFIG_DRM_OLD" = "y" ]; then
3638 + comment 'DRM 4.0 drivers'
3639 + source drivers/char/drm-4.0/Config.in
3640 + else
3641 + comment 'DRM 4.1 drivers'
3642 + define_bool CONFIG_DRM_NEW y
3643 + source drivers/char/drm/Config.in
3644 + fi
3645 +fi
3646 +
3647 +if [ "$CONFIG_X86" = "y" ]; then
3648 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3649 +fi
3650 +
3651 +endmenu
3652 +
3653 +if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
3654 + source drivers/char/pcmcia/Config.in
3655 +fi
3656 +if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3657 + tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
3658 + tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
3659 + #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
3660 +fi
3661 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3662 + tristate ' ITE GPIO' CONFIG_ITE_GPIO
3663 +fi
3664 +
3665 +if [ "$CONFIG_X86" = "y" ]; then
3666 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3667 + dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
3668 +fi
3669 +
3670 +endmenu
3671 diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
3672 --- linux.old/drivers/char/Makefile 2005-10-21 16:43:16.460960500 +0200
3673 +++ linux.dev/drivers/char/Makefile 2005-11-10 01:10:45.871576250 +0100
3674 @@ -240,6 +240,13 @@
3675 obj-y += joystick/js.o
3676 endif
3677
3678 +#
3679 +# Texas Intruments VLYNQ driver
3680 +#
3681 +
3682 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3683 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3684 +
3685 obj-$(CONFIG_FETCHOP) += fetchop.o
3686 obj-$(CONFIG_BUSMOUSE) += busmouse.o
3687 obj-$(CONFIG_DTLK) += dtlk.o
3688 @@ -340,6 +347,11 @@
3689 obj-y += ipmi/ipmi.o
3690 endif
3691
3692 +subdir-$(CONFIG_AR7_ADAM2) += ticfg
3693 +ifeq ($(CONFIG_AR7_ADAM2),y)
3694 + obj-y += ticfg/ticfg.o
3695 +endif
3696 +
3697 include $(TOPDIR)/Rules.make
3698
3699 fastdep:
3700 diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
3701 --- linux.old/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
3702 +++ linux.dev/drivers/char/Makefile.orig 2005-11-10 01:10:45.871576250 +0100
3703 @@ -0,0 +1,374 @@
3704 +#
3705 +# Makefile for the kernel character device drivers.
3706 +#
3707 +# Note! Dependencies are done automagically by 'make dep', which also
3708 +# removes any old dependencies. DON'T put your own dependencies here
3709 +# unless it's something special (ie not a .c file).
3710 +#
3711 +# Note 2! The CFLAGS definitions are now inherited from the
3712 +# parent makes..
3713 +#
3714 +
3715 +#
3716 +# This file contains the font map for the default (hardware) font
3717 +#
3718 +FONTMAPFILE = cp437.uni
3719 +
3720 +O_TARGET := char.o
3721 +
3722 +obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
3723 +
3724 +# All of the (potential) objects that export symbols.
3725 +# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
3726 +
3727 +export-objs := busmouse.o console.o keyboard.o sysrq.o \
3728 + misc.o pty.o random.o selection.o serial.o \
3729 + sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
3730 + au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
3731 + scx200.o fetchop.o
3732 +
3733 +mod-subdirs := joystick ftape drm drm-4.0 pcmcia
3734 +
3735 +list-multi :=
3736 +
3737 +KEYMAP =defkeymap.o
3738 +KEYBD =pc_keyb.o
3739 +CONSOLE =console.o
3740 +SERIAL =serial.o
3741 +
3742 +ifeq ($(ARCH),s390)
3743 + KEYMAP =
3744 + KEYBD =
3745 + CONSOLE =
3746 + SERIAL =
3747 +endif
3748 +
3749 +ifeq ($(ARCH),mips)
3750 + ifneq ($(CONFIG_PC_KEYB),y)
3751 + KEYBD =
3752 + endif
3753 + ifeq ($(CONFIG_VR41XX_KIU),y)
3754 + ifeq ($(CONFIG_IBM_WORKPAD),y)
3755 + KEYMAP = ibm_workpad_keymap.o
3756 + endif
3757 + ifeq ($(CONFIG_VICTOR_MPC30X),y)
3758 + KEYMAP = victor_mpc30x_keymap.o
3759 + endif
3760 + KEYBD = vr41xx_keyb.o
3761 + endif
3762 +endif
3763 +
3764 +ifeq ($(ARCH),s390x)
3765 + KEYMAP =
3766 + KEYBD =
3767 + CONSOLE =
3768 + SERIAL =
3769 +endif
3770 +
3771 +ifeq ($(ARCH),m68k)
3772 + ifdef CONFIG_AMIGA
3773 + KEYBD = amikeyb.o
3774 + else
3775 + ifndef CONFIG_MAC
3776 + KEYBD =
3777 + endif
3778 + endif
3779 + SERIAL =
3780 +endif
3781 +
3782 +ifeq ($(ARCH),parisc)
3783 + ifdef CONFIG_GSC_PS2
3784 + KEYBD = hp_psaux.o hp_keyb.o
3785 + else
3786 + KEYBD =
3787 + endif
3788 + ifdef CONFIG_SERIAL_MUX
3789 + CONSOLE += mux.o
3790 + endif
3791 + ifdef CONFIG_PDC_CONSOLE
3792 + CONSOLE += pdc_console.o
3793 + endif
3794 +endif
3795 +
3796 +ifdef CONFIG_Q40
3797 + KEYBD += q40_keyb.o
3798 + SERIAL = serial.o
3799 +endif
3800 +
3801 +ifdef CONFIG_APOLLO
3802 + KEYBD += dn_keyb.o
3803 +endif
3804 +
3805 +ifeq ($(ARCH),parisc)
3806 + ifdef CONFIG_GSC_PS2
3807 + KEYBD = hp_psaux.o hp_keyb.o
3808 + else
3809 + KEYBD =
3810 + endif
3811 + ifdef CONFIG_PDC_CONSOLE
3812 + CONSOLE += pdc_console.o
3813 + endif
3814 +endif
3815 +
3816 +ifeq ($(ARCH),arm)
3817 + ifneq ($(CONFIG_PC_KEYMAP),y)
3818 + KEYMAP =
3819 + endif
3820 + ifneq ($(CONFIG_PC_KEYB),y)
3821 + KEYBD =
3822 + endif
3823 +endif
3824 +
3825 +ifeq ($(ARCH),sh)
3826 + KEYMAP =
3827 + KEYBD =
3828 + CONSOLE =
3829 + ifeq ($(CONFIG_SH_HP600),y)
3830 + KEYMAP = defkeymap.o
3831 + KEYBD = scan_keyb.o hp600_keyb.o
3832 + CONSOLE = console.o
3833 + endif
3834 + ifeq ($(CONFIG_SH_DMIDA),y)
3835 + # DMIDA does not connect the HD64465 PS/2 keyboard port
3836 + # but we allow for USB keyboards to be plugged in.
3837 + KEYMAP = defkeymap.o
3838 + KEYBD = # hd64465_keyb.o pc_keyb.o
3839 + CONSOLE = console.o
3840 + endif
3841 + ifeq ($(CONFIG_SH_EC3104),y)
3842 + KEYMAP = defkeymap.o
3843 + KEYBD = ec3104_keyb.o
3844 + CONSOLE = console.o
3845 + endif
3846 + ifeq ($(CONFIG_SH_DREAMCAST),y)
3847 + KEYMAP = defkeymap.o
3848 + KEYBD =
3849 + CONSOLE = console.o
3850 + endif
3851 +endif
3852 +
3853 +ifeq ($(CONFIG_DECSTATION),y)
3854 + KEYMAP =
3855 + KEYBD =
3856 +endif
3857 +
3858 +ifeq ($(CONFIG_BAGET_MIPS),y)
3859 + KEYBD =
3860 + SERIAL = vac-serial.o
3861 +endif
3862 +
3863 +ifeq ($(CONFIG_NINO),y)
3864 + SERIAL =
3865 +endif
3866 +
3867 +ifneq ($(CONFIG_SUN_SERIAL),)
3868 + SERIAL =
3869 +endif
3870 +
3871 +ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
3872 + KEYBD = qtronix.o
3873 + KEYMAP = qtronixmap.o
3874 +endif
3875 +
3876 +ifeq ($(CONFIG_DUMMY_KEYB),y)
3877 + KEYBD = dummy_keyb.o
3878 +endif
3879 +
3880 +obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
3881 +obj-$(CONFIG_SERIAL) += $(SERIAL)
3882 +obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
3883 +obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
3884 +obj-$(CONFIG_SERIAL_21285) += serial_21285.o
3885 +obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
3886 +obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
3887 +obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
3888 +obj-$(CONFIG_SERIAL_DEC) += decserial.o
3889 +
3890 +ifndef CONFIG_SUN_KEYBOARD
3891 + obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
3892 +else
3893 + obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
3894 +endif
3895 +
3896 +obj-$(CONFIG_HIL) += hp_keyb.o
3897 +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
3898 +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
3899 +obj-$(CONFIG_ROCKETPORT) += rocket.o
3900 +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
3901 +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
3902 +obj-$(CONFIG_DIGI) += pcxx.o
3903 +obj-$(CONFIG_DIGIEPCA) += epca.o
3904 +obj-$(CONFIG_CYCLADES) += cyclades.o
3905 +obj-$(CONFIG_STALLION) += stallion.o
3906 +obj-$(CONFIG_ISTALLION) += istallion.o
3907 +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
3908 +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
3909 +obj-$(CONFIG_RISCOM8) += riscom8.o
3910 +obj-$(CONFIG_ISI) += isicom.o
3911 +obj-$(CONFIG_ESPSERIAL) += esp.o
3912 +obj-$(CONFIG_SYNCLINK) += synclink.o
3913 +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
3914 +obj-$(CONFIG_N_HDLC) += n_hdlc.o
3915 +obj-$(CONFIG_SPECIALIX) += specialix.o
3916 +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
3917 +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
3918 +obj-$(CONFIG_SX) += sx.o generic_serial.o
3919 +obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
3920 +obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
3921 +obj-$(CONFIG_SERIAL167) += serial167.o
3922 +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
3923 +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
3924 +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
3925 +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
3926 +obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
3927 +obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
3928 +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
3929 +obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
3930 +obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
3931 +obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
3932 +
3933 +subdir-$(CONFIG_RIO) += rio
3934 +subdir-$(CONFIG_INPUT) += joystick
3935 +
3936 +obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
3937 +obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
3938 +obj-$(CONFIG_PRINTER) += lp.o
3939 +obj-$(CONFIG_TIPAR) += tipar.o
3940 +obj-$(CONFIG_OBMOUSE) += obmouse.o
3941 +
3942 +ifeq ($(CONFIG_INPUT),y)
3943 +obj-y += joystick/js.o
3944 +endif
3945 +
3946 +#
3947 +# Texas Intruments VLYNQ driver
3948 +#
3949 +
3950 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3951 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3952 +
3953 +obj-$(CONFIG_FETCHOP) += fetchop.o
3954 +obj-$(CONFIG_BUSMOUSE) += busmouse.o
3955 +obj-$(CONFIG_DTLK) += dtlk.o
3956 +obj-$(CONFIG_R3964) += n_r3964.o
3957 +obj-$(CONFIG_APPLICOM) += applicom.o
3958 +obj-$(CONFIG_SONYPI) += sonypi.o
3959 +obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
3960 +obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
3961 +obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
3962 +obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
3963 +obj-$(CONFIG_ADBMOUSE) += adbmouse.o
3964 +obj-$(CONFIG_PC110_PAD) += pc110pad.o
3965 +obj-$(CONFIG_MK712_MOUSE) += mk712.o
3966 +obj-$(CONFIG_RTC) += rtc.o
3967 +obj-$(CONFIG_GEN_RTC) += genrtc.o
3968 +obj-$(CONFIG_EFI_RTC) += efirtc.o
3969 +obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
3970 +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
3971 +ifeq ($(CONFIG_PPC),)
3972 + obj-$(CONFIG_NVRAM) += nvram.o
3973 +endif
3974 +obj-$(CONFIG_TOSHIBA) += toshiba.o
3975 +obj-$(CONFIG_I8K) += i8k.o
3976 +obj-$(CONFIG_DS1286) += ds1286.o
3977 +obj-$(CONFIG_DS1620) += ds1620.o
3978 +obj-$(CONFIG_DS1742) += ds1742.o
3979 +obj-$(CONFIG_INTEL_RNG) += i810_rng.o
3980 +obj-$(CONFIG_AMD_RNG) += amd768_rng.o
3981 +obj-$(CONFIG_HW_RANDOM) += hw_random.o
3982 +obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
3983 +obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
3984 +
3985 +obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
3986 +obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o
3987 +obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o
3988 +obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o
3989 +obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o
3990 +obj-$(CONFIG_COBALT_LCD) += lcd.o
3991 +
3992 +obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
3993 +
3994 +subdir-$(CONFIG_FTAPE) += ftape
3995 +subdir-$(CONFIG_DRM_OLD) += drm-4.0
3996 +subdir-$(CONFIG_DRM_NEW) += drm
3997 +subdir-$(CONFIG_PCMCIA) += pcmcia
3998 +subdir-$(CONFIG_AGP) += agp
3999 +
4000 +ifeq ($(CONFIG_FTAPE),y)
4001 +obj-y += ftape/ftape.o
4002 +endif
4003 +
4004 +obj-$(CONFIG_H8) += h8.o
4005 +obj-$(CONFIG_PPDEV) += ppdev.o
4006 +obj-$(CONFIG_DZ) += dz.o
4007 +obj-$(CONFIG_NWBUTTON) += nwbutton.o
4008 +obj-$(CONFIG_NWFLASH) += nwflash.o
4009 +obj-$(CONFIG_SCx200) += scx200.o
4010 +obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
4011 +
4012 +# Only one watchdog can succeed. We probe the hardware watchdog
4013 +# drivers first, then the softdog driver. This means if your hardware
4014 +# watchdog dies or is 'borrowed' for some reason the software watchdog
4015 +# still gives you some cover.
4016 +
4017 +obj-$(CONFIG_PCWATCHDOG) += pcwd.o
4018 +obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4019 +obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4020 +obj-$(CONFIG_IB700_WDT) += ib700wdt.o
4021 +obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
4022 +obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
4023 +obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
4024 +obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
4025 +obj-$(CONFIG_WDT) += wdt.o
4026 +obj-$(CONFIG_WDTPCI) += wdt_pci.o
4027 +obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
4028 +obj-$(CONFIG_977_WATCHDOG) += wdt977.o
4029 +obj-$(CONFIG_I810_TCO) += i810-tco.o
4030 +obj-$(CONFIG_MACHZ_WDT) += machzwd.o
4031 +obj-$(CONFIG_SH_WDT) += shwdt.o
4032 +obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
4033 +obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
4034 +obj-$(CONFIG_ALIM1535_WDT) += alim1535d_wdt.o
4035 +obj-$(CONFIG_INDYDOG) += indydog.o
4036 +obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
4037 +obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
4038 +obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
4039 +obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
4040 +obj-$(CONFIG_INDYDOG) += indydog.o
4041 +obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
4042 +
4043 +subdir-$(CONFIG_MWAVE) += mwave
4044 +ifeq ($(CONFIG_MWAVE),y)
4045 + obj-y += mwave/mwave.o
4046 +endif
4047 +
4048 +subdir-$(CONFIG_IPMI_HANDLER) += ipmi
4049 +ifeq ($(CONFIG_IPMI_HANDLER),y)
4050 + obj-y += ipmi/ipmi.o
4051 +endif
4052 +
4053 +include $(TOPDIR)/Rules.make
4054 +
4055 +fastdep:
4056 +
4057 +conmakehash: conmakehash.c
4058 + $(HOSTCC) $(HOSTCFLAGS) -o conmakehash conmakehash.c
4059 +
4060 +consolemap_deftbl.c: $(FONTMAPFILE) conmakehash
4061 + ./conmakehash $(FONTMAPFILE) > consolemap_deftbl.c
4062 +
4063 +consolemap_deftbl.o: consolemap_deftbl.c $(TOPDIR)/include/linux/types.h
4064 +
4065 +.DELETE_ON_ERROR:
4066 +
4067 +defkeymap.c: defkeymap.map
4068 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4069 +
4070 +qtronixmap.c: qtronixmap.map
4071 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4072 +
4073 +ibm_workpad_keymap.c: ibm_workpad_keymap.map
4074 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4075 +
4076 +victor_mpc30x_keymap.c: victor_mpc30x_keymap.map
4077 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4078 diff -urN linux.old/drivers/char/avalanche_vlynq/Makefile linux.dev/drivers/char/avalanche_vlynq/Makefile
4079 --- linux.old/drivers/char/avalanche_vlynq/Makefile 1970-01-01 01:00:00.000000000 +0100
4080 +++ linux.dev/drivers/char/avalanche_vlynq/Makefile 2005-11-10 01:10:45.871576250 +0100
4081 @@ -0,0 +1,16 @@
4082 +#
4083 +# Makefile for the linux kernel.
4084 +#
4085 +# Note! Dependencies are done automagically by 'make dep', which also
4086 +# removes any old dependencies. DON'T put your own dependencies here
4087 +# unless it's something special (ie not a .c file).
4088 +#
4089 +# Note 2! The CFLAGS definitions are now in the main makefile...
4090 +
4091 +O_TARGET := avalanche_vlynq.o
4092 +
4093 +export-objs := vlynq_board.o
4094 +
4095 +obj-y += vlynq_drv.o vlynq_hal.o vlynq_board.o
4096 +
4097 +include $(TOPDIR)/Rules.make
4098 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_board.c linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c
4099 --- linux.old/drivers/char/avalanche_vlynq/vlynq_board.c 1970-01-01 01:00:00.000000000 +0100
4100 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c 2005-11-10 01:10:45.871576250 +0100
4101 @@ -0,0 +1,184 @@
4102 +/*
4103 + * Jeff Harrell, jharrell@ti.com
4104 + * Copyright (C) 2001 Texas Instruments, Inc. All rights reserved.
4105 + *
4106 + * This program is free software; you can distribute it and/or modify it
4107 + * under the terms of the GNU General Public License (Version 2) as
4108 + * published by the Free Software Foundation.
4109 + *
4110 + * This program is distributed in the hope it will be useful, but WITHOUT
4111 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4112 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4113 + * for more details.
4114 + *
4115 + * You should have received a copy of the GNU General Public License along
4116 + * with this program; if not, write to the Free Software Foundation, Inc.,
4117 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4118 + *
4119 + * Texas Instruments Sangam specific setup.
4120 + */
4121 +#include <linux/config.h>
4122 +#include <linux/module.h>
4123 +#include <asm/ar7/sangam.h>
4124 +#include <asm/ar7/avalanche_misc.h>
4125 +#include <asm/ar7/vlynq.h>
4126 +
4127 +#define SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR 30 /* MSB - 1 bit */
4128 +#define SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR 31 /* MSB bit */
4129 +#define SYS_VLYNQ_OPTIONS 0x7F; /* all options*/
4130 +
4131 +/* These defines are board specific */
4132 +
4133 +
4134 +#define VLYNQ0_REMOTE_WINDOW1_OFFSET (0x0C000000)
4135 +#define VLYNQ0_REMOTE_WINDOW1_SIZE (0x500)
4136 +
4137 +
4138 +#define VLYNQ1_REMOTE_WINDOW1_OFFSET (0x0C000000)
4139 +#define VLYNQ1_REMOTE_WINDOW1_SIZE (0x500)
4140 +
4141 +
4142 +extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
4143 +int vlynq_init_status[2] = {0, 0};
4144 +EXPORT_SYMBOL(vlynq_init_status);
4145 +static int reset_hack = 1;
4146 +
4147 +void vlynq_ar7wrd_dev_init()
4148 +{
4149 + *(unsigned long*) AVALANCHE_GPIO_ENBL |= (1<<18);
4150 + vlynq_delay(20000);
4151 + *(unsigned long*) AVALANCHE_GPIO_DIR &= ~(1<<18);
4152 + vlynq_delay(20000);
4153 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT&= ~(1<<18);
4154 + vlynq_delay(50000);
4155 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT|= (1<<18);
4156 + vlynq_delay(50000);
4157 +
4158 + /* Initialize the MIPS host vlynq driver for a given vlynq interface */
4159 + vlynqDevice0.dev_idx = 0; /* first vlynq module - this parameter is for reference only */
4160 + vlynqDevice0.module_base = AVALANCHE_LOW_VLYNQ_CONTROL_BASE; /* vlynq0 module base address */
4161 +
4162 +#if defined(CONFIG_VLYNQ_CLK_LOCAL)
4163 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_LOCAL;
4164 +#else
4165 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_REMOTE;
4166 +#endif
4167 + vlynqDevice0.clk_div = 0x01; /* board/hardware specific */
4168 + vlynqDevice0.state = VLYNQ_DRV_STATE_UNINIT; /* uninitialized module */
4169 +
4170 + /* Populate vlynqDevice0.local_mem & Vlynq0.remote_mem based on system configuration */
4171 + /*Local memory configuration */
4172 +
4173 + /* Demiurg : not good !*/
4174 +#if 0
4175 + vlynqDevice0.local_mem.Txmap= AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE & ~(0xc0000000) ; /* physical address */
4176 + vlynqDevice0.remote_mem.RxOffset[0]= VLYNQ0_REMOTE_WINDOW1_OFFSET; /* This is specific to the board on the other end */
4177 + vlynqDevice0.remote_mem.RxSize[0]=VLYNQ0_REMOTE_WINDOW1_SIZE;
4178 +#endif
4179 +
4180 + /* Demiurg : This is how it should be ! */
4181 + vlynqDevice0.local_mem.Txmap = PHYSADDR(AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE);
4182 +#define VLYNQ_ACX111_MEM_OFFSET 0xC0000000 /* Physical address of ACX111 memory */
4183 +#define VLYNQ_ACX111_MEM_SIZE 0x00040000 /* Total size of the ACX111 memory */
4184 +#define VLYNQ_ACX111_REG_OFFSET 0xF0000000 /* PHYS_ADDR of ACX111 control registers */
4185 +#define VLYNQ_ACX111_REG_SIZE 0x00022000 /* Size of ACX111 registers area, MAC+PHY */
4186 +#define ACX111_VL1_REMOTE_SIZE 0x1000000
4187 + vlynqDevice0.remote_mem.RxOffset[0] = VLYNQ_ACX111_MEM_OFFSET;
4188 + vlynqDevice0.remote_mem.RxSize[0] = VLYNQ_ACX111_MEM_SIZE ;
4189 + vlynqDevice0.remote_mem.RxOffset[1] = VLYNQ_ACX111_REG_OFFSET;
4190 + vlynqDevice0.remote_mem.RxSize[1] = VLYNQ_ACX111_REG_SIZE ;
4191 + vlynqDevice0.remote_mem.Txmap = 0;
4192 + vlynqDevice0.local_mem.RxOffset[0] = AVALANCHE_SDRAM_BASE;
4193 + vlynqDevice0.local_mem.RxSize[0] = ACX111_VL1_REMOTE_SIZE;
4194 +
4195 +
4196 + /* Local interrupt configuration */
4197 + vlynqDevice0.local_irq.intLocal = VLYNQ_INT_LOCAL; /* Host handles vlynq interrupts*/
4198 + vlynqDevice0.local_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* vlynq root isr used */
4199 + vlynqDevice0.local_irq.map_vector = SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR;
4200 + vlynqDevice0.local_irq.intr_ptr = 0; /* Since remote interrupts part of vlynq root isr this is unused */
4201 +
4202 + /* Remote interrupt configuration */
4203 + vlynqDevice0.remote_irq.intLocal = VLYNQ_INT_REMOTE; /* MIPS handles interrupts */
4204 + vlynqDevice0.remote_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* Not significant since MIPS handles interrupts */
4205 + vlynqDevice0.remote_irq.map_vector = SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR;
4206 + vlynqDevice0. remote_irq.intr_ptr = AVALANCHE_INTC_BASE; /* Not significant since MIPS handles interrupts */
4207 +
4208 + if(reset_hack != 1)
4209 + printk("About to re-init the VLYNQ.\n");
4210 +
4211 + if(vlynq_init(&vlynqDevice0,VLYNQ_INIT_PERFORM_ALL)== 0)
4212 + {
4213 + /* Suraj added the following to keep the 1130 going. */
4214 + vlynq_interrupt_vector_set(&vlynqDevice0, 0 /* intr vector line running into 1130 vlynq */,
4215 + 0 /* intr mapped onto the interrupt register on remote vlynq and this vlynq */,
4216 + VLYNQ_REMOTE_DVC, 0 /* polarity active high */, 0 /* interrupt Level triggered */);
4217 +
4218 + /* System wide interrupt is 80 for 1130, please note. */
4219 + vlynq_init_status[0] = 1;
4220 + reset_hack = 2;
4221 + }
4222 + else
4223 + {
4224 + if(reset_hack == 1)
4225 + printk("VLYNQ INIT FAILED: Please try cold reboot. \n");
4226 + else
4227 + printk("Failed to initialize the VLYNQ interface at insmod.\n");
4228 +
4229 + }
4230 +}
4231 +
4232 +void vlynq_dev_init(void)
4233 +{
4234 + volatile unsigned int *reset_base = (unsigned int *) AVALANCHE_RESET_CONTROL_BASE;
4235 +
4236 + *reset_base &= ~((1 << AVALANCHE_LOW_VLYNQ_RESET_BIT)); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT)); */
4237 +
4238 + vlynq_delay(20000);
4239 +
4240 + /* Bring vlynq out of reset if not already done */
4241 + *reset_base |= (1 << AVALANCHE_LOW_VLYNQ_RESET_BIT); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT); */
4242 + vlynq_delay(20000); /* Allowing sufficient time to VLYNQ to settle down.*/
4243 +
4244 + vlynq_ar7wrd_dev_init( );
4245 +
4246 +}
4247 +
4248 +/* This function is board specific and should be ported for each board. */
4249 +void remote_vlynq_dev_reset_ctrl(unsigned int module_reset_bit,
4250 + AVALANCHE_RESET_CTRL_T reset_ctrl)
4251 +{
4252 + if(module_reset_bit >= 32)
4253 + return;
4254 +
4255 + switch(module_reset_bit)
4256 + {
4257 + case 0:
4258 + if(OUT_OF_RESET == reset_ctrl)
4259 + {
4260 + if(reset_hack) return;
4261 +
4262 + vlynq_delay(20000);
4263 + printk("Un-resetting the remote device.\n");
4264 + vlynq_dev_init();
4265 + printk("Re-initialized the VLYNQ.\n");
4266 + reset_hack = 2;
4267 + }
4268 + else if(IN_RESET == reset_ctrl)
4269 + {
4270 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT &= ~(1<<18);
4271 +
4272 + vlynq_delay(20000);
4273 + printk("Resetting the remote device.\n");
4274 + reset_hack = 0;
4275 + }
4276 + else
4277 + ;
4278 + break;
4279 +
4280 + default:
4281 + break;
4282 +
4283 + }
4284 +}
4285 +
4286 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c
4287 --- linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c 1970-01-01 01:00:00.000000000 +0100
4288 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c 2005-11-10 01:10:45.891577500 +0100
4289 @@ -0,0 +1,243 @@
4290 +/******************************************************************************
4291 + * FILE PURPOSE: Vlynq Linux Device Driver Source
4292 + ******************************************************************************
4293 + * FILE NAME: vlynq_drv.c
4294 + *
4295 + * DESCRIPTION: Vlynq Linux Device Driver Source
4296 + *
4297 + * REVISION HISTORY:
4298 + *
4299 + * Date Description Author
4300 + *-----------------------------------------------------------------------------
4301 + * 17 July 2003 Initial Creation Anant Gole
4302 + * 17 Dec 2003 Updates Sharath Kumar
4303 + *
4304 + * (C) Copyright 2003, Texas Instruments, Inc
4305 + *******************************************************************************/
4306 +
4307 +#include <linux/config.h>
4308 +#include <linux/init.h>
4309 +#include <linux/module.h>
4310 +#include <linux/sched.h>
4311 +#include <linux/miscdevice.h>
4312 +#include <linux/smp_lock.h>
4313 +#include <linux/delay.h>
4314 +#include <linux/proc_fs.h>
4315 +#include <linux/capability.h>
4316 +#include <asm/ar7/avalanche_intc.h>
4317 +#include <asm/ar7/sangam.h>
4318 +#include <asm/ar7/vlynq.h>
4319 +
4320 +
4321 +#define TI_VLYNQ_VERSION "0.2"
4322 +
4323 +/* debug on ? */
4324 +#define VLYNQ_DEBUG
4325 +
4326 +/* Macro for debug and error printf's */
4327 +#ifdef VLYNQ_DEBUG
4328 +#define DBGPRINT printk
4329 +#else
4330 +#define DBGPRINT(x)
4331 +#endif
4332 +
4333 +#define ERRPRINT printk
4334 +
4335 +/* Define the max vlynq ports this driver will support.
4336 + Device name strings are statically added here */
4337 +#define MAX_VLYNQ_PORTS 2
4338 +
4339 +
4340 +/* Type define for VLYNQ private structure */
4341 +typedef struct vlynqPriv{
4342 + int irq;
4343 + VLYNQ_DEV *vlynqDevice;
4344 +}VLYNQ_PRIV;
4345 +
4346 +extern int vlynq_init_status[2];
4347 +
4348 +/* Extern Global variable for vlynq devices used in initialization of the vlynq device
4349 + * These variables need to be populated/initialized by the system as part of initialization
4350 + * process. The vlynq enumerator can run at initialization and populate these globals
4351 + */
4352 +
4353 +VLYNQ_DEV vlynqDevice0;
4354 +VLYNQ_DEV vlynqDevice1;
4355 +
4356 +/* Defining dummy macro AVALANCHE_HIGH_VLYNQ_INT to take
4357 + * care of compilation in case of single vlynq device
4358 + */
4359 +
4360 +#ifndef AVALANCHE_HIGH_VLYNQ_INT
4361 +#define AVALANCHE_HIGH_VLYNQ_INT 0
4362 +#endif
4363 +
4364 +
4365 +
4366 +/* vlynq private object */
4367 +VLYNQ_PRIV vlynq_priv[CONFIG_AR7_VLYNQ_PORTS] = {
4368 + { LNXINTNUM(AVALANCHE_LOW_VLYNQ_INT),&vlynqDevice0},
4369 + { LNXINTNUM(AVALANCHE_HIGH_VLYNQ_INT),&vlynqDevice1},
4370 +};
4371 +
4372 +extern void vlynq_dev_init(void);
4373 +
4374 +
4375 +/* =================================== all the operations */
4376 +
4377 +static int
4378 +vlynq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4379 +{
4380 + return 0;
4381 +}
4382 +
4383 +static struct file_operations vlynq_fops = {
4384 + owner: THIS_MODULE,
4385 + ioctl: vlynq_ioctl,
4386 +};
4387 +
4388 +/* Vlynq device object */
4389 +static struct miscdevice vlynq_dev [MAX_VLYNQ_PORTS] = {
4390 + { MISC_DYNAMIC_MINOR , "vlynq0", &vlynq_fops },
4391 + { MISC_DYNAMIC_MINOR , "vlynq1", &vlynq_fops },
4392 +};
4393 +
4394 +
4395 +/* Proc read function */
4396 +static int
4397 +vlynq_read_link_proc(char *buf, char **start, off_t offset, int count, int *eof, void *unused)
4398 +{
4399 + int instance;
4400 + int len = 0;
4401 +
4402 + len += sprintf(buf +len,"VLYNQ Devices : %d\n",CONFIG_AR7_VLYNQ_PORTS);
4403 +
4404 + for(instance =0;instance < CONFIG_AR7_VLYNQ_PORTS;instance++)
4405 + {
4406 + int link_state;
4407 + char *link_msg[] = {" DOWN "," UP "};
4408 +
4409 + if(vlynq_init_status[instance] == 0)
4410 + link_state = 0;
4411 +
4412 + else if (vlynq_link_check(vlynq_priv[instance].vlynqDevice))
4413 + link_state = 1;
4414 +
4415 + else
4416 + link_state = 0;
4417 +
4418 + len += sprintf(buf + len, "VLYNQ %d: Link state: %s\n",instance,link_msg[link_state]);
4419 +
4420 + }
4421 + /* Print info about vlynq device 1 */
4422 +
4423 + return len;
4424 +}
4425 +
4426 +
4427 +/* Proc function to display driver version */
4428 +static int
4429 +vlynq_read_ver_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
4430 +{
4431 + int instance;
4432 + int len=0;
4433 +
4434 + len += sprintf(buf +len,"\nTI Linux VLYNQ Driver Version %s\n",TI_VLYNQ_VERSION);
4435 + return len;
4436 +}
4437 +
4438 +
4439 +
4440 +
4441 +/* Wrapper for vlynq ISR */
4442 +static void lnx_vlynq_root_isr(int irq, void * arg, struct pt_regs *regs)
4443 +{
4444 + vlynq_root_isr(arg);
4445 +}
4446 +
4447 +/* =================================== init and cleanup */
4448 +
4449 +int vlynq_init_module(void)
4450 +{
4451 + int ret;
4452 + int unit = 0;
4453 + int instance_count = CONFIG_AR7_VLYNQ_PORTS;
4454 + volatile int *ptr;
4455 +
4456 + vlynq_dev_init();
4457 +
4458 + DBGPRINT("Vlynq CONFIG_AR7_VLYNQ_PORTS=%d\n", CONFIG_AR7_VLYNQ_PORTS);
4459 + /* If num of configured vlynq ports > supported by driver return error */
4460 + if (instance_count > MAX_VLYNQ_PORTS)
4461 + {
4462 + ERRPRINT("ERROR: vlynq_init_module(): Max %d supported\n", MAX_VLYNQ_PORTS);
4463 + return (-1);
4464 + }
4465 +
4466 + /* register the misc device */
4467 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4468 + {
4469 + ret = misc_register(&vlynq_dev[unit]);
4470 +
4471 + if(ret < 0)
4472 + {
4473 + ERRPRINT("ERROR:Could not register vlynq device:%d\n",unit);
4474 + continue;
4475 + }
4476 + else
4477 + DBGPRINT("Vlynq Device %s registered with minor no %d as misc device. Result=%d\n",
4478 + vlynq_dev[unit].name, vlynq_dev[unit].minor, ret);
4479 +#if 0
4480 +
4481 + DBGPRINT("Calling vlynq init\n");
4482 +
4483 + /* Read the global variable for VLYNQ device structure and initialize vlynq driver */
4484 + ret = vlynq_init(vlynq_priv[unit].vlynqDevice,VLYNQ_INIT_PERFORM_ALL );
4485 +#endif
4486 +
4487 + if(vlynq_init_status[unit] == 0)
4488 + {
4489 + printk("VLYNQ %d : init failed\n",unit);
4490 + continue;
4491 + }
4492 +
4493 + /* Check link before proceeding */
4494 + if (!vlynq_link_check(vlynq_priv[unit].vlynqDevice))
4495 + {
4496 + DBGPRINT("\nError: Vlynq link not available.trying once before Exiting");
4497 + }
4498 + else
4499 + {
4500 + DBGPRINT("Vlynq instance:%d Link UP\n",unit);
4501 +
4502 + /* Install the vlynq local root ISR */
4503 + request_irq(vlynq_priv[unit].irq,lnx_vlynq_root_isr,0,vlynq_dev[unit].name,vlynq_priv[unit].vlynqDevice);
4504 + }
4505 + }
4506 +
4507 + proc_mkdir("avalanche", NULL);
4508 + /* Creating proc entry for the devices */
4509 + create_proc_read_entry("avalanche/vlynq_link", 0, NULL, vlynq_read_link_proc, NULL);
4510 + create_proc_read_entry("avalanche/vlynq_ver", 0, NULL, vlynq_read_ver_proc, NULL);
4511 +
4512 + return 0;
4513 +}
4514 +
4515 +void vlynq_cleanup_module(void)
4516 +{
4517 + int unit = 0;
4518 +
4519 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4520 + {
4521 + DBGPRINT("vlynq_cleanup_module(): Unregistring misc device %s\n",vlynq_dev[unit].name);
4522 + misc_deregister(&vlynq_dev[unit]);
4523 + }
4524 +
4525 + remove_proc_entry("avalanche/vlynq_link", NULL);
4526 + remove_proc_entry("avalanche/vlynq_ver", NULL);
4527 +}
4528 +
4529 +
4530 +module_init(vlynq_init_module);
4531 +module_exit(vlynq_cleanup_module);
4532 +
4533 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c
4534 --- linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c 1970-01-01 01:00:00.000000000 +0100
4535 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c 2005-11-10 01:10:45.975582750 +0100
4536 @@ -0,0 +1,1214 @@
4537 +/***************************************************************************
4538 +**+----------------------------------------------------------------------+**
4539 +**| **** |**
4540 +**| **** |**
4541 +**| ******o*** |**
4542 +**| ********_///_**** |**
4543 +**| ***** /_//_/ **** |**
4544 +**| ** ** (__/ **** |**
4545 +**| ********* |**
4546 +**| **** |**
4547 +**| *** |**
4548 +**| |**
4549 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
4550 +**| ALL RIGHTS RESERVED |**
4551 +**| |**
4552 +**| Permission is hereby granted to licensees of Texas Instruments |**
4553 +**| Incorporated (TI) products to use this computer program for the sole |**
4554 +**| purpose of implementing a licensee product based on TI products. |**
4555 +**| No other rights to reproduce, use, or disseminate this computer |**
4556 +**| program, whether in part or in whole, are granted. |**
4557 +**| |**
4558 +**| TI makes no representation or warranties with respect to the |**
4559 +**| performance of this computer program, and specifically disclaims |**
4560 +**| any responsibility for any damages, special or consequential, |**
4561 +**| connected with the use of this program. |**
4562 +**| |**
4563 +**+----------------------------------------------------------------------+**
4564 +***************************************************************************/
4565 +
4566 +/***************************************************************************
4567 + * ------------------------------------------------------------------------------
4568 + * Module : vlynq_hal.c
4569 + * Description : This file implements VLYNQ HAL API.
4570 + * ------------------------------------------------------------------------------
4571 + ***************************************************************************/
4572 +
4573 +#include <linux/stddef.h>
4574 +#include <linux/types.h>
4575 +#include <asm/ar7/vlynq.h>
4576 +
4577 +/**** Local Function prototypes *******/
4578 +static int vlynqInterruptInit(VLYNQ_DEV *pdev);
4579 +static void vlynq_configClock(VLYNQ_DEV *pdev);
4580 +
4581 +/*** Second argument must be explicitly type casted to
4582 + * (VLYNQ_DEV*) inside the following functions */
4583 +static void vlynq_local_module_isr(void *arg1, void *arg2, void *arg3);
4584 +static void vlynq_remote_module_isr(void *arg1, void *arg2, void *arg3);
4585 +
4586 +
4587 +volatile int vlynq_delay_value = 0;
4588 +
4589 +/* Code adopted from original vlynq driver */
4590 +void vlynq_delay(unsigned int clktime)
4591 +{
4592 + int i = 0;
4593 + volatile int *ptr = &vlynq_delay_value;
4594 + *ptr = 0;
4595 +
4596 + /* We are assuming that the each cycle takes about
4597 + * 23 assembly instructions. */
4598 + for(i = 0; i < (clktime + 23)/23; i++)
4599 + {
4600 + *ptr = *ptr + 1;
4601 + }
4602 +}
4603 +
4604 +
4605 +/* ----------------------------------------------------------------------------
4606 + * Function : vlynq_configClock()
4607 + * Description: Configures clock settings based on input parameters
4608 + * Adapted from original vlyna driver from Cable
4609 + */
4610 +static void vlynq_configClock(VLYNQ_DEV * pdev)
4611 +{
4612 + unsigned int tmp;
4613 +
4614 + switch( pdev->clk_source)
4615 + {
4616 + case VLYNQ_CLK_SOURCE_LOCAL: /* we output the clock, clk_div in range [1..8]. */
4617 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
4618 + VLYNQ_CTRL_REG = tmp;
4619 + VLYNQ_R_CTRL_REG = 0ul;
4620 + break;
4621 + case VLYNQ_CLK_SOURCE_REMOTE: /* we need to set the clock pin as input */
4622 + VLYNQ_CTRL_REG = 0ul;
4623 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
4624 + VLYNQ_R_CTRL_REG = tmp;
4625 + break;
4626 + default: /* do nothing about the clock, but clear other bits. */
4627 + tmp = ~(VLYNQ_CTL_CLKDIR_MASK | VLYNQ_CTL_CLKDIV_MASK);
4628 + VLYNQ_CTRL_REG &= tmp;
4629 + break;
4630 + }
4631 +}
4632 +
4633 + /* ----------------------------------------------------------------------------
4634 + * Function : vlynq_link_check()
4635 + * Description: This function checks the current VLYNQ for a link.
4636 + * An arbitrary amount of time is allowed for the link to come up .
4637 + * Returns 0 for "no link / failure " and 1 for "link available".
4638 + * -----------------------------------------------------------------------------
4639 + */
4640 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev)
4641 +{
4642 + /*sleep for 64 cycles, allow link to come up*/
4643 + vlynq_delay(64);
4644 +
4645 + /* check status register return OK if link is found. */
4646 + if (VLYNQ_STATUS_REG & VLYNQ_STS_LINK_MASK)
4647 + {
4648 + return 1; /* Link Available */
4649 + }
4650 + else
4651 + {
4652 + return 0; /* Link Failure */
4653 + }
4654 +}
4655 +
4656 +/* ----------------------------------------------------------------------------
4657 + * Function : vlynq_init()
4658 + * Description: Initialization function accepting paramaters for VLYNQ module
4659 + * initialization. The Options bitmap decides what operations are performed
4660 + * as a part of initialization. The Input parameters are obtained through the
4661 + * sub fields of VLYNQ_DEV structure.
4662 + */
4663 +
4664 +int vlynq_init(VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options)
4665 +{
4666 + unsigned int map;
4667 + unsigned int val=0,cnt,tmp;
4668 + unsigned int counter=0;
4669 + VLYNQ_INTERRUPT_CNTRL *intSetting=NULL;
4670 +
4671 + /* validate arguments */
4672 + if( VLYNQ_OUTRANGE(pdev->clk_source, VLYNQ_CLK_SOURCE_REMOTE, VLYNQ_CLK_SOURCE_NONE) ||
4673 + VLYNQ_OUTRANGE(pdev->clk_div, 8, 1) )
4674 + {
4675 + return VLYNQ_INVALID_ARG;
4676 + }
4677 +
4678 + /** perform all sanity checks first **/
4679 + if(pdev->state != VLYNQ_DRV_STATE_UNINIT)
4680 + return VLYNQ_INVALID_DRV_STATE;
4681 +
4682 + /** Initialize local and remote register set addresses- additional
4683 + * provision to access the registers directly if need be */
4684 + pdev->local = (VLYNQ_REG_SET*)pdev->module_base;
4685 + pdev->remote = (VLYNQ_REG_SET*) (pdev->module_base + VLYNQ_REMOTE_REGS_OFFSET);
4686 +
4687 + /* Detect faulty int configuration that might induce int pkt looping */
4688 + if ( (options & VLYNQ_INIT_LOCAL_INTERRUPTS) && (options & VLYNQ_INIT_REMOTE_INTERRUPTS) )
4689 + {
4690 + /* case when both local and remote are configured */
4691 + if((pdev->local_irq.intLocal== VLYNQ_INT_REMOTE ) /* interrupts transfered to remote from local */
4692 + && (pdev->remote_irq.intLocal== VLYNQ_INT_REMOTE) /* interrupts transfered from remote to local */
4693 + && ((pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) || (pdev->remote_irq.intRemote == VLYNQ_INT_ROOT_ISR)) )
4694 + {
4695 + return (VLYNQ_INT_CONFIG_ERR);
4696 + }
4697 + }
4698 +
4699 + pdev->state = VLYNQ_DRV_STATE_ININIT;
4700 + pdev->intCount = 0;
4701 + pdev->isrCount = 0;
4702 +
4703 + /*** Its assumed that the vlynq module has been brought out of reset
4704 + * before invocation of vlynq_init. Since, this operation is board specific
4705 + * it must be handled outside this generic driver */
4706 +
4707 + /* Assert reset the remote device, call reset_cb,
4708 + * reset CB holds Reset according to the device needs. */
4709 + VLYNQ_RESETCB(VLYNQ_RESET_ASSERT);
4710 +
4711 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
4712 + * usually input for all the devices. */
4713 + if (options & VLYNQ_INIT_CONFIG_CLOCK)
4714 + {
4715 + vlynq_configClock(pdev);
4716 + }
4717 +
4718 + /* Call reset_cb again. It will release the remote device
4719 + * from reset, and wait for a while. */
4720 + VLYNQ_RESETCB(VLYNQ_RESET_DEASSERT);
4721 +
4722 + if(options & VLYNQ_INIT_CHECK_LINK )
4723 + {
4724 + /* Check for link up during initialization*/
4725 + while( counter < 25 )
4726 + {
4727 + /* loop around giving a chance for link status to settle down */
4728 + counter++;
4729 + if(vlynq_link_check(pdev))
4730 + {
4731 + /* Link is up exit loop*/
4732 + break;
4733 + }
4734 +
4735 + vlynq_delay(4000);
4736 + }/*end of while counter loop */
4737 +
4738 + if(!vlynq_link_check(pdev))
4739 + {
4740 + /* Handle this case as abort */
4741 + pdev->state = VLYNQ_DRV_STATE_ERROR;
4742 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4743 + return VLYNQ_LINK_DOWN;
4744 + }/* end of if not vlynq_link_check conditional block */
4745 +
4746 + }/*end of if options & VLYNQ_INIT_CHECK_LINK conditional block */
4747 +
4748 +
4749 + if (options & VLYNQ_INIT_LOCAL_MEM_REGIONS)
4750 + {
4751 + /* Initialise local memory regions . This initialization lets
4752 + * the local host access remote device memory regions*/
4753 + int i;
4754 +
4755 + /* configure the VLYNQ portal window to a PHYSICAL
4756 + * address of the local CPU */
4757 + VLYNQ_ALIGN4(pdev->local_mem.Txmap);
4758 + VLYNQ_TXMAP_REG = (pdev->local_mem.Txmap);
4759 +
4760 + /*This code assumes input parameter is itself a physical address */
4761 + for(i=0; i < VLYNQ_MAX_MEMORY_REGIONS ; i++)
4762 + {
4763 + /* Physical address on the remote */
4764 + map = i+1;
4765 + VLYNQ_R_RXMAP_SIZE_REG(map) = 0;
4766 + if( pdev->remote_mem.RxSize[i])
4767 + {
4768 + VLYNQ_ALIGN4(pdev->remote_mem.RxOffset[i]);
4769 + VLYNQ_ALIGN4(pdev->remote_mem.RxSize[i]);
4770 + VLYNQ_R_RXMAP_OFFSET_REG(map) = pdev->remote_mem.RxOffset[i];
4771 + VLYNQ_R_RXMAP_SIZE_REG(map) = pdev->remote_mem.RxSize[i];
4772 + }
4773 + }
4774 + }
4775 +
4776 + if(options & VLYNQ_INIT_REMOTE_MEM_REGIONS )
4777 + {
4778 + int i;
4779 +
4780 + /* Initialise remote memory regions. This initialization lets remote
4781 + * device access local host memory regions. It configures the VLYNQ portal
4782 + * window to a PHYSICAL address of the remote */
4783 + VLYNQ_ALIGN4(pdev->remote_mem.Txmap);
4784 + VLYNQ_R_TXMAP_REG = pdev->remote_mem.Txmap;
4785 +
4786 + for( i=0; i<VLYNQ_MAX_MEMORY_REGIONS; i++)
4787 + {
4788 + /* Physical address on the local */
4789 + map = i+1;
4790 + VLYNQ_RXMAP_SIZE_REG(map) = 0;
4791 + if( pdev->local_mem.RxSize[i])
4792 + {
4793 + VLYNQ_ALIGN4(pdev->local_mem.RxOffset[i]);
4794 + VLYNQ_ALIGN4(pdev->local_mem.RxSize[i]);
4795 + VLYNQ_RXMAP_OFFSET_REG(map) = (pdev->local_mem.RxOffset[i]);
4796 + VLYNQ_RXMAP_SIZE_REG(map) = (pdev->local_mem.RxSize[i]);
4797 + }
4798 + }
4799 + }
4800 +
4801 + /* Adapted from original vlynq driver from cable - Calculate VLYNQ bus width */
4802 + pdev->width = 3 + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_STATUS_REG)
4803 + + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_R_STATUS_REG);
4804 +
4805 + /* chance to initialize the device, e.g. to boost VLYNQ
4806 + * clock by modifying pdev->clk_div or and verify the width. */
4807 + VLYNQ_RESETCB(VLYNQ_RESET_LINKESTABLISH);
4808 +
4809 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
4810 + * usually input for all the devices. */
4811 + if(options & VLYNQ_INIT_CONFIG_CLOCK )
4812 + {
4813 + vlynq_configClock(pdev);
4814 + }
4815 +
4816 + /* last check for link*/
4817 + if(options & VLYNQ_INIT_CHECK_LINK )
4818 + {
4819 + /* Final Check for link during initialization*/
4820 + while( counter < 25 )
4821 + {
4822 + /* loop around giving a chance for link status to settle down */
4823 + counter++;
4824 + if(vlynq_link_check(pdev))
4825 + {
4826 + /* Link is up exit loop*/
4827 + break;
4828 + }
4829 +
4830 + vlynq_delay(4000);
4831 + }/*end of while counter loop */
4832 +
4833 + if(!vlynq_link_check(pdev))
4834 + {
4835 + /* Handle this case as abort */
4836 + pdev->state = VLYNQ_DRV_STATE_ERROR;
4837 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4838 + return VLYNQ_LINK_DOWN;
4839 + }/* end of if not vlynq_link_check conditional block */
4840 +
4841 + } /* end of if options & VLYNQ_INIT_CHECK_LINK */
4842 +
4843 + if(options & VLYNQ_INIT_LOCAL_INTERRUPTS )
4844 + {
4845 + /* Configure local interrupt settings */
4846 + intSetting = &(pdev->local_irq);
4847 +
4848 + /* Map local module status interrupts to interrupt vector*/
4849 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4850 +
4851 + /* enable local module status interrupts */
4852 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4853 +
4854 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4855 + {
4856 + /*set the intLocal bit*/
4857 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4858 + }
4859 +
4860 + /* Irrespective of whether interrupts are handled locally, program
4861 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4862 + * i.e remote packets are set intPending register->which will result in
4863 + * same packet being sent out) has been done already
4864 + */
4865 +
4866 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4867 + {
4868 + /* Set the int2Cfg register, so that remote interrupt
4869 + * packets are written to intPending register */
4870 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4871 +
4872 + /* Set intPtr register to point to intPending register */
4873 + VLYNQ_INT_PTR_REG = VLYNQ_INT_PENDING_REG_PTR ;
4874 + }
4875 + else
4876 + {
4877 + /*set the interrupt pointer register*/
4878 + VLYNQ_INT_PTR_REG = intSetting->intr_ptr;
4879 + /* Dont bother to modify int2Cfg as it would be zero */
4880 + }
4881 +
4882 + /** Clear bits related to INT settings in control register **/
4883 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4884 +
4885 + /** Or the bits to be set with Control register **/
4886 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG | val;
4887 +
4888 + /* initialise local ICB */
4889 + if(vlynqInterruptInit(pdev)==VLYNQ_MEMALLOC_FAIL)
4890 + return VLYNQ_MEMALLOC_FAIL;
4891 +
4892 + /* Install handler for local module status interrupts. By default when
4893 + * local interrupt setting is initialised, the local module status are
4894 + * enabled and handler hooked up */
4895 + if(vlynq_install_isr(pdev, intSetting->map_vector, vlynq_local_module_isr,
4896 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4897 + return VLYNQ_INVALID_ARG;
4898 + } /* end of init local interrupts */
4899 +
4900 + if(options & VLYNQ_INIT_REMOTE_INTERRUPTS )
4901 + {
4902 + /* Configure remote interrupt settings from configuration */
4903 + intSetting = &(pdev->remote_irq);
4904 +
4905 + /* Map remote module status interrupts to remote interrupt vector*/
4906 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4907 + /* enable remote module status interrupts */
4908 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4909 +
4910 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4911 + {
4912 + /*set the intLocal bit*/
4913 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4914 + }
4915 +
4916 + /* Irrespective of whether interrupts are handled locally, program
4917 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4918 + * i.e remote packets are set intPending register->which will result in
4919 + * same packet being sent out) has been done already
4920 + */
4921 +
4922 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4923 + {
4924 + /* Set the int2Cfg register, so that remote interrupt
4925 + * packets are written to intPending register */
4926 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4927 + /* Set intPtr register to point to intPending register */
4928 + VLYNQ_R_INT_PTR_REG = VLYNQ_R_INT_PENDING_REG_PTR ;
4929 + }
4930 + else
4931 + {
4932 + /*set the interrupt pointer register*/
4933 + VLYNQ_R_INT_PTR_REG = intSetting->intr_ptr;
4934 + /* Dont bother to modify int2Cfg as it would be zero */
4935 + }
4936 +
4937 + if( (intSetting->intLocal == VLYNQ_INT_REMOTE) &&
4938 + (options & VLYNQ_INIT_LOCAL_INTERRUPTS) &&
4939 + (pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) )
4940 + {
4941 + /* Install handler for remote module status interrupts. By default when
4942 + * remote interrupts are forwarded to local root_isr then remote_module_isr is
4943 + * enabled and handler hooked up */
4944 + if(vlynq_install_isr(pdev,intSetting->map_vector,vlynq_remote_module_isr,
4945 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4946 + return VLYNQ_INVALID_ARG;
4947 + }
4948 +
4949 +
4950 + /** Clear bits related to INT settings in control register **/
4951 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4952 +
4953 + /** Or the bits to be set with the remote Control register **/
4954 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG | val;
4955 +
4956 + } /* init remote interrupt settings*/
4957 +
4958 + if(options & VLYNQ_INIT_CLEAR_ERRORS )
4959 + {
4960 + /* Clear errors during initialization */
4961 + tmp = VLYNQ_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4962 + VLYNQ_STATUS_REG = tmp;
4963 + tmp = VLYNQ_R_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4964 + VLYNQ_R_STATUS_REG = tmp;
4965 + }
4966 +
4967 + /* clear int status */
4968 + val = VLYNQ_INT_STAT_REG;
4969 + VLYNQ_INT_STAT_REG = val;
4970 +
4971 + /* finish initialization */
4972 + pdev->state = VLYNQ_DRV_STATE_RUN;
4973 + VLYNQ_RESETCB( VLYNQ_RESET_INITOK);
4974 + return VLYNQ_SUCCESS;
4975 +
4976 +}
4977 +
4978 +
4979 +/* ----------------------------------------------------------------------------
4980 + * Function : vlynqInterruptInit()
4981 + * Description: This local function is used to set up the ICB table for the
4982 + * VLYNQ_STATUS_REG vlynq module. The input parameter "pdev" points the vlynq
4983 + * device instance whose ICB is allocated.
4984 + * Return : returns VLYNQ_SUCCESS or vlynq error for failure
4985 + * -----------------------------------------------------------------------------
4986 + */
4987 +static int vlynqInterruptInit(VLYNQ_DEV *pdev)
4988 +{
4989 + int i, numslots;
4990 +
4991 + /* Memory allocated statically.
4992 + * Initialise ICB,free list.Indicate primary slot empty.
4993 + * Intialise intVector <==> map_vector translation table*/
4994 + for(i=0; i < VLYNQ_NUM_INT_BITS; i++)
4995 + {
4996 + pdev->pIntrCB[i].isr = NULL;
4997 + pdev->pIntrCB[i].next = NULL; /*nothing chained */
4998 + pdev->vector_map[i] = -1; /* indicates unmapped */
4999 + }
5000 +
5001 + /* In the ICB slots, [VLYNQ_NUM_INT_BITS i.e 32 to ICB array size) are expansion slots
5002 + * required only when interrupt chaining/sharing is supported. In case
5003 + * of chained interrupts the list starts from primary slot and the
5004 + * additional slots are obtained from the common free area */
5005 +
5006 + /* Initialise freelist */
5007 +
5008 + numslots = VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS;
5009 +
5010 + if (numslots > VLYNQ_NUM_INT_BITS)
5011 + {
5012 + pdev->freelist = &(pdev->pIntrCB[VLYNQ_NUM_INT_BITS]);
5013 +
5014 + for(i = VLYNQ_NUM_INT_BITS; i < (numslots-1) ; i++)
5015 + {
5016 + pdev->pIntrCB[i].next = &(pdev->pIntrCB[i+1]);
5017 + pdev->pIntrCB[i].isr = NULL;
5018 + }
5019 + pdev->pIntrCB[i].next=NULL; /* Indicate end of freelist*/
5020 + pdev->pIntrCB[i].isr=NULL;
5021 + }
5022 + else
5023 + {
5024 + pdev->freelist = NULL;
5025 + }
5026 +
5027 + /** Reset mapping for IV 0-7 **/
5028 + VLYNQ_IVR_03TO00_REG = 0;
5029 + VLYNQ_IVR_07TO04_REG = 0;
5030 +
5031 + return VLYNQ_SUCCESS;
5032 +}
5033 +
5034 +/** remember that hooking up of root ISR handler with the interrupt controller
5035 + * is not done as a part of this driver. Typically, it must be done after
5036 + * invoking vlynq_init*/
5037 +
5038 +
5039 + /* ----------------------------------------------------------------------------
5040 + * ISR with the SOC interrupt controller. This ISR typically scans
5041 + * the Int PENDING/SET register in the VLYNQ module and calls the
5042 + * appropriate ISR associated with the correponding vector number.
5043 + * -----------------------------------------------------------------------------
5044 + */
5045 +void vlynq_root_isr(void *arg)
5046 +{
5047 + int source; /* Bit position of pending interrupt, start from 0 */
5048 + unsigned int interrupts, clrInterrupts;
5049 + VLYNQ_DEV * pdev;
5050 + VLYNQ_INTR_CNTRL_ICB *entry;
5051 +
5052 + pdev=(VLYNQ_DEV*)(arg); /*obtain the vlynq device pointer*/
5053 +
5054 + interrupts = VLYNQ_INT_STAT_REG; /* Get the list of pending interrupts */
5055 + VLYNQ_INT_STAT_REG = interrupts; /* clear the int CR register */
5056 + clrInterrupts = interrupts; /* save them for further analysis */
5057 +
5058 + debugPrint("vlynq_root_isr: dev %u. INTCR = 0x%08lx\n", pdev->dev_idx, clrInterrupts,0,0,0,0);
5059 +
5060 + /* Scan interrupt bits */
5061 + source =0;
5062 + while( clrInterrupts != 0)
5063 + {
5064 + /* test if bit is set? */
5065 + if( 0x1ul & clrInterrupts)
5066 + {
5067 + entry = &(pdev->pIntrCB[source]); /* Get the ISR entry */
5068 + pdev->intCount++; /* update interrupt count */
5069 + if(entry->isr != NULL)
5070 + {
5071 + do
5072 + {
5073 + pdev->isrCount++; /* update isr invocation count */
5074 + /* Call the user ISR and update the count for ISR */
5075 + entry->isrCount++;
5076 + entry->isr(entry->arg1, entry->arg2, entry->arg3);
5077 + if (entry->next == NULL) break;
5078 + entry = entry->next;
5079 +
5080 + } while (entry->isr != NULL);
5081 + }
5082 + else
5083 + {
5084 + debugPrint(" ISR not installed for vlynq vector:%d\n",source,0,0,0,0,0);
5085 + }
5086 + }
5087 + clrInterrupts >>= 1; /* Next source bit */
5088 + ++source;
5089 + } /* endWhile clrInterrupts != 0 */
5090 +}
5091 +
5092 +
5093 + /* ----------------------------------------------------------------------------
5094 + * Function : vlynq_local__module_isr()
5095 + * Description: This ISR is attached to the local VLYNQ interrupt vector
5096 + * by the Vlynq Driver when local interrupts are being handled. i.e.
5097 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5098 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5099 + * is invoked.
5100 + * VLYNQ_DEV is passed as arg1. arg2 and arg3 are unused.
5101 + * -----------------------------------------------------------------------------
5102 + */
5103 +static void vlynq_local_module_isr(void *arg1,void *arg2, void *arg3)
5104 +{
5105 + VLYNQ_REPORT_CB func;
5106 + unsigned int dwStatRegVal;
5107 + VLYNQ_DEV * pdev;
5108 +
5109 + pdev = (VLYNQ_DEV*) arg1;
5110 + /* Callback function is read from the device pointer that is passed as an argument */
5111 + func = pdev->report_cb;
5112 +
5113 + /* read local status register */
5114 + dwStatRegVal = VLYNQ_STATUS_REG;
5115 +
5116 + /* clear pending events */
5117 + VLYNQ_STATUS_REG = dwStatRegVal;
5118 +
5119 + /* invoke user callback */
5120 + if( func != NULL)
5121 + func( pdev, VLYNQ_LOCAL_DVC, dwStatRegVal);
5122 +
5123 +}
5124 +
5125 + /* ----------------------------------------------------------------------------
5126 + * Function : vlynq_remote_module_isr()
5127 + * Description: This ISR is attached to the remote VLYNQ interrupt vector
5128 + * by the Vlynq Driver when remote interrupts are being handled locally. i.e.
5129 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5130 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5131 + * is invoked.
5132 + * The parameters irq,regs ar unused.
5133 + * -----------------------------------------------------------------------------
5134 + */
5135 +static void vlynq_remote_module_isr(void *arg1,void *arg2, void *arg3)
5136 +{
5137 + VLYNQ_REPORT_CB func;
5138 + unsigned int dwStatRegVal;
5139 + VLYNQ_DEV * pdev;
5140 +
5141 +
5142 + pdev = (VLYNQ_DEV*) arg1;
5143 +
5144 + /* Callback function is read from the device pointer that is passed as an argument */
5145 + func = pdev->report_cb;
5146 +
5147 + /* read local status register */
5148 + dwStatRegVal = VLYNQ_R_STATUS_REG;
5149 +
5150 + /* clear pending events */
5151 + VLYNQ_R_STATUS_REG = dwStatRegVal;
5152 +
5153 + /* invoke user callback */
5154 + if( func != NULL)
5155 + func( pdev, VLYNQ_REMOTE_DVC, dwStatRegVal);
5156 +
5157 +}
5158 +
5159 +/* ----------------------------------------------------------------------------
5160 + * Function : vlynq_interrupt_get_count()
5161 + * Description: This function returns the number of times a particular intr
5162 + * has been invoked.
5163 + *
5164 + * It returns 0, if erroneous map_vector is specified or if the corres isr
5165 + * has not been registered with VLYNQ.
5166 + */
5167 +unsigned int vlynq_interrupt_get_count(VLYNQ_DEV *pdev,
5168 + unsigned int map_vector)
5169 +{
5170 + VLYNQ_INTR_CNTRL_ICB *entry;
5171 + unsigned int count = 0;
5172 +
5173 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5174 + return count;
5175 +
5176 + entry = &(pdev->pIntrCB[map_vector]);
5177 +
5178 + if (entry)
5179 + count = entry->isrCount;
5180 +
5181 + return (count);
5182 +}
5183 +
5184 +
5185 +/* ----------------------------------------------------------------------------
5186 + * Function : vlynq_install_isr()
5187 + * Description: This function installs ISR for Vlynq interrupt vector
5188 + * bits(in IntPending register). This function should be used only when
5189 + * Vlynq interrupts are being handled locally(remote may be programmed to send
5190 + * interrupt packets).Also, the int2cfg should be 1 and the least significant
5191 + * 8 bits of the Interrupt Pointer Register must point to Interrupt
5192 + * Pending/Set Register).
5193 + * If host int2cfg=0 and the Interrupt Pointer register contains
5194 + * the address of the interrupt set register in the interrupt controller
5195 + * module of the local device , then the ISR for the remote interrupt must be
5196 + * directly registered with the Interrupt controller and must not use this API
5197 + * Note: this function simply installs the ISR in ICB It doesnt modify
5198 + * any register settings
5199 + */
5200 +int
5201 +vlynq_install_isr(VLYNQ_DEV *pdev,
5202 + unsigned int map_vector,
5203 + VLYNQ_INTR_CNTRL_ISR isr,
5204 + void *arg1, void *arg2, void *arg3)
5205 +{
5206 + VLYNQ_INTR_CNTRL_ICB *entry;
5207 +
5208 + if ( (map_vector > (VLYNQ_NUM_INT_BITS-1)) || (isr == NULL) )
5209 + return VLYNQ_INVALID_ARG;
5210 +
5211 + entry = &(pdev->pIntrCB[map_vector]);
5212 +
5213 + if(entry->isr == NULL)
5214 + {
5215 + entry->isr = isr;
5216 + entry->arg1 = arg1;
5217 + entry->arg2 = arg2;
5218 + entry->arg3 = arg3;
5219 + entry->next = NULL;
5220 + }
5221 + else
5222 + {
5223 + /** No more empty slots,return error */
5224 + if(pdev->freelist == NULL)
5225 + return VLYNQ_MEMALLOC_FAIL;
5226 +
5227 + while(entry->next != NULL)
5228 + {
5229 + entry = entry->next;
5230 + }
5231 +
5232 + /* Append new node to the chain */
5233 + entry->next = pdev->freelist;
5234 + /* Remove the appended node from freelist */
5235 + pdev->freelist = pdev->freelist->next;
5236 + entry= entry->next;
5237 +
5238 + /*** Set the ICB fields ***/
5239 + entry->isr = isr;
5240 + entry->arg1 = arg1;
5241 + entry->arg2 = arg2;
5242 + entry->arg3 = arg3;
5243 + entry->next = NULL;
5244 + }
5245 +
5246 + return VLYNQ_SUCCESS;
5247 +}
5248 +
5249 +
5250 +
5251 +/* ----------------------------------------------------------------------------
5252 + * Function : vlynq_uninstall_isr
5253 + * Description: This function is used to uninstall a previously
5254 + * registered ISR. In case of shared/chained interrupts, the
5255 + * void * arg parameter must uniquely identify the ISR to be
5256 + * uninstalled.
5257 + * Note: this function simply uninstalls the ISR in ICB
5258 + * It doesnt modify any register settings
5259 + */
5260 +int
5261 +vlynq_uninstall_isr(VLYNQ_DEV *pdev,
5262 + unsigned int map_vector,
5263 + void *arg1, void *arg2, void *arg3)
5264 +{
5265 + VLYNQ_INTR_CNTRL_ICB *entry,*temp;
5266 +
5267 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5268 + return VLYNQ_INVALID_ARG;
5269 +
5270 + entry = &(pdev->pIntrCB[map_vector]);
5271 +
5272 + if(entry->isr == NULL )
5273 + return VLYNQ_ISR_NON_EXISTENT;
5274 +
5275 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5276 + {
5277 + if(entry->next == NULL)
5278 + {
5279 + entry->isr=NULL;
5280 + return VLYNQ_SUCCESS;
5281 + }
5282 + else
5283 + {
5284 + temp = entry->next;
5285 + /* Copy next node in the chain to prim.slot */
5286 + entry->isr = temp->isr;
5287 + entry->arg1 = temp->arg1;
5288 + entry->arg2 = temp->arg2;
5289 + entry->arg3 = temp->arg3;
5290 + entry->next = temp->next;
5291 + /* Free the just copied node */
5292 + temp->isr = NULL;
5293 + temp->arg1 = NULL;
5294 + temp->arg2 = NULL;
5295 + temp->arg3 = NULL;
5296 + temp->next = pdev->freelist;
5297 + pdev->freelist = temp;
5298 + return VLYNQ_SUCCESS;
5299 + }
5300 + }
5301 + else
5302 + {
5303 + temp = entry;
5304 + while ( (entry = temp->next) != NULL)
5305 + {
5306 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5307 + {
5308 + /* remove node from chain */
5309 + temp->next = entry->next;
5310 + /* Add the removed node to freelist */
5311 + entry->isr = NULL;
5312 + entry->arg1 = NULL;
5313 + entry->arg2 = NULL;
5314 + entry->arg3 = NULL;
5315 + entry->next = pdev->freelist;
5316 + entry->isrCount = 0;
5317 + pdev->freelist = entry;
5318 + return VLYNQ_SUCCESS;
5319 + }
5320 + temp = entry;
5321 + }
5322 +
5323 + return VLYNQ_ISR_NON_EXISTENT;
5324 + }
5325 +}
5326 +
5327 +
5328 +
5329 +
5330 +/* ----------------------------------------------------------------------------
5331 + * function : vlynq_interrupt_vector_set()
5332 + * description:configures interrupt vector mapping,interrupt type
5333 + * polarity -all in one go.
5334 + */
5335 +int
5336 +vlynq_interrupt_vector_set(VLYNQ_DEV *pdev, /* vlynq device */
5337 + unsigned int int_vector, /* int vector on vlynq device */
5338 + unsigned int map_vector, /* bit for this interrupt */
5339 + VLYNQ_DEV_TYPE dev_type, /* local or remote device */
5340 + VLYNQ_INTR_POLARITY pol, /* polarity of interrupt */
5341 + VLYNQ_INTR_TYPE type) /* pulsed/level interrupt */
5342 +{
5343 + volatile unsigned int * vecreg;
5344 + unsigned int val=0;
5345 + unsigned int bytemask=0XFF;
5346 +
5347 + /* use the lower 8 bits of val to set the value , shift it to
5348 + * appropriate byte position in the ivr and write it to the
5349 + * corresponding register */
5350 +
5351 + /* validate the number of interrupts supported */
5352 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5353 + return VLYNQ_INVALID_ARG;
5354 +
5355 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5356 + return VLYNQ_INVALID_ARG;
5357 +
5358 + if (dev_type == VLYNQ_LOCAL_DVC)
5359 + {
5360 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5361 + }
5362 + else
5363 + {
5364 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5365 + }
5366 +
5367 + /* Update the intVector<==> bit position translation table */
5368 + pdev->vector_map[map_vector] = int_vector;
5369 +
5370 + /* val has been initialised to zero. we only have to turn on appropriate bits*/
5371 + if(type == VLYNQ_INTR_PULSED)
5372 + val |= VLYNQ_IVR_INTTYPE_MASK;
5373 +
5374 + if(pol == VLYNQ_INTR_ACTIVE_LOW)
5375 + val |= VLYNQ_IVR_INTPOL_MASK;
5376 +
5377 + val |= map_vector;
5378 +
5379 + /** clear the correct byte position and then or val **/
5380 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5381 +
5382 + /** write to correct byte position in vecreg*/
5383 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5384 +
5385 + /* Setting a interrupt vector, leaves the interrupt disabled
5386 + * which must be enabled subsequently */
5387 +
5388 + return VLYNQ_SUCCESS;
5389 +}
5390 +
5391 +
5392 +/* ----------------------------------------------------------------------------
5393 + * Function : vlynq_interrupt_vector_cntl()
5394 + * Description:enables/disable interrupt
5395 + */
5396 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
5397 + unsigned int int_vector,
5398 + VLYNQ_DEV_TYPE dev_type,
5399 + unsigned int enable)
5400 +{
5401 + volatile unsigned int *vecReg;
5402 + unsigned int val=0;
5403 + unsigned int intenMask=0x80;
5404 +
5405 + /* validate the number of interrupts supported */
5406 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5407 + return VLYNQ_INVALID_ARG;
5408 +
5409 + if (dev_type == VLYNQ_LOCAL_DVC)
5410 + {
5411 + vecReg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5412 + }
5413 + else
5414 + {
5415 + vecReg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5416 + }
5417 +
5418 + /** Clear the correct byte position and then or val **/
5419 + *vecReg = (*vecReg) & ( ~(intenMask << ( (int_vector %4)*8) ) );
5420 +
5421 + if(enable)
5422 + {
5423 + val |= VLYNQ_IVR_INTEN_MASK;
5424 + /** Write to correct byte position in vecReg*/
5425 + *vecReg = (*vecReg) | (val << ( (int_vector % 4)*8) ) ;
5426 + }
5427 +
5428 + return VLYNQ_SUCCESS;
5429 +
5430 +}/* end of function vlynq_interrupt_vector_cntl */
5431 +
5432 +
5433 +
5434 +/* ----------------------------------------------------------------------------
5435 + * Function : vlynq_interrupt_vector_map()
5436 + * Description:Configures interrupt vector mapping alone
5437 + */
5438 +int
5439 +vlynq_interrupt_vector_map( VLYNQ_DEV *pdev,
5440 + VLYNQ_DEV_TYPE dev_type,
5441 + unsigned int int_vector,
5442 + unsigned int map_vector)
5443 +{
5444 + volatile unsigned int * vecreg;
5445 + unsigned int val=0;
5446 + unsigned int bytemask=0x1f; /* mask to turn off bits corresponding to int vector */
5447 +
5448 + /* use the lower 8 bits of val to set the value , shift it to
5449 + * appropriate byte position in the ivr and write it to the
5450 + * corresponding register */
5451 +
5452 + /* validate the number of interrupts supported */
5453 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5454 + return VLYNQ_INVALID_ARG;
5455 +
5456 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5457 + return VLYNQ_INVALID_ARG;
5458 +
5459 + if (dev_type == VLYNQ_LOCAL_DVC)
5460 + {
5461 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5462 + }
5463 + else
5464 + {
5465 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5466 + }
5467 +
5468 + /* Update the intVector<==> bit position translation table */
5469 + pdev->vector_map[map_vector] = int_vector;
5470 +
5471 + /** val has been initialised to zero. we only have to turn on
5472 + * appropriate bits*/
5473 + val |= map_vector;
5474 +
5475 + /** clear the correct byte position and then or val **/
5476 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5477 +
5478 + /** write to correct byte position in vecreg*/
5479 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5480 +
5481 + return VLYNQ_SUCCESS;
5482 +}
5483 +
5484 +
5485 +/* ----------------------------------------------------------------------------
5486 + * function : vlynq_interrupt_set_polarity()
5487 + * description:configures interrupt polarity .
5488 + */
5489 +int
5490 +vlynq_interrupt_set_polarity( VLYNQ_DEV *pdev ,
5491 + VLYNQ_DEV_TYPE dev_type,
5492 + unsigned int map_vector,
5493 + VLYNQ_INTR_POLARITY pol)
5494 +{
5495 + volatile unsigned int * vecreg;
5496 + int int_vector;
5497 + unsigned int val=0;
5498 + unsigned int bytemask=0x20; /** mask to turn off bits corresponding to int polarity */
5499 +
5500 + /* get the int_vector from map_vector */
5501 + int_vector = pdev->vector_map[map_vector];
5502 +
5503 + if(int_vector == -1)
5504 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5505 +
5506 + /* use the lower 8 bits of val to set the value , shift it to
5507 + * appropriate byte position in the ivr and write it to the
5508 + * corresponding register */
5509 +
5510 + if (dev_type == VLYNQ_LOCAL_DVC)
5511 + {
5512 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5513 + }
5514 + else
5515 + {
5516 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5517 + }
5518 +
5519 + /* val has been initialised to zero. we only have to turn on
5520 + * appropriate bits, if need be*/
5521 +
5522 + /** clear the correct byte position and then or val **/
5523 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5524 +
5525 + if( pol == VLYNQ_INTR_ACTIVE_LOW)
5526 + {
5527 + val |= VLYNQ_IVR_INTPOL_MASK;
5528 + /** write to correct byte position in vecreg*/
5529 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5530 + }
5531 +
5532 + return VLYNQ_SUCCESS;
5533 +}
5534 +
5535 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
5536 + VLYNQ_DEV_TYPE dev_type,
5537 + unsigned int map_vector)
5538 +{
5539 + volatile unsigned int * vecreg;
5540 + int int_vector;
5541 + unsigned int val=0;
5542 +
5543 + /* get the int_vector from map_vector */
5544 + int_vector = pdev->vector_map[map_vector];
5545 +
5546 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5547 + return(-1);
5548 +
5549 + if(int_vector == -1)
5550 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5551 +
5552 + /* use the lower 8 bits of val to set the value , shift it to
5553 + * appropriate byte position in the ivr and write it to the
5554 + * corresponding register */
5555 +
5556 + if (dev_type == VLYNQ_LOCAL_DVC)
5557 + {
5558 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5559 + }
5560 + else
5561 + {
5562 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5563 + }
5564 +
5565 + /** read the information into val **/
5566 + val = (*vecreg) & ((VLYNQ_IVR_INTPOL_MASK << ( (int_vector %4)*8) ) );
5567 +
5568 + return (val ? (VLYNQ_INTR_ACTIVE_LOW) : (VLYNQ_INTR_ACTIVE_HIGH));
5569 +}
5570 +
5571 +
5572 +/* ----------------------------------------------------------------------------
5573 + * function : vlynq_interrupt_set_type()
5574 + * description:configures interrupt type .
5575 + */
5576 +int vlynq_interrupt_set_type( VLYNQ_DEV *pdev,
5577 + VLYNQ_DEV_TYPE dev_type,
5578 + unsigned int map_vector,
5579 + VLYNQ_INTR_TYPE type)
5580 +{
5581 + volatile unsigned int * vecreg;
5582 + unsigned int val=0;
5583 + int int_vector;
5584 +
5585 + /** mask to turn off bits corresponding to interrupt type */
5586 + unsigned int bytemask=0x40;
5587 +
5588 + /* get the int_vector from map_vector */
5589 + int_vector = pdev->vector_map[map_vector];
5590 + if(int_vector == -1)
5591 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5592 +
5593 + /* use the lower 8 bits of val to set the value , shift it to
5594 + * appropriate byte position in the ivr and write it to the
5595 + * corresponding register */
5596 + if (dev_type == VLYNQ_LOCAL_DVC)
5597 + {
5598 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5599 + }
5600 + else
5601 + {
5602 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5603 + }
5604 +
5605 + /** val has been initialised to zero. we only have to turn on
5606 + * appropriate bits if need be*/
5607 +
5608 + /** clear the correct byte position and then or val **/
5609 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5610 +
5611 + if( type == VLYNQ_INTR_PULSED)
5612 + {
5613 + val |= VLYNQ_IVR_INTTYPE_MASK;
5614 + /** write to correct byte position in vecreg*/
5615 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5616 + }
5617 +
5618 + return VLYNQ_SUCCESS;
5619 +}
5620 +
5621 +/* ----------------------------------------------------------------------------
5622 + * function : vlynq_interrupt_get_type()
5623 + * description:returns interrupt type .
5624 + */
5625 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev, VLYNQ_DEV_TYPE dev_type,
5626 + unsigned int map_vector)
5627 +{
5628 + volatile unsigned int * vecreg;
5629 + unsigned int val=0;
5630 + int int_vector;
5631 +
5632 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5633 + return(-1);
5634 +
5635 + /* get the int_vector from map_vector */
5636 + int_vector = pdev->vector_map[map_vector];
5637 + if(int_vector == -1)
5638 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5639 +
5640 + /* use the lower 8 bits of val to set the value , shift it to
5641 + * appropriate byte position in the ivr and write it to the
5642 + * corresponding register */
5643 + if (dev_type == VLYNQ_LOCAL_DVC)
5644 + {
5645 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5646 + }
5647 + else
5648 + {
5649 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5650 + }
5651 +
5652 + /** Read the correct bit position into val **/
5653 + val = (*vecreg) & ((VLYNQ_IVR_INTTYPE_MASK << ( (int_vector %4)*8) ) );
5654 +
5655 + return (val ? (VLYNQ_INTR_PULSED) : (VLYNQ_INTR_LEVEL));
5656 +}
5657 +
5658 +/* ----------------------------------------------------------------------------
5659 + * function : vlynq_interrupt_enable()
5660 + * description:Enable interrupt by writing to IVR register.
5661 + */
5662 +int vlynq_interrupt_enable( VLYNQ_DEV *pdev,
5663 + VLYNQ_DEV_TYPE dev_type,
5664 + unsigned int map_vector)
5665 +{
5666 + volatile unsigned int * vecreg;
5667 + unsigned int val=0;
5668 + int int_vector;
5669 +
5670 + /** mask to turn off bits corresponding to interrupt enable */
5671 + unsigned int bytemask=0x80;
5672 +
5673 + /* get the int_vector from map_vector */
5674 + int_vector = pdev->vector_map[map_vector];
5675 + if(int_vector == -1)
5676 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5677 +
5678 + /* use the lower 8 bits of val to set the value , shift it to
5679 + * appropriate byte position in the ivr and write it to the
5680 + * corresponding register */
5681 +
5682 + if (dev_type == VLYNQ_LOCAL_DVC)
5683 + {
5684 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5685 + }
5686 + else
5687 + {
5688 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5689 + }
5690 +
5691 + /** val has been initialised to zero. we only have to turn on
5692 + * bit corresponding to interrupt enable*/
5693 + val |= VLYNQ_IVR_INTEN_MASK;
5694 +
5695 + /** clear the correct byte position and then or val **/
5696 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5697 +
5698 + /** write to correct byte position in vecreg*/
5699 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5700 +
5701 + return VLYNQ_SUCCESS;
5702 +}
5703 +
5704 +
5705 +/* ----------------------------------------------------------------------------
5706 + * function : vlynq_interrupt_disable()
5707 + * description:Disable interrupt by writing to IVR register.
5708 + */
5709 +int
5710 +vlynq_interrupt_disable( VLYNQ_DEV *pdev,
5711 + VLYNQ_DEV_TYPE dev_type,
5712 + unsigned int map_vector)
5713 +{
5714 + volatile unsigned int * vecreg;
5715 + int int_vector;
5716 +
5717 + /** mask to turn off bits corresponding to interrupt enable */
5718 + unsigned int bytemask=0x80;
5719 +
5720 + /* get the int_vector from map_vector */
5721 + int_vector = pdev->vector_map[map_vector];
5722 + if(int_vector == -1)
5723 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5724 +
5725 + /* use the lower 8 bits of val to set the value , shift it to
5726 + * appropriate byte position in the ivr and write it to the
5727 + * corresponding register */
5728 + if (dev_type == VLYNQ_LOCAL_DVC)
5729 + {
5730 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5731 + }
5732 + else
5733 + {
5734 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5735 + }
5736 +
5737 + /* We disable the interrupt by simply turning off the bit
5738 + * corresponding to Interrupt enable.
5739 + * Clear the interrupt enable bit in the correct byte position **/
5740 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5741 +
5742 + /* Dont have to set any bit positions */
5743 +
5744 + return VLYNQ_SUCCESS;
5745 +
5746 +}
5747 +
5748 +
5749 +
5750 +
5751 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
5752 --- linux.old/drivers/char/serial.c 2005-10-21 16:43:20.709226000 +0200
5753 +++ linux.dev/drivers/char/serial.c 2005-11-10 01:10:46.015585250 +0100
5754 @@ -419,7 +419,40 @@
5755 return 0;
5756 }
5757
5758 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5759 +#if defined(CONFIG_AR7)
5760 +
5761 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
5762 +{
5763 + return (inb(info->port + (offset * 4)) & 0xff);
5764 +}
5765 +
5766 +
5767 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
5768 +{
5769 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5770 + return (inb(info->port + (offset * 4)) & 0xff);
5771 +#else
5772 + return (inb_p(info->port + (offset * 4)) & 0xff);
5773 +#endif
5774 +}
5775 +
5776 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
5777 +{
5778 + outb(value, info->port + (offset * 4));
5779 +}
5780 +
5781 +
5782 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
5783 + int value)
5784 +{
5785 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5786 + outb(value, info->port + (offset * 4));
5787 +#else
5788 + outb_p(value, info->port + (offset * 4));
5789 +#endif
5790 +}
5791 +
5792 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5793
5794 #include <asm/mips-boards/atlas.h>
5795
5796 @@ -478,8 +511,10 @@
5797 * needed for certain old 386 machines, I've left these #define's
5798 * in....
5799 */
5800 +#ifndef CONFIG_AR7
5801 #define serial_inp(info, offset) serial_in(info, offset)
5802 #define serial_outp(info, offset, value) serial_out(info, offset, value)
5803 +#endif
5804
5805
5806 /*
5807 @@ -1728,7 +1763,15 @@
5808 /* Special case since 134 is really 134.5 */
5809 quot = (2*baud_base / 269);
5810 else if (baud)
5811 +#ifdef CONFIG_AR7
5812 + quot = (CONFIG_AR7_SYS*500000) / baud;
5813 +
5814 + if ((quot%16)>7)
5815 + quot += 8;
5816 + quot /=16;
5817 +#else
5818 quot = baud_base / baud;
5819 +#endif
5820 }
5821 /* If the quotient is zero refuse the change */
5822 if (!quot && old_termios) {
5823 @@ -5540,8 +5583,10 @@
5824 state->irq = irq_cannonicalize(state->irq);
5825 if (state->hub6)
5826 state->io_type = SERIAL_IO_HUB6;
5827 +#ifndef CONFIG_AR7
5828 if (state->port && check_region(state->port,8))
5829 continue;
5830 +#endif
5831 #ifdef CONFIG_MCA
5832 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
5833 continue;
5834 @@ -5997,7 +6042,15 @@
5835 info->io_type = state->io_type;
5836 info->iomem_base = state->iomem_base;
5837 info->iomem_reg_shift = state->iomem_reg_shift;
5838 +#ifdef CONFIG_AR7
5839 + quot = (CONFIG_AR7_SYS*500000) / baud;
5840 +
5841 + if ((quot%16)>7)
5842 + quot += 8;
5843 + quot /=16;
5844 +#else
5845 quot = state->baud_base / baud;
5846 +#endif
5847 cval = cflag & (CSIZE | CSTOPB);
5848 #if defined(__powerpc__) || defined(__alpha__)
5849 cval >>= 8;
5850 diff -urN linux.old/drivers/char/serial.c.orig linux.dev/drivers/char/serial.c.orig
5851 --- linux.old/drivers/char/serial.c.orig 1970-01-01 01:00:00.000000000 +0100
5852 +++ linux.dev/drivers/char/serial.c.orig 2005-11-10 01:10:46.051587500 +0100
5853 @@ -0,0 +1,6054 @@
5854 +/*
5855 + * linux/drivers/char/serial.c
5856 + *
5857 + * Copyright (C) 1991, 1992 Linus Torvalds
5858 + * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997,
5859 + * 1998, 1999 Theodore Ts'o
5860 + *
5861 + * Extensively rewritten by Theodore Ts'o, 8/16/92 -- 9/14/92. Now
5862 + * much more extensible to support other serial cards based on the
5863 + * 16450/16550A UART's. Added support for the AST FourPort and the
5864 + * Accent Async board.
5865 + *
5866 + * set_serial_info fixed to set the flags, custom divisor, and uart
5867 + * type fields. Fix suggested by Michael K. Johnson 12/12/92.
5868 + *
5869 + * 11/95: TIOCMIWAIT, TIOCGICOUNT by Angelo Haritsis <ah@doc.ic.ac.uk>
5870 + *
5871 + * 03/96: Modularised by Angelo Haritsis <ah@doc.ic.ac.uk>
5872 + *
5873 + * rs_set_termios fixed to look also for changes of the input
5874 + * flags INPCK, BRKINT, PARMRK, IGNPAR and IGNBRK.
5875 + * Bernd Anhäupl 05/17/96.
5876 + *
5877 + * 1/97: Extended dumb serial ports are a config option now.
5878 + * Saves 4k. Michael A. Griffith <grif@acm.org>
5879 + *
5880 + * 8/97: Fix bug in rs_set_termios with RTS
5881 + * Stanislav V. Voronyi <stas@uanet.kharkov.ua>
5882 + *
5883 + * 3/98: Change the IRQ detection, use of probe_irq_o*(),
5884 + * suppress TIOCSERGWILD and TIOCSERSWILD
5885 + * Etienne Lorrain <etienne.lorrain@ibm.net>
5886 + *
5887 + * 4/98: Added changes to support the ARM architecture proposed by
5888 + * Russell King
5889 + *
5890 + * 5/99: Updated to include support for the XR16C850 and ST16C654
5891 + * uarts. Stuart MacDonald <stuartm@connecttech.com>
5892 + *
5893 + * 8/99: Generalized PCI support added. Theodore Ts'o
5894 + *
5895 + * 3/00: Rid circular buffer of redundant xmit_cnt. Fix a
5896 + * few races on freeing buffers too.
5897 + * Alan Modra <alan@linuxcare.com>
5898 + *
5899 + * 5/00: Support for the RSA-DV II/S card added.
5900 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
5901 + *
5902 + * 6/00: Remove old-style timer, use timer_list
5903 + * Andrew Morton <andrewm@uow.edu.au>
5904 + *
5905 + * 7/00: Support Timedia/Sunix/Exsys PCI cards
5906 + *
5907 + * 7/00: fix some returns on failure not using MOD_DEC_USE_COUNT.
5908 + * Arnaldo Carvalho de Melo <acme@conectiva.com.br>
5909 + *
5910 + * 10/00: add in optional software flow control for serial console.
5911 + * Kanoj Sarcar <kanoj@sgi.com> (Modified by Theodore Ts'o)
5912 + *
5913 + * 02/02: Fix for AMD Elan bug in transmit irq routine, by
5914 + * Christer Weinigel <wingel@hog.ctrl-c.liu.se>,
5915 + * Robert Schwebel <robert@schwebel.de>,
5916 + * Juergen Beisert <jbeisert@eurodsn.de>,
5917 + * Theodore Ts'o <tytso@mit.edu>
5918 + *
5919 + * 10/00: Added suport for MIPS Atlas board.
5920 + * 11/00: Hooks for serial kernel debug port support added.
5921 + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard,
5922 + * carstenl@mips.com
5923 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5924 + */
5925 +
5926 +static char *serial_version = "5.05c";
5927 +static char *serial_revdate = "2001-07-08";
5928 +
5929 +/*
5930 + * Serial driver configuration section. Here are the various options:
5931 + *
5932 + * CONFIG_HUB6
5933 + * Enables support for the venerable Bell Technologies
5934 + * HUB6 card.
5935 + *
5936 + * CONFIG_SERIAL_MANY_PORTS
5937 + * Enables support for ports beyond the standard, stupid
5938 + * COM 1/2/3/4.
5939 + *
5940 + * CONFIG_SERIAL_MULTIPORT
5941 + * Enables support for special multiport board support.
5942 + *
5943 + * CONFIG_SERIAL_SHARE_IRQ
5944 + * Enables support for multiple serial ports on one IRQ
5945 + *
5946 + * CONFIG_SERIAL_DETECT_IRQ
5947 + * Enable the autodetection of IRQ on standart ports
5948 + *
5949 + * SERIAL_PARANOIA_CHECK
5950 + * Check the magic number for the async_structure where
5951 + * ever possible.
5952 + *
5953 + * CONFIG_SERIAL_ACPI
5954 + * Enable support for serial console port and serial
5955 + * debug port as defined by the SPCR and DBGP tables in
5956 + * ACPI 2.0.
5957 + */
5958 +
5959 +#include <linux/config.h>
5960 +#include <linux/version.h>
5961 +
5962 +#undef SERIAL_PARANOIA_CHECK
5963 +#define CONFIG_SERIAL_NOPAUSE_IO
5964 +#define SERIAL_DO_RESTART
5965 +
5966 +#if 0
5967 +/* These defines are normally controlled by the autoconf.h */
5968 +#define CONFIG_SERIAL_MANY_PORTS
5969 +#define CONFIG_SERIAL_SHARE_IRQ
5970 +#define CONFIG_SERIAL_DETECT_IRQ
5971 +#define CONFIG_SERIAL_MULTIPORT
5972 +#define CONFIG_HUB6
5973 +#endif
5974 +
5975 +#ifdef CONFIG_PCI
5976 +#define ENABLE_SERIAL_PCI
5977 +#ifndef CONFIG_SERIAL_SHARE_IRQ
5978 +#define CONFIG_SERIAL_SHARE_IRQ
5979 +#endif
5980 +#ifndef CONFIG_SERIAL_MANY_PORTS
5981 +#define CONFIG_SERIAL_MANY_PORTS
5982 +#endif
5983 +#endif
5984 +
5985 +#ifdef CONFIG_SERIAL_ACPI
5986 +#define ENABLE_SERIAL_ACPI
5987 +#endif
5988 +
5989 +#if defined(CONFIG_ISAPNP)|| (defined(CONFIG_ISAPNP_MODULE) && defined(MODULE))
5990 +#ifndef ENABLE_SERIAL_PNP
5991 +#define ENABLE_SERIAL_PNP
5992 +#endif
5993 +#endif
5994 +
5995 +/* Set of debugging defines */
5996 +
5997 +#undef SERIAL_DEBUG_INTR
5998 +#undef SERIAL_DEBUG_OPEN
5999 +#undef SERIAL_DEBUG_FLOW
6000 +#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
6001 +#undef SERIAL_DEBUG_PCI
6002 +#undef SERIAL_DEBUG_AUTOCONF
6003 +
6004 +/* Sanity checks */
6005 +
6006 +#ifdef CONFIG_SERIAL_MULTIPORT
6007 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6008 +#define CONFIG_SERIAL_SHARE_IRQ
6009 +#endif
6010 +#endif
6011 +
6012 +#ifdef CONFIG_HUB6
6013 +#ifndef CONFIG_SERIAL_MANY_PORTS
6014 +#define CONFIG_SERIAL_MANY_PORTS
6015 +#endif
6016 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6017 +#define CONFIG_SERIAL_SHARE_IRQ
6018 +#endif
6019 +#endif
6020 +
6021 +#ifdef MODULE
6022 +#undef CONFIG_SERIAL_CONSOLE
6023 +#endif
6024 +
6025 +#define CONFIG_SERIAL_RSA
6026 +
6027 +#define RS_STROBE_TIME (10*HZ)
6028 +#define RS_ISR_PASS_LIMIT 256
6029 +
6030 +#if defined(__i386__) && (defined(CONFIG_M386) || defined(CONFIG_M486))
6031 +#define SERIAL_INLINE
6032 +#endif
6033 +
6034 +/*
6035 + * End of serial driver configuration section.
6036 + */
6037 +
6038 +#include <linux/module.h>
6039 +
6040 +#include <linux/types.h>
6041 +#ifdef LOCAL_HEADERS
6042 +#include "serial_local.h"
6043 +#else
6044 +#include <linux/serial.h>
6045 +#include <linux/serialP.h>
6046 +#include <linux/serial_reg.h>
6047 +#include <asm/serial.h>
6048 +#define LOCAL_VERSTRING ""
6049 +#endif
6050 +
6051 +#include <linux/errno.h>
6052 +#include <linux/signal.h>
6053 +#include <linux/sched.h>
6054 +#include <linux/timer.h>
6055 +#include <linux/interrupt.h>
6056 +#include <linux/tty.h>
6057 +#include <linux/tty_flip.h>
6058 +#include <linux/major.h>
6059 +#include <linux/string.h>
6060 +#include <linux/fcntl.h>
6061 +#include <linux/ptrace.h>
6062 +#include <linux/ioport.h>
6063 +#include <linux/mm.h>
6064 +#include <linux/slab.h>
6065 +#if (LINUX_VERSION_CODE >= 131343)
6066 +#include <linux/init.h>
6067 +#endif
6068 +#if (LINUX_VERSION_CODE >= 131336)
6069 +#include <asm/uaccess.h>
6070 +#endif
6071 +#include <linux/delay.h>
6072 +#ifdef CONFIG_SERIAL_CONSOLE
6073 +#include <linux/console.h>
6074 +#endif
6075 +#ifdef ENABLE_SERIAL_PCI
6076 +#include <linux/pci.h>
6077 +#endif
6078 +#ifdef ENABLE_SERIAL_PNP
6079 +#include <linux/isapnp.h>
6080 +#endif
6081 +#ifdef CONFIG_MAGIC_SYSRQ
6082 +#include <linux/sysrq.h>
6083 +#endif
6084 +
6085 +/*
6086 + * All of the compatibilty code so we can compile serial.c against
6087 + * older kernels is hidden in serial_compat.h
6088 + */
6089 +#if defined(LOCAL_HEADERS) || (LINUX_VERSION_CODE < 0x020317) /* 2.3.23 */
6090 +#include "serial_compat.h"
6091 +#endif
6092 +
6093 +#include <asm/system.h>
6094 +#include <asm/io.h>
6095 +#include <asm/irq.h>
6096 +#include <asm/bitops.h>
6097 +
6098 +#if defined(CONFIG_MAC_SERIAL)
6099 +#define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2)
6100 +#else
6101 +#define SERIAL_DEV_OFFSET 0
6102 +#endif
6103 +
6104 +#ifdef SERIAL_INLINE
6105 +#define _INLINE_ inline
6106 +#else
6107 +#define _INLINE_
6108 +#endif
6109 +
6110 +static char *serial_name = "Serial driver";
6111 +
6112 +static DECLARE_TASK_QUEUE(tq_serial);
6113 +
6114 +static struct tty_driver serial_driver, callout_driver;
6115 +static int serial_refcount;
6116 +
6117 +static struct timer_list serial_timer;
6118 +
6119 +/* serial subtype definitions */
6120 +#ifndef SERIAL_TYPE_NORMAL
6121 +#define SERIAL_TYPE_NORMAL 1
6122 +#define SERIAL_TYPE_CALLOUT 2
6123 +#endif
6124 +
6125 +/* number of characters left in xmit buffer before we ask for more */
6126 +#define WAKEUP_CHARS 256
6127 +
6128 +/*
6129 + * IRQ_timeout - How long the timeout should be for each IRQ
6130 + * should be after the IRQ has been active.
6131 + */
6132 +
6133 +static struct async_struct *IRQ_ports[NR_IRQS];
6134 +#ifdef CONFIG_SERIAL_MULTIPORT
6135 +static struct rs_multiport_struct rs_multiport[NR_IRQS];
6136 +#endif
6137 +static int IRQ_timeout[NR_IRQS];
6138 +#ifdef CONFIG_SERIAL_CONSOLE
6139 +static struct console sercons;
6140 +static int lsr_break_flag;
6141 +#endif
6142 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6143 +static unsigned long break_pressed; /* break, really ... */
6144 +#endif
6145 +
6146 +static unsigned detect_uart_irq (struct serial_state * state);
6147 +static void autoconfig(struct serial_state * state);
6148 +static void change_speed(struct async_struct *info, struct termios *old);
6149 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
6150 +
6151 +/*
6152 + * Here we define the default xmit fifo size used for each type of
6153 + * UART
6154 + */
6155 +static struct serial_uart_config uart_config[] = {
6156 + { "unknown", 1, 0 },
6157 + { "8250", 1, 0 },
6158 + { "16450", 1, 0 },
6159 + { "16550", 1, 0 },
6160 + { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
6161 + { "cirrus", 1, 0 }, /* usurped by cyclades.c */
6162 + { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
6163 + { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO |
6164 + UART_STARTECH },
6165 + { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO},
6166 + { "Startech", 1, 0}, /* usurped by cyclades.c */
6167 + { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO},
6168 + { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO |
6169 + UART_STARTECH },
6170 + { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO |
6171 + UART_STARTECH },
6172 + { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO },
6173 + { 0, 0}
6174 +};
6175 +
6176 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
6177 +
6178 +#define PORT_RSA_MAX 4
6179 +static int probe_rsa[PORT_RSA_MAX];
6180 +static int force_rsa[PORT_RSA_MAX];
6181 +
6182 +MODULE_PARM(probe_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6183 +MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
6184 +MODULE_PARM(force_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6185 +MODULE_PARM_DESC(force_rsa, "Force I/O ports for RSA");
6186 +#endif /* CONFIG_SERIAL_RSA */
6187 +
6188 +struct serial_state rs_table[RS_TABLE_SIZE] = {
6189 + SERIAL_PORT_DFNS /* Defined in serial.h */
6190 +};
6191 +
6192 +#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state))
6193 +int serial_nr_ports = NR_PORTS;
6194 +
6195 +#if (defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP))
6196 +#define NR_PCI_BOARDS 8
6197 +
6198 +static struct pci_board_inst serial_pci_board[NR_PCI_BOARDS];
6199 +
6200 +#ifndef IS_PCI_REGION_IOPORT
6201 +#define IS_PCI_REGION_IOPORT(dev, r) (pci_resource_flags((dev), (r)) & \
6202 + IORESOURCE_IO)
6203 +#endif
6204 +#ifndef IS_PCI_REGION_IOMEM
6205 +#define IS_PCI_REGION_IOMEM(dev, r) (pci_resource_flags((dev), (r)) & \
6206 + IORESOURCE_MEM)
6207 +#endif
6208 +#ifndef PCI_IRQ_RESOURCE
6209 +#define PCI_IRQ_RESOURCE(dev, r) ((dev)->irq_resource[r].start)
6210 +#endif
6211 +#ifndef pci_get_subvendor
6212 +#define pci_get_subvendor(dev) ((dev)->subsystem_vendor)
6213 +#define pci_get_subdevice(dev) ((dev)->subsystem_device)
6214 +#endif
6215 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
6216 +
6217 +#ifndef PREPARE_FUNC
6218 +#define PREPARE_FUNC(dev) (dev->prepare)
6219 +#define ACTIVATE_FUNC(dev) (dev->activate)
6220 +#define DEACTIVATE_FUNC(dev) (dev->deactivate)
6221 +#endif
6222 +
6223 +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
6224 +
6225 +static struct tty_struct *serial_table[NR_PORTS];
6226 +static struct termios *serial_termios[NR_PORTS];
6227 +static struct termios *serial_termios_locked[NR_PORTS];
6228 +
6229 +
6230 +#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT)
6231 +#define DBG_CNT(s) printk("(%s): [%x] refc=%d, serc=%d, ttyc=%d -> %s\n", \
6232 + kdevname(tty->device), (info->flags), serial_refcount,info->count,tty->count,s)
6233 +#else
6234 +#define DBG_CNT(s)
6235 +#endif
6236 +
6237 +/*
6238 + * tmp_buf is used as a temporary buffer by serial_write. We need to
6239 + * lock it in case the copy_from_user blocks while swapping in a page,
6240 + * and some other program tries to do a serial write at the same time.
6241 + * Since the lock will only come under contention when the system is
6242 + * swapping and available memory is low, it makes sense to share one
6243 + * buffer across all the serial ports, since it significantly saves
6244 + * memory if large numbers of serial ports are open.
6245 + */
6246 +static unsigned char *tmp_buf;
6247 +#ifdef DECLARE_MUTEX
6248 +static DECLARE_MUTEX(tmp_buf_sem);
6249 +#else
6250 +static struct semaphore tmp_buf_sem = MUTEX;
6251 +#endif
6252 +
6253 +
6254 +static inline int serial_paranoia_check(struct async_struct *info,
6255 + kdev_t device, const char *routine)
6256 +{
6257 +#ifdef SERIAL_PARANOIA_CHECK
6258 + static const char *badmagic =
6259 + "Warning: bad magic number for serial struct (%s) in %s\n";
6260 + static const char *badinfo =
6261 + "Warning: null async_struct for (%s) in %s\n";
6262 +
6263 + if (!info) {
6264 + printk(badinfo, kdevname(device), routine);
6265 + return 1;
6266 + }
6267 + if (info->magic != SERIAL_MAGIC) {
6268 + printk(badmagic, kdevname(device), routine);
6269 + return 1;
6270 + }
6271 +#endif
6272 + return 0;
6273 +}
6274 +
6275 +#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
6276 +
6277 +#include <asm/mips-boards/atlas.h>
6278 +
6279 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6280 +{
6281 + return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff);
6282 +}
6283 +
6284 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
6285 +{
6286 + *(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value;
6287 +}
6288 +
6289 +#else
6290 +
6291 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6292 +{
6293 + switch (info->io_type) {
6294 +#ifdef CONFIG_HUB6
6295 + case SERIAL_IO_HUB6:
6296 + outb(info->hub6 - 1 + offset, info->port);
6297 + return inb(info->port+1);
6298 +#endif
6299 + case SERIAL_IO_MEM:
6300 + return readb((unsigned long) info->iomem_base +
6301 + (offset<<info->iomem_reg_shift));
6302 + default:
6303 + return inb(info->port + offset);
6304 + }
6305 +}
6306 +
6307 +static _INLINE_ void serial_out(struct async_struct *info, int offset,
6308 + int value)
6309 +{
6310 + switch (info->io_type) {
6311 +#ifdef CONFIG_HUB6
6312 + case SERIAL_IO_HUB6:
6313 + outb(info->hub6 - 1 + offset, info->port);
6314 + outb(value, info->port+1);
6315 + break;
6316 +#endif
6317 + case SERIAL_IO_MEM:
6318 + writeb(value, (unsigned long) info->iomem_base +
6319 + (offset<<info->iomem_reg_shift));
6320 + break;
6321 + default:
6322 + outb(value, info->port+offset);
6323 + }
6324 +}
6325 +#endif
6326 +
6327 +
6328 +/*
6329 + * We used to support using pause I/O for certain machines. We
6330 + * haven't supported this for a while, but just in case it's badly
6331 + * needed for certain old 386 machines, I've left these #define's
6332 + * in....
6333 + */
6334 +#define serial_inp(info, offset) serial_in(info, offset)
6335 +#define serial_outp(info, offset, value) serial_out(info, offset, value)
6336 +
6337 +
6338 +/*
6339 + * For the 16C950
6340 + */
6341 +void serial_icr_write(struct async_struct *info, int offset, int value)
6342 +{
6343 + serial_out(info, UART_SCR, offset);
6344 + serial_out(info, UART_ICR, value);
6345 +}
6346 +
6347 +unsigned int serial_icr_read(struct async_struct *info, int offset)
6348 +{
6349 + int value;
6350 +
6351 + serial_icr_write(info, UART_ACR, info->ACR | UART_ACR_ICRRD);
6352 + serial_out(info, UART_SCR, offset);
6353 + value = serial_in(info, UART_ICR);
6354 + serial_icr_write(info, UART_ACR, info->ACR);
6355 + return value;
6356 +}
6357 +
6358 +/*
6359 + * ------------------------------------------------------------
6360 + * rs_stop() and rs_start()
6361 + *
6362 + * This routines are called before setting or resetting tty->stopped.
6363 + * They enable or disable transmitter interrupts, as necessary.
6364 + * ------------------------------------------------------------
6365 + */
6366 +static void rs_stop(struct tty_struct *tty)
6367 +{
6368 + struct async_struct *info = (struct async_struct *)tty->driver_data;
6369 + unsigned long flags;
6370 +
6371 + if (serial_paranoia_check(info, tty->device, "rs_stop"))
6372 + return;
6373 +
6374 + save_flags(flags); cli();
6375 + if (info->IER & UART_IER_THRI) {
6376 + info->IER &= ~UART_IER_THRI;
6377 + serial_out(info, UART_IER, info->IER);
6378 + }
6379 + if (info->state->type == PORT_16C950) {
6380 + info->ACR |= UART_ACR_TXDIS;
6381 + serial_icr_write(info, UART_ACR, info->ACR);
6382 + }
6383 + restore_flags(flags);
6384 +}
6385 +
6386 +static void rs_start(struct tty_struct *tty)
6387 +{
6388 + struct async_struct *info = (struct async_struct *)tty->driver_data;
6389 + unsigned long flags;
6390 +
6391 + if (serial_paranoia_check(info, tty->device, "rs_start"))
6392 + return;
6393 +
6394 + save_flags(flags); cli();
6395 + if (info->xmit.head != info->xmit.tail
6396 + && info->xmit.buf
6397 + && !(info->IER & UART_IER_THRI)) {
6398 + info->IER |= UART_IER_THRI;
6399 + serial_out(info, UART_IER, info->IER);
6400 + }
6401 + if (info->state->type == PORT_16C950) {
6402 + info->ACR &= ~UART_ACR_TXDIS;
6403 + serial_icr_write(info, UART_ACR, info->ACR);
6404 + }
6405 + restore_flags(flags);
6406 +}
6407 +
6408 +/*
6409 + * ----------------------------------------------------------------------
6410 + *
6411 + * Here starts the interrupt handling routines. All of the following
6412 + * subroutines are declared as inline and are folded into
6413 + * rs_interrupt(). They were separated out for readability's sake.
6414 + *
6415 + * Note: rs_interrupt() is a "fast" interrupt, which means that it
6416 + * runs with interrupts turned off. People who may want to modify
6417 + * rs_interrupt() should try to keep the interrupt handler as fast as
6418 + * possible. After you are done making modifications, it is not a bad
6419 + * idea to do:
6420 + *
6421 + * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
6422 + *
6423 + * and look at the resulting assemble code in serial.s.
6424 + *
6425 + * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
6426 + * -----------------------------------------------------------------------
6427 + */
6428 +
6429 +/*
6430 + * This routine is used by the interrupt handler to schedule
6431 + * processing in the software interrupt portion of the driver.
6432 + */
6433 +static _INLINE_ void rs_sched_event(struct async_struct *info,
6434 + int event)
6435 +{
6436 + info->event |= 1 << event;
6437 + queue_task(&info->tqueue, &tq_serial);
6438 + mark_bh(SERIAL_BH);
6439 +}
6440 +
6441 +static _INLINE_ void receive_chars(struct async_struct *info,
6442 + int *status, struct pt_regs * regs)
6443 +{
6444 + struct tty_struct *tty = info->tty;
6445 + unsigned char ch;
6446 + struct async_icount *icount;
6447 + int max_count = 256;
6448 +
6449 + icount = &info->state->icount;
6450 + do {
6451 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
6452 + tty->flip.tqueue.routine((void *) tty);
6453 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
6454 + /* no room in flip buffer, discard rx FIFO contents to clear IRQ
6455 + * *FIXME* Hardware with auto flow control
6456 + * would benefit from leaving the data in the FIFO and
6457 + * disabling the rx IRQ until space becomes available.
6458 + */
6459 + do {
6460 + serial_inp(info, UART_RX);
6461 + icount->overrun++;
6462 + *status = serial_inp(info, UART_LSR);
6463 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
6464 + return; // if TTY_DONT_FLIP is set
6465 + }
6466 + }
6467 + ch = serial_inp(info, UART_RX);
6468 + *tty->flip.char_buf_ptr = ch;
6469 + icount->rx++;
6470 +
6471 +#ifdef SERIAL_DEBUG_INTR
6472 + printk("DR%02x:%02x...", ch, *status);
6473 +#endif
6474 + *tty->flip.flag_buf_ptr = 0;
6475 + if (*status & (UART_LSR_BI | UART_LSR_PE |
6476 + UART_LSR_FE | UART_LSR_OE)) {
6477 + /*
6478 + * For statistics only
6479 + */
6480 + if (*status & UART_LSR_BI) {
6481 + *status &= ~(UART_LSR_FE | UART_LSR_PE);
6482 + icount->brk++;
6483 + /*
6484 + * We do the SysRQ and SAK checking
6485 + * here because otherwise the break
6486 + * may get masked by ignore_status_mask
6487 + * or read_status_mask.
6488 + */
6489 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6490 + if (info->line == sercons.index) {
6491 + if (!break_pressed) {
6492 + break_pressed = jiffies;
6493 + goto ignore_char;
6494 + }
6495 + break_pressed = 0;
6496 + }
6497 +#endif
6498 + if (info->flags & ASYNC_SAK)
6499 + do_SAK(tty);
6500 + } else if (*status & UART_LSR_PE)
6501 + icount->parity++;
6502 + else if (*status & UART_LSR_FE)
6503 + icount->frame++;
6504 + if (*status & UART_LSR_OE)
6505 + icount->overrun++;
6506 +
6507 + /*
6508 + * Mask off conditions which should be ignored.
6509 + */
6510 + *status &= info->read_status_mask;
6511 +
6512 +#ifdef CONFIG_SERIAL_CONSOLE
6513 + if (info->line == sercons.index) {
6514 + /* Recover the break flag from console xmit */
6515 + *status |= lsr_break_flag;
6516 + lsr_break_flag = 0;
6517 + }
6518 +#endif
6519 + if (*status & (UART_LSR_BI)) {
6520 +#ifdef SERIAL_DEBUG_INTR
6521 + printk("handling break....");
6522 +#endif
6523 + *tty->flip.flag_buf_ptr = TTY_BREAK;
6524 + } else if (*status & UART_LSR_PE)
6525 + *tty->flip.flag_buf_ptr = TTY_PARITY;
6526 + else if (*status & UART_LSR_FE)
6527 + *tty->flip.flag_buf_ptr = TTY_FRAME;
6528 + }
6529 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6530 + if (break_pressed && info->line == sercons.index) {
6531 + if (ch != 0 &&
6532 + time_before(jiffies, break_pressed + HZ*5)) {
6533 + handle_sysrq(ch, regs, NULL, NULL);
6534 + break_pressed = 0;
6535 + goto ignore_char;
6536 + }
6537 + break_pressed = 0;
6538 + }
6539 +#endif
6540 + if ((*status & info->ignore_status_mask) == 0) {
6541 + tty->flip.flag_buf_ptr++;
6542 + tty->flip.char_buf_ptr++;
6543 + tty->flip.count++;
6544 + }
6545 + if ((*status & UART_LSR_OE) &&
6546 + (tty->flip.count < TTY_FLIPBUF_SIZE)) {
6547 + /*
6548 + * Overrun is special, since it's reported
6549 + * immediately, and doesn't affect the current
6550 + * character
6551 + */
6552 + *tty->flip.flag_buf_ptr = TTY_OVERRUN;
6553 + tty->flip.count++;
6554 + tty->flip.flag_buf_ptr++;
6555 + tty->flip.char_buf_ptr++;
6556 + }
6557 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6558 + ignore_char:
6559 +#endif
6560 + *status = serial_inp(info, UART_LSR);
6561 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
6562 +#if (LINUX_VERSION_CODE > 131394) /* 2.1.66 */
6563 + tty_flip_buffer_push(tty);
6564 +#else
6565 + queue_task_irq_off(&tty->flip.tqueue, &tq_timer);
6566 +#endif
6567 +}
6568 +
6569 +static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done)
6570 +{
6571 + int count;
6572 +
6573 + if (info->x_char) {
6574 + serial_outp(info, UART_TX, info->x_char);
6575 + info->state->icount.tx++;
6576 + info->x_char = 0;
6577 + if (intr_done)
6578 + *intr_done = 0;
6579 + return;
6580 + }
6581 + if (info->xmit.head == info->xmit.tail
6582 + || info->tty->stopped
6583 + || info->tty->hw_stopped) {
6584 + info->IER &= ~UART_IER_THRI;
6585 + serial_out(info, UART_IER, info->IER);
6586 + return;
6587 + }
6588 +
6589 + count = info->xmit_fifo_size;
6590 + do {
6591 + serial_out(info, UART_TX, info->xmit.buf[info->xmit.tail]);
6592 + info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
6593 + info->state->icount.tx++;
6594 + if (info->xmit.head == info->xmit.tail)
6595 + break;
6596 + } while (--count > 0);
6597 +
6598 + if (CIRC_CNT(info->xmit.head,
6599 + info->xmit.tail,
6600 + SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
6601 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
6602 +
6603 +#ifdef SERIAL_DEBUG_INTR
6604 + printk("THRE...");
6605 +#endif
6606 + if (intr_done)
6607 + *intr_done = 0;
6608 +
6609 + if (info->xmit.head == info->xmit.tail) {
6610 + info->IER &= ~UART_IER_THRI;
6611 + serial_out(info, UART_IER, info->IER);
6612 + }
6613 +}
6614 +
6615 +static _INLINE_ void check_modem_status(struct async_struct *info)
6616 +{
6617 + int status;
6618 + struct async_icount *icount;
6619 +
6620 + status = serial_in(info, UART_MSR);
6621 +
6622 + if (status & UART_MSR_ANY_DELTA) {
6623 + icount = &info->state->icount;
6624 + /* update input line counters */
6625 + if (status & UART_MSR_TERI)
6626 + icount->rng++;
6627 + if (status & UART_MSR_DDSR)
6628 + icount->dsr++;
6629 + if (status & UART_MSR_DDCD) {
6630 + icount->dcd++;
6631 +#ifdef CONFIG_HARD_PPS
6632 + if ((info->flags & ASYNC_HARDPPS_CD) &&
6633 + (status & UART_MSR_DCD))
6634 + hardpps();
6635 +#endif
6636 + }
6637 + if (status & UART_MSR_DCTS)
6638 + icount->cts++;
6639 + wake_up_interruptible(&info->delta_msr_wait);
6640 + }
6641 +
6642 + if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
6643 +#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
6644 + printk("ttys%d CD now %s...", info->line,
6645 + (status & UART_MSR_DCD) ? "on" : "off");
6646 +#endif
6647 + if (status & UART_MSR_DCD)
6648 + wake_up_interruptible(&info->open_wait);
6649 + else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
6650 + (info->flags & ASYNC_CALLOUT_NOHUP))) {
6651 +#ifdef SERIAL_DEBUG_OPEN
6652 + printk("doing serial hangup...");
6653 +#endif
6654 + if (info->tty)
6655 + tty_hangup(info->tty);
6656 + }
6657 + }
6658 + if (info->flags & ASYNC_CTS_FLOW) {
6659 + if (info->tty->hw_stopped) {
6660 + if (status & UART_MSR_CTS) {
6661 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
6662 + printk("CTS tx start...");
6663 +#endif
6664 + info->tty->hw_stopped = 0;
6665 + info->IER |= UART_IER_THRI;
6666 + serial_out(info, UART_IER, info->IER);
6667 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
6668 + return;
6669 + }
6670 + } else {
6671 + if (!(status & UART_MSR_CTS)) {
6672 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
6673 + printk("CTS tx stop...");
6674 +#endif
6675 + info->tty->hw_stopped = 1;
6676 + info->IER &= ~UART_IER_THRI;
6677 + serial_out(info, UART_IER, info->IER);
6678 + }
6679 + }
6680 + }
6681 +}
6682 +
6683 +#ifdef CONFIG_SERIAL_SHARE_IRQ
6684 +/*
6685 + * This is the serial driver's generic interrupt routine
6686 + */
6687 +static void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs)
6688 +{
6689 + int status, iir;
6690 + struct async_struct * info;
6691 + int pass_counter = 0;
6692 + struct async_struct *end_mark = 0;
6693 +#ifdef CONFIG_SERIAL_MULTIPORT
6694 + int first_multi = 0;
6695 + struct rs_multiport_struct *multi;
6696 +#endif
6697 +
6698 +#ifdef SERIAL_DEBUG_INTR
6699 + printk("rs_interrupt(%d)...", irq);
6700 +#endif
6701 +
6702 + info = IRQ_ports[irq];
6703 + if (!info)
6704 + return;
6705 +
6706 +#ifdef CONFIG_SERIAL_MULTIPORT
6707 + multi = &rs_multiport[irq];
6708 + if (multi->port_monitor)
6709 + first_multi = inb(multi->port_monitor);
6710 +#endif
6711 +
6712 + do {
6713 + if (!info->tty ||
6714 + ((iir=serial_in(info, UART_IIR)) & UART_IIR_NO_INT)) {
6715 + if (!end_mark)
6716 + end_mark = info;
6717 + goto next;
6718 + }
6719 +#ifdef SERIAL_DEBUG_INTR
6720 + printk("IIR = %x...", serial_in(info, UART_IIR));
6721 +#endif
6722 + end_mark = 0;
6723 +
6724 + info->last_active = jiffies;
6725 +
6726 + status = serial_inp(info, UART_LSR);
6727 +#ifdef SERIAL_DEBUG_INTR
6728 + printk("status = %x...", status);
6729 +#endif
6730 + if (status & UART_LSR_DR)
6731 + receive_chars(info, &status, regs);
6732 + check_modem_status(info);
6733 +#ifdef CONFIG_MELAN
6734 + if ((status & UART_LSR_THRE) ||
6735 + /* for buggy ELAN processors */
6736 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
6737 + transmit_chars(info, 0);
6738 +#else
6739 + if (status & UART_LSR_THRE)
6740 + transmit_chars(info, 0);
6741 +#endif
6742 +
6743 + next:
6744 + info = info->next_port;
6745 + if (!info) {
6746 + info = IRQ_ports[irq];
6747 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6748 +#if 0
6749 + printk("rs loop break\n");
6750 +#endif
6751 + break; /* Prevent infinite loops */
6752 + }
6753 + continue;
6754 + }
6755 + } while (end_mark != info);
6756 +#ifdef CONFIG_SERIAL_MULTIPORT
6757 + if (multi->port_monitor)
6758 + printk("rs port monitor (normal) irq %d: 0x%x, 0x%x\n",
6759 + info->state->irq, first_multi,
6760 + inb(multi->port_monitor));
6761 +#endif
6762 +#ifdef SERIAL_DEBUG_INTR
6763 + printk("end.\n");
6764 +#endif
6765 +}
6766 +#endif /* #ifdef CONFIG_SERIAL_SHARE_IRQ */
6767 +
6768 +
6769 +/*
6770 + * This is the serial driver's interrupt routine for a single port
6771 + */
6772 +static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs)
6773 +{
6774 + int status, iir;
6775 + int pass_counter = 0;
6776 + struct async_struct * info;
6777 +#ifdef CONFIG_SERIAL_MULTIPORT
6778 + int first_multi = 0;
6779 + struct rs_multiport_struct *multi;
6780 +#endif
6781 +
6782 +#ifdef SERIAL_DEBUG_INTR
6783 + printk("rs_interrupt_single(%d)...", irq);
6784 +#endif
6785 +
6786 + info = IRQ_ports[irq];
6787 + if (!info || !info->tty)
6788 + return;
6789 +
6790 +#ifdef CONFIG_SERIAL_MULTIPORT
6791 + multi = &rs_multiport[irq];
6792 + if (multi->port_monitor)
6793 + first_multi = inb(multi->port_monitor);
6794 +#endif
6795 +
6796 + iir = serial_in(info, UART_IIR);
6797 + do {
6798 + status = serial_inp(info, UART_LSR);
6799 +#ifdef SERIAL_DEBUG_INTR
6800 + printk("status = %x...", status);
6801 +#endif
6802 + if (status & UART_LSR_DR)
6803 + receive_chars(info, &status, regs);
6804 + check_modem_status(info);
6805 +#ifdef CONFIG_MELAN
6806 + if ((status & UART_LSR_THRE) ||
6807 + /* For buggy ELAN processors */
6808 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
6809 + transmit_chars(info, 0);
6810 +#else
6811 + if (status & UART_LSR_THRE)
6812 + transmit_chars(info, 0);
6813 +#endif
6814 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6815 +#if SERIAL_DEBUG_INTR
6816 + printk("rs_single loop break.\n");
6817 +#endif
6818 + break;
6819 + }
6820 + iir = serial_in(info, UART_IIR);
6821 +#ifdef SERIAL_DEBUG_INTR
6822 + printk("IIR = %x...", iir);
6823 +#endif
6824 + } while ((iir & UART_IIR_NO_INT) == 0);
6825 + info->last_active = jiffies;
6826 +#ifdef CONFIG_SERIAL_MULTIPORT
6827 + if (multi->port_monitor)
6828 + printk("rs port monitor (single) irq %d: 0x%x, 0x%x\n",
6829 + info->state->irq, first_multi,
6830 + inb(multi->port_monitor));
6831 +#endif
6832 +#ifdef SERIAL_DEBUG_INTR
6833 + printk("end.\n");
6834 +#endif
6835 +}
6836 +
6837 +#ifdef CONFIG_SERIAL_MULTIPORT
6838 +/*
6839 + * This is the serial driver's for multiport boards
6840 + */
6841 +static void rs_interrupt_multi(int irq, void *dev_id, struct pt_regs * regs)
6842 +{
6843 + int status;
6844 + struct async_struct * info;
6845 + int pass_counter = 0;
6846 + int first_multi= 0;
6847 + struct rs_multiport_struct *multi;
6848 +
6849 +#ifdef SERIAL_DEBUG_INTR
6850 + printk("rs_interrupt_multi(%d)...", irq);
6851 +#endif
6852 +
6853 + info = IRQ_ports[irq];
6854 + if (!info)
6855 + return;
6856 + multi = &rs_multiport[irq];
6857 + if (!multi->port1) {
6858 + /* Should never happen */
6859 + printk("rs_interrupt_multi: NULL port1!\n");
6860 + return;
6861 + }
6862 + if (multi->port_monitor)
6863 + first_multi = inb(multi->port_monitor);
6864 +
6865 + while (1) {
6866 + if (!info->tty ||
6867 + (serial_in(info, UART_IIR) & UART_IIR_NO_INT))
6868 + goto next;
6869 +
6870 + info->last_active = jiffies;
6871 +
6872 + status = serial_inp(info, UART_LSR);
6873 +#ifdef SERIAL_DEBUG_INTR
6874 + printk("status = %x...", status);
6875 +#endif
6876 + if (status & UART_LSR_DR)
6877 + receive_chars(info, &status, regs);
6878 + check_modem_status(info);
6879 + if (status & UART_LSR_THRE)
6880 + transmit_chars(info, 0);
6881 +
6882 + next:
6883 + info = info->next_port;
6884 + if (info)
6885 + continue;
6886 +
6887 + info = IRQ_ports[irq];
6888 + /*
6889 + * The user was a bonehead, and misconfigured their
6890 + * multiport info. Rather than lock up the kernel
6891 + * in an infinite loop, if we loop too many times,
6892 + * print a message and break out of the loop.
6893 + */
6894 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6895 + printk("Misconfigured multiport serial info "
6896 + "for irq %d. Breaking out irq loop\n", irq);
6897 + break;
6898 + }
6899 + if (multi->port_monitor)
6900 + printk("rs port monitor irq %d: 0x%x, 0x%x\n",
6901 + info->state->irq, first_multi,
6902 + inb(multi->port_monitor));
6903 + if ((inb(multi->port1) & multi->mask1) != multi->match1)
6904 + continue;
6905 + if (!multi->port2)
6906 + break;
6907 + if ((inb(multi->port2) & multi->mask2) != multi->match2)
6908 + continue;
6909 + if (!multi->port3)
6910 + break;
6911 + if ((inb(multi->port3) & multi->mask3) != multi->match3)
6912 + continue;
6913 + if (!multi->port4)
6914 + break;
6915 + if ((inb(multi->port4) & multi->mask4) != multi->match4)
6916 + continue;
6917 + break;
6918 + }
6919 +#ifdef SERIAL_DEBUG_INTR
6920 + printk("end.\n");
6921 +#endif
6922 +}
6923 +#endif
6924 +
6925 +/*
6926 + * -------------------------------------------------------------------
6927 + * Here ends the serial interrupt routines.
6928 + * -------------------------------------------------------------------
6929 + */
6930 +
6931 +/*
6932 + * This routine is used to handle the "bottom half" processing for the
6933 + * serial driver, known also the "software interrupt" processing.
6934 + * This processing is done at the kernel interrupt level, after the
6935 + * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
6936 + * is where time-consuming activities which can not be done in the
6937 + * interrupt driver proper are done; the interrupt driver schedules
6938 + * them using rs_sched_event(), and they get done here.
6939 + */
6940 +static void do_serial_bh(void)
6941 +{
6942 + run_task_queue(&tq_serial);
6943 +}
6944 +
6945 +static void do_softint(void *private_)
6946 +{
6947 + struct async_struct *info = (struct async_struct *) private_;
6948 + struct tty_struct *tty;
6949 +
6950 + tty = info->tty;
6951 + if (!tty)
6952 + return;
6953 +
6954 + if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) {
6955 + tty_wakeup(tty);
6956 +
6957 +#ifdef SERIAL_HAVE_POLL_WAIT
6958 + wake_up_interruptible(&tty->poll_wait);
6959 +#endif
6960 + }
6961 +}
6962 +
6963 +/*
6964 + * This subroutine is called when the RS_TIMER goes off. It is used
6965 + * by the serial driver to handle ports that do not have an interrupt
6966 + * (irq=0). This doesn't work very well for 16450's, but gives barely
6967 + * passable results for a 16550A. (Although at the expense of much
6968 + * CPU overhead).
6969 + */
6970 +static void rs_timer(unsigned long dummy)
6971 +{
6972 + static unsigned long last_strobe;
6973 + struct async_struct *info;
6974 + unsigned int i;
6975 + unsigned long flags;
6976 +
6977 + if ((jiffies - last_strobe) >= RS_STROBE_TIME) {
6978 + for (i=0; i < NR_IRQS; i++) {
6979 + info = IRQ_ports[i];
6980 + if (!info)
6981 + continue;
6982 + save_flags(flags); cli();
6983 +#ifdef CONFIG_SERIAL_SHARE_IRQ
6984 + if (info->next_port) {
6985 + do {
6986 + serial_out(info, UART_IER, 0);
6987 + info->IER |= UART_IER_THRI;
6988 + serial_out(info, UART_IER, info->IER);
6989 + info = info->next_port;
6990 + } while (info);
6991 +#ifdef CONFIG_SERIAL_MULTIPORT
6992 + if (rs_multiport[i].port1)
6993 + rs_interrupt_multi(i, NULL, NULL);
6994 + else
6995 +#endif
6996 + rs_interrupt(i, NULL, NULL);
6997 + } else
6998 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
6999 + rs_interrupt_single(i, NULL, NULL);
7000 + restore_flags(flags);
7001 + }
7002 + }
7003 + last_strobe = jiffies;
7004 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
7005 +
7006 + if (IRQ_ports[0]) {
7007 + save_flags(flags); cli();
7008 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7009 + rs_interrupt(0, NULL, NULL);
7010 +#else
7011 + rs_interrupt_single(0, NULL, NULL);
7012 +#endif
7013 + restore_flags(flags);
7014 +
7015 + mod_timer(&serial_timer, jiffies + IRQ_timeout[0]);
7016 + }
7017 +}
7018 +
7019 +/*
7020 + * ---------------------------------------------------------------
7021 + * Low level utility subroutines for the serial driver: routines to
7022 + * figure out the appropriate timeout for an interrupt chain, routines
7023 + * to initialize and startup a serial port, and routines to shutdown a
7024 + * serial port. Useful stuff like that.
7025 + * ---------------------------------------------------------------
7026 + */
7027 +
7028 +/*
7029 + * This routine figures out the correct timeout for a particular IRQ.
7030 + * It uses the smallest timeout of all of the serial ports in a
7031 + * particular interrupt chain. Now only used for IRQ 0....
7032 + */
7033 +static void figure_IRQ_timeout(int irq)
7034 +{
7035 + struct async_struct *info;
7036 + int timeout = 60*HZ; /* 60 seconds === a long time :-) */
7037 +
7038 + info = IRQ_ports[irq];
7039 + if (!info) {
7040 + IRQ_timeout[irq] = 60*HZ;
7041 + return;
7042 + }
7043 + while (info) {
7044 + if (info->timeout < timeout)
7045 + timeout = info->timeout;
7046 + info = info->next_port;
7047 + }
7048 + if (!irq)
7049 + timeout = timeout / 2;
7050 + IRQ_timeout[irq] = (timeout > 3) ? timeout-2 : 1;
7051 +}
7052 +
7053 +#ifdef CONFIG_SERIAL_RSA
7054 +/* Attempts to turn on the RSA FIFO. Returns zero on failure */
7055 +static int enable_rsa(struct async_struct *info)
7056 +{
7057 + unsigned char mode;
7058 + int result;
7059 + unsigned long flags;
7060 +
7061 + save_flags(flags); cli();
7062 + mode = serial_inp(info, UART_RSA_MSR);
7063 + result = mode & UART_RSA_MSR_FIFO;
7064 +
7065 + if (!result) {
7066 + serial_outp(info, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
7067 + mode = serial_inp(info, UART_RSA_MSR);
7068 + result = mode & UART_RSA_MSR_FIFO;
7069 + }
7070 +
7071 + restore_flags(flags);
7072 + return result;
7073 +}
7074 +
7075 +/* Attempts to turn off the RSA FIFO. Returns zero on failure */
7076 +static int disable_rsa(struct async_struct *info)
7077 +{
7078 + unsigned char mode;
7079 + int result;
7080 + unsigned long flags;
7081 +
7082 + save_flags(flags); cli();
7083 + mode = serial_inp(info, UART_RSA_MSR);
7084 + result = !(mode & UART_RSA_MSR_FIFO);
7085 +
7086 + if (!result) {
7087 + serial_outp(info, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
7088 + mode = serial_inp(info, UART_RSA_MSR);
7089 + result = !(mode & UART_RSA_MSR_FIFO);
7090 + }
7091 +
7092 + restore_flags(flags);
7093 + return result;
7094 +}
7095 +#endif /* CONFIG_SERIAL_RSA */
7096 +
7097 +static int startup(struct async_struct * info)
7098 +{
7099 + unsigned long flags;
7100 + int retval=0;
7101 + void (*handler)(int, void *, struct pt_regs *);
7102 + struct serial_state *state= info->state;
7103 + unsigned long page;
7104 +#ifdef CONFIG_SERIAL_MANY_PORTS
7105 + unsigned short ICP;
7106 +#endif
7107 +
7108 + page = get_zeroed_page(GFP_KERNEL);
7109 + if (!page)
7110 + return -ENOMEM;
7111 +
7112 + save_flags(flags); cli();
7113 +
7114 + if (info->flags & ASYNC_INITIALIZED) {
7115 + free_page(page);
7116 + goto errout;
7117 + }
7118 +
7119 + if (!CONFIGURED_SERIAL_PORT(state) || !state->type) {
7120 + if (info->tty)
7121 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7122 + free_page(page);
7123 + goto errout;
7124 + }
7125 + if (info->xmit.buf)
7126 + free_page(page);
7127 + else
7128 + info->xmit.buf = (unsigned char *) page;
7129 +
7130 +#ifdef SERIAL_DEBUG_OPEN
7131 + printk("starting up ttys%d (irq %d)...", info->line, state->irq);
7132 +#endif
7133 +
7134 + if (uart_config[state->type].flags & UART_STARTECH) {
7135 + /* Wake up UART */
7136 + serial_outp(info, UART_LCR, 0xBF);
7137 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7138 + /*
7139 + * Turn off LCR == 0xBF so we actually set the IER
7140 + * register on the XR16C850
7141 + */
7142 + serial_outp(info, UART_LCR, 0);
7143 + serial_outp(info, UART_IER, 0);
7144 + /*
7145 + * Now reset LCR so we can turn off the ECB bit
7146 + */
7147 + serial_outp(info, UART_LCR, 0xBF);
7148 + serial_outp(info, UART_EFR, 0);
7149 + /*
7150 + * For a XR16C850, we need to set the trigger levels
7151 + */
7152 + if (state->type == PORT_16850) {
7153 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7154 + UART_FCTR_RX);
7155 + serial_outp(info, UART_TRG, UART_TRG_96);
7156 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7157 + UART_FCTR_TX);
7158 + serial_outp(info, UART_TRG, UART_TRG_96);
7159 + }
7160 + serial_outp(info, UART_LCR, 0);
7161 + }
7162 +
7163 + if (state->type == PORT_16750) {
7164 + /* Wake up UART */
7165 + serial_outp(info, UART_IER, 0);
7166 + }
7167 +
7168 + if (state->type == PORT_16C950) {
7169 + /* Wake up and initialize UART */
7170 + info->ACR = 0;
7171 + serial_outp(info, UART_LCR, 0xBF);
7172 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7173 + serial_outp(info, UART_IER, 0);
7174 + serial_outp(info, UART_LCR, 0);
7175 + serial_icr_write(info, UART_CSR, 0); /* Reset the UART */
7176 + serial_outp(info, UART_LCR, 0xBF);
7177 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7178 + serial_outp(info, UART_LCR, 0);
7179 + }
7180 +
7181 +#ifdef CONFIG_SERIAL_RSA
7182 + /*
7183 + * If this is an RSA port, see if we can kick it up to the
7184 + * higher speed clock.
7185 + */
7186 + if (state->type == PORT_RSA) {
7187 + if (state->baud_base != SERIAL_RSA_BAUD_BASE &&
7188 + enable_rsa(info))
7189 + state->baud_base = SERIAL_RSA_BAUD_BASE;
7190 + if (state->baud_base == SERIAL_RSA_BAUD_BASE)
7191 + serial_outp(info, UART_RSA_FRR, 0);
7192 + }
7193 +#endif
7194 +
7195 + /*
7196 + * Clear the FIFO buffers and disable them
7197 + * (they will be reenabled in change_speed())
7198 + */
7199 + if (uart_config[state->type].flags & UART_CLEAR_FIFO) {
7200 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
7201 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
7202 + UART_FCR_CLEAR_RCVR |
7203 + UART_FCR_CLEAR_XMIT));
7204 + serial_outp(info, UART_FCR, 0);
7205 + }
7206 +
7207 + /*
7208 + * Clear the interrupt registers.
7209 + */
7210 + (void) serial_inp(info, UART_LSR);
7211 + (void) serial_inp(info, UART_RX);
7212 + (void) serial_inp(info, UART_IIR);
7213 + (void) serial_inp(info, UART_MSR);
7214 +
7215 + /*
7216 + * At this point there's no way the LSR could still be 0xFF;
7217 + * if it is, then bail out, because there's likely no UART
7218 + * here.
7219 + */
7220 + if (!(info->flags & ASYNC_BUGGY_UART) &&
7221 + (serial_inp(info, UART_LSR) == 0xff)) {
7222 + printk("ttyS%d: LSR safety check engaged!\n", state->line);
7223 + if (capable(CAP_SYS_ADMIN)) {
7224 + if (info->tty)
7225 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7226 + } else
7227 + retval = -ENODEV;
7228 + goto errout;
7229 + }
7230 +
7231 + /*
7232 + * Allocate the IRQ if necessary
7233 + */
7234 + if (state->irq && (!IRQ_ports[state->irq] ||
7235 + !IRQ_ports[state->irq]->next_port)) {
7236 + if (IRQ_ports[state->irq]) {
7237 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7238 + free_irq(state->irq, &IRQ_ports[state->irq]);
7239 +#ifdef CONFIG_SERIAL_MULTIPORT
7240 + if (rs_multiport[state->irq].port1)
7241 + handler = rs_interrupt_multi;
7242 + else
7243 +#endif
7244 + handler = rs_interrupt;
7245 +#else
7246 + retval = -EBUSY;
7247 + goto errout;
7248 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
7249 + } else
7250 + handler = rs_interrupt_single;
7251 +
7252 + retval = request_irq(state->irq, handler, SA_SHIRQ,
7253 + "serial", &IRQ_ports[state->irq]);
7254 + if (retval) {
7255 + if (capable(CAP_SYS_ADMIN)) {
7256 + if (info->tty)
7257 + set_bit(TTY_IO_ERROR,
7258 + &info->tty->flags);
7259 + retval = 0;
7260 + }
7261 + goto errout;
7262 + }
7263 + }
7264 +
7265 + /*
7266 + * Insert serial port into IRQ chain.
7267 + */
7268 + info->prev_port = 0;
7269 + info->next_port = IRQ_ports[state->irq];
7270 + if (info->next_port)
7271 + info->next_port->prev_port = info;
7272 + IRQ_ports[state->irq] = info;
7273 + figure_IRQ_timeout(state->irq);
7274 +
7275 + /*
7276 + * Now, initialize the UART
7277 + */
7278 + serial_outp(info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
7279 +
7280 + info->MCR = 0;
7281 + if (info->tty->termios->c_cflag & CBAUD)
7282 + info->MCR = UART_MCR_DTR | UART_MCR_RTS;
7283 +#ifdef CONFIG_SERIAL_MANY_PORTS
7284 + if (info->flags & ASYNC_FOURPORT) {
7285 + if (state->irq == 0)
7286 + info->MCR |= UART_MCR_OUT1;
7287 + } else
7288 +#endif
7289 + {
7290 + if (state->irq != 0)
7291 + info->MCR |= UART_MCR_OUT2;
7292 + }
7293 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
7294 + serial_outp(info, UART_MCR, info->MCR);
7295 +
7296 + /*
7297 + * Finally, enable interrupts
7298 + */
7299 + info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
7300 + serial_outp(info, UART_IER, info->IER); /* enable interrupts */
7301 +
7302 +#ifdef CONFIG_SERIAL_MANY_PORTS
7303 + if (info->flags & ASYNC_FOURPORT) {
7304 + /* Enable interrupts on the AST Fourport board */
7305 + ICP = (info->port & 0xFE0) | 0x01F;
7306 + outb_p(0x80, ICP);
7307 + (void) inb_p(ICP);
7308 + }
7309 +#endif
7310 +
7311 + /*
7312 + * And clear the interrupt registers again for luck.
7313 + */
7314 + (void)serial_inp(info, UART_LSR);
7315 + (void)serial_inp(info, UART_RX);
7316 + (void)serial_inp(info, UART_IIR);
7317 + (void)serial_inp(info, UART_MSR);
7318 +
7319 + if (info->tty)
7320 + clear_bit(TTY_IO_ERROR, &info->tty->flags);
7321 + info->xmit.head = info->xmit.tail = 0;
7322 +
7323 + /*
7324 + * Set up serial timers...
7325 + */
7326 + mod_timer(&serial_timer, jiffies + 2*HZ/100);
7327 +
7328 + /*
7329 + * Set up the tty->alt_speed kludge
7330 + */
7331 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
7332 + if (info->tty) {
7333 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
7334 + info->tty->alt_speed = 57600;
7335 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
7336 + info->tty->alt_speed = 115200;
7337 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
7338 + info->tty->alt_speed = 230400;
7339 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
7340 + info->tty->alt_speed = 460800;
7341 + }
7342 +#endif
7343 +
7344 + /*
7345 + * and set the speed of the serial port
7346 + */
7347 + change_speed(info, 0);
7348 +
7349 + info->flags |= ASYNC_INITIALIZED;
7350 + restore_flags(flags);
7351 + return 0;
7352 +
7353 +errout:
7354 + restore_flags(flags);
7355 + return retval;
7356 +}
7357 +
7358 +/*
7359 + * This routine will shutdown a serial port; interrupts are disabled, and
7360 + * DTR is dropped if the hangup on close termio flag is on.
7361 + */
7362 +static void shutdown(struct async_struct * info)
7363 +{
7364 + unsigned long flags;
7365 + struct serial_state *state;
7366 + int retval;
7367 +
7368 + if (!(info->flags & ASYNC_INITIALIZED))
7369 + return;
7370 +
7371 + state = info->state;
7372 +
7373 +#ifdef SERIAL_DEBUG_OPEN
7374 + printk("Shutting down serial port %d (irq %d)....", info->line,
7375 + state->irq);
7376 +#endif
7377 +
7378 + save_flags(flags); cli(); /* Disable interrupts */
7379 +
7380 + /*
7381 + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
7382 + * here so the queue might never be waken up
7383 + */
7384 + wake_up_interruptible(&info->delta_msr_wait);
7385 +
7386 + /*
7387 + * First unlink the serial port from the IRQ chain...
7388 + */
7389 + if (info->next_port)
7390 + info->next_port->prev_port = info->prev_port;
7391 + if (info->prev_port)
7392 + info->prev_port->next_port = info->next_port;
7393 + else
7394 + IRQ_ports[state->irq] = info->next_port;
7395 + figure_IRQ_timeout(state->irq);
7396 +
7397 + /*
7398 + * Free the IRQ, if necessary
7399 + */
7400 + if (state->irq && (!IRQ_ports[state->irq] ||
7401 + !IRQ_ports[state->irq]->next_port)) {
7402 + if (IRQ_ports[state->irq]) {
7403 + free_irq(state->irq, &IRQ_ports[state->irq]);
7404 + retval = request_irq(state->irq, rs_interrupt_single,
7405 + SA_SHIRQ, "serial",
7406 + &IRQ_ports[state->irq]);
7407 +
7408 + if (retval)
7409 + printk("serial shutdown: request_irq: error %d"
7410 + " Couldn't reacquire IRQ.\n", retval);
7411 + } else
7412 + free_irq(state->irq, &IRQ_ports[state->irq]);
7413 + }
7414 +
7415 + if (info->xmit.buf) {
7416 + unsigned long pg = (unsigned long) info->xmit.buf;
7417 + info->xmit.buf = 0;
7418 + free_page(pg);
7419 + }
7420 +
7421 + info->IER = 0;
7422 + serial_outp(info, UART_IER, 0x00); /* disable all intrs */
7423 +#ifdef CONFIG_SERIAL_MANY_PORTS
7424 + if (info->flags & ASYNC_FOURPORT) {
7425 + /* reset interrupts on the AST Fourport board */
7426 + (void) inb((info->port & 0xFE0) | 0x01F);
7427 + info->MCR |= UART_MCR_OUT1;
7428 + } else
7429 +#endif
7430 + info->MCR &= ~UART_MCR_OUT2;
7431 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
7432 +
7433 + /* disable break condition */
7434 + serial_out(info, UART_LCR, serial_inp(info, UART_LCR) & ~UART_LCR_SBC);
7435 +
7436 + if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
7437 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
7438 + serial_outp(info, UART_MCR, info->MCR);
7439 +
7440 + /* disable FIFO's */
7441 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
7442 + UART_FCR_CLEAR_RCVR |
7443 + UART_FCR_CLEAR_XMIT));
7444 + serial_outp(info, UART_FCR, 0);
7445 +
7446 +#ifdef CONFIG_SERIAL_RSA
7447 + /*
7448 + * Reset the RSA board back to 115kbps compat mode.
7449 + */
7450 + if ((state->type == PORT_RSA) &&
7451 + (state->baud_base == SERIAL_RSA_BAUD_BASE &&
7452 + disable_rsa(info)))
7453 + state->baud_base = SERIAL_RSA_BAUD_BASE_LO;
7454 +#endif
7455 +
7456 +
7457 + (void)serial_in(info, UART_RX); /* read data port to reset things */
7458 +
7459 + if (info->tty)
7460 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7461 +
7462 + if (uart_config[info->state->type].flags & UART_STARTECH) {
7463 + /* Arrange to enter sleep mode */
7464 + serial_outp(info, UART_LCR, 0xBF);
7465 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7466 + serial_outp(info, UART_LCR, 0);
7467 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
7468 + serial_outp(info, UART_LCR, 0xBF);
7469 + serial_outp(info, UART_EFR, 0);
7470 + serial_outp(info, UART_LCR, 0);
7471 + }
7472 + if (info->state->type == PORT_16750) {
7473 + /* Arrange to enter sleep mode */
7474 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
7475 + }
7476 + info->flags &= ~ASYNC_INITIALIZED;
7477 + restore_flags(flags);
7478 +}
7479 +
7480 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
7481 +static int baud_table[] = {
7482 + 0, 50, 75, 110, 134, 150, 200, 300,
7483 + 600, 1200, 1800, 2400, 4800, 9600, 19200,
7484 + 38400, 57600, 115200, 230400, 460800, 0 };
7485 +
7486 +static int tty_get_baud_rate(struct tty_struct *tty)
7487 +{
7488 + struct async_struct * info = (struct async_struct *)tty->driver_data;
7489 + unsigned int cflag, i;
7490 +
7491 + cflag = tty->termios->c_cflag;
7492 +
7493 + i = cflag & CBAUD;
7494 + if (i & CBAUDEX) {
7495 + i &= ~CBAUDEX;
7496 + if (i < 1 || i > 2)
7497 + tty->termios->c_cflag &= ~CBAUDEX;
7498 + else
7499 + i += 15;
7500 + }
7501 + if (i == 15) {
7502 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
7503 + i += 1;
7504 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
7505 + i += 2;
7506 + }
7507 + return baud_table[i];
7508 +}
7509 +#endif
7510 +
7511 +/*
7512 + * This routine is called to set the UART divisor registers to match
7513 + * the specified baud rate for a serial port.
7514 + */
7515 +static void change_speed(struct async_struct *info,
7516 + struct termios *old_termios)
7517 +{
7518 + int quot = 0, baud_base, baud;
7519 + unsigned cflag, cval, fcr = 0;
7520 + int bits;
7521 + unsigned long flags;
7522 +
7523 + if (!info->tty || !info->tty->termios)
7524 + return;
7525 + cflag = info->tty->termios->c_cflag;
7526 + if (!CONFIGURED_SERIAL_PORT(info))
7527 + return;
7528 +
7529 + /* byte size and parity */
7530 + switch (cflag & CSIZE) {
7531 + case CS5: cval = 0x00; bits = 7; break;
7532 + case CS6: cval = 0x01; bits = 8; break;
7533 + case CS7: cval = 0x02; bits = 9; break;
7534 + case CS8: cval = 0x03; bits = 10; break;
7535 + /* Never happens, but GCC is too dumb to figure it out */
7536 + default: cval = 0x00; bits = 7; break;
7537 + }
7538 + if (cflag & CSTOPB) {
7539 + cval |= 0x04;
7540 + bits++;
7541 + }
7542 + if (cflag & PARENB) {
7543 + cval |= UART_LCR_PARITY;
7544 + bits++;
7545 + }
7546 + if (!(cflag & PARODD))
7547 + cval |= UART_LCR_EPAR;
7548 +#ifdef CMSPAR
7549 + if (cflag & CMSPAR)
7550 + cval |= UART_LCR_SPAR;
7551 +#endif
7552 +
7553 + /* Determine divisor based on baud rate */
7554 + baud = tty_get_baud_rate(info->tty);
7555 + if (!baud)
7556 + baud = 9600; /* B0 transition handled in rs_set_termios */
7557 +#ifdef CONFIG_SERIAL_RSA
7558 + if ((info->state->type == PORT_RSA) &&
7559 + (info->state->baud_base != SERIAL_RSA_BAUD_BASE) &&
7560 + enable_rsa(info))
7561 + info->state->baud_base = SERIAL_RSA_BAUD_BASE;
7562 +#endif
7563 + baud_base = info->state->baud_base;
7564 + if (info->state->type == PORT_16C950) {
7565 + if (baud <= baud_base)
7566 + serial_icr_write(info, UART_TCR, 0);
7567 + else if (baud <= 2*baud_base) {
7568 + serial_icr_write(info, UART_TCR, 0x8);
7569 + baud_base = baud_base * 2;
7570 + } else if (baud <= 4*baud_base) {
7571 + serial_icr_write(info, UART_TCR, 0x4);
7572 + baud_base = baud_base * 4;
7573 + } else
7574 + serial_icr_write(info, UART_TCR, 0);
7575 + }
7576 + if (baud == 38400 &&
7577 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
7578 + quot = info->state->custom_divisor;
7579 + else {
7580 + if (baud == 134)
7581 + /* Special case since 134 is really 134.5 */
7582 + quot = (2*baud_base / 269);
7583 + else if (baud)
7584 + quot = baud_base / baud;
7585 + }
7586 + /* If the quotient is zero refuse the change */
7587 + if (!quot && old_termios) {
7588 + info->tty->termios->c_cflag &= ~CBAUD;
7589 + info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD);
7590 + baud = tty_get_baud_rate(info->tty);
7591 + if (!baud)
7592 + baud = 9600;
7593 + if (baud == 38400 &&
7594 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
7595 + quot = info->state->custom_divisor;
7596 + else {
7597 + if (baud == 134)
7598 + /* Special case since 134 is really 134.5 */
7599 + quot = (2*baud_base / 269);
7600 + else if (baud)
7601 + quot = baud_base / baud;
7602 + }
7603 + }
7604 + /* As a last resort, if the quotient is zero, default to 9600 bps */
7605 + if (!quot)
7606 + quot = baud_base / 9600;
7607 + /*
7608 + * Work around a bug in the Oxford Semiconductor 952 rev B
7609 + * chip which causes it to seriously miscalculate baud rates
7610 + * when DLL is 0.
7611 + */
7612 + if (((quot & 0xFF) == 0) && (info->state->type == PORT_16C950) &&
7613 + (info->state->revision == 0x5201))
7614 + quot++;
7615 +
7616 + info->quot = quot;
7617 + info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base);
7618 + info->timeout += HZ/50; /* Add .02 seconds of slop */
7619 +
7620 + /* Set up FIFO's */
7621 + if (uart_config[info->state->type].flags & UART_USE_FIFO) {
7622 + if ((info->state->baud_base / quot) < 2400)
7623 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
7624 +#ifdef CONFIG_SERIAL_RSA
7625 + else if (info->state->type == PORT_RSA)
7626 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
7627 +#endif
7628 + else
7629 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
7630 + }
7631 + if (info->state->type == PORT_16750)
7632 + fcr |= UART_FCR7_64BYTE;
7633 +
7634 + /* CTS flow control flag and modem status interrupts */
7635 + info->IER &= ~UART_IER_MSI;
7636 + if (info->flags & ASYNC_HARDPPS_CD)
7637 + info->IER |= UART_IER_MSI;
7638 + if (cflag & CRTSCTS) {
7639 + info->flags |= ASYNC_CTS_FLOW;
7640 + info->IER |= UART_IER_MSI;
7641 + } else
7642 + info->flags &= ~ASYNC_CTS_FLOW;
7643 + if (cflag & CLOCAL)
7644 + info->flags &= ~ASYNC_CHECK_CD;
7645 + else {
7646 + info->flags |= ASYNC_CHECK_CD;
7647 + info->IER |= UART_IER_MSI;
7648 + }
7649 + serial_out(info, UART_IER, info->IER);
7650 +
7651 + /*
7652 + * Set up parity check flag
7653 + */
7654 +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
7655 +
7656 + info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
7657 + if (I_INPCK(info->tty))
7658 + info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
7659 + if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
7660 + info->read_status_mask |= UART_LSR_BI;
7661 +
7662 + /*
7663 + * Characters to ignore
7664 + */
7665 + info->ignore_status_mask = 0;
7666 + if (I_IGNPAR(info->tty))
7667 + info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
7668 + if (I_IGNBRK(info->tty)) {
7669 + info->ignore_status_mask |= UART_LSR_BI;
7670 + /*
7671 + * If we're ignore parity and break indicators, ignore
7672 + * overruns too. (For real raw support).
7673 + */
7674 + if (I_IGNPAR(info->tty))
7675 + info->ignore_status_mask |= UART_LSR_OE;
7676 + }
7677 + /*
7678 + * !!! ignore all characters if CREAD is not set
7679 + */
7680 + if ((cflag & CREAD) == 0)
7681 + info->ignore_status_mask |= UART_LSR_DR;
7682 + save_flags(flags); cli();
7683 + if (uart_config[info->state->type].flags & UART_STARTECH) {
7684 + serial_outp(info, UART_LCR, 0xBF);
7685 + serial_outp(info, UART_EFR,
7686 + (cflag & CRTSCTS) ? UART_EFR_CTS : 0);
7687 + }
7688 + serial_outp(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
7689 + serial_outp(info, UART_DLL, quot & 0xff); /* LS of divisor */
7690 + serial_outp(info, UART_DLM, quot >> 8); /* MS of divisor */
7691 + if (info->state->type == PORT_16750)
7692 + serial_outp(info, UART_FCR, fcr); /* set fcr */
7693 + serial_outp(info, UART_LCR, cval); /* reset DLAB */
7694 + info->LCR = cval; /* Save LCR */
7695 + if (info->state->type != PORT_16750) {
7696 + if (fcr & UART_FCR_ENABLE_FIFO) {
7697 + /* emulated UARTs (Lucent Venus 167x) need two steps */
7698 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
7699 + }
7700 + serial_outp(info, UART_FCR, fcr); /* set fcr */
7701 + }
7702 + restore_flags(flags);
7703 +}
7704 +
7705 +static void rs_put_char(struct tty_struct *tty, unsigned char ch)
7706 +{
7707 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7708 + unsigned long flags;
7709 +
7710 + if (serial_paranoia_check(info, tty->device, "rs_put_char"))
7711 + return;
7712 +
7713 + if (!tty || !info->xmit.buf)
7714 + return;
7715 +
7716 + save_flags(flags); cli();
7717 + if (CIRC_SPACE(info->xmit.head,
7718 + info->xmit.tail,
7719 + SERIAL_XMIT_SIZE) == 0) {
7720 + restore_flags(flags);
7721 + return;
7722 + }
7723 +
7724 + info->xmit.buf[info->xmit.head] = ch;
7725 + info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
7726 + restore_flags(flags);
7727 +}
7728 +
7729 +static void rs_flush_chars(struct tty_struct *tty)
7730 +{
7731 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7732 + unsigned long flags;
7733 +
7734 + if (serial_paranoia_check(info, tty->device, "rs_flush_chars"))
7735 + return;
7736 +
7737 + if (info->xmit.head == info->xmit.tail
7738 + || tty->stopped
7739 + || tty->hw_stopped
7740 + || !info->xmit.buf)
7741 + return;
7742 +
7743 + save_flags(flags); cli();
7744 + info->IER |= UART_IER_THRI;
7745 + serial_out(info, UART_IER, info->IER);
7746 + restore_flags(flags);
7747 +}
7748 +
7749 +static int rs_write(struct tty_struct * tty, int from_user,
7750 + const unsigned char *buf, int count)
7751 +{
7752 + int c, ret = 0;
7753 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7754 + unsigned long flags;
7755 +
7756 + if (serial_paranoia_check(info, tty->device, "rs_write"))
7757 + return 0;
7758 +
7759 + if (!tty || !info->xmit.buf || !tmp_buf)
7760 + return 0;
7761 +
7762 + save_flags(flags);
7763 + if (from_user) {
7764 + down(&tmp_buf_sem);
7765 + while (1) {
7766 + int c1;
7767 + c = CIRC_SPACE_TO_END(info->xmit.head,
7768 + info->xmit.tail,
7769 + SERIAL_XMIT_SIZE);
7770 + if (count < c)
7771 + c = count;
7772 + if (c <= 0)
7773 + break;
7774 +
7775 + c -= copy_from_user(tmp_buf, buf, c);
7776 + if (!c) {
7777 + if (!ret)
7778 + ret = -EFAULT;
7779 + break;
7780 + }
7781 + cli();
7782 + c1 = CIRC_SPACE_TO_END(info->xmit.head,
7783 + info->xmit.tail,
7784 + SERIAL_XMIT_SIZE);
7785 + if (c1 < c)
7786 + c = c1;
7787 + memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c);
7788 + info->xmit.head = ((info->xmit.head + c) &
7789 + (SERIAL_XMIT_SIZE-1));
7790 + restore_flags(flags);
7791 + buf += c;
7792 + count -= c;
7793 + ret += c;
7794 + }
7795 + up(&tmp_buf_sem);
7796 + } else {
7797 + cli();
7798 + while (1) {
7799 + c = CIRC_SPACE_TO_END(info->xmit.head,
7800 + info->xmit.tail,
7801 + SERIAL_XMIT_SIZE);
7802 + if (count < c)
7803 + c = count;
7804 + if (c <= 0) {
7805 + break;
7806 + }
7807 + memcpy(info->xmit.buf + info->xmit.head, buf, c);
7808 + info->xmit.head = ((info->xmit.head + c) &
7809 + (SERIAL_XMIT_SIZE-1));
7810 + buf += c;
7811 + count -= c;
7812 + ret += c;
7813 + }
7814 + restore_flags(flags);
7815 + }
7816 + if (info->xmit.head != info->xmit.tail
7817 + && !tty->stopped
7818 + && !tty->hw_stopped
7819 + && !(info->IER & UART_IER_THRI)) {
7820 + info->IER |= UART_IER_THRI;
7821 + serial_out(info, UART_IER, info->IER);
7822 + }
7823 + return ret;
7824 +}
7825 +
7826 +static int rs_write_room(struct tty_struct *tty)
7827 +{
7828 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7829 +
7830 + if (serial_paranoia_check(info, tty->device, "rs_write_room"))
7831 + return 0;
7832 + return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
7833 +}
7834 +
7835 +static int rs_chars_in_buffer(struct tty_struct *tty)
7836 +{
7837 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7838 +
7839 + if (serial_paranoia_check(info, tty->device, "rs_chars_in_buffer"))
7840 + return 0;
7841 + return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
7842 +}
7843 +
7844 +static void rs_flush_buffer(struct tty_struct *tty)
7845 +{
7846 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7847 + unsigned long flags;
7848 +
7849 + if (serial_paranoia_check(info, tty->device, "rs_flush_buffer"))
7850 + return;
7851 + save_flags(flags); cli();
7852 + info->xmit.head = info->xmit.tail = 0;
7853 + restore_flags(flags);
7854 +#ifdef SERIAL_HAVE_POLL_WAIT
7855 + wake_up_interruptible(&tty->poll_wait);
7856 +#endif
7857 + tty_wakeup(tty);
7858 +}
7859 +
7860 +/*
7861 + * This function is used to send a high-priority XON/XOFF character to
7862 + * the device
7863 + */
7864 +static void rs_send_xchar(struct tty_struct *tty, char ch)
7865 +{
7866 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7867 +
7868 + if (serial_paranoia_check(info, tty->device, "rs_send_char"))
7869 + return;
7870 +
7871 + info->x_char = ch;
7872 + if (ch) {
7873 + /* Make sure transmit interrupts are on */
7874 + info->IER |= UART_IER_THRI;
7875 + serial_out(info, UART_IER, info->IER);
7876 + }
7877 +}
7878 +
7879 +/*
7880 + * ------------------------------------------------------------
7881 + * rs_throttle()
7882 + *
7883 + * This routine is called by the upper-layer tty layer to signal that
7884 + * incoming characters should be throttled.
7885 + * ------------------------------------------------------------
7886 + */
7887 +static void rs_throttle(struct tty_struct * tty)
7888 +{
7889 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7890 + unsigned long flags;
7891 +#ifdef SERIAL_DEBUG_THROTTLE
7892 + char buf[64];
7893 +
7894 + printk("throttle %s: %d....\n", tty_name(tty, buf),
7895 + tty->ldisc.chars_in_buffer(tty));
7896 +#endif
7897 +
7898 + if (serial_paranoia_check(info, tty->device, "rs_throttle"))
7899 + return;
7900 +
7901 + if (I_IXOFF(tty))
7902 + rs_send_xchar(tty, STOP_CHAR(tty));
7903 +
7904 + if (tty->termios->c_cflag & CRTSCTS)
7905 + info->MCR &= ~UART_MCR_RTS;
7906 +
7907 + save_flags(flags); cli();
7908 + serial_out(info, UART_MCR, info->MCR);
7909 + restore_flags(flags);
7910 +}
7911 +
7912 +static void rs_unthrottle(struct tty_struct * tty)
7913 +{
7914 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7915 + unsigned long flags;
7916 +#ifdef SERIAL_DEBUG_THROTTLE
7917 + char buf[64];
7918 +
7919 + printk("unthrottle %s: %d....\n", tty_name(tty, buf),
7920 + tty->ldisc.chars_in_buffer(tty));
7921 +#endif
7922 +
7923 + if (serial_paranoia_check(info, tty->device, "rs_unthrottle"))
7924 + return;
7925 +
7926 + if (I_IXOFF(tty)) {
7927 + if (info->x_char)
7928 + info->x_char = 0;
7929 + else
7930 + rs_send_xchar(tty, START_CHAR(tty));
7931 + }
7932 + if (tty->termios->c_cflag & CRTSCTS)
7933 + info->MCR |= UART_MCR_RTS;
7934 + save_flags(flags); cli();
7935 + serial_out(info, UART_MCR, info->MCR);
7936 + restore_flags(flags);
7937 +}
7938 +
7939 +/*
7940 + * ------------------------------------------------------------
7941 + * rs_ioctl() and friends
7942 + * ------------------------------------------------------------
7943 + */
7944 +
7945 +static int get_serial_info(struct async_struct * info,
7946 + struct serial_struct * retinfo)
7947 +{
7948 + struct serial_struct tmp;
7949 + struct serial_state *state = info->state;
7950 +
7951 + if (!retinfo)
7952 + return -EFAULT;
7953 + memset(&tmp, 0, sizeof(tmp));
7954 + tmp.type = state->type;
7955 + tmp.line = state->line;
7956 + tmp.port = state->port;
7957 + if (HIGH_BITS_OFFSET)
7958 + tmp.port_high = state->port >> HIGH_BITS_OFFSET;
7959 + else
7960 + tmp.port_high = 0;
7961 + tmp.irq = state->irq;
7962 + tmp.flags = state->flags;
7963 + tmp.xmit_fifo_size = state->xmit_fifo_size;
7964 + tmp.baud_base = state->baud_base;
7965 + tmp.close_delay = state->close_delay;
7966 + tmp.closing_wait = state->closing_wait;
7967 + tmp.custom_divisor = state->custom_divisor;
7968 + tmp.hub6 = state->hub6;
7969 + tmp.io_type = state->io_type;
7970 + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
7971 + return -EFAULT;
7972 + return 0;
7973 +}
7974 +
7975 +static int set_serial_info(struct async_struct * info,
7976 + struct serial_struct * new_info)
7977 +{
7978 + struct serial_struct new_serial;
7979 + struct serial_state old_state, *state;
7980 + unsigned int i,change_irq,change_port;
7981 + int retval = 0;
7982 + unsigned long new_port;
7983 +
7984 + if (copy_from_user(&new_serial,new_info,sizeof(new_serial)))
7985 + return -EFAULT;
7986 + state = info->state;
7987 + old_state = *state;
7988 +
7989 + new_port = new_serial.port;
7990 + if (HIGH_BITS_OFFSET)
7991 + new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET;
7992 +
7993 + change_irq = new_serial.irq != state->irq;
7994 + change_port = (new_port != ((int) state->port)) ||
7995 + (new_serial.hub6 != state->hub6);
7996 +
7997 + if (!capable(CAP_SYS_ADMIN)) {
7998 + if (change_irq || change_port ||
7999 + (new_serial.baud_base != state->baud_base) ||
8000 + (new_serial.type != state->type) ||
8001 + (new_serial.close_delay != state->close_delay) ||
8002 + (new_serial.xmit_fifo_size != state->xmit_fifo_size) ||
8003 + ((new_serial.flags & ~ASYNC_USR_MASK) !=
8004 + (state->flags & ~ASYNC_USR_MASK)))
8005 + return -EPERM;
8006 + state->flags = ((state->flags & ~ASYNC_USR_MASK) |
8007 + (new_serial.flags & ASYNC_USR_MASK));
8008 + info->flags = ((info->flags & ~ASYNC_USR_MASK) |
8009 + (new_serial.flags & ASYNC_USR_MASK));
8010 + state->custom_divisor = new_serial.custom_divisor;
8011 + goto check_and_exit;
8012 + }
8013 +
8014 + new_serial.irq = irq_cannonicalize(new_serial.irq);
8015 +
8016 + if ((new_serial.irq >= NR_IRQS) || (new_serial.irq < 0) ||
8017 + (new_serial.baud_base < 9600)|| (new_serial.type < PORT_UNKNOWN) ||
8018 + (new_serial.type > PORT_MAX) || (new_serial.type == PORT_CIRRUS) ||
8019 + (new_serial.type == PORT_STARTECH)) {
8020 + return -EINVAL;
8021 + }
8022 +
8023 + if ((new_serial.type != state->type) ||
8024 + (new_serial.xmit_fifo_size <= 0))
8025 + new_serial.xmit_fifo_size =
8026 + uart_config[new_serial.type].dfl_xmit_fifo_size;
8027 +
8028 + /* Make sure address is not already in use */
8029 + if (new_serial.type) {
8030 + for (i = 0 ; i < NR_PORTS; i++)
8031 + if ((state != &rs_table[i]) &&
8032 + (rs_table[i].io_type == SERIAL_IO_PORT) &&
8033 + (rs_table[i].port == new_port) &&
8034 + rs_table[i].type)
8035 + return -EADDRINUSE;
8036 + }
8037 +
8038 + if ((change_port || change_irq) && (state->count > 1))
8039 + return -EBUSY;
8040 +
8041 + /*
8042 + * OK, past this point, all the error checking has been done.
8043 + * At this point, we start making changes.....
8044 + */
8045 +
8046 + state->baud_base = new_serial.baud_base;
8047 + state->flags = ((state->flags & ~ASYNC_FLAGS) |
8048 + (new_serial.flags & ASYNC_FLAGS));
8049 + info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) |
8050 + (info->flags & ASYNC_INTERNAL_FLAGS));
8051 + state->custom_divisor = new_serial.custom_divisor;
8052 + state->close_delay = new_serial.close_delay * HZ/100;
8053 + state->closing_wait = new_serial.closing_wait * HZ/100;
8054 +#if (LINUX_VERSION_CODE > 0x20100)
8055 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
8056 +#endif
8057 + info->xmit_fifo_size = state->xmit_fifo_size =
8058 + new_serial.xmit_fifo_size;
8059 +
8060 + if ((state->type != PORT_UNKNOWN) && state->port) {
8061 +#ifdef CONFIG_SERIAL_RSA
8062 + if (old_state.type == PORT_RSA)
8063 + release_region(state->port + UART_RSA_BASE, 16);
8064 + else
8065 +#endif
8066 + release_region(state->port,8);
8067 + }
8068 + state->type = new_serial.type;
8069 + if (change_port || change_irq) {
8070 + /*
8071 + * We need to shutdown the serial port at the old
8072 + * port/irq combination.
8073 + */
8074 + shutdown(info);
8075 + state->irq = new_serial.irq;
8076 + info->port = state->port = new_port;
8077 + info->hub6 = state->hub6 = new_serial.hub6;
8078 + if (info->hub6)
8079 + info->io_type = state->io_type = SERIAL_IO_HUB6;
8080 + else if (info->io_type == SERIAL_IO_HUB6)
8081 + info->io_type = state->io_type = SERIAL_IO_PORT;
8082 + }
8083 + if ((state->type != PORT_UNKNOWN) && state->port) {
8084 +#ifdef CONFIG_SERIAL_RSA
8085 + if (state->type == PORT_RSA)
8086 + request_region(state->port + UART_RSA_BASE,
8087 + 16, "serial_rsa(set)");
8088 + else
8089 +#endif
8090 + request_region(state->port,8,"serial(set)");
8091 + }
8092 +
8093 +
8094 +check_and_exit:
8095 + if ((!state->port && !state->iomem_base) || !state->type)
8096 + return 0;
8097 + if (info->flags & ASYNC_INITIALIZED) {
8098 + if (((old_state.flags & ASYNC_SPD_MASK) !=
8099 + (state->flags & ASYNC_SPD_MASK)) ||
8100 + (old_state.custom_divisor != state->custom_divisor)) {
8101 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
8102 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
8103 + info->tty->alt_speed = 57600;
8104 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
8105 + info->tty->alt_speed = 115200;
8106 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
8107 + info->tty->alt_speed = 230400;
8108 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
8109 + info->tty->alt_speed = 460800;
8110 +#endif
8111 + change_speed(info, 0);
8112 + }
8113 + } else
8114 + retval = startup(info);
8115 + return retval;
8116 +}
8117 +
8118 +
8119 +/*
8120 + * get_lsr_info - get line status register info
8121 + *
8122 + * Purpose: Let user call ioctl() to get info when the UART physically
8123 + * is emptied. On bus types like RS485, the transmitter must
8124 + * release the bus after transmitting. This must be done when
8125 + * the transmit shift register is empty, not be done when the
8126 + * transmit holding register is empty. This functionality
8127 + * allows an RS485 driver to be written in user space.
8128 + */
8129 +static int get_lsr_info(struct async_struct * info, unsigned int *value)
8130 +{
8131 + unsigned char status;
8132 + unsigned int result;
8133 + unsigned long flags;
8134 +
8135 + save_flags(flags); cli();
8136 + status = serial_in(info, UART_LSR);
8137 + restore_flags(flags);
8138 + result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
8139 +
8140 + /*
8141 + * If we're about to load something into the transmit
8142 + * register, we'll pretend the transmitter isn't empty to
8143 + * avoid a race condition (depending on when the transmit
8144 + * interrupt happens).
8145 + */
8146 + if (info->x_char ||
8147 + ((CIRC_CNT(info->xmit.head, info->xmit.tail,
8148 + SERIAL_XMIT_SIZE) > 0) &&
8149 + !info->tty->stopped && !info->tty->hw_stopped))
8150 + result &= ~TIOCSER_TEMT;
8151 +
8152 + if (copy_to_user(value, &result, sizeof(int)))
8153 + return -EFAULT;
8154 + return 0;
8155 +}
8156 +
8157 +
8158 +static int get_modem_info(struct async_struct * info, unsigned int *value)
8159 +{
8160 + unsigned char control, status;
8161 + unsigned int result;
8162 + unsigned long flags;
8163 +
8164 + control = info->MCR;
8165 + save_flags(flags); cli();
8166 + status = serial_in(info, UART_MSR);
8167 + restore_flags(flags);
8168 + result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
8169 + | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
8170 +#ifdef TIOCM_OUT1
8171 + | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
8172 + | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
8173 +#endif
8174 + | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0)
8175 + | ((status & UART_MSR_RI) ? TIOCM_RNG : 0)
8176 + | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0)
8177 + | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
8178 +
8179 + if (copy_to_user(value, &result, sizeof(int)))
8180 + return -EFAULT;
8181 + return 0;
8182 +}
8183 +
8184 +static int set_modem_info(struct async_struct * info, unsigned int cmd,
8185 + unsigned int *value)
8186 +{
8187 + unsigned int arg;
8188 + unsigned long flags;
8189 +
8190 + if (copy_from_user(&arg, value, sizeof(int)))
8191 + return -EFAULT;
8192 +
8193 + switch (cmd) {
8194 + case TIOCMBIS:
8195 + if (arg & TIOCM_RTS)
8196 + info->MCR |= UART_MCR_RTS;
8197 + if (arg & TIOCM_DTR)
8198 + info->MCR |= UART_MCR_DTR;
8199 +#ifdef TIOCM_OUT1
8200 + if (arg & TIOCM_OUT1)
8201 + info->MCR |= UART_MCR_OUT1;
8202 + if (arg & TIOCM_OUT2)
8203 + info->MCR |= UART_MCR_OUT2;
8204 +#endif
8205 + if (arg & TIOCM_LOOP)
8206 + info->MCR |= UART_MCR_LOOP;
8207 + break;
8208 + case TIOCMBIC:
8209 + if (arg & TIOCM_RTS)
8210 + info->MCR &= ~UART_MCR_RTS;
8211 + if (arg & TIOCM_DTR)
8212 + info->MCR &= ~UART_MCR_DTR;
8213 +#ifdef TIOCM_OUT1
8214 + if (arg & TIOCM_OUT1)
8215 + info->MCR &= ~UART_MCR_OUT1;
8216 + if (arg & TIOCM_OUT2)
8217 + info->MCR &= ~UART_MCR_OUT2;
8218 +#endif
8219 + if (arg & TIOCM_LOOP)
8220 + info->MCR &= ~UART_MCR_LOOP;
8221 + break;
8222 + case TIOCMSET:
8223 + info->MCR = ((info->MCR & ~(UART_MCR_RTS |
8224 +#ifdef TIOCM_OUT1
8225 + UART_MCR_OUT1 |
8226 + UART_MCR_OUT2 |
8227 +#endif
8228 + UART_MCR_LOOP |
8229 + UART_MCR_DTR))
8230 + | ((arg & TIOCM_RTS) ? UART_MCR_RTS : 0)
8231 +#ifdef TIOCM_OUT1
8232 + | ((arg & TIOCM_OUT1) ? UART_MCR_OUT1 : 0)
8233 + | ((arg & TIOCM_OUT2) ? UART_MCR_OUT2 : 0)
8234 +#endif
8235 + | ((arg & TIOCM_LOOP) ? UART_MCR_LOOP : 0)
8236 + | ((arg & TIOCM_DTR) ? UART_MCR_DTR : 0));
8237 + break;
8238 + default:
8239 + return -EINVAL;
8240 + }
8241 + save_flags(flags); cli();
8242 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
8243 + serial_out(info, UART_MCR, info->MCR);
8244 + restore_flags(flags);
8245 + return 0;
8246 +}
8247 +
8248 +static int do_autoconfig(struct async_struct * info)
8249 +{
8250 + int irq, retval;
8251 +
8252 + if (!capable(CAP_SYS_ADMIN))
8253 + return -EPERM;
8254 +
8255 + if (info->state->count > 1)
8256 + return -EBUSY;
8257 +
8258 + shutdown(info);
8259 +
8260 + autoconfig(info->state);
8261 + if ((info->state->flags & ASYNC_AUTO_IRQ) &&
8262 + (info->state->port != 0 || info->state->iomem_base != 0) &&
8263 + (info->state->type != PORT_UNKNOWN)) {
8264 + irq = detect_uart_irq(info->state);
8265 + if (irq > 0)
8266 + info->state->irq = irq;
8267 + }
8268 +
8269 + retval = startup(info);
8270 + if (retval)
8271 + return retval;
8272 + return 0;
8273 +}
8274 +
8275 +/*
8276 + * rs_break() --- routine which turns the break handling on or off
8277 + */
8278 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8279 +static void send_break( struct async_struct * info, int duration)
8280 +{
8281 + if (!CONFIGURED_SERIAL_PORT(info))
8282 + return;
8283 + current->state = TASK_INTERRUPTIBLE;
8284 + current->timeout = jiffies + duration;
8285 + cli();
8286 + info->LCR |= UART_LCR_SBC;
8287 + serial_out(info, UART_LCR, info->LCR);
8288 + schedule();
8289 + info->LCR &= ~UART_LCR_SBC;
8290 + serial_out(info, UART_LCR, info->LCR);
8291 + sti();
8292 +}
8293 +#else
8294 +static void rs_break(struct tty_struct *tty, int break_state)
8295 +{
8296 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8297 + unsigned long flags;
8298 +
8299 + if (serial_paranoia_check(info, tty->device, "rs_break"))
8300 + return;
8301 +
8302 + if (!CONFIGURED_SERIAL_PORT(info))
8303 + return;
8304 + save_flags(flags); cli();
8305 + if (break_state == -1)
8306 + info->LCR |= UART_LCR_SBC;
8307 + else
8308 + info->LCR &= ~UART_LCR_SBC;
8309 + serial_out(info, UART_LCR, info->LCR);
8310 + restore_flags(flags);
8311 +}
8312 +#endif
8313 +
8314 +#ifdef CONFIG_SERIAL_MULTIPORT
8315 +static int get_multiport_struct(struct async_struct * info,
8316 + struct serial_multiport_struct *retinfo)
8317 +{
8318 + struct serial_multiport_struct ret;
8319 + struct rs_multiport_struct *multi;
8320 +
8321 + multi = &rs_multiport[info->state->irq];
8322 +
8323 + ret.port_monitor = multi->port_monitor;
8324 +
8325 + ret.port1 = multi->port1;
8326 + ret.mask1 = multi->mask1;
8327 + ret.match1 = multi->match1;
8328 +
8329 + ret.port2 = multi->port2;
8330 + ret.mask2 = multi->mask2;
8331 + ret.match2 = multi->match2;
8332 +
8333 + ret.port3 = multi->port3;
8334 + ret.mask3 = multi->mask3;
8335 + ret.match3 = multi->match3;
8336 +
8337 + ret.port4 = multi->port4;
8338 + ret.mask4 = multi->mask4;
8339 + ret.match4 = multi->match4;
8340 +
8341 + ret.irq = info->state->irq;
8342 +
8343 + if (copy_to_user(retinfo,&ret,sizeof(*retinfo)))
8344 + return -EFAULT;
8345 + return 0;
8346 +}
8347 +
8348 +static int set_multiport_struct(struct async_struct * info,
8349 + struct serial_multiport_struct *in_multi)
8350 +{
8351 + struct serial_multiport_struct new_multi;
8352 + struct rs_multiport_struct *multi;
8353 + struct serial_state *state;
8354 + int was_multi, now_multi;
8355 + int retval;
8356 + void (*handler)(int, void *, struct pt_regs *);
8357 +
8358 + if (!capable(CAP_SYS_ADMIN))
8359 + return -EPERM;
8360 + state = info->state;
8361 +
8362 + if (copy_from_user(&new_multi, in_multi,
8363 + sizeof(struct serial_multiport_struct)))
8364 + return -EFAULT;
8365 +
8366 + if (new_multi.irq != state->irq || state->irq == 0 ||
8367 + !IRQ_ports[state->irq])
8368 + return -EINVAL;
8369 +
8370 + multi = &rs_multiport[state->irq];
8371 + was_multi = (multi->port1 != 0);
8372 +
8373 + multi->port_monitor = new_multi.port_monitor;
8374 +
8375 + if (multi->port1)
8376 + release_region(multi->port1,1);
8377 + multi->port1 = new_multi.port1;
8378 + multi->mask1 = new_multi.mask1;
8379 + multi->match1 = new_multi.match1;
8380 + if (multi->port1)
8381 + request_region(multi->port1,1,"serial(multiport1)");
8382 +
8383 + if (multi->port2)
8384 + release_region(multi->port2,1);
8385 + multi->port2 = new_multi.port2;
8386 + multi->mask2 = new_multi.mask2;
8387 + multi->match2 = new_multi.match2;
8388 + if (multi->port2)
8389 + request_region(multi->port2,1,"serial(multiport2)");
8390 +
8391 + if (multi->port3)
8392 + release_region(multi->port3,1);
8393 + multi->port3 = new_multi.port3;
8394 + multi->mask3 = new_multi.mask3;
8395 + multi->match3 = new_multi.match3;
8396 + if (multi->port3)
8397 + request_region(multi->port3,1,"serial(multiport3)");
8398 +
8399 + if (multi->port4)
8400 + release_region(multi->port4,1);
8401 + multi->port4 = new_multi.port4;
8402 + multi->mask4 = new_multi.mask4;
8403 + multi->match4 = new_multi.match4;
8404 + if (multi->port4)
8405 + request_region(multi->port4,1,"serial(multiport4)");
8406 +
8407 + now_multi = (multi->port1 != 0);
8408 +
8409 + if (IRQ_ports[state->irq]->next_port &&
8410 + (was_multi != now_multi)) {
8411 + free_irq(state->irq, &IRQ_ports[state->irq]);
8412 + if (now_multi)
8413 + handler = rs_interrupt_multi;
8414 + else
8415 + handler = rs_interrupt;
8416 +
8417 + retval = request_irq(state->irq, handler, SA_SHIRQ,
8418 + "serial", &IRQ_ports[state->irq]);
8419 + if (retval) {
8420 + printk("Couldn't reallocate serial interrupt "
8421 + "driver!!\n");
8422 + }
8423 + }
8424 + return 0;
8425 +}
8426 +#endif
8427 +
8428 +static int rs_ioctl(struct tty_struct *tty, struct file * file,
8429 + unsigned int cmd, unsigned long arg)
8430 +{
8431 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8432 + struct async_icount cprev, cnow; /* kernel counter temps */
8433 + struct serial_icounter_struct icount;
8434 + unsigned long flags;
8435 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8436 + int retval, tmp;
8437 +#endif
8438 +
8439 + if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
8440 + return -ENODEV;
8441 +
8442 + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
8443 + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) &&
8444 + (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
8445 + if (tty->flags & (1 << TTY_IO_ERROR))
8446 + return -EIO;
8447 + }
8448 +
8449 + switch (cmd) {
8450 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8451 + case TCSBRK: /* SVID version: non-zero arg --> no break */
8452 + retval = tty_check_change(tty);
8453 + if (retval)
8454 + return retval;
8455 + tty_wait_until_sent(tty, 0);
8456 + if (signal_pending(current))
8457 + return -EINTR;
8458 + if (!arg) {
8459 + send_break(info, HZ/4); /* 1/4 second */
8460 + if (signal_pending(current))
8461 + return -EINTR;
8462 + }
8463 + return 0;
8464 + case TCSBRKP: /* support for POSIX tcsendbreak() */
8465 + retval = tty_check_change(tty);
8466 + if (retval)
8467 + return retval;
8468 + tty_wait_until_sent(tty, 0);
8469 + if (signal_pending(current))
8470 + return -EINTR;
8471 + send_break(info, arg ? arg*(HZ/10) : HZ/4);
8472 + if (signal_pending(current))
8473 + return -EINTR;
8474 + return 0;
8475 + case TIOCGSOFTCAR:
8476 + tmp = C_CLOCAL(tty) ? 1 : 0;
8477 + if (copy_to_user((void *)arg, &tmp, sizeof(int)))
8478 + return -EFAULT;
8479 + return 0;
8480 + case TIOCSSOFTCAR:
8481 + if (copy_from_user(&tmp, (void *)arg, sizeof(int)))
8482 + return -EFAULT;
8483 +
8484 + tty->termios->c_cflag =
8485 + ((tty->termios->c_cflag & ~CLOCAL) |
8486 + (tmp ? CLOCAL : 0));
8487 + return 0;
8488 +#endif
8489 + case TIOCMGET:
8490 + return get_modem_info(info, (unsigned int *) arg);
8491 + case TIOCMBIS:
8492 + case TIOCMBIC:
8493 + case TIOCMSET:
8494 + return set_modem_info(info, cmd, (unsigned int *) arg);
8495 + case TIOCGSERIAL:
8496 + return get_serial_info(info,
8497 + (struct serial_struct *) arg);
8498 + case TIOCSSERIAL:
8499 + return set_serial_info(info,
8500 + (struct serial_struct *) arg);
8501 + case TIOCSERCONFIG:
8502 + return do_autoconfig(info);
8503 +
8504 + case TIOCSERGETLSR: /* Get line status register */
8505 + return get_lsr_info(info, (unsigned int *) arg);
8506 +
8507 + case TIOCSERGSTRUCT:
8508 + if (copy_to_user((struct async_struct *) arg,
8509 + info, sizeof(struct async_struct)))
8510 + return -EFAULT;
8511 + return 0;
8512 +
8513 +#ifdef CONFIG_SERIAL_MULTIPORT
8514 + case TIOCSERGETMULTI:
8515 + return get_multiport_struct(info,
8516 + (struct serial_multiport_struct *) arg);
8517 + case TIOCSERSETMULTI:
8518 + return set_multiport_struct(info,
8519 + (struct serial_multiport_struct *) arg);
8520 +#endif
8521 +
8522 + /*
8523 + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
8524 + * - mask passed in arg for lines of interest
8525 + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
8526 + * Caller should use TIOCGICOUNT to see which one it was
8527 + */
8528 + case TIOCMIWAIT:
8529 + save_flags(flags); cli();
8530 + /* note the counters on entry */
8531 + cprev = info->state->icount;
8532 + restore_flags(flags);
8533 + /* Force modem status interrupts on */
8534 + info->IER |= UART_IER_MSI;
8535 + serial_out(info, UART_IER, info->IER);
8536 + while (1) {
8537 + interruptible_sleep_on(&info->delta_msr_wait);
8538 + /* see if a signal did it */
8539 + if (signal_pending(current))
8540 + return -ERESTARTSYS;
8541 + save_flags(flags); cli();
8542 + cnow = info->state->icount; /* atomic copy */
8543 + restore_flags(flags);
8544 + if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
8545 + cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
8546 + return -EIO; /* no change => error */
8547 + if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
8548 + ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
8549 + ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
8550 + ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
8551 + return 0;
8552 + }
8553 + cprev = cnow;
8554 + }
8555 + /* NOTREACHED */
8556 +
8557 + /*
8558 + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
8559 + * Return: write counters to the user passed counter struct
8560 + * NB: both 1->0 and 0->1 transitions are counted except for
8561 + * RI where only 0->1 is counted.
8562 + */
8563 + case TIOCGICOUNT:
8564 + save_flags(flags); cli();
8565 + cnow = info->state->icount;
8566 + restore_flags(flags);
8567 + icount.cts = cnow.cts;
8568 + icount.dsr = cnow.dsr;
8569 + icount.rng = cnow.rng;
8570 + icount.dcd = cnow.dcd;
8571 + icount.rx = cnow.rx;
8572 + icount.tx = cnow.tx;
8573 + icount.frame = cnow.frame;
8574 + icount.overrun = cnow.overrun;
8575 + icount.parity = cnow.parity;
8576 + icount.brk = cnow.brk;
8577 + icount.buf_overrun = cnow.buf_overrun;
8578 +
8579 + if (copy_to_user((void *)arg, &icount, sizeof(icount)))
8580 + return -EFAULT;
8581 + return 0;
8582 + case TIOCSERGWILD:
8583 + case TIOCSERSWILD:
8584 + /* "setserial -W" is called in Debian boot */
8585 + printk ("TIOCSER?WILD ioctl obsolete, ignored.\n");
8586 + return 0;
8587 +
8588 + default:
8589 + return -ENOIOCTLCMD;
8590 + }
8591 + return 0;
8592 +}
8593 +
8594 +static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios)
8595 +{
8596 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8597 + unsigned long flags;
8598 + unsigned int cflag = tty->termios->c_cflag;
8599 +
8600 + if ( (cflag == old_termios->c_cflag)
8601 + && ( RELEVANT_IFLAG(tty->termios->c_iflag)
8602 + == RELEVANT_IFLAG(old_termios->c_iflag)))
8603 + return;
8604 +
8605 + change_speed(info, old_termios);
8606 +
8607 + /* Handle transition to B0 status */
8608 + if ((old_termios->c_cflag & CBAUD) &&
8609 + !(cflag & CBAUD)) {
8610 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
8611 + save_flags(flags); cli();
8612 + serial_out(info, UART_MCR, info->MCR);
8613 + restore_flags(flags);
8614 + }
8615 +
8616 + /* Handle transition away from B0 status */
8617 + if (!(old_termios->c_cflag & CBAUD) &&
8618 + (cflag & CBAUD)) {
8619 + info->MCR |= UART_MCR_DTR;
8620 + if (!(tty->termios->c_cflag & CRTSCTS) ||
8621 + !test_bit(TTY_THROTTLED, &tty->flags)) {
8622 + info->MCR |= UART_MCR_RTS;
8623 + }
8624 + save_flags(flags); cli();
8625 + serial_out(info, UART_MCR, info->MCR);
8626 + restore_flags(flags);
8627 + }
8628 +
8629 + /* Handle turning off CRTSCTS */
8630 + if ((old_termios->c_cflag & CRTSCTS) &&
8631 + !(tty->termios->c_cflag & CRTSCTS)) {
8632 + tty->hw_stopped = 0;
8633 + rs_start(tty);
8634 + }
8635 +
8636 +#if 0
8637 + /*
8638 + * No need to wake up processes in open wait, since they
8639 + * sample the CLOCAL flag once, and don't recheck it.
8640 + * XXX It's not clear whether the current behavior is correct
8641 + * or not. Hence, this may change.....
8642 + */
8643 + if (!(old_termios->c_cflag & CLOCAL) &&
8644 + (tty->termios->c_cflag & CLOCAL))
8645 + wake_up_interruptible(&info->open_wait);
8646 +#endif
8647 +}
8648 +
8649 +/*
8650 + * ------------------------------------------------------------
8651 + * rs_close()
8652 + *
8653 + * This routine is called when the serial port gets closed. First, we
8654 + * wait for the last remaining data to be sent. Then, we unlink its
8655 + * async structure from the interrupt chain if necessary, and we free
8656 + * that IRQ if nothing is left in the chain.
8657 + * ------------------------------------------------------------
8658 + */
8659 +static void rs_close(struct tty_struct *tty, struct file * filp)
8660 +{
8661 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8662 + struct serial_state *state;
8663 + unsigned long flags;
8664 +
8665 + if (!info || serial_paranoia_check(info, tty->device, "rs_close"))
8666 + return;
8667 +
8668 + state = info->state;
8669 +
8670 + save_flags(flags); cli();
8671 +
8672 + if (tty_hung_up_p(filp)) {
8673 + DBG_CNT("before DEC-hung");
8674 + MOD_DEC_USE_COUNT;
8675 + restore_flags(flags);
8676 + return;
8677 + }
8678 +
8679 +#ifdef SERIAL_DEBUG_OPEN
8680 + printk("rs_close ttys%d, count = %d\n", info->line, state->count);
8681 +#endif
8682 + if ((tty->count == 1) && (state->count != 1)) {
8683 + /*
8684 + * Uh, oh. tty->count is 1, which means that the tty
8685 + * structure will be freed. state->count should always
8686 + * be one in these conditions. If it's greater than
8687 + * one, we've got real problems, since it means the
8688 + * serial port won't be shutdown.
8689 + */
8690 + printk("rs_close: bad serial port count; tty->count is 1, "
8691 + "state->count is %d\n", state->count);
8692 + state->count = 1;
8693 + }
8694 + if (--state->count < 0) {
8695 + printk("rs_close: bad serial port count for ttys%d: %d\n",
8696 + info->line, state->count);
8697 + state->count = 0;
8698 + }
8699 + if (state->count) {
8700 + DBG_CNT("before DEC-2");
8701 + MOD_DEC_USE_COUNT;
8702 + restore_flags(flags);
8703 + return;
8704 + }
8705 + info->flags |= ASYNC_CLOSING;
8706 + restore_flags(flags);
8707 + /*
8708 + * Save the termios structure, since this port may have
8709 + * separate termios for callout and dialin.
8710 + */
8711 + if (info->flags & ASYNC_NORMAL_ACTIVE)
8712 + info->state->normal_termios = *tty->termios;
8713 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
8714 + info->state->callout_termios = *tty->termios;
8715 + /*
8716 + * Now we wait for the transmit buffer to clear; and we notify
8717 + * the line discipline to only process XON/XOFF characters.
8718 + */
8719 + tty->closing = 1;
8720 + if (state->closing_wait != ASYNC_CLOSING_WAIT_NONE)
8721 + tty_wait_until_sent(tty, state->closing_wait);
8722 + /*
8723 + * At this point we stop accepting input. To do this, we
8724 + * disable the receive line status interrupts, and tell the
8725 + * interrupt driver to stop checking the data ready bit in the
8726 + * line status register.
8727 + */
8728 + info->IER &= ~UART_IER_RLSI;
8729 + info->read_status_mask &= ~UART_LSR_DR;
8730 + if (info->flags & ASYNC_INITIALIZED) {
8731 + serial_out(info, UART_IER, info->IER);
8732 + /*
8733 + * Before we drop DTR, make sure the UART transmitter
8734 + * has completely drained; this is especially
8735 + * important if there is a transmit FIFO!
8736 + */
8737 + rs_wait_until_sent(tty, info->timeout);
8738 + }
8739 + shutdown(info);
8740 + if (tty->driver.flush_buffer)
8741 + tty->driver.flush_buffer(tty);
8742 + tty_ldisc_flush(tty);
8743 + tty->closing = 0;
8744 + info->event = 0;
8745 + info->tty = 0;
8746 + if (info->blocked_open) {
8747 + if (state->close_delay) {
8748 + set_current_state(TASK_INTERRUPTIBLE);
8749 + schedule_timeout(state->close_delay);
8750 + }
8751 + wake_up_interruptible(&info->open_wait);
8752 + }
8753 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
8754 + ASYNC_CLOSING);
8755 + wake_up_interruptible(&info->close_wait);
8756 + MOD_DEC_USE_COUNT;
8757 +}
8758 +
8759 +/*
8760 + * rs_wait_until_sent() --- wait until the transmitter is empty
8761 + */
8762 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
8763 +{
8764 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8765 + unsigned long orig_jiffies, char_time;
8766 + int lsr;
8767 +
8768 + if (serial_paranoia_check(info, tty->device, "rs_wait_until_sent"))
8769 + return;
8770 +
8771 + if (info->state->type == PORT_UNKNOWN)
8772 + return;
8773 +
8774 + if (info->xmit_fifo_size == 0)
8775 + return; /* Just in case.... */
8776 +
8777 + orig_jiffies = jiffies;
8778 + /*
8779 + * Set the check interval to be 1/5 of the estimated time to
8780 + * send a single character, and make it at least 1. The check
8781 + * interval should also be less than the timeout.
8782 + *
8783 + * Note: we have to use pretty tight timings here to satisfy
8784 + * the NIST-PCTS.
8785 + */
8786 + char_time = (info->timeout - HZ/50) / info->xmit_fifo_size;
8787 + char_time = char_time / 5;
8788 + if (char_time == 0)
8789 + char_time = 1;
8790 + if (timeout && timeout < char_time)
8791 + char_time = timeout;
8792 + /*
8793 + * If the transmitter hasn't cleared in twice the approximate
8794 + * amount of time to send the entire FIFO, it probably won't
8795 + * ever clear. This assumes the UART isn't doing flow
8796 + * control, which is currently the case. Hence, if it ever
8797 + * takes longer than info->timeout, this is probably due to a
8798 + * UART bug of some kind. So, we clamp the timeout parameter at
8799 + * 2*info->timeout.
8800 + */
8801 + if (!timeout || timeout > 2*info->timeout)
8802 + timeout = 2*info->timeout;
8803 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8804 + printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
8805 + printk("jiff=%lu...", jiffies);
8806 +#endif
8807 + while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
8808 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8809 + printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
8810 +#endif
8811 + set_current_state(TASK_INTERRUPTIBLE);
8812 + schedule_timeout(char_time);
8813 + if (signal_pending(current))
8814 + break;
8815 + if (timeout && time_after(jiffies, orig_jiffies + timeout))
8816 + break;
8817 + }
8818 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8819 + printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
8820 +#endif
8821 +}
8822 +
8823 +/*
8824 + * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
8825 + */
8826 +static void rs_hangup(struct tty_struct *tty)
8827 +{
8828 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8829 + struct serial_state *state = info->state;
8830 +
8831 + if (serial_paranoia_check(info, tty->device, "rs_hangup"))
8832 + return;
8833 +
8834 + state = info->state;
8835 +
8836 + rs_flush_buffer(tty);
8837 + if (info->flags & ASYNC_CLOSING)
8838 + return;
8839 + shutdown(info);
8840 + info->event = 0;
8841 + state->count = 0;
8842 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
8843 + info->tty = 0;
8844 + wake_up_interruptible(&info->open_wait);
8845 +}
8846 +
8847 +/*
8848 + * ------------------------------------------------------------
8849 + * rs_open() and friends
8850 + * ------------------------------------------------------------
8851 + */
8852 +static int block_til_ready(struct tty_struct *tty, struct file * filp,
8853 + struct async_struct *info)
8854 +{
8855 + DECLARE_WAITQUEUE(wait, current);
8856 + struct serial_state *state = info->state;
8857 + int retval;
8858 + int do_clocal = 0, extra_count = 0;
8859 + unsigned long flags;
8860 +
8861 + /*
8862 + * If the device is in the middle of being closed, then block
8863 + * until it's done, and then try again.
8864 + */
8865 + if (tty_hung_up_p(filp) ||
8866 + (info->flags & ASYNC_CLOSING)) {
8867 + if (info->flags & ASYNC_CLOSING)
8868 + interruptible_sleep_on(&info->close_wait);
8869 +#ifdef SERIAL_DO_RESTART
8870 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
8871 + -EAGAIN : -ERESTARTSYS);
8872 +#else
8873 + return -EAGAIN;
8874 +#endif
8875 + }
8876 +
8877 + /*
8878 + * If this is a callout device, then just make sure the normal
8879 + * device isn't being used.
8880 + */
8881 + if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
8882 + if (info->flags & ASYNC_NORMAL_ACTIVE)
8883 + return -EBUSY;
8884 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
8885 + (info->flags & ASYNC_SESSION_LOCKOUT) &&
8886 + (info->session != current->session))
8887 + return -EBUSY;
8888 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
8889 + (info->flags & ASYNC_PGRP_LOCKOUT) &&
8890 + (info->pgrp != current->pgrp))
8891 + return -EBUSY;
8892 + info->flags |= ASYNC_CALLOUT_ACTIVE;
8893 + return 0;
8894 + }
8895 +
8896 + /*
8897 + * If non-blocking mode is set, or the port is not enabled,
8898 + * then make the check up front and then exit.
8899 + */
8900 + if ((filp->f_flags & O_NONBLOCK) ||
8901 + (tty->flags & (1 << TTY_IO_ERROR))) {
8902 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
8903 + return -EBUSY;
8904 + info->flags |= ASYNC_NORMAL_ACTIVE;
8905 + return 0;
8906 + }
8907 +
8908 + if (info->flags & ASYNC_CALLOUT_ACTIVE) {
8909 + if (state->normal_termios.c_cflag & CLOCAL)
8910 + do_clocal = 1;
8911 + } else {
8912 + if (tty->termios->c_cflag & CLOCAL)
8913 + do_clocal = 1;
8914 + }
8915 +
8916 + /*
8917 + * Block waiting for the carrier detect and the line to become
8918 + * free (i.e., not in use by the callout). While we are in
8919 + * this loop, state->count is dropped by one, so that
8920 + * rs_close() knows when to free things. We restore it upon
8921 + * exit, either normal or abnormal.
8922 + */
8923 + retval = 0;
8924 + add_wait_queue(&info->open_wait, &wait);
8925 +#ifdef SERIAL_DEBUG_OPEN
8926 + printk("block_til_ready before block: ttys%d, count = %d\n",
8927 + state->line, state->count);
8928 +#endif
8929 + save_flags(flags); cli();
8930 + if (!tty_hung_up_p(filp)) {
8931 + extra_count = 1;
8932 + state->count--;
8933 + }
8934 + restore_flags(flags);
8935 + info->blocked_open++;
8936 + while (1) {
8937 + save_flags(flags); cli();
8938 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
8939 + (tty->termios->c_cflag & CBAUD))
8940 + serial_out(info, UART_MCR,
8941 + serial_inp(info, UART_MCR) |
8942 + (UART_MCR_DTR | UART_MCR_RTS));
8943 + restore_flags(flags);
8944 + set_current_state(TASK_INTERRUPTIBLE);
8945 + if (tty_hung_up_p(filp) ||
8946 + !(info->flags & ASYNC_INITIALIZED)) {
8947 +#ifdef SERIAL_DO_RESTART
8948 + if (info->flags & ASYNC_HUP_NOTIFY)
8949 + retval = -EAGAIN;
8950 + else
8951 + retval = -ERESTARTSYS;
8952 +#else
8953 + retval = -EAGAIN;
8954 +#endif
8955 + break;
8956 + }
8957 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
8958 + !(info->flags & ASYNC_CLOSING) &&
8959 + (do_clocal || (serial_in(info, UART_MSR) &
8960 + UART_MSR_DCD)))
8961 + break;
8962 + if (signal_pending(current)) {
8963 + retval = -ERESTARTSYS;
8964 + break;
8965 + }
8966 +#ifdef SERIAL_DEBUG_OPEN
8967 + printk("block_til_ready blocking: ttys%d, count = %d\n",
8968 + info->line, state->count);
8969 +#endif
8970 + schedule();
8971 + }
8972 + set_current_state(TASK_RUNNING);
8973 + remove_wait_queue(&info->open_wait, &wait);
8974 + if (extra_count)
8975 + state->count++;
8976 + info->blocked_open--;
8977 +#ifdef SERIAL_DEBUG_OPEN
8978 + printk("block_til_ready after blocking: ttys%d, count = %d\n",
8979 + info->line, state->count);
8980 +#endif
8981 + if (retval)
8982 + return retval;
8983 + info->flags |= ASYNC_NORMAL_ACTIVE;
8984 + return 0;
8985 +}
8986 +
8987 +static int get_async_struct(int line, struct async_struct **ret_info)
8988 +{
8989 + struct async_struct *info;
8990 + struct serial_state *sstate;
8991 +
8992 + sstate = rs_table + line;
8993 + sstate->count++;
8994 + if (sstate->info) {
8995 + *ret_info = sstate->info;
8996 + return 0;
8997 + }
8998 + info = kmalloc(sizeof(struct async_struct), GFP_KERNEL);
8999 + if (!info) {
9000 + sstate->count--;
9001 + return -ENOMEM;
9002 + }
9003 + memset(info, 0, sizeof(struct async_struct));
9004 + init_waitqueue_head(&info->open_wait);
9005 + init_waitqueue_head(&info->close_wait);
9006 + init_waitqueue_head(&info->delta_msr_wait);
9007 + info->magic = SERIAL_MAGIC;
9008 + info->port = sstate->port;
9009 + info->flags = sstate->flags;
9010 + info->io_type = sstate->io_type;
9011 + info->iomem_base = sstate->iomem_base;
9012 + info->iomem_reg_shift = sstate->iomem_reg_shift;
9013 + info->xmit_fifo_size = sstate->xmit_fifo_size;
9014 + info->line = line;
9015 + info->tqueue.routine = do_softint;
9016 + info->tqueue.data = info;
9017 + info->state = sstate;
9018 + if (sstate->info) {
9019 + kfree(info);
9020 + *ret_info = sstate->info;
9021 + return 0;
9022 + }
9023 + *ret_info = sstate->info = info;
9024 + return 0;
9025 +}
9026 +
9027 +/*
9028 + * This routine is called whenever a serial port is opened. It
9029 + * enables interrupts for a serial port, linking in its async structure into
9030 + * the IRQ chain. It also performs the serial-specific
9031 + * initialization for the tty structure.
9032 + *
9033 + * Note that on failure, we don't decrement the module use count - the tty
9034 + * later will call rs_close, which will decrement it for us as long as
9035 + * tty->driver_data is set non-NULL. --rmk
9036 + */
9037 +static int rs_open(struct tty_struct *tty, struct file * filp)
9038 +{
9039 + struct async_struct *info;
9040 + int retval, line;
9041 + unsigned long page;
9042 +
9043 + MOD_INC_USE_COUNT;
9044 + line = MINOR(tty->device) - tty->driver.minor_start;
9045 + if ((line < 0) || (line >= NR_PORTS)) {
9046 + MOD_DEC_USE_COUNT;
9047 + return -ENODEV;
9048 + }
9049 + retval = get_async_struct(line, &info);
9050 + if (retval) {
9051 + MOD_DEC_USE_COUNT;
9052 + return retval;
9053 + }
9054 + tty->driver_data = info;
9055 + info->tty = tty;
9056 + if (serial_paranoia_check(info, tty->device, "rs_open"))
9057 + return -ENODEV;
9058 +
9059 +#ifdef SERIAL_DEBUG_OPEN
9060 + printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line,
9061 + info->state->count);
9062 +#endif
9063 +#if (LINUX_VERSION_CODE > 0x20100)
9064 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
9065 +#endif
9066 +
9067 + /*
9068 + * This relies on lock_kernel() stuff so wants tidying for 2.5
9069 + */
9070 + if (!tmp_buf) {
9071 + page = get_zeroed_page(GFP_KERNEL);
9072 + if (!page)
9073 + return -ENOMEM;
9074 + if (tmp_buf)
9075 + free_page(page);
9076 + else
9077 + tmp_buf = (unsigned char *) page;
9078 + }
9079 +
9080 + /*
9081 + * If the port is the middle of closing, bail out now
9082 + */
9083 + if (tty_hung_up_p(filp) ||
9084 + (info->flags & ASYNC_CLOSING)) {
9085 + if (info->flags & ASYNC_CLOSING)
9086 + interruptible_sleep_on(&info->close_wait);
9087 +#ifdef SERIAL_DO_RESTART
9088 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
9089 + -EAGAIN : -ERESTARTSYS);
9090 +#else
9091 + return -EAGAIN;
9092 +#endif
9093 + }
9094 +
9095 + /*
9096 + * Start up serial port
9097 + */
9098 + retval = startup(info);
9099 + if (retval)
9100 + return retval;
9101 +
9102 + retval = block_til_ready(tty, filp, info);
9103 + if (retval) {
9104 +#ifdef SERIAL_DEBUG_OPEN
9105 + printk("rs_open returning after block_til_ready with %d\n",
9106 + retval);
9107 +#endif
9108 + return retval;
9109 + }
9110 +
9111 + if ((info->state->count == 1) &&
9112 + (info->flags & ASYNC_SPLIT_TERMIOS)) {
9113 + if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
9114 + *tty->termios = info->state->normal_termios;
9115 + else
9116 + *tty->termios = info->state->callout_termios;
9117 + change_speed(info, 0);
9118 + }
9119 +#ifdef CONFIG_SERIAL_CONSOLE
9120 + if (sercons.cflag && sercons.index == line) {
9121 + tty->termios->c_cflag = sercons.cflag;
9122 + sercons.cflag = 0;
9123 + change_speed(info, 0);
9124 + }
9125 +#endif
9126 + info->session = current->session;
9127 + info->pgrp = current->pgrp;
9128 +
9129 +#ifdef SERIAL_DEBUG_OPEN
9130 + printk("rs_open ttys%d successful...", info->line);
9131 +#endif
9132 + return 0;
9133 +}
9134 +
9135 +/*
9136 + * /proc fs routines....
9137 + */
9138 +
9139 +static inline int line_info(char *buf, struct serial_state *state)
9140 +{
9141 + struct async_struct *info = state->info, scr_info;
9142 + char stat_buf[30], control, status;
9143 + int ret;
9144 + unsigned long flags;
9145 +
9146 + /*
9147 + * Return zero characters for ports not claimed by driver.
9148 + */
9149 + if (state->type == PORT_UNKNOWN) {
9150 + return 0; /* ignore unused ports */
9151 + }
9152 +
9153 + ret = sprintf(buf, "%d: uart:%s port:%lX irq:%d",
9154 + state->line, uart_config[state->type].name,
9155 + (state->port ? state->port : (long)state->iomem_base),
9156 + state->irq);
9157 +
9158 + /*
9159 + * Figure out the current RS-232 lines
9160 + */
9161 + if (!info) {
9162 + info = &scr_info; /* This is just for serial_{in,out} */
9163 +
9164 + info->magic = SERIAL_MAGIC;
9165 + info->port = state->port;
9166 + info->flags = state->flags;
9167 + info->hub6 = state->hub6;
9168 + info->io_type = state->io_type;
9169 + info->iomem_base = state->iomem_base;
9170 + info->iomem_reg_shift = state->iomem_reg_shift;
9171 + info->quot = 0;
9172 + info->tty = 0;
9173 + }
9174 + save_flags(flags); cli();
9175 + status = serial_in(info, UART_MSR);
9176 + control = info != &scr_info ? info->MCR : serial_in(info, UART_MCR);
9177 + restore_flags(flags);
9178 +
9179 + stat_buf[0] = 0;
9180 + stat_buf[1] = 0;
9181 + if (control & UART_MCR_RTS)
9182 + strcat(stat_buf, "|RTS");
9183 + if (status & UART_MSR_CTS)
9184 + strcat(stat_buf, "|CTS");
9185 + if (control & UART_MCR_DTR)
9186 + strcat(stat_buf, "|DTR");
9187 + if (status & UART_MSR_DSR)
9188 + strcat(stat_buf, "|DSR");
9189 + if (status & UART_MSR_DCD)
9190 + strcat(stat_buf, "|CD");
9191 + if (status & UART_MSR_RI)
9192 + strcat(stat_buf, "|RI");
9193 +
9194 + if (info->quot) {
9195 + ret += sprintf(buf+ret, " baud:%d",
9196 + state->baud_base / info->quot);
9197 + }
9198 +
9199 + ret += sprintf(buf+ret, " tx:%d rx:%d",
9200 + state->icount.tx, state->icount.rx);
9201 +
9202 + if (state->icount.frame)
9203 + ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
9204 +
9205 + if (state->icount.parity)
9206 + ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
9207 +
9208 + if (state->icount.brk)
9209 + ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
9210 +
9211 + if (state->icount.overrun)
9212 + ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
9213 +
9214 + /*
9215 + * Last thing is the RS-232 status lines
9216 + */
9217 + ret += sprintf(buf+ret, " %s\n", stat_buf+1);
9218 + return ret;
9219 +}
9220 +
9221 +static int rs_read_proc(char *page, char **start, off_t off, int count,
9222 + int *eof, void *data)
9223 +{
9224 + int i, len = 0, l;
9225 + off_t begin = 0;
9226 +
9227 + len += sprintf(page, "serinfo:1.0 driver:%s%s revision:%s\n",
9228 + serial_version, LOCAL_VERSTRING, serial_revdate);
9229 + for (i = 0; i < NR_PORTS && len < 4000; i++) {
9230 + l = line_info(page + len, &rs_table[i]);
9231 + len += l;
9232 + if (len+begin > off+count)
9233 + goto done;
9234 + if (len+begin < off) {
9235 + begin += len;
9236 + len = 0;
9237 + }
9238 + }
9239 + *eof = 1;
9240 +done:
9241 + if (off >= len+begin)
9242 + return 0;
9243 + *start = page + (off-begin);
9244 + return ((count < begin+len-off) ? count : begin+len-off);
9245 +}
9246 +
9247 +/*
9248 + * ---------------------------------------------------------------------
9249 + * rs_init() and friends
9250 + *
9251 + * rs_init() is called at boot-time to initialize the serial driver.
9252 + * ---------------------------------------------------------------------
9253 + */
9254 +
9255 +/*
9256 + * This routine prints out the appropriate serial driver version
9257 + * number, and identifies which options were configured into this
9258 + * driver.
9259 + */
9260 +static char serial_options[] __initdata =
9261 +#ifdef CONFIG_HUB6
9262 + " HUB-6"
9263 +#define SERIAL_OPT
9264 +#endif
9265 +#ifdef CONFIG_SERIAL_MANY_PORTS
9266 + " MANY_PORTS"
9267 +#define SERIAL_OPT
9268 +#endif
9269 +#ifdef CONFIG_SERIAL_MULTIPORT
9270 + " MULTIPORT"
9271 +#define SERIAL_OPT
9272 +#endif
9273 +#ifdef CONFIG_SERIAL_SHARE_IRQ
9274 + " SHARE_IRQ"
9275 +#define SERIAL_OPT
9276 +#endif
9277 +#ifdef CONFIG_SERIAL_DETECT_IRQ
9278 + " DETECT_IRQ"
9279 +#define SERIAL_OPT
9280 +#endif
9281 +#ifdef ENABLE_SERIAL_PCI
9282 + " SERIAL_PCI"
9283 +#define SERIAL_OPT
9284 +#endif
9285 +#ifdef ENABLE_SERIAL_PNP
9286 + " ISAPNP"
9287 +#define SERIAL_OPT
9288 +#endif
9289 +#ifdef ENABLE_SERIAL_ACPI
9290 + " SERIAL_ACPI"
9291 +#define SERIAL_OPT
9292 +#endif
9293 +#ifdef SERIAL_OPT
9294 + " enabled\n";
9295 +#else
9296 + " no serial options enabled\n";
9297 +#endif
9298 +#undef SERIAL_OPT
9299 +
9300 +static _INLINE_ void show_serial_version(void)
9301 +{
9302 + printk(KERN_INFO "%s version %s%s (%s) with%s", serial_name,
9303 + serial_version, LOCAL_VERSTRING, serial_revdate,
9304 + serial_options);
9305 +}
9306 +
9307 +/*
9308 + * This routine detect the IRQ of a serial port by clearing OUT2 when
9309 + * no UART interrupt are requested (IER = 0) (*GPL*). This seems to work at
9310 + * each time, as long as no other device permanently request the IRQ.
9311 + * If no IRQ is detected, or multiple IRQ appear, this function returns 0.
9312 + * The variable "state" and the field "state->port" should not be null.
9313 + */
9314 +static unsigned detect_uart_irq (struct serial_state * state)
9315 +{
9316 + int irq;
9317 + unsigned long irqs;
9318 + unsigned char save_mcr, save_ier;
9319 + struct async_struct scr_info; /* serial_{in,out} because HUB6 */
9320 +
9321 +#ifdef CONFIG_SERIAL_MANY_PORTS
9322 + unsigned char save_ICP=0; /* no warning */
9323 + unsigned short ICP=0;
9324 +
9325 + if (state->flags & ASYNC_FOURPORT) {
9326 + ICP = (state->port & 0xFE0) | 0x01F;
9327 + save_ICP = inb_p(ICP);
9328 + outb_p(0x80, ICP);
9329 + (void) inb_p(ICP);
9330 + }
9331 +#endif
9332 + scr_info.magic = SERIAL_MAGIC;
9333 + scr_info.state = state;
9334 + scr_info.port = state->port;
9335 + scr_info.flags = state->flags;
9336 +#ifdef CONFIG_HUB6
9337 + scr_info.hub6 = state->hub6;
9338 +#endif
9339 + scr_info.io_type = state->io_type;
9340 + scr_info.iomem_base = state->iomem_base;
9341 + scr_info.iomem_reg_shift = state->iomem_reg_shift;
9342 +
9343 + /* forget possible initially masked and pending IRQ */
9344 + probe_irq_off(probe_irq_on());
9345 + save_mcr = serial_inp(&scr_info, UART_MCR);
9346 + save_ier = serial_inp(&scr_info, UART_IER);
9347 + serial_outp(&scr_info, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
9348 +
9349 + irqs = probe_irq_on();
9350 + serial_outp(&scr_info, UART_MCR, 0);
9351 + udelay (10);
9352 + if (state->flags & ASYNC_FOURPORT) {
9353 + serial_outp(&scr_info, UART_MCR,
9354 + UART_MCR_DTR | UART_MCR_RTS);
9355 + } else {
9356 + serial_outp(&scr_info, UART_MCR,
9357 + UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
9358 + }
9359 + serial_outp(&scr_info, UART_IER, 0x0f); /* enable all intrs */
9360 + (void)serial_inp(&scr_info, UART_LSR);
9361 + (void)serial_inp(&scr_info, UART_RX);
9362 + (void)serial_inp(&scr_info, UART_IIR);
9363 + (void)serial_inp(&scr_info, UART_MSR);
9364 + serial_outp(&scr_info, UART_TX, 0xFF);
9365 + udelay (20);
9366 + irq = probe_irq_off(irqs);
9367 +
9368 + serial_outp(&scr_info, UART_MCR, save_mcr);
9369 + serial_outp(&scr_info, UART_IER, save_ier);
9370 +#ifdef CONFIG_SERIAL_MANY_PORTS
9371 + if (state->flags & ASYNC_FOURPORT)
9372 + outb_p(save_ICP, ICP);
9373 +#endif
9374 + return (irq > 0)? irq : 0;
9375 +}
9376 +
9377 +/*
9378 + * This is a quickie test to see how big the FIFO is.
9379 + * It doesn't work at all the time, more's the pity.
9380 + */
9381 +static int size_fifo(struct async_struct *info)
9382 +{
9383 + unsigned char old_fcr, old_mcr, old_dll, old_dlm;
9384 + int count;
9385 +
9386 + old_fcr = serial_inp(info, UART_FCR);
9387 + old_mcr = serial_inp(info, UART_MCR);
9388 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO |
9389 + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
9390 + serial_outp(info, UART_MCR, UART_MCR_LOOP);
9391 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9392 + old_dll = serial_inp(info, UART_DLL);
9393 + old_dlm = serial_inp(info, UART_DLM);
9394 + serial_outp(info, UART_DLL, 0x01);
9395 + serial_outp(info, UART_DLM, 0x00);
9396 + serial_outp(info, UART_LCR, 0x03);
9397 + for (count = 0; count < 256; count++)
9398 + serial_outp(info, UART_TX, count);
9399 + mdelay(20);
9400 + for (count = 0; (serial_inp(info, UART_LSR) & UART_LSR_DR) &&
9401 + (count < 256); count++)
9402 + serial_inp(info, UART_RX);
9403 + serial_outp(info, UART_FCR, old_fcr);
9404 + serial_outp(info, UART_MCR, old_mcr);
9405 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9406 + serial_outp(info, UART_DLL, old_dll);
9407 + serial_outp(info, UART_DLM, old_dlm);
9408 +
9409 + return count;
9410 +}
9411 +
9412 +/*
9413 + * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
9414 + * When this function is called we know it is at least a StarTech
9415 + * 16650 V2, but it might be one of several StarTech UARTs, or one of
9416 + * its clones. (We treat the broken original StarTech 16650 V1 as a
9417 + * 16550, and why not? Startech doesn't seem to even acknowledge its
9418 + * existence.)
9419 + *
9420 + * What evil have men's minds wrought...
9421 + */
9422 +static void autoconfig_startech_uarts(struct async_struct *info,
9423 + struct serial_state *state,
9424 + unsigned long flags)
9425 +{
9426 + unsigned char scratch, scratch2, scratch3, scratch4;
9427 +
9428 + /*
9429 + * First we check to see if it's an Oxford Semiconductor UART.
9430 + *
9431 + * If we have to do this here because some non-National
9432 + * Semiconductor clone chips lock up if you try writing to the
9433 + * LSR register (which serial_icr_read does)
9434 + */
9435 + if (state->type == PORT_16550A) {
9436 + /*
9437 + * EFR [4] must be set else this test fails
9438 + *
9439 + * This shouldn't be necessary, but Mike Hudson
9440 + * (Exoray@isys.ca) claims that it's needed for 952
9441 + * dual UART's (which are not recommended for new designs).
9442 + */
9443 + info->ACR = 0;
9444 + serial_out(info, UART_LCR, 0xBF);
9445 + serial_out(info, UART_EFR, 0x10);
9446 + serial_out(info, UART_LCR, 0x00);
9447 + /* Check for Oxford Semiconductor 16C950 */
9448 + scratch = serial_icr_read(info, UART_ID1);
9449 + scratch2 = serial_icr_read(info, UART_ID2);
9450 + scratch3 = serial_icr_read(info, UART_ID3);
9451 +
9452 + if (scratch == 0x16 && scratch2 == 0xC9 &&
9453 + (scratch3 == 0x50 || scratch3 == 0x52 ||
9454 + scratch3 == 0x54)) {
9455 + state->type = PORT_16C950;
9456 + state->revision = serial_icr_read(info, UART_REV) |
9457 + (scratch3 << 8);
9458 + return;
9459 + }
9460 + }
9461 +
9462 + /*
9463 + * We check for a XR16C850 by setting DLL and DLM to 0, and
9464 + * then reading back DLL and DLM. If DLM reads back 0x10,
9465 + * then the UART is a XR16C850 and the DLL contains the chip
9466 + * revision. If DLM reads back 0x14, then the UART is a
9467 + * XR16C854.
9468 + *
9469 + */
9470 +
9471 + /* Save the DLL and DLM */
9472 +
9473 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9474 + scratch3 = serial_inp(info, UART_DLL);
9475 + scratch4 = serial_inp(info, UART_DLM);
9476 +
9477 + serial_outp(info, UART_DLL, 0);
9478 + serial_outp(info, UART_DLM, 0);
9479 + scratch2 = serial_inp(info, UART_DLL);
9480 + scratch = serial_inp(info, UART_DLM);
9481 + serial_outp(info, UART_LCR, 0);
9482 +
9483 + if (scratch == 0x10 || scratch == 0x14) {
9484 + if (scratch == 0x10)
9485 + state->revision = scratch2;
9486 + state->type = PORT_16850;
9487 + return;
9488 + }
9489 +
9490 + /* Restore the DLL and DLM */
9491 +
9492 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9493 + serial_outp(info, UART_DLL, scratch3);
9494 + serial_outp(info, UART_DLM, scratch4);
9495 + serial_outp(info, UART_LCR, 0);
9496 + /*
9497 + * We distinguish between the '654 and the '650 by counting
9498 + * how many bytes are in the FIFO. I'm using this for now,
9499 + * since that's the technique that was sent to me in the
9500 + * serial driver update, but I'm not convinced this works.
9501 + * I've had problems doing this in the past. -TYT
9502 + */
9503 + if (size_fifo(info) == 64)
9504 + state->type = PORT_16654;
9505 + else
9506 + state->type = PORT_16650V2;
9507 +}
9508 +
9509 +/*
9510 + * This routine is called by rs_init() to initialize a specific serial
9511 + * port. It determines what type of UART chip this serial port is
9512 + * using: 8250, 16450, 16550, 16550A. The important question is
9513 + * whether or not this UART is a 16550A or not, since this will
9514 + * determine whether or not we can use its FIFO features or not.
9515 + */
9516 +static void autoconfig(struct serial_state * state)
9517 +{
9518 + unsigned char status1, status2, scratch, scratch2, scratch3;
9519 + unsigned char save_lcr, save_mcr;
9520 + struct async_struct *info, scr_info;
9521 + unsigned long flags;
9522 +
9523 + state->type = PORT_UNKNOWN;
9524 +
9525 +#ifdef SERIAL_DEBUG_AUTOCONF
9526 + printk("Testing ttyS%d (0x%04lx, 0x%04x)...\n", state->line,
9527 + state->port, (unsigned) state->iomem_base);
9528 +#endif
9529 +
9530 + if (!CONFIGURED_SERIAL_PORT(state))
9531 + return;
9532 +
9533 + info = &scr_info; /* This is just for serial_{in,out} */
9534 +
9535 + info->magic = SERIAL_MAGIC;
9536 + info->state = state;
9537 + info->port = state->port;
9538 + info->flags = state->flags;
9539 +#ifdef CONFIG_HUB6
9540 + info->hub6 = state->hub6;
9541 +#endif
9542 + info->io_type = state->io_type;
9543 + info->iomem_base = state->iomem_base;
9544 + info->iomem_reg_shift = state->iomem_reg_shift;
9545 +
9546 + save_flags(flags); cli();
9547 +
9548 + if (!(state->flags & ASYNC_BUGGY_UART) &&
9549 + !state->iomem_base) {
9550 + /*
9551 + * Do a simple existence test first; if we fail this,
9552 + * there's no point trying anything else.
9553 + *
9554 + * 0x80 is used as a nonsense port to prevent against
9555 + * false positives due to ISA bus float. The
9556 + * assumption is that 0x80 is a non-existent port;
9557 + * which should be safe since include/asm/io.h also
9558 + * makes this assumption.
9559 + */
9560 + scratch = serial_inp(info, UART_IER);
9561 + serial_outp(info, UART_IER, 0);
9562 +#ifdef __i386__
9563 + outb(0xff, 0x080);
9564 +#endif
9565 + scratch2 = serial_inp(info, UART_IER);
9566 + serial_outp(info, UART_IER, 0x0F);
9567 +#ifdef __i386__
9568 + outb(0, 0x080);
9569 +#endif
9570 + scratch3 = serial_inp(info, UART_IER);
9571 + serial_outp(info, UART_IER, scratch);
9572 + if (scratch2 || scratch3 != 0x0F) {
9573 +#ifdef SERIAL_DEBUG_AUTOCONF
9574 + printk("serial: ttyS%d: simple autoconfig failed "
9575 + "(%02x, %02x)\n", state->line,
9576 + scratch2, scratch3);
9577 +#endif
9578 + restore_flags(flags);
9579 + return; /* We failed; there's nothing here */
9580 + }
9581 + }
9582 +
9583 + save_mcr = serial_in(info, UART_MCR);
9584 + save_lcr = serial_in(info, UART_LCR);
9585 +
9586 + /*
9587 + * Check to see if a UART is really there. Certain broken
9588 + * internal modems based on the Rockwell chipset fail this
9589 + * test, because they apparently don't implement the loopback
9590 + * test mode. So this test is skipped on the COM 1 through
9591 + * COM 4 ports. This *should* be safe, since no board
9592 + * manufacturer would be stupid enough to design a board
9593 + * that conflicts with COM 1-4 --- we hope!
9594 + */
9595 + if (!(state->flags & ASYNC_SKIP_TEST)) {
9596 + serial_outp(info, UART_MCR, UART_MCR_LOOP | 0x0A);
9597 + status1 = serial_inp(info, UART_MSR) & 0xF0;
9598 + serial_outp(info, UART_MCR, save_mcr);
9599 + if (status1 != 0x90) {
9600 +#ifdef SERIAL_DEBUG_AUTOCONF
9601 + printk("serial: ttyS%d: no UART loopback failed\n",
9602 + state->line);
9603 +#endif
9604 + restore_flags(flags);
9605 + return;
9606 + }
9607 + }
9608 + serial_outp(info, UART_LCR, 0xBF); /* set up for StarTech test */
9609 + serial_outp(info, UART_EFR, 0); /* EFR is the same as FCR */
9610 + serial_outp(info, UART_LCR, 0);
9611 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9612 + scratch = serial_in(info, UART_IIR) >> 6;
9613 + switch (scratch) {
9614 + case 0:
9615 + state->type = PORT_16450;
9616 + break;
9617 + case 1:
9618 + state->type = PORT_UNKNOWN;
9619 + break;
9620 + case 2:
9621 + state->type = PORT_16550;
9622 + break;
9623 + case 3:
9624 + state->type = PORT_16550A;
9625 + break;
9626 + }
9627 + if (state->type == PORT_16550A) {
9628 + /* Check for Startech UART's */
9629 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9630 + if (serial_in(info, UART_EFR) == 0) {
9631 + serial_outp(info, UART_EFR, 0xA8);
9632 + if (serial_in(info, UART_EFR) == 0) {
9633 + /* We are a NS16552D/Motorola
9634 + * 8xxx DUART, stop. */
9635 + goto out;
9636 + }
9637 + state->type = PORT_16650;
9638 + serial_outp(info, UART_EFR, 0);
9639 + } else {
9640 + serial_outp(info, UART_LCR, 0xBF);
9641 + if (serial_in(info, UART_EFR) == 0)
9642 + autoconfig_startech_uarts(info, state, flags);
9643 + }
9644 + }
9645 + if (state->type == PORT_16550A) {
9646 + /* Check for TI 16750 */
9647 + serial_outp(info, UART_LCR, save_lcr | UART_LCR_DLAB);
9648 + serial_outp(info, UART_FCR,
9649 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
9650 + scratch = serial_in(info, UART_IIR) >> 5;
9651 + if (scratch == 7) {
9652 + /*
9653 + * If this is a 16750, and not a cheap UART
9654 + * clone, then it should only go into 64 byte
9655 + * mode if the UART_FCR7_64BYTE bit was set
9656 + * while UART_LCR_DLAB was latched.
9657 + */
9658 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9659 + serial_outp(info, UART_LCR, 0);
9660 + serial_outp(info, UART_FCR,
9661 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
9662 + scratch = serial_in(info, UART_IIR) >> 5;
9663 + if (scratch == 6)
9664 + state->type = PORT_16750;
9665 + }
9666 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9667 + }
9668 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
9669 + if (state->type == PORT_16550A) {
9670 + int i;
9671 +
9672 + for (i = 0 ; i < PORT_RSA_MAX ; ++i) {
9673 + if (!probe_rsa[i] && !force_rsa[i])
9674 + break;
9675 + if (((probe_rsa[i] != state->port) ||
9676 + check_region(state->port + UART_RSA_BASE, 16)) &&
9677 + (force_rsa[i] != state->port))
9678 + continue;
9679 + if (!enable_rsa(info))
9680 + continue;
9681 + state->type = PORT_RSA;
9682 + state->baud_base = SERIAL_RSA_BAUD_BASE;
9683 + break;
9684 + }
9685 + }
9686 +#endif
9687 +out:
9688 + serial_outp(info, UART_LCR, save_lcr);
9689 + if (state->type == PORT_16450) {
9690 + scratch = serial_in(info, UART_SCR);
9691 + serial_outp(info, UART_SCR, 0xa5);
9692 + status1 = serial_in(info, UART_SCR);
9693 + serial_outp(info, UART_SCR, 0x5a);
9694 + status2 = serial_in(info, UART_SCR);
9695 + serial_outp(info, UART_SCR, scratch);
9696 +
9697 + if ((status1 != 0xa5) || (status2 != 0x5a))
9698 + state->type = PORT_8250;
9699 + }
9700 + state->xmit_fifo_size = uart_config[state->type].dfl_xmit_fifo_size;
9701 +
9702 + if (state->type == PORT_UNKNOWN) {
9703 + restore_flags(flags);
9704 + return;
9705 + }
9706 +
9707 + if (info->port) {
9708 +#ifdef CONFIG_SERIAL_RSA
9709 + if (state->type == PORT_RSA)
9710 + request_region(info->port + UART_RSA_BASE, 16,
9711 + "serial_rsa(auto)");
9712 + else
9713 +#endif
9714 + request_region(info->port,8,"serial(auto)");
9715 + }
9716 +
9717 + /*
9718 + * Reset the UART.
9719 + */
9720 +#ifdef CONFIG_SERIAL_RSA
9721 + if (state->type == PORT_RSA)
9722 + serial_outp(info, UART_RSA_FRR, 0);
9723 +#endif
9724 + serial_outp(info, UART_MCR, save_mcr);
9725 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
9726 + UART_FCR_CLEAR_RCVR |
9727 + UART_FCR_CLEAR_XMIT));
9728 + serial_outp(info, UART_FCR, 0);
9729 + (void)serial_in(info, UART_RX);
9730 + serial_outp(info, UART_IER, 0);
9731 +
9732 + restore_flags(flags);
9733 +}
9734 +
9735 +int register_serial(struct serial_struct *req);
9736 +void unregister_serial(int line);
9737 +
9738 +#if (LINUX_VERSION_CODE > 0x20100)
9739 +EXPORT_SYMBOL(register_serial);
9740 +EXPORT_SYMBOL(unregister_serial);
9741 +#else
9742 +static struct symbol_table serial_syms = {
9743 +#include <linux/symtab_begin.h>
9744 + X(register_serial),
9745 + X(unregister_serial),
9746 +#include <linux/symtab_end.h>
9747 +};
9748 +#endif
9749 +
9750 +
9751 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
9752 +
9753 +static void __devinit printk_pnp_dev_id(unsigned short vendor,
9754 + unsigned short device)
9755 +{
9756 + printk("%c%c%c%x%x%x%x",
9757 + 'A' + ((vendor >> 2) & 0x3f) - 1,
9758 + 'A' + (((vendor & 3) << 3) | ((vendor >> 13) & 7)) - 1,
9759 + 'A' + ((vendor >> 8) & 0x1f) - 1,
9760 + (device >> 4) & 0x0f,
9761 + device & 0x0f,
9762 + (device >> 12) & 0x0f,
9763 + (device >> 8) & 0x0f);
9764 +}
9765 +
9766 +static _INLINE_ int get_pci_port(struct pci_dev *dev,
9767 + struct pci_board *board,
9768 + struct serial_struct *req,
9769 + int idx)
9770 +{
9771 + unsigned long port;
9772 + int base_idx;
9773 + int max_port;
9774 + int offset;
9775 +
9776 + base_idx = SPCI_FL_GET_BASE(board->flags);
9777 + if (board->flags & SPCI_FL_BASE_TABLE)
9778 + base_idx += idx;
9779 +
9780 + if (board->flags & SPCI_FL_REGION_SZ_CAP) {
9781 + max_port = pci_resource_len(dev, base_idx) / 8;
9782 + if (idx >= max_port)
9783 + return 1;
9784 + }
9785 +
9786 + offset = board->first_uart_offset;
9787 +
9788 + /* Timedia/SUNIX uses a mixture of BARs and offsets */
9789 + /* Ugh, this is ugly as all hell --- TYT */
9790 + if(dev->vendor == PCI_VENDOR_ID_TIMEDIA ) /* 0x1409 */
9791 + switch(idx) {
9792 + case 0: base_idx=0;
9793 + break;
9794 + case 1: base_idx=0; offset=8;
9795 + break;
9796 + case 2: base_idx=1;
9797 + break;
9798 + case 3: base_idx=1; offset=8;
9799 + break;
9800 + case 4: /* BAR 2*/
9801 + case 5: /* BAR 3 */
9802 + case 6: /* BAR 4*/
9803 + case 7: base_idx=idx-2; /* BAR 5*/
9804 + }
9805 +
9806 + /* Some Titan cards are also a little weird */
9807 + if (dev->vendor == PCI_VENDOR_ID_TITAN &&
9808 + (dev->device == PCI_DEVICE_ID_TITAN_400L ||
9809 + dev->device == PCI_DEVICE_ID_TITAN_800L)) {
9810 + switch (idx) {
9811 + case 0: base_idx = 1;
9812 + break;
9813 + case 1: base_idx = 2;
9814 + break;
9815 + default:
9816 + base_idx = 4;
9817 + offset = 8 * (idx - 2);
9818 + }
9819 +
9820 + }
9821 +
9822 + /* HP's Diva chip puts the 4th/5th serial port further out, and
9823 + * some serial ports are supposed to be hidden on certain models.
9824 + */
9825 + if (dev->vendor == PCI_VENDOR_ID_HP &&
9826 + dev->device == PCI_DEVICE_ID_HP_SAS) {
9827 + switch (dev->subsystem_device) {
9828 + case 0x104B: /* Maestro */
9829 + if (idx == 3) idx++;
9830 + break;
9831 + case 0x1282: /* Everest / Longs Peak */
9832 + if (idx > 0) idx++;
9833 + if (idx > 2) idx++;
9834 + break;
9835 + }
9836 + if (idx > 2) {
9837 + offset = 0x18;
9838 + }
9839 + }
9840 +
9841 + port = pci_resource_start(dev, base_idx) + offset;
9842 +
9843 + if ((board->flags & SPCI_FL_BASE_TABLE) == 0)
9844 + port += idx * (board->uart_offset ? board->uart_offset : 8);
9845 +
9846 + if (IS_PCI_REGION_IOPORT(dev, base_idx)) {
9847 + req->port = port;
9848 + if (HIGH_BITS_OFFSET)
9849 + req->port_high = port >> HIGH_BITS_OFFSET;
9850 + else
9851 + req->port_high = 0;
9852 + return 0;
9853 + }
9854 + req->io_type = SERIAL_IO_MEM;
9855 + req->iomem_base = ioremap(port, board->uart_offset);
9856 + req->iomem_reg_shift = board->reg_shift;
9857 + req->port = 0;
9858 + return 0;
9859 +}
9860 +
9861 +static _INLINE_ int get_pci_irq(struct pci_dev *dev,
9862 + struct pci_board *board,
9863 + int idx)
9864 +{
9865 + int base_idx;
9866 +
9867 + if ((board->flags & SPCI_FL_IRQRESOURCE) == 0)
9868 + return dev->irq;
9869 +
9870 + base_idx = SPCI_FL_GET_IRQBASE(board->flags);
9871 + if (board->flags & SPCI_FL_IRQ_TABLE)
9872 + base_idx += idx;
9873 +
9874 + return PCI_IRQ_RESOURCE(dev, base_idx);
9875 +}
9876 +
9877 +/*
9878 + * Common enabler code shared by both PCI and ISAPNP probes
9879 + */
9880 +static void __devinit start_pci_pnp_board(struct pci_dev *dev,
9881 + struct pci_board *board)
9882 +{
9883 + int k, line;
9884 + struct serial_struct serial_req;
9885 + int base_baud;
9886 +
9887 + if (PREPARE_FUNC(dev) && (PREPARE_FUNC(dev))(dev) < 0) {
9888 + printk("serial: PNP device '");
9889 + printk_pnp_dev_id(dev->vendor, dev->device);
9890 + printk("' prepare failed\n");
9891 + return;
9892 + }
9893 +
9894 + if (ACTIVATE_FUNC(dev) && (ACTIVATE_FUNC(dev))(dev) < 0) {
9895 + printk("serial: PNP device '");
9896 + printk_pnp_dev_id(dev->vendor, dev->device);
9897 + printk("' activate failed\n");
9898 + return;
9899 + }
9900 +
9901 + /*
9902 + * Run the initialization function, if any
9903 + */
9904 + if (board->init_fn && ((board->init_fn)(dev, board, 1) != 0))
9905 + return;
9906 +
9907 + /*
9908 + * Register the serial board in the array if we need to
9909 + * shutdown the board on a module unload or card removal
9910 + */
9911 + if (DEACTIVATE_FUNC(dev) || board->init_fn) {
9912 + for (k=0; k < NR_PCI_BOARDS; k++)
9913 + if (serial_pci_board[k].dev == 0)
9914 + break;
9915 + if (k >= NR_PCI_BOARDS)
9916 + return;
9917 + serial_pci_board[k].board = *board;
9918 + serial_pci_board[k].dev = dev;
9919 + }
9920 +
9921 + base_baud = board->base_baud;
9922 + if (!base_baud)
9923 + base_baud = BASE_BAUD;
9924 + memset(&serial_req, 0, sizeof(serial_req));
9925 +
9926 + for (k=0; k < board->num_ports; k++) {
9927 + serial_req.irq = get_pci_irq(dev, board, k);
9928 + if (get_pci_port(dev, board, &serial_req, k))
9929 + break;
9930 + serial_req.flags = ASYNC_SKIP_TEST | ASYNC_AUTOPROBE;
9931 +#ifdef SERIAL_DEBUG_PCI
9932 + printk("Setup PCI/PNP port: port %x, irq %d, type %d\n",
9933 + serial_req.port, serial_req.irq, serial_req.io_type);
9934 +#endif
9935 + line = register_serial(&serial_req);
9936 + if (line < 0)
9937 + break;
9938 + rs_table[line].baud_base = base_baud;
9939 + rs_table[line].dev = dev;
9940 + }
9941 +}
9942 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
9943 +
9944 +#ifdef ENABLE_SERIAL_PCI
9945 +/*
9946 + * Some PCI serial cards using the PLX 9050 PCI interface chip require
9947 + * that the card interrupt be explicitly enabled or disabled. This
9948 + * seems to be mainly needed on card using the PLX which also use I/O
9949 + * mapped memory.
9950 + */
9951 +static int __devinit
9952 +pci_plx9050_fn(struct pci_dev *dev, struct pci_board *board, int enable)
9953 +{
9954 + u8 data, *p, irq_config;
9955 + int pci_config;
9956 +
9957 + irq_config = 0x41;
9958 + pci_config = PCI_COMMAND_MEMORY;
9959 + if (dev->vendor == PCI_VENDOR_ID_PANACOM)
9960 + irq_config = 0x43;
9961 + if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
9962 + (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
9963 + /*
9964 + * As the megawolf cards have the int pins active
9965 + * high, and have 2 UART chips, both ints must be
9966 + * enabled on the 9050. Also, the UARTS are set in
9967 + * 16450 mode by default, so we have to enable the
9968 + * 16C950 'enhanced' mode so that we can use the deep
9969 + * FIFOs
9970 + */
9971 + irq_config = 0x5b;
9972 + pci_config = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
9973 + }
9974 +
9975 + pci_read_config_byte(dev, PCI_COMMAND, &data);
9976 +
9977 + if (enable)
9978 + pci_write_config_byte(dev, PCI_COMMAND,
9979 + data | pci_config);
9980 +
9981 + /* enable/disable interrupts */
9982 + p = ioremap(pci_resource_start(dev, 0), 0x80);
9983 + writel(enable ? irq_config : 0x00, (unsigned long)p + 0x4c);
9984 + iounmap(p);
9985 +
9986 + if (!enable)
9987 + pci_write_config_byte(dev, PCI_COMMAND,
9988 + data & ~pci_config);
9989 + return 0;
9990 +}
9991 +
9992 +
9993 +/*
9994 + * SIIG serial cards have an PCI interface chip which also controls
9995 + * the UART clocking frequency. Each UART can be clocked independently
9996 + * (except cards equiped with 4 UARTs) and initial clocking settings
9997 + * are stored in the EEPROM chip. It can cause problems because this
9998 + * version of serial driver doesn't support differently clocked UART's
9999 + * on single PCI card. To prevent this, initialization functions set
10000 + * high frequency clocking for all UART's on given card. It is safe (I
10001 + * hope) because it doesn't touch EEPROM settings to prevent conflicts
10002 + * with other OSes (like M$ DOS).
10003 + *
10004 + * SIIG support added by Andrey Panin <pazke@mail.tp.ru>, 10/1999
10005 + *
10006 + * There is two family of SIIG serial cards with different PCI
10007 + * interface chip and different configuration methods:
10008 + * - 10x cards have control registers in IO and/or memory space;
10009 + * - 20x cards have control registers in standard PCI configuration space.
10010 + *
10011 + * SIIG initialization functions exported for use by parport_serial.c module.
10012 + */
10013 +
10014 +#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
10015 +#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
10016 +
10017 +int __devinit
10018 +pci_siig10x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10019 +{
10020 + u16 data, *p;
10021 +
10022 + if (!enable) return 0;
10023 +
10024 + p = ioremap(pci_resource_start(dev, 0), 0x80);
10025 +
10026 + switch (dev->device & 0xfff8) {
10027 + case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
10028 + data = 0xffdf;
10029 + break;
10030 + case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
10031 + data = 0xf7ff;
10032 + break;
10033 + default: /* 1S1P, 4S */
10034 + data = 0xfffb;
10035 + break;
10036 + }
10037 +
10038 + writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
10039 + iounmap(p);
10040 + return 0;
10041 +}
10042 +EXPORT_SYMBOL(pci_siig10x_fn);
10043 +
10044 +#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
10045 +#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
10046 +
10047 +int __devinit
10048 +pci_siig20x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10049 +{
10050 + u8 data;
10051 +
10052 + if (!enable) return 0;
10053 +
10054 + /* Change clock frequency for the first UART. */
10055 + pci_read_config_byte(dev, 0x6f, &data);
10056 + pci_write_config_byte(dev, 0x6f, data & 0xef);
10057 +
10058 + /* If this card has 2 UART, we have to do the same with second UART. */
10059 + if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
10060 + ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
10061 + pci_read_config_byte(dev, 0x73, &data);
10062 + pci_write_config_byte(dev, 0x73, data & 0xef);
10063 + }
10064 + return 0;
10065 +}
10066 +EXPORT_SYMBOL(pci_siig20x_fn);
10067 +
10068 +/* Added for EKF Intel i960 serial boards */
10069 +static int __devinit
10070 +pci_inteli960ni_fn(struct pci_dev *dev,
10071 + struct pci_board *board,
10072 + int enable)
10073 +{
10074 + unsigned long oldval;
10075 +
10076 + if (!(pci_get_subdevice(dev) & 0x1000))
10077 + return(-1);
10078 +
10079 + if (!enable) /* is there something to deinit? */
10080 + return(0);
10081 +
10082 +#ifdef SERIAL_DEBUG_PCI
10083 + printk(KERN_DEBUG " Subsystem ID %lx (intel 960)\n",
10084 + (unsigned long) board->subdevice);
10085 +#endif
10086 + /* is firmware started? */
10087 + pci_read_config_dword(dev, 0x44, (void*) &oldval);
10088 + if (oldval == 0x00001000L) { /* RESET value */
10089 + printk(KERN_DEBUG "Local i960 firmware missing");
10090 + return(-1);
10091 + }
10092 + return(0);
10093 +}
10094 +
10095 +/*
10096 + * Timedia has an explosion of boards, and to avoid the PCI table from
10097 + * growing *huge*, we use this function to collapse some 70 entries
10098 + * in the PCI table into one, for sanity's and compactness's sake.
10099 + */
10100 +static unsigned short timedia_single_port[] = {
10101 + 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 };
10102 +static unsigned short timedia_dual_port[] = {
10103 + 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
10104 + 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
10105 + 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
10106 + 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
10107 + 0xD079, 0 };
10108 +static unsigned short timedia_quad_port[] = {
10109 + 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
10110 + 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
10111 + 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
10112 + 0xB157, 0 };
10113 +static unsigned short timedia_eight_port[] = {
10114 + 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
10115 + 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 };
10116 +static struct timedia_struct {
10117 + int num;
10118 + unsigned short *ids;
10119 +} timedia_data[] = {
10120 + { 1, timedia_single_port },
10121 + { 2, timedia_dual_port },
10122 + { 4, timedia_quad_port },
10123 + { 8, timedia_eight_port },
10124 + { 0, 0 }
10125 +};
10126 +
10127 +static int __devinit
10128 +pci_timedia_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10129 +{
10130 + int i, j;
10131 + unsigned short *ids;
10132 +
10133 + if (!enable)
10134 + return 0;
10135 +
10136 + for (i=0; timedia_data[i].num; i++) {
10137 + ids = timedia_data[i].ids;
10138 + for (j=0; ids[j]; j++) {
10139 + if (pci_get_subdevice(dev) == ids[j]) {
10140 + board->num_ports = timedia_data[i].num;
10141 + return 0;
10142 + }
10143 + }
10144 + }
10145 + return 0;
10146 +}
10147 +
10148 +/*
10149 + * HP's Remote Management Console. The Diva chip came in several
10150 + * different versions. N-class, L2000 and A500 have two Diva chips, each
10151 + * with 3 UARTs (the third UART on the second chip is unused). Superdome
10152 + * and Keystone have one Diva chip with 3 UARTs. Some later machines have
10153 + * one Diva chip, but it has been expanded to 5 UARTs.
10154 + */
10155 +static int __devinit
10156 +pci_hp_diva(struct pci_dev *dev, struct pci_board *board, int enable)
10157 +{
10158 + if (!enable)
10159 + return 0;
10160 +
10161 + switch (dev->subsystem_device) {
10162 + case 0x1049: /* Prelude Diva 1 */
10163 + case 0x1223: /* Superdome */
10164 + case 0x1226: /* Keystone */
10165 + case 0x1282: /* Everest / Longs Peak */
10166 + board->num_ports = 3;
10167 + break;
10168 + case 0x104A: /* Prelude Diva 2 */
10169 + board->num_ports = 2;
10170 + break;
10171 + case 0x104B: /* Maestro */
10172 + board->num_ports = 4;
10173 + break;
10174 + case 0x1227: /* Powerbar */
10175 + board->num_ports = 1;
10176 + break;
10177 + }
10178 +
10179 + return 0;
10180 +}
10181 +
10182 +static int __devinit
10183 +pci_xircom_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10184 +{
10185 + __set_current_state(TASK_UNINTERRUPTIBLE);
10186 + schedule_timeout(HZ/10);
10187 + return 0;
10188 +}
10189 +
10190 +/*
10191 + * This is the configuration table for all of the PCI serial boards
10192 + * which we support. It is directly indexed by the pci_board_num_t enum
10193 + * value, which is encoded in the pci_device_id PCI probe table's
10194 + * driver_data member.
10195 + */
10196 +enum pci_board_num_t {
10197 + pbn_b0_1_115200,
10198 + pbn_default = 0,
10199 +
10200 + pbn_b0_2_115200,
10201 + pbn_b0_4_115200,
10202 +
10203 + pbn_b0_1_921600,
10204 + pbn_b0_2_921600,
10205 + pbn_b0_4_921600,
10206 +
10207 + pbn_b0_bt_1_115200,
10208 + pbn_b0_bt_2_115200,
10209 + pbn_b0_bt_1_460800,
10210 + pbn_b0_bt_2_460800,
10211 + pbn_b0_bt_2_921600,
10212 +
10213 + pbn_b1_1_115200,
10214 + pbn_b1_2_115200,
10215 + pbn_b1_4_115200,
10216 + pbn_b1_8_115200,
10217 +
10218 + pbn_b1_2_921600,
10219 + pbn_b1_4_921600,
10220 + pbn_b1_8_921600,
10221 +
10222 + pbn_b1_2_1382400,
10223 + pbn_b1_4_1382400,
10224 + pbn_b1_8_1382400,
10225 +
10226 + pbn_b2_1_115200,
10227 + pbn_b2_8_115200,
10228 + pbn_b2_4_460800,
10229 + pbn_b2_8_460800,
10230 + pbn_b2_16_460800,
10231 + pbn_b2_4_921600,
10232 + pbn_b2_8_921600,
10233 +
10234 + pbn_b2_bt_1_115200,
10235 + pbn_b2_bt_2_115200,
10236 + pbn_b2_bt_4_115200,
10237 + pbn_b2_bt_2_921600,
10238 +
10239 + pbn_panacom,
10240 + pbn_panacom2,
10241 + pbn_panacom4,
10242 + pbn_plx_romulus,
10243 + pbn_oxsemi,
10244 + pbn_timedia,
10245 + pbn_intel_i960,
10246 + pbn_sgi_ioc3,
10247 + pbn_hp_diva,
10248 +#ifdef CONFIG_DDB5074
10249 + pbn_nec_nile4,
10250 +#endif
10251 +
10252 + pbn_dci_pccom4,
10253 + pbn_dci_pccom8,
10254 +
10255 + pbn_xircom_combo,
10256 +
10257 + pbn_siig10x_0,
10258 + pbn_siig10x_1,
10259 + pbn_siig10x_2,
10260 + pbn_siig10x_4,
10261 + pbn_siig20x_0,
10262 + pbn_siig20x_2,
10263 + pbn_siig20x_4,
10264 +
10265 + pbn_computone_4,
10266 + pbn_computone_6,
10267 + pbn_computone_8,
10268 +};
10269 +
10270 +static struct pci_board pci_boards[] __devinitdata = {
10271 + /*
10272 + * PCI Flags, Number of Ports, Base (Maximum) Baud Rate,
10273 + * Offset to get to next UART's registers,
10274 + * Register shift to use for memory-mapped I/O,
10275 + * Initialization function, first UART offset
10276 + */
10277 +
10278 + /* Generic serial board, pbn_b0_1_115200, pbn_default */
10279 + { SPCI_FL_BASE0, 1, 115200 }, /* pbn_b0_1_115200,
10280 + pbn_default */
10281 +
10282 + { SPCI_FL_BASE0, 2, 115200 }, /* pbn_b0_2_115200 */
10283 + { SPCI_FL_BASE0, 4, 115200 }, /* pbn_b0_4_115200 */
10284 +
10285 + { SPCI_FL_BASE0, 1, 921600 }, /* pbn_b0_1_921600 */
10286 + { SPCI_FL_BASE0, 2, 921600 }, /* pbn_b0_2_921600 */
10287 + { SPCI_FL_BASE0, 4, 921600 }, /* pbn_b0_4_921600 */
10288 +
10289 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b0_bt_1_115200 */
10290 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b0_bt_2_115200 */
10291 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 460800 }, /* pbn_b0_bt_1_460800 */
10292 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 460800 }, /* pbn_b0_bt_2_460800 */
10293 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b0_bt_2_921600 */
10294 +
10295 + { SPCI_FL_BASE1, 1, 115200 }, /* pbn_b1_1_115200 */
10296 + { SPCI_FL_BASE1, 2, 115200 }, /* pbn_b1_2_115200 */
10297 + { SPCI_FL_BASE1, 4, 115200 }, /* pbn_b1_4_115200 */
10298 + { SPCI_FL_BASE1, 8, 115200 }, /* pbn_b1_8_115200 */
10299 +
10300 + { SPCI_FL_BASE1, 2, 921600 }, /* pbn_b1_2_921600 */
10301 + { SPCI_FL_BASE1, 4, 921600 }, /* pbn_b1_4_921600 */
10302 + { SPCI_FL_BASE1, 8, 921600 }, /* pbn_b1_8_921600 */
10303 +
10304 + { SPCI_FL_BASE1, 2, 1382400 }, /* pbn_b1_2_1382400 */
10305 + { SPCI_FL_BASE1, 4, 1382400 }, /* pbn_b1_4_1382400 */
10306 + { SPCI_FL_BASE1, 8, 1382400 }, /* pbn_b1_8_1382400 */
10307 +
10308 + { SPCI_FL_BASE2, 1, 115200 }, /* pbn_b2_1_115200 */
10309 + { SPCI_FL_BASE2, 8, 115200 }, /* pbn_b2_8_115200 */
10310 + { SPCI_FL_BASE2, 4, 460800 }, /* pbn_b2_4_460800 */
10311 + { SPCI_FL_BASE2, 8, 460800 }, /* pbn_b2_8_460800 */
10312 + { SPCI_FL_BASE2, 16, 460800 }, /* pbn_b2_16_460800 */
10313 + { SPCI_FL_BASE2, 4, 921600 }, /* pbn_b2_4_921600 */
10314 + { SPCI_FL_BASE2, 8, 921600 }, /* pbn_b2_8_921600 */
10315 +
10316 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b2_bt_1_115200 */
10317 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b2_bt_2_115200 */
10318 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 115200 }, /* pbn_b2_bt_4_115200 */
10319 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b2_bt_2_921600 */
10320 +
10321 + { SPCI_FL_BASE2, 2, 921600, /* IOMEM */ /* pbn_panacom */
10322 + 0x400, 7, pci_plx9050_fn },
10323 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_panacom2 */
10324 + 0x400, 7, pci_plx9050_fn },
10325 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_panacom4 */
10326 + 0x400, 7, pci_plx9050_fn },
10327 + { SPCI_FL_BASE2, 4, 921600, /* pbn_plx_romulus */
10328 + 0x20, 2, pci_plx9050_fn, 0x03 },
10329 + /* This board uses the size of PCI Base region 0 to
10330 + * signal now many ports are available */
10331 + { SPCI_FL_BASE0 | SPCI_FL_REGION_SZ_CAP, 32, 115200 }, /* pbn_oxsemi */
10332 + { SPCI_FL_BASE_TABLE, 1, 921600, /* pbn_timedia */
10333 + 0, 0, pci_timedia_fn },
10334 + /* EKF addition for i960 Boards form EKF with serial port */
10335 + { SPCI_FL_BASE0, 32, 921600, /* max 256 ports */ /* pbn_intel_i960 */
10336 + 8<<2, 2, pci_inteli960ni_fn, 0x10000},
10337 + { SPCI_FL_BASE0 | SPCI_FL_IRQRESOURCE, /* pbn_sgi_ioc3 */
10338 + 1, 458333, 0, 0, 0, 0x20178 },
10339 + { SPCI_FL_BASE0, 5, 115200, 8, 0, pci_hp_diva, 0}, /* pbn_hp_diva */
10340 +#ifdef CONFIG_DDB5074
10341 + /*
10342 + * NEC Vrc-5074 (Nile 4) builtin UART.
10343 + * Conditionally compiled in since this is a motherboard device.
10344 + */
10345 + { SPCI_FL_BASE0, 1, 520833, /* pbn_nec_nile4 */
10346 + 64, 3, NULL, 0x300 },
10347 +#endif
10348 +
10349 + {SPCI_FL_BASE3, 4, 115200, 8}, /* pbn_dci_pccom4 */
10350 + {SPCI_FL_BASE3, 8, 115200, 8}, /* pbn_dci_pccom8 */
10351 +
10352 + { SPCI_FL_BASE0, 1, 115200, /* pbn_xircom_combo */
10353 + 0, 0, pci_xircom_fn },
10354 +
10355 + { SPCI_FL_BASE2, 1, 460800, /* pbn_siig10x_0 */
10356 + 0, 0, pci_siig10x_fn },
10357 + { SPCI_FL_BASE2, 1, 921600, /* pbn_siig10x_1 */
10358 + 0, 0, pci_siig10x_fn },
10359 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siig10x_2 */
10360 + 0, 0, pci_siig10x_fn },
10361 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siig10x_4 */
10362 + 0, 0, pci_siig10x_fn },
10363 + { SPCI_FL_BASE0, 1, 921600, /* pbn_siix20x_0 */
10364 + 0, 0, pci_siig20x_fn },
10365 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siix20x_2 */
10366 + 0, 0, pci_siig20x_fn },
10367 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siix20x_4 */
10368 + 0, 0, pci_siig20x_fn },
10369 +
10370 + { SPCI_FL_BASE0, 4, 921600, /* IOMEM */ /* pbn_computone_4 */
10371 + 0x40, 2, NULL, 0x200 },
10372 + { SPCI_FL_BASE0, 6, 921600, /* IOMEM */ /* pbn_computone_6 */
10373 + 0x40, 2, NULL, 0x200 },
10374 + { SPCI_FL_BASE0, 8, 921600, /* IOMEM */ /* pbn_computone_8 */
10375 + 0x40, 2, NULL, 0x200 },
10376 +};
10377 +
10378 +/*
10379 + * Given a complete unknown PCI device, try to use some heuristics to
10380 + * guess what the configuration might be, based on the pitiful PCI
10381 + * serial specs. Returns 0 on success, 1 on failure.
10382 + */
10383 +static int __devinit serial_pci_guess_board(struct pci_dev *dev,
10384 + struct pci_board *board)
10385 +{
10386 + int num_iomem = 0, num_port = 0, first_port = -1;
10387 + int i;
10388 +
10389 + /*
10390 + * If it is not a communications device or the programming
10391 + * interface is greater than 6, give up.
10392 + *
10393 + * (Should we try to make guesses for multiport serial devices
10394 + * later?)
10395 + */
10396 + if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
10397 + ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
10398 + (dev->class & 0xff) > 6)
10399 + return 1;
10400 +
10401 + for (i=0; i < 6; i++) {
10402 + if (IS_PCI_REGION_IOPORT(dev, i)) {
10403 + num_port++;
10404 + if (first_port == -1)
10405 + first_port = i;
10406 + }
10407 + if (IS_PCI_REGION_IOMEM(dev, i))
10408 + num_iomem++;
10409 + }
10410 +
10411 + /*
10412 + * If there is 1 or 0 iomem regions, and exactly one port, use
10413 + * it.
10414 + */
10415 + if (num_iomem <= 1 && num_port == 1) {
10416 + board->flags = first_port;
10417 + return 0;
10418 + }
10419 + return 1;
10420 +}
10421 +
10422 +static int __devinit serial_init_one(struct pci_dev *dev,
10423 + const struct pci_device_id *ent)
10424 +{
10425 + struct pci_board *board, tmp;
10426 + int rc;
10427 +
10428 + board = &pci_boards[ent->driver_data];
10429 +
10430 + rc = pci_enable_device(dev);
10431 + if (rc) return rc;
10432 +
10433 + if (ent->driver_data == pbn_default &&
10434 + serial_pci_guess_board(dev, board))
10435 + return -ENODEV;
10436 + else if (serial_pci_guess_board(dev, &tmp) == 0) {
10437 + printk(KERN_INFO "Redundant entry in serial pci_table. "
10438 + "Please send the output of\n"
10439 + "lspci -vv, this message (%04x,%04x,%04x,%04x)\n"
10440 + "and the manufacturer and name of "
10441 + "serial board or modem board\n"
10442 + "to serial-pci-info@lists.sourceforge.net.\n",
10443 + dev->vendor, dev->device,
10444 + pci_get_subvendor(dev), pci_get_subdevice(dev));
10445 + }
10446 +
10447 + start_pci_pnp_board(dev, board);
10448 +
10449 + return 0;
10450 +}
10451 +
10452 +static void __devexit serial_remove_one(struct pci_dev *dev)
10453 +{
10454 + int i;
10455 +
10456 + /*
10457 + * Iterate through all of the ports finding those that belong
10458 + * to this PCI device.
10459 + */
10460 + for(i = 0; i < NR_PORTS; i++) {
10461 + if (rs_table[i].dev != dev)
10462 + continue;
10463 + unregister_serial(i);
10464 + rs_table[i].dev = 0;
10465 + }
10466 + /*
10467 + * Now execute any board-specific shutdown procedure
10468 + */
10469 + for (i=0; i < NR_PCI_BOARDS; i++) {
10470 + struct pci_board_inst *brd = &serial_pci_board[i];
10471 +
10472 + if (serial_pci_board[i].dev != dev)
10473 + continue;
10474 + if (brd->board.init_fn)
10475 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
10476 + if (DEACTIVATE_FUNC(brd->dev))
10477 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
10478 + serial_pci_board[i].dev = 0;
10479 + }
10480 +}
10481 +
10482 +
10483 +static struct pci_device_id serial_pci_tbl[] __devinitdata = {
10484 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10485 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10486 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
10487 + pbn_b1_8_1382400 },
10488 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10489 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10490 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
10491 + pbn_b1_4_1382400 },
10492 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10493 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10494 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
10495 + pbn_b1_2_1382400 },
10496 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10497 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10498 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
10499 + pbn_b1_8_1382400 },
10500 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10501 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10502 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
10503 + pbn_b1_4_1382400 },
10504 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10505 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10506 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
10507 + pbn_b1_2_1382400 },
10508 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10509 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10510 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
10511 + pbn_b1_8_921600 },
10512 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10513 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10514 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
10515 + pbn_b1_8_921600 },
10516 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10517 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10518 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
10519 + pbn_b1_4_921600 },
10520 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10521 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10522 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
10523 + pbn_b1_4_921600 },
10524 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10525 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10526 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
10527 + pbn_b1_2_921600 },
10528 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10529 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10530 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
10531 + pbn_b1_8_921600 },
10532 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10533 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10534 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
10535 + pbn_b1_8_921600 },
10536 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10537 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10538 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
10539 + pbn_b1_4_921600 },
10540 +
10541 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
10542 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10543 + pbn_b2_bt_1_115200 },
10544 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
10545 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10546 + pbn_b2_bt_2_115200 },
10547 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
10548 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10549 + pbn_b2_bt_4_115200 },
10550 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
10551 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10552 + pbn_b2_bt_2_115200 },
10553 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
10554 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10555 + pbn_b2_bt_4_115200 },
10556 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
10557 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10558 + pbn_b2_8_115200 },
10559 +
10560 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
10561 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10562 + pbn_b2_bt_2_115200 },
10563 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
10564 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10565 + pbn_b2_bt_2_921600 },
10566 + /* VScom SPCOM800, from sl@s.pl */
10567 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
10568 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10569 + pbn_b2_8_921600 },
10570 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
10571 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10572 + pbn_b2_4_921600 },
10573 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10574 + PCI_SUBVENDOR_ID_KEYSPAN,
10575 + PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
10576 + pbn_panacom },
10577 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
10578 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10579 + pbn_panacom4 },
10580 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
10581 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10582 + pbn_panacom2 },
10583 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10584 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10585 + PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
10586 + pbn_b2_4_460800 },
10587 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10588 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10589 + PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
10590 + pbn_b2_8_460800 },
10591 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10592 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10593 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
10594 + pbn_b2_16_460800 },
10595 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10596 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10597 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
10598 + pbn_b2_16_460800 },
10599 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10600 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
10601 + PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
10602 + pbn_b2_4_460800 },
10603 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10604 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
10605 + PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
10606 + pbn_b2_8_460800 },
10607 + /* Megawolf Romulus PCI Serial Card, from Mike Hudson */
10608 + /* (Exoray@isys.ca) */
10609 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
10610 + 0x10b5, 0x106a, 0, 0,
10611 + pbn_plx_romulus },
10612 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
10613 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10614 + pbn_b1_4_115200 },
10615 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
10616 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10617 + pbn_b1_2_115200 },
10618 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
10619 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10620 + pbn_b1_8_115200 },
10621 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
10622 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10623 + pbn_b1_8_115200 },
10624 + { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
10625 + PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
10626 + pbn_b0_4_921600 },
10627 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
10628 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10629 + pbn_b0_4_115200 },
10630 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
10631 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10632 + pbn_b0_bt_2_921600 },
10633 +
10634 + /* Digitan DS560-558, from jimd@esoft.com */
10635 + { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
10636 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10637 + pbn_b1_1_115200 },
10638 +
10639 + /* 3Com US Robotics 56k Voice Internal PCI model 5610 */
10640 + { PCI_VENDOR_ID_USR, 0x1008,
10641 + PCI_ANY_ID, PCI_ANY_ID, },
10642 +
10643 + /* Titan Electronic cards */
10644 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
10645 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10646 + pbn_b0_1_921600 },
10647 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
10648 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10649 + pbn_b0_2_921600 },
10650 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
10651 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10652 + pbn_b0_4_921600 },
10653 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
10654 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10655 + pbn_b0_4_921600 },
10656 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
10657 + PCI_ANY_ID, PCI_ANY_ID,
10658 + SPCI_FL_BASE1, 1, 921600 },
10659 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
10660 + PCI_ANY_ID, PCI_ANY_ID,
10661 + SPCI_FL_BASE1 | SPCI_FL_BASE_TABLE, 2, 921600 },
10662 + /* The 400L and 800L have a custom hack in get_pci_port */
10663 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
10664 + PCI_ANY_ID, PCI_ANY_ID,
10665 + SPCI_FL_BASE_TABLE, 4, 921600 },
10666 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
10667 + PCI_ANY_ID, PCI_ANY_ID,
10668 + SPCI_FL_BASE_TABLE, 8, 921600 },
10669 +
10670 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
10671 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10672 + pbn_siig10x_0 },
10673 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
10674 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10675 + pbn_siig10x_0 },
10676 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
10677 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10678 + pbn_siig10x_0 },
10679 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
10680 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10681 + pbn_siig10x_2 },
10682 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
10683 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10684 + pbn_siig10x_2 },
10685 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
10686 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10687 + pbn_siig10x_2 },
10688 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
10689 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10690 + pbn_siig10x_4 },
10691 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
10692 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10693 + pbn_siig10x_4 },
10694 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
10695 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10696 + pbn_siig10x_4 },
10697 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
10698 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10699 + pbn_siig20x_0 },
10700 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
10701 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10702 + pbn_siig20x_0 },
10703 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
10704 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10705 + pbn_siig20x_0 },
10706 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
10707 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10708 + pbn_siig20x_2 },
10709 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
10710 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10711 + pbn_siig20x_2 },
10712 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
10713 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10714 + pbn_siig20x_2 },
10715 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
10716 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10717 + pbn_siig20x_4 },
10718 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
10719 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10720 + pbn_siig20x_4 },
10721 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
10722 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10723 + pbn_siig20x_4 },
10724 +
10725 + /* Computone devices submitted by Doug McNash dmcnash@computone.com */
10726 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10727 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
10728 + 0, 0, pbn_computone_4 },
10729 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10730 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
10731 + 0, 0, pbn_computone_8 },
10732 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10733 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
10734 + 0, 0, pbn_computone_6 },
10735 +
10736 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
10737 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_oxsemi },
10738 + { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
10739 + PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, pbn_timedia },
10740 +
10741 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
10742 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10743 + pbn_b0_bt_2_115200 },
10744 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
10745 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10746 + pbn_b0_bt_2_115200 },
10747 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
10748 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10749 + pbn_b0_bt_2_115200 },
10750 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
10751 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10752 + pbn_b0_bt_2_460800 },
10753 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
10754 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10755 + pbn_b0_bt_2_460800 },
10756 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
10757 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10758 + pbn_b0_bt_2_460800 },
10759 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
10760 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10761 + pbn_b0_bt_1_115200 },
10762 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
10763 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10764 + pbn_b0_bt_1_460800 },
10765 +
10766 + /* RAStel 2 port modem, gerg@moreton.com.au */
10767 + { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
10768 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10769 + pbn_b2_bt_2_115200 },
10770 +
10771 + /* EKF addition for i960 Boards form EKF with serial port */
10772 + { PCI_VENDOR_ID_INTEL, 0x1960,
10773 + 0xE4BF, PCI_ANY_ID, 0, 0,
10774 + pbn_intel_i960 },
10775 +
10776 + /* Xircom Cardbus/Ethernet combos */
10777 + { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
10778 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10779 + pbn_xircom_combo },
10780 +
10781 + /*
10782 + * Untested PCI modems, sent in from various folks...
10783 + */
10784 +
10785 + /* Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> */
10786 + { PCI_VENDOR_ID_ROCKWELL, 0x1004,
10787 + 0x1048, 0x1500, 0, 0,
10788 + pbn_b1_1_115200 },
10789 +
10790 + { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
10791 + 0xFF00, 0, 0, 0,
10792 + pbn_sgi_ioc3 },
10793 +
10794 + /* HP Diva card */
10795 + { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_SAS,
10796 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10797 + pbn_hp_diva },
10798 + { PCI_VENDOR_ID_HP, 0x1290,
10799 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10800 + pbn_b2_1_115200 },
10801 +
10802 +#ifdef CONFIG_DDB5074
10803 + /*
10804 + * NEC Vrc-5074 (Nile 4) builtin UART.
10805 + * Conditionally compiled in since this is a motherboard device.
10806 + */
10807 + { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
10808 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10809 + pbn_nec_nile4 },
10810 +#endif
10811 +
10812 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
10813 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10814 + pbn_dci_pccom4 },
10815 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
10816 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10817 + pbn_dci_pccom8 },
10818 +
10819 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
10820 + PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, },
10821 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
10822 + PCI_CLASS_COMMUNICATION_MODEM << 8, 0xffff00, },
10823 + { 0, }
10824 +};
10825 +
10826 +MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
10827 +
10828 +static struct pci_driver serial_pci_driver = {
10829 + name: "serial",
10830 + probe: serial_init_one,
10831 + remove: __devexit_p(serial_remove_one),
10832 + id_table: serial_pci_tbl,
10833 +};
10834 +
10835 +
10836 +/*
10837 + * Query PCI space for known serial boards
10838 + * If found, add them to the PCI device space in rs_table[]
10839 + *
10840 + * Accept a maximum of eight boards
10841 + *
10842 + */
10843 +static void __devinit probe_serial_pci(void)
10844 +{
10845 +#ifdef SERIAL_DEBUG_PCI
10846 + printk(KERN_DEBUG "Entered probe_serial_pci()\n");
10847 +#endif
10848 +
10849 + /* Register call PCI serial devices. Null out
10850 + * the driver name upon failure, as a signal
10851 + * not to attempt to unregister the driver later
10852 + */
10853 + if (pci_module_init (&serial_pci_driver) != 0)
10854 + serial_pci_driver.name = "";
10855 +
10856 +#ifdef SERIAL_DEBUG_PCI
10857 + printk(KERN_DEBUG "Leaving probe_serial_pci() (probe finished)\n");
10858 +#endif
10859 + return;
10860 +}
10861 +
10862 +#endif /* ENABLE_SERIAL_PCI */
10863 +
10864 +#ifdef ENABLE_SERIAL_PNP
10865 +
10866 +struct pnp_board {
10867 + unsigned short vendor;
10868 + unsigned short device;
10869 +};
10870 +
10871 +static struct pnp_board pnp_devices[] __devinitdata = {
10872 + /* Archtek America Corp. */
10873 + /* Archtek SmartLink Modem 3334BT Plug & Play */
10874 + { ISAPNP_VENDOR('A', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
10875 + /* Anchor Datacomm BV */
10876 + /* SXPro 144 External Data Fax Modem Plug & Play */
10877 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0001) },
10878 + /* SXPro 288 External Data Fax Modem Plug & Play */
10879 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0002) },
10880 + /* Rockwell 56K ACF II Fax+Data+Voice Modem */
10881 + { ISAPNP_VENDOR('A', 'K', 'Y'), ISAPNP_DEVICE(0x1021) },
10882 + /* AZT3005 PnP SOUND DEVICE */
10883 + { ISAPNP_VENDOR('A', 'Z', 'T'), ISAPNP_DEVICE(0x4001) },
10884 + /* Best Data Products Inc. Smart One 336F PnP Modem */
10885 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
10886 + /* Boca Research */
10887 + /* Boca Complete Ofc Communicator 14.4 Data-FAX */
10888 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
10889 + /* Boca Research 33,600 ACF Modem */
10890 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x1400) },
10891 + /* Boca 33.6 Kbps Internal FD34FSVD */
10892 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x3400) },
10893 + /* Boca 33.6 Kbps Internal FD34FSVD */
10894 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
10895 + /* Best Data Products Inc. Smart One 336F PnP Modem */
10896 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
10897 + /* Computer Peripherals Inc */
10898 + /* EuroViVa CommCenter-33.6 SP PnP */
10899 + { ISAPNP_VENDOR('C', 'P', 'I'), ISAPNP_DEVICE(0x4050) },
10900 + /* Creative Labs */
10901 + /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
10902 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3001) },
10903 + /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
10904 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3011) },
10905 + /* Creative */
10906 + /* Creative Modem Blaster Flash56 DI5601-1 */
10907 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x1032) },
10908 + /* Creative Modem Blaster V.90 DI5660 */
10909 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x2001) },
10910 + /* FUJITSU */
10911 + /* Fujitsu 33600 PnP-I2 R Plug & Play */
10912 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0202) },
10913 + /* Fujitsu FMV-FX431 Plug & Play */
10914 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0205) },
10915 + /* Fujitsu 33600 PnP-I4 R Plug & Play */
10916 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0206) },
10917 + /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
10918 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0209) },
10919 + /* Archtek America Corp. */
10920 + /* Archtek SmartLink Modem 3334BT Plug & Play */
10921 + { ISAPNP_VENDOR('G', 'V', 'C'), ISAPNP_DEVICE(0x000F) },
10922 + /* Hayes */
10923 + /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
10924 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x0001) },
10925 + /* Hayes Optima 336 V.34 + FAX + Voice PnP */
10926 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000C) },
10927 + /* Hayes Optima 336B V.34 + FAX + Voice PnP */
10928 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000D) },
10929 + /* Hayes Accura 56K Ext Fax Modem PnP */
10930 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5670) },
10931 + /* Hayes Accura 56K Ext Fax Modem PnP */
10932 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5674) },
10933 + /* Hayes Accura 56K Fax Modem PnP */
10934 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5675) },
10935 + /* Hayes 288, V.34 + FAX */
10936 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF000) },
10937 + /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
10938 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF001) },
10939 + /* IBM */
10940 + /* IBM Thinkpad 701 Internal Modem Voice */
10941 + { ISAPNP_VENDOR('I', 'B', 'M'), ISAPNP_DEVICE(0x0033) },
10942 + /* Intertex */
10943 + /* Intertex 28k8 33k6 Voice EXT PnP */
10944 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC801) },
10945 + /* Intertex 33k6 56k Voice EXT PnP */
10946 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC901) },
10947 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
10948 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD801) },
10949 + /* Intertex 33k6 56k Voice SP EXT PnP */
10950 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD901) },
10951 + /* Intertex 28k8 33k6 Voice SP INT PnP */
10952 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF401) },
10953 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
10954 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF801) },
10955 + /* Intertex 33k6 56k Voice SP EXT PnP */
10956 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF901) },
10957 + /* Kortex International */
10958 + /* KORTEX 28800 Externe PnP */
10959 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0x4522) },
10960 + /* KXPro 33.6 Vocal ASVD PnP */
10961 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0xF661) },
10962 + /* Lasat */
10963 + /* LASAT Internet 33600 PnP */
10964 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4040) },
10965 + /* Lasat Safire 560 PnP */
10966 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4540) },
10967 + /* Lasat Safire 336 PnP */
10968 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x5440) },
10969 + /* Microcom, Inc. */
10970 + /* Microcom TravelPorte FAST V.34 Plug & Play */
10971 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x281) },
10972 + /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
10973 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0336) },
10974 + /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
10975 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0339) },
10976 + /* Microcom DeskPorte 28.8P Plug & Play */
10977 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0342) },
10978 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
10979 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
10980 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
10981 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
10982 + /* Microcom DeskPorte 28.8S Internal Plug & Play */
10983 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0502) },
10984 + /* Motorola */
10985 + /* Motorola BitSURFR Plug & Play */
10986 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1105) },
10987 + /* Motorola TA210 Plug & Play */
10988 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1111) },
10989 + /* Motorola HMTA 200 (ISDN) Plug & Play */
10990 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1114) },
10991 + /* Motorola BitSURFR Plug & Play */
10992 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1115) },
10993 + /* Motorola Lifestyle 28.8 Internal */
10994 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1190) },
10995 + /* Motorola V.3400 Plug & Play */
10996 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1501) },
10997 + /* Motorola Lifestyle 28.8 V.34 Plug & Play */
10998 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1502) },
10999 + /* Motorola Power 28.8 V.34 Plug & Play */
11000 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1505) },
11001 + /* Motorola ModemSURFR External 28.8 Plug & Play */
11002 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1509) },
11003 + /* Motorola Premier 33.6 Desktop Plug & Play */
11004 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150A) },
11005 + /* Motorola VoiceSURFR 56K External PnP */
11006 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150F) },
11007 + /* Motorola ModemSURFR 56K External PnP */
11008 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1510) },
11009 + /* Motorola ModemSURFR 56K Internal PnP */
11010 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1550) },
11011 + /* Motorola ModemSURFR Internal 28.8 Plug & Play */
11012 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1560) },
11013 + /* Motorola Premier 33.6 Internal Plug & Play */
11014 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1580) },
11015 + /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
11016 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15B0) },
11017 + /* Motorola VoiceSURFR 56K Internal PnP */
11018 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15F0) },
11019 + /* Com 1 */
11020 + /* Deskline K56 Phone System PnP */
11021 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00A1) },
11022 + /* PC Rider K56 Phone System PnP */
11023 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00F2) },
11024 + /* Pace 56 Voice Internal Plug & Play Modem */
11025 + { ISAPNP_VENDOR('P', 'M', 'C'), ISAPNP_DEVICE(0x2430) },
11026 + /* Generic */
11027 + /* Generic standard PC COM port */
11028 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
11029 + /* Generic 16550A-compatible COM port */
11030 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
11031 + /* Compaq 14400 Modem */
11032 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC000) },
11033 + /* Compaq 2400/9600 Modem */
11034 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC001) },
11035 + /* Dial-Up Networking Serial Cable between 2 PCs */
11036 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC031) },
11037 + /* Dial-Up Networking Parallel Cable between 2 PCs */
11038 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC032) },
11039 + /* Standard 9600 bps Modem */
11040 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC100) },
11041 + /* Standard 14400 bps Modem */
11042 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC101) },
11043 + /* Standard 28800 bps Modem*/
11044 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC102) },
11045 + /* Standard Modem*/
11046 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC103) },
11047 + /* Standard 9600 bps Modem*/
11048 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC104) },
11049 + /* Standard 14400 bps Modem*/
11050 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC105) },
11051 + /* Standard 28800 bps Modem*/
11052 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC106) },
11053 + /* Standard Modem */
11054 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC107) },
11055 + /* Standard 9600 bps Modem */
11056 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC108) },
11057 + /* Standard 14400 bps Modem */
11058 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC109) },
11059 + /* Standard 28800 bps Modem */
11060 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10A) },
11061 + /* Standard Modem */
11062 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10B) },
11063 + /* Standard 9600 bps Modem */
11064 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10C) },
11065 + /* Standard 14400 bps Modem */
11066 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10D) },
11067 + /* Standard 28800 bps Modem */
11068 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10E) },
11069 + /* Standard Modem */
11070 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10F) },
11071 + /* Standard PCMCIA Card Modem */
11072 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x2000) },
11073 + /* Rockwell */
11074 + /* Modular Technology */
11075 + /* Rockwell 33.6 DPF Internal PnP */
11076 + /* Modular Technology 33.6 Internal PnP */
11077 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0030) },
11078 + /* Kortex International */
11079 + /* KORTEX 14400 Externe PnP */
11080 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0100) },
11081 + /* Viking Components, Inc */
11082 + /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
11083 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x4920) },
11084 + /* Rockwell */
11085 + /* British Telecom */
11086 + /* Modular Technology */
11087 + /* Rockwell 33.6 DPF External PnP */
11088 + /* BT Prologue 33.6 External PnP */
11089 + /* Modular Technology 33.6 External PnP */
11090 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x00A0) },
11091 + /* Viking 56K FAX INT */
11092 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x0262) },
11093 + /* SupraExpress 28.8 Data/Fax PnP modem */
11094 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1310) },
11095 + /* SupraExpress 33.6 Data/Fax PnP modem */
11096 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1421) },
11097 + /* SupraExpress 33.6 Data/Fax PnP modem */
11098 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1590) },
11099 + /* SupraExpress 33.6 Data/Fax PnP modem */
11100 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1760) },
11101 + /* Phoebe Micro */
11102 + /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
11103 + { ISAPNP_VENDOR('T', 'E', 'X'), ISAPNP_DEVICE(0x0011) },
11104 + /* Archtek America Corp. */
11105 + /* Archtek SmartLink Modem 3334BT Plug & Play */
11106 + { ISAPNP_VENDOR('U', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
11107 + /* 3Com Corp. */
11108 + /* Gateway Telepath IIvi 33.6 */
11109 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0000) },
11110 + /* Sportster Vi 14.4 PnP FAX Voicemail */
11111 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0004) },
11112 + /* U.S. Robotics 33.6K Voice INT PnP */
11113 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0006) },
11114 + /* U.S. Robotics 33.6K Voice EXT PnP */
11115 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0007) },
11116 + /* U.S. Robotics 33.6K Voice INT PnP */
11117 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2002) },
11118 + /* U.S. Robotics 56K Voice INT PnP */
11119 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2070) },
11120 + /* U.S. Robotics 56K Voice EXT PnP */
11121 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2080) },
11122 + /* U.S. Robotics 56K FAX INT */
11123 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3031) },
11124 + /* U.S. Robotics 56K Voice INT PnP */
11125 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3070) },
11126 + /* U.S. Robotics 56K Voice EXT PnP */
11127 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3080) },
11128 + /* U.S. Robotics 56K Voice INT PnP */
11129 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3090) },
11130 + /* U.S. Robotics 56K Message */
11131 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9100) },
11132 + /* U.S. Robotics 56K FAX EXT PnP*/
11133 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9160) },
11134 + /* U.S. Robotics 56K FAX INT PnP*/
11135 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9170) },
11136 + /* U.S. Robotics 56K Voice EXT PnP*/
11137 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9180) },
11138 + /* U.S. Robotics 56K Voice INT PnP*/
11139 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9190) },
11140 + { 0, }
11141 +};
11142 +
11143 +static inline void avoid_irq_share(struct pci_dev *dev)
11144 +{
11145 + int i, map = 0x1FF8;
11146 + struct serial_state *state = rs_table;
11147 + struct isapnp_irq *irq;
11148 + struct isapnp_resources *res = dev->sysdata;
11149 +
11150 + for (i = 0; i < NR_PORTS; i++) {
11151 + if (state->type != PORT_UNKNOWN)
11152 + clear_bit(state->irq, &map);
11153 + state++;
11154 + }
11155 +
11156 + for ( ; res; res = res->alt)
11157 + for(irq = res->irq; irq; irq = irq->next)
11158 + irq->map = map;
11159 +}
11160 +
11161 +static char *modem_names[] __devinitdata = {
11162 + "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
11163 + "56K", "56k", "K56", "33.6", "28.8", "14.4",
11164 + "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
11165 + "33600", "28800", "14400", "V.90", "V.34", "V.32", 0
11166 +};
11167 +
11168 +static int __devinit check_name(char *name)
11169 +{
11170 + char **tmp = modem_names;
11171 +
11172 + while (*tmp) {
11173 + if (strstr(name, *tmp))
11174 + return 1;
11175 + tmp++;
11176 + }
11177 + return 0;
11178 +}
11179 +
11180 +static inline int check_compatible_id(struct pci_dev *dev)
11181 +{
11182 + int i;
11183 + for (i = 0; i < DEVICE_COUNT_COMPATIBLE; i++)
11184 + if ((dev->vendor_compatible[i] ==
11185 + ISAPNP_VENDOR('P', 'N', 'P')) &&
11186 + (swab16(dev->device_compatible[i]) >= 0xc000) &&
11187 + (swab16(dev->device_compatible[i]) <= 0xdfff))
11188 + return 0;
11189 + return 1;
11190 +}
11191 +
11192 +/*
11193 + * Given a complete unknown ISA PnP device, try to use some heuristics to
11194 + * detect modems. Currently use such heuristic set:
11195 + * - dev->name or dev->bus->name must contain "modem" substring;
11196 + * - device must have only one IO region (8 byte long) with base adress
11197 + * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
11198 + *
11199 + * Such detection looks very ugly, but can detect at least some of numerous
11200 + * ISA PnP modems, alternatively we must hardcode all modems in pnp_devices[]
11201 + * table.
11202 + */
11203 +static int _INLINE_ serial_pnp_guess_board(struct pci_dev *dev,
11204 + struct pci_board *board)
11205 +{
11206 + struct isapnp_resources *res = (struct isapnp_resources *)dev->sysdata;
11207 + struct isapnp_resources *resa;
11208 +
11209 + if (!(check_name(dev->name) || check_name(dev->bus->name)) &&
11210 + !(check_compatible_id(dev)))
11211 + return 1;
11212 +
11213 + if (!res || res->next)
11214 + return 1;
11215 +
11216 + for (resa = res->alt; resa; resa = resa->alt) {
11217 + struct isapnp_port *port;
11218 + for (port = res->port; port; port = port->next)
11219 + if ((port->size == 8) &&
11220 + ((port->min == 0x2f8) ||
11221 + (port->min == 0x3f8) ||
11222 + (port->min == 0x2e8) ||
11223 + (port->min == 0x3e8)))
11224 + return 0;
11225 + }
11226 +
11227 + return 1;
11228 +}
11229 +
11230 +static void __devinit probe_serial_pnp(void)
11231 +{
11232 + struct pci_dev *dev = NULL;
11233 + struct pnp_board *pnp_board;
11234 + struct pci_board board;
11235 +
11236 +#ifdef SERIAL_DEBUG_PNP
11237 + printk("Entered probe_serial_pnp()\n");
11238 +#endif
11239 + if (!isapnp_present()) {
11240 +#ifdef SERIAL_DEBUG_PNP
11241 + printk("Leaving probe_serial_pnp() (no isapnp)\n");
11242 +#endif
11243 + return;
11244 + }
11245 +
11246 + isapnp_for_each_dev(dev) {
11247 + if (dev->active)
11248 + continue;
11249 +
11250 + memset(&board, 0, sizeof(board));
11251 + board.flags = SPCI_FL_BASE0 | SPCI_FL_PNPDEFAULT;
11252 + board.num_ports = 1;
11253 + board.base_baud = 115200;
11254 +
11255 + for (pnp_board = pnp_devices; pnp_board->vendor; pnp_board++)
11256 + if ((dev->vendor == pnp_board->vendor) &&
11257 + (dev->device == pnp_board->device))
11258 + break;
11259 +
11260 + if (pnp_board->vendor) {
11261 + /* Special case that's more efficient to hardcode */
11262 + if ((pnp_board->vendor == ISAPNP_VENDOR('A', 'K', 'Y') &&
11263 + pnp_board->device == ISAPNP_DEVICE(0x1021)))
11264 + board.flags |= SPCI_FL_NO_SHIRQ;
11265 + } else {
11266 + if (serial_pnp_guess_board(dev, &board))
11267 + continue;
11268 + }
11269 +
11270 + if (board.flags & SPCI_FL_NO_SHIRQ)
11271 + avoid_irq_share(dev);
11272 + start_pci_pnp_board(dev, &board);
11273 + }
11274 +
11275 +#ifdef SERIAL_DEBUG_PNP
11276 + printk("Leaving probe_serial_pnp() (probe finished)\n");
11277 +#endif
11278 + return;
11279 +}
11280 +
11281 +#endif /* ENABLE_SERIAL_PNP */
11282 +
11283 +/*
11284 + * The serial driver boot-time initialization code!
11285 + */
11286 +static int __init rs_init(void)
11287 +{
11288 + int i;
11289 + struct serial_state * state;
11290 +
11291 + init_bh(SERIAL_BH, do_serial_bh);
11292 + init_timer(&serial_timer);
11293 + serial_timer.function = rs_timer;
11294 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
11295 +
11296 + for (i = 0; i < NR_IRQS; i++) {
11297 + IRQ_ports[i] = 0;
11298 + IRQ_timeout[i] = 0;
11299 +#ifdef CONFIG_SERIAL_MULTIPORT
11300 + memset(&rs_multiport[i], 0,
11301 + sizeof(struct rs_multiport_struct));
11302 +#endif
11303 + }
11304 + show_serial_version();
11305 +
11306 + /* Initialize the tty_driver structure */
11307 +
11308 + memset(&serial_driver, 0, sizeof(struct tty_driver));
11309 + serial_driver.magic = TTY_DRIVER_MAGIC;
11310 +#if (LINUX_VERSION_CODE > 0x20100)
11311 + serial_driver.driver_name = "serial";
11312 +#endif
11313 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11314 + serial_driver.name = "tts/%d";
11315 +#else
11316 + serial_driver.name = "ttyS";
11317 +#endif
11318 + serial_driver.major = TTY_MAJOR;
11319 + serial_driver.minor_start = 64 + SERIAL_DEV_OFFSET;
11320 + serial_driver.name_base = SERIAL_DEV_OFFSET;
11321 + serial_driver.num = NR_PORTS;
11322 + serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
11323 + serial_driver.subtype = SERIAL_TYPE_NORMAL;
11324 + serial_driver.init_termios = tty_std_termios;
11325 + serial_driver.init_termios.c_cflag =
11326 + B9600 | CS8 | CREAD | HUPCL | CLOCAL;
11327 + serial_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
11328 + serial_driver.refcount = &serial_refcount;
11329 + serial_driver.table = serial_table;
11330 + serial_driver.termios = serial_termios;
11331 + serial_driver.termios_locked = serial_termios_locked;
11332 +
11333 + serial_driver.open = rs_open;
11334 + serial_driver.close = rs_close;
11335 + serial_driver.write = rs_write;
11336 + serial_driver.put_char = rs_put_char;
11337 + serial_driver.flush_chars = rs_flush_chars;
11338 + serial_driver.write_room = rs_write_room;
11339 + serial_driver.chars_in_buffer = rs_chars_in_buffer;
11340 + serial_driver.flush_buffer = rs_flush_buffer;
11341 + serial_driver.ioctl = rs_ioctl;
11342 + serial_driver.throttle = rs_throttle;
11343 + serial_driver.unthrottle = rs_unthrottle;
11344 + serial_driver.set_termios = rs_set_termios;
11345 + serial_driver.stop = rs_stop;
11346 + serial_driver.start = rs_start;
11347 + serial_driver.hangup = rs_hangup;
11348 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
11349 + serial_driver.break_ctl = rs_break;
11350 +#endif
11351 +#if (LINUX_VERSION_CODE >= 131343)
11352 + serial_driver.send_xchar = rs_send_xchar;
11353 + serial_driver.wait_until_sent = rs_wait_until_sent;
11354 + serial_driver.read_proc = rs_read_proc;
11355 +#endif
11356 +
11357 + /*
11358 + * The callout device is just like normal device except for
11359 + * major number and the subtype code.
11360 + */
11361 + callout_driver = serial_driver;
11362 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11363 + callout_driver.name = "cua/%d";
11364 +#else
11365 + callout_driver.name = "cua";
11366 +#endif
11367 + callout_driver.major = TTYAUX_MAJOR;
11368 + callout_driver.subtype = SERIAL_TYPE_CALLOUT;
11369 +#if (LINUX_VERSION_CODE >= 131343)
11370 + callout_driver.read_proc = 0;
11371 + callout_driver.proc_entry = 0;
11372 +#endif
11373 +
11374 + if (tty_register_driver(&serial_driver))
11375 + panic("Couldn't register serial driver\n");
11376 + if (tty_register_driver(&callout_driver))
11377 + panic("Couldn't register callout driver\n");
11378 +
11379 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
11380 + state->magic = SSTATE_MAGIC;
11381 + state->line = i;
11382 + state->type = PORT_UNKNOWN;
11383 + state->custom_divisor = 0;
11384 + state->close_delay = 5*HZ/10;
11385 + state->closing_wait = 30*HZ;
11386 + state->callout_termios = callout_driver.init_termios;
11387 + state->normal_termios = serial_driver.init_termios;
11388 + state->icount.cts = state->icount.dsr =
11389 + state->icount.rng = state->icount.dcd = 0;
11390 + state->icount.rx = state->icount.tx = 0;
11391 + state->icount.frame = state->icount.parity = 0;
11392 + state->icount.overrun = state->icount.brk = 0;
11393 + state->irq = irq_cannonicalize(state->irq);
11394 + if (state->hub6)
11395 + state->io_type = SERIAL_IO_HUB6;
11396 + if (state->port && check_region(state->port,8))
11397 + continue;
11398 +#ifdef CONFIG_MCA
11399 + if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
11400 + continue;
11401 +#endif
11402 + if (state->flags & ASYNC_BOOT_AUTOCONF)
11403 + autoconfig(state);
11404 + }
11405 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
11406 + if (state->type == PORT_UNKNOWN)
11407 + continue;
11408 + if ( (state->flags & ASYNC_BOOT_AUTOCONF)
11409 + && (state->flags & ASYNC_AUTO_IRQ)
11410 + && (state->port != 0 || state->iomem_base != 0))
11411 + state->irq = detect_uart_irq(state);
11412 + if (state->io_type == SERIAL_IO_MEM) {
11413 + printk(KERN_INFO"ttyS%02d%s at 0x%p (irq = %d) is a %s\n",
11414 + state->line + SERIAL_DEV_OFFSET,
11415 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
11416 + state->iomem_base, state->irq,
11417 + uart_config[state->type].name);
11418 + }
11419 + else {
11420 + printk(KERN_INFO "ttyS%02d%s at 0x%04lx (irq = %d) is a %s\n",
11421 + state->line + SERIAL_DEV_OFFSET,
11422 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
11423 + state->port, state->irq,
11424 + uart_config[state->type].name);
11425 + }
11426 + tty_register_devfs(&serial_driver, 0,
11427 + serial_driver.minor_start + state->line);
11428 + tty_register_devfs(&callout_driver, 0,
11429 + callout_driver.minor_start + state->line);
11430 + }
11431 +#ifdef ENABLE_SERIAL_PCI
11432 + probe_serial_pci();
11433 +#endif
11434 +#ifdef ENABLE_SERIAL_PNP
11435 + probe_serial_pnp();
11436 +#endif
11437 + return 0;
11438 +}
11439 +
11440 +/*
11441 + * This is for use by architectures that know their serial console
11442 + * attributes only at run time. Not to be invoked after rs_init().
11443 + */
11444 +int __init early_serial_setup(struct serial_struct *req)
11445 +{
11446 + int i = req->line;
11447 +
11448 + if (i >= NR_IRQS)
11449 + return(-ENOENT);
11450 + rs_table[i].magic = 0;
11451 + rs_table[i].baud_base = req->baud_base;
11452 + rs_table[i].port = req->port;
11453 + if (HIGH_BITS_OFFSET)
11454 + rs_table[i].port += (unsigned long) req->port_high <<
11455 + HIGH_BITS_OFFSET;
11456 + rs_table[i].irq = req->irq;
11457 + rs_table[i].flags = req->flags;
11458 + rs_table[i].close_delay = req->close_delay;
11459 + rs_table[i].io_type = req->io_type;
11460 + rs_table[i].hub6 = req->hub6;
11461 + rs_table[i].iomem_base = req->iomem_base;
11462 + rs_table[i].iomem_reg_shift = req->iomem_reg_shift;
11463 + rs_table[i].type = req->type;
11464 + rs_table[i].xmit_fifo_size = req->xmit_fifo_size;
11465 + rs_table[i].custom_divisor = req->custom_divisor;
11466 + rs_table[i].closing_wait = req->closing_wait;
11467 + return(0);
11468 +}
11469 +
11470 +/*
11471 + * register_serial and unregister_serial allows for 16x50 serial ports to be
11472 + * configured at run-time, to support PCMCIA modems.
11473 + */
11474 +
11475 +/**
11476 + * register_serial - configure a 16x50 serial port at runtime
11477 + * @req: request structure
11478 + *
11479 + * Configure the serial port specified by the request. If the
11480 + * port exists and is in use an error is returned. If the port
11481 + * is not currently in the table it is added.
11482 + *
11483 + * The port is then probed and if neccessary the IRQ is autodetected
11484 + * If this fails an error is returned.
11485 + *
11486 + * On success the port is ready to use and the line number is returned.
11487 + */
11488 +
11489 +int register_serial(struct serial_struct *req)
11490 +{
11491 + int i;
11492 + unsigned long flags;
11493 + struct serial_state *state;
11494 + struct async_struct *info;
11495 + unsigned long port;
11496 +
11497 + port = req->port;
11498 + if (HIGH_BITS_OFFSET)
11499 + port += (unsigned long) req->port_high << HIGH_BITS_OFFSET;
11500 +
11501 + save_flags(flags); cli();
11502 + for (i = 0; i < NR_PORTS; i++) {
11503 + if ((rs_table[i].port == port) &&
11504 + (rs_table[i].iomem_base == req->iomem_base))
11505 + break;
11506 + }
11507 +#ifdef __i386__
11508 + if (i == NR_PORTS) {
11509 + for (i = 4; i < NR_PORTS; i++)
11510 + if ((rs_table[i].type == PORT_UNKNOWN) &&
11511 + (rs_table[i].count == 0))
11512 + break;
11513 + }
11514 +#endif
11515 + if (i == NR_PORTS) {
11516 + for (i = 0; i < NR_PORTS; i++)
11517 + if ((rs_table[i].type == PORT_UNKNOWN) &&
11518 + (rs_table[i].count == 0))
11519 + break;
11520 + }
11521 + if (i == NR_PORTS) {
11522 + restore_flags(flags);
11523 + return -1;
11524 + }
11525 + state = &rs_table[i];
11526 + if (rs_table[i].count) {
11527 + restore_flags(flags);
11528 + printk("Couldn't configure serial #%d (port=%ld,irq=%d): "
11529 + "device already open\n", i, port, req->irq);
11530 + return -1;
11531 + }
11532 + state->irq = req->irq;
11533 + state->port = port;
11534 + state->flags = req->flags;
11535 + state->io_type = req->io_type;
11536 + state->iomem_base = req->iomem_base;
11537 + state->iomem_reg_shift = req->iomem_reg_shift;
11538 + if (req->baud_base)
11539 + state->baud_base = req->baud_base;
11540 + if ((info = state->info) != NULL) {
11541 + info->port = port;
11542 + info->flags = req->flags;
11543 + info->io_type = req->io_type;
11544 + info->iomem_base = req->iomem_base;
11545 + info->iomem_reg_shift = req->iomem_reg_shift;
11546 + }
11547 + autoconfig(state);
11548 + if (state->type == PORT_UNKNOWN) {
11549 + restore_flags(flags);
11550 + printk("register_serial(): autoconfig failed\n");
11551 + return -1;
11552 + }
11553 + restore_flags(flags);
11554 +
11555 + if ((state->flags & ASYNC_AUTO_IRQ) && CONFIGURED_SERIAL_PORT(state))
11556 + state->irq = detect_uart_irq(state);
11557 +
11558 + printk(KERN_INFO "ttyS%02d at %s 0x%04lx (irq = %d) is a %s\n",
11559 + state->line + SERIAL_DEV_OFFSET,
11560 + state->iomem_base ? "iomem" : "port",
11561 + state->iomem_base ? (unsigned long)state->iomem_base :
11562 + state->port, state->irq, uart_config[state->type].name);
11563 + tty_register_devfs(&serial_driver, 0,
11564 + serial_driver.minor_start + state->line);
11565 + tty_register_devfs(&callout_driver, 0,
11566 + callout_driver.minor_start + state->line);
11567 + return state->line + SERIAL_DEV_OFFSET;
11568 +}
11569 +
11570 +/**
11571 + * unregister_serial - deconfigure a 16x50 serial port
11572 + * @line: line to deconfigure
11573 + *
11574 + * The port specified is deconfigured and its resources are freed. Any
11575 + * user of the port is disconnected as if carrier was dropped. Line is
11576 + * the port number returned by register_serial().
11577 + */
11578 +
11579 +void unregister_serial(int line)
11580 +{
11581 + unsigned long flags;
11582 + struct serial_state *state = &rs_table[line];
11583 +
11584 + save_flags(flags); cli();
11585 + if (state->info && state->info->tty)
11586 + tty_hangup(state->info->tty);
11587 + state->type = PORT_UNKNOWN;
11588 + printk(KERN_INFO "ttyS%02d unloaded\n", state->line);
11589 + /* These will be hidden, because they are devices that will no longer
11590 + * be available to the system. (ie, PCMCIA modems, once ejected)
11591 + */
11592 + tty_unregister_devfs(&serial_driver,
11593 + serial_driver.minor_start + state->line);
11594 + tty_unregister_devfs(&callout_driver,
11595 + callout_driver.minor_start + state->line);
11596 + restore_flags(flags);
11597 +}
11598 +
11599 +static void __exit rs_fini(void)
11600 +{
11601 + unsigned long flags;
11602 + int e1, e2;
11603 + int i;
11604 + struct async_struct *info;
11605 +
11606 + /* printk("Unloading %s: version %s\n", serial_name, serial_version); */
11607 + del_timer_sync(&serial_timer);
11608 + save_flags(flags); cli();
11609 + remove_bh(SERIAL_BH);
11610 + if ((e1 = tty_unregister_driver(&serial_driver)))
11611 + printk("serial: failed to unregister serial driver (%d)\n",
11612 + e1);
11613 + if ((e2 = tty_unregister_driver(&callout_driver)))
11614 + printk("serial: failed to unregister callout driver (%d)\n",
11615 + e2);
11616 + restore_flags(flags);
11617 +
11618 + for (i = 0; i < NR_PORTS; i++) {
11619 + if ((info = rs_table[i].info)) {
11620 + rs_table[i].info = NULL;
11621 + kfree(info);
11622 + }
11623 + if ((rs_table[i].type != PORT_UNKNOWN) && rs_table[i].port) {
11624 +#ifdef CONFIG_SERIAL_RSA
11625 + if (rs_table[i].type == PORT_RSA)
11626 + release_region(rs_table[i].port +
11627 + UART_RSA_BASE, 16);
11628 + else
11629 +#endif
11630 + release_region(rs_table[i].port, 8);
11631 + }
11632 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
11633 + if (rs_table[i].iomem_base)
11634 + iounmap(rs_table[i].iomem_base);
11635 +#endif
11636 + }
11637 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
11638 + for (i=0; i < NR_PCI_BOARDS; i++) {
11639 + struct pci_board_inst *brd = &serial_pci_board[i];
11640 +
11641 + if (serial_pci_board[i].dev == 0)
11642 + continue;
11643 + if (brd->board.init_fn)
11644 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
11645 + if (DEACTIVATE_FUNC(brd->dev))
11646 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
11647 + }
11648 +#endif
11649 + if (tmp_buf) {
11650 + unsigned long pg = (unsigned long) tmp_buf;
11651 + tmp_buf = NULL;
11652 + free_page(pg);
11653 + }
11654 +
11655 +#ifdef ENABLE_SERIAL_PCI
11656 + if (serial_pci_driver.name[0])
11657 + pci_unregister_driver (&serial_pci_driver);
11658 +#endif
11659 +}
11660 +
11661 +module_init(rs_init);
11662 +module_exit(rs_fini);
11663 +MODULE_DESCRIPTION("Standard/generic (dumb) serial driver");
11664 +MODULE_AUTHOR("Theodore Ts'o <tytso@mit.edu>");
11665 +MODULE_LICENSE("GPL");
11666 +
11667 +
11668 +/*
11669 + * ------------------------------------------------------------
11670 + * Serial console driver
11671 + * ------------------------------------------------------------
11672 + */
11673 +#ifdef CONFIG_SERIAL_CONSOLE
11674 +
11675 +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
11676 +
11677 +static struct async_struct async_sercons;
11678 +
11679 +/*
11680 + * Wait for transmitter & holding register to empty
11681 + */
11682 +static inline void wait_for_xmitr(struct async_struct *info)
11683 +{
11684 + unsigned int status, tmout = 1000000;
11685 +
11686 + do {
11687 + status = serial_in(info, UART_LSR);
11688 +
11689 + if (status & UART_LSR_BI)
11690 + lsr_break_flag = UART_LSR_BI;
11691 +
11692 + if (--tmout == 0)
11693 + break;
11694 + } while((status & BOTH_EMPTY) != BOTH_EMPTY);
11695 +
11696 + /* Wait for flow control if necessary */
11697 + if (info->flags & ASYNC_CONS_FLOW) {
11698 + tmout = 1000000;
11699 + while (--tmout &&
11700 + ((serial_in(info, UART_MSR) & UART_MSR_CTS) == 0));
11701 + }
11702 +}
11703 +
11704 +
11705 +/*
11706 + * Print a string to the serial port trying not to disturb
11707 + * any possible real use of the port...
11708 + *
11709 + * The console must be locked when we get here.
11710 + */
11711 +static void serial_console_write(struct console *co, const char *s,
11712 + unsigned count)
11713 +{
11714 + static struct async_struct *info = &async_sercons;
11715 + int ier;
11716 + unsigned i;
11717 +
11718 + /*
11719 + * First save the IER then disable the interrupts
11720 + */
11721 + ier = serial_in(info, UART_IER);
11722 + serial_out(info, UART_IER, 0x00);
11723 +
11724 + /*
11725 + * Now, do each character
11726 + */
11727 + for (i = 0; i < count; i++, s++) {
11728 + wait_for_xmitr(info);
11729 +
11730 + /*
11731 + * Send the character out.
11732 + * If a LF, also do CR...
11733 + */
11734 + serial_out(info, UART_TX, *s);
11735 + if (*s == 10) {
11736 + wait_for_xmitr(info);
11737 + serial_out(info, UART_TX, 13);
11738 + }
11739 + }
11740 +
11741 + /*
11742 + * Finally, Wait for transmitter & holding register to empty
11743 + * and restore the IER
11744 + */
11745 + wait_for_xmitr(info);
11746 + serial_out(info, UART_IER, ier);
11747 +}
11748 +
11749 +static kdev_t serial_console_device(struct console *c)
11750 +{
11751 + return MKDEV(TTY_MAJOR, 64 + c->index);
11752 +}
11753 +
11754 +/*
11755 + * Setup initial baud/bits/parity/flow control. We do two things here:
11756 + * - construct a cflag setting for the first rs_open()
11757 + * - initialize the serial port
11758 + * Return non-zero if we didn't find a serial port.
11759 + */
11760 +static int __init serial_console_setup(struct console *co, char *options)
11761 +{
11762 + static struct async_struct *info;
11763 + struct serial_state *state;
11764 + unsigned cval;
11765 + int baud = 9600;
11766 + int bits = 8;
11767 + int parity = 'n';
11768 + int doflow = 0;
11769 + int cflag = CREAD | HUPCL | CLOCAL;
11770 + int quot = 0;
11771 + char *s;
11772 +
11773 + if (options) {
11774 + baud = simple_strtoul(options, NULL, 10);
11775 + s = options;
11776 + while(*s >= '0' && *s <= '9')
11777 + s++;
11778 + if (*s) parity = *s++;
11779 + if (*s) bits = *s++ - '0';
11780 + if (*s) doflow = (*s++ == 'r');
11781 + }
11782 +
11783 + /*
11784 + * Now construct a cflag setting.
11785 + */
11786 + switch(baud) {
11787 + case 1200:
11788 + cflag |= B1200;
11789 + break;
11790 + case 2400:
11791 + cflag |= B2400;
11792 + break;
11793 + case 4800:
11794 + cflag |= B4800;
11795 + break;
11796 + case 19200:
11797 + cflag |= B19200;
11798 + break;
11799 + case 38400:
11800 + cflag |= B38400;
11801 + break;
11802 + case 57600:
11803 + cflag |= B57600;
11804 + break;
11805 + case 115200:
11806 + cflag |= B115200;
11807 + break;
11808 + case 9600:
11809 + default:
11810 + cflag |= B9600;
11811 + /*
11812 + * Set this to a sane value to prevent a divide error
11813 + */
11814 + baud = 9600;
11815 + break;
11816 + }
11817 + switch(bits) {
11818 + case 7:
11819 + cflag |= CS7;
11820 + break;
11821 + default:
11822 + case 8:
11823 + cflag |= CS8;
11824 + break;
11825 + }
11826 + switch(parity) {
11827 + case 'o': case 'O':
11828 + cflag |= PARODD;
11829 + break;
11830 + case 'e': case 'E':
11831 + cflag |= PARENB;
11832 + break;
11833 + }
11834 + co->cflag = cflag;
11835 +
11836 + /*
11837 + * Divisor, bytesize and parity
11838 + */
11839 + state = rs_table + co->index;
11840 + if (doflow)
11841 + state->flags |= ASYNC_CONS_FLOW;
11842 + info = &async_sercons;
11843 + info->magic = SERIAL_MAGIC;
11844 + info->state = state;
11845 + info->port = state->port;
11846 + info->flags = state->flags;
11847 +#ifdef CONFIG_HUB6
11848 + info->hub6 = state->hub6;
11849 +#endif
11850 + info->io_type = state->io_type;
11851 + info->iomem_base = state->iomem_base;
11852 + info->iomem_reg_shift = state->iomem_reg_shift;
11853 + quot = state->baud_base / baud;
11854 + cval = cflag & (CSIZE | CSTOPB);
11855 +#if defined(__powerpc__) || defined(__alpha__)
11856 + cval >>= 8;
11857 +#else /* !__powerpc__ && !__alpha__ */
11858 + cval >>= 4;
11859 +#endif /* !__powerpc__ && !__alpha__ */
11860 + if (cflag & PARENB)
11861 + cval |= UART_LCR_PARITY;
11862 + if (!(cflag & PARODD))
11863 + cval |= UART_LCR_EPAR;
11864 +
11865 + /*
11866 + * Disable UART interrupts, set DTR and RTS high
11867 + * and set speed.
11868 + */
11869 + serial_out(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
11870 + serial_out(info, UART_DLL, quot & 0xff); /* LS of divisor */
11871 + serial_out(info, UART_DLM, quot >> 8); /* MS of divisor */
11872 + serial_out(info, UART_LCR, cval); /* reset DLAB */
11873 + serial_out(info, UART_IER, 0);
11874 + serial_out(info, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
11875 +
11876 + /*
11877 + * If we read 0xff from the LSR, there is no UART here.
11878 + */
11879 + if (serial_in(info, UART_LSR) == 0xff)
11880 + return -1;
11881 +
11882 + return 0;
11883 +}
11884 +
11885 +static struct console sercons = {
11886 + name: "ttyS",
11887 + write: serial_console_write,
11888 + device: serial_console_device,
11889 + setup: serial_console_setup,
11890 + flags: CON_PRINTBUFFER,
11891 + index: -1,
11892 +};
11893 +
11894 +/*
11895 + * Register console.
11896 + */
11897 +void __init serial_console_init(void)
11898 +{
11899 + register_console(&sercons);
11900 +}
11901 +#endif
11902 +
11903 +/*
11904 + Local variables:
11905 + compile-command: "gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing -pipe -fno-strength-reduce -march=i586 -DMODULE -DMODVERSIONS -include ../../include/linux/modversions.h -DEXPORT_SYMTAB -c serial.c"
11906 + End:
11907 +*/
11908 diff -urN linux.old/drivers/char/ticfg/Makefile linux.dev/drivers/char/ticfg/Makefile
11909 --- linux.old/drivers/char/ticfg/Makefile 1970-01-01 01:00:00.000000000 +0100
11910 +++ linux.dev/drivers/char/ticfg/Makefile 2005-11-10 01:10:46.051587500 +0100
11911 @@ -0,0 +1,6 @@
11912 +
11913 +O_TARGET := ticfg.o
11914 +
11915 +obj-$(CONFIG_AR7_ADAM2) := adam2_env.o
11916 +
11917 +include $(TOPDIR)/Rules.make
11918 diff -urN linux.old/drivers/char/ticfg/adam2_env.c linux.dev/drivers/char/ticfg/adam2_env.c
11919 --- linux.old/drivers/char/ticfg/adam2_env.c 1970-01-01 01:00:00.000000000 +0100
11920 +++ linux.dev/drivers/char/ticfg/adam2_env.c 2005-11-10 01:10:46.051587500 +0100
11921 @@ -0,0 +1,85 @@
11922 +#include <linux/types.h>
11923 +#include <linux/errno.h>
11924 +#include <linux/module.h>
11925 +#include <linux/kernel.h>
11926 +#include <linux/proc_fs.h>
11927 +#include <linux/fcntl.h>
11928 +#include <linux/init.h>
11929 +
11930 +#include <asm/ar7/adam2_env.h>
11931 +
11932 +#undef ADAM2_ENV_DEBUG
11933 +
11934 +#ifdef ADAM2_ENV_DEBUG
11935 +#define DPRINTK(args...) do { printk(args); } while(0);
11936 +#else
11937 +#define DPRINTK(args...) do { } while(0);
11938 +#endif
11939 +
11940 +#define ADAM2_ENV_DIR "ticfg"
11941 +#define ADAM2_ENV_NAME "env"
11942 +
11943 +static struct proc_dir_entry *adam2_env_proc_dir;
11944 +static struct proc_dir_entry *adam2_env_proc_ent;
11945 +
11946 +static int
11947 +adam2_proc_read_env(char *page, char **start, off_t pos, int count,
11948 + int *eof, void *data)
11949 +{
11950 + int len;
11951 + t_env_var *env;
11952 +
11953 + if (pos > 0)
11954 + return 0;
11955 +
11956 + len=0;
11957 + for (env = prom_iterenv(0); env; env = prom_iterenv(env)) {
11958 + if (env->val) {
11959 + /* XXX check for page len */
11960 + len += sprintf(page + len, "%s\t%s\n",
11961 + env->name, env->val);
11962 + }
11963 + }
11964 +
11965 + *eof=1;
11966 + return len;
11967 +}
11968 +
11969 +static int __init
11970 +adam2_env_init(void)
11971 +{
11972 +
11973 + DPRINTK("%s\n", __FUNCTION__);
11974 +
11975 + adam2_env_proc_dir = proc_mkdir(ADAM2_ENV_DIR, NULL);
11976 + if (!adam2_env_proc_dir) {
11977 + printk(KERN_ERR "%s: Unable to create /proc/%s entry\n",
11978 + __FUNCTION__, ADAM2_ENV_DIR);
11979 + return -ENOMEM;
11980 + }
11981 +
11982 + adam2_env_proc_ent =
11983 + create_proc_entry(ADAM2_ENV_NAME, 0444, adam2_env_proc_dir);
11984 + if (!adam2_env_proc_ent) {
11985 + printk(KERN_ERR "%s: Unable to create /proc/%s/%s entry\n",
11986 + __FUNCTION__, ADAM2_ENV_DIR, ADAM2_ENV_NAME);
11987 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
11988 + return -ENOMEM;
11989 + }
11990 + adam2_env_proc_ent->read_proc = adam2_proc_read_env;
11991 +
11992 + return 0;
11993 +}
11994 +
11995 +static
11996 +void __exit
11997 +adam2_env_cleanup(void)
11998 +{
11999 + remove_proc_entry(ADAM2_ENV_NAME, adam2_env_proc_dir);
12000 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
12001 +}
12002 +
12003 +module_init(adam2_env_init);
12004 +module_exit(adam2_env_cleanup);
12005 +
12006 +MODULE_LICENSE("GPL");
12007 diff -urN linux.old/include/asm-mips/addrspace.h linux.dev/include/asm-mips/addrspace.h
12008 --- linux.old/include/asm-mips/addrspace.h 2002-11-29 00:53:15.000000000 +0100
12009 +++ linux.dev/include/asm-mips/addrspace.h 2005-11-10 01:14:16.400733500 +0100
12010 @@ -11,6 +11,8 @@
12011 #ifndef __ASM_MIPS_ADDRSPACE_H
12012 #define __ASM_MIPS_ADDRSPACE_H
12013
12014 +#include <linux/config.h>
12015 +
12016 /*
12017 * Configure language
12018 */
12019 @@ -102,4 +104,11 @@
12020 #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
12021 #define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a))
12022
12023 +#ifdef CONFIG_AR7_MEMORY
12024 +#define PHYS_OFFSET ((unsigned long)(CONFIG_AR7_MEMORY))
12025 +#else
12026 +#define PHYS_OFFSET (0)
12027 +#endif
12028 +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
12029 +
12030 #endif /* __ASM_MIPS_ADDRSPACE_H */
12031 diff -urN linux.old/include/asm-mips/ar7/adam2_env.h linux.dev/include/asm-mips/ar7/adam2_env.h
12032 --- linux.old/include/asm-mips/ar7/adam2_env.h 1970-01-01 01:00:00.000000000 +0100
12033 +++ linux.dev/include/asm-mips/ar7/adam2_env.h 2005-11-10 01:10:46.067588500 +0100
12034 @@ -0,0 +1,13 @@
12035 +#ifndef _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12036 +#define _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12037 +
12038 +/* Environment variable */
12039 +typedef struct {
12040 + char *name;
12041 + char *val;
12042 +} t_env_var;
12043 +
12044 +char *prom_getenv(char *);
12045 +t_env_var *prom_iterenv(t_env_var *);
12046 +
12047 +#endif /* _INCLUDE_ASM_AR7_ADAM2_ENV_H_ */
12048 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
12049 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
12050 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-11-10 01:10:46.067588500 +0100
12051 @@ -0,0 +1,33 @@
12052 +/*
12053 + * $Id$
12054 + * Copyright (C) $Date$ $Author$
12055 + *
12056 + * This program is free software; you can redistribute it and/or modify
12057 + * it under the terms of the GNU General Public License as published by
12058 + * the Free Software Foundation; either version 2 of the License, or
12059 + * (at your option) any later version.
12060 + *
12061 + * This program is distributed in the hope that it will be useful,
12062 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12063 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12064 + * GNU General Public License for more details.
12065 + *
12066 + * You should have received a copy of the GNU General Public License
12067 + * along with this program; if not, write to the Free Software
12068 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
12069 + *
12070 + */
12071 +
12072 +#ifndef _AR7_H
12073 +#define _AR7_H
12074 +
12075 +#include <asm/addrspace.h>
12076 +#include <linux/config.h>
12077 +
12078 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
12079 +
12080 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
12081 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
12082 +#define AR7_BASE_BAUD ( 3686400 / 16 )
12083 +
12084 +#endif
12085 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
12086 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
12087 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-11-10 01:10:46.067588500 +0100
12088 @@ -0,0 +1,292 @@
12089 + /*
12090 + * Nitin Dhingra, iamnd@ti.com
12091 + * Copyright (C) 2000 Texas Instruments Inc.
12092 + *
12093 + *
12094 + * ########################################################################
12095 + *
12096 + * This program is free software; you can distribute it and/or modify it
12097 + * under the terms of the GNU General Public License (Version 2) as
12098 + * published by the Free Software Foundation.
12099 + *
12100 + * This program is distributed in the hope it will be useful, but WITHOUT
12101 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12102 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12103 + * for more details.
12104 + *
12105 + * You should have received a copy of the GNU General Public License along
12106 + * with this program; if not, write to the Free Software Foundation, Inc.,
12107 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
12108 + *
12109 + * ########################################################################
12110 + *
12111 + * Defines of the Sead board specific address-MAP, registers, etc.
12112 + *
12113 + */
12114 +#ifndef _AVALANCHE_INTC_H
12115 +#define _AVALANCHE_INTC_H
12116 +
12117 +#include <linux/config.h>
12118 +
12119 +/* ----- */
12120 +
12121 +#define KSEG1_BASE 0xA0000000
12122 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
12123 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
12124 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
12125 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
12126 +
12127 +/* ----- */
12128 +
12129 +#define MIPS_EXCEPTION_OFFSET 8
12130 +
12131 +/******************************************************************************
12132 + Avalanche Interrupt number
12133 +******************************************************************************/
12134 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
12135 +
12136 +/*******************************************************************************
12137 +*Linux Interrupt number
12138 +*******************************************************************************/
12139 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
12140 +
12141 +
12142 +
12143 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
12144 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
12145 +
12146 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
12147 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
12148 +
12149 +#define AVALANCHE_INTC_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
12150 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) + \
12151 + MIPS_EXCEPTION_OFFSET)
12152 +
12153 +#if defined(CONFIG_AR7_VLYNQ)
12154 +#define AVALANCHE_INT_END_LOW_VLYNQ (AVALANCHE_INTC_END + 32)
12155 +#define AVALANCHE_INT_END_VLYNQ (AVALANCHE_INTC_END + 32 * CONFIG_AR7_VLYNQ_PORTS)
12156 +#define AVALANCHE_INT_END AVALANCHE_INT_END_VLYNQ
12157 +#else
12158 +#define AVALANCHE_INT_END AVALANCHE_INTC_END
12159 +#endif
12160 +
12161 +
12162 +/*
12163 + * Avalanche interrupt controller register base (primary)
12164 + */
12165 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
12166 +
12167 +/******************************************************************************
12168 + * Avalanche exception controller register base (secondary)
12169 + ******************************************************************************/
12170 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
12171 +
12172 +
12173 +/******************************************************************************
12174 + * Avalanche Interrupt pacing register base (secondary)
12175 + ******************************************************************************/
12176 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
12177 +
12178 +
12179 +
12180 +/******************************************************************************
12181 + * Avalanche Interrupt Channel Control register base
12182 + *****************************************************************************/
12183 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
12184 +
12185 +
12186 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
12187 +{
12188 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
12189 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
12190 + volatile unsigned long unused1; /*0x08 */
12191 + volatile unsigned long unused2; /*0x0C */
12192 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
12193 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
12194 + volatile unsigned long unused3; /*0x18 */
12195 + volatile unsigned long unused4; /*0x1C */
12196 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
12197 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
12198 + volatile unsigned long unused5; /*0x28 */
12199 + volatile unsigned long unused6; /*0x2C */
12200 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
12201 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
12202 + volatile unsigned long unused7; /* 0x38 */
12203 + volatile unsigned long unused8; /* 0x3c */
12204 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
12205 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
12206 + volatile unsigned long unused9; /* 0x48 */
12207 + volatile unsigned long unused10; /* 0x4C */
12208 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
12209 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
12210 + volatile unsigned long unused11; /* 0x58 */
12211 + volatile unsigned long unused12; /*0x5C */
12212 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
12213 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
12214 +};
12215 +
12216 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
12217 +{
12218 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
12219 + volatile unsigned long reserved; /*0x84 */
12220 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
12221 + volatile unsigned long reserved1; /*0x8c */
12222 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
12223 + volatile unsigned long reserved2; /*0x94 */
12224 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
12225 +};
12226 +struct avalanche_ipace_regs
12227 +{
12228 +
12229 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
12230 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
12231 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
12232 +};
12233 +struct avalanche_channel_int_number
12234 +{
12235 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
12236 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
12237 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
12238 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
12239 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
12240 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
12241 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
12242 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
12243 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
12244 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
12245 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
12246 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
12247 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
12248 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
12249 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
12250 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
12251 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
12252 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
12253 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
12254 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
12255 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
12256 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
12257 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
12258 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
12259 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
12260 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
12261 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
12262 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
12263 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
12264 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
12265 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
12266 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
12267 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
12268 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
12269 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
12270 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
12271 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
12272 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
12273 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
12274 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
12275 +};
12276 +
12277 +struct avalanche_interrupt_line_to_channel
12278 +{
12279 + unsigned long int_line0; /* Start of primary interrupts */
12280 + unsigned long int_line1;
12281 + unsigned long int_line2;
12282 + unsigned long int_line3;
12283 + unsigned long int_line4;
12284 + unsigned long int_line5;
12285 + unsigned long int_line6;
12286 + unsigned long int_line7;
12287 + unsigned long int_line8;
12288 + unsigned long int_line9;
12289 + unsigned long int_line10;
12290 + unsigned long int_line11;
12291 + unsigned long int_line12;
12292 + unsigned long int_line13;
12293 + unsigned long int_line14;
12294 + unsigned long int_line15;
12295 + unsigned long int_line16;
12296 + unsigned long int_line17;
12297 + unsigned long int_line18;
12298 + unsigned long int_line19;
12299 + unsigned long int_line20;
12300 + unsigned long int_line21;
12301 + unsigned long int_line22;
12302 + unsigned long int_line23;
12303 + unsigned long int_line24;
12304 + unsigned long int_line25;
12305 + unsigned long int_line26;
12306 + unsigned long int_line27;
12307 + unsigned long int_line28;
12308 + unsigned long int_line29;
12309 + unsigned long int_line30;
12310 + unsigned long int_line31;
12311 + unsigned long int_line32;
12312 + unsigned long int_line33;
12313 + unsigned long int_line34;
12314 + unsigned long int_line35;
12315 + unsigned long int_line36;
12316 + unsigned long int_line37;
12317 + unsigned long int_line38;
12318 + unsigned long int_line39;
12319 +};
12320 +
12321 +
12322 +/* Interrupt Line #'s (Sangam peripherals) */
12323 +
12324 +/*------------------------------*/
12325 +/* Sangam primary interrupts */
12326 +/*------------------------------*/
12327 +
12328 +#define UNIFIED_SECONDARY_INTERRUPT 0
12329 +#define AVALANCHE_EXT_INT_0 1
12330 +#define AVALANCHE_EXT_INT_1 2
12331 +/* Line #3 Reserved */
12332 +/* Line #4 Reserved */
12333 +#define AVALANCHE_TIMER_0_INT 5
12334 +#define AVALANCHE_TIMER_1_INT 6
12335 +#define AVALANCHE_UART0_INT 7
12336 +#define AVALANCHE_UART1_INT 8
12337 +#define AVALANCHE_PDMA_INT0 9
12338 +#define AVALANCHE_PDMA_INT1 10
12339 +/* Line #11 Reserved */
12340 +/* Line #12 Reserved */
12341 +/* Line #13 Reserved */
12342 +/* Line #14 Reserved */
12343 +#define AVALANCHE_ATM_SAR_INT 15
12344 +/* Line #16 Reserved */
12345 +/* Line #17 Reserved */
12346 +/* Line #18 Reserved */
12347 +#define AVALANCHE_MAC0_INT 19
12348 +/* Line #20 Reserved */
12349 +#define AVALANCHE_VLYNQ0_INT 21
12350 +#define AVALANCHE_CODEC_WAKE_INT 22
12351 +/* Line #23 Reserved */
12352 +#define AVALANCHE_USB_INT 24
12353 +#define AVALANCHE_VLYNQ1_INT 25
12354 +/* Line #26 Reserved */
12355 +/* Line #27 Reserved */
12356 +#define AVALANCHE_MAC1_INT 28
12357 +#define AVALANCHE_I2CM_INT 29
12358 +#define AVALANCHE_PDMA_INT2 30
12359 +#define AVALANCHE_PDMA_INT3 31
12360 +/* Line #32 Reserved */
12361 +/* Line #33 Reserved */
12362 +/* Line #34 Reserved */
12363 +/* Line #35 Reserved */
12364 +/* Line #36 Reserved */
12365 +#define AVALANCHE_VDMA_VT_RX_INT 37
12366 +#define AVALANCHE_VDMA_VT_TX_INT 38
12367 +#define AVALANCHE_ADSLSS_INT 39
12368 +
12369 +/*-----------------------------------*/
12370 +/* Sangam Secondary Interrupts */
12371 +/*-----------------------------------*/
12372 +#define PRIMARY_INTS 40
12373 +
12374 +#define EMIF_INT (7 + PRIMARY_INTS)
12375 +
12376 +
12377 +extern void avalanche_int_set(int channel, int line);
12378 +
12379 +
12380 +#endif /* _AVALANCHE_INTC_H */
12381 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
12382 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
12383 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-11-10 01:10:46.067588500 +0100
12384 @@ -0,0 +1,174 @@
12385 +#ifndef _AVALANCHE_MISC_H_
12386 +#define _AVALANCHE_MISC_H_
12387 +
12388 +typedef enum AVALANCHE_ERR_t
12389 +{
12390 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
12391 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
12392 +
12393 + /* Pointers and args */
12394 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
12395 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
12396 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
12397 +
12398 + /* Memory issues */
12399 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
12400 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
12401 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
12402 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
12403 +
12404 + /* Device issues */
12405 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
12406 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
12407 +
12408 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
12409 +
12410 +} AVALANCHE_ERR;
12411 +
12412 +/*****************************************************************************
12413 + * Reset Control Module
12414 + *****************************************************************************/
12415 +
12416 +typedef enum AVALANCHE_RESET_MODULE_tag
12417 +{
12418 + RESET_MODULE_UART0 = 0,
12419 + RESET_MODULE_UART1 = 1,
12420 + RESET_MODULE_I2C = 2,
12421 + RESET_MODULE_TIMER0 = 3,
12422 + RESET_MODULE_TIMER1 = 4,
12423 + RESET_MODULE_GPIO = 6,
12424 + RESET_MODULE_ADSLSS = 7,
12425 + RESET_MODULE_USBS = 8,
12426 + RESET_MODULE_SAR = 9,
12427 + RESET_MODULE_VDMA_VT = 11,
12428 + RESET_MODULE_FSER = 12,
12429 + RESET_MODULE_VLYNQ1 = 16,
12430 + RESET_MODULE_EMAC0 = 17,
12431 + RESET_MODULE_DMA = 18,
12432 + RESET_MODULE_BIST = 19,
12433 + RESET_MODULE_VLYNQ0 = 20,
12434 + RESET_MODULE_EMAC1 = 21,
12435 + RESET_MODULE_MDIO = 22,
12436 + RESET_MODULE_ADSLSS_DSP = 23,
12437 + RESET_MODULE_EPHY = 26
12438 +} AVALANCHE_RESET_MODULE_T;
12439 +
12440 +typedef enum AVALANCHE_RESET_CTRL_tag
12441 +{
12442 + IN_RESET = 0,
12443 + OUT_OF_RESET
12444 +} AVALANCHE_RESET_CTRL_T;
12445 +
12446 +typedef enum AVALANCHE_SYS_RST_MODE_tag
12447 +{
12448 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
12449 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
12450 +} AVALANCHE_SYS_RST_MODE_T;
12451 +
12452 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
12453 +{
12454 + HARDWARE_RESET = 0,
12455 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
12456 + WATCHDOG_RESET,
12457 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
12458 +} AVALANCHE_SYS_RESET_STATUS_T;
12459 +
12460 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
12461 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
12462 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
12463 +
12464 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
12465 +
12466 +/*****************************************************************************
12467 + * Power Control Module
12468 + *****************************************************************************/
12469 +
12470 +typedef enum AVALANCHE_POWER_CTRL_tag
12471 +{
12472 + POWER_CTRL_POWER_UP = 0,
12473 + POWER_CTRL_POWER_DOWN
12474 +} AVALANCHE_POWER_CTRL_T;
12475 +
12476 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
12477 +{
12478 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
12479 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
12480 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
12481 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
12482 +} AVALANCHE_SYS_POWER_MODE_T;
12483 +
12484 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
12485 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
12486 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
12487 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
12488 +
12489 +/*****************************************************************************
12490 + * Wakeup Control
12491 + *****************************************************************************/
12492 +
12493 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
12494 +{
12495 + WAKEUP_INT0 = 1,
12496 + WAKEUP_INT1 = 2,
12497 + WAKEUP_INT2 = 4,
12498 + WAKEUP_INT3 = 8
12499 +} AVALANCHE_WAKEUP_INTERRUPT_T;
12500 +
12501 +typedef enum TNETV1050_WAKEUP_CTRL_tag
12502 +{
12503 + WAKEUP_DISABLED = 0,
12504 + WAKEUP_ENABLED
12505 +} AVALANCHE_WAKEUP_CTRL_T;
12506 +
12507 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
12508 +{
12509 + WAKEUP_ACTIVE_HIGH = 0,
12510 + WAKEUP_ACTIVE_LOW
12511 +} AVALANCHE_WAKEUP_POLARITY_T;
12512 +
12513 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
12514 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
12515 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
12516 +
12517 +/*****************************************************************************
12518 + * GPIO Control
12519 + *****************************************************************************/
12520 +
12521 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
12522 +{
12523 + FUNCTIONAL_PIN = 0,
12524 + GPIO_PIN = 1
12525 +} AVALANCHE_GPIO_PIN_MODE_T;
12526 +
12527 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
12528 +{
12529 + GPIO_OUTPUT_PIN = 0,
12530 + GPIO_INPUT_PIN = 1
12531 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
12532 +
12533 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
12534 +
12535 +void avalanche_gpio_init(void);
12536 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
12537 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
12538 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
12539 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
12540 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
12541 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
12542 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
12543 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
12544 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
12545 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
12546 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
12547 +
12548 +unsigned int avalanche_get_chip_version_info(void);
12549 +
12550 +unsigned int avalanche_get_vbus_freq(void);
12551 +void avalanche_set_vbus_freq(unsigned int);
12552 +
12553 +
12554 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
12555 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
12556 +unsigned int avalanche_is_mdix_on_chip(void);
12557 +
12558 +#endif
12559 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
12560 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
12561 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-11-10 01:10:46.071588750 +0100
12562 @@ -0,0 +1,567 @@
12563 +/*
12564 + * $Id$
12565 + * Avalanche Register Descriptions
12566 + *
12567 + * Jeff Harrell, jharrell@ti.com
12568 + * 2000 (c) Texas Instruments Inc.
12569 + */
12570 +
12571 +#ifndef __AVALANCHE_REGS_H
12572 +#define __AVALANCHE_REGS_H
12573 +
12574 +#include <asm/addrspace.h>
12575 +#include <linux/config.h>
12576 +
12577 +/*----------------------------------------*/
12578 +/* Base offsets within the Avalanche ASIC */
12579 +/*----------------------------------------*/
12580 +
12581 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
12582 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
12583 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
12584 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
12585 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
12586 +#define DES_BASE (KSEG1ADDR(0x08600000))
12587 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
12588 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
12589 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
12590 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
12591 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
12592 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
12593 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
12594 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
12595 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
12596 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
12597 +#define I2C_BASE (KSEG1ADDR(0x08611000))
12598 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
12599 +#define USB_BASE (KSEG1ADDR(0x08611200))
12600 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
12601 +#define DMA_BASE (KSEG1ADDR(0x08611400))
12602 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
12603 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
12604 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
12605 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
12606 +
12607 +/*---------------------------------*/
12608 +/* Device ID, chip version number */
12609 +/*---------------------------------*/
12610 +
12611 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
12612 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
12613 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
12614 +
12615 +/*----------------------------------*/
12616 +/* Reset Control VW changed to ptrs */
12617 +/*----------------------------------*/
12618 +
12619 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
12620 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
12621 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
12622 +
12623 +/* reset control bits */
12624 +
12625 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
12626 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
12627 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
12628 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
12629 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
12630 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
12631 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
12632 +/*
12633 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12634 + If you reset the GPIO interface all of the directions (i/o) of the UART B
12635 + interface pins are inputs and must be reconfigured so as not to lose the
12636 + serial console interface
12637 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12638 +*/
12639 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
12640 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
12641 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
12642 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
12643 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
12644 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
12645 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
12646 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
12647 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
12648 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
12649 +
12650 +/*----------------------*/
12651 +/* Physical interfaces */
12652 +/*----------------------*/
12653 +
12654 +/* Phy loopback */
12655 +#define PHY_LOOPBACK 1
12656 +
12657 +
12658 +/* Phy 0 */
12659 +#define PHY0BASE (PHY_BASE)
12660 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
12661 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
12662 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
12663 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
12664 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
12665 +
12666 +
12667 +/* Phy 1 */
12668 +
12669 +#define PHY1BASE (PHY_BASE + 0x100000)
12670 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
12671 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
12672 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
12673 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
12674 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
12675 +
12676 +/* Phy 2 */
12677 +
12678 +#define PHY2BASE (PHY_BASE + 0x200000)
12679 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
12680 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
12681 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
12682 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
12683 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
12684 +
12685 +/*-------------------*/
12686 +/* Avalanche ATM SAR */
12687 +/*-------------------*/
12688 +
12689 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
12690 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
12691 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
12692 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
12693 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
12694 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
12695 +
12696 +/* Transmit completion ring registers */
12697 +
12698 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
12699 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
12700 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
12701 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
12702 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
12703 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
12704 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
12705 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
12706 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
12707 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
12708 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
12709 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
12710 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
12711 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
12712 +
12713 +/* Transmit Queue Packet registers */
12714 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
12715 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
12716 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
12717 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
12718 +/* Receive completion ring registers */
12719 +
12720 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
12721 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
12722 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
12723 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
12724 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
12725 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
12726 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
12727 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
12728 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
12729 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
12730 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
12731 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
12732 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
12733 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
12734 +
12735 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
12736 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
12737 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
12738 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
12739 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
12740 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
12741 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
12742 +
12743 +
12744 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
12745 +
12746 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
12747 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
12748 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
12749 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
12750 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
12751 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
12752 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
12753 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
12754 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
12755 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
12756 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
12757 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
12758 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
12759 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
12760 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
12761 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
12762 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
12763 +
12764 +
12765 +/*
12766 +
12767 +#define OAM_CPID_ADD 0xa30104e0
12768 +
12769 +#define OAM_LLID_ADD 0xa30104f0
12770 +
12771 +#define OAM_LLID_VAL 0xffffffff
12772 +
12773 +#define OAM_CORR_TAG 0xa3010500
12774 +
12775 +#define OAM_FAR_COUNT_ADD 0xa3010520
12776 +
12777 +#define OAM_NEAR_COUNT_ADD 0xa3010540
12778 +
12779 +#define OAM_CONFIG_REG_ADD 0xa3000018
12780 +*/
12781 +
12782 +
12783 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
12784 +
12785 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
12786 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
12787 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
12788 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
12789 +
12790 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
12791 +
12792 +
12793 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
12794 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
12795 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
12796 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
12797 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
12798 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
12799 +
12800 +/*------------------------------------------*/
12801 +/* DSL Interface */
12802 +/*------------------------------------------*/
12803 +
12804 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
12805 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
12806 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
12807 +
12808 +/* Fast */
12809 +
12810 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
12811 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
12812 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
12813 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
12814 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
12815 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
12816 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
12817 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
12818 +
12819 +/* Interleaved */
12820 +
12821 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
12822 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
12823 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
12824 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
12825 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
12826 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
12827 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
12828 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
12829 +
12830 +/*------------------------------------------*/
12831 +/* Broadband I/F */
12832 +/*------------------------------------------*/
12833 +
12834 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
12835 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
12836 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
12837 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
12838 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
12839 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
12840 +
12841 +#define AVBBIF_DISABLED 0x0
12842 +#define AVBBIF_LBT4040_INT 0x1
12843 +#define AVBBIF_XBUS 0x2
12844 +#define AVBBIF_LBT4040_EXT 0x4
12845 +
12846 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
12847 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
12848 +#define AVBBIF_TRANS_MASK 0xff000000
12849 +/*------------------------------------------*/
12850 +/* GPIO I/F */
12851 +/*------------------------------------------*/
12852 +
12853 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
12854 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
12855 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
12856 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
12857 +
12858 +#define GPIO_0 (1<<21)
12859 +#define GPIO_1 (1<<22)
12860 +#define GPIO_2 (1<<23)
12861 +#define GPIO_3 (1<<24)
12862 +#define EINT_1 (1<<18)
12863 +
12864 +/*
12865 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12866 + If you reset the GPIO interface all of the directions (i/o) of the UART B
12867 + interface pins are inputs and must be reconfigured so as not to lose the
12868 + serial console interface
12869 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12870 +*/
12871 +
12872 +/*------------------------------------------*/
12873 +/* CLK_CTRL */
12874 +/*------------------------------------------*/
12875 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
12876 +
12877 +#define PCLK_0_HALF_VBUS (0<<16)
12878 +#define PCLK_EQ_INPUT (1<<16)
12879 +#define BBIF_CLK_HALF_VBUS (0<<17)
12880 +#define BBIF_CLK_EQ_VBUS (1<<17)
12881 +#define BBIF_CLK_EQ_BBCLK (3<<17)
12882 +#define DSP_MODCLK_DSPCLKI (0<<20)
12883 +#define DSP_MODCLK_REFCLKI (1<<20)
12884 +#define USB_CLK_EQ_USBCLKI (0<<21)
12885 +#define USB_CLK_EQ_REFCLKI (1<<21)
12886 +
12887 +/*------------------------------------------*/
12888 +/* PCI Control Registers */
12889 +/*------------------------------------------*/
12890 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
12891 +#define PCIC_CONTROL_CFG_DONE (1<<0)
12892 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
12893 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
12894 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
12895 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
12896 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
12897 +#define PCIC_CONTROL_MEM_MASK (1<<6)
12898 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
12899 +#define PCIC_CONTROL_IO_MASK (1<<8)
12900 +/* PCIC_CONTROL_RESERVED (1<<9) */
12901 +#define PCIC_CONTROL_BASE0_EN (1<<10)
12902 +#define PCIC_CONTROL_BASE1_EN (1<<11)
12903 +#define PCIC_CONTROL_BASE2_EN (1<<12)
12904 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
12905 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
12906 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
12907 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
12908 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
12909 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
12910 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
12911 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
12912 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
12913 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
12914 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
12915 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
12916 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
12917 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
12918 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
12919 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
12920 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
12921 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
12922 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
12923 +#define PCIC_INT_CLEAR_PM (1<<0)
12924 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
12925 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
12926 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
12927 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
12928 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
12929 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
12930 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
12931 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
12932 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
12933 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
12934 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
12935 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
12936 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
12937 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
12938 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
12939 +#define PCIC_INT_EN_AVAL_PM (1<<0)
12940 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
12941 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
12942 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
12943 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
12944 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
12945 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
12946 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
12947 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
12948 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
12949 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
12950 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
12951 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
12952 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
12953 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
12954 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
12955 +#define PCIC_INT_EN_PCI_PM (1<<0)
12956 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
12957 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
12958 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
12959 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
12960 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
12961 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
12962 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
12963 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
12964 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
12965 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
12966 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
12967 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
12968 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
12969 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
12970 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
12971 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
12972 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
12973 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
12974 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
12975 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
12976 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
12977 +/* PCIC_PM_CTL_RESERVED (1<<2) */
12978 +/* PCIC_PM_CTL_RESERVED (1<<3) */
12979 +/* PCIC_PM_CTL_RESERVED (1<<4) */
12980 +/* PCIC_PM_CTL_RESERVED (1<<5) */
12981 +/* PCIC_PM_CTL_RESERVED (1<<6) */
12982 +/* PCIC_PM_CTL_RESERVED (1<<7) */
12983 +/* PCIC_PM_CTL_RESERVED (1<<8) */
12984 +/* PCIC_PM_CTL_RESERVED (1<<9) */
12985 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
12986 +#define PCIC_PM_CTL_PMEIN (1<<11)
12987 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
12988 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
12989 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
12990 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
12991 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
12992 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
12993 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
12994 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
12995 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
12996 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
12997 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
12998 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
12999 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
13000 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
13001 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
13002 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
13003 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
13004 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
13005 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
13006 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
13007 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
13008 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
13009 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
13010 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
13011 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
13012 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
13013 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
13014 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
13015 +
13016 +/*------------------------------------------*/
13017 +/* IIC_INTERFACE */
13018 +/*------------------------------------------*/
13019 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
13020 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
13021 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
13022 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
13023 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
13024 +
13025 +#define I2CWRITE 0x200
13026 +#define I2CREAD 0x300
13027 +#define I2C_END_BURST 0x400
13028 +
13029 +/* read bits */
13030 +#define I2C_READ_ERROR 0x8000
13031 +#define I2C_READ_COMPLETE 0x4000
13032 +#define I2C_READ_BUSY 0x2000
13033 +
13034 +/* device types */
13035 +#define I2C_IO_EXPANDER 0x2
13036 +#define I2C_RTC 0xd
13037 +
13038 +/* device Addresses on I2C bus (EVM3) */
13039 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
13040 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
13041 +#define EVM3_RTC_I2C_ADDR 0x0
13042 +
13043 +/*------------------------------------------*/
13044 +/* Ethernet MAC register offset definitions */
13045 +/*------------------------------------------*/
13046 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
13047 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
13048 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
13049 +
13050 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13051 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
13052 +
13053 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
13054 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
13055 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
13056 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
13057 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
13058 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
13059 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
13060 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
13061 +
13062 +
13063 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
13064 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
13065 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
13066 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
13067 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
13068 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
13069 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
13070 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
13071 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
13072 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
13073 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
13074 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
13075 +
13076 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
13077 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
13078 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
13079 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
13080 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
13081 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
13082 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
13083 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
13084 +
13085 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
13086 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
13087 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
13088 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
13089 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
13090 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
13091 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
13092 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
13093 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
13094 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
13095 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
13096 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
13097 +
13098 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
13099 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
13100 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
13101 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
13102 +
13103 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
13104 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
13105 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
13106 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
13107 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
13108 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
13109 +
13110 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13111 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
13112 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
13113 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
13114 +
13115 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
13116 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
13117 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
13118 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
13119 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
13120 +
13121 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
13122 +
13123 +#endif __AVALANCHE_REGS_H
13124 +
13125 +
13126 +
13127 +
13128 +
13129 +
13130 diff -urN linux.old/include/asm-mips/ar7/avalanche_types.h linux.dev/include/asm-mips/ar7/avalanche_types.h
13131 --- linux.old/include/asm-mips/ar7/avalanche_types.h 1970-01-01 01:00:00.000000000 +0100
13132 +++ linux.dev/include/asm-mips/ar7/avalanche_types.h 2005-11-10 01:10:46.071588750 +0100
13133 @@ -0,0 +1,126 @@
13134 +/*------------------------------------------------------------------------------------------*\
13135 +\*------------------------------------------------------------------------------------------*/
13136 +#ifndef _avalanche_types_h_
13137 +#define _avalanche_types_h_
13138 +
13139 +/*--- #include <asm/avalanche/generic/hal_modules/haltypes.h> ---*/
13140 +#ifndef TRUE
13141 +#define TRUE 1
13142 +#endif
13143 +#ifndef FALSE
13144 +#define FALSE 0
13145 +#endif
13146 +#ifndef NULL
13147 +#define NULL (void *)0
13148 +#endif
13149 +
13150 +/*------------------------------------------------------------------------------------------*\
13151 + * Typen für Texas GPL Module
13152 +\*------------------------------------------------------------------------------------------*/
13153 +#ifndef __UINT8_T__
13154 +typedef unsigned char UINT8;
13155 +#define __UINT8_T__
13156 +#endif
13157 +
13158 +#ifndef __UCHAR_T__
13159 +typedef unsigned char UCHAR;
13160 +#define __UCHAR_T__
13161 +#endif
13162 +
13163 +#ifndef __INT8_T__
13164 +typedef signed char INT8;
13165 +#define __INT8_T__
13166 +#endif
13167 +
13168 +#ifndef __UINT16_T__
13169 +typedef unsigned short UINT16;
13170 +#define __UINT16_T__
13171 +#endif
13172 +
13173 +#ifndef __USHORT_T__
13174 +typedef unsigned short USHORT;
13175 +#define __USHORT_T__
13176 +#endif
13177 +
13178 +#ifndef __INT16_T__
13179 +typedef signed short INT16;
13180 +#define __INT16_T__
13181 +#endif
13182 +
13183 +#ifndef __UINT32_T__
13184 +typedef unsigned int UINT32;
13185 +#define __UINT32_T__
13186 +#endif
13187 +
13188 +#ifndef __UINT_T__
13189 +typedef unsigned int UINT;
13190 +#define __UINT_T__
13191 +#endif
13192 +
13193 +#ifndef __INT32_T__
13194 +typedef signed int INT32;
13195 +#define __INT32_T__
13196 +#endif
13197 +
13198 +#ifndef __ULONG_T__
13199 +typedef unsigned long ULONG;
13200 +#define __ULONG_T__
13201 +#endif
13202 +
13203 +#ifndef __BOOL_T__
13204 +typedef int BOOL;
13205 +#define __BOOL_T__
13206 +#endif
13207 +
13208 +#ifndef __STATUS_T__
13209 +typedef int STATUS;
13210 +#define __STATUS_T__
13211 +#endif
13212 +
13213 +/*------------------------------------------------------------------------------------------*\
13214 +\*------------------------------------------------------------------------------------------*/
13215 +typedef void (*p_vlynq_intr_cntrl_isr_t)(void *,void *,void *);
13216 +typedef INT32 (*p_vlynq_interrupt_vector_set_t)(void *, UINT32, UINT32, INT32, INT32, INT32);
13217 +typedef INT32 (*p_vlynq_interrupt_vector_cntl_t)(void *, UINT32, INT32, UINT32);
13218 +typedef UINT32 (*p_vlynq_interrupt_get_count_t)(void *, UINT32);
13219 +typedef INT32 (*p_vlynq_install_isr_t)(void *, UINT32, p_vlynq_intr_cntrl_isr_t, void *, void *, void *);
13220 +typedef INT32 (*p_vlynq_uninstall_isr_t)(void *, UINT32, void *, void *, void *);
13221 +typedef void (*p_vlynq_root_isr_t)(void *);
13222 +typedef void (*p_vlynq_delay_t)(UINT32);
13223 +typedef INT32 (*p_vlynq_interrupt_vector_map_t)(void *, INT32, UINT32, UINT32);
13224 +typedef INT32 (*p_vlynq_interrupt_set_polarity_t)(void *, INT32, UINT32, INT32);
13225 +typedef INT32 (*p_vlynq_interrupt_get_polarity_t)(void *, INT32, UINT32);
13226 +typedef INT32 (*p_vlynq_interrupt_set_type_t)(void *, INT32, UINT32, INT32);
13227 +typedef INT32 (*p_vlynq_interrupt_get_type_t)(void *, INT32, UINT32);
13228 +typedef INT32 (*p_vlynq_interrupt_enable_t)(void *, INT32, UINT32);
13229 +typedef INT32 (*p_vlynq_interrupt_disable_t)(void *, INT32, UINT32);
13230 +
13231 +/*------------------------------------------------------------------------------------------*\
13232 +\*------------------------------------------------------------------------------------------*/
13233 +extern p_vlynq_interrupt_vector_set_t p_vlynq_interrupt_vector_set;
13234 +extern p_vlynq_interrupt_vector_cntl_t p_vlynq_interrupt_vector_cntl;
13235 +extern p_vlynq_interrupt_get_count_t p_vlynq_interrupt_get_count;
13236 +extern p_vlynq_install_isr_t p_vlynq_install_isr;
13237 +extern p_vlynq_uninstall_isr_t p_vlynq_uninstall_isr;
13238 +extern p_vlynq_root_isr_t p_vlynq_root_isr;
13239 +extern p_vlynq_delay_t p_vlynq_delay;
13240 +extern p_vlynq_interrupt_vector_map_t p_vlynq_interrupt_vector_map;
13241 +extern p_vlynq_interrupt_set_polarity_t p_vlynq_interrupt_set_polarity;
13242 +extern p_vlynq_interrupt_get_polarity_t p_vlynq_interrupt_get_polarity;
13243 +extern p_vlynq_interrupt_set_type_t p_vlynq_interrupt_set_type;
13244 +extern p_vlynq_interrupt_get_type_t p_vlynq_interrupt_get_type;
13245 +extern p_vlynq_interrupt_enable_t p_vlynq_interrupt_enable;
13246 +extern p_vlynq_interrupt_disable_t p_vlynq_interrupt_disable;
13247 +extern void *p_vlynqDevice0;
13248 +extern void *p_vlynqDevice1;
13249 +
13250 +/*------------------------------------------------------------------------------------------*\
13251 +\*------------------------------------------------------------------------------------------*/
13252 +enum _avalanche_need_ {
13253 + avalanche_need_vlynq,
13254 + avalanche_need_auto_mdix
13255 +};
13256 +
13257 +int avalanche_need(enum _avalanche_need_);
13258 +
13259 +#endif /*--- #ifndef _avalanche_types_h_ ---*/
13260 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
13261 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
13262 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-11-10 01:10:46.071588750 +0100
13263 @@ -0,0 +1,26 @@
13264 +/*******************************************************************************
13265 + * FILE PURPOSE: Interface port id Header file
13266 + *******************************************************************************
13267 + * FILE NAME: if_port.h
13268 + *
13269 + * DESCRIPTION: Header file carrying information about port ids of interfaces
13270 + *
13271 + *
13272 + * (C) Copyright 2003, Texas Instruments, Inc
13273 + ******************************************************************************/
13274 +#ifndef _IF_PORT_H_
13275 +#define _IF_PORT_H_
13276 +
13277 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
13278 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
13279 +#define AVALANCHE_USB_PORT_ID 2
13280 +#define AVALANCHE_WLAN_PORT_ID 3
13281 +
13282 +
13283 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
13284 +
13285 +/* The marvell ports occupy port ids from 4 to 8 */
13286 +/* so the next port id number should start at 9 */
13287 +
13288 +
13289 +#endif /* _IF_PORT_H_ */
13290 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
13291 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
13292 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-11-10 01:10:46.071588750 +0100
13293 @@ -0,0 +1,180 @@
13294 +#ifndef _SANGAM_H_
13295 +#define _SANGAM_H_
13296 +
13297 +#include <linux/config.h>
13298 +#include <asm/addrspace.h>
13299 +
13300 +/*----------------------------------------------------
13301 + * Sangam's Module Base Addresses
13302 + *--------------------------------------------------*/
13303 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
13304 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
13305 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
13306 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
13307 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
13308 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
13309 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
13310 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
13311 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
13312 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
13313 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
13314 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
13315 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
13316 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
13317 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
13318 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
13319 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
13320 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
13321 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
13322 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
13323 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
13324 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
13325 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
13326 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
13327 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
13328 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
13329 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
13330 +
13331 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
13332 +
13333 +
13334 +/*----------------------------------------------------
13335 + * Sangam Interrupt Map (Primary Interrupts)
13336 + *--------------------------------------------------*/
13337 +
13338 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
13339 +#define AVALANCHE_EXT_INT_0 1
13340 +#define AVALANCHE_EXT_INT_1 2
13341 +/* Line# 3 to 4 are reserved */
13342 +#define AVALANCHE_TIMER_0_INT 5
13343 +#define AVALANCHE_TIMER_1_INT 6
13344 +#define AVALANCHE_UART0_INT 7
13345 +#define AVALANCHE_UART1_INT 8
13346 +#define AVALANCHE_DMA_INT0 9
13347 +#define AVALANCHE_DMA_INT1 10
13348 +/* Line# 11 to 14 are reserved */
13349 +#define AVALANCHE_ATM_SAR_INT 15
13350 +/* Line# 16 to 18 are reserved */
13351 +#define AVALANCHE_LOW_CPMAC_INT 19
13352 +/* Line# 20 is reserved */
13353 +#define AVALANCHE_LOW_VLYNQ_INT 21
13354 +#define AVALANCHE_CODEC_WAKEUP_INT 22
13355 +/* Line# 23 is reserved */
13356 +#define AVALANCHE_USB_SLAVE_INT 24
13357 +#define AVALANCHE_HIGH_VLYNQ_INT 25
13358 +/* Line# 26 to 27 are reserved */
13359 +#define AVALANCHE_UNIFIED_PHY_INT 28
13360 +#define AVALANCHE_I2C_INT 29
13361 +#define AVALANCHE_DMA_INT2 30
13362 +#define AVALANCHE_DMA_INT3 31
13363 +/* Line# 32 is reserved */
13364 +#define AVALANCHE_HIGH_CPMAC_INT 33
13365 +/* Line# 34 to 36 is reserved */
13366 +#define AVALANCHE_VDMA_VT_RX_INT 37
13367 +#define AVALANCHE_VDMA_VT_TX_INT 38
13368 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
13369 +
13370 +
13371 +#define AVALANCHE_EMIF_INT 47
13372 +
13373 +
13374 +
13375 +/*-----------------------------------------------------------
13376 + * Sangam's Reset Bits
13377 + *---------------------------------------------------------*/
13378 +
13379 +#define AVALANCHE_UART0_RESET_BIT 0
13380 +#define AVALANCHE_UART1_RESET_BIT 1
13381 +#define AVALANCHE_I2C_RESET_BIT 2
13382 +#define AVALANCHE_TIMER0_RESET_BIT 3
13383 +#define AVALANCHE_TIMER1_RESET_BIT 4
13384 +/* Reset bit 5 is reserved. */
13385 +#define AVALANCHE_GPIO_RESET_BIT 6
13386 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
13387 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
13388 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
13389 +/* Reset bit 10 is reserved. */
13390 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
13391 +#define AVALANCHE_FSER_RESET_BIT 12
13392 +/* Reset bit 13 to 15 are reserved */
13393 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
13394 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
13395 +#define AVALANCHE_MCDMA_RESET_BIT 18
13396 +#define AVALANCHE_BIST_RESET_BIT 19
13397 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
13398 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
13399 +#define AVALANCHE_MDIO_RESET_BIT 22
13400 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
13401 +/* Reset bit 24 to 25 are reserved */
13402 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
13403 +/* Reset bit 27 to 31 are reserved */
13404 +
13405 +
13406 +#define AVALANCHE_POWER_MODULE_USBSP 0
13407 +#define AVALANCHE_POWER_MODULE_WDTP 1
13408 +#define AVALANCHE_POWER_MODULE_UT0P 2
13409 +#define AVALANCHE_POWER_MODULE_UT1P 3
13410 +#define AVALANCHE_POWER_MODULE_IICP 4
13411 +#define AVALANCHE_POWER_MODULE_VDMAP 5
13412 +#define AVALANCHE_POWER_MODULE_GPIOP 6
13413 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
13414 +#define AVALANCHE_POWER_MODULE_SARP 8
13415 +#define AVALANCHE_POWER_MODULE_ADSLP 9
13416 +#define AVALANCHE_POWER_MODULE_EMIFP 10
13417 +#define AVALANCHE_POWER_MODULE_ADSPP 12
13418 +#define AVALANCHE_POWER_MODULE_RAMP 13
13419 +#define AVALANCHE_POWER_MODULE_ROMP 14
13420 +#define AVALANCHE_POWER_MODULE_DMAP 15
13421 +#define AVALANCHE_POWER_MODULE_BISTP 16
13422 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
13423 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
13424 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
13425 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
13426 +#define AVALANCHE_POWER_MODULE_EPHYP 24
13427 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
13428 +
13429 +
13430 +
13431 +
13432 +
13433 +/*
13434 + * Sangam board vectors
13435 + */
13436 +
13437 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
13438 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
13439 +
13440 +/*-----------------------------------------------------------------------------
13441 + * Sangam's system register.
13442 + *
13443 + *---------------------------------------------------------------------------*/
13444 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
13445 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
13446 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
13447 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
13448 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
13449 +
13450 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
13451 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
13452 +
13453 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
13454 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
13455 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
13456 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
13457 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
13458 +
13459 +/*
13460 + * Yamon Prom print address.
13461 + */
13462 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
13463 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
13464 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
13465 +
13466 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
13467 +
13468 +#define AVALANCHE_GPIO_PIN_COUNT 32
13469 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
13470 +
13471 +#include "sangam_boards.h"
13472 +
13473 +#endif /*_SANGAM_H_ */
13474 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
13475 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
13476 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-11-10 01:10:46.071588750 +0100
13477 @@ -0,0 +1,77 @@
13478 +#ifndef _SANGAM_BOARDS_H
13479 +#define _SANGAM_BOARDS_H
13480 +
13481 +// Let us define board specific information here.
13482 +
13483 +
13484 +#if defined(CONFIG_AR7DB)
13485 +
13486 +#define AFECLK_FREQ 35328000
13487 +#define REFCLK_FREQ 25000000
13488 +#define OSC3_FREQ 24000000
13489 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13490 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
13491 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13492 +
13493 +#endif
13494 +
13495 +
13496 +#if defined(CONFIG_AR7RD)
13497 +#define AFECLK_FREQ 35328000
13498 +#define REFCLK_FREQ 25000000
13499 +#define OSC3_FREQ 24000000
13500 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13501 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13502 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13503 +#endif
13504 +
13505 +
13506 +#if defined(CONFIG_AR7WI)
13507 +#define AFECLK_FREQ 35328000
13508 +#define REFCLK_FREQ 25000000
13509 +#define OSC3_FREQ 24000000
13510 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13511 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13512 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13513 +#endif
13514 +
13515 +
13516 +#if defined(CONFIG_AR7V)
13517 +#define AFECLK_FREQ 35328000
13518 +#define REFCLK_FREQ 25000000
13519 +#define OSC3_FREQ 24000000
13520 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13521 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13522 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13523 +#endif
13524 +
13525 +
13526 +#if defined(CONFIG_AR7WRD)
13527 +#define AFECLK_FREQ 35328000
13528 +#define REFCLK_FREQ 25000000
13529 +#define OSC3_FREQ 24000000
13530 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13531 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
13532 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13533 +#endif
13534 +
13535 +
13536 +#if defined(CONFIG_AR7VWI)
13537 +#define AFECLK_FREQ 35328000
13538 +#define REFCLK_FREQ 25000000
13539 +#define OSC3_FREQ 24000000
13540 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13541 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
13542 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13543 +#endif
13544 +
13545 +
13546 +#if defined CONFIG_SEAD2
13547 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
13548 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
13549 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
13550 +#include <asm/mips-boards/sead.h>
13551 +#endif
13552 +
13553 +
13554 +#endif
13555 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
13556 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
13557 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-11-10 01:10:46.075589000 +0100
13558 @@ -0,0 +1,338 @@
13559 +/******************************************************************************
13560 + * FILE PURPOSE: TNETD73xx Common Header File
13561 + ******************************************************************************
13562 + * FILE NAME: tnetd73xx.h
13563 + *
13564 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
13565 + *
13566 + * REVISION HISTORY:
13567 + * 27 Nov 02 - PSP TII
13568 + *
13569 + * (C) Copyright 2002, Texas Instruments, Inc
13570 + *******************************************************************************/
13571 +
13572 +/*
13573 + *
13574 + *
13575 + * These are const, typedef, and api definitions for tnetd73xx.
13576 + *
13577 + * NOTES:
13578 + * 1. This file may be included into both C and Assembly files.
13579 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
13580 + * avoid C data types (typedefs) below;
13581 + * - for .c files, you don't have to do anything special.
13582 + *
13583 + * 2. This file has a number of sections for each SOC subsystem. When adding
13584 + * a new constant, find the subsystem you are working on and follow the
13585 + * name pattern. If you are adding another typedef for your interface, please,
13586 + * place it with other typedefs and function prototypes.
13587 + *
13588 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
13589 + * cluttering. Include such items directly into the module's .c file or have a
13590 + * local .h file to pass data between smaller modules. This file defines only
13591 + * shared items.
13592 + */
13593 +
13594 +#ifndef __TNETD73XX_H__
13595 +#define __TNETD73XX_H__
13596 +
13597 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
13598 +
13599 +extern unsigned int tnetd73xx_mips_freq;
13600 +extern unsigned int tnetd73xx_vbus_freq;
13601 +
13602 +#include "tnetd73xx_err.h"
13603 +
13604 +#endif /* _ASMLANGUAGE */
13605 +
13606 +
13607 +/*******************************************************************************************
13608 +* Emerald core specific
13609 +******************************************************************************************** */
13610 +
13611 +#ifdef BIG_ENDIAN
13612 +#elif defined(LITTLE_ENDIAN)
13613 +#else
13614 +#error Need to define endianism
13615 +#endif
13616 +
13617 +#ifndef KSEG_MSK
13618 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
13619 +#endif
13620 +
13621 +#ifndef KSEG_INV_MASK
13622 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
13623 +#endif
13624 +
13625 +#ifndef KSEG0_BASE
13626 +#define KSEG0_BASE 0x80000000
13627 +#endif
13628 +
13629 +#ifndef KSEG1_BASE
13630 +#define KSEG1_BASE 0xA0000000
13631 +#endif
13632 +
13633 +#ifndef KSEG0
13634 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
13635 +#endif
13636 +
13637 +#ifndef KSEG1
13638 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
13639 +#endif
13640 +
13641 +#ifndef KUSEG
13642 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
13643 +#endif
13644 +
13645 +#ifndef PHYS_ADDR
13646 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
13647 +#endif
13648 +
13649 +#ifndef PHYS_TO_K0
13650 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
13651 +#endif
13652 +
13653 +#ifndef PHYS_TO_K1
13654 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
13655 +#endif
13656 +
13657 +#ifndef REG8_ADDR
13658 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
13659 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
13660 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
13661 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
13662 +#endif
13663 +
13664 +#ifndef REG16_ADDR
13665 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
13666 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
13667 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
13668 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
13669 +#endif
13670 +
13671 +#ifndef REG32_ADDR
13672 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
13673 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
13674 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
13675 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
13676 +#endif
13677 +
13678 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
13679 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
13680 +#endif
13681 +
13682 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
13683 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
13684 +#endif
13685 +
13686 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
13687 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
13688 +#endif
13689 +
13690 +/* TNETD73XX chip definations */
13691 +
13692 +#define FREQ_1MHZ 1000000
13693 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
13694 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
13695 +
13696 +#ifdef AR7SEAD2
13697 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
13698 +#else
13699 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
13700 +#endif
13701 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
13702 +
13703 +
13704 +
13705 +/* Module base addresses */
13706 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
13707 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
13708 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
13709 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
13710 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
13711 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
13712 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
13713 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
13714 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
13715 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
13716 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
13717 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
13718 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
13719 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
13720 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
13721 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
13722 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
13723 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
13724 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
13725 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
13726 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
13727 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
13728 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
13729 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
13730 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
13731 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
13732 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
13733 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
13734 +
13735 +/* BBIF Registers */
13736 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
13737 +
13738 +/* Device Configuration Latch Registers */
13739 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
13740 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
13741 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
13742 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
13743 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
13744 +
13745 +/* GPIO Control */
13746 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
13747 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
13748 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
13749 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
13750 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
13751 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
13752 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
13753 +
13754 +/* Reset Control */
13755 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
13756 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
13757 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
13758 +
13759 +/* Power Control */
13760 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
13761 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
13762 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
13763 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
13764 +
13765 +/* Clock Control */
13766 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
13767 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
13768 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
13769 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
13770 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
13771 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
13772 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
13773 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
13774 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
13775 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
13776 +
13777 +/* EMIF control */
13778 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
13779 +
13780 +/* UART */
13781 +#ifdef AR7SEAD2
13782 +#define TNETD73XX_UART_FREQ 3686400
13783 +#else
13784 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
13785 +#endif
13786 +
13787 +/* Interrupt Controller */
13788 +
13789 +/* Primary interrupts */
13790 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
13791 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
13792 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
13793 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
13794 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
13795 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
13796 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
13797 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
13798 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
13799 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
13800 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
13801 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
13802 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
13803 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
13804 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
13805 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
13806 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
13807 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
13808 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
13809 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
13810 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
13811 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
13812 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
13813 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
13814 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
13815 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
13816 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
13817 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
13818 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
13819 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
13820 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
13821 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
13822 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
13823 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
13824 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
13825 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
13826 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
13827 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
13828 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
13829 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
13830 +
13831 +/* Secondary interrupts */
13832 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
13833 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
13834 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
13835 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
13836 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
13837 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
13838 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
13839 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
13840 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
13841 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
13842 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
13843 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
13844 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
13845 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
13846 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
13847 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
13848 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
13849 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
13850 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
13851 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
13852 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
13853 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
13854 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
13855 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
13856 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
13857 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
13858 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
13859 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
13860 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
13861 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
13862 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
13863 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
13864 +
13865 +/* These ugly macros are to access the -1 registers, like config1 */
13866 +#define MFC0_SEL1_OPCODE(dst, src)\
13867 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
13868 + nop; \
13869 + nop; \
13870 + nop
13871 +
13872 +#define MTC0_SEL1_OPCODE(dst, src)\
13873 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
13874 + nop; \
13875 + nop; \
13876 + nop
13877 +
13878 +
13879 +/* Below are Jade core specific */
13880 +#define CFG0_4K_IL_MASK 0x00380000
13881 +#define CFG0_4K_IL_SHIFT 19
13882 +#define CFG0_4K_IA_MASK 0x00070000
13883 +#define CFG0_4K_IA_SHIFT 16
13884 +#define CFG0_4K_IS_MASK 0x01c00000
13885 +#define CFG0_4K_IS_SHIFT 22
13886 +
13887 +#define CFG0_4K_DL_MASK 0x00001c00
13888 +#define CFG0_4K_DL_SHIFT 10
13889 +#define CFG0_4K_DA_MASK 0x00000380
13890 +#define CFG0_4K_DA_SHIFT 7
13891 +#define CFG0_4K_DS_MASK 0x0000E000
13892 +#define CFG0_4K_DS_SHIFT 13
13893 +
13894 +
13895 +
13896 +#endif /* __TNETD73XX_H_ */
13897 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
13898 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
13899 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-11-10 01:10:46.075589000 +0100
13900 @@ -0,0 +1,42 @@
13901 +/******************************************************************************
13902 + * FILE PURPOSE: TNETD73xx Error Definations Header File
13903 + ******************************************************************************
13904 + * FILE NAME: tnetd73xx_err.h
13905 + *
13906 + * DESCRIPTION: Error definations for TNETD73XX
13907 + *
13908 + * REVISION HISTORY:
13909 + * 27 Nov 02 - PSP TII
13910 + *
13911 + * (C) Copyright 2002, Texas Instruments, Inc
13912 + *******************************************************************************/
13913 +
13914 +
13915 +#ifndef __TNETD73XX_ERR_H__
13916 +#define __TNETD73XX_ERR_H__
13917 +
13918 +typedef enum TNETD73XX_ERR_t
13919 +{
13920 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
13921 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
13922 +
13923 + /* Pointers and args */
13924 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
13925 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
13926 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
13927 +
13928 + /* Memory issues */
13929 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
13930 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
13931 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
13932 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
13933 +
13934 + /* Device issues */
13935 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
13936 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
13937 +
13938 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
13939 +
13940 +} TNETD73XX_ERR;
13941 +
13942 +#endif /* __TNETD73XX_ERR_H__ */
13943 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
13944 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
13945 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-11-10 01:10:46.075589000 +0100
13946 @@ -0,0 +1,239 @@
13947 +/******************************************************************************
13948 + * FILE PURPOSE: TNETD73xx Misc modules API Header
13949 + ******************************************************************************
13950 + * FILE NAME: tnetd73xx_misc.h
13951 + *
13952 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
13953 + * FSER Modules API
13954 + * As per TNETD73xx specifications
13955 + *
13956 + * REVISION HISTORY:
13957 + * 27 Nov 02 - Sharath Kumar PSP TII
13958 + * 14 Feb 03 - Anant Gole PSP TII
13959 + *
13960 + * (C) Copyright 2002, Texas Instruments, Inc
13961 + *******************************************************************************/
13962 +
13963 +#ifndef __TNETD73XX_MISC_H__
13964 +#define __TNETD73XX_MISC_H__
13965 +
13966 +/*****************************************************************************
13967 + * Reset Control Module
13968 + *****************************************************************************/
13969 +
13970 +typedef enum TNETD73XX_RESET_MODULE_tag
13971 +{
13972 + RESET_MODULE_UART0 = 0,
13973 + RESET_MODULE_UART1 = 1,
13974 + RESET_MODULE_I2C = 2,
13975 + RESET_MODULE_TIMER0 = 3,
13976 + RESET_MODULE_TIMER1 = 4,
13977 + RESET_MODULE_GPIO = 6,
13978 + RESET_MODULE_ADSLSS = 7,
13979 + RESET_MODULE_USBS = 8,
13980 + RESET_MODULE_SAR = 9,
13981 + RESET_MODULE_VDMA_VT = 11,
13982 + RESET_MODULE_FSER = 12,
13983 + RESET_MODULE_VLYNQ1 = 16,
13984 + RESET_MODULE_EMAC0 = 17,
13985 + RESET_MODULE_DMA = 18,
13986 + RESET_MODULE_BIST = 19,
13987 + RESET_MODULE_VLYNQ0 = 20,
13988 + RESET_MODULE_EMAC1 = 21,
13989 + RESET_MODULE_MDIO = 22,
13990 + RESET_MODULE_ADSLSS_DSP = 23,
13991 + RESET_MODULE_EPHY = 26
13992 +} TNETD73XX_RESET_MODULE_T;
13993 +
13994 +typedef enum TNETD73XX_RESET_CTRL_tag
13995 +{
13996 + IN_RESET = 0,
13997 + OUT_OF_RESET
13998 +} TNETD73XX_RESET_CTRL_T;
13999 +
14000 +typedef enum TNETD73XX_SYS_RST_MODE_tag
14001 +{
14002 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
14003 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
14004 +} TNETD73XX_SYS_RST_MODE_T;
14005 +
14006 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
14007 +{
14008 + HARDWARE_RESET = 0,
14009 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
14010 + WATCHDOG_RESET,
14011 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
14012 +} TNETD73XX_SYS_RESET_STATUS_T;
14013 +
14014 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
14015 + TNETD73XX_RESET_CTRL_T reset_ctrl);
14016 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
14017 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
14018 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
14019 +
14020 +/*****************************************************************************
14021 + * Power Control Module
14022 + *****************************************************************************/
14023 +
14024 +typedef enum TNETD73XX_POWER_MODULE_tag
14025 +{
14026 + POWER_MODULE_USBSP = 0,
14027 + POWER_MODULE_WDTP = 1,
14028 + POWER_MODULE_UT0P = 2,
14029 + POWER_MODULE_UT1P = 3,
14030 + POWER_MODULE_IICP = 4,
14031 + POWER_MODULE_VDMAP = 5,
14032 + POWER_MODULE_GPIOP = 6,
14033 + POWER_MODULE_VLYNQ1P = 7,
14034 + POWER_MODULE_SARP = 8,
14035 + POWER_MODULE_ADSLP = 9,
14036 + POWER_MODULE_EMIFP = 10,
14037 + POWER_MODULE_ADSPP = 12,
14038 + POWER_MODULE_RAMP = 13,
14039 + POWER_MODULE_ROMP = 14,
14040 + POWER_MODULE_DMAP = 15,
14041 + POWER_MODULE_BISTP = 16,
14042 + POWER_MODULE_TIMER0P = 18,
14043 + POWER_MODULE_TIMER1P = 19,
14044 + POWER_MODULE_EMAC0P = 20,
14045 + POWER_MODULE_EMAC1P = 22,
14046 + POWER_MODULE_EPHYP = 24,
14047 + POWER_MODULE_VLYNQ0P = 27,
14048 +} TNETD73XX_POWER_MODULE_T;
14049 +
14050 +typedef enum TNETD73XX_POWER_CTRL_tag
14051 +{
14052 + POWER_CTRL_POWER_UP = 0,
14053 + POWER_CTRL_POWER_DOWN
14054 +} TNETD73XX_POWER_CTRL_T;
14055 +
14056 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
14057 +{
14058 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
14059 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
14060 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
14061 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
14062 +} TNETD73XX_SYS_POWER_MODE_T;
14063 +
14064 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
14065 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
14066 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
14067 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
14068 +
14069 +/*****************************************************************************
14070 + * Wakeup Control
14071 + *****************************************************************************/
14072 +
14073 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
14074 +{
14075 + WAKEUP_INT0 = 1,
14076 + WAKEUP_INT1 = 2,
14077 + WAKEUP_INT2 = 4,
14078 + WAKEUP_INT3 = 8
14079 +} TNETD73XX_WAKEUP_INTERRUPT_T;
14080 +
14081 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
14082 +{
14083 + WAKEUP_DISABLED = 0,
14084 + WAKEUP_ENABLED
14085 +} TNETD73XX_WAKEUP_CTRL_T;
14086 +
14087 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
14088 +{
14089 + WAKEUP_ACTIVE_HIGH = 0,
14090 + WAKEUP_ACTIVE_LOW
14091 +} TNETD73XX_WAKEUP_POLARITY_T;
14092 +
14093 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
14094 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
14095 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
14096 +
14097 +/*****************************************************************************
14098 + * FSER Control
14099 + *****************************************************************************/
14100 +
14101 +typedef enum TNETD73XX_FSER_MODE_tag
14102 +{
14103 + FSER_I2C = 0,
14104 + FSER_UART = 1
14105 +} TNETD73XX_FSER_MODE_T;
14106 +
14107 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
14108 +
14109 +/*****************************************************************************
14110 + * Clock Control
14111 + *****************************************************************************/
14112 +
14113 +#define CLK_MHZ(x) ( (x) * 1000000 )
14114 +
14115 +typedef enum TNETD73XX_CLKC_ID_tag
14116 +{
14117 + CLKC_SYS = 0,
14118 + CLKC_MIPS,
14119 + CLKC_USB,
14120 + CLKC_ADSLSS
14121 +} TNETD73XX_CLKC_ID_T;
14122 +
14123 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
14124 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
14125 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
14126 +
14127 +/*****************************************************************************
14128 + * GPIO Control
14129 + *****************************************************************************/
14130 +
14131 +typedef enum TNETD73XX_GPIO_PIN_tag
14132 +{
14133 + GPIO_UART0_RD = 0,
14134 + GPIO_UART0_TD = 1,
14135 + GPIO_UART0_RTS = 2,
14136 + GPIO_UART0_CTS = 3,
14137 + GPIO_FSER_CLK = 4,
14138 + GPIO_FSER_D = 5,
14139 + GPIO_EXT_AFE_SCLK = 6,
14140 + GPIO_EXT_AFE_TX_FS = 7,
14141 + GPIO_EXT_AFE_TXD = 8,
14142 + GPIO_EXT_AFE_RS_FS = 9,
14143 + GPIO_EXT_AFE_RXD1 = 10,
14144 + GPIO_EXT_AFE_RXD0 = 11,
14145 + GPIO_EXT_AFE_CDIN = 12,
14146 + GPIO_EXT_AFE_CDOUT = 13,
14147 + GPIO_EPHY_SPEED100 = 14,
14148 + GPIO_EPHY_LINKON = 15,
14149 + GPIO_EPHY_ACTIVITY = 16,
14150 + GPIO_EPHY_FDUPLEX = 17,
14151 + GPIO_EINT0 = 18,
14152 + GPIO_EINT1 = 19,
14153 + GPIO_MBSP0_TCLK = 20,
14154 + GPIO_MBSP0_RCLK = 21,
14155 + GPIO_MBSP0_RD = 22,
14156 + GPIO_MBSP0_TD = 23,
14157 + GPIO_MBSP0_RFS = 24,
14158 + GPIO_MBSP0_TFS = 25,
14159 + GPIO_MII_DIO = 26,
14160 + GPIO_MII_DCLK = 27,
14161 +} TNETD73XX_GPIO_PIN_T;
14162 +
14163 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
14164 +{
14165 + FUNCTIONAL_PIN = 0,
14166 + GPIO_PIN = 1
14167 +} TNETD73XX_GPIO_PIN_MODE_T;
14168 +
14169 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
14170 +{
14171 + GPIO_OUTPUT_PIN = 0,
14172 + GPIO_INPUT_PIN = 1
14173 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
14174 +
14175 +void tnetd73xx_gpio_init(void);
14176 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
14177 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
14178 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
14179 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
14180 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
14181 +
14182 +/* TNETD73XX Revision */
14183 +__u32 tnetd73xx_get_revision(void);
14184 +
14185 +#endif /* __TNETD73XX_MISC_H__ */
14186 diff -urN linux.old/include/asm-mips/ar7/vlynq.h linux.dev/include/asm-mips/ar7/vlynq.h
14187 --- linux.old/include/asm-mips/ar7/vlynq.h 1970-01-01 01:00:00.000000000 +0100
14188 +++ linux.dev/include/asm-mips/ar7/vlynq.h 2005-11-10 01:10:46.095590250 +0100
14189 @@ -0,0 +1,610 @@
14190 +/***************************************************************************
14191 +**+----------------------------------------------------------------------+**
14192 +**| **** |**
14193 +**| **** |**
14194 +**| ******o*** |**
14195 +**| ********_///_**** |**
14196 +**| ***** /_//_/ **** |**
14197 +**| ** ** (__/ **** |**
14198 +**| ********* |**
14199 +**| **** |**
14200 +**| *** |**
14201 +**| |**
14202 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
14203 +**| ALL RIGHTS RESERVED |**
14204 +**| |**
14205 +**| Permission is hereby granted to licensees of Texas Instruments |**
14206 +**| Incorporated (TI) products to use this computer program for the sole |**
14207 +**| purpose of implementing a licensee product based on TI products. |**
14208 +**| No other rights to reproduce, use, or disseminate this computer |**
14209 +**| program, whether in part or in whole, are granted. |**
14210 +**| |**
14211 +**| TI makes no representation or warranties with respect to the |**
14212 +**| performance of this computer program, and specifically disclaims |**
14213 +**| any responsibility for any damages, special or consequential, |**
14214 +**| connected with the use of this program. |**
14215 +**| |**
14216 +**+----------------------------------------------------------------------+**
14217 +***************************************************************************/
14218 +
14219 +/*********************************************************************************
14220 + * ------------------------------------------------------------------------------
14221 + * Module : vlynq_hal.h
14222 + * Description :
14223 + * This header file provides the set of functions exported by the
14224 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
14225 + * ------------------------------------------------------------------------------
14226 + *********************************************************************************/
14227 +
14228 +#ifndef _VLYNQ_HAL_H_
14229 +#define _VLYNQ_HAL_H_
14230 +
14231 +/* Enable/Disable debug feature */
14232 +#undef VLYNQ_DEBUG
14233 +
14234 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
14235 +#define debugPrint(format,args...)
14236 +#else
14237 +#define debugPrint(format,args...)
14238 +#endif
14239 +
14240 + /* number of VLYNQ memory regions supported */
14241 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
14242 +
14243 + /* Max.number of external interrupt inputs supported by VLYNQ module */
14244 +#define VLYNQ_IVR_MAXIVR 0x08
14245 +
14246 +#define VLYNQ_CLK_DIV_MAX 0x08
14247 +#define VLYNQ_CLK_DIV_MIN 0x01
14248 +
14249 +
14250 +/*** the total number of entries allocated for ICB would be
14251 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
14252 +#define VLYNQ_IVR_CHAIN_SLOTS 10
14253 +
14254 +
14255 +/* Error defines */
14256 +#define VLYNQ_SUCCESS 0
14257 +
14258 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
14259 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
14260 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
14261 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
14262 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
14263 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
14264 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
14265 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
14266 +
14267 +/* Vlynq Defines and Macros */
14268 +
14269 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
14270 +
14271 +/* Base address of module */
14272 +#define VLYNQ_BASE (pdev->module_base)
14273 +
14274 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
14275 +
14276 +#define VLYNQ_REV_OFFSET 0x0000
14277 +#define VLYNQ_CTRL_OFFSET 0x0004
14278 +#define VLYNQ_STATUS_OFFSET 0x0008
14279 +#define VLYNQ_INT_STAT_OFFSET 0x0010
14280 +#define VLYNQ_INT_PEND_OFFSET 0x0014
14281 +#define VLYNQ_INT_PTR_OFFSET 0x0018
14282 +#define VLYNQ_TXMAP_OFFSET 0x001c
14283 +
14284 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
14285 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
14286 +
14287 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
14288 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
14289 +
14290 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
14291 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
14292 +
14293 +#define VLYNQ_REV_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
14294 +#define VLYNQ_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
14295 +#define VLYNQ_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
14296 +#define VLYNQ_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
14297 +#define VLYNQ_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
14298 +#define VLYNQ_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
14299 +#define VLYNQ_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
14300 +
14301 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14302 +#define VLYNQ_RXMAP_SIZE_REG(map) \
14303 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
14304 +
14305 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14306 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
14307 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
14308 +
14309 +#define VLYNQ_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
14310 +
14311 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
14312 +#define VLYNQ_IVR_OFFSET(ivr) \
14313 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
14314 +
14315 +#define VLYNQ_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(0)) )
14316 +#define VLYNQ_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(4)) )
14317 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14318 +
14319 +#define VLYNQ_IVR_INTEN(ivr) (((unsigned int)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
14320 +#define VLYNQ_IVR_INTTYPE(ivr) (((unsigned int)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
14321 +#define VLYNQ_IVR_INTPOL(ivr) (((unsigned int)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
14322 +#define VLYNQ_IVR_INTVEC(ivr) (((unsigned int)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
14323 +#define VLYNQ_IVR_INTALL(ivr) (((unsigned int)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
14324 +
14325 +
14326 +
14327 +/*********************************
14328 + * Remote VLYNQ register set *
14329 + *********************************/
14330 +
14331 +#define VLYNQ_R_REV_OFFSET 0x0080
14332 +#define VLYNQ_R_CTRL_OFFSET 0x0084
14333 +#define VLYNQ_R_STATUS_OFFSET 0x0088
14334 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
14335 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
14336 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
14337 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
14338 +
14339 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
14340 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
14341 +
14342 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
14343 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
14344 +
14345 +#define VLYNQ_R_REV_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
14346 +#define VLYNQ_R_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
14347 +#define VLYNQ_R_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
14348 +#define VLYNQ_R_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
14349 +#define VLYNQ_R_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
14350 +#define VLYNQ_R_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
14351 +#define VLYNQ_R_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
14352 +
14353 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14354 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
14355 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
14356 +
14357 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14358 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
14359 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
14360 +
14361 +#define VLYNQ_R_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
14362 +
14363 +#define VLYNQ_R_IVR_OFFSET(ivr) \
14364 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
14365 +
14366 +
14367 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14368 +#define VLYNQ_R_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(0)) )
14369 +#define VLYNQ_R_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(4)) )
14370 +
14371 +
14372 +/****End of remote register set definition******/
14373 +
14374 +
14375 +/*** Masks for individual register fields ***/
14376 +
14377 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
14378 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
14379 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
14380 +
14381 +
14382 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
14383 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
14384 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
14385 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
14386 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
14387 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
14388 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
14389 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
14390 +
14391 +
14392 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
14393 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
14394 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
14395 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
14396 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
14397 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
14398 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
14399 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
14400 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
14401 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
14402 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
14403 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
14404 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
14405 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
14406 +
14407 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
14408 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
14409 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
14410 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
14411 +
14412 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
14413 +
14414 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
14415 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
14416 +
14417 +#define VLYNQ_IVR_INTEN_MASK 0x80
14418 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
14419 +#define VLYNQ_IVR_INTPOL_MASK 0x20
14420 +
14421 +
14422 +/**** Helper macros ****/
14423 +
14424 +#define VLYNQ_RESETCB(arg) \
14425 + if( pdev->reset_cb != NULL) \
14426 + { \
14427 + (pdev->reset_cb)(pdev, (arg)); \
14428 + }
14429 +
14430 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
14431 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
14432 +
14433 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
14434 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
14435 +
14436 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
14437 +
14438 +
14439 +/*************************************
14440 + * Enums *
14441 + *************************************/
14442 +
14443 +/* Initialization options define what operations are
14444 + * undertaken during vlynq module initialization */
14445 +typedef enum
14446 +{
14447 + /* Init host local memory regions.This allows
14448 + * local host access remote memory regions */
14449 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
14450 + /* Init host remote memory regions.This allows
14451 + * remote device access local memory regions */
14452 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
14453 + /* Init local interrupt config*/
14454 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
14455 + /* Init remote interrupt config*/
14456 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
14457 + /* Check link during initialization*/
14458 + VLYNQ_INIT_CHECK_LINK =0x10,
14459 + /* configure clock during init */
14460 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
14461 + /* Clear errors during init */
14462 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
14463 + /* All options */
14464 + VLYNQ_INIT_PERFORM_ALL =0x7F
14465 +}VLYNQ_INIT_OPTIONS;
14466 +
14467 +
14468 +/* VLYNQ_DEV_TYPE identifies local or remote device */
14469 +typedef enum
14470 +{
14471 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
14472 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
14473 +}VLYNQ_DEV_TYPE;
14474 +
14475 +
14476 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
14477 +typedef enum
14478 +{
14479 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
14480 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
14481 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
14482 +}VLYNQ_CLK_SOURCE;
14483 +
14484 +
14485 +/* VLYNQ_DRV_STATE indicates the current driver state */
14486 +typedef enum
14487 +{
14488 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
14489 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
14490 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
14491 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
14492 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
14493 +}VLYNQ_DRV_STATE;
14494 +
14495 +
14496 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
14497 +typedef enum
14498 +{
14499 + VLYNQ_BUS_WIDTH_3 = 3,
14500 + VLYNQ_BUS_WIDTH_5 = 5,
14501 + VLYNQ_BUS_WIDTH_7 = 7,
14502 + VLYNQ_BUS_WIDTH_9 = 9
14503 +}VLYNQ_BUS_WIDTH;
14504 +
14505 +
14506 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
14507 + * interrupts are processed by the host or passed on to the
14508 + * remote device.
14509 + */
14510 +typedef enum
14511 +{
14512 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
14513 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
14514 +}VLYNQ_LOCAL_INT_CONFIG;
14515 +
14516 +
14517 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
14518 + * interrupts are to be handled by the SOC system ISR
14519 + * or via the vlynq root ISR
14520 + */
14521 +typedef enum
14522 +{
14523 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
14524 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
14525 +}VLYNQ_REMOTE_INT_CONFIG;
14526 +
14527 +
14528 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
14529 +typedef enum
14530 +{
14531 + VLYNQ_INTR_ACTIVE_HIGH = 0,
14532 + VLYNQ_INTR_ACTIVE_LOW = 1
14533 +}VLYNQ_INTR_POLARITY;
14534 +
14535 +
14536 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
14537 +typedef enum
14538 +{
14539 + VLYNQ_INTR_LEVEL = 0,
14540 + VLYNQ_INTR_PULSED = 1
14541 +}VLYNQ_INTR_TYPE;
14542 +
14543 +
14544 +/* VLYNQ_RESET_MODE - vlynq reset mode */
14545 +typedef enum
14546 +{
14547 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
14548 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
14549 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
14550 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
14551 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
14552 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
14553 +}VLYNQ_RESET_MODE;
14554 +
14555 +
14556 +
14557 +/*************************************
14558 + * Typedefs *
14559 + *************************************/
14560 +
14561 +struct VLYNQ_DEV_t; /*forward declaration*/
14562 +
14563 +/*--------Function Pointers defintions -----------*/
14564 +
14565 +/* prototype for interrupt handler definition */
14566 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
14567 +
14568 +typedef void
14569 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
14570 +
14571 +typedef void
14572 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
14573 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
14574 + unsigned int dwStatRegVal); /* Value of the relevant status register */
14575 +
14576 +
14577 +/*-------Structure Definitions------------*/
14578 +
14579 +typedef struct VLYNQ_MEMORY_MAP_t
14580 +{
14581 + unsigned int Txmap;
14582 + unsigned int RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
14583 + unsigned int RxSize[VLYNQ_MAX_MEMORY_REGIONS];
14584 +}VLYNQ_MEMORY_MAP;
14585 +
14586 +
14587 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
14588 + * settings in vlynq Control register */
14589 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
14590 +{
14591 + /* vlynq interrupts handled by host or remote - maps to
14592 + * intLocal bit in vlynq control register */
14593 + VLYNQ_LOCAL_INT_CONFIG intLocal;
14594 +
14595 + /* remote interrupts handled by vlynq isr or host system
14596 + * interrupt controller - maps to the int2Cfg in vlynq
14597 + * control register */
14598 + VLYNQ_REMOTE_INT_CONFIG intRemote;
14599 +
14600 + /* bit in pending/set register used for module interrupts*/
14601 + unsigned int map_vector;
14602 +
14603 + /* used only if remote interrupts are to be handled by system ISR*/
14604 + unsigned int intr_ptr;
14605 +
14606 +}VLYNQ_INTERRUPT_CNTRL;
14607 +
14608 +
14609 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
14610 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
14611 + * table to identify the ISR to be invoked
14612 + */
14613 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
14614 +{
14615 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
14616 + void *arg1 ; /* Arg 1 for the ISR */
14617 + void *arg2 ; /* Arg 2 for the ISR */
14618 + void *arg3 ; /* Arg 3 for the ISR */
14619 + unsigned int isrCount; /* number of ISR invocations so far */
14620 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
14621 +}VLYNQ_INTR_CNTRL_ICB;
14622 +
14623 +/* overlay of vlynq register set */
14624 +typedef struct VLYNQ_REG_SET_t
14625 +{
14626 + unsigned int revision; /*offset : 0x00 */
14627 + unsigned int control; /* 0x04*/
14628 + unsigned int status; /* 0x08*/
14629 + unsigned int pad1; /* 0x0c*/
14630 + unsigned int intStatus; /*0x10*/
14631 + unsigned int intPending; /*0x14*/
14632 + unsigned int intPtr; /*0x18*/
14633 + unsigned int txMap; /*0x1C*/
14634 + unsigned int rxSize1; /*0x20*/
14635 + unsigned int rxOffset1; /*0x24*/
14636 + unsigned int rxSize2; /*0x28*/
14637 + unsigned int rxOffset2; /*0x2C*/
14638 + unsigned int rxSize3; /*0x30*/
14639 + unsigned int rxOffset3; /*0x34*/
14640 + unsigned int rxSize4; /*0x38*/
14641 + unsigned int rxOffset4; /*0x3C*/
14642 + unsigned int chipVersion; /*0x40*/
14643 + unsigned int pad2[8];
14644 + unsigned int ivr30; /*0x60*/
14645 + unsigned int ivr74; /*0x64*/
14646 + unsigned int pad3[7];
14647 +}VLYNQ_REG_SET;
14648 +
14649 +
14650 +typedef struct VLYNQ_DEV_t
14651 +{
14652 + /** module index:1,2,3... used for debugging purposes */
14653 + unsigned int dev_idx;
14654 +
14655 + /*VLYNQ module base address */
14656 + unsigned int module_base;
14657 +
14658 + /* clock source selection */
14659 + VLYNQ_CLK_SOURCE clk_source;
14660 +
14661 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
14662 + unsigned int clk_div;
14663 +
14664 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
14665 + VLYNQ_DRV_STATE state;
14666 +
14667 + /* Valid VLYNQ bus width, filled by driver */
14668 + VLYNQ_BUS_WIDTH width;
14669 +
14670 + /* local memory mapping */
14671 + VLYNQ_MEMORY_MAP local_mem;
14672 +
14673 + /* remote memory mapping */
14674 + VLYNQ_MEMORY_MAP remote_mem;
14675 +
14676 + /* Local module interrupt params */
14677 + VLYNQ_INTERRUPT_CNTRL local_irq;
14678 +
14679 + /* remote module interrupt params */
14680 + VLYNQ_INTERRUPT_CNTRL remote_irq;
14681 +
14682 + /*** ICB related fields **/
14683 +
14684 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
14685 + * expansion slots for shared interrupts*/
14686 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
14687 + VLYNQ_INTR_CNTRL_ICB *freelist;
14688 +
14689 + /* table holding mapping between intVector and the bit position the interrupt
14690 + * is mapped to(mapVector)*/
14691 + char vector_map[32];
14692 +
14693 + /* user callback for vlynq events, NULL if unused */
14694 + VLYNQ_REPORT_CB report_cb;
14695 +
14696 + /* user callback for resetting/realeasing remote device */
14697 + VLYNQ_RESET_REMOTE reset_cb;
14698 +
14699 + /*** Handles provided for direct access to register set if need be
14700 + * Must be intialized to point to appropriate address during
14701 + * vlynq_init */
14702 + volatile VLYNQ_REG_SET * local;
14703 + volatile VLYNQ_REG_SET * remote;
14704 +
14705 + unsigned int intCount; /* number of interrupts generated so far */
14706 + unsigned int isrCount; /* number of ISR invocations so far */
14707 +}VLYNQ_DEV;
14708 +
14709 +
14710 +typedef struct VLYNQ_ISR_ARGS_t
14711 +{
14712 + int irq;
14713 + void * arg;
14714 + void * regset;
14715 +}VLYNQ_ISR_ARGS;
14716 +
14717 +
14718 +/****************************************
14719 + * Function Prototypes *
14720 + * API exported by generic vlynq driver *
14721 + ****************************************/
14722 +/* Initialization function */
14723 +int vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
14724 +
14725 +/* Check vlynq link */
14726 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev);
14727 +
14728 +/* Set interrupt vector in local or remote device */
14729 +int vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
14730 + unsigned int int_vector,
14731 + unsigned int map_vector,
14732 + VLYNQ_DEV_TYPE dev,
14733 + VLYNQ_INTR_POLARITY pol,
14734 + VLYNQ_INTR_TYPE type);
14735 +
14736 +
14737 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
14738 + unsigned int int_vector,
14739 + VLYNQ_DEV_TYPE dev,
14740 + unsigned int enable);
14741 +
14742 +unsigned int vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
14743 + unsigned int map_vector);
14744 +
14745 +int vlynq_install_isr( VLYNQ_DEV *pdev,
14746 + unsigned int map_vector,
14747 + VLYNQ_INTR_CNTRL_ISR isr,
14748 + void *arg1, void *arg2, void *arg3);
14749 +
14750 +int vlynq_uninstall_isr( VLYNQ_DEV *pdev,
14751 + unsigned int map_vector,
14752 + void *arg1, void *arg2, void *arg3);
14753 +
14754 +
14755 +void vlynq_root_isr(void *arg);
14756 +
14757 +void vlynq_delay(unsigned int clktime);
14758 +
14759 +/* The following functions, provide better granularity in setting
14760 + * interrupt parameters. (for better support of linux INT Controller)
14761 + * Note: The interrupt source is identified by "map_vector"- the bit
14762 + * position in interrupt status register*/
14763 +
14764 +int vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
14765 + VLYNQ_DEV_TYPE dev,
14766 + unsigned int int_vector,
14767 + unsigned int map_vector);
14768 +
14769 +int vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
14770 + VLYNQ_DEV_TYPE dev,
14771 + unsigned int map_vector,
14772 + VLYNQ_INTR_POLARITY pol);
14773 +
14774 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
14775 + VLYNQ_DEV_TYPE dev_type,
14776 + unsigned int map_vector);
14777 +
14778 +int vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
14779 + VLYNQ_DEV_TYPE dev,
14780 + unsigned int map_vector,
14781 + VLYNQ_INTR_TYPE type);
14782 +
14783 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
14784 + VLYNQ_DEV_TYPE dev_type,
14785 + unsigned int map_vector);
14786 +
14787 +int vlynq_interrupt_enable(VLYNQ_DEV* pdev,
14788 + VLYNQ_DEV_TYPE dev,
14789 + unsigned int map_vector);
14790 +
14791 +int vlynq_interrupt_disable(VLYNQ_DEV * pdev,
14792 + VLYNQ_DEV_TYPE dev,
14793 + unsigned int map_vector);
14794 +
14795 +
14796 +
14797 +
14798 +
14799 +#endif /* _VLYNQ_HAL_H_ */
14800 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal.h linux.dev/include/asm-mips/ar7/vlynq_hal.h
14801 --- linux.old/include/asm-mips/ar7/vlynq_hal.h 1970-01-01 01:00:00.000000000 +0100
14802 +++ linux.dev/include/asm-mips/ar7/vlynq_hal.h 2005-11-10 01:10:46.095590250 +0100
14803 @@ -0,0 +1,606 @@
14804 +/***************************************************************************
14805 +**+----------------------------------------------------------------------+**
14806 +**| **** |**
14807 +**| **** |**
14808 +**| ******o*** |**
14809 +**| ********_///_**** |**
14810 +**| ***** /_//_/ **** |**
14811 +**| ** ** (__/ **** |**
14812 +**| ********* |**
14813 +**| **** |**
14814 +**| *** |**
14815 +**| |**
14816 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
14817 +**| ALL RIGHTS RESERVED |**
14818 +**| |**
14819 +**| Permission is hereby granted to licensees of Texas Instruments |**
14820 +**| Incorporated (TI) products to use this computer program for the sole |**
14821 +**| purpose of implementing a licensee product based on TI products. |**
14822 +**| No other rights to reproduce, use, or disseminate this computer |**
14823 +**| program, whether in part or in whole, are granted. |**
14824 +**| |**
14825 +**| TI makes no representation or warranties with respect to the |**
14826 +**| performance of this computer program, and specifically disclaims |**
14827 +**| any responsibility for any damages, special or consequential, |**
14828 +**| connected with the use of this program. |**
14829 +**| |**
14830 +**+----------------------------------------------------------------------+**
14831 +***************************************************************************/
14832 +
14833 +/*********************************************************************************
14834 + * ------------------------------------------------------------------------------
14835 + * Module : vlynq_hal.h
14836 + * Description :
14837 + * This header file provides the set of functions exported by the
14838 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
14839 + * ------------------------------------------------------------------------------
14840 + *********************************************************************************/
14841 +
14842 +#ifndef _VLYNQ_HAL_H_
14843 +#define _VLYNQ_HAL_H_
14844 +
14845 +#include <asm/ar7/avalanche_types.h>
14846 +#include <asm/ar7/vlynq_hal_params.h>
14847 +
14848 +#ifndef PRIVATE
14849 +#define PRIVATE static
14850 +#endif
14851 +
14852 +#ifndef GLOBAL
14853 +#define GLOBAL
14854 +#endif
14855 +
14856 +/* Enable/Disable debug feature */
14857 +#undef VLYNQ_DEBUG
14858 +
14859 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
14860 +#define debugPrint(format,args...)
14861 +#else
14862 +#define debugPrint(format,args...)
14863 +#endif
14864 +
14865 +/* Error defines */
14866 +#define VLYNQ_SUCCESS 0
14867 +
14868 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
14869 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
14870 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
14871 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
14872 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
14873 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
14874 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
14875 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
14876 +
14877 +/* Vlynq Defines and Macros */
14878 +
14879 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
14880 +
14881 +/* Base address of module */
14882 +#define VLYNQ_BASE (pdev->module_base)
14883 +
14884 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
14885 +
14886 +#define VLYNQ_REV_OFFSET 0x0000
14887 +#define VLYNQ_CTRL_OFFSET 0x0004
14888 +#define VLYNQ_STATUS_OFFSET 0x0008
14889 +#define VLYNQ_INT_STAT_OFFSET 0x0010
14890 +#define VLYNQ_INT_PEND_OFFSET 0x0014
14891 +#define VLYNQ_INT_PTR_OFFSET 0x0018
14892 +#define VLYNQ_TXMAP_OFFSET 0x001c
14893 +
14894 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
14895 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
14896 +
14897 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
14898 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
14899 +
14900 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
14901 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
14902 +
14903 +#define VLYNQ_REV_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
14904 +#define VLYNQ_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
14905 +#define VLYNQ_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
14906 +#define VLYNQ_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
14907 +#define VLYNQ_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
14908 +#define VLYNQ_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
14909 +#define VLYNQ_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
14910 +
14911 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14912 +#define VLYNQ_RXMAP_SIZE_REG(map) \
14913 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
14914 +
14915 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14916 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
14917 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
14918 +
14919 +#define VLYNQ_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
14920 +
14921 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
14922 +#define VLYNQ_IVR_OFFSET(ivr) \
14923 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
14924 +
14925 +#define VLYNQ_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(0)) )
14926 +#define VLYNQ_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(4)) )
14927 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14928 +
14929 +#define VLYNQ_IVR_INTEN(ivr) (((UINT32)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
14930 +#define VLYNQ_IVR_INTTYPE(ivr) (((UINT32)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
14931 +#define VLYNQ_IVR_INTPOL(ivr) (((UINT32)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
14932 +#define VLYNQ_IVR_INTVEC(ivr) (((UINT32)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
14933 +#define VLYNQ_IVR_INTALL(ivr) (((UINT32)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
14934 +
14935 +
14936 +
14937 +/*********************************
14938 + * Remote VLYNQ register set *
14939 + *********************************/
14940 +
14941 +#define VLYNQ_R_REV_OFFSET 0x0080
14942 +#define VLYNQ_R_CTRL_OFFSET 0x0084
14943 +#define VLYNQ_R_STATUS_OFFSET 0x0088
14944 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
14945 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
14946 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
14947 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
14948 +
14949 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
14950 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
14951 +
14952 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
14953 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
14954 +
14955 +#define VLYNQ_R_REV_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
14956 +#define VLYNQ_R_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
14957 +#define VLYNQ_R_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
14958 +#define VLYNQ_R_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
14959 +#define VLYNQ_R_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
14960 +#define VLYNQ_R_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
14961 +#define VLYNQ_R_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
14962 +
14963 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14964 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
14965 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
14966 +
14967 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14968 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
14969 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
14970 +
14971 +#define VLYNQ_R_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
14972 +
14973 +#define VLYNQ_R_IVR_OFFSET(ivr) \
14974 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
14975 +
14976 +
14977 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14978 +#define VLYNQ_R_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(0)) )
14979 +#define VLYNQ_R_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(4)) )
14980 +
14981 +
14982 +/****End of remote register set definition******/
14983 +
14984 +
14985 +/*** Masks for individual register fields ***/
14986 +
14987 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
14988 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
14989 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
14990 +
14991 +
14992 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
14993 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
14994 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
14995 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
14996 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
14997 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
14998 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
14999 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
15000 +
15001 +
15002 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
15003 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
15004 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
15005 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
15006 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
15007 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
15008 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
15009 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
15010 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
15011 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
15012 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
15013 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
15014 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
15015 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
15016 +
15017 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
15018 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
15019 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
15020 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
15021 +
15022 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
15023 +
15024 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
15025 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
15026 +
15027 +#define VLYNQ_IVR_INTEN_MASK 0x80
15028 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
15029 +#define VLYNQ_IVR_INTPOL_MASK 0x20
15030 +
15031 +
15032 +/**** Helper macros ****/
15033 +
15034 +#define VLYNQ_RESETCB(arg) \
15035 + if( pdev->reset_cb != NULL) \
15036 + { \
15037 + (pdev->reset_cb)(pdev, (arg)); \
15038 + }
15039 +
15040 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
15041 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
15042 +
15043 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
15044 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
15045 +
15046 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
15047 +
15048 +
15049 +/*************************************
15050 + * Enums *
15051 + *************************************/
15052 +
15053 +/* Initialization options define what operations are
15054 + * undertaken during vlynq module initialization */
15055 +typedef enum
15056 +{
15057 + /* Init host local memory regions.This allows
15058 + * local host access remote memory regions */
15059 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
15060 + /* Init host remote memory regions.This allows
15061 + * remote device access local memory regions */
15062 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
15063 + /* Init local interrupt config*/
15064 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
15065 + /* Init remote interrupt config*/
15066 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
15067 + /* Check link during initialization*/
15068 + VLYNQ_INIT_CHECK_LINK =0x10,
15069 + /* configure clock during init */
15070 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
15071 + /* Clear errors during init */
15072 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
15073 + /* All options */
15074 + VLYNQ_INIT_PERFORM_ALL =0x7F
15075 +}VLYNQ_INIT_OPTIONS;
15076 +
15077 +
15078 +/* VLYNQ_DEV_TYPE identifies local or remote device */
15079 +typedef enum
15080 +{
15081 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
15082 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
15083 +}VLYNQ_DEV_TYPE;
15084 +
15085 +
15086 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
15087 +typedef enum
15088 +{
15089 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
15090 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
15091 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
15092 +}VLYNQ_CLK_SOURCE;
15093 +
15094 +
15095 +/* VLYNQ_DRV_STATE indicates the current driver state */
15096 +typedef enum
15097 +{
15098 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
15099 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
15100 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
15101 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
15102 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
15103 +}VLYNQ_DRV_STATE;
15104 +
15105 +
15106 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
15107 +typedef enum
15108 +{
15109 + VLYNQ_BUS_WIDTH_3 = 3,
15110 + VLYNQ_BUS_WIDTH_5 = 5,
15111 + VLYNQ_BUS_WIDTH_7 = 7,
15112 + VLYNQ_BUS_WIDTH_9 = 9
15113 +}VLYNQ_BUS_WIDTH;
15114 +
15115 +
15116 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
15117 + * interrupts are processed by the host or passed on to the
15118 + * remote device.
15119 + */
15120 +typedef enum
15121 +{
15122 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
15123 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
15124 +}VLYNQ_LOCAL_INT_CONFIG;
15125 +
15126 +
15127 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
15128 + * interrupts are to be handled by the SOC system ISR
15129 + * or via the vlynq root ISR
15130 + */
15131 +typedef enum
15132 +{
15133 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
15134 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
15135 +}VLYNQ_REMOTE_INT_CONFIG;
15136 +
15137 +
15138 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
15139 +typedef enum
15140 +{
15141 + VLYNQ_INTR_ACTIVE_HIGH = 0,
15142 + VLYNQ_INTR_ACTIVE_LOW = 1
15143 +}VLYNQ_INTR_POLARITY;
15144 +
15145 +
15146 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
15147 +typedef enum
15148 +{
15149 + VLYNQ_INTR_LEVEL = 0,
15150 + VLYNQ_INTR_PULSED = 1
15151 +}VLYNQ_INTR_TYPE;
15152 +
15153 +
15154 +/* VLYNQ_RESET_MODE - vlynq reset mode */
15155 +typedef enum
15156 +{
15157 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
15158 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
15159 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
15160 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
15161 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
15162 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
15163 +}VLYNQ_RESET_MODE;
15164 +
15165 +
15166 +
15167 +/*************************************
15168 + * Typedefs *
15169 + *************************************/
15170 +
15171 +struct VLYNQ_DEV_t; /*forward declaration*/
15172 +
15173 +/*--------Function Pointers defintions -----------*/
15174 +
15175 +/* prototype for interrupt handler definition */
15176 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
15177 +
15178 +typedef void
15179 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
15180 +
15181 +typedef void
15182 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
15183 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
15184 + UINT32 dwStatRegVal); /* Value of the relevant status register */
15185 +
15186 +
15187 +/*-------Structure Definitions------------*/
15188 +
15189 +typedef struct VLYNQ_MEMORY_MAP_t
15190 +{
15191 + UINT32 Txmap;
15192 + UINT32 RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
15193 + UINT32 RxSize[VLYNQ_MAX_MEMORY_REGIONS];
15194 +}VLYNQ_MEMORY_MAP;
15195 +
15196 +
15197 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
15198 + * settings in vlynq Control register */
15199 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
15200 +{
15201 + /* vlynq interrupts handled by host or remote - maps to
15202 + * intLocal bit in vlynq control register */
15203 + VLYNQ_LOCAL_INT_CONFIG intLocal;
15204 +
15205 + /* remote interrupts handled by vlynq isr or host system
15206 + * interrupt controller - maps to the int2Cfg in vlynq
15207 + * control register */
15208 + VLYNQ_REMOTE_INT_CONFIG intRemote;
15209 +
15210 + /* bit in pending/set register used for module interrupts*/
15211 + UINT32 map_vector;
15212 +
15213 + /* used only if remote interrupts are to be handled by system ISR*/
15214 + UINT32 intr_ptr;
15215 +
15216 +}VLYNQ_INTERRUPT_CNTRL;
15217 +
15218 +
15219 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
15220 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
15221 + * table to identify the ISR to be invoked
15222 + */
15223 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
15224 +{
15225 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
15226 + void *arg1 ; /* Arg 1 for the ISR */
15227 + void *arg2 ; /* Arg 2 for the ISR */
15228 + void *arg3 ; /* Arg 3 for the ISR */
15229 + UINT32 isrCount; /* number of ISR invocations so far */
15230 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
15231 +}VLYNQ_INTR_CNTRL_ICB;
15232 +
15233 +/* overlay of vlynq register set */
15234 +typedef struct VLYNQ_REG_SET_t
15235 +{
15236 + UINT32 revision; /*offset : 0x00 */
15237 + UINT32 control; /* 0x04*/
15238 + UINT32 status; /* 0x08*/
15239 + UINT32 pad1; /* 0x0c*/
15240 + UINT32 intStatus; /*0x10*/
15241 + UINT32 intPending; /*0x14*/
15242 + UINT32 intPtr; /*0x18*/
15243 + UINT32 txMap; /*0x1C*/
15244 + UINT32 rxSize1; /*0x20*/
15245 + UINT32 rxOffset1; /*0x24*/
15246 + UINT32 rxSize2; /*0x28*/
15247 + UINT32 rxOffset2; /*0x2C*/
15248 + UINT32 rxSize3; /*0x30*/
15249 + UINT32 rxOffset3; /*0x34*/
15250 + UINT32 rxSize4; /*0x38*/
15251 + UINT32 rxOffset4; /*0x3C*/
15252 + UINT32 chipVersion; /*0x40*/
15253 + UINT32 pad2[8];
15254 + UINT32 ivr30; /*0x60*/
15255 + UINT32 ivr74; /*0x64*/
15256 + UINT32 pad3[7];
15257 +}VLYNQ_REG_SET;
15258 +
15259 +
15260 +typedef struct VLYNQ_DEV_t
15261 +{
15262 + /** module index:1,2,3... used for debugging purposes */
15263 + UINT32 dev_idx;
15264 +
15265 + /*VLYNQ module base address */
15266 + UINT32 module_base;
15267 +
15268 + /* clock source selection */
15269 + VLYNQ_CLK_SOURCE clk_source;
15270 +
15271 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
15272 + UINT32 clk_div;
15273 +
15274 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
15275 + VLYNQ_DRV_STATE state;
15276 +
15277 + /* Valid VLYNQ bus width, filled by driver */
15278 + VLYNQ_BUS_WIDTH width;
15279 +
15280 + /* local memory mapping */
15281 + VLYNQ_MEMORY_MAP local_mem;
15282 +
15283 + /* remote memory mapping */
15284 + VLYNQ_MEMORY_MAP remote_mem;
15285 +
15286 + /* Local module interrupt params */
15287 + VLYNQ_INTERRUPT_CNTRL local_irq;
15288 +
15289 + /* remote module interrupt params */
15290 + VLYNQ_INTERRUPT_CNTRL remote_irq;
15291 +
15292 + /*** ICB related fields **/
15293 +
15294 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
15295 + * expansion slots for shared interrupts*/
15296 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
15297 + VLYNQ_INTR_CNTRL_ICB *freelist;
15298 +
15299 + /* table holding mapping between intVector and the bit position the interrupt
15300 + * is mapped to(mapVector)*/
15301 + INT8 vector_map[32];
15302 +
15303 + /* user callback for vlynq events, NULL if unused */
15304 + VLYNQ_REPORT_CB report_cb;
15305 +
15306 + /* user callback for resetting/realeasing remote device */
15307 + VLYNQ_RESET_REMOTE reset_cb;
15308 +
15309 + /*** Handles provided for direct access to register set if need be
15310 + * Must be intialized to point to appropriate address during
15311 + * vlynq_init */
15312 + volatile VLYNQ_REG_SET * local;
15313 + volatile VLYNQ_REG_SET * remote;
15314 +
15315 + UINT32 intCount; /* number of interrupts generated so far */
15316 + UINT32 isrCount; /* number of ISR invocations so far */
15317 +}VLYNQ_DEV;
15318 +
15319 +
15320 +typedef struct VLYNQ_ISR_ARGS_t
15321 +{
15322 + int irq;
15323 + void * arg;
15324 + void * regset;
15325 +}VLYNQ_ISR_ARGS;
15326 +
15327 +
15328 +/****************************************
15329 + * Function Prototypes *
15330 + * API exported by generic vlynq driver *
15331 + ****************************************/
15332 +/* Initialization function */
15333 +GLOBAL INT32 vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
15334 +
15335 +/* Check vlynq link */
15336 +GLOBAL UINT32 vlynq_link_check( VLYNQ_DEV * pdev);
15337 +
15338 +/* Set interrupt vector in local or remote device */
15339 +GLOBAL INT32 vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
15340 + UINT32 int_vector,
15341 + UINT32 map_vector,
15342 + VLYNQ_DEV_TYPE dev,
15343 + VLYNQ_INTR_POLARITY pol,
15344 + VLYNQ_INTR_TYPE type);
15345 +
15346 +
15347 +GLOBAL INT32 vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
15348 + UINT32 int_vector,
15349 + VLYNQ_DEV_TYPE dev,
15350 + UINT32 enable);
15351 +
15352 +GLOBAL UINT32 vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
15353 + UINT32 map_vector);
15354 +
15355 +GLOBAL INT32 vlynq_install_isr( VLYNQ_DEV *pdev,
15356 + UINT32 map_vector,
15357 + VLYNQ_INTR_CNTRL_ISR isr,
15358 + void *arg1, void *arg2, void *arg3);
15359 +
15360 +GLOBAL INT32 vlynq_uninstall_isr( VLYNQ_DEV *pdev,
15361 + UINT32 map_vector,
15362 + void *arg1, void *arg2, void *arg3);
15363 +
15364 +
15365 +GLOBAL void vlynq_root_isr(void *arg);
15366 +
15367 +GLOBAL void vlynq_delay(UINT32 clktime);
15368 +
15369 +/* The following functions, provide better granularity in setting
15370 + * interrupt parameters. (for better support of linux INT Controller)
15371 + * Note: The interrupt source is identified by "map_vector"- the bit
15372 + * position in interrupt status register*/
15373 +
15374 +GLOBAL INT32 vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
15375 + VLYNQ_DEV_TYPE dev,
15376 + UINT32 int_vector,
15377 + UINT32 map_vector);
15378 +
15379 +GLOBAL INT32 vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
15380 + VLYNQ_DEV_TYPE dev,
15381 + UINT32 map_vector,
15382 + VLYNQ_INTR_POLARITY pol);
15383 +
15384 +GLOBAL INT32 vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
15385 + VLYNQ_DEV_TYPE dev_type,
15386 + UINT32 map_vector);
15387 +
15388 +GLOBAL INT32 vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
15389 + VLYNQ_DEV_TYPE dev,
15390 + UINT32 map_vector,
15391 + VLYNQ_INTR_TYPE type);
15392 +
15393 +GLOBAL INT32 vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
15394 + VLYNQ_DEV_TYPE dev_type,
15395 + UINT32 map_vector);
15396 +
15397 +GLOBAL INT32 vlynq_interrupt_enable(VLYNQ_DEV* pdev,
15398 + VLYNQ_DEV_TYPE dev,
15399 + UINT32 map_vector);
15400 +
15401 +GLOBAL INT32 vlynq_interrupt_disable(VLYNQ_DEV * pdev,
15402 + VLYNQ_DEV_TYPE dev,
15403 + UINT32 map_vector);
15404 +
15405 +
15406 +
15407 +
15408 +
15409 +#endif /* _VLYNQ_HAL_H_ */
15410 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal_params.h linux.dev/include/asm-mips/ar7/vlynq_hal_params.h
15411 --- linux.old/include/asm-mips/ar7/vlynq_hal_params.h 1970-01-01 01:00:00.000000000 +0100
15412 +++ linux.dev/include/asm-mips/ar7/vlynq_hal_params.h 2005-11-10 01:10:46.095590250 +0100
15413 @@ -0,0 +1,50 @@
15414 +/***************************************************************************
15415 +**+----------------------------------------------------------------------+**
15416 +**| **** |**
15417 +**| **** |**
15418 +**| ******o*** |**
15419 +**| ********_///_**** |**
15420 +**| ***** /_//_/ **** |**
15421 +**| ** ** (__/ **** |**
15422 +**| ********* |**
15423 +**| **** |**
15424 +**| *** |**
15425 +**| |**
15426 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
15427 +**| ALL RIGHTS RESERVED |**
15428 +**| |**
15429 +**| Permission is hereby granted to licensees of Texas Instruments |**
15430 +**| Incorporated (TI) products to use this computer program for the sole |**
15431 +**| purpose of implementing a licensee product based on TI products. |**
15432 +**| No other rights to reproduce, use, or disseminate this computer |**
15433 +**| program, whether in part or in whole, are granted. |**
15434 +**| |**
15435 +**| TI makes no representation or warranties with respect to the |**
15436 +**| performance of this computer program, and specifically disclaims |**
15437 +**| any responsibility for any damages, special or consequential, |**
15438 +**| connected with the use of this program. |**
15439 +**| |**
15440 +**+----------------------------------------------------------------------+**
15441 +***************************************************************************/
15442 +
15443 +/* This file defines Vlynq module parameters*/
15444 +
15445 +#ifndef _VLYNQ_HAL_PARAMS_H
15446 +#define _VLYNQ_HAL_PARAMS_H
15447 +
15448 + /* number of VLYNQ memory regions supported */
15449 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
15450 +
15451 + /* Max.number of external interrupt inputs supported by VLYNQ module */
15452 +#define VLYNQ_IVR_MAXIVR 0x08
15453 +
15454 +#define VLYNQ_CLK_DIV_MAX 0x08
15455 +#define VLYNQ_CLK_DIV_MIN 0x01
15456 +
15457 +
15458 +/*** the total number of entries allocated for ICB would be
15459 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
15460 +#define VLYNQ_IVR_CHAIN_SLOTS 10
15461 +
15462 +
15463 +#endif /* _VLYNQ_HAL_PARAMS_H */
15464 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
15465 --- linux.old/include/asm-mips/io.h 2003-08-25 13:44:43.000000000 +0200
15466 +++ linux.dev/include/asm-mips/io.h 2005-11-10 01:14:16.400733500 +0100
15467 @@ -61,9 +61,9 @@
15468 * Change "struct page" to physical address.
15469 */
15470 #ifdef CONFIG_64BIT_PHYS_ADDR
15471 -#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
15472 +#define page_to_phys(page) (((u64)(page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
15473 #else
15474 -#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
15475 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
15476 #endif
15477
15478 #define IO_SPACE_LIMIT 0xffff
15479 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
15480 --- linux.old/include/asm-mips/irq.h 2003-08-25 13:44:43.000000000 +0200
15481 +++ linux.dev/include/asm-mips/irq.h 2005-11-10 01:12:43.950955750 +0100
15482 @@ -14,7 +14,20 @@
15483 #include <linux/config.h>
15484 #include <linux/linkage.h>
15485
15486 +#ifdef CONFIG_AR7
15487 +/* MIPS has 8 irqs
15488 + * AR7 has 40 primary and 32 secondary irqs
15489 + * vlynq0 has 32 irqs
15490 + * vlynq1 has 32 irqs
15491 + */
15492 +#ifdef CONFIG_AR7_VLYNQ
15493 +#define NR_IRQS (80 + 32 * CONFIG_AR7_VLYNQ_PORTS)
15494 +#else
15495 +#define NR_IRQS 80
15496 +#endif
15497 +#else
15498 #define NR_IRQS 128 /* Largest number of ints of all machines. */
15499 +#endif
15500
15501 #ifdef CONFIG_I8259
15502 static inline int irq_cannonicalize(int irq)
15503 diff -urN linux.old/include/asm-mips/mips-boards/prom.h linux.dev/include/asm-mips/mips-boards/prom.h
15504 --- linux.old/include/asm-mips/mips-boards/prom.h 2001-09-09 19:43:02.000000000 +0200
15505 +++ linux.dev/include/asm-mips/mips-boards/prom.h 2005-11-10 01:14:16.436735750 +0100
15506 @@ -33,7 +33,7 @@
15507 extern void prom_init_cmdline(void);
15508 extern void prom_meminit(void);
15509 extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
15510 -extern void prom_free_prom_memory (void);
15511 +extern unsigned long prom_free_prom_memory (void);
15512 extern void mips_display_message(const char *str);
15513 extern void mips_display_word(unsigned int num);
15514 extern int get_ethernet_addr(char *ethernet_addr);
15515 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
15516 --- linux.old/include/asm-mips/page.h 2004-02-18 14:36:32.000000000 +0100
15517 +++ linux.dev/include/asm-mips/page.h 2005-11-10 01:14:16.436735750 +0100
15518 @@ -12,6 +12,7 @@
15519
15520 #include <linux/config.h>
15521 #include <asm/break.h>
15522 +#include <asm/addrspace.h>
15523
15524 #ifdef __KERNEL__
15525
15526 @@ -129,7 +130,7 @@
15527
15528 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
15529 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
15530 -#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
15531 +#define virt_to_page(kaddr) (mem_map + ((__pa(kaddr)-PHYS_OFFSET) >> PAGE_SHIFT))
15532 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
15533
15534 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
15535 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
15536 --- linux.old/include/asm-mips/pgtable-32.h 2004-02-18 14:36:32.000000000 +0100
15537 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-11-10 01:14:16.436735750 +0100
15538 @@ -108,7 +108,7 @@
15539 * and a page entry and page directory to the page they refer to.
15540 */
15541
15542 -#ifdef CONFIG_CPU_VR41XX
15543 +#if defined(CONFIG_CPU_VR41XX)
15544 #define mk_pte(page, pgprot) \
15545 ({ \
15546 pte_t __pte; \
15547 @@ -123,13 +123,14 @@
15548 ({ \
15549 pte_t __pte; \
15550 \
15551 - pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \
15552 - pgprot_val(pgprot); \
15553 + pte_val(__pte) = (((phys_t)(page - mem_map) << PAGE_SHIFT) + \
15554 + PHYS_OFFSET) | pgprot_val(pgprot); \
15555 \
15556 __pte; \
15557 })
15558 #endif
15559
15560 +
15561 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
15562 {
15563 #ifdef CONFIG_CPU_VR41XX
15564 @@ -175,12 +176,12 @@
15565 set_pte(ptep, __pte(0));
15566 }
15567
15568 -#ifdef CONFIG_CPU_VR41XX
15569 +#if defined(CONFIG_CPU_VR41XX)
15570 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
15571 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
15572 #else
15573 -#define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> PAGE_SHIFT))))
15574 -#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << PAGE_SHIFT) | pgprot_val(pgprot))
15575 +#define pte_page(x) (mem_map+((unsigned long)((((x).pte_low-PHYS_OFFSET) >> PAGE_SHIFT))))
15576 +#define __mk_pte(page_nr,pgprot) __pte((((page_nr) << PAGE_SHIFT)+PHYS_OFFSET)|pgprot_val(pgprot))
15577 #endif
15578
15579 #endif
15580 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
15581 --- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
15582 +++ linux.dev/include/asm-mips/serial.h 2005-11-10 01:14:16.436735750 +0100
15583 @@ -65,6 +65,16 @@
15584
15585 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
15586
15587 +#ifdef CONFIG_AR7
15588 +#include <asm/ar7/ar7.h>
15589 +#include <asm/ar7/avalanche_intc.h>
15590 +#define AR7_SERIAL_PORT_DEFNS \
15591 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
15592 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
15593 +#else
15594 +#define AR7_SERIAL_PORT_DEFNS
15595 +#endif
15596 +
15597 #ifdef CONFIG_MIPS_JAZZ
15598 #define _JAZZ_SERIAL_INIT(int, base) \
15599 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
15600 @@ -468,6 +478,7 @@
15601 #endif
15602
15603 #define SERIAL_PORT_DFNS \
15604 + AR7_SERIAL_PORT_DEFNS \
15605 ATLAS_SERIAL_PORT_DEFNS \
15606 AU1000_SERIAL_PORT_DEFNS \
15607 COBALT_SERIAL_PORT_DEFNS \
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