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Add rt2x00-mac80211 snapshot (#1916)
[openwrt.git] / package / rt2x00 / src / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt61pci"
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/delay.h>
39 #include <linux/etherdevice.h>
40 #include <linux/eeprom_93cx6.h>
41
42 #include <asm/io.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00pci.h"
46 #include "rt61pci.h"
47
48 /*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
59 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
60 {
61 u32 reg;
62 unsigned int i;
63
64 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
65 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
66 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
67 break;
68 udelay(REGISTER_BUSY_DELAY);
69 }
70
71 return reg;
72 }
73
74 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
75 const u8 reg_id, const u8 value)
76 {
77 u32 reg;
78
79 /*
80 * Wait until the BBP becomes ready.
81 */
82 reg = rt61pci_bbp_check(rt2x00dev);
83 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
84 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
85 return;
86 }
87
88 /*
89 * Write the data into the BBP.
90 */
91 reg = 0;
92 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
93 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
94 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
95 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
96
97 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
98 }
99
100 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
101 const u8 reg_id, u8 *value)
102 {
103 u32 reg;
104
105 /*
106 * Wait until the BBP becomes ready.
107 */
108 reg = rt61pci_bbp_check(rt2x00dev);
109 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
110 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
111 return;
112 }
113
114 /*
115 * Write the request into the BBP.
116 */
117 reg =0;
118 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
119 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
120 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
121
122 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
123
124 /*
125 * Wait until the BBP becomes ready.
126 */
127 reg = rt61pci_bbp_check(rt2x00dev);
128 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
129 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
130 *value = 0xff;
131 return;
132 }
133
134 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
135 }
136
137 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
138 const u32 value)
139 {
140 u32 reg;
141 unsigned int i;
142
143 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
144 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
145 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
146 goto rf_write;
147 udelay(REGISTER_BUSY_DELAY);
148 }
149
150 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
151 return;
152
153 rf_write:
154 reg = 0;
155 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
156 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
157 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
158 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
159
160 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
161 }
162
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token, const u8 arg0, const u8 arg1)
165 {
166 u32 reg;
167
168 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
169
170 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
171 ERROR(rt2x00dev, "mcu request error. "
172 "Request 0x%02x failed for token 0x%02x.\n",
173 command, token);
174 return;
175 }
176
177 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
178 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
181 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
182
183 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
184 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
185 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
186 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
187 }
188
189 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
190 {
191 struct rt2x00_dev *rt2x00dev = eeprom->data;
192 u32 reg;
193
194 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
195
196 eeprom->reg_data_in = !!rt2x00_get_field32(reg,
197 E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg,
199 E2PROM_CSR_DATA_OUT);
200 eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
201 E2PROM_CSR_DATA_CLOCK);
202 eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
203 E2PROM_CSR_CHIP_SELECT);
204 }
205
206 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
207 {
208 struct rt2x00_dev *rt2x00dev = eeprom->data;
209 u32 reg = 0;
210
211 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN,
212 !!eeprom->reg_data_in);
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT,
214 !!eeprom->reg_data_out);
215 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216 !!eeprom->reg_data_clock);
217 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218 !!eeprom->reg_chip_select);
219
220 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221 }
222
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
227 const unsigned long word, void *data)
228 {
229 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230 }
231
232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
233 const unsigned long word, void *data)
234 {
235 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
236 }
237
238 static void rt61pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
239 const unsigned long word, void *data)
240 {
241 rt2x00_eeprom_read(rt2x00dev, word, data);
242 }
243
244 static void rt61pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
245 const unsigned long word, void *data)
246 {
247 rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
248 }
249
250 static void rt61pci_read_bbp(struct rt2x00_dev *rt2x00dev,
251 const unsigned long word, void *data)
252 {
253 rt61pci_bbp_read(rt2x00dev, word, data);
254 }
255
256 static void rt61pci_write_bbp(struct rt2x00_dev *rt2x00dev,
257 const unsigned long word, void *data)
258 {
259 rt61pci_bbp_write(rt2x00dev, word, *((u8*)data));
260 }
261
262 static const struct rt2x00debug rt61pci_rt2x00debug = {
263 .owner = THIS_MODULE,
264 .reg_csr = {
265 .read = rt61pci_read_csr,
266 .write = rt61pci_write_csr,
267 .word_size = sizeof(u32),
268 .word_count = CSR_REG_SIZE / sizeof(u32),
269 },
270 .reg_eeprom = {
271 .read = rt61pci_read_eeprom,
272 .write = rt61pci_write_eeprom,
273 .word_size = sizeof(u16),
274 .word_count = EEPROM_SIZE / sizeof(u16),
275 },
276 .reg_bbp = {
277 .read = rt61pci_read_bbp,
278 .write = rt61pci_write_bbp,
279 .word_size = sizeof(u8),
280 .word_count = BBP_SIZE / sizeof(u8),
281 },
282 };
283 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
284
285 #ifdef CONFIG_RT61PCI_RFKILL
286 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
287 {
288 u32 reg;
289
290 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
291 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
292 }
293 #endif /* CONFIG_RT2400PCI_RFKILL */
294
295 /*
296 * Configuration handlers.
297 */
298 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
299 {
300 u32 reg[2];
301
302 memset(&reg, 0, sizeof(reg));
303 memcpy(&reg, bssid, ETH_ALEN);
304
305 rt2x00_set_field32(&reg[1], MAC_CSR5_BSS_ID_MASK, 3);
306
307 /*
308 * The BSSID is passed to us as an array of bytes,
309 * that array is little endian, so no need for byte ordering.
310 */
311 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, &reg, sizeof(reg));
312 }
313
314 static void rt61pci_config_promisc(struct rt2x00_dev *rt2x00dev,
315 const int promisc)
316 {
317 u32 reg;
318
319 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
320 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, !promisc);
321 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
322 }
323
324 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev,
325 const int type)
326 {
327 u32 reg;
328
329 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
330
331 /*
332 * Apply hardware packet filter.
333 */
334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
335
336 if (!is_monitor_present(&rt2x00dev->interface) &&
337 (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
338 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 1);
339 else
340 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 0);
341
342 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 1);
343 if (is_monitor_present(&rt2x00dev->interface)) {
344 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 0);
345 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 0);
346 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 0);
347 } else {
348 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 1);
349 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 1);
350 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
351 }
352
353 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, 0);
354 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
355
356 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
357
358 /*
359 * Enable synchronisation.
360 */
361 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
362 if (is_interface_present(&rt2x00dev->interface)) {
363 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
364 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
365 }
366
367 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
368 if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
369 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 2);
370 else if (type == IEEE80211_IF_TYPE_STA)
371 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 1);
372 else if (is_monitor_present(&rt2x00dev->interface) &&
373 !is_interface_present(&rt2x00dev->interface))
374 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
375
376 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
377 }
378
379 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
380 const int value, const int channel, const int txpower)
381 {
382 u8 reg = 0;
383 u32 rf1 = 0;
384 u32 rf2 = value;
385 u32 rf3 = 0;
386 u32 rf4 = 0;
387
388 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags) || channel <= 14)
389 rf1 = 0x00002ccc;
390 else if (channel == 36 ||
391 (channel >= 100 && channel <= 116) ||
392 channel >= 157)
393 rf1 = 0x00002cd4;
394 else
395 rf1 = 0x00002cd0;
396
397 if (channel <= 14) {
398 rf3 = 0x00068455;
399 } else if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
400 if (channel >= 36 && channel <= 48)
401 rf3 = 0x0009be55;
402 else if (channel >= 52 && channel <= 64)
403 rf3 = 0x0009ae55;
404 else if (channel >= 100 && channel <= 112)
405 rf3 = 0x000bae55;
406 else
407 rf3 = 0x000bbe55;
408 } else {
409 switch (channel) {
410 case 36:
411 case 40:
412 case 44:
413 rf3 = 0x00098455;
414 break;
415 case 48:
416 rf3 = 0x00098655;
417 break;
418 case 52:
419 rf3 = 0x00098855;
420 break;
421 case 56:
422 rf3 = 0x00098c55;
423
424 case 60:
425 rf3 = 0x00098e55;
426 break;
427 case 64:
428 rf3 = 0x00099255;
429 break;
430 case 100:
431 case 104:
432 case 108:
433 rf3 = 0x000b9855;
434 break;
435 case 112:
436 case 116:
437 case 120:
438 case 124:
439 rf3 = 0x000b9a55;
440 break;
441 case 128:
442 case 132:
443 rf3 = 0x000b9c55;
444 break;
445 case 136:
446 case 140:
447 rf3 = 0x000b9e55;
448 break;
449 case 149:
450 case 153:
451 case 157:
452 case 161:
453 case 165:
454 rf3 = 0x000ba255;
455 break;
456 }
457 }
458
459 if (channel < 14) {
460 if (channel & 1)
461 rf4 = 0x000ffa0b;
462 else
463 rf4 = 0x000ffa1f;
464 } else if (channel == 14) {
465 rf4 = 0x000ffa13;
466 } else if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
467 switch (channel) {
468 case 36:
469 case 56:
470 case 116:
471 case 136:
472 rf4 = 0x000ffa23;
473 break;
474 case 40:
475 case 60:
476 case 100:
477 case 120:
478 case 140:
479 rf4 = 0x000ffa03;
480 break;
481 case 44:
482 case 64:
483 case 104:
484 case 124:
485 rf4 = 0x000ffa0b;
486 break;
487 case 48:
488 case 108:
489 case 128:
490 rf4 = 0x000ffa13;
491 break;
492 case 52:
493 case 112:
494 case 132:
495 rf4 = 0x000ffa1b;
496 break;
497 case 149:
498 rf4 = 0x000ffa1f;
499 break;
500 case 153:
501 rf4 = 0x000ffa27;
502 break;
503 case 157:
504 rf4 = 0x000ffa07;
505 break;
506 case 161:
507 rf4 = 0x000ffa0f;
508 break;
509 case 165:
510 rf4 = 0x000ffa17;
511 break;
512 }
513 } else {
514 switch (channel) {
515 case 36:
516 case 40:
517 case 60:
518 case 140:
519 case 100:
520 case 104:
521 case 108:
522 case 112:
523 case 116:
524 case 120:
525 rf4 = 0x000c0a03;
526 break;
527 case 44:
528 case 64:
529 case 124:
530 case 149:
531 rf4 = 0x000c0a1b;
532 break;
533 case 48:
534 case 128:
535 case 153:
536 rf4 = 0x000c0a0b;
537 break;
538 case 52:
539 case 132:
540 rf4 = 0x000c0a23;
541 break;
542 case 56:
543 case 136:
544 rf4 = 0x000c0a13;
545 break;
546 case 157:
547 case 161:
548 case 165:
549 rf4 = 0x000c0a17;
550 break;
551 }
552 }
553
554 /*
555 * Set TXpower.
556 */
557 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
558
559 /*
560 * Set Frequency offset.
561 */
562 rt2x00_set_field32(&rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
563
564 rt61pci_rf_write(rt2x00dev, rf1);
565 rt61pci_rf_write(rt2x00dev, rf2);
566 rt61pci_rf_write(rt2x00dev, rf3 & ~0x00000004);
567 rt61pci_rf_write(rt2x00dev, rf4);
568
569 udelay(200);
570
571 rt61pci_rf_write(rt2x00dev, rf1);
572 rt61pci_rf_write(rt2x00dev, rf2);
573 rt61pci_rf_write(rt2x00dev, rf3 | 0x00000004);
574 rt61pci_rf_write(rt2x00dev, rf4);
575
576 udelay(200);
577
578 rt61pci_rf_write(rt2x00dev, rf1);
579 rt61pci_rf_write(rt2x00dev, rf2);
580 rt61pci_rf_write(rt2x00dev, rf3 & ~0x00000004);
581 rt61pci_rf_write(rt2x00dev, rf4);
582
583 rt61pci_bbp_read(rt2x00dev, 3, &reg);
584 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
585 rt2x00_rf(&rt2x00dev->chip, RF2527))
586 reg &= ~0x01;
587 else
588 reg |= 0x01;
589 rt61pci_bbp_write(rt2x00dev, 3, reg);
590
591 msleep(1);
592
593 /*
594 * Update rf fields
595 */
596 rt2x00dev->rf1 = rf1;
597 rt2x00dev->rf2 = rf2;
598 rt2x00dev->rf3 = rf3;
599 rt2x00dev->rf4 = rf4;
600 rt2x00dev->tx_power = txpower;
601 }
602
603 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
604 const int txpower)
605 {
606 rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
607 TXPOWER_TO_DEV(txpower));
608
609 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
610 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
611 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
612 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
613
614 udelay(200);
615
616 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
617 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
618 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 | 0x00000004);
619 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
620
621 udelay(200);
622
623 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf1);
624 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf2);
625 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
626 rt61pci_rf_write(rt2x00dev, rt2x00dev->rf4);
627 }
628
629 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
630 const int antenna_tx, const int antenna_rx)
631 {
632 u32 reg;
633 u8 r3;
634 u8 r4;
635 u8 r77;
636
637 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
638
639 if (rt2x00dev->curr_hwmode == HWMODE_A) {
640 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
641 rt61pci_bbp_write(rt2x00dev, 17, 0x38);
642 rt61pci_bbp_write(rt2x00dev, 96, 0x78);
643 rt61pci_bbp_write(rt2x00dev, 104, 0x48);
644 rt61pci_bbp_write(rt2x00dev, 75, 0x80);
645 rt61pci_bbp_write(rt2x00dev, 86, 0x80);
646 rt61pci_bbp_write(rt2x00dev, 88, 0x80);
647 } else {
648 rt61pci_bbp_write(rt2x00dev, 17, 0x28);
649 rt61pci_bbp_write(rt2x00dev, 96, 0x58);
650 rt61pci_bbp_write(rt2x00dev, 104, 0x38);
651 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
652 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
653 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
654 }
655 rt61pci_bbp_write(rt2x00dev, 35, 0x60);
656 rt61pci_bbp_write(rt2x00dev, 97, 0x58);
657 rt61pci_bbp_write(rt2x00dev, 98, 0x58);
658
659 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
660 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
661 } else {
662 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
663 rt61pci_bbp_write(rt2x00dev, 17, 0x30);
664 rt61pci_bbp_write(rt2x00dev, 96, 0x68);
665 rt61pci_bbp_write(rt2x00dev, 104, 0x3c);
666 rt61pci_bbp_write(rt2x00dev, 75, 0x80);
667 rt61pci_bbp_write(rt2x00dev, 86, 0x80);
668 rt61pci_bbp_write(rt2x00dev, 88, 0x80);
669 } else {
670 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
671 rt61pci_bbp_write(rt2x00dev, 96, 0x48);
672 rt61pci_bbp_write(rt2x00dev, 104, 0x2c);
673 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
674 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
675 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
676 }
677 rt61pci_bbp_write(rt2x00dev, 35, 0x50);
678 rt61pci_bbp_write(rt2x00dev, 97, 0x48);
679 rt61pci_bbp_write(rt2x00dev, 98, 0x48);
680
681 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
682 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
683 }
684
685 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
686
687 rt61pci_bbp_read(rt2x00dev, 3, &r3);
688 rt61pci_bbp_read(rt2x00dev, 4, &r4);
689 rt61pci_bbp_read(rt2x00dev, 77, &r77);
690
691 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
692 rt2x00_rf(&rt2x00dev->chip, RF2527))
693 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
694
695 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
696 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
697 if (antenna_rx == ANTENNA_DIVERSITY) {
698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
699 if (rt2x00dev->curr_hwmode != HWMODE_A)
700 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
701 } else if (antenna_rx == ANTENNA_A) {
702 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
703 if (rt2x00dev->curr_hwmode == HWMODE_A)
704 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
705 else
706 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
707 rt61pci_bbp_write(rt2x00dev, 77, r77);
708 } else if (antenna_rx == ANTENNA_B) {
709 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
710 if (rt2x00dev->curr_hwmode == HWMODE_A)
711 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
712 else
713 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
714 rt61pci_bbp_write(rt2x00dev, 77, r77);
715 }
716 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527) ||
717 (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
718 test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))) {
719 if (antenna_rx == ANTENNA_DIVERSITY) {
720 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
721 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
722 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
723 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
724 } else if (antenna_rx == ANTENNA_A) {
725 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
726 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
727 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
728 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
729 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
730 rt61pci_bbp_write(rt2x00dev, 77, r77);
731 } else if (antenna_rx == ANTENNA_B) {
732 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
733 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
734 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
735 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
736 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
737 rt61pci_bbp_write(rt2x00dev, 77, r77);
738 }
739 }
740
741 /*
742 * TODO: RF2529 with another antenna value then 2 are ignored.
743 * The legacy driver is unclear whether in those cases there is
744 * a possibility to switch antenna.
745 */
746
747 rt61pci_bbp_write(rt2x00dev, 3, r3);
748 rt61pci_bbp_write(rt2x00dev, 4, r4);
749 }
750
751 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
752 const int short_slot_time, const int beacon_int)
753 {
754 u32 reg;
755
756 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
757 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
758 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
759 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
760
761 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
762 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
763 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
764 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
765 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
766
767 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
768 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
769 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
770
771 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
772 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
773 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
774
775 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
776 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
777 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
778 }
779
780 static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
781 {
782 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
783 u32 reg;
784 u32 value;
785 u32 preamble;
786
787 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
788 ? SHORT_PREAMBLE : PREAMBLE;
789
790 /*
791 * Extract the allowed ratemask from the device specific rate value,
792 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
793 * off the non-basic rates.
794 */
795 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
796
797 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
798
799 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
800 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
801 SHORT_DIFS : DIFS) +
802 PLCP + preamble + get_duration(ACK_SIZE, 10);
803 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
804 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
805
806 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
807 if (preamble == SHORT_PREAMBLE)
808 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
809 else
810 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
811 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
812 }
813
814 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
815 const int phymode)
816 {
817 struct ieee80211_hw_mode *mode;
818 struct ieee80211_rate *rate;
819
820 if (phymode == MODE_IEEE80211A)
821 rt2x00dev->curr_hwmode = HWMODE_A;
822 else if (phymode == MODE_IEEE80211B)
823 rt2x00dev->curr_hwmode = HWMODE_B;
824 else
825 rt2x00dev->curr_hwmode = HWMODE_G;
826
827 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
828 rate = &mode->rates[mode->num_rates - 1];
829
830 rt61pci_config_rate(rt2x00dev, rate->val2);
831 }
832
833 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
834 {
835 u32 reg[2];
836
837 memset(&reg, 0, sizeof(reg));
838 memcpy(&reg, addr, ETH_ALEN);
839
840 rt2x00_set_field32(&reg[1], MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
841
842 /*
843 * The MAC address is passed to us as an array of bytes,
844 * that array is little endian, so no need for byte ordering.
845 */
846 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, &reg, sizeof(reg));
847 }
848
849 /*
850 * LED functions.
851 */
852 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
853 {
854 u32 reg;
855 u16 led_reg;
856 u8 arg0;
857 u8 arg1;
858
859 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
860 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
861 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
862 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
863
864 led_reg = rt2x00dev->led_reg;
865 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
866 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
867 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
868 else
869 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
870
871 arg0 = led_reg & 0xff;
872 arg1 = (led_reg >> 8) & 0xff;
873
874 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
875 }
876
877 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
878 {
879 u16 led_reg;
880 u8 arg0;
881 u8 arg1;
882
883 led_reg = rt2x00dev->led_reg;
884 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
885 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
886 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
887
888 arg0 = led_reg & 0xff;
889 arg1 = (led_reg >> 8) & 0xff;
890
891 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
892 }
893
894 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, char rssi)
895 {
896 u8 led;
897
898 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
899 return;
900
901 if (rssi <= 30)
902 led = 0;
903 else if (rssi <= 39)
904 led = 1;
905 else if (rssi <= 49)
906 led = 2;
907 else if (rssi <= 53)
908 led = 3;
909 else if (rssi <= 63)
910 led = 4;
911 else
912 led = 5;
913
914 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
915 }
916
917 /*
918 * Link tuning
919 */
920 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, int rssi)
921 {
922 u32 reg;
923 u8 r17;
924 u8 up_bound;
925 u8 low_bound;
926
927 /*
928 * Update Led strength
929 */
930 rt61pci_activity_led(rt2x00dev, rssi);
931
932 rt61pci_bbp_read(rt2x00dev, 17, &r17);
933
934 /*
935 * Determine r17 bounds.
936 */
937 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
938 low_bound = 0x28;
939 up_bound = 0x48;
940 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
941 low_bound += 0x10;
942 up_bound += 0x10;
943 }
944 } else {
945 low_bound = 0x20;
946 up_bound = 0x40;
947 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
948 low_bound += 0x10;
949 up_bound += 0x10;
950 }
951 }
952
953 /*
954 * Special big-R17 for very short distance
955 */
956 if (rssi >= -35) {
957 if (r17 != 0x60)
958 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
959 return;
960 }
961
962 /*
963 * Special big-R17 for short distance
964 */
965 if (rssi >= -58) {
966 if (r17 != up_bound)
967 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
968 return;
969 }
970
971 /*
972 * Special big-R17 for middle-short distance
973 */
974 if (rssi >= -66) {
975 low_bound += 0x10;
976 if (r17 != low_bound)
977 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
978 return;
979 }
980
981 /*
982 * Special mid-R17 for middle distance
983 */
984 if (rssi >= -74) {
985 low_bound += 0x08;
986 if (r17 != low_bound)
987 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
988 return;
989 }
990
991 /*
992 * Special case: Change up_bound based on the rssi.
993 * Lower up_bound when rssi is weaker then -74 dBm.
994 */
995 up_bound -= 2 * (-74 - rssi);
996 if (low_bound > up_bound)
997 up_bound = low_bound;
998
999 if (r17 > up_bound) {
1000 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1001 return;
1002 }
1003
1004 /*
1005 * r17 does not yet exceed upper limit, continue and base
1006 * the r17 tuning on the false CCA count.
1007 */
1008 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1009 rt2x00dev->link.false_cca =
1010 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1011
1012 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
1013 if (++r17 > up_bound)
1014 r17 = up_bound;
1015 rt61pci_bbp_write(rt2x00dev, 17, r17);
1016 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
1017 if (--r17 < low_bound)
1018 r17 = low_bound;
1019 rt61pci_bbp_write(rt2x00dev, 17, r17);
1020 }
1021 }
1022
1023 /*
1024 * Firmware name function.
1025 */
1026 static char *rt61pci_get_fw_name(struct rt2x00_dev *rt2x00dev)
1027 {
1028 char *fw_name;
1029
1030 switch (rt2x00dev->chip.rt) {
1031 case RT2561:
1032 fw_name = FIRMWARE_RT2561;
1033 break;
1034 case RT2561s:
1035 fw_name = FIRMWARE_RT2561s;
1036 break;
1037 case RT2661:
1038 fw_name = FIRMWARE_RT2661;
1039 break;
1040 default:
1041 fw_name = NULL;
1042 break;
1043 }
1044
1045 return fw_name;
1046 }
1047
1048 /*
1049 * Initialization functions.
1050 */
1051 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
1052 const size_t len)
1053 {
1054 int i;
1055 u32 reg;
1056
1057 /*
1058 * Wait for stable hardware.
1059 */
1060 for (i = 0; i < 100; i++) {
1061 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1062 if (reg)
1063 break;
1064 msleep(1);
1065 }
1066
1067 if (!reg) {
1068 ERROR(rt2x00dev, "Unstable hardware.\n");
1069 return -EBUSY;
1070 }
1071
1072 /*
1073 * Prepare MCU and mailbox for firmware loading.
1074 */
1075 reg = 0;
1076 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1077 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1078 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1079 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1080 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1081
1082 /*
1083 * Write firmware to device.
1084 */
1085 reg = 0;
1086 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1087 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1088 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1089
1090 rt2x00pci_register_multiwrite(
1091 rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1092
1093 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1094 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1095
1096 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1097 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1098
1099 for (i = 0; i < 100; i++) {
1100 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1101 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1102 break;
1103 msleep(1);
1104 }
1105
1106 if (i == 100) {
1107 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1108 return -EBUSY;
1109 }
1110
1111 /*
1112 * Reset MAC and BBP registers.
1113 */
1114 reg = 0;
1115 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1116 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1117 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1118
1119 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1120 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1121 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1122 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1123
1124 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1125 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1126 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1127
1128 return 0;
1129 }
1130
1131 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1132 {
1133 struct data_desc *rxd;
1134 unsigned int i;
1135 u32 word;
1136
1137 memset(rt2x00dev->rx->data_addr, 0x00,
1138 rt2x00_get_ring_size(rt2x00dev->rx));
1139
1140 for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
1141 rxd = rt2x00dev->rx->entry[i].priv;
1142
1143 rt2x00_desc_read(rxd, 5, &word);
1144 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1145 rt2x00dev->rx->entry[i].data_dma);
1146 rt2x00_desc_write(rxd, 5, word);
1147
1148 rt2x00_desc_read(rxd, 0, &word);
1149 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1150 rt2x00_desc_write(rxd, 0, word);
1151 }
1152
1153 rt2x00_ring_index_clear(rt2x00dev->rx);
1154 }
1155
1156 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev,
1157 const int queue)
1158 {
1159 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1160 struct data_desc *txd;
1161 unsigned int i;
1162 u32 word;
1163
1164 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1165
1166 for (i = 0; i < ring->stats.limit; i++) {
1167 txd = ring->entry[i].priv;
1168
1169 rt2x00_desc_read(txd, 1, &word);
1170 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1171 rt2x00_desc_write(txd, 1, word);
1172
1173 rt2x00_desc_read(txd, 5, &word);
1174 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1175 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1176 rt2x00_desc_write(txd, 5, word);
1177
1178 rt2x00_desc_read(txd, 6, &word);
1179 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1180 ring->entry[i].data_dma);
1181 rt2x00_desc_write(txd, 6, word);
1182
1183 rt2x00_desc_read(txd, 0, &word);
1184 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1185 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1186 rt2x00_desc_write(txd, 0, word);
1187 }
1188
1189 rt2x00_ring_index_clear(ring);
1190 }
1191
1192 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1193 {
1194 u32 reg;
1195
1196 /*
1197 * Initialize rings.
1198 */
1199 rt61pci_init_rxring(rt2x00dev);
1200 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1201 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1202 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1203 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1204 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1205 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1206
1207 /*
1208 * Initialize registers.
1209 */
1210 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1211 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1212 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1213 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1214 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1215 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1216 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1217 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1218 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1219 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1220
1221 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1222 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1223 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1224 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1225 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size / 4);
1226 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1227
1228 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1229 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1230 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1231 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1232
1233 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1234 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1235 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1236 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1237
1238 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1239 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1240 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1241 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1242
1243 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1244 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1245 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1246 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1247
1248 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1249 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1250 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1251 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1252
1253 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1254 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
1255 rt2x00dev->rx->stats.limit);
1256 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1257 rt2x00dev->rx->desc_size / 4);
1258 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1259 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1260
1261 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1262 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1263 rt2x00dev->rx->data_dma);
1264 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1265
1266 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, 0x000000aa);
1267 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, 0x0000001f);
1268 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, 0x00000002);
1269
1270 return 0;
1271 }
1272
1273 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1274 {
1275 u32 reg;
1276
1277 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1278 return -EBUSY;
1279
1280 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1281
1282 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, 0x025eb032);
1283
1284 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, 0x9eb39eb3);
1285 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, 0x8a8b8c8d);
1286 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, 0x00858687);
1287
1288 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, 0x2e31353b);
1289 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, 0x2a2a2a2c);
1290
1291 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1292
1293 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1294
1295 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1296
1297 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1298 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1299 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1300
1301 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1302 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1303 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1304 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1305
1306 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1307 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1308 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1309 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1310
1311 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1312 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1313 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1314
1315 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1316 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1317 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1318
1319 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1320 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1321 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1322 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1323
1324 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1325
1326 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1327
1328 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1329
1330 /*
1331 * We must clear the error counters.
1332 * These registers are cleared on read,
1333 * so we may pass a useless variable to store the value.
1334 */
1335 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1336 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1337 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1338
1339 /*
1340 * Reset MAC and BBP registers.
1341 */
1342 reg = 0;
1343 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1344 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1345 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1346
1347 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1348 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1349 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1350 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1351
1352 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1353 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1354 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1355
1356 return 0;
1357 }
1358
1359 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1360 {
1361 unsigned int i;
1362 u16 eeprom;
1363 u8 reg_id;
1364 u8 value;
1365
1366 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1367 rt61pci_bbp_read(rt2x00dev, 0, &value);
1368 if ((value != 0xff) && (value != 0x00))
1369 goto continue_csr_init;
1370 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1371 udelay(REGISTER_BUSY_DELAY);
1372 }
1373
1374 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1375 return -EACCES;
1376
1377 continue_csr_init:
1378 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1379 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1380 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1381 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1382 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1383 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1384 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1385 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1386 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1387 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1388 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1389 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1390 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1391 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1392 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1393 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1394 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1395 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1396 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1397 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1398 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1399 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1400 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1401 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1402 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1403
1404 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1405 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1406 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1407
1408 if (eeprom != 0xffff && eeprom != 0x0000) {
1409 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1410 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1411 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1412 reg_id, value);
1413 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1414 }
1415 }
1416 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1417
1418 return 0;
1419 }
1420
1421 /*
1422 * Device state switch handlers.
1423 */
1424 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1425 enum dev_state state)
1426 {
1427 u32 reg;
1428
1429 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1430 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1431 state == STATE_RADIO_RX_OFF);
1432 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1433 }
1434
1435 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1436 {
1437 u32 reg;
1438
1439 /*
1440 * Initialize all registers.
1441 */
1442 if (rt61pci_init_rings(rt2x00dev) ||
1443 rt61pci_init_registers(rt2x00dev) ||
1444 rt61pci_init_bbp(rt2x00dev)) {
1445 ERROR(rt2x00dev, "Register initialization failed.\n");
1446 return -EIO;
1447 }
1448
1449 /*
1450 * Clear interrupts.
1451 */
1452 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1453 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1454
1455 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1456 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1457
1458 /*
1459 * Enable interrupts.
1460 */
1461 reg = 0;
1462 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_ABORT_DONE, 1);
1463 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1464 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1465
1466 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, 0x00000000);
1467
1468 /*
1469 * Enable RX.
1470 */
1471 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, 0x00000001);
1472
1473 /*
1474 * Enable LED
1475 */
1476 rt61pci_enable_led(rt2x00dev);
1477
1478 return 0;
1479 }
1480
1481 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1482 {
1483 u32 reg;
1484
1485 /*
1486 * Disable LED
1487 */
1488 rt61pci_disable_led(rt2x00dev);
1489
1490 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1491
1492 /*
1493 * Disable synchronisation.
1494 */
1495 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1496
1497 /*
1498 * Cancel RX and TX.
1499 */
1500 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1501 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1502 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1503 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1504 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1505 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1506 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1507
1508 /*
1509 * Disable interrupts.
1510 */
1511 reg = 0xffffffff;
1512 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, 0);
1513 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1514
1515 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, 0xffffffff);
1516 }
1517
1518 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev,
1519 enum dev_state state)
1520 {
1521 u32 reg;
1522 unsigned int i;
1523 char put_to_sleep;
1524 char current_state;
1525
1526 put_to_sleep = (state != STATE_AWAKE);
1527
1528 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1529 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1530 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1531 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1532
1533 if (put_to_sleep) {
1534 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
1535 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
1536 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
1537 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0x00, 0x00);
1538 } else {
1539 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
1540 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
1541 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
1542 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0x00, 0x00);
1543 }
1544
1545 /*
1546 * Device is not guaranteed to be in the requested state yet.
1547 * We must wait until the register indicates that the
1548 * device has entered the correct state.
1549 */
1550 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1551 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1552 current_state = rt2x00_get_field32(reg,
1553 MAC_CSR12_BBP_CURRENT_STATE);
1554 if (current_state == !put_to_sleep)
1555 return 0;
1556 msleep(10);
1557 }
1558
1559 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1560 "current device state %d.\n", !put_to_sleep, current_state);
1561
1562 return -EBUSY;
1563 }
1564
1565 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1566 enum dev_state state)
1567 {
1568 int retval = 0;
1569
1570 switch (state) {
1571 case STATE_RADIO_ON:
1572 retval = rt61pci_enable_radio(rt2x00dev);
1573 break;
1574 case STATE_RADIO_OFF:
1575 rt61pci_disable_radio(rt2x00dev);
1576 break;
1577 case STATE_RADIO_RX_ON:
1578 case STATE_RADIO_RX_OFF:
1579 rt61pci_toggle_rx(rt2x00dev, state);
1580 break;
1581 case STATE_DEEP_SLEEP:
1582 case STATE_SLEEP:
1583 case STATE_STANDBY:
1584 case STATE_AWAKE:
1585 retval = rt61pci_set_state(rt2x00dev, state);
1586 break;
1587 default:
1588 retval = -ENOTSUPP;
1589 break;
1590 }
1591
1592 return retval;
1593 }
1594
1595 /*
1596 * TX descriptor initialization
1597 */
1598 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1599 struct data_entry *entry, struct data_desc *txd,
1600 struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1601 unsigned int length, struct ieee80211_tx_control *control)
1602 {
1603 u32 word;
1604
1605 /*
1606 * Start writing the descriptor words.
1607 */
1608 rt2x00_desc_read(txd, 1, &word);
1609 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1610 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->ring->tx_params.aifs);
1611 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->ring->tx_params.cw_min);
1612 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->ring->tx_params.cw_max);
1613 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1614 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1615 rt2x00_desc_write(txd, 1, word);
1616
1617 rt2x00_desc_read(txd, 2, &word);
1618 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1619 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1620 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1621 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1622 rt2x00_desc_write(txd, 2, word);
1623
1624 rt2x00_desc_read(txd, 5, &word);
1625 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1626 TXPOWER_TO_DEV(control->power_level));
1627 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1628 rt2x00_desc_write(txd, 5, word);
1629
1630 rt2x00_desc_read(txd, 11, &word);
1631 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1632 rt2x00_desc_write(txd, 11, word);
1633
1634 rt2x00_desc_read(txd, 0, &word);
1635 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1636 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1637 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1638 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1639 rt2x00_set_field32(&word, TXD_W0_ACK,
1640 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1641 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1642 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1643 rt2x00_set_field32(&word, TXD_W0_OFDM,
1644 test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
1645 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1646 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1647 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1648 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1649 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1650 rt2x00_desc_write(txd, 0, word);
1651 }
1652
1653 /*
1654 * TX data initialization
1655 */
1656 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1657 {
1658 u32 reg;
1659
1660 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1661 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1662 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1663 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1664 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1665 }
1666 return;
1667 }
1668
1669 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1670 if (queue == IEEE80211_TX_QUEUE_DATA0)
1671 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1672 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1673 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1674 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1675 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1676 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1677 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1678 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1679 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1680 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1681 }
1682
1683 /*
1684 * Interrupt functions.
1685 */
1686 static void rt61pci_rxdone(struct rt2x00_dev *rt2x00dev)
1687 {
1688 struct data_ring *ring = rt2x00dev->rx;
1689 struct data_entry *entry;
1690 struct data_desc *rxd;
1691 u32 word0;
1692 u32 word1;
1693 int signal;
1694 int rssi;
1695 int ofdm;
1696 u16 size;
1697
1698 while (1) {
1699 entry = rt2x00_get_data_entry(ring);
1700 rxd = entry->priv;
1701 rt2x00_desc_read(rxd, 0, &word0);
1702 rt2x00_desc_read(rxd, 1, &word1);
1703
1704 if (rt2x00_get_field32(word0, RXD_W0_OWNER_NIC))
1705 break;
1706
1707 /*
1708 * TODO: Don't we need to keep statistics
1709 * updated about events like CRC and physical errors?
1710 */
1711 if (rt2x00_get_field32(word0, RXD_W0_CRC))
1712 goto skip_entry;
1713
1714 /*
1715 * Obtain the status about this packet.
1716 */
1717 size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1718 signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1719 rssi = rt2x00_get_field32(word1, RXD_W1_RSSI);
1720 ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1721
1722 /*
1723 * Send the packet to upper layer.
1724 */
1725 rt2x00lib_rxdone(entry, entry->data_addr, size,
1726 signal, rssi, ofdm);
1727
1728 skip_entry:
1729 if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
1730 rt2x00_set_field32(&word0, RXD_W0_OWNER_NIC, 1);
1731 rt2x00_desc_write(rxd, 0, word0);
1732 }
1733
1734 rt2x00_ring_index_inc(ring);
1735 }
1736 }
1737
1738 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1739 {
1740 struct data_ring *ring;
1741 struct data_entry *entry;
1742 struct data_desc *txd;
1743 u32 word;
1744 u32 reg;
1745 int index;
1746 int tx_status;
1747 int retry;
1748
1749 while (1) {
1750 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1751 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1752 break;
1753
1754 /*
1755 * Skip this entry when it contains an invalid
1756 * ring identication number.
1757 */
1758 ring = rt2x00_get_ring(rt2x00dev,
1759 rt2x00_get_field32(reg, STA_CSR4_PID_TYPE));
1760 if (unlikely(!ring))
1761 continue;
1762
1763 /*
1764 * Skip this entry when it contains an invalid
1765 * index number.
1766 */
1767 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1768 if (unlikely(index >= ring->stats.limit))
1769 continue;
1770
1771 entry = &ring->entry[index];
1772 txd = entry->priv;
1773 rt2x00_desc_read(txd, 0, &word);
1774
1775 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1776 !rt2x00_get_field32(word, TXD_W0_VALID))
1777 return;
1778
1779 /*
1780 * Obtain the status about this packet.
1781 */
1782 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1783 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1784
1785 rt2x00lib_txdone(entry, tx_status, retry);
1786
1787 /*
1788 * Make this entry available for reuse.
1789 */
1790 entry->flags = 0;
1791 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1792 rt2x00_desc_write(txd, 0, word);
1793 rt2x00_ring_index_done_inc(entry->ring);
1794
1795 /*
1796 * If the data ring was full before the txdone handler
1797 * we must make sure the packet queue in the mac80211 stack
1798 * is reenabled when the txdone handler has finished.
1799 */
1800 if (!rt2x00_ring_full(ring))
1801 ieee80211_wake_queue(rt2x00dev->hw,
1802 entry->tx_status.control.queue);
1803 }
1804 }
1805
1806 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1807 {
1808 struct rt2x00_dev *rt2x00dev = dev_instance;
1809 u32 reg;
1810
1811 /*
1812 * Get the interrupt sources & saved to local variable.
1813 * Write register value back to clear pending interrupts.
1814 */
1815 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1816 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1817
1818 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1819 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1820
1821 if (!reg)
1822 return IRQ_NONE;
1823
1824 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1825 return IRQ_HANDLED;
1826
1827 /*
1828 * Handle interrupts, walk through all bits
1829 * and run the tasks, the bits are checked in order of
1830 * priority.
1831 */
1832
1833 /*
1834 * 1 - Beacon timer expired interrupt.
1835 */
1836 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
1837 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1838
1839 /*
1840 * 2 - Rx ring done interrupt.
1841 */
1842 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1843 rt61pci_rxdone(rt2x00dev);
1844
1845 /*
1846 * 3 - Tx ring done interrupt.
1847 */
1848 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1849 rt61pci_txdone(rt2x00dev);
1850
1851 return IRQ_HANDLED;
1852 }
1853
1854 /*
1855 * Device initialization functions.
1856 */
1857 static int rt61pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1858 {
1859 struct eeprom_93cx6 eeprom;
1860 u32 reg;
1861 u16 word;
1862
1863 /*
1864 * Allocate the eeprom memory, check the eeprom width
1865 * and copy the entire eeprom into this allocated memory.
1866 */
1867 rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1868 if (!rt2x00dev->eeprom)
1869 return -ENOMEM;
1870
1871 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1872
1873 eeprom.data = rt2x00dev;
1874 eeprom.register_read = rt61pci_eepromregister_read;
1875 eeprom.register_write = rt61pci_eepromregister_write;
1876 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1877 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1878 eeprom.reg_data_in = 0;
1879 eeprom.reg_data_out = 0;
1880 eeprom.reg_data_clock = 0;
1881 eeprom.reg_chip_select = 0;
1882
1883 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1884 EEPROM_SIZE / sizeof(u16));
1885
1886 /*
1887 * Start validation of the data that has been read.
1888 */
1889 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1890 if (word == 0xffff) {
1891 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1892 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1893 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1894 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1895 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1896 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1897 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1898 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1899 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1900 }
1901
1902 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1903 if (word == 0xffff) {
1904 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1905 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1906 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1907 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1908 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1909 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1910 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1911 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1912 }
1913
1914 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1915 if (word == 0xffff) {
1916 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1917 LED_MODE_DEFAULT);
1918 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1919 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1920 }
1921
1922 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1923 if (word == 0xffff) {
1924 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1925 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1926 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1927 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1928 }
1929
1930 return 0;
1931 }
1932
1933 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1934 {
1935 u32 reg;
1936 u16 value;
1937 u16 eeprom;
1938 u16 device;
1939
1940 /*
1941 * Read EEPROM word for configuration.
1942 */
1943 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1944
1945 /*
1946 * Identify RF chipset.
1947 * To determine the RT chip we have to read the
1948 * PCI header of the device.
1949 */
1950 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1951 PCI_CONFIG_HEADER_DEVICE, &device);
1952 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1953 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1954 rt2x00_set_chip(rt2x00dev, device, value, reg);
1955
1956 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1957 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1958 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1959 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1960 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1961 return -ENODEV;
1962 }
1963
1964 /*
1965 * Identify default antenna configuration.
1966 */
1967 rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1968 EEPROM_ANTENNA_TX_DEFAULT);
1969 rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1970 EEPROM_ANTENNA_RX_DEFAULT);
1971
1972 /*
1973 * Read the Frame type.
1974 */
1975 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1976 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1977
1978 /*
1979 * Determine number of antenna's.
1980 */
1981 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1982 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1983
1984 /*
1985 * Detect if this device has an hardware controlled radio.
1986 */
1987 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1988 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1989
1990 /*
1991 * Read frequency offset and RF programming sequence.
1992 */
1993 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1994 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1995 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1996
1997 rt2x00dev->freq_offset =
1998 rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1999
2000 /*
2001 * Read external LNA informations.
2002 */
2003 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2004
2005 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2006 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2007 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2008 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2009
2010 /*
2011 * Store led settings, for correct led behaviour.
2012 * If the eeprom value is invalid,
2013 * switch to default led mode.
2014 */
2015 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2016
2017 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2018
2019 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2020 rt2x00dev->led_mode);
2021 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2022 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_0));
2023 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2024 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_1));
2025 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2026 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_2));
2027 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2028 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_3));
2029 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2030 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_4));
2031 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2032 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2033 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2034 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_G));
2035 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2036 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_A));
2037
2038 return 0;
2039 }
2040
2041 /*
2042 * RF value list for RF5225, RF5325, RF2527 & RF2529
2043 * Supports: 2.4 GHz
2044 */
2045 static const u32 rf_vals_bg[] = {
2046 0x00004786, 0x00004786, 0x0000478a, 0x0000478a, 0x0000478e,
2047 0x0000478e, 0x00004792, 0x00004792, 0x00004796, 0x00004796,
2048 0x0000479a, 0x0000479a, 0x0000479e, 0x000047a2
2049 };
2050
2051 /*
2052 * RF value list for RF5225 & RF5325 (supplement to vals_bg)
2053 * Supports: 5.2 GHz, rf_sequence disabled
2054 */
2055 static const u32 rf_vals_a_5x_noseq[] = {
2056 0x0000499a, 0x000049a2, 0x000049a6, 0x000049aa, 0x000049ae,
2057 0x000049b2, 0x000049ba, 0x000049be, 0x00004a2a, 0x00004a2e,
2058 0x00004a32, 0x00004a36, 0x00004a3a, 0x00004a82, 0x00004a86,
2059 0x00004a8a, 0x00004a8e, 0x00004a92, 0x00004a9a, 0x00004aa2,
2060 0x00004aa6, 0x00004aae, 0x00004ab2, 0x00004ab6
2061 };
2062
2063 /*
2064 * RF value list for RF5225 & RF5325 (supplement to vals_bg)
2065 * Supports: 5.2 GHz, rf_sequence enabled
2066 */
2067 static const u32 rf_vals_a_5x_seq[] = {
2068 0x0004481a, 0x00044682, 0x00044686, 0x0004468e, 0x00044692,
2069 0x0004469a, 0x000446a2, 0x000446a6, 0x0004489a, 0x000448a2,
2070 0x000448aa, 0x000448b2, 0x000448ba, 0x00044702, 0x00044706,
2071 0x0004470e, 0x00044712, 0x0004471a, 0x00044722, 0x0004472e,
2072 0x00044736, 0x0004490a, 0x00044912, 0x0004491a
2073 };
2074
2075 static void rt61pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
2076 {
2077 struct hw_mode_spec *spec = &rt2x00dev->spec;
2078 u8 *txpower;
2079 unsigned int i;
2080
2081 /*
2082 * Initialize all hw fields.
2083 */
2084 rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
2085 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2086 IEEE80211_HW_WEP_INCLUDE_IV |
2087 IEEE80211_HW_DATA_NULLFUNC_ACK |
2088 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
2089 IEEE80211_HW_MONITOR_DURING_OPER;
2090 rt2x00dev->hw->extra_tx_headroom = 0;
2091 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2092 rt2x00dev->hw->max_noise = MAX_RX_NOISE;
2093 rt2x00dev->hw->queues = 5;
2094
2095 /*
2096 * Convert tx_power array in eeprom.
2097 */
2098 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2099 for (i = 0; i < 14; i++)
2100 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2101
2102 /*
2103 * Initialize hw_mode information.
2104 */
2105 spec->mac_addr = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2106 spec->num_modes = 2;
2107 spec->num_rates = 12;
2108 spec->num_channels = 14;
2109 spec->tx_power_a = NULL;
2110 spec->tx_power_bg = txpower;
2111 spec->tx_power_default = DEFAULT_TXPOWER;
2112 spec->chan_val_a = NULL;
2113 spec->chan_val_bg = rf_vals_bg;
2114
2115 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2116 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2117 spec->num_modes = 3;
2118 spec->num_channels += 24;
2119
2120 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2121 for (i = 0; i < 14; i++)
2122 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2123
2124 spec->tx_power_a = txpower;
2125 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags))
2126 spec->chan_val_a = rf_vals_a_5x_noseq;
2127 else
2128 spec->chan_val_a = rf_vals_a_5x_seq;
2129 }
2130 }
2131
2132 static int rt61pci_init_hw(struct rt2x00_dev *rt2x00dev)
2133 {
2134 int retval;
2135
2136 /*
2137 * Allocate eeprom data.
2138 */
2139 retval = rt61pci_alloc_eeprom(rt2x00dev);
2140 if (retval)
2141 return retval;
2142
2143 retval = rt61pci_init_eeprom(rt2x00dev);
2144 if (retval)
2145 return retval;
2146
2147 /*
2148 * Initialize hw specifications.
2149 */
2150 rt61pci_init_hw_mode(rt2x00dev);
2151
2152 /*
2153 * rt61pci requires firmware
2154 */
2155 __set_bit(FIRMWARE_REQUIRED, &rt2x00dev->flags);
2156
2157 return 0;
2158 }
2159
2160 /*
2161 * IEEE80211 stack callback functions.
2162 */
2163 static int rt61pci_get_stats(struct ieee80211_hw *hw,
2164 struct ieee80211_low_level_stats *stats)
2165 {
2166 struct rt2x00_dev *rt2x00dev = hw->priv;
2167 u32 reg;
2168
2169 /*
2170 * Update FCS error count from register.
2171 * The dot11ACKFailureCount, dot11RTSFailureCount and
2172 * dot11RTSSuccessCount are updated in interrupt time.
2173 */
2174 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
2175 rt2x00dev->low_level_stats.dot11FCSErrorCount +=
2176 rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
2177
2178 memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
2179
2180 return 0;
2181 }
2182
2183 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2184 u32 short_retry, u32 long_retry)
2185 {
2186 struct rt2x00_dev *rt2x00dev = hw->priv;
2187 u32 reg;
2188
2189 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2190 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2191 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2192 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2193
2194 return 0;
2195 }
2196
2197 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2198 {
2199 struct rt2x00_dev *rt2x00dev = hw->priv;
2200 u64 tsf;
2201 u32 reg;
2202
2203 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2204 tsf = (u64)rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2205 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2206 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2207
2208 return tsf;
2209 }
2210
2211 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2212 {
2213 struct rt2x00_dev *rt2x00dev = hw->priv;
2214
2215 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2216 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2217 }
2218
2219 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2220 .tx = rt2x00lib_tx,
2221 .reset = rt2x00lib_reset,
2222 .open = rt2x00lib_open,
2223 .stop = rt2x00lib_stop,
2224 .add_interface = rt2x00lib_add_interface,
2225 .remove_interface = rt2x00lib_remove_interface,
2226 .config = rt2x00lib_config,
2227 .config_interface = rt2x00lib_config_interface,
2228 .set_multicast_list = rt2x00lib_set_multicast_list,
2229 .get_stats = rt61pci_get_stats,
2230 .set_retry_limit = rt61pci_set_retry_limit,
2231 .conf_tx = rt2x00lib_conf_tx,
2232 .get_tx_stats = rt2x00lib_get_tx_stats,
2233 .get_tsf = rt61pci_get_tsf,
2234 .reset_tsf = rt61pci_reset_tsf,
2235 .beacon_update = rt2x00pci_beacon_update,
2236 };
2237
2238 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2239 .irq_handler = rt61pci_interrupt,
2240 .init_hw = rt61pci_init_hw,
2241 .get_fw_name = rt61pci_get_fw_name,
2242 .load_firmware = rt61pci_load_firmware,
2243 .initialize = rt2x00pci_initialize,
2244 .uninitialize = rt2x00pci_uninitialize,
2245 .set_device_state = rt61pci_set_device_state,
2246 #ifdef CONFIG_RT61PCI_RFKILL
2247 .rfkill_poll = rt61pci_rfkill_poll,
2248 #endif /* CONFIG_RT61PCI_RFKILL */
2249 .link_tuner = rt61pci_link_tuner,
2250 .write_tx_desc = rt61pci_write_tx_desc,
2251 .write_tx_data = rt2x00pci_write_tx_data,
2252 .kick_tx_queue = rt61pci_kick_tx_queue,
2253 .config_type = rt61pci_config_type,
2254 .config_phymode = rt61pci_config_phymode,
2255 .config_channel = rt61pci_config_channel,
2256 .config_mac_addr = rt61pci_config_mac_addr,
2257 .config_bssid = rt61pci_config_bssid,
2258 .config_promisc = rt61pci_config_promisc,
2259 .config_txpower = rt61pci_config_txpower,
2260 .config_antenna = rt61pci_config_antenna,
2261 .config_duration = rt61pci_config_duration,
2262 };
2263
2264 static const struct rt2x00_ops rt61pci_ops = {
2265 .name = DRV_NAME,
2266 .rxd_size = RXD_DESC_SIZE,
2267 .txd_size = TXD_DESC_SIZE,
2268 .lib = &rt61pci_rt2x00_ops,
2269 .hw = &rt61pci_mac80211_ops,
2270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2271 .debugfs = &rt61pci_rt2x00debug,
2272 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2273 };
2274
2275 /*
2276 * RT61pci module information.
2277 */
2278 static struct pci_device_id rt61pci_device_table[] = {
2279 /* RT2561s */
2280 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2281 /* RT2561 v2 */
2282 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2283 /* RT2661 */
2284 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2285 { 0, }
2286 };
2287
2288 MODULE_AUTHOR(DRV_PROJECT);
2289 MODULE_VERSION(DRV_VERSION);
2290 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2291 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2292 "PCI & PCMCIA chipset based cards");
2293 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2294 MODULE_FIRMWARE(FIRMWARE_RT2561);
2295 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2296 MODULE_FIRMWARE(FIRMWARE_RT2661);
2297 MODULE_LICENSE("GPL");
2298
2299 static struct pci_driver rt61pci_driver = {
2300 .name = DRV_NAME,
2301 .id_table = rt61pci_device_table,
2302 .probe = rt2x00pci_probe,
2303 .remove = __devexit_p(rt2x00pci_remove),
2304 #ifdef CONFIG_PM
2305 .suspend = rt2x00pci_suspend,
2306 .resume = rt2x00pci_resume,
2307 #endif /* CONFIG_PM */
2308 };
2309
2310 static int __init rt61pci_init(void)
2311 {
2312 printk(KERN_INFO "Loading module: %s - %s by %s.\n",
2313 DRV_NAME, DRV_VERSION, DRV_PROJECT);
2314 return pci_register_driver(&rt61pci_driver);
2315 }
2316
2317 static void __exit rt61pci_exit(void)
2318 {
2319 printk(KERN_INFO "Unloading module: %s.\n", DRV_NAME);
2320 pci_unregister_driver(&rt61pci_driver);
2321 }
2322
2323 module_init(rt61pci_init);
2324 module_exit(rt61pci_exit);
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