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[ar71xx] add default network configuration for the TL-WR941ND board
[openwrt.git] / target / linux / s3c24xx / patches-2.6.24 / 1231-fix-glamo-suspend-resume-dram-and-engines.patch.patch
1 From e1673170182af199be7c6a2a346d8bad7e4dc532 Mon Sep 17 00:00:00 2001
2 From: Andy Green <andy@openmoko.com>
3 Date: Tue, 15 Jul 2008 09:04:00 +0100
4 Subject: [PATCH] fix-glamo-suspend-resume-dram-and-engines.patch
5
6 Two issues... we never took care to take down engines in suspend
7 and bring them back in resume. This was part of the display
8 corruption that could be seen briefly on resume. The other issue
9 that made the "noise" corruption was bad ordering of resume steps.
10
11 This patch simplifies (removing needless re-init) resume actions
12 and makes explicit the suspend and resume steps. It also adds
13 code to track which engines are up and push them down in suspend
14 and bring them back in resume.
15
16 The result is no more corruption of display buffer in suspend, it
17 comes back completely clean.
18
19 Signed-off-by: Andy Green <andy@openmoko.com>
20 ---
21 drivers/mfd/glamo/glamo-core.c | 266 +++++++++++++++++++---------------------
22 drivers/mfd/glamo/glamo-core.h | 2 +
23 drivers/mfd/glamo/glamo-regs.h | 6 +-
24 3 files changed, 135 insertions(+), 139 deletions(-)
25
26 diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
27 index 2412b7d..bea0387 100644
28 --- a/drivers/mfd/glamo/glamo-core.c
29 +++ b/drivers/mfd/glamo/glamo-core.c
30 @@ -54,6 +54,8 @@
31
32 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
33
34 +#define GLAMO_MEM_REFRESH_COUNT 0x100
35 +
36 static struct glamo_core *glamo_handle;
37
38 static inline void __reg_write(struct glamo_core *glamo,
39 @@ -381,9 +383,8 @@ out_unlock:
40 * 'engine' support
41 ***********************************************************************/
42
43 -int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
44 +int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
45 {
46 - spin_lock(&glamo->lock);
47 switch (engine) {
48 case GLAMO_ENGINE_LCD:
49 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
50 @@ -432,27 +433,59 @@ int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
51 default:
52 break;
53 }
54 - spin_unlock(&glamo->lock);
55 +
56 + glamo->engine_enabled_bitfield |= 1 << engine;
57
58 return 0;
59 }
60 -EXPORT_SYMBOL_GPL(glamo_engine_enable);
61
62 -int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
63 +int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
64 {
65 + int ret;
66 +
67 spin_lock(&glamo->lock);
68 +
69 + ret = __glamo_engine_enable(glamo, engine);
70 +
71 + spin_unlock(&glamo->lock);
72 +
73 + return ret;
74 +}
75 +EXPORT_SYMBOL_GPL(glamo_engine_enable);
76 +
77 +int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
78 +{
79 switch (engine) {
80 + case GLAMO_ENGINE_LCD:
81 + /* remove pixel clock to LCM */
82 + __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
83 + GLAMO_CLOCK_LCD_EN_DCLK, 0);
84 + __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
85 + GLAMO_CLOCK_LCD_EN_DHCLK |
86 + GLAMO_CLOCK_LCD_EN_DMCLK, 0);
87 + /* kill memory clock */
88 + __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89 + GLAMO_CLOCK_LCD_EN_M5CLK, 0);
90 + /* stop dividing the clocks */
91 + __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
92 + GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
93 + GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
94 + GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
95 + __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
96 + GLAMO_HOSTBUS2_MMIO_EN_LCD, 0);
97 + break;
98 +
99 case GLAMO_ENGINE_MMC:
100 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC, 0,
101 GLAMO_CLOCK_MMC_EN_M9CLK |
102 GLAMO_CLOCK_MMC_EN_TCLK |
103 GLAMO_CLOCK_MMC_DG_M9CLK |
104 GLAMO_CLOCK_MMC_DG_TCLK);
105 - __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2), 0,
106 - GLAMO_HOSTBUS2_MMIO_EN_MMC);
107 /* disable the TCLK divider clk input */
108 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0,
109 GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
110 + __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2), 0,
111 + GLAMO_HOSTBUS2_MMIO_EN_MMC);
112 /* good idea to hold the thing in reset when we power it off? */
113 /* writew(readw(glamo->base + GLAMO_REG_CLOCK_MMC) |
114 GLAMO_CLOCK_MMC_RESET, glamo->base + GLAMO_REG_CLOCK_MMC);
115 @@ -461,10 +494,23 @@ int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
116 default:
117 break;
118 }
119 - spin_unlock(&glamo->lock);
120 +
121 + glamo->engine_enabled_bitfield &= ~(1 << engine);
122
123 return 0;
124 }
125 +int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
126 +{
127 + int ret;
128 +
129 + spin_lock(&glamo->lock);
130 +
131 + ret = __glamo_engine_disable(glamo, engine);
132 +
133 + spin_unlock(&glamo->lock);
134 +
135 + return ret;
136 +}
137 EXPORT_SYMBOL_GPL(glamo_engine_disable);
138
139 struct glamo_script reset_regs[] = {
140 @@ -618,7 +664,7 @@ int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
141 if (may_sleep)
142 msleep(line->val);
143 else
144 - mdelay(line->val);
145 + mdelay(line->val * 4);
146 break;
147 case 0xfffd:
148 /* spin until PLLs lock */
149 @@ -717,111 +763,17 @@ static struct glamo_script glamo_init_script[] = {
150 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
151 };
152
153 -static struct glamo_script glamo_resume_script[] = {
154 - { GLAMO_REG_IRQ_ENABLE, 0x01ff },
155 - { GLAMO_REG_CLOCK_GEN6, 0x2000 },
156 - { GLAMO_REG_CLOCK_GEN7, 0x0001 }, /* 0101 */
157 - { GLAMO_REG_CLOCK_GEN8, 0x0100 },
158 - { GLAMO_REG_CLOCK_HOST, 0x000d },
159 - { 0x200, 0x0ef0 },
160 - { 0x202, 0x07ff },
161 - { 0x212, 0x0000 },
162 - { 0x214, 0x4000 },
163 - { 0x216, 0xf00e },
164 - { GLAMO_REG_MEM_TYPE, 0x0874 }, /* 8MB, 16 word pg wr+rd */
165 - { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
166 -
167 - { GLAMO_REG_MEM_TIMING1, 0x0108 },
168 - { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
169 - { GLAMO_REG_MEM_TIMING3, 0x0000 },
170 - { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
171 - { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
172 - { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
173 - { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
174 - { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
175 - { GLAMO_REG_MEM_TIMING9, 0x6006 },
176 - { GLAMO_REG_MEM_TIMING10, 0x00ff },
177 - { GLAMO_REG_MEM_TIMING11, 0x0001 },
178 - { GLAMO_REG_MEM_POWER1, 0x0020 },
179 - { GLAMO_REG_MEM_POWER2, 0x0000 },
180 - { GLAMO_REG_MEM_DRAM1, 0x0000 },
181 - { 0xfffe, 1 },
182 - { GLAMO_REG_MEM_DRAM1, 0xc100 },
183 - { 0xfffe, 1 },
184 - { GLAMO_REG_MEM_DRAM1, 0xe100 },
185 - { GLAMO_REG_MEM_DRAM2, 0x01d6 },
186 - { GLAMO_REG_CLOCK_MEMORY, 0x000b },
187 -};
188 -
189 -#if 0 /* MM370 */
190 -static const struct glamo_script regs_vram_2mb = {
191 - { GLAMO_REG_CLOCK_MEMORY, 0x3aaa },
192 - { 0xfffe, 50 },
193 - { GLAMO_REG_CLOCK_MEMORY, 0x0aaa },
194 - { 0xfffe, 3 },
195 - { GLAMO_REG_MEM_POWER1, 0x0020 },
196 - { 0x033a, 0x0000 },
197 - { 0x033c, 0x0000 },
198 - { 0x033e, 0x0000 },
199 - { 0x0340, 0x0000 },
200 - { 0x0342, 0x0000 },
201 - { 0x0344, 0x0000 },
202 - { 0x0346, 0x0240 },
203 - { GLAMO_REG_MEM_TIMING8, 0x1016 },
204 - { GLAMO_REG_MEM_TIMING9, 0x6067 },
205 - { GLAMO_REG_MEM_TIMING10, 0x00ff },
206 - { GLAMO_REG_MEM_TIMING11, 0x0030 },
207 - { GLAMO_REG_MEM_GEN, 0x3fff },
208 - { GLAMO_REG_MEM_GEN, 0xafaf },
209 - { GLAMO_REG_MEM_TIMING1, 0x0108 },
210 - { GLAMO_REG_MEM_TIMING2, 0x0010 },
211 - { GLAMO_REG_MEM_DRAM1, 0x0a00 },
212 - { 0xfffe, 3 },
213 - { GLAMO_REG_MEM_DRAM1, 0xe200 },
214 - { 0xfffe, 1 },
215 -};
216 -
217 -static const struct glamo_script regs_vram_8mb = {
218 - { GLAMO_REG_CLOCK_MEMORY, 0x3aaa },
219 - { 0xfffe, 50 },
220 - { GLAMO_REG_CLOCK_MEMORY, 0x0aaa },
221 - { 0xfffe, 3 },
222 - { GLAMO_REG_MEM_POWER1, 0x0020 },
223 - { 0x033a, 0x45cf },
224 - { 0x033c, 0x4240 },
225 - { 0x033e, 0x53e0 },
226 - { 0x0340, 0x1401 },
227 - { 0x0342, 0x0c44 },
228 - { 0x0344, 0x1d0b },
229 - { 0x0346, 0x25ac },
230 - { 0x0348, 0x1953 },
231 - { 0xfffe, 1 },
232 - { GLAMO_REG_MEM_TYPE, 0x087a },
233 - { GLAMO_REG_MEM_DRAM2, 0x01d6 },
234 - { GLAMO_REG_MEM_TIMING8, 0x1060 },
235 - { GLAMO_REG_MEM_TIMING9, 0x6067 },
236 - { GLAMO_REG_MEM_TIMING10, 0x00ff },
237 - { GLAMO_REG_MEM_TIMING11, 0x0030 },
238 - { GLAMO_REG_MEM_GEN, 0x3fff },
239 - { GLAMO_REG_MEM_GEN, 0xafaf },
240 - { GLAMO_REG_MEM_TIMING1, 0x3108 },
241 - { GLAMO_REG_MEM_TIMING2, 0x0010 },
242 - { GLAMO_REG_MEM_DRAM1, 0x0a00 },
243 - { 0xfffe, 3 },
244 - { GLAMO_REG_MEM_DRAM1, 0xe200 },
245 - { 0xfffe, 1 },
246 -};
247 -#endif
248
249 enum glamo_power {
250 GLAMO_POWER_ON,
251 - GLAMO_POWER_STANDBY,
252 GLAMO_POWER_SUSPEND,
253 };
254
255 static void glamo_power(struct glamo_core *glamo,
256 enum glamo_power new_state)
257 {
258 + int n;
259 +
260 spin_lock(&glamo->lock);
261
262 dev_dbg(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
263 @@ -836,37 +788,76 @@ static void glamo_power(struct glamo_core *glamo,
264 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
265 ;
266
267 - /* enable memory clock and get it out of deep pwrdown */
268 - __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
269 - GLAMO_CLOCK_MEM_EN_MOCACLK, 0xffff);
270 - __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM2,
271 - GLAMO_MEM_DRAM2_DEEP_PWRDOWN, 0x0000);
272 - __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM1,
273 - GLAMO_MEM_DRAM1_SELF_REFRESH, 0x0000);
274 -
275 - glamo_run_script(glamo, glamo_resume_script,
276 - ARRAY_SIZE(glamo_resume_script), 0);
277 -
278 - break;
279 -
280 - case GLAMO_POWER_STANDBY:
281 - /* enable memory self-refresh */
282 - __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM1,
283 - GLAMO_MEM_DRAM1_SELF_REFRESH, 0xffff);
284 - /* stop memory clock */
285 - __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
286 - GLAMO_CLOCK_MEM_EN_MOCACLK, 0x0000);
287 - /* power down PLL2 and then PLL1 */
288 - __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 0x2000, 0xffff);
289 - __reg_set_bit_mask(glamo, GLAMO_REG_DFT_GEN5, 0x0001, 0xffff);
290 + /* Get memory out of deep powerdown */
291 +
292 + __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
293 + (7 << 6) | /* tRC */
294 + (1 << 4) | /* tRP */
295 + (1 << 2) | /* tRCD */
296 + 2); /* CAS latency */
297 +
298 + /* Stop self-refresh */
299 +
300 + __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
301 + GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
302 + GLAMO_MEM_DRAM1_EN_GATE_CKE |
303 + GLAMO_MEM_REFRESH_COUNT);
304 + __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
305 + GLAMO_MEM_DRAM1_EN_MODEREG_SET |
306 + GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
307 + GLAMO_MEM_DRAM1_EN_GATE_CKE |
308 + GLAMO_MEM_REFRESH_COUNT);
309 +
310 + /* re-enable clocks to memory */
311 +
312 + __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY,
313 + GLAMO_CLOCK_MEM_EN_MOCACLK |
314 + GLAMO_CLOCK_MEM_EN_M1CLK |
315 + GLAMO_CLOCK_MEM_DG_M1CLK);
316 +
317 + /* restore each engine that was up before suspend */
318 + for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
319 + if (glamo->engine_enabled_bitfield_suspend & (1 << n))
320 + __glamo_engine_enable(glamo, n);
321 break;
322
323 case GLAMO_POWER_SUSPEND:
324 - __reg_set_bit_mask(glamo, GLAMO_REG_MEM_DRAM2,
325 - GLAMO_MEM_DRAM2_DEEP_PWRDOWN, 0xffff);
326 - /* stop memory clock */
327 - __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MEMORY,
328 - GLAMO_CLOCK_MEM_EN_MOCACLK, 0x0000);
329 + /* stash a copy of which engines were running */
330 + glamo->engine_enabled_bitfield_suspend =
331 + glamo->engine_enabled_bitfield;
332 +
333 + /* take down each engine before we kill mem and pll */
334 + for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
335 + if (glamo->engine_enabled_bitfield & (1 << n))
336 + __glamo_engine_disable(glamo, n);
337 +
338 + /* enable self-refresh */
339 +
340 + __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
341 + GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
342 + GLAMO_MEM_DRAM1_EN_GATE_CKE |
343 + GLAMO_MEM_DRAM1_SELF_REFRESH |
344 + GLAMO_MEM_REFRESH_COUNT);
345 + __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
346 + GLAMO_MEM_DRAM1_EN_MODEREG_SET |
347 + GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
348 + GLAMO_MEM_DRAM1_EN_GATE_CKE |
349 + GLAMO_MEM_DRAM1_SELF_REFRESH |
350 + GLAMO_MEM_REFRESH_COUNT);
351 +
352 + /* force RAM into deep powerdown */
353 +
354 + __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
355 + GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
356 + (7 << 6) | /* tRC */
357 + (1 << 4) | /* tRP */
358 + (1 << 2) | /* tRCD */
359 + 2); /* CAS latency */
360 +
361 + /* kill clocks to memory */
362 +
363 + __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
364 +
365 /* power down PLL2 and then PLL1 */
366 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 0x2000, 0xffff);
367 __reg_set_bit_mask(glamo, GLAMO_REG_DFT_GEN5, 0x0001, 0xffff);
368 @@ -1016,9 +1007,9 @@ static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
369 char * name;
370 };
371 struct reg_range reg_range[] = {
372 - { 0x0000, 0x200, "General" },
373 + { 0x0000, 0x76, "General" },
374 { 0x0200, 0x100, "Host Bus" },
375 - { 0x0300, 0x100, "Memory" },
376 + { 0x0300, 0x38, "Memory" },
377 /* { 0x0400, 0x100, "Sensor" },
378 { 0x0500, 0x300, "ISP" },
379 { 0x0800, 0x400, "JPEG" },
380 @@ -1037,12 +1028,11 @@ static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
381
382 for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
383 n1 = 0;
384 - end += sprintf(end, "\n%s\n\n", reg_range[r].name);
385 + end += sprintf(end, "\n%s\n", reg_range[r].name);
386 for (n = reg_range[r].start;
387 n < reg_range[r].start + reg_range[r].count; n += 2) {
388 if (((n1++) & 7) == 0)
389 - end += sprintf(end, "\n%04X: ",
390 - n + reg_range[r].start);
391 + end += sprintf(end, "\n%04X: ", n);
392 end += sprintf(end, "%04x ", __reg_read(glamo, n));
393 }
394 end += sprintf(end, "\n");
395 diff --git a/drivers/mfd/glamo/glamo-core.h b/drivers/mfd/glamo/glamo-core.h
396 index 82b95f5..8d647ec 100644
397 --- a/drivers/mfd/glamo/glamo-core.h
398 +++ b/drivers/mfd/glamo/glamo-core.h
399 @@ -30,6 +30,8 @@ struct glamo_core {
400 u_int16_t revision;
401 spinlock_t lock;
402 struct resume_dependency resume_dependency;
403 + u32 engine_enabled_bitfield;
404 + u32 engine_enabled_bitfield_suspend;
405 };
406
407 struct glamo_script {
408 diff --git a/drivers/mfd/glamo/glamo-regs.h b/drivers/mfd/glamo/glamo-regs.h
409 index 32411e3..2328b8a 100644
410 --- a/drivers/mfd/glamo/glamo-regs.h
411 +++ b/drivers/mfd/glamo/glamo-regs.h
412 @@ -142,8 +142,12 @@ enum glamo_register_mem {
413 #define GLAMO_MEM_TYPE_MASK 0x03
414
415 enum glamo_reg_mem_dram1 {
416 - GLAMO_MEM_DRAM1_EN_SDRAM_CLK = (1 << 11),
417 + /* b0 - b10 == refresh period, 1 -> 2048 clocks */
418 + GLAMO_MEM_DRAM1_EN_GATE_CLK = (1 << 11),
419 GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
420 + GLAMO_MEM_DRAM1_EN_GATE_CKE = (1 << 13),
421 + GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
422 + GLAMO_MEM_DRAM1_EN_MODEREG_SET = (1 << 15),
423 };
424
425 enum glamo_reg_mem_dram2 {
426 --
427 1.5.6.5
428
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