package/mac80211/patches/546-ath9k_cleanup_ar9287_settings.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
   2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
   3 @@ -499,45 +499,6 @@ void ar9002_hw_enable_async_fifo(struct
   4         }
   5  }
   6
   7 -/*
   8 - * If Async FIFO is enabled, the following counters change as MAC now runs
   9 - * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
  10 - *
  11 - * The values below tested for ht40 2 chain.
  12 - * Overwrite the delay/timeouts initialized in process ini.
  13 - */
  14 -void ar9002_hw_update_async_fifo(struct ath_hw *ah)
  15 -{
  16 -       if (AR_SREV_9287_13_OR_LATER(ah)) {
  17 -               REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
  18 -                         AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
  19 -               REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
  20 -                         AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
  21 -               REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
  22 -                         AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
  23 -
  24 -               REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
  25 -               REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
  26 -
  27 -               REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
  28 -                           AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
  29 -               REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
  30 -                             AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
  31 -       }
  32 -}
  33 -
  34 -/*
  35 - * We don't enable WEP aggregation on mac80211 but we keep this
  36 - * around for HAL unification purposes.
  37 - */
  38 -void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
  39 -{
  40 -       if (AR_SREV_9287_13_OR_LATER(ah)) {
  41 -               REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
  42 -                           AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
  43 -       }
  44 -}
  45 -
  46  /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
  47  void ar9002_hw_attach_ops(struct ath_hw *ah)
  48  {
  49 --- a/drivers/net/wireless/ath/ath9k/hw.c
  50 +++ b/drivers/net/wireless/ath/ath9k/hw.c
  51 @@ -1641,9 +1641,13 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  52
  53         ath9k_hw_init_global_settings(ah);
  54
  55 -       if (!AR_SREV_9300_20_OR_LATER(ah)) {
  56 -               ar9002_hw_update_async_fifo(ah);
  57 -               ar9002_hw_enable_wep_aggregation(ah);
  58 +       if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
  59 +               REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
  60 +                           AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
  61 +               REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
  62 +                             AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
  63 +               REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
  64 +                           AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
  65         }
  66
  67         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
  68 --- a/drivers/net/wireless/ath/ath9k/hw.h
  69 +++ b/drivers/net/wireless/ath/ath9k/hw.h
  70 @@ -984,8 +984,6 @@ void ath9k_hw_get_delta_slope_vals(struc
  71  void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
  72  int ar9002_hw_rf_claim(struct ath_hw *ah);
  73  void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
  74 -void ar9002_hw_update_async_fifo(struct ath_hw *ah);
  75 -void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
  76
  77  /*
  78   * Code specific to AR9003, we stuff these here to avoid callbacks
  79 --- a/drivers/net/wireless/ath/ath9k/reg.h
  80 +++ b/drivers/net/wireless/ath/ath9k/reg.h
  81 @@ -600,7 +600,6 @@
  82
  83  #define AR_D_GBL_IFS_SIFS         0x1030
  84  #define AR_D_GBL_IFS_SIFS_M       0x0000FFFF
  85 -#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
  86  #define AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF
  87
  88  #define AR_D_TXBLK_BASE            0x1038
  89 @@ -616,12 +615,10 @@
  90  #define AR_D_GBL_IFS_SLOT         0x1070
  91  #define AR_D_GBL_IFS_SLOT_M       0x0000FFFF
  92  #define AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000
  93 -#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR   0x00000420
  94
  95  #define AR_D_GBL_IFS_EIFS         0x10b0
  96  #define AR_D_GBL_IFS_EIFS_M       0x0000FFFF
  97  #define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000
  98 -#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR   0x0000A5EB
  99
 100  #define AR_D_GBL_IFS_MISC        0x10f0
 101  #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL        0x00000007
 102 @@ -1477,7 +1474,6 @@ enum {
 103  #define AR_TIME_OUT_ACK_S    0
 104  #define AR_TIME_OUT_CTS      0x3FFF0000
 105  #define AR_TIME_OUT_CTS_S    16
 106 -#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR    0x16001D56
 107
 108  #define AR_RSSI_THR          0x8018
 109  #define AR_RSSI_THR_MASK     0x000000FF
 110 @@ -1493,7 +1489,6 @@ enum {
 111  #define AR_USEC_TX_LAT_S     14
 112  #define AR_USEC_RX_LAT       0x1F800000
 113  #define AR_USEC_RX_LAT_S     23
 114 -#define AR_USEC_ASYNC_FIFO_DUR    0x12e00074
 115
 116  #define AR_RESET_TSF        0x8020
 117  #define AR_RESET_TSF_ONCE   0x01000000