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don't hardcode the cpu frequency for bcm47xx in linux 2.6
[openwrt.git] / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2006-10-15 23:29:14.000000000 +0200
4 @@ -0,0 +1,481 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2005, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id$
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <osl.h>
20 +#include <bcmutils.h>
21 +#include <bcmsrom.h>
22 +#include <bcmdevs.h>
23 +#include <bcmendian.h>
24 +#include <pcicfg.h>
25 +#include <sbutils.h>
26 +
27 +#include <proto/ethernet.h> /* for sprom content groking */
28 +
29 +#define VARS_MAX 4096 /* should be reduced */
30 +
31 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
32 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
33 +
34 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
35 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
36 +
37 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
38 +
39 +/*
40 + * Initialize local vars from the right source for this platform.
41 + * Return 0 on success, nonzero on error.
42 + */
43 +int
44 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
45 +{
46 + ASSERT(bustype == BUSTYPE(bustype));
47 + if (vars == NULL || count == NULL)
48 + return (0);
49 +
50 + switch (BUSTYPE(bustype)) {
51 +
52 + case PCI_BUS:
53 + ASSERT(curmap); /* can not be NULL */
54 + return initvars_srom_pci(sbh, curmap, vars, count);
55 +
56 + default:
57 + return 0;
58 + }
59 + return (-1);
60 +}
61 +
62 +/* support only 16-bit word read from srom */
63 +int
64 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
65 +{
66 + void *srom;
67 + uint off, nw;
68 +
69 + ASSERT(bustype == BUSTYPE(bustype));
70 +
71 + /* check input - 16-bit access only */
72 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
73 + return 1;
74 +
75 + off = byteoff / 2;
76 + nw = nbytes / 2;
77 +
78 + if (BUSTYPE(bustype) == PCI_BUS) {
79 + if (!curmap)
80 + return 1;
81 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
82 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
83 + return 1;
84 + } else {
85 + return 1;
86 + }
87 +
88 + return 0;
89 +}
90 +
91 +/* support only 16-bit word write into srom */
92 +int
93 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
94 +{
95 + uint16 *srom;
96 + uint i, off, nw, crc_range;
97 + uint16 image[SPROM_SIZE], *p;
98 + uint8 crc;
99 + volatile uint32 val32;
100 +
101 + ASSERT(bustype == BUSTYPE(bustype));
102 +
103 + /* check input - 16-bit access only */
104 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
105 + return 1;
106 +
107 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
108 +
109 + /* if changes made inside crc cover range */
110 + if (byteoff < crc_range) {
111 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
112 + /* read data including entire first 64 words from srom */
113 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
114 + return 1;
115 + /* make changes */
116 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
117 + /* calculate crc */
118 + htol16_buf(image, crc_range);
119 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
120 + ltoh16_buf(image, crc_range);
121 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
122 + p = image;
123 + off = 0;
124 + } else {
125 + p = buf;
126 + off = byteoff / 2;
127 + nw = nbytes / 2;
128 + }
129 +
130 + if (BUSTYPE(bustype) == PCI_BUS) {
131 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
132 + /* enable writes to the SPROM */
133 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
134 + val32 |= SPROM_WRITEEN;
135 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
136 + bcm_mdelay(WRITE_ENABLE_DELAY);
137 + /* write srom */
138 + for (i = 0; i < nw; i++) {
139 + W_REG(&srom[off + i], p[i]);
140 + bcm_mdelay(WRITE_WORD_DELAY);
141 + }
142 + /* disable writes to the SPROM */
143 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
144 + } else {
145 + return 1;
146 + }
147 +
148 + bcm_mdelay(WRITE_ENABLE_DELAY);
149 + return 0;
150 +}
151 +
152 +
153 +/*
154 + * Read in and validate sprom.
155 + * Return 0 on success, nonzero on error.
156 + */
157 +static int
158 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
159 +{
160 + int err = 0;
161 + uint i;
162 +
163 + /* read the sprom */
164 + for (i = 0; i < nwords; i++)
165 + buf[i] = R_REG(&sprom[wordoff + i]);
166 +
167 + if (check_crc) {
168 + /* fixup the endianness so crc8 will pass */
169 + htol16_buf(buf, nwords * 2);
170 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
171 + err = 1;
172 + /* now correct the endianness of the byte array */
173 + ltoh16_buf(buf, nwords * 2);
174 + }
175 +
176 + return err;
177 +}
178 +
179 +/*
180 +* Create variable table from memory.
181 +* Return 0 on success, nonzero on error.
182 +*/
183 +static int
184 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
185 +{
186 + int c = (int)(end - start);
187 +
188 + /* do it only when there is more than just the null string */
189 + if (c > 1) {
190 + char *vp = MALLOC(osh, c);
191 + ASSERT(vp);
192 + if (!vp)
193 + return BCME_NOMEM;
194 + bcopy(start, vp, c);
195 + *vars = vp;
196 + *count = c;
197 + }
198 + else {
199 + *vars = NULL;
200 + *count = 0;
201 + }
202 +
203 + return 0;
204 +}
205 +
206 +/*
207 + * Initialize nonvolatile variable table from sprom.
208 + * Return 0 on success, nonzero on error.
209 + */
210 +static int
211 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
212 +{
213 + uint16 w, b[64];
214 + uint8 sromrev;
215 + struct ether_addr ea;
216 + char eabuf[32];
217 + uint32 w32;
218 + int woff, i;
219 + char *vp, *base;
220 + osl_t *osh = sb_osh(sbh);
221 + int err;
222 +
223 + /*
224 + * Apply CRC over SROM content regardless SROM is present or not,
225 + * and use variable <devpath>sromrev's existance in flash to decide
226 + * if we should return an error when CRC fails or read SROM variables
227 + * from flash.
228 + */
229 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
230 +
231 + /* top word of sprom contains version and crc8 */
232 + sromrev = b[63] & 0xff;
233 + /* bcm4401 sroms misprogrammed */
234 + if (sromrev == 0x10)
235 + sromrev = 1;
236 +
237 + /* srom version check */
238 + if (sromrev > 3)
239 + return (-2);
240 +
241 + ASSERT(vars);
242 + ASSERT(count);
243 +
244 + base = vp = MALLOC(osh, VARS_MAX);
245 + ASSERT(vp);
246 + if (!vp)
247 + return -2;
248 +
249 + vp += sprintf(vp, "sromrev=%d", sromrev);
250 + vp++;
251 +
252 + if (sromrev >= 3) {
253 + /* New section takes over the 3th hardware function space */
254 +
255 + /* Words 22+23 are 11a (mid) ofdm power offsets */
256 + w32 = ((uint32)b[23] << 16) | b[22];
257 + vp += sprintf(vp, "ofdmapo=%d", w32);
258 + vp++;
259 +
260 + /* Words 24+25 are 11a (low) ofdm power offsets */
261 + w32 = ((uint32)b[25] << 16) | b[24];
262 + vp += sprintf(vp, "ofdmalpo=%d", w32);
263 + vp++;
264 +
265 + /* Words 26+27 are 11a (high) ofdm power offsets */
266 + w32 = ((uint32)b[27] << 16) | b[26];
267 + vp += sprintf(vp, "ofdmahpo=%d", w32);
268 + vp++;
269 +
270 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
271 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
272 + vp += sprintf(vp, "gpiotimerval=%d", w32);
273 +
274 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
275 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
276 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
277 + vp += sprintf(vp, "gpiotimerval=%d", w32);
278 +
279 + vp++;
280 + }
281 +
282 + if (sromrev >= 2) {
283 + /* New section takes over the 4th hardware function space */
284 +
285 + /* Word 29 is max power 11a high/low */
286 + w = b[29];
287 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
288 + vp++;
289 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
290 + vp++;
291 +
292 + /* Words 30-32 set the 11alow pa settings,
293 + * 33-35 are the 11ahigh ones.
294 + */
295 + for (i = 0; i < 3; i++) {
296 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
297 + vp++;
298 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
299 + vp++;
300 + }
301 + w = b[59];
302 + if (w == 0)
303 + vp += sprintf(vp, "ccode=");
304 + else
305 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
306 + vp++;
307 +
308 + }
309 +
310 + /* parameter section of sprom starts at byte offset 72 */
311 + woff = 72/2;
312 +
313 + /* first 6 bytes are il0macaddr */
314 + ea.octet[0] = (b[woff] >> 8) & 0xff;
315 + ea.octet[1] = b[woff] & 0xff;
316 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
317 + ea.octet[3] = b[woff+1] & 0xff;
318 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
319 + ea.octet[5] = b[woff+2] & 0xff;
320 + woff += ETHER_ADDR_LEN/2 ;
321 + bcm_ether_ntoa((uchar*)&ea, eabuf);
322 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
323 + vp++;
324 +
325 + /* next 6 bytes are et0macaddr */
326 + ea.octet[0] = (b[woff] >> 8) & 0xff;
327 + ea.octet[1] = b[woff] & 0xff;
328 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
329 + ea.octet[3] = b[woff+1] & 0xff;
330 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
331 + ea.octet[5] = b[woff+2] & 0xff;
332 + woff += ETHER_ADDR_LEN/2 ;
333 + bcm_ether_ntoa((uchar*)&ea, eabuf);
334 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
335 + vp++;
336 +
337 + /* next 6 bytes are et1macaddr */
338 + ea.octet[0] = (b[woff] >> 8) & 0xff;
339 + ea.octet[1] = b[woff] & 0xff;
340 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
341 + ea.octet[3] = b[woff+1] & 0xff;
342 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
343 + ea.octet[5] = b[woff+2] & 0xff;
344 + woff += ETHER_ADDR_LEN/2 ;
345 + bcm_ether_ntoa((uchar*)&ea, eabuf);
346 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
347 + vp++;
348 +
349 + /*
350 + * Enet phy settings one or two singles or a dual
351 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
352 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
353 + * Bit 14 : Mdio for enet0
354 + * Bit 15 : Mdio for enet1
355 + */
356 + w = b[woff];
357 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
358 + vp++;
359 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
360 + vp++;
361 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
362 + vp++;
363 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
364 + vp++;
365 +
366 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
367 + w = b[46];
368 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
369 + vp++;
370 +
371 + if (sromrev > 1)
372 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
373 + else
374 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
375 + vp++;
376 +
377 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
378 + vp++;
379 +
380 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
381 + vp++;
382 +
383 + /* Words 47-49 set the (wl) pa settings */
384 + woff = 47;
385 +
386 + for (i = 0; i < 3; i++) {
387 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
388 + vp++;
389 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
390 + vp++;
391 + }
392 +
393 + /*
394 + * Words 50-51 set the customer-configured wl led behavior.
395 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
396 + * LED behavior values defined in wlioctl.h .
397 + */
398 + w = b[50];
399 + if ((w != 0) && (w != 0xffff)) {
400 + /* gpio0 */
401 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
402 + vp++;
403 +
404 + /* gpio1 */
405 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
406 + vp++;
407 + }
408 + w = b[51];
409 + if ((w != 0) && (w != 0xffff)) {
410 + /* gpio2 */
411 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
412 + vp++;
413 +
414 + /* gpio3 */
415 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
416 + vp++;
417 + }
418 +
419 + /* Word 52 is max power 0/1 */
420 + w = b[52];
421 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
422 + vp++;
423 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
424 + vp++;
425 +
426 + /* Word 56 is idle tssi target 0/1 */
427 + w = b[56];
428 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
429 + vp++;
430 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
431 + vp++;
432 +
433 + /* Word 57 is boardflags, if not programmed make it zero */
434 + w32 = (uint32)b[57];
435 + if (w32 == 0xffff) w32 = 0;
436 + if (sromrev > 1) {
437 + /* Word 28 is the high bits of boardflags */
438 + w32 |= (uint32)b[28] << 16;
439 + }
440 + vp += sprintf(vp, "boardflags=%d", w32);
441 + vp++;
442 +
443 + /* Word 58 is antenna gain 0/1 */
444 + w = b[58];
445 + vp += sprintf(vp, "ag0=%d", w & 0xff);
446 + vp++;
447 +
448 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
449 + vp++;
450 +
451 + if (sromrev == 1) {
452 + /* set the oem string */
453 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
454 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
455 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
456 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
457 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
458 + vp++;
459 + } else if (sromrev == 2) {
460 + /* Word 60 OFDM tx power offset from CCK level */
461 + /* OFDM Power Offset - opo */
462 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
463 + vp++;
464 + } else {
465 + /* Word 60: cck power offsets */
466 + vp += sprintf(vp, "cckpo=%d", b[60]);
467 + vp++;
468 +
469 + /* Words 61+62: 11g ofdm power offsets */
470 + w32 = ((uint32)b[62] << 16) | b[61];
471 + vp += sprintf(vp, "ofdmgpo=%d", w32);
472 + vp++;
473 + }
474 +
475 + /* final nullbyte terminator */
476 + *vp++ = '\0';
477 +
478 + ASSERT((vp - base) <= VARS_MAX);
479 +
480 + err = initvars_table(osh, base, vp, vars, count);
481 +
482 + MFREE(osh, base, VARS_MAX);
483 + return err;
484 +}
485 +
486 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
487 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
488 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2006-10-15 23:29:14.000000000 +0200
489 @@ -0,0 +1,356 @@
490 +/*
491 + * Misc useful OS-independent routines.
492 + *
493 + * Copyright 2005, Broadcom Corporation
494 + * All Rights Reserved.
495 + *
496 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
497 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
498 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
499 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
500 + * $Id$
501 + */
502 +
503 +#include <typedefs.h>
504 +#include <osl.h>
505 +#include <sbutils.h>
506 +#include <bcmnvram.h>
507 +#include <bcmutils.h>
508 +#include <bcmendian.h>
509 +#include <bcmdevs.h>
510 +
511 +unsigned char bcm_ctype[] = {
512 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
513 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
514 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
515 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
516 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
517 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
518 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
519 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
520 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
521 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
522 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
523 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
524 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
525 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
526 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
527 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
528 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
529 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
530 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
531 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
532 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
533 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
534 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
535 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
536 +};
537 +
538 +uchar
539 +bcm_toupper(uchar c)
540 +{
541 + if (bcm_islower(c))
542 + c -= 'a'-'A';
543 + return (c);
544 +}
545 +
546 +ulong
547 +bcm_strtoul(char *cp, char **endp, uint base)
548 +{
549 + ulong result, value;
550 + bool minus;
551 +
552 + minus = FALSE;
553 +
554 + while (bcm_isspace(*cp))
555 + cp++;
556 +
557 + if (cp[0] == '+')
558 + cp++;
559 + else if (cp[0] == '-') {
560 + minus = TRUE;
561 + cp++;
562 + }
563 +
564 + if (base == 0) {
565 + if (cp[0] == '0') {
566 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
567 + base = 16;
568 + cp = &cp[2];
569 + } else {
570 + base = 8;
571 + cp = &cp[1];
572 + }
573 + } else
574 + base = 10;
575 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
576 + cp = &cp[2];
577 + }
578 +
579 + result = 0;
580 +
581 + while (bcm_isxdigit(*cp) &&
582 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
583 + result = result*base + value;
584 + cp++;
585 + }
586 +
587 + if (minus)
588 + result = (ulong)(result * -1);
589 +
590 + if (endp)
591 + *endp = (char *)cp;
592 +
593 + return (result);
594 +}
595 +
596 +uint
597 +bcm_atoi(char *s)
598 +{
599 + uint n;
600 +
601 + n = 0;
602 +
603 + while (bcm_isdigit(*s))
604 + n = (n * 10) + *s++ - '0';
605 + return (n);
606 +}
607 +
608 +/* return pointer to location of substring 'needle' in 'haystack' */
609 +char*
610 +bcmstrstr(char *haystack, char *needle)
611 +{
612 + int len, nlen;
613 + int i;
614 +
615 + if ((haystack == NULL) || (needle == NULL))
616 + return (haystack);
617 +
618 + nlen = strlen(needle);
619 + len = strlen(haystack) - nlen + 1;
620 +
621 + for (i = 0; i < len; i++)
622 + if (bcmp(needle, &haystack[i], nlen) == 0)
623 + return (&haystack[i]);
624 + return (NULL);
625 +}
626 +
627 +char*
628 +bcmstrcat(char *dest, const char *src)
629 +{
630 + strcpy(&dest[strlen(dest)], src);
631 + return (dest);
632 +}
633 +
634 +
635 +char*
636 +bcm_ether_ntoa(char *ea, char *buf)
637 +{
638 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
639 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
640 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
641 + return (buf);
642 +}
643 +
644 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
645 +int
646 +bcm_ether_atoe(char *p, char *ea)
647 +{
648 + int i = 0;
649 +
650 + for (;;) {
651 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
652 + if (!*p++ || i == 6)
653 + break;
654 + }
655 +
656 + return (i == 6);
657 +}
658 +
659 +void
660 +bcm_mdelay(uint ms)
661 +{
662 + uint i;
663 +
664 + for (i = 0; i < ms; i++) {
665 + OSL_DELAY(1000);
666 + }
667 +}
668 +
669 +/*
670 + * Search the name=value vars for a specific one and return its value.
671 + * Returns NULL if not found.
672 + */
673 +char*
674 +getvar(char *vars, char *name)
675 +{
676 + char *s;
677 + int len;
678 +
679 + len = strlen(name);
680 +
681 + /* first look in vars[] */
682 + for (s = vars; s && *s; ) {
683 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
684 + return (&s[len+1]);
685 +
686 + while (*s++)
687 + ;
688 + }
689 +
690 + /* then query nvram */
691 + return (BCMINIT(nvram_get)(name));
692 +}
693 +
694 +/*
695 + * Search the vars for a specific one and return its value as
696 + * an integer. Returns 0 if not found.
697 + */
698 +int
699 +getintvar(char *vars, char *name)
700 +{
701 + char *val;
702 +
703 + if ((val = getvar(vars, name)) == NULL)
704 + return (0);
705 +
706 + return (bcm_strtoul(val, NULL, 0));
707 +}
708 +
709 +
710 +/* Search for token in comma separated token-string */
711 +static int
712 +findmatch(char *string, char *name)
713 +{
714 + uint len;
715 + char *c;
716 +
717 + len = strlen(name);
718 + while ((c = strchr(string, ',')) != NULL) {
719 + if (len == (uint)(c - string) && !strncmp(string, name, len))
720 + return 1;
721 + string = c + 1;
722 + }
723 +
724 + return (!strcmp(string, name));
725 +}
726 +
727 +/* Return gpio pin number assigned to the named pin */
728 +/*
729 +* Variable should be in format:
730 +*
731 +* gpio<N>=pin_name,pin_name
732 +*
733 +* This format allows multiple features to share the gpio with mutual
734 +* understanding.
735 +*
736 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
737 +* and if def_pin is not used by others.
738 +*/
739 +uint
740 +getgpiopin(char *vars, char *pin_name, uint def_pin)
741 +{
742 + char name[] = "gpioXXXX";
743 + char *val;
744 + uint pin;
745 +
746 + /* Go thru all possibilities till a match in pin name */
747 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
748 + sprintf(name, "gpio%d", pin);
749 + val = getvar(vars, name);
750 + if (val && findmatch(val, pin_name))
751 + return pin;
752 + }
753 +
754 + if (def_pin != GPIO_PIN_NOTDEFINED) {
755 + /* make sure the default pin is not used by someone else */
756 + sprintf(name, "gpio%d", def_pin);
757 + if (getvar(vars, name)) {
758 + def_pin = GPIO_PIN_NOTDEFINED;
759 + }
760 + }
761 +
762 + return def_pin;
763 +}
764 +
765 +
766 +/*******************************************************************************
767 + * crc8
768 + *
769 + * Computes a crc8 over the input data using the polynomial:
770 + *
771 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
772 + *
773 + * The caller provides the initial value (either CRC8_INIT_VALUE
774 + * or the previous returned value) to allow for processing of
775 + * discontiguous blocks of data. When generating the CRC the
776 + * caller is responsible for complementing the final return value
777 + * and inserting it into the byte stream. When checking, a final
778 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
779 + *
780 + * Reference: Dallas Semiconductor Application Note 27
781 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
782 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
783 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
784 + *
785 + ******************************************************************************/
786 +
787 +static uint8 crc8_table[256] = {
788 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
789 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
790 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
791 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
792 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
793 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
794 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
795 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
796 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
797 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
798 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
799 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
800 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
801 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
802 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
803 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
804 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
805 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
806 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
807 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
808 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
809 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
810 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
811 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
812 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
813 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
814 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
815 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
816 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
817 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
818 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
819 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
820 +};
821 +
822 +#define CRC_INNER_LOOP(n, c, x) \
823 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
824 +
825 +uint8
826 +hndcrc8(
827 + uint8 *pdata, /* pointer to array of data to process */
828 + uint nbytes, /* number of input data bytes to process */
829 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
830 +)
831 +{
832 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
833 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
834 + while (nbytes-- > 0)
835 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
836 +
837 + return crc;
838 +}
839 +
840 +#ifdef notdef
841 +#define CLEN 1499
842 +#define CBUFSIZ (CLEN+4)
843 +#define CNBUFS 5
844 +
845 +#endif
846 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
847 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
848 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2006-10-15 23:29:14.000000000 +0200
849 @@ -0,0 +1,234 @@
850 +/*
851 + * NVRAM variable manipulation (Linux kernel half)
852 + *
853 + * Copyright 2001-2003, Broadcom Corporation
854 + * All Rights Reserved.
855 + *
856 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
857 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
858 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
859 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
860 + *
861 + * $Id$
862 + */
863 +
864 +#include <linux/config.h>
865 +#include <linux/init.h>
866 +#include <linux/module.h>
867 +#include <linux/kernel.h>
868 +#include <linux/string.h>
869 +#include <asm/io.h>
870 +#include <asm/uaccess.h>
871 +
872 +#include <typedefs.h>
873 +#include <osl.h>
874 +#include <bcmendian.h>
875 +#include <bcmutils.h>
876 +
877 +#define NVRAM_SIZE (0x1ff0)
878 +static char _nvdata[NVRAM_SIZE] __initdata;
879 +static char _valuestr[256] __initdata;
880 +
881 +/*
882 + * TLV types. These codes are used in the "type-length-value"
883 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
884 + *
885 + * The layout of the flash/nvram is as follows:
886 + *
887 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
888 + *
889 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
890 + * The "length" field marks the length of the data section, not
891 + * including the type and length fields.
892 + *
893 + * Environment variables are stored as follows:
894 + *
895 + * <type_env> <length> <flags> <name> = <value>
896 + *
897 + * If bit 0 (low bit) is set, the length is an 8-bit value.
898 + * If bit 0 (low bit) is clear, the length is a 16-bit value
899 + *
900 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
901 + * indicates the size of the length field.
902 + *
903 + * Flags are from the constants below:
904 + *
905 + */
906 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
907 +#define ENV_LENGTH_8BITS 0x01
908 +
909 +#define ENV_TYPE_USER 0x80
910 +
911 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
912 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
913 +
914 +/*
915 + * The actual TLV types we support
916 + */
917 +
918 +#define ENV_TLV_TYPE_END 0x00
919 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
920 +
921 +/*
922 + * Environment variable flags
923 + */
924 +
925 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
926 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
927 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
928 +
929 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
930 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
931 +
932 +
933 +/* *********************************************************************
934 + * _nvram_read(buffer,offset,length)
935 + *
936 + * Read data from the NVRAM device
937 + *
938 + * Input parameters:
939 + * buffer - destination buffer
940 + * offset - offset of data to read
941 + * length - number of bytes to read
942 + *
943 + * Return value:
944 + * number of bytes read, or <0 if error occured
945 + ********************************************************************* */
946 +static int
947 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
948 +{
949 + int i;
950 + if (offset > NVRAM_SIZE)
951 + return -1;
952 +
953 + for ( i = 0; i < length; i++) {
954 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
955 + }
956 + return length;
957 +}
958 +
959 +
960 +static char*
961 +_strnchr(const char *dest,int c,size_t cnt)
962 +{
963 + while (*dest && (cnt > 0)) {
964 + if (*dest == c) return (char *) dest;
965 + dest++;
966 + cnt--;
967 + }
968 + return NULL;
969 +}
970 +
971 +
972 +
973 +/*
974 + * Core support API: Externally visible.
975 + */
976 +
977 +/*
978 + * Get the value of an NVRAM variable
979 + * @param name name of variable to get
980 + * @return value of variable or NULL if undefined
981 + */
982 +
983 +char*
984 +cfe_env_get(unsigned char *nv_buf, char* name)
985 +{
986 + int size;
987 + unsigned char *buffer;
988 + unsigned char *ptr;
989 + unsigned char *envval;
990 + unsigned int reclen;
991 + unsigned int rectype;
992 + int offset;
993 + int flg;
994 +
995 + size = NVRAM_SIZE;
996 + buffer = &_nvdata[0];
997 +
998 + ptr = buffer;
999 + offset = 0;
1000 +
1001 + /* Read the record type and length */
1002 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1003 + goto error;
1004 + }
1005 +
1006 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1007 +
1008 + /* Adjust pointer for TLV type */
1009 + rectype = *(ptr);
1010 + offset++;
1011 + size--;
1012 +
1013 + /*
1014 + * Read the length. It can be either 1 or 2 bytes
1015 + * depending on the code
1016 + */
1017 + if (rectype & ENV_LENGTH_8BITS) {
1018 + /* Read the record type and length - 8 bits */
1019 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1020 + goto error;
1021 + }
1022 + reclen = *(ptr);
1023 + size--;
1024 + offset++;
1025 + }
1026 + else {
1027 + /* Read the record type and length - 16 bits, MSB first */
1028 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1029 + goto error;
1030 + }
1031 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1032 + size -= 2;
1033 + offset += 2;
1034 + }
1035 +
1036 + if (reclen > size)
1037 + break; /* should not happen, bad NVRAM */
1038 +
1039 + switch (rectype) {
1040 + case ENV_TLV_TYPE_ENV:
1041 + /* Read the TLV data */
1042 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1043 + goto error;
1044 + flg = *ptr++;
1045 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1046 + if (envval) {
1047 + *envval++ = '\0';
1048 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1049 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1050 +#if 0
1051 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1052 +#endif
1053 + if(!strcmp(ptr, name)){
1054 + return _valuestr;
1055 + }
1056 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1057 + return _valuestr;
1058 + }
1059 + break;
1060 +
1061 + default:
1062 + /* Unknown TLV type, skip it. */
1063 + break;
1064 + }
1065 +
1066 + /*
1067 + * Advance to next TLV
1068 + */
1069 +
1070 + size -= (int)reclen;
1071 + offset += reclen;
1072 +
1073 + /* Read the next record type */
1074 + ptr = buffer;
1075 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1076 + goto error;
1077 + }
1078 +
1079 +error:
1080 + return NULL;
1081 +
1082 +}
1083 +
1084 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1085 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1086 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2006-10-15 23:29:14.000000000 +0200
1087 @@ -0,0 +1,102 @@
1088 +/*
1089 + * Linux OS Independent Layer
1090 + *
1091 + * Copyright 2005, Broadcom Corporation
1092 + * All Rights Reserved.
1093 + *
1094 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1095 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1096 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1097 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1098 + *
1099 + * $Id$
1100 + */
1101 +
1102 +#define LINUX_OSL
1103 +
1104 +#include <typedefs.h>
1105 +#include <bcmendian.h>
1106 +#include <linux/module.h>
1107 +#include <linuxver.h>
1108 +#include <osl.h>
1109 +#include <bcmutils.h>
1110 +#include <linux/delay.h>
1111 +#ifdef mips
1112 +#include <asm/paccess.h>
1113 +#endif
1114 +#include <pcicfg.h>
1115 +
1116 +#define PCI_CFG_RETRY 10
1117 +
1118 +#define OS_HANDLE_MAGIC 0x1234abcd
1119 +#define BCM_MEM_FILENAME_LEN 24
1120 +
1121 +typedef struct bcm_mem_link {
1122 + struct bcm_mem_link *prev;
1123 + struct bcm_mem_link *next;
1124 + uint size;
1125 + int line;
1126 + char file[BCM_MEM_FILENAME_LEN];
1127 +} bcm_mem_link_t;
1128 +
1129 +struct os_handle {
1130 + uint magic;
1131 + void *pdev;
1132 + uint malloced;
1133 + uint failed;
1134 + bcm_mem_link_t *dbgmem_list;
1135 +};
1136 +
1137 +uint32
1138 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1139 +{
1140 + uint val;
1141 + uint retry=PCI_CFG_RETRY;
1142 +
1143 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1144 +
1145 + /* only 4byte access supported */
1146 + ASSERT(size == 4);
1147 +
1148 + do {
1149 + pci_read_config_dword(osh->pdev, offset, &val);
1150 + if (val != 0xffffffff)
1151 + break;
1152 + } while (retry--);
1153 +
1154 +
1155 + return (val);
1156 +}
1157 +
1158 +void
1159 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1160 +{
1161 + uint retry=PCI_CFG_RETRY;
1162 +
1163 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1164 +
1165 + /* only 4byte access supported */
1166 + ASSERT(size == 4);
1167 +
1168 + do {
1169 + pci_write_config_dword(osh->pdev, offset, val);
1170 + if (offset!=PCI_BAR0_WIN)
1171 + break;
1172 + if (osl_pci_read_config(osh,offset,size) == val)
1173 + break;
1174 + } while (retry--);
1175 +
1176 +}
1177 +
1178 +void
1179 +osl_delay(uint usec)
1180 +{
1181 + uint d;
1182 +
1183 + while (usec > 0) {
1184 + d = MIN(usec, 1000);
1185 + udelay(d);
1186 + usec -= d;
1187 + }
1188 +}
1189 +
1190 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
1191 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
1192 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2006-10-15 23:29:14.000000000 +0200
1193 @@ -0,0 +1,6 @@
1194 +#
1195 +# Makefile for the BCM47xx specific kernel interface routines
1196 +# under Linux.
1197 +#
1198 +
1199 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
1200 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1201 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2006-10-15 23:29:14.000000000 +0200
1203 @@ -0,0 +1,192 @@
1204 +/*
1205 + * NVRAM variable manipulation (Linux kernel half)
1206 + *
1207 + * Copyright 2005, Broadcom Corporation
1208 + * All Rights Reserved.
1209 + *
1210 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1211 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1212 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1213 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1214 + *
1215 + * $Id$
1216 + */
1217 +
1218 +#include <linux/config.h>
1219 +#include <linux/init.h>
1220 +#include <linux/module.h>
1221 +#include <linux/kernel.h>
1222 +#include <linux/string.h>
1223 +#include <linux/interrupt.h>
1224 +#include <linux/spinlock.h>
1225 +#include <linux/slab.h>
1226 +#include <asm/bootinfo.h>
1227 +#include <asm/addrspace.h>
1228 +#include <asm/io.h>
1229 +#include <asm/uaccess.h>
1230 +
1231 +#include <typedefs.h>
1232 +#include <bcmendian.h>
1233 +#include <bcmnvram.h>
1234 +#include <bcmutils.h>
1235 +#include <sbconfig.h>
1236 +#include <sbchipc.h>
1237 +#include <sbutils.h>
1238 +#include <sbmips.h>
1239 +#include <sflash.h>
1240 +
1241 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1242 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1243 +
1244 +/* Global SB handle */
1245 +extern void *sbh;
1246 +extern spinlock_t bcm947xx_sbh_lock;
1247 +static int cfe_env;
1248 +
1249 +extern char *cfe_env_get(char *nv_buf, const char *name);
1250 +
1251 +
1252 +/* Convenience */
1253 +#define sbh_lock bcm947xx_sbh_lock
1254 +#define KB * 1024
1255 +#define MB * 1024 * 1024
1256 +
1257 +/* Probe for NVRAM header */
1258 +static void __init
1259 +early_nvram_init(void)
1260 +{
1261 + struct nvram_header *header;
1262 + chipcregs_t *cc;
1263 + struct sflash *info = NULL;
1264 + int i;
1265 + uint32 base, off, lim;
1266 + u32 *src, *dst;
1267 +
1268 + cfe_env = 0;
1269 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1270 + base = KSEG1ADDR(SB_FLASH2);
1271 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1272 + case PFLASH:
1273 + lim = SB_FLASH2_SZ;
1274 + break;
1275 +
1276 + case SFLASH_ST:
1277 + case SFLASH_AT:
1278 + if ((info = sflash_init(cc)) == NULL)
1279 + return;
1280 + lim = info->size;
1281 + break;
1282 +
1283 + case FLASH_NONE:
1284 + default:
1285 + return;
1286 + }
1287 + } else {
1288 + /* extif assumed, Stop at 4 MB */
1289 + base = KSEG1ADDR(SB_FLASH1);
1290 + lim = SB_FLASH1_SZ;
1291 + }
1292 +
1293 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1294 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1295 + dst = (u32 *) nvram_buf;
1296 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1297 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1298 +
1299 + for (i = 0; i < 0x1ff0; i++) {
1300 + if (*src == 0xFFFFFFFF)
1301 + break;
1302 + *dst++ = *src++;
1303 + }
1304 + cfe_env = 1;
1305 + return;
1306 + }
1307 +
1308 + off = FLASH_MIN;
1309 + while (off <= lim) {
1310 + /* Windowed flash access */
1311 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1312 + if (header->magic == NVRAM_MAGIC)
1313 + goto found;
1314 + off <<= 1;
1315 + }
1316 +
1317 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1318 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1319 + if (header->magic == NVRAM_MAGIC)
1320 + goto found;
1321 +
1322 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1323 + if (header->magic == NVRAM_MAGIC)
1324 + goto found;
1325 +
1326 + return;
1327 +
1328 +found:
1329 + src = (u32 *) header;
1330 + dst = (u32 *) nvram_buf;
1331 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1332 + *dst++ = *src++;
1333 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1334 + *dst++ = ltoh32(*src++);
1335 +}
1336 +
1337 +/* Early (before mm or mtd) read-only access to NVRAM */
1338 +char * __init early_nvram_get(const char *name)
1339 +{
1340 + char *var, *value, *end, *eq;
1341 +
1342 + if (!name)
1343 + return NULL;
1344 +
1345 + /* Too early? */
1346 + if (sbh == NULL)
1347 + return NULL;
1348 +
1349 + if (!nvram_buf[0])
1350 + early_nvram_init();
1351 +
1352 + if (cfe_env)
1353 + return cfe_env_get(nvram_buf, name);
1354 +
1355 + /* Look for name=value and return value */
1356 + var = &nvram_buf[sizeof(struct nvram_header)];
1357 + end = nvram_buf + sizeof(nvram_buf) - 2;
1358 + end[0] = end[1] = '\0';
1359 + for (; *var; var = value + strlen(value) + 1) {
1360 + if (!(eq = strchr(var, '=')))
1361 + break;
1362 + value = eq + 1;
1363 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1364 + return value;
1365 + }
1366 +
1367 + return NULL;
1368 +}
1369 +
1370 +char *nvram_get(const char *name)
1371 +{
1372 + char *var, *value, *end, *eq;
1373 +
1374 + if (!name)
1375 + return NULL;
1376 +
1377 + if (!nvram_buf[0])
1378 + return NULL;
1379 +
1380 + /* Look for name=value and return value */
1381 + var = &nvram_buf[sizeof(struct nvram_header)];
1382 + end = nvram_buf + sizeof(nvram_buf) - 2;
1383 + end[0] = end[1] = '\0';
1384 + for (; *var; var = value + strlen(value) + 1) {
1385 + if (!(eq = strchr(var, '=')))
1386 + break;
1387 + value = eq + 1;
1388 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1389 + return value;
1390 + }
1391 +
1392 + return NULL;
1393 +}
1394 +
1395 +EXPORT_SYMBOL(nvram_get);
1396 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1397 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1398 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2006-10-15 23:46:15.000000000 +0200
1399 @@ -0,0 +1,1115 @@
1400 +/*
1401 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1402 + *
1403 + * Copyright 2005, Broadcom Corporation
1404 + * All Rights Reserved.
1405 + *
1406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1410 + *
1411 + * $Id$
1412 + */
1413 +
1414 +#include <typedefs.h>
1415 +#include <osl.h>
1416 +#include <sbutils.h>
1417 +#include <bcmdevs.h>
1418 +#include <bcmnvram.h>
1419 +#include <bcmutils.h>
1420 +#include <hndmips.h>
1421 +#include <sbconfig.h>
1422 +#include <sbextif.h>
1423 +#include <sbchipc.h>
1424 +#include <sbmemc.h>
1425 +#include <mipsinc.h>
1426 +#include <sbutils.h>
1427 +
1428 +/*
1429 + * Returns TRUE if an external UART exists at the given base
1430 + * register.
1431 + */
1432 +static bool
1433 +BCMINITFN(serial_exists)(uint8 *regs)
1434 +{
1435 + uint8 save_mcr, status1;
1436 +
1437 + save_mcr = R_REG(&regs[UART_MCR]);
1438 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1439 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1440 + W_REG(&regs[UART_MCR], save_mcr);
1441 +
1442 + return (status1 == 0x90);
1443 +}
1444 +
1445 +/*
1446 + * Initializes UART access. The callback function will be called once
1447 + * per found UART.
1448 + */
1449 +void
1450 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1451 +{
1452 + void *regs;
1453 + ulong base;
1454 + uint irq;
1455 + int i, n;
1456 +
1457 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1458 + extifregs_t *eir = (extifregs_t *) regs;
1459 + sbconfig_t *sb;
1460 +
1461 + /* Determine external UART register base */
1462 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1463 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1464 +
1465 + /* Determine IRQ */
1466 + irq = sb_irq(sbh);
1467 +
1468 + /* Disable GPIO interrupt initially */
1469 + W_REG(&eir->gpiointpolarity, 0);
1470 + W_REG(&eir->gpiointmask, 0);
1471 +
1472 + /* Search for external UARTs */
1473 + n = 2;
1474 + for (i = 0; i < 2; i++) {
1475 + regs = (void *) REG_MAP(base + (i * 8), 8);
1476 + if (BCMINIT(serial_exists)(regs)) {
1477 + /* Set GPIO 1 to be the external UART IRQ */
1478 + W_REG(&eir->gpiointmask, 2);
1479 + if (add)
1480 + add(regs, irq, 13500000, 0);
1481 + }
1482 + }
1483 +
1484 + /* Add internal UART if enabled */
1485 + if (R_REG(&eir->corecontrol) & CC_UE)
1486 + if (add)
1487 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1488 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1489 + chipcregs_t *cc = (chipcregs_t *) regs;
1490 + uint32 rev, cap, pll, baud_base, div;
1491 +
1492 + /* Determine core revision and capabilities */
1493 + rev = sb_corerev(sbh);
1494 + cap = R_REG(&cc->capabilities);
1495 + pll = cap & CAP_PLL_MASK;
1496 +
1497 + /* Determine IRQ */
1498 + irq = sb_irq(sbh);
1499 +
1500 + if (pll == PLL_TYPE1) {
1501 + /* PLL clock */
1502 + baud_base = sb_clock_rate(pll,
1503 + R_REG(&cc->clockcontrol_n),
1504 + R_REG(&cc->clockcontrol_m2));
1505 + div = 1;
1506 + } else {
1507 + if (rev >= 11) {
1508 + /* Fixed ALP clock */
1509 + baud_base = 20000000;
1510 + div = 1;
1511 + /* Set the override bit so we don't divide it */
1512 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1513 + } else if (rev >= 3) {
1514 + /* Internal backplane clock */
1515 + baud_base = sb_clock(sbh);
1516 + div = 2; /* Minimum divisor */
1517 + W_REG(&cc->clkdiv,
1518 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1519 + } else {
1520 + /* Fixed internal backplane clock */
1521 + baud_base = 88000000;
1522 + div = 48;
1523 + }
1524 +
1525 + /* Clock source depends on strapping if UartClkOverride is unset */
1526 + if ((rev > 0) &&
1527 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1528 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1529 + /* Internal divided backplane clock */
1530 + baud_base /= div;
1531 + } else {
1532 + /* Assume external clock of 1.8432 MHz */
1533 + baud_base = 1843200;
1534 + }
1535 + }
1536 + }
1537 +
1538 + /* Add internal UARTs */
1539 + n = cap & CAP_UARTS_MASK;
1540 + for (i = 0; i < n; i++) {
1541 + /* Register offset changed after revision 0 */
1542 + if (rev)
1543 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1544 + else
1545 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1546 +
1547 + if (add)
1548 + add(regs, irq, baud_base, 0);
1549 + }
1550 + }
1551 +}
1552 +
1553 +/*
1554 + * Initialize jtag master and return handle for
1555 + * jtag_rwreg. Returns NULL on failure.
1556 + */
1557 +void *
1558 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1559 +{
1560 + void *regs;
1561 +
1562 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1563 + chipcregs_t *cc = (chipcregs_t *) regs;
1564 + uint32 tmp;
1565 +
1566 + /*
1567 + * Determine jtagm availability from
1568 + * core revision and capabilities.
1569 + */
1570 + tmp = sb_corerev(sbh);
1571 + /*
1572 + * Corerev 10 has jtagm, but the only chip
1573 + * with it does not have a mips, and
1574 + * the layout of the jtagcmd register is
1575 + * different. We'll only accept >= 11.
1576 + */
1577 + if (tmp < 11)
1578 + return (NULL);
1579 +
1580 + tmp = R_REG(&cc->capabilities);
1581 + if ((tmp & CAP_JTAGP) == 0)
1582 + return (NULL);
1583 +
1584 + /* Set clock divider if requested */
1585 + if (clkd != 0) {
1586 + tmp = R_REG(&cc->clkdiv);
1587 + tmp = (tmp & ~CLKD_JTAG) |
1588 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1589 + W_REG(&cc->clkdiv, tmp);
1590 + }
1591 +
1592 + /* Enable jtagm */
1593 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1594 + W_REG(&cc->jtagctrl, tmp);
1595 + }
1596 +
1597 + return (regs);
1598 +}
1599 +
1600 +void
1601 +sb_jtagm_disable(void *h)
1602 +{
1603 + chipcregs_t *cc = (chipcregs_t *)h;
1604 +
1605 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1606 +}
1607 +
1608 +/*
1609 + * Read/write a jtag register. Assumes a target with
1610 + * 8 bit IR and 32 bit DR.
1611 + */
1612 +#define IRWIDTH 8
1613 +#define DRWIDTH 32
1614 +uint32
1615 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1616 +{
1617 + chipcregs_t *cc = (chipcregs_t *) h;
1618 + uint32 tmp;
1619 +
1620 + W_REG(&cc->jtagir, ir);
1621 + W_REG(&cc->jtagdr, dr);
1622 + tmp = JCMD_START | JCMD_ACC_IRDR |
1623 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1624 + (DRWIDTH - 1);
1625 + W_REG(&cc->jtagcmd, tmp);
1626 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1627 + /* OSL_DELAY(1); */
1628 + }
1629 +
1630 + tmp = R_REG(&cc->jtagdr);
1631 + return (tmp);
1632 +}
1633 +
1634 +/* Returns the SB interrupt flag of the current core. */
1635 +uint32
1636 +sb_flag(sb_t *sbh)
1637 +{
1638 + void *regs;
1639 + sbconfig_t *sb;
1640 +
1641 + regs = sb_coreregs(sbh);
1642 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1643 +
1644 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1645 +}
1646 +
1647 +static const uint32 sbips_int_mask[] = {
1648 + 0,
1649 + SBIPS_INT1_MASK,
1650 + SBIPS_INT2_MASK,
1651 + SBIPS_INT3_MASK,
1652 + SBIPS_INT4_MASK
1653 +};
1654 +
1655 +static const uint32 sbips_int_shift[] = {
1656 + 0,
1657 + 0,
1658 + SBIPS_INT2_SHIFT,
1659 + SBIPS_INT3_SHIFT,
1660 + SBIPS_INT4_SHIFT
1661 +};
1662 +
1663 +/*
1664 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1665 + * 0 is returned.
1666 + */
1667 +uint
1668 +sb_irq(sb_t *sbh)
1669 +{
1670 + uint idx;
1671 + void *regs;
1672 + sbconfig_t *sb;
1673 + uint32 flag, sbipsflag;
1674 + uint irq = 0;
1675 +
1676 + flag = sb_flag(sbh);
1677 +
1678 + idx = sb_coreidx(sbh);
1679 +
1680 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1681 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1682 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1683 +
1684 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1685 + sbipsflag = R_REG(&sb->sbipsflag);
1686 + for (irq = 1; irq <= 4; irq++) {
1687 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1688 + break;
1689 + }
1690 + if (irq == 5)
1691 + irq = 0;
1692 + }
1693 +
1694 + sb_setcoreidx(sbh, idx);
1695 +
1696 + return irq;
1697 +}
1698 +
1699 +/* Clears the specified MIPS IRQ. */
1700 +static void
1701 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1702 +{
1703 + void *regs;
1704 + sbconfig_t *sb;
1705 +
1706 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1707 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1708 + ASSERT(regs);
1709 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1710 +
1711 + if (irq == 0)
1712 + W_REG(&sb->sbintvec, 0);
1713 + else
1714 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1715 +}
1716 +
1717 +/*
1718 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1719 + * IRQ 0 may be assigned more than once.
1720 + */
1721 +static void
1722 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 + uint32 flag;
1727 +
1728 + regs = sb_setcore(sbh, coreid, coreunit);
1729 + ASSERT(regs);
1730 + flag = sb_flag(sbh);
1731 +
1732 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1733 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1734 + ASSERT(regs);
1735 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1736 +
1737 + if (irq == 0)
1738 + OR_REG(&sb->sbintvec, 1 << flag);
1739 + else {
1740 + flag <<= sbips_int_shift[irq];
1741 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1742 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1743 + W_REG(&sb->sbipsflag, flag);
1744 + }
1745 +}
1746 +
1747 +/*
1748 + * Initializes clocks and interrupts. SB and NVRAM access must be
1749 + * initialized prior to calling.
1750 + */
1751 +void
1752 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1753 +{
1754 + ulong hz, ns, tmp;
1755 + extifregs_t *eir;
1756 + chipcregs_t *cc;
1757 + char *value;
1758 + uint irq;
1759 +
1760 + /* Figure out current SB clock speed */
1761 + if ((hz = sb_clock(sbh)) == 0)
1762 + hz = 100000000;
1763 + ns = 1000000000 / hz;
1764 +
1765 + /* Setup external interface timing */
1766 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1767 + /* Initialize extif so we can get to the LEDs and external UART */
1768 + W_REG(&eir->prog_config, CF_EN);
1769 +
1770 + /* Set timing for the flash */
1771 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1772 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1773 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1774 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1775 +
1776 + /* Set programmable interface timing for external uart */
1777 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1778 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1779 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1780 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1781 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1782 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1783 + /* set register for external IO to control LED. */
1784 + W_REG(&cc->prog_config, 0x11);
1785 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1786 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1787 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
1788 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1789 +
1790 + /* Set timing for the flash */
1791 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1792 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1793 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1794 +
1795 + // Added by Chen-I for 5365
1796 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1797 + {
1798 + W_REG(&cc->flash_waitcount, tmp);
1799 + W_REG(&cc->pcmcia_memwait, tmp);
1800 + }
1801 + else
1802 + {
1803 + if (sb_corerev(sbh) < 9)
1804 + W_REG(&cc->flash_waitcount, tmp);
1805 +
1806 + if ((sb_corerev(sbh) < 9) ||
1807 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1808 + W_REG(&cc->pcmcia_memwait, tmp);
1809 + }
1810 + }
1811 + // Added by Chen-I & Yen for enabling 5350 EXTIF
1812 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
1813 + {
1814 + /* Set programmable interface timing for external uart */
1815 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1816 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1817 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1818 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1819 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1820 + }
1821 + }
1822 +
1823 + /* Chip specific initialization */
1824 + switch (BCMINIT(sb_chip)(sbh)) {
1825 + case BCM4710_DEVICE_ID:
1826 + /* Clear interrupt map */
1827 + for (irq = 0; irq <= 4; irq++)
1828 + BCMINIT(sb_clearirq)(sbh, irq);
1829 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1830 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1831 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1832 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1833 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1834 + ASSERT(eir);
1835 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1836 + if (value && !strcmp(value, "31")) {
1837 + /* Enable internal UART */
1838 + W_REG(&eir->corecontrol, CC_UE);
1839 + /* Give USB its own interrupt */
1840 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1841 + } else {
1842 + /* Disable internal UART */
1843 + W_REG(&eir->corecontrol, 0);
1844 + /* Give Ethernet its own interrupt */
1845 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1846 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1847 + }
1848 + break;
1849 + case BCM5350_DEVICE_ID:
1850 + /* Clear interrupt map */
1851 + for (irq = 0; irq <= 4; irq++)
1852 + BCMINIT(sb_clearirq)(sbh, irq);
1853 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1854 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1855 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1856 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1857 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1858 + break;
1859 + }
1860 +}
1861 +
1862 +uint32
1863 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1864 +{
1865 + extifregs_t *eir;
1866 + chipcregs_t *cc;
1867 + uint32 n, m;
1868 + uint idx;
1869 + uint32 pll_type, rate = 0;
1870 +
1871 + /* get index of the current core */
1872 + idx = sb_coreidx(sbh);
1873 + pll_type = PLL_TYPE1;
1874 +
1875 + /* switch to extif or chipc core */
1876 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1877 + n = R_REG(&eir->clockcontrol_n);
1878 + m = R_REG(&eir->clockcontrol_sb);
1879 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1880 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1881 + n = R_REG(&cc->clockcontrol_n);
1882 + if ((pll_type == PLL_TYPE2) ||
1883 + (pll_type == PLL_TYPE4) ||
1884 + (pll_type == PLL_TYPE6) ||
1885 + (pll_type == PLL_TYPE7))
1886 + m = R_REG(&cc->clockcontrol_mips);
1887 + else if (pll_type == PLL_TYPE5) {
1888 + rate = 200000000;
1889 + goto out;
1890 + }
1891 + else if (pll_type == PLL_TYPE3) {
1892 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1893 + rate = 200000000;
1894 + goto out;
1895 + } else
1896 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1897 + } else
1898 + m = R_REG(&cc->clockcontrol_sb);
1899 + } else
1900 + goto out;
1901 +
1902 + // Added by Chen-I for 5365
1903 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1904 + rate = 100000000;
1905 + else
1906 + /* calculate rate */
1907 + rate = sb_clock_rate(pll_type, n, m);
1908 +
1909 + if (pll_type == PLL_TYPE6)
1910 + rate = SB2MIPS_T6(rate);
1911 +
1912 +out:
1913 + /* switch back to previous core */
1914 + sb_setcoreidx(sbh, idx);
1915 +
1916 + return rate;
1917 +}
1918 +
1919 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1920 +
1921 +static void
1922 +BCMINITFN(handler)(void)
1923 +{
1924 + /* Step 11 */
1925 + __asm__ (
1926 + ".set\tmips32\n\t"
1927 + "ssnop\n\t"
1928 + "ssnop\n\t"
1929 + /* Disable interrupts */
1930 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1931 + "mfc0 $15, $12\n\t"
1932 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1933 + "li $14, -31746\n\t"
1934 + "and $15, $15, $14\n\t"
1935 + "mtc0 $15, $12\n\t"
1936 + "eret\n\t"
1937 + "nop\n\t"
1938 + "nop\n\t"
1939 + ".set\tmips0"
1940 + );
1941 +}
1942 +
1943 +/* The following MUST come right after handler() */
1944 +static void
1945 +BCMINITFN(afterhandler)(void)
1946 +{
1947 +}
1948 +
1949 +/*
1950 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1951 + */
1952 +bool
1953 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1954 +{
1955 + extifregs_t *eir = NULL;
1956 + chipcregs_t *cc = NULL;
1957 + mipsregs_t *mipsr = NULL;
1958 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1959 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1960 + uint32 pll_type, sync_mode;
1961 + uint ic_size, ic_lsize;
1962 + uint idx, i;
1963 + typedef struct {
1964 + uint32 mipsclock;
1965 + uint16 n;
1966 + uint32 sb;
1967 + uint32 pci33;
1968 + uint32 pci25;
1969 + } n3m_table_t;
1970 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1971 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1972 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1973 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1974 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1975 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1976 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1977 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1978 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1979 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1980 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1981 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1982 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1983 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1984 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1985 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1986 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1987 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1988 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1989 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1990 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1991 + };
1992 + typedef struct {
1993 + uint32 mipsclock;
1994 + uint16 n;
1995 + uint32 m2; /* that is the clockcontrol_m2 */
1996 + } type3_table_t;
1997 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
1998 + { 150000000, 0x311, 0x4020005 },
1999 + { 200000000, 0x311, 0x4020003 },
2000 + };
2001 + typedef struct {
2002 + uint32 mipsclock;
2003 + uint32 sbclock;
2004 + uint16 n;
2005 + uint32 sb;
2006 + uint32 pci33;
2007 + uint32 m2;
2008 + uint32 m3;
2009 + uint32 ratio_cfg;
2010 + uint32 ratio_parm;
2011 + } n4m_table_t;
2012 +
2013 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2014 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2015 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2016 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2017 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2018 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2019 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2020 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2021 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2023 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2026 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2027 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2028 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2029 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2031 + };
2032 +
2033 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2034 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2035 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2036 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2037 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2038 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2039 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2041 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2042 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2043 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2045 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2047 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2048 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2049 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2050 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2051 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2052 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2053 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2054 + };
2055 +
2056 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2057 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2058 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2059 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2060 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2061 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2062 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2063 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2065 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2066 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2067 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2068 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2070 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2071 + };
2072 +
2073 + ulong start, end, dst;
2074 + bool ret = FALSE;
2075 +
2076 + /* get index of the current core */
2077 + idx = sb_coreidx(sbh);
2078 + clockcontrol_m2 = NULL;
2079 +
2080 + /* switch to extif or chipc core */
2081 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2082 + pll_type = PLL_TYPE1;
2083 + clockcontrol_n = &eir->clockcontrol_n;
2084 + clockcontrol_sb = &eir->clockcontrol_sb;
2085 + clockcontrol_pci = &eir->clockcontrol_pci;
2086 + clockcontrol_m2 = &cc->clockcontrol_m2;
2087 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2088 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2089 + if (pll_type == PLL_TYPE6) {
2090 + clockcontrol_n = NULL;
2091 + clockcontrol_sb = NULL;
2092 + clockcontrol_pci = NULL;
2093 + } else {
2094 + clockcontrol_n = &cc->clockcontrol_n;
2095 + clockcontrol_sb = &cc->clockcontrol_sb;
2096 + clockcontrol_pci = &cc->clockcontrol_pci;
2097 + clockcontrol_m2 = &cc->clockcontrol_m2;
2098 + }
2099 + } else
2100 + goto done;
2101 +
2102 + if (pll_type == PLL_TYPE6) {
2103 + /* Silence compilers */
2104 + orig_n = orig_sb = orig_pci = 0;
2105 + } else {
2106 + /* Store the current clock register values */
2107 + orig_n = R_REG(clockcontrol_n);
2108 + orig_sb = R_REG(clockcontrol_sb);
2109 + orig_pci = R_REG(clockcontrol_pci);
2110 + }
2111 +
2112 + if (pll_type == PLL_TYPE1) {
2113 + /* Keep the current PCI clock if not specified */
2114 + if (pciclock == 0) {
2115 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2116 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2117 + }
2118 +
2119 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2120 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2121 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2122 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2123 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2124 + break;
2125 + }
2126 + if (i == 0) {
2127 + ret = FALSE;
2128 + goto done;
2129 + } else {
2130 + ret = TRUE;
2131 + i--;
2132 + }
2133 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2134 +
2135 + /* No PLL change */
2136 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2137 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2138 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2139 + goto done;
2140 +
2141 + /* Set the PLL controls */
2142 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2143 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2144 + if (pciclock == 25000000)
2145 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2146 + else
2147 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2148 +
2149 + /* Reset */
2150 + sb_watchdog(sbh, 1);
2151 +
2152 + while (1);
2153 + } else if ((pll_type == PLL_TYPE3) &&
2154 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2155 + /* 5350 */
2156 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2157 +
2158 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2159 + if (type3_table[i].mipsclock > mipsclock)
2160 + break;
2161 + }
2162 + if (i == 0) {
2163 + ret = FALSE;
2164 + goto done;
2165 + } else {
2166 + ret = TRUE;
2167 + i--;
2168 + }
2169 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2170 +
2171 + /* No PLL change */
2172 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2173 + if ((orig_n == type3_table[i].n) &&
2174 + (orig_m2 == type3_table[i].m2)) {
2175 + goto done;
2176 + }
2177 +
2178 + /* Set the PLL controls */
2179 + W_REG(clockcontrol_n, type3_table[i].n);
2180 + W_REG(clockcontrol_m2, type3_table[i].m2);
2181 +
2182 + /* Reset */
2183 + sb_watchdog(sbh, 1);
2184 + while (1);
2185 + } else if ((pll_type == PLL_TYPE2) ||
2186 + (pll_type == PLL_TYPE4) ||
2187 + (pll_type == PLL_TYPE6) ||
2188 + (pll_type == PLL_TYPE7)) {
2189 + n4m_table_t *table = NULL, *te;
2190 + uint tabsz = 0;
2191 +
2192 + ASSERT(cc);
2193 +
2194 + orig_mips = R_REG(&cc->clockcontrol_mips);
2195 +
2196 + if (pll_type == PLL_TYPE6) {
2197 + uint32 new_mips = 0;
2198 +
2199 + ret = TRUE;
2200 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2201 + new_mips = CC_T6_MMASK;
2202 +
2203 + if (orig_mips == new_mips)
2204 + goto done;
2205 +
2206 + W_REG(&cc->clockcontrol_mips, new_mips);
2207 + goto end_fill;
2208 + }
2209 +
2210 + if (pll_type == PLL_TYPE2) {
2211 + table = BCMINIT(type2_table);
2212 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2213 + } else if (pll_type == PLL_TYPE4) {
2214 + table = BCMINIT(type4_table);
2215 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2216 + } else if (pll_type == PLL_TYPE7) {
2217 + table = BCMINIT(type7_table);
2218 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2219 + } else
2220 + ASSERT("No table for plltype" == NULL);
2221 +
2222 + /* Store the current clock register values */
2223 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2224 + orig_ratio_parm = 0;
2225 + orig_ratio_cfg = 0;
2226 +
2227 + /* Look up current ratio */
2228 + for (i = 0; i < tabsz; i++) {
2229 + if ((orig_n == table[i].n) &&
2230 + (orig_sb == table[i].sb) &&
2231 + (orig_pci == table[i].pci33) &&
2232 + (orig_m2 == table[i].m2) &&
2233 + (orig_mips == table[i].m3)) {
2234 + orig_ratio_parm = table[i].ratio_parm;
2235 + orig_ratio_cfg = table[i].ratio_cfg;
2236 + break;
2237 + }
2238 + }
2239 +
2240 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2241 + for (i = 0; i < tabsz; i++) {
2242 + ASSERT(table[i].mipsclock ==
2243 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2244 + if ((mipsclock <= table[i].mipsclock) &&
2245 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2246 + break;
2247 + }
2248 + if (i == tabsz) {
2249 + ret = FALSE;
2250 + goto done;
2251 + } else {
2252 + te = &table[i];
2253 + ret = TRUE;
2254 + }
2255 +
2256 + /* No PLL change */
2257 + if ((orig_n == te->n) &&
2258 + (orig_sb == te->sb) &&
2259 + (orig_pci == te->pci33) &&
2260 + (orig_m2 == te->m2) &&
2261 + (orig_mips == te->m3))
2262 + goto done;
2263 +
2264 + /* Set the PLL controls */
2265 + W_REG(clockcontrol_n, te->n);
2266 + W_REG(clockcontrol_sb, te->sb);
2267 + W_REG(clockcontrol_pci, te->pci33);
2268 + W_REG(&cc->clockcontrol_m2, te->m2);
2269 + W_REG(&cc->clockcontrol_mips, te->m3);
2270 +
2271 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2272 + if ((pll_type == PLL_TYPE7) &&
2273 + (te->sb != te->m2) &&
2274 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2275 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2276 +
2277 + /* No ratio change */
2278 + if (orig_ratio_parm == te->ratio_parm)
2279 + goto end_fill;
2280 +
2281 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2282 +
2283 + /* Preload the code into the cache */
2284 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2285 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2286 + while (start < end) {
2287 + cache_op(start, Fill_I);
2288 + start += ic_lsize;
2289 + }
2290 +
2291 + /* Copy the handler */
2292 + start = (ulong) &BCMINIT(handler);
2293 + end = (ulong) &BCMINIT(afterhandler);
2294 + dst = KSEG1ADDR(0x180);
2295 + for (i = 0; i < (end - start); i += 4)
2296 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2297 +
2298 + /* Preload handler into the cache one line at a time */
2299 + for (i = 0; i < (end - start); i += 4)
2300 + cache_op(dst + i, Fill_I);
2301 +
2302 + /* Clear BEV bit */
2303 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2304 +
2305 + /* Enable interrupts */
2306 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2307 +
2308 + /* Enable MIPS timer interrupt */
2309 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2310 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2311 + ASSERT(mipsr);
2312 + W_REG(&mipsr->intmask, 1);
2313 +
2314 + start_fill:
2315 + /* step 1, set clock ratios */
2316 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2317 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2318 +
2319 + /* step 2: program timer intr */
2320 + W_REG(&mipsr->timer, 100);
2321 + (void) R_REG(&mipsr->timer);
2322 +
2323 + /* step 3, switch to async */
2324 + sync_mode = MFC0(C0_BROADCOM, 4);
2325 + MTC0(C0_BROADCOM, 4, 1 << 22);
2326 +
2327 + /* step 4, set cfg active */
2328 + MTC0(C0_BROADCOM, 2, 0x9);
2329 +
2330 +
2331 + /* steps 5 & 6 */
2332 + __asm__ __volatile__ (
2333 + ".set\tmips3\n\t"
2334 + "wait\n\t"
2335 + ".set\tmips0"
2336 + );
2337 +
2338 + /* step 7, clear cfg_active */
2339 + MTC0(C0_BROADCOM, 2, 0);
2340 +
2341 + /* Additional Step: set back to orig sync mode */
2342 + MTC0(C0_BROADCOM, 4, sync_mode);
2343 +
2344 + /* step 8, fake soft reset */
2345 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2346 +
2347 + end_fill:
2348 + /* step 9 set watchdog timer */
2349 + sb_watchdog(sbh, 20);
2350 + (void) R_REG(&cc->chipid);
2351 +
2352 + /* step 11 */
2353 + __asm__ __volatile__ (
2354 + ".set\tmips3\n\t"
2355 + "sync\n\t"
2356 + "wait\n\t"
2357 + ".set\tmips0"
2358 + );
2359 + while (1);
2360 + }
2361 +
2362 +done:
2363 + /* switch back to previous core */
2364 + sb_setcoreidx(sbh, idx);
2365 +
2366 + return ret;
2367 +}
2368 +
2369 +/*
2370 + * This also must be run from the cache on 47xx
2371 + * so there are no mips core BIU ops in progress
2372 + * when the PFC is enabled.
2373 + */
2374 +
2375 +static void
2376 +BCMINITFN(_enable_pfc)(uint32 mode)
2377 +{
2378 + /* write range */
2379 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2380 +
2381 + /* enable */
2382 + *(volatile uint32 *)PFC_CR0 = mode;
2383 +}
2384 +
2385 +void
2386 +BCMINITFN(enable_pfc)(uint32 mode)
2387 +{
2388 + ulong start, end;
2389 + int i;
2390 +
2391 + /* If auto then choose the correct mode for this
2392 + platform, currently we only ever select one mode */
2393 + if (mode == PFC_AUTO)
2394 + mode = PFC_INST;
2395 +
2396 + /* enable prefetch cache if available */
2397 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2398 + start = (ulong) &BCMINIT(_enable_pfc);
2399 + end = (ulong) &BCMINIT(enable_pfc);
2400 +
2401 + /* Preload handler into the cache one line at a time */
2402 + for (i = 0; i < (end - start); i += 4)
2403 + cache_op(start + i, Fill_I);
2404 +
2405 + BCMINIT(_enable_pfc)(mode);
2406 + }
2407 +}
2408 +
2409 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2410 +uint32
2411 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2412 +{
2413 + sbmemcregs_t *memc;
2414 + uint32 ret = 0;
2415 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2416 + uint idx, rev;
2417 +
2418 + idx = sb_coreidx(sbh);
2419 +
2420 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2421 + if (memc == 0)
2422 + goto out;
2423 +
2424 + rev = sb_corerev(sbh);
2425 +
2426 + config = R_REG(&memc->config);
2427 + wr = R_REG(&memc->wrncdlcor);
2428 + rd = R_REG(&memc->rdncdlcor);
2429 + misc = R_REG(&memc->miscdlyctl);
2430 + dqsg = R_REG(&memc->dqsgatencdl);
2431 +
2432 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2433 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2434 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2435 +
2436 + if (config & MEMC_CONFIG_DDR) {
2437 + ret = (wr << 16) | (rd << 8) | dqsg;
2438 + } else {
2439 + if (rev > 0)
2440 + cd = rd;
2441 + else
2442 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2443 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2444 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2445 + ret = (sm << 16) | (sd << 8) | cd;
2446 + }
2447 +
2448 +out:
2449 + /* switch back to previous core */
2450 + sb_setcoreidx(sbh, idx);
2451 +
2452 + return ret;
2453 +}
2454 +
2455 +uint32
2456 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
2457 +{
2458 + extifregs_t *eir;
2459 + chipcregs_t *cc;
2460 + uint32 n, m;
2461 + uint idx;
2462 + uint32 pll_type, rate = 0;
2463 +
2464 + /* get index of the current core */
2465 + idx = sb_coreidx(sbh);
2466 + pll_type = PLL_TYPE1;
2467 +
2468 + /* switch to extif or chipc core */
2469 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2470 + n = R_REG(&eir->clockcontrol_n);
2471 + m = R_REG(&eir->clockcontrol_sb);
2472 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2473 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2474 + n = R_REG(&cc->clockcontrol_n);
2475 + if ((pll_type == PLL_TYPE2) ||
2476 + (pll_type == PLL_TYPE4) ||
2477 + (pll_type == PLL_TYPE6) ||
2478 + (pll_type == PLL_TYPE7))
2479 + m = R_REG(&cc->clockcontrol_mips);
2480 + else if (pll_type == PLL_TYPE5) {
2481 + rate = 200000000;
2482 + goto out;
2483 + }
2484 + else if (pll_type == PLL_TYPE3) {
2485 + if (sb_chip(sbh) == 0x5365) {
2486 + rate = 200000000;
2487 + goto out;
2488 + }
2489 + /* 5350 uses m2 to control mips */
2490 + else
2491 + m = R_REG(&cc->clockcontrol_m2);
2492 + } else
2493 + m = R_REG(&cc->clockcontrol_sb);
2494 + } else
2495 + goto out;
2496 +
2497 +
2498 + /* calculate rate */
2499 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
2500 + rate = 100000000;
2501 + else
2502 + rate = sb_clock_rate(pll_type, n, m);
2503 +
2504 + if (pll_type == PLL_TYPE6)
2505 + rate = SB2MIPS_T6(rate);
2506 +
2507 +out:
2508 + /* switch back to previous core */
2509 + sb_setcoreidx(sbh, idx);
2510 +
2511 + return rate;
2512 +}
2513 +
2514 +
2515 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2516 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2517 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2006-10-15 23:29:14.000000000 +0200
2518 @@ -0,0 +1,534 @@
2519 +/*
2520 + * Low-Level PCI and SB support for BCM47xx
2521 + *
2522 + * Copyright 2005, Broadcom Corporation
2523 + * All Rights Reserved.
2524 + *
2525 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2526 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2527 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2528 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2529 + *
2530 + * $Id$
2531 + */
2532 +
2533 +#include <typedefs.h>
2534 +#include <pcicfg.h>
2535 +#include <bcmdevs.h>
2536 +#include <sbconfig.h>
2537 +#include <osl.h>
2538 +#include <sbutils.h>
2539 +#include <sbpci.h>
2540 +#include <bcmendian.h>
2541 +#include <bcmutils.h>
2542 +#include <bcmnvram.h>
2543 +#include <hndmips.h>
2544 +
2545 +/* Can free sbpci_init() memory after boot */
2546 +#ifndef linux
2547 +#define __init
2548 +#endif
2549 +
2550 +/* Emulated configuration space */
2551 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2552 +
2553 +/* Banned cores */
2554 +static uint16 pci_ban[32] = { 0 };
2555 +static uint pci_banned = 0;
2556 +
2557 +/* CardBus mode */
2558 +static bool cardbus = FALSE;
2559 +
2560 +/* Disable PCI host core */
2561 +static bool pci_disabled = FALSE;
2562 +
2563 +/*
2564 + * Functions for accessing external PCI configuration space
2565 + */
2566 +
2567 +/* Assume one-hot slot wiring */
2568 +#define PCI_SLOT_MAX 16
2569 +
2570 +static uint32
2571 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2572 +{
2573 + uint coreidx;
2574 + sbpciregs_t *regs;
2575 + uint32 addr = 0;
2576 +
2577 + /* CardBusMode supports only one device */
2578 + if (cardbus && dev > 1)
2579 + return 0;
2580 +
2581 + coreidx = sb_coreidx(sbh);
2582 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2583 +
2584 + /* Type 0 transaction */
2585 + if (bus == 1) {
2586 + /* Skip unwired slots */
2587 + if (dev < PCI_SLOT_MAX) {
2588 + /* Slide the PCI window to the appropriate slot */
2589 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2590 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2591 + (func << 8) | (off & ~3);
2592 + }
2593 + }
2594 +
2595 + /* Type 1 transaction */
2596 + else {
2597 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2598 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2599 + }
2600 +
2601 + sb_setcoreidx(sbh, coreidx);
2602 +
2603 + return addr;
2604 +}
2605 +
2606 +static int
2607 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2608 +{
2609 + uint32 addr, *reg = NULL, val;
2610 + int ret = 0;
2611 +
2612 + if (pci_disabled ||
2613 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2614 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2615 + BUSPROBE(val, reg))
2616 + val = 0xffffffff;
2617 +
2618 + val >>= 8 * (off & 3);
2619 + if (len == 4)
2620 + *((uint32 *) buf) = val;
2621 + else if (len == 2)
2622 + *((uint16 *) buf) = (uint16) val;
2623 + else if (len == 1)
2624 + *((uint8 *) buf) = (uint8) val;
2625 + else
2626 + ret = -1;
2627 +
2628 + if (reg)
2629 + REG_UNMAP(reg);
2630 +
2631 + return ret;
2632 +}
2633 +
2634 +static int
2635 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2636 +{
2637 + uint32 addr, *reg = NULL, val;
2638 + int ret = 0;
2639 +
2640 + if (pci_disabled ||
2641 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2642 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2643 + BUSPROBE(val, reg))
2644 + goto done;
2645 +
2646 + if (len == 4)
2647 + val = *((uint32 *) buf);
2648 + else if (len == 2) {
2649 + val &= ~(0xffff << (8 * (off & 3)));
2650 + val |= *((uint16 *) buf) << (8 * (off & 3));
2651 + } else if (len == 1) {
2652 + val &= ~(0xff << (8 * (off & 3)));
2653 + val |= *((uint8 *) buf) << (8 * (off & 3));
2654 + } else
2655 + ret = -1;
2656 +
2657 + W_REG(reg, val);
2658 +
2659 + done:
2660 + if (reg)
2661 + REG_UNMAP(reg);
2662 +
2663 + return ret;
2664 +}
2665 +
2666 +/*
2667 + * Functions for accessing translated SB configuration space
2668 + */
2669 +
2670 +static int
2671 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2672 +{
2673 + pci_config_regs *cfg;
2674 +
2675 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2676 + return -1;
2677 + cfg = &sb_config_regs[dev];
2678 +
2679 + ASSERT(ISALIGNED(off, len));
2680 + ASSERT(ISALIGNED((uintptr)buf, len));
2681 +
2682 + if (len == 4)
2683 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2684 + else if (len == 2)
2685 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2686 + else if (len == 1)
2687 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2688 + else
2689 + return -1;
2690 +
2691 + return 0;
2692 +}
2693 +
2694 +static int
2695 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2696 +{
2697 + uint coreidx, n;
2698 + void *regs;
2699 + sbconfig_t *sb;
2700 + pci_config_regs *cfg;
2701 +
2702 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2703 + return -1;
2704 + cfg = &sb_config_regs[dev];
2705 +
2706 + ASSERT(ISALIGNED(off, len));
2707 + ASSERT(ISALIGNED((uintptr)buf, len));
2708 +
2709 + /* Emulate BAR sizing */
2710 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2711 + len == 4 && *((uint32 *) buf) == ~0) {
2712 + coreidx = sb_coreidx(sbh);
2713 + if ((regs = sb_setcoreidx(sbh, dev))) {
2714 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2715 + /* Highest numbered address match register */
2716 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2717 + if (off == OFFSETOF(pci_config_regs, base[0]))
2718 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2719 +#if 0
2720 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2721 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2722 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2723 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2724 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2725 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2726 +#endif
2727 + }
2728 + sb_setcoreidx(sbh, coreidx);
2729 + return 0;
2730 + }
2731 +
2732 + if (len == 4)
2733 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2734 + else if (len == 2)
2735 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2736 + else if (len == 1)
2737 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2738 + else
2739 + return -1;
2740 +
2741 + return 0;
2742 +}
2743 +
2744 +int
2745 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2746 +{
2747 + if (bus == 0)
2748 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2749 + else
2750 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2751 +}
2752 +
2753 +int
2754 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2755 +{
2756 + if (bus == 0)
2757 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2758 + else
2759 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2760 +}
2761 +
2762 +void
2763 +sbpci_ban(uint16 core)
2764 +{
2765 + if (pci_banned < ARRAYSIZE(pci_ban))
2766 + pci_ban[pci_banned++] = core;
2767 +}
2768 +
2769 +static int
2770 +sbpci_init_pci(sb_t *sbh)
2771 +{
2772 + uint chip, chiprev, chippkg, host;
2773 + uint32 boardflags;
2774 + sbpciregs_t *pci;
2775 + sbconfig_t *sb;
2776 + uint32 val;
2777 +
2778 + chip = sb_chip(sbh);
2779 + chiprev = sb_chiprev(sbh);
2780 + chippkg = sb_chippkg(sbh);
2781 +
2782 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2783 + printf("PCI: no core\n");
2784 + pci_disabled = TRUE;
2785 + return -1;
2786 + }
2787 + sb_core_reset(sbh, 0);
2788 +
2789 + boardflags = (uint32) getintvar(NULL, "boardflags");
2790 +
2791 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2792 + pci_disabled = TRUE;
2793 +
2794 + /*
2795 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2796 + * PCI is bonded out, some boards may leave the pins
2797 + * floating.
2798 + */
2799 + if (((chip == BCM4712_DEVICE_ID) &&
2800 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2801 + (chippkg == BCM4712MID_PKG_ID))) ||
2802 + (chip == BCM5350_DEVICE_ID) ||
2803 + (boardflags & BFL_NOPCI))
2804 + pci_disabled = TRUE;
2805 +
2806 + /*
2807 + * If the PCI core should not be touched (disabled, not bonded
2808 + * out, or pins floating), do not even attempt to access core
2809 + * registers. Otherwise, try to determine if it is in host
2810 + * mode.
2811 + */
2812 + if (pci_disabled)
2813 + host = 0;
2814 + else
2815 + host = !BUSPROBE(val, &pci->control);
2816 +
2817 + if (!host) {
2818 + /* Disable PCI interrupts in client mode */
2819 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2820 + W_REG(&sb->sbintvec, 0);
2821 +
2822 + /* Disable the PCI bridge in client mode */
2823 + sbpci_ban(SB_PCI);
2824 + printf("PCI: Disabled\n");
2825 + } else {
2826 + /* Reset the external PCI bus and enable the clock */
2827 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2828 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2829 + OSL_DELAY(150); /* delay > 100 us */
2830 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2831 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2832 + OSL_DELAY(1); /* delay 1 us */
2833 +
2834 + /* Enable CardBusMode */
2835 + cardbus = nvram_match("cardbus", "1");
2836 + if (cardbus) {
2837 + printf("PCI: Enabling CardBus\n");
2838 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2839 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2840 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2841 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2842 + }
2843 +
2844 + /* 64 MB I/O access window */
2845 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2846 + /* 64 MB configuration access window */
2847 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2848 + /* 1 GB memory access window */
2849 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2850 +
2851 + /* Enable PCI bridge BAR0 prefetch and burst */
2852 + val = 6;
2853 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2854 +
2855 + /* Enable PCI interrupts */
2856 + W_REG(&pci->intmask, PCI_INTA);
2857 + }
2858 +
2859 + return 0;
2860 +}
2861 +
2862 +static int
2863 +sbpci_init_cores(sb_t *sbh)
2864 +{
2865 + uint chip, chiprev, chippkg, coreidx, i;
2866 + sbconfig_t *sb;
2867 + pci_config_regs *cfg;
2868 + void *regs;
2869 + char varname[8];
2870 + uint wlidx = 0;
2871 + uint16 vendor, core;
2872 + uint8 class, subclass, progif;
2873 + uint32 val;
2874 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2875 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2876 +
2877 + chip = sb_chip(sbh);
2878 + chiprev = sb_chiprev(sbh);
2879 + chippkg = sb_chippkg(sbh);
2880 + coreidx = sb_coreidx(sbh);
2881 +
2882 + /* Scan the SB bus */
2883 + bzero(sb_config_regs, sizeof(sb_config_regs));
2884 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2885 + cfg->vendor = 0xffff;
2886 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2887 + continue;
2888 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2889 +
2890 + /* Read ID register and parse vendor and core */
2891 + val = R_REG(&sb->sbidhigh);
2892 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2893 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2894 + progif = 0;
2895 +
2896 + /* Check if this core is banned */
2897 + for (i = 0; i < pci_banned; i++)
2898 + if (core == pci_ban[i])
2899 + break;
2900 + if (i < pci_banned)
2901 + continue;
2902 +
2903 + /* Known vendor translations */
2904 + switch (vendor) {
2905 + case SB_VEND_BCM:
2906 + vendor = VENDOR_BROADCOM;
2907 + break;
2908 + }
2909 +
2910 + /* Determine class based on known core codes */
2911 + switch (core) {
2912 + case SB_ILINE20:
2913 + class = PCI_CLASS_NET;
2914 + subclass = PCI_NET_ETHER;
2915 + core = BCM47XX_ILINE_ID;
2916 + break;
2917 + case SB_ILINE100:
2918 + class = PCI_CLASS_NET;
2919 + subclass = PCI_NET_ETHER;
2920 + core = BCM4610_ILINE_ID;
2921 + break;
2922 + case SB_ENET:
2923 + class = PCI_CLASS_NET;
2924 + subclass = PCI_NET_ETHER;
2925 + core = BCM47XX_ENET_ID;
2926 + break;
2927 + case SB_SDRAM:
2928 + case SB_MEMC:
2929 + class = PCI_CLASS_MEMORY;
2930 + subclass = PCI_MEMORY_RAM;
2931 + break;
2932 + case SB_PCI:
2933 +#if 0
2934 + class = PCI_CLASS_BRIDGE;
2935 + subclass = PCI_BRIDGE_PCI;
2936 + break;
2937 +#endif
2938 + case SB_MIPS:
2939 + case SB_MIPS33:
2940 + class = PCI_CLASS_CPU;
2941 + subclass = PCI_CPU_MIPS;
2942 + break;
2943 + case SB_CODEC:
2944 + class = PCI_CLASS_COMM;
2945 + subclass = PCI_COMM_MODEM;
2946 + core = BCM47XX_V90_ID;
2947 + break;
2948 + case SB_USB:
2949 + class = PCI_CLASS_SERIAL;
2950 + subclass = PCI_SERIAL_USB;
2951 + progif = 0x10; /* OHCI */
2952 + core = BCM47XX_USB_ID;
2953 + break;
2954 + case SB_USB11H:
2955 + class = PCI_CLASS_SERIAL;
2956 + subclass = PCI_SERIAL_USB;
2957 + progif = 0x10; /* OHCI */
2958 + core = BCM47XX_USBH_ID;
2959 + break;
2960 + case SB_USB11D:
2961 + class = PCI_CLASS_SERIAL;
2962 + subclass = PCI_SERIAL_USB;
2963 + core = BCM47XX_USBD_ID;
2964 + break;
2965 + case SB_IPSEC:
2966 + class = PCI_CLASS_CRYPT;
2967 + subclass = PCI_CRYPT_NETWORK;
2968 + core = BCM47XX_IPSEC_ID;
2969 + break;
2970 + case SB_ROBO:
2971 + class = PCI_CLASS_NET;
2972 + subclass = PCI_NET_OTHER;
2973 + core = BCM47XX_ROBO_ID;
2974 + break;
2975 + case SB_EXTIF:
2976 + case SB_CC:
2977 + class = PCI_CLASS_MEMORY;
2978 + subclass = PCI_MEMORY_FLASH;
2979 + break;
2980 + case SB_D11:
2981 + class = PCI_CLASS_NET;
2982 + subclass = PCI_NET_OTHER;
2983 + /* Let an nvram variable override this */
2984 + sprintf(varname, "wl%did", wlidx);
2985 + wlidx++;
2986 + if ((core = getintvar(NULL, varname)) == 0) {
2987 + if (chip == BCM4712_DEVICE_ID) {
2988 + if (chippkg == BCM4712SMALL_PKG_ID)
2989 + core = BCM4306_D11G_ID;
2990 + else
2991 + core = BCM4306_D11DUAL_ID;
2992 + } else {
2993 + /* 4310 */
2994 + core = BCM4310_D11B_ID;
2995 + }
2996 + }
2997 + break;
2998 +
2999 + default:
3000 + class = subclass = progif = 0xff;
3001 + break;
3002 + }
3003 +
3004 + /* Supported translations */
3005 + cfg->vendor = htol16(vendor);
3006 + cfg->device = htol16(core);
3007 + cfg->rev_id = chiprev;
3008 + cfg->prog_if = progif;
3009 + cfg->sub_class = subclass;
3010 + cfg->base_class = class;
3011 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
3012 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
3013 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
3014 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
3015 + cfg->base[4] = 0;
3016 + cfg->base[5] = 0;
3017 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
3018 + cfg->header_type = PCI_HEADER_BRIDGE;
3019 + else
3020 + cfg->header_type = PCI_HEADER_NORMAL;
3021 + /* Save core interrupt flag */
3022 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
3023 + /* Default to MIPS shared interrupt 0 */
3024 + cfg->int_line = 0;
3025 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
3026 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3027 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3028 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3029 + val = R_REG(&sb->sbipsflag);
3030 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
3031 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
3032 + break;
3033 + }
3034 + if (cfg->int_line > 4)
3035 + cfg->int_line = 0;
3036 + }
3037 + /* Emulated core */
3038 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
3039 + }
3040 +
3041 + sb_setcoreidx(sbh, coreidx);
3042 + return 0;
3043 +}
3044 +
3045 +int __init
3046 +sbpci_init(sb_t *sbh)
3047 +{
3048 + sbpci_init_pci(sbh);
3049 + sbpci_init_cores(sbh);
3050 + return 0;
3051 +}
3052 +
3053 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
3054 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
3055 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2006-10-15 23:29:14.000000000 +0200
3056 @@ -0,0 +1,2370 @@
3057 +/*
3058 + * Misc utility routines for accessing chip-specific features
3059 + * of the SiliconBackplane-based Broadcom chips.
3060 + *
3061 + * Copyright 2005, Broadcom Corporation
3062 + * All Rights Reserved.
3063 + *
3064 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3065 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3066 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3067 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3068 + * $Id$
3069 + */
3070 +
3071 +#include <typedefs.h>
3072 +#include <osl.h>
3073 +#include <sbutils.h>
3074 +#include <bcmutils.h>
3075 +#include <bcmdevs.h>
3076 +#include <sbconfig.h>
3077 +#include <sbchipc.h>
3078 +#include <sbpci.h>
3079 +#include <pcicfg.h>
3080 +#include <sbextif.h>
3081 +#include <bcmsrom.h>
3082 +
3083 +/* debug/trace */
3084 +#define SB_ERROR(args)
3085 +
3086 +
3087 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3088 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3089 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3090 +
3091 +/* misc sb info needed by some of the routines */
3092 +typedef struct sb_info {
3093 +
3094 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3095 +
3096 + void *osh; /* osl os handle */
3097 + void *sdh; /* bcmsdh handle */
3098 +
3099 + void *curmap; /* current regs va */
3100 + void *regs[SB_MAXCORES]; /* other regs va */
3101 +
3102 + uint curidx; /* current core index */
3103 + uint dev_coreid; /* the core provides driver functions */
3104 +
3105 + uint gpioidx; /* gpio control core index */
3106 + uint gpioid; /* gpio control coretype */
3107 +
3108 + uint numcores; /* # discovered cores */
3109 + uint coreid[SB_MAXCORES]; /* id of each core */
3110 +
3111 + void *intr_arg; /* interrupt callback function arg */
3112 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3113 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3114 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3115 +
3116 +} sb_info_t;
3117 +
3118 +/* local prototypes */
3119 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3120 + uint bustype, void *sdh, char **vars, int *varsz);
3121 +static void BCMINIT(sb_scan)(sb_info_t *si);
3122 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3123 +static uint _sb_coreidx(sb_info_t *si);
3124 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3125 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3126 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3127 +static int sb_pci_fixcfg(sb_info_t *si);
3128 +
3129 +/* delay needed between the mdio control/ mdiodata register data access */
3130 +#define PR28829_DELAY() OSL_DELAY(10)
3131 +
3132 +
3133 +/* global variable to indicate reservation/release of gpio's*/
3134 +static uint32 sb_gpioreservation = 0;
3135 +
3136 +#define SB_INFO(sbh) (sb_info_t*)sbh
3137 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3138 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3139 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3140 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3141 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3142 +#define BADIDX (SB_MAXCORES+1)
3143 +#define NOREV -1
3144 +
3145 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3146 +
3147 +/* sonicsrev */
3148 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3149 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3150 +
3151 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3152 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3153 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3154 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3155 +
3156 +/*
3157 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3158 + * after core switching to avoid invalid register accesss inside ISR.
3159 + */
3160 +#define INTR_OFF(si, intr_val) \
3161 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3162 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3163 +#define INTR_RESTORE(si, intr_val) \
3164 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3165 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3166 +
3167 +/* dynamic clock control defines */
3168 +#define LPOMINFREQ 25000 /* low power oscillator min */
3169 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3170 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3171 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3172 +#define PCIMINFREQ 25000000 /* 25 MHz */
3173 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3174 +
3175 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3176 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3177 +
3178 +#define MIN_DUMPBUFLEN 32 /* debug */
3179 +
3180 +/* GPIO Based LED powersave defines */
3181 +#define DEFAULT_GPIO_ONTIME 10
3182 +#define DEFAULT_GPIO_OFFTIME 90
3183 +
3184 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3185 +
3186 +static uint32
3187 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3188 +{
3189 + uint32 val = R_REG(sbr);
3190 +
3191 + return (val);
3192 +}
3193 +
3194 +static void
3195 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3196 +{
3197 + W_REG(sbr, v);
3198 +}
3199 +
3200 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3201 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3202 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3203 +
3204 +/* global kernel resource */
3205 +static sb_info_t ksi;
3206 +
3207 +/* generic kernel variant of sb_attach() */
3208 +sb_t *
3209 +BCMINITFN(sb_kattach)()
3210 +{
3211 + uint32 *regs;
3212 +
3213 + if (ksi.curmap == NULL) {
3214 + uint32 cid;
3215 +
3216 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3217 + cid = R_REG((uint32 *)regs);
3218 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3219 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3220 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3221 + uint32 *scc, val;
3222 +
3223 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3224 + val = R_REG(scc);
3225 + SB_ERROR((" initial scc = 0x%x\n", val));
3226 + val |= SCC_SS_XTAL;
3227 + W_REG(scc, val);
3228 + }
3229 +
3230 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3231 + SB_BUS, NULL, NULL, NULL) == NULL) {
3232 + return NULL;
3233 + }
3234 + }
3235 +
3236 + return (sb_t *)&ksi;
3237 +}
3238 +#endif
3239 +
3240 +static sb_info_t *
3241 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3242 + uint bustype, void *sdh, char **vars, int *varsz)
3243 +{
3244 + uint origidx;
3245 + chipcregs_t *cc;
3246 + sbconfig_t *sb;
3247 + uint32 w;
3248 +
3249 + ASSERT(GOODREGS(regs));
3250 +
3251 + bzero((uchar*)si, sizeof (sb_info_t));
3252 +
3253 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3254 +
3255 + si->osh = osh;
3256 + si->curmap = regs;
3257 + si->sdh = sdh;
3258 +
3259 + /* check to see if we are a sb core mimic'ing a pci core */
3260 + if (bustype == PCI_BUS) {
3261 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3262 + bustype = SB_BUS;
3263 + else
3264 + bustype = PCI_BUS;
3265 + }
3266 +
3267 + si->sb.bustype = bustype;
3268 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3269 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3270 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3271 + return NULL;
3272 + }
3273 +
3274 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3275 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3276 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3277 +
3278 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3279 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3280 + if (!GOODCOREADDR(w))
3281 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3282 + }
3283 +
3284 + /* initialize current core index value */
3285 + si->curidx = _sb_coreidx(si);
3286 +
3287 + if (si->curidx == BADIDX) {
3288 + SB_ERROR(("sb_doattach: bad core index\n"));
3289 + return NULL;
3290 + }
3291 +
3292 + /* get sonics backplane revision */
3293 + sb = REGS2SB(si->curmap);
3294 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3295 +
3296 + /* keep and reuse the initial register mapping */
3297 + origidx = si->curidx;
3298 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3299 + si->regs[origidx] = regs;
3300 +
3301 + /* is core-0 a chipcommon core? */
3302 + si->numcores = 1;
3303 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3304 + if (sb_coreid(&si->sb) != SB_CC)
3305 + cc = NULL;
3306 +
3307 + /* determine chip id and rev */
3308 + if (cc) {
3309 + /* chip common core found! */
3310 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3311 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3312 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3313 + } else {
3314 + /* no chip common core -- must convert device id to chip id */
3315 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3316 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3317 + sb_setcoreidx(&si->sb, origidx);
3318 + return NULL;
3319 + }
3320 + }
3321 +
3322 + /* get chipcommon rev */
3323 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3324 +
3325 + /* determine numcores */
3326 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3327 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3328 + else
3329 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3330 +
3331 + /* return to original core */
3332 + sb_setcoreidx(&si->sb, origidx);
3333 +
3334 + /* sanity checks */
3335 + ASSERT(si->sb.chip);
3336 +
3337 + /* scan for cores */
3338 + BCMINIT(sb_scan)(si);
3339 +
3340 + /* fixup necessary chip/core configurations */
3341 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3342 + if (sb_pci_fixcfg(si)) {
3343 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3344 + return NULL;
3345 + }
3346 + }
3347 +
3348 + /* srom_var_init() depends on sb_scan() info */
3349 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3350 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3351 + return (NULL);
3352 + }
3353 +
3354 + if (cc == NULL) {
3355 + /*
3356 + * The chip revision number is hardwired into all
3357 + * of the pci function config rev fields and is
3358 + * independent from the individual core revision numbers.
3359 + * For example, the "A0" silicon of each chip is chip rev 0.
3360 + */
3361 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3362 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3363 + si->sb.chiprev = w & 0xff;
3364 + } else
3365 + si->sb.chiprev = 0;
3366 + }
3367 +
3368 + /* gpio control core is required */
3369 + if (!GOODIDX(si->gpioidx)) {
3370 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3371 + return NULL;
3372 + }
3373 +
3374 + /* get boardtype and boardrev */
3375 + switch (BUSTYPE(si->sb.bustype)) {
3376 + case PCI_BUS:
3377 + /* do a pci config read to get subsystem id and subvendor id */
3378 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3379 + si->sb.boardvendor = w & 0xffff;
3380 + si->sb.boardtype = (w >> 16) & 0xffff;
3381 + break;
3382 +
3383 + case SB_BUS:
3384 + case JTAG_BUS:
3385 + si->sb.boardvendor = VENDOR_BROADCOM;
3386 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3387 + si->sb.boardtype = 0xffff;
3388 + break;
3389 + }
3390 +
3391 + if (si->sb.boardtype == 0) {
3392 + SB_ERROR(("sb_doattach: unknown board type\n"));
3393 + ASSERT(si->sb.boardtype);
3394 + }
3395 +
3396 + /* setup the GPIO based LED powersave register */
3397 + if (si->sb.ccrev >= 16) {
3398 + w = getintvar(*vars, "gpiotimerval");
3399 + if (!w)
3400 + w = DEFAULT_GPIOTIMERVAL;
3401 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3402 + }
3403 +
3404 +
3405 + return (si);
3406 +}
3407 +
3408 +uint
3409 +sb_coreid(sb_t *sbh)
3410 +{
3411 + sb_info_t *si;
3412 + sbconfig_t *sb;
3413 +
3414 + si = SB_INFO(sbh);
3415 + sb = REGS2SB(si->curmap);
3416 +
3417 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3418 +}
3419 +
3420 +uint
3421 +sb_coreidx(sb_t *sbh)
3422 +{
3423 + sb_info_t *si;
3424 +
3425 + si = SB_INFO(sbh);
3426 + return (si->curidx);
3427 +}
3428 +
3429 +/* return current index of core */
3430 +static uint
3431 +_sb_coreidx(sb_info_t *si)
3432 +{
3433 + sbconfig_t *sb;
3434 + uint32 sbaddr = 0;
3435 +
3436 + ASSERT(si);
3437 +
3438 + switch (BUSTYPE(si->sb.bustype)) {
3439 + case SB_BUS:
3440 + sb = REGS2SB(si->curmap);
3441 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3442 + break;
3443 +
3444 + case PCI_BUS:
3445 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3446 + break;
3447 +
3448 +#ifdef BCMJTAG
3449 + case JTAG_BUS:
3450 + sbaddr = (uint32)si->curmap;
3451 + break;
3452 +#endif /* BCMJTAG */
3453 +
3454 + default:
3455 + ASSERT(0);
3456 + }
3457 +
3458 + if (!GOODCOREADDR(sbaddr))
3459 + return BADIDX;
3460 +
3461 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3462 +}
3463 +
3464 +uint
3465 +sb_corevendor(sb_t *sbh)
3466 +{
3467 + sb_info_t *si;
3468 + sbconfig_t *sb;
3469 +
3470 + si = SB_INFO(sbh);
3471 + sb = REGS2SB(si->curmap);
3472 +
3473 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3474 +}
3475 +
3476 +uint
3477 +sb_corerev(sb_t *sbh)
3478 +{
3479 + sb_info_t *si;
3480 + sbconfig_t *sb;
3481 + uint sbidh;
3482 +
3483 + si = SB_INFO(sbh);
3484 + sb = REGS2SB(si->curmap);
3485 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3486 +
3487 + return (SBCOREREV(sbidh));
3488 +}
3489 +
3490 +void *
3491 +sb_osh(sb_t *sbh)
3492 +{
3493 + sb_info_t *si;
3494 +
3495 + si = SB_INFO(sbh);
3496 + return si->osh;
3497 +}
3498 +
3499 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3500 +
3501 +/* set/clear sbtmstatelow core-specific flags */
3502 +uint32
3503 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3504 +{
3505 + sb_info_t *si;
3506 + sbconfig_t *sb;
3507 + uint32 w;
3508 +
3509 + si = SB_INFO(sbh);
3510 + sb = REGS2SB(si->curmap);
3511 +
3512 + ASSERT((val & ~mask) == 0);
3513 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3514 +
3515 + /* mask and set */
3516 + if (mask || val) {
3517 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3518 + W_SBREG(si, &sb->sbtmstatelow, w);
3519 + }
3520 +
3521 + /* return the new value */
3522 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3523 +}
3524 +
3525 +/* set/clear sbtmstatehigh core-specific flags */
3526 +uint32
3527 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3528 +{
3529 + sb_info_t *si;
3530 + sbconfig_t *sb;
3531 + uint32 w;
3532 +
3533 + si = SB_INFO(sbh);
3534 + sb = REGS2SB(si->curmap);
3535 +
3536 + ASSERT((val & ~mask) == 0);
3537 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3538 +
3539 + /* mask and set */
3540 + if (mask || val) {
3541 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3542 + W_SBREG(si, &sb->sbtmstatehigh, w);
3543 + }
3544 +
3545 + /* return the new value */
3546 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3547 +}
3548 +
3549 +/* caller needs to take care of core-specific bist hazards */
3550 +int
3551 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3552 +{
3553 + uint32 sblo;
3554 + uint coreidx;
3555 + sb_info_t *si;
3556 + int result = 0;
3557 +
3558 + si = SB_INFO(sbh);
3559 +
3560 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3561 + if (!GOODIDX(coreidx))
3562 + result = BCME_ERROR;
3563 + else {
3564 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3565 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3566 +
3567 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3568 +
3569 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3570 + result = BCME_ERROR;
3571 +
3572 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3573 + }
3574 +
3575 + return result;
3576 +}
3577 +
3578 +bool
3579 +sb_iscoreup(sb_t *sbh)
3580 +{
3581 + sb_info_t *si;
3582 + sbconfig_t *sb;
3583 +
3584 + si = SB_INFO(sbh);
3585 + sb = REGS2SB(si->curmap);
3586 +
3587 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3588 +}
3589 +
3590 +/*
3591 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3592 + * switch back to the original core, and return the new value.
3593 + */
3594 +static uint
3595 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3596 +{
3597 + uint origidx;
3598 + uint32 *r;
3599 + uint w;
3600 + uint intr_val = 0;
3601 +
3602 + ASSERT(GOODIDX(coreidx));
3603 + ASSERT(regoff < SB_CORE_SIZE);
3604 + ASSERT((val & ~mask) == 0);
3605 +
3606 + INTR_OFF(si, intr_val);
3607 +
3608 + /* save current core index */
3609 + origidx = sb_coreidx(&si->sb);
3610 +
3611 + /* switch core */
3612 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3613 +
3614 + /* mask and set */
3615 + if (mask || val) {
3616 + if (regoff >= SBCONFIGOFF) {
3617 + w = (R_SBREG(si, r) & ~mask) | val;
3618 + W_SBREG(si, r, w);
3619 + } else {
3620 + w = (R_REG(r) & ~mask) | val;
3621 + W_REG(r, w);
3622 + }
3623 + }
3624 +
3625 + /* readback */
3626 + if (regoff >= SBCONFIGOFF)
3627 + w = R_SBREG(si, r);
3628 + else
3629 + w = R_REG(r);
3630 +
3631 + /* restore core index */
3632 + if (origidx != coreidx)
3633 + sb_setcoreidx(&si->sb, origidx);
3634 +
3635 + INTR_RESTORE(si, intr_val);
3636 + return (w);
3637 +}
3638 +
3639 +#define DWORD_ALIGN(x) (x & ~(0x03))
3640 +#define BYTE_POS(x) (x & 0x3)
3641 +#define WORD_POS(x) (x & 0x1)
3642 +
3643 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3644 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3645 +
3646 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3647 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3648 +
3649 +#define read_pci_cfg_byte(a) \
3650 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3651 +
3652 +#define read_pci_cfg_write(a) \
3653 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3654 +
3655 +
3656 +/* scan the sb enumerated space to identify all cores */
3657 +static void
3658 +BCMINITFN(sb_scan)(sb_info_t *si)
3659 +{
3660 + uint origidx;
3661 + uint i;
3662 + bool pci;
3663 + uint pciidx;
3664 + uint pcirev;
3665 +
3666 +
3667 +
3668 + /* numcores should already be set */
3669 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3670 +
3671 + /* save current core index */
3672 + origidx = sb_coreidx(&si->sb);
3673 +
3674 + si->sb.buscorerev = NOREV;
3675 + si->sb.buscoreidx = BADIDX;
3676 +
3677 + si->gpioidx = BADIDX;
3678 +
3679 + pci = FALSE;
3680 + pcirev = NOREV;
3681 + pciidx = BADIDX;
3682 +
3683 + for (i = 0; i < si->numcores; i++) {
3684 + sb_setcoreidx(&si->sb, i);
3685 + si->coreid[i] = sb_coreid(&si->sb);
3686 +
3687 + if (si->coreid[i] == SB_PCI) {
3688 + pciidx = i;
3689 + pcirev = sb_corerev(&si->sb);
3690 + pci = TRUE;
3691 + }
3692 + }
3693 + if (pci) {
3694 + si->sb.buscoretype = SB_PCI;
3695 + si->sb.buscorerev = pcirev;
3696 + si->sb.buscoreidx = pciidx;
3697 + }
3698 +
3699 + /*
3700 + * Find the gpio "controlling core" type and index.
3701 + * Precedence:
3702 + * - if there's a chip common core - use that
3703 + * - else if there's a pci core (rev >= 2) - use that
3704 + * - else there had better be an extif core (4710 only)
3705 + */
3706 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3707 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3708 + si->gpioid = SB_CC;
3709 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3710 + si->gpioidx = si->sb.buscoreidx;
3711 + si->gpioid = SB_PCI;
3712 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3713 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3714 + si->gpioid = SB_EXTIF;
3715 + } else
3716 + ASSERT(si->gpioidx != BADIDX);
3717 +
3718 + /* return to original core index */
3719 + sb_setcoreidx(&si->sb, origidx);
3720 +}
3721 +
3722 +/* may be called with core in reset */
3723 +void
3724 +sb_detach(sb_t *sbh)
3725 +{
3726 + sb_info_t *si;
3727 + uint idx;
3728 +
3729 + si = SB_INFO(sbh);
3730 +
3731 + if (si == NULL)
3732 + return;
3733 +
3734 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3735 + for (idx = 0; idx < SB_MAXCORES; idx++)
3736 + if (si->regs[idx]) {
3737 + REG_UNMAP(si->regs[idx]);
3738 + si->regs[idx] = NULL;
3739 + }
3740 +
3741 + if (si != &ksi)
3742 + MFREE(si->osh, si, sizeof (sb_info_t));
3743 +}
3744 +
3745 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3746 +static uint
3747 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3748 +{
3749 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3750 + return (BCM4710_DEVICE_ID);
3751 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3752 + return (BCM4402_DEVICE_ID);
3753 + if (pcidev == BCM4401_ENET_ID)
3754 + return (BCM4402_DEVICE_ID);
3755 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3756 + return (BCM4307_DEVICE_ID);
3757 + if (pcidev == BCM4301_DEVICE_ID)
3758 + return (BCM4301_DEVICE_ID);
3759 +
3760 + return (0);
3761 +}
3762 +
3763 +/* convert chip number to number of i/o cores */
3764 +static uint
3765 +BCMINITFN(sb_chip2numcores)(uint chip)
3766 +{
3767 + if (chip == BCM4710_DEVICE_ID)
3768 + return (9);
3769 + if (chip == BCM4402_DEVICE_ID)
3770 + return (3);
3771 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3772 + return (5);
3773 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3774 + return (6);
3775 + if (chip == BCM4704_DEVICE_ID)
3776 + return (9);
3777 + if (chip == BCM5365_DEVICE_ID)
3778 + return (7);
3779 +
3780 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3781 + ASSERT(0);
3782 + return (1);
3783 +}
3784 +
3785 +/* return index of coreid or BADIDX if not found */
3786 +static uint
3787 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3788 +{
3789 + uint found;
3790 + uint i;
3791 +
3792 + found = 0;
3793 +
3794 + for (i = 0; i < si->numcores; i++)
3795 + if (si->coreid[i] == coreid) {
3796 + if (found == coreunit)
3797 + return (i);
3798 + found++;
3799 + }
3800 +
3801 + return (BADIDX);
3802 +}
3803 +
3804 +/*
3805 + * this function changes logical "focus" to the indiciated core,
3806 + * must be called with interrupt off.
3807 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3808 + */
3809 +void*
3810 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3811 +{
3812 + sb_info_t *si;
3813 + uint32 sbaddr;
3814 +
3815 + si = SB_INFO(sbh);
3816 +
3817 + if (coreidx >= si->numcores)
3818 + return (NULL);
3819 +
3820 + /*
3821 + * If the user has provided an interrupt mask enabled function,
3822 + * then assert interrupts are disabled before switching the core.
3823 + */
3824 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3825 +
3826 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3827 +
3828 + switch (BUSTYPE(si->sb.bustype)) {
3829 + case SB_BUS:
3830 + /* map new one */
3831 + if (!si->regs[coreidx]) {
3832 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3833 + ASSERT(GOODREGS(si->regs[coreidx]));
3834 + }
3835 + si->curmap = si->regs[coreidx];
3836 + break;
3837 +
3838 + case PCI_BUS:
3839 + /* point bar0 window */
3840 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3841 + break;
3842 +
3843 +#ifdef BCMJTAG
3844 + case JTAG_BUS:
3845 + /* map new one */
3846 + if (!si->regs[coreidx]) {
3847 + si->regs[coreidx] = (void *)sbaddr;
3848 + ASSERT(GOODREGS(si->regs[coreidx]));
3849 + }
3850 + si->curmap = si->regs[coreidx];
3851 + break;
3852 +#endif /* BCMJTAG */
3853 + }
3854 +
3855 + si->curidx = coreidx;
3856 +
3857 + return (si->curmap);
3858 +}
3859 +
3860 +/*
3861 + * this function changes logical "focus" to the indiciated core,
3862 + * must be called with interrupt off.
3863 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3864 + */
3865 +void*
3866 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3867 +{
3868 + sb_info_t *si;
3869 + uint idx;
3870 +
3871 + si = SB_INFO(sbh);
3872 + idx = sb_findcoreidx(si, coreid, coreunit);
3873 + if (!GOODIDX(idx))
3874 + return (NULL);
3875 +
3876 + return (sb_setcoreidx(sbh, idx));
3877 +}
3878 +
3879 +/* return chip number */
3880 +uint
3881 +BCMINITFN(sb_chip)(sb_t *sbh)
3882 +{
3883 + sb_info_t *si;
3884 +
3885 + si = SB_INFO(sbh);
3886 + return (si->sb.chip);
3887 +}
3888 +
3889 +/* return chip revision number */
3890 +uint
3891 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3892 +{
3893 + sb_info_t *si;
3894 +
3895 + si = SB_INFO(sbh);
3896 + return (si->sb.chiprev);
3897 +}
3898 +
3899 +/* return chip common revision number */
3900 +uint
3901 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3902 +{
3903 + sb_info_t *si;
3904 +
3905 + si = SB_INFO(sbh);
3906 + return (si->sb.ccrev);
3907 +}
3908 +
3909 +/* return chip package option */
3910 +uint
3911 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3912 +{
3913 + sb_info_t *si;
3914 +
3915 + si = SB_INFO(sbh);
3916 + return (si->sb.chippkg);
3917 +}
3918 +
3919 +/* return PCI core rev. */
3920 +uint
3921 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3922 +{
3923 + sb_info_t *si;
3924 +
3925 + si = SB_INFO(sbh);
3926 + return (si->sb.buscorerev);
3927 +}
3928 +
3929 +bool
3930 +BCMINITFN(sb_war16165)(sb_t *sbh)
3931 +{
3932 + sb_info_t *si;
3933 +
3934 + si = SB_INFO(sbh);
3935 +
3936 + return (PCI(si) && (si->sb.buscorerev <= 10));
3937 +}
3938 +
3939 +/* return board vendor id */
3940 +uint
3941 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3942 +{
3943 + sb_info_t *si;
3944 +
3945 + si = SB_INFO(sbh);
3946 + return (si->sb.boardvendor);
3947 +}
3948 +
3949 +/* return boardtype */
3950 +uint
3951 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3952 +{
3953 + sb_info_t *si;
3954 + char *var;
3955 +
3956 + si = SB_INFO(sbh);
3957 +
3958 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3959 + /* boardtype format is a hex string */
3960 + si->sb.boardtype = getintvar(NULL, "boardtype");
3961 +
3962 + /* backward compatibility for older boardtype string format */
3963 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3964 + if (!strcmp(var, "bcm94710dev"))
3965 + si->sb.boardtype = BCM94710D_BOARD;
3966 + else if (!strcmp(var, "bcm94710ap"))
3967 + si->sb.boardtype = BCM94710AP_BOARD;
3968 + else if (!strcmp(var, "bu4710"))
3969 + si->sb.boardtype = BU4710_BOARD;
3970 + else if (!strcmp(var, "bcm94702mn"))
3971 + si->sb.boardtype = BCM94702MN_BOARD;
3972 + else if (!strcmp(var, "bcm94710r1"))
3973 + si->sb.boardtype = BCM94710R1_BOARD;
3974 + else if (!strcmp(var, "bcm94710r4"))
3975 + si->sb.boardtype = BCM94710R4_BOARD;
3976 + else if (!strcmp(var, "bcm94702cpci"))
3977 + si->sb.boardtype = BCM94702CPCI_BOARD;
3978 + else if (!strcmp(var, "bcm95380_rr"))
3979 + si->sb.boardtype = BCM95380RR_BOARD;
3980 + }
3981 + }
3982 +
3983 + return (si->sb.boardtype);
3984 +}
3985 +
3986 +/* return bus type of sbh device */
3987 +uint
3988 +sb_bus(sb_t *sbh)
3989 +{
3990 + sb_info_t *si;
3991 +
3992 + si = SB_INFO(sbh);
3993 + return (si->sb.bustype);
3994 +}
3995 +
3996 +/* return bus core type */
3997 +uint
3998 +sb_buscoretype(sb_t *sbh)
3999 +{
4000 + sb_info_t *si;
4001 +
4002 + si = SB_INFO(sbh);
4003 +
4004 + return (si->sb.buscoretype);
4005 +}
4006 +
4007 +/* return bus core revision */
4008 +uint
4009 +sb_buscorerev(sb_t *sbh)
4010 +{
4011 + sb_info_t *si;
4012 + si = SB_INFO(sbh);
4013 +
4014 + return (si->sb.buscorerev);
4015 +}
4016 +
4017 +/* return list of found cores */
4018 +uint
4019 +sb_corelist(sb_t *sbh, uint coreid[])
4020 +{
4021 + sb_info_t *si;
4022 +
4023 + si = SB_INFO(sbh);
4024 +
4025 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
4026 + return (si->numcores);
4027 +}
4028 +
4029 +/* return current register mapping */
4030 +void *
4031 +sb_coreregs(sb_t *sbh)
4032 +{
4033 + sb_info_t *si;
4034 +
4035 + si = SB_INFO(sbh);
4036 + ASSERT(GOODREGS(si->curmap));
4037 +
4038 + return (si->curmap);
4039 +}
4040 +
4041 +
4042 +/* do buffered registers update */
4043 +void
4044 +sb_commit(sb_t *sbh)
4045 +{
4046 + sb_info_t *si;
4047 + uint origidx;
4048 + uint intr_val = 0;
4049 +
4050 + si = SB_INFO(sbh);
4051 +
4052 + origidx = si->curidx;
4053 + ASSERT(GOODIDX(origidx));
4054 +
4055 + INTR_OFF(si, intr_val);
4056 +
4057 + /* switch over to chipcommon core if there is one, else use pci */
4058 + if (si->sb.ccrev != NOREV) {
4059 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4060 +
4061 + /* do the buffer registers update */
4062 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4063 + W_REG(&ccregs->broadcastdata, 0x0);
4064 + } else if (PCI(si)) {
4065 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4066 +
4067 + /* do the buffer registers update */
4068 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4069 + W_REG(&pciregs->bcastdata, 0x0);
4070 + } else
4071 + ASSERT(0);
4072 +
4073 + /* restore core index */
4074 + sb_setcoreidx(sbh, origidx);
4075 + INTR_RESTORE(si, intr_val);
4076 +}
4077 +
4078 +/* reset and re-enable a core */
4079 +void
4080 +sb_core_reset(sb_t *sbh, uint32 bits)
4081 +{
4082 + sb_info_t *si;
4083 + sbconfig_t *sb;
4084 + volatile uint32 dummy;
4085 +
4086 + si = SB_INFO(sbh);
4087 + ASSERT(GOODREGS(si->curmap));
4088 + sb = REGS2SB(si->curmap);
4089 +
4090 + /*
4091 + * Must do the disable sequence first to work for arbitrary current core state.
4092 + */
4093 + sb_core_disable(sbh, bits);
4094 +
4095 + /*
4096 + * Now do the initialization sequence.
4097 + */
4098 +
4099 + /* set reset while enabling the clock and forcing them on throughout the core */
4100 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4101 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4102 + OSL_DELAY(1);
4103 +
4104 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4105 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4106 + }
4107 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4108 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4109 + }
4110 +
4111 + /* clear reset and allow it to propagate throughout the core */
4112 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4113 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4114 + OSL_DELAY(1);
4115 +
4116 + /* leave clock enabled */
4117 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4118 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4119 + OSL_DELAY(1);
4120 +}
4121 +
4122 +void
4123 +sb_core_tofixup(sb_t *sbh)
4124 +{
4125 + sb_info_t *si;
4126 + sbconfig_t *sb;
4127 +
4128 + si = SB_INFO(sbh);
4129 +
4130 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4131 + return;
4132 +
4133 + ASSERT(GOODREGS(si->curmap));
4134 + sb = REGS2SB(si->curmap);
4135 +
4136 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4137 + SET_SBREG(si, &sb->sbimconfiglow,
4138 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4139 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4140 + } else {
4141 + if (sb_coreid(sbh) == SB_PCI) {
4142 + SET_SBREG(si, &sb->sbimconfiglow,
4143 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4144 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4145 + } else {
4146 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4147 + }
4148 + }
4149 +
4150 + sb_commit(sbh);
4151 +}
4152 +
4153 +/*
4154 + * Set the initiator timeout for the "master core".
4155 + * The master core is defined to be the core in control
4156 + * of the chip and so it issues accesses to non-memory
4157 + * locations (Because of dma *any* core can access memeory).
4158 + *
4159 + * The routine uses the bus to decide who is the master:
4160 + * SB_BUS => mips
4161 + * JTAG_BUS => chipc
4162 + * PCI_BUS => pci
4163 + *
4164 + * This routine exists so callers can disable initiator
4165 + * timeouts so accesses to very slow devices like otp
4166 + * won't cause an abort. The routine allows arbitrary
4167 + * settings of the service and request timeouts, though.
4168 + *
4169 + * Returns the timeout state before changing it or -1
4170 + * on error.
4171 + */
4172 +
4173 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4174 +
4175 +uint32
4176 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4177 +{
4178 + sb_info_t *si;
4179 + uint origidx, idx;
4180 + uint intr_val = 0;
4181 + uint32 tmp, ret = 0xffffffff;
4182 + sbconfig_t *sb;
4183 +
4184 + si = SB_INFO(sbh);
4185 +
4186 + if ((to & ~TO_MASK) != 0)
4187 + return ret;
4188 +
4189 + /* Figure out the master core */
4190 + idx = BADIDX;
4191 + switch (BUSTYPE(si->sb.bustype)) {
4192 + case PCI_BUS:
4193 + idx = si->sb.buscoreidx;
4194 + break;
4195 + case JTAG_BUS:
4196 + idx = SB_CC_IDX;
4197 + break;
4198 + case SB_BUS:
4199 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4200 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4201 + break;
4202 + default:
4203 + ASSERT(0);
4204 + }
4205 + if (idx == BADIDX)
4206 + return ret;
4207 +
4208 + INTR_OFF(si, intr_val);
4209 + origidx = sb_coreidx(sbh);
4210 +
4211 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4212 +
4213 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4214 + ret = tmp & TO_MASK;
4215 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4216 +
4217 + sb_commit(sbh);
4218 + sb_setcoreidx(sbh, origidx);
4219 + INTR_RESTORE(si, intr_val);
4220 + return ret;
4221 +}
4222 +
4223 +void
4224 +sb_core_disable(sb_t *sbh, uint32 bits)
4225 +{
4226 + sb_info_t *si;
4227 + volatile uint32 dummy;
4228 + uint32 rej;
4229 + sbconfig_t *sb;
4230 +
4231 + si = SB_INFO(sbh);
4232 +
4233 + ASSERT(GOODREGS(si->curmap));
4234 + sb = REGS2SB(si->curmap);
4235 +
4236 + /* if core is already in reset, just return */
4237 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4238 + return;
4239 +
4240 + /* reject value changed between sonics 2.2 and 2.3 */
4241 + if (si->sb.sonicsrev == SONICS_2_2)
4242 + rej = (1 << SBTML_REJ_SHIFT);
4243 + else
4244 + rej = (2 << SBTML_REJ_SHIFT);
4245 +
4246 + /* if clocks are not enabled, put into reset and return */
4247 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4248 + goto disable;
4249 +
4250 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4251 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4252 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4253 + OSL_DELAY(1);
4254 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4255 +
4256 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4257 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4258 + dummy = R_SBREG(si, &sb->sbimstate);
4259 + OSL_DELAY(1);
4260 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4261 + }
4262 +
4263 + /* set reset and reject while enabling the clocks */
4264 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4265 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4266 + OSL_DELAY(10);
4267 +
4268 + /* don't forget to clear the initiator reject bit */
4269 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4270 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4271 +
4272 +disable:
4273 + /* leave reset and reject asserted */
4274 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4275 + OSL_DELAY(1);
4276 +}
4277 +
4278 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4279 +void
4280 +sb_watchdog(sb_t *sbh, uint ticks)
4281 +{
4282 + sb_info_t *si = SB_INFO(sbh);
4283 +
4284 + /* instant NMI */
4285 + switch (si->gpioid) {
4286 + case SB_CC:
4287 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4288 + break;
4289 + case SB_EXTIF:
4290 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4291 + break;
4292 + }
4293 +}
4294 +
4295 +
4296 +/*
4297 + * Configure the pci core for pci client (NIC) action
4298 + * coremask is the bitvec of cores by index to be enabled.
4299 + */
4300 +void
4301 +sb_pci_setup(sb_t *sbh, uint coremask)
4302 +{
4303 + sb_info_t *si;
4304 + sbconfig_t *sb;
4305 + sbpciregs_t *pciregs;
4306 + uint32 sbflag;
4307 + uint32 w;
4308 + uint idx;
4309 +
4310 + si = SB_INFO(sbh);
4311 +
4312 + /* if not pci bus, we're done */
4313 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4314 + return;
4315 +
4316 + ASSERT(PCI(si));
4317 + ASSERT(si->sb.buscoreidx != BADIDX);
4318 +
4319 + /* get current core index */
4320 + idx = si->curidx;
4321 +
4322 + /* we interrupt on this backplane flag number */
4323 + ASSERT(GOODREGS(si->curmap));
4324 + sb = REGS2SB(si->curmap);
4325 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4326 +
4327 + /* switch over to pci core */
4328 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4329 + sb = REGS2SB(pciregs);
4330 +
4331 + /*
4332 + * Enable sb->pci interrupts. Assume
4333 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4334 + */
4335 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4336 + /* pci config write to set this core bit in PCIIntMask */
4337 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4338 + w |= (coremask << PCI_SBIM_SHIFT);
4339 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4340 + } else {
4341 + /* set sbintvec bit for our flag number */
4342 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4343 + }
4344 +
4345 + if (PCI(si)) {
4346 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4347 + if (si->sb.buscorerev >= 11)
4348 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4349 + if (si->sb.buscorerev < 5) {
4350 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4351 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4352 + sb_commit(sbh);
4353 + }
4354 + }
4355 +
4356 + /* switch back to previous core */
4357 + sb_setcoreidx(sbh, idx);
4358 +}
4359 +
4360 +uint32
4361 +sb_base(uint32 admatch)
4362 +{
4363 + uint32 base;
4364 + uint type;
4365 +
4366 + type = admatch & SBAM_TYPE_MASK;
4367 + ASSERT(type < 3);
4368 +
4369 + base = 0;
4370 +
4371 + if (type == 0) {
4372 + base = admatch & SBAM_BASE0_MASK;
4373 + } else if (type == 1) {
4374 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4375 + base = admatch & SBAM_BASE1_MASK;
4376 + } else if (type == 2) {
4377 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4378 + base = admatch & SBAM_BASE2_MASK;
4379 + }
4380 +
4381 + return (base);
4382 +}
4383 +
4384 +uint32
4385 +sb_size(uint32 admatch)
4386 +{
4387 + uint32 size;
4388 + uint type;
4389 +
4390 + type = admatch & SBAM_TYPE_MASK;
4391 + ASSERT(type < 3);
4392 +
4393 + size = 0;
4394 +
4395 + if (type == 0) {
4396 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4397 + } else if (type == 1) {
4398 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4399 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4400 + } else if (type == 2) {
4401 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4402 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4403 + }
4404 +
4405 + return (size);
4406 +}
4407 +
4408 +/* return the core-type instantiation # of the current core */
4409 +uint
4410 +sb_coreunit(sb_t *sbh)
4411 +{
4412 + sb_info_t *si;
4413 + uint idx;
4414 + uint coreid;
4415 + uint coreunit;
4416 + uint i;
4417 +
4418 + si = SB_INFO(sbh);
4419 + coreunit = 0;
4420 +
4421 + idx = si->curidx;
4422 +
4423 + ASSERT(GOODREGS(si->curmap));
4424 + coreid = sb_coreid(sbh);
4425 +
4426 + /* count the cores of our type */
4427 + for (i = 0; i < idx; i++)
4428 + if (si->coreid[i] == coreid)
4429 + coreunit++;
4430 +
4431 + return (coreunit);
4432 +}
4433 +
4434 +static INLINE uint32
4435 +factor6(uint32 x)
4436 +{
4437 + switch (x) {
4438 + case CC_F6_2: return 2;
4439 + case CC_F6_3: return 3;
4440 + case CC_F6_4: return 4;
4441 + case CC_F6_5: return 5;
4442 + case CC_F6_6: return 6;
4443 + case CC_F6_7: return 7;
4444 + default: return 0;
4445 + }
4446 +}
4447 +
4448 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4449 +uint32
4450 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4451 +{
4452 + uint32 n1, n2, clock, m1, m2, m3, mc;
4453 +
4454 + n1 = n & CN_N1_MASK;
4455 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4456 +
4457 + if (pll_type == PLL_TYPE6) {
4458 + if (m & CC_T6_MMASK)
4459 + return CC_T6_M1;
4460 + else
4461 + return CC_T6_M0;
4462 + } else if ((pll_type == PLL_TYPE1) ||
4463 + (pll_type == PLL_TYPE3) ||
4464 + (pll_type == PLL_TYPE4) ||
4465 + (pll_type == PLL_TYPE7)) {
4466 + n1 = factor6(n1);
4467 + n2 += CC_F5_BIAS;
4468 + } else if (pll_type == PLL_TYPE2) {
4469 + n1 += CC_T2_BIAS;
4470 + n2 += CC_T2_BIAS;
4471 + ASSERT((n1 >= 2) && (n1 <= 7));
4472 + ASSERT((n2 >= 5) && (n2 <= 23));
4473 + } else if (pll_type == PLL_TYPE5) {
4474 + return (100000000);
4475 + } else
4476 + ASSERT(0);
4477 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4478 + if ((pll_type == PLL_TYPE3) ||
4479 + (pll_type == PLL_TYPE7)) {
4480 + clock = CC_CLOCK_BASE2 * n1 * n2;
4481 + }
4482 + else
4483 + clock = CC_CLOCK_BASE1 * n1 * n2;
4484 +
4485 + if (clock == 0)
4486 + return 0;
4487 +
4488 + m1 = m & CC_M1_MASK;
4489 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4490 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4491 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4492 +
4493 + if ((pll_type == PLL_TYPE1) ||
4494 + (pll_type == PLL_TYPE3) ||
4495 + (pll_type == PLL_TYPE4) ||
4496 + (pll_type == PLL_TYPE7)) {
4497 + m1 = factor6(m1);
4498 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4499 + m2 += CC_F5_BIAS;
4500 + else
4501 + m2 = factor6(m2);
4502 + m3 = factor6(m3);
4503 +
4504 + switch (mc) {
4505 + case CC_MC_BYPASS: return (clock);
4506 + case CC_MC_M1: return (clock / m1);
4507 + case CC_MC_M1M2: return (clock / (m1 * m2));
4508 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4509 + case CC_MC_M1M3: return (clock / (m1 * m3));
4510 + default: return (0);
4511 + }
4512 + } else {
4513 + ASSERT(pll_type == PLL_TYPE2);
4514 +
4515 + m1 += CC_T2_BIAS;
4516 + m2 += CC_T2M2_BIAS;
4517 + m3 += CC_T2_BIAS;
4518 + ASSERT((m1 >= 2) && (m1 <= 7));
4519 + ASSERT((m2 >= 3) && (m2 <= 10));
4520 + ASSERT((m3 >= 2) && (m3 <= 7));
4521 +
4522 + if ((mc & CC_T2MC_M1BYP) == 0)
4523 + clock /= m1;
4524 + if ((mc & CC_T2MC_M2BYP) == 0)
4525 + clock /= m2;
4526 + if ((mc & CC_T2MC_M3BYP) == 0)
4527 + clock /= m3;
4528 +
4529 + return(clock);
4530 + }
4531 +}
4532 +
4533 +/* returns the current speed the SB is running at */
4534 +uint32
4535 +sb_clock(sb_t *sbh)
4536 +{
4537 + sb_info_t *si;
4538 + extifregs_t *eir;
4539 + chipcregs_t *cc;
4540 + uint32 n, m;
4541 + uint idx;
4542 + uint32 pll_type, rate;
4543 + uint intr_val = 0;
4544 +
4545 + si = SB_INFO(sbh);
4546 + idx = si->curidx;
4547 + pll_type = PLL_TYPE1;
4548 +
4549 + INTR_OFF(si, intr_val);
4550 +
4551 + /* switch to extif or chipc core */
4552 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4553 + n = R_REG(&eir->clockcontrol_n);
4554 + m = R_REG(&eir->clockcontrol_sb);
4555 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4556 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4557 + n = R_REG(&cc->clockcontrol_n);
4558 + if (pll_type == PLL_TYPE6)
4559 + m = R_REG(&cc->clockcontrol_mips);
4560 + else if (pll_type == PLL_TYPE3)
4561 + {
4562 + // Added by Chen-I for 5365
4563 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4564 + m = R_REG(&cc->clockcontrol_sb);
4565 + else
4566 + m = R_REG(&cc->clockcontrol_m2);
4567 + }
4568 + else
4569 + m = R_REG(&cc->clockcontrol_sb);
4570 + } else {
4571 + INTR_RESTORE(si, intr_val);
4572 + return 0;
4573 + }
4574 +
4575 + // Added by Chen-I for 5365
4576 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4577 + {
4578 + rate = 100000000;
4579 + }
4580 + else
4581 + {
4582 + /* calculate rate */
4583 + rate = sb_clock_rate(pll_type, n, m);
4584 + if (pll_type == PLL_TYPE3)
4585 + rate = rate / 2;
4586 + }
4587 +
4588 + /* switch back to previous core */
4589 + sb_setcoreidx(sbh, idx);
4590 +
4591 + INTR_RESTORE(si, intr_val);
4592 +
4593 + return rate;
4594 +}
4595 +
4596 +/* change logical "focus" to the gpio core for optimized access */
4597 +void*
4598 +sb_gpiosetcore(sb_t *sbh)
4599 +{
4600 + sb_info_t *si;
4601 +
4602 + si = SB_INFO(sbh);
4603 +
4604 + return (sb_setcoreidx(sbh, si->gpioidx));
4605 +}
4606 +
4607 +/* mask&set gpiocontrol bits */
4608 +uint32
4609 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4610 +{
4611 + sb_info_t *si;
4612 + uint regoff;
4613 +
4614 + si = SB_INFO(sbh);
4615 + regoff = 0;
4616 +
4617 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4618 +
4619 + /* gpios could be shared on router platforms */
4620 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4621 + mask = priority ? (sb_gpioreservation & mask) :
4622 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4623 + val &= mask;
4624 + }
4625 +
4626 + switch (si->gpioid) {
4627 + case SB_CC:
4628 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4629 + break;
4630 +
4631 + case SB_PCI:
4632 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4633 + break;
4634 +
4635 + case SB_EXTIF:
4636 + return (0);
4637 + }
4638 +
4639 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4640 +}
4641 +
4642 +/* mask&set gpio output enable bits */
4643 +uint32
4644 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4645 +{
4646 + sb_info_t *si;
4647 + uint regoff;
4648 +
4649 + si = SB_INFO(sbh);
4650 + regoff = 0;
4651 +
4652 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4653 +
4654 + /* gpios could be shared on router platforms */
4655 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4656 + mask = priority ? (sb_gpioreservation & mask) :
4657 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4658 + val &= mask;
4659 + }
4660 +
4661 + switch (si->gpioid) {
4662 + case SB_CC:
4663 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4664 + break;
4665 +
4666 + case SB_PCI:
4667 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4668 + break;
4669 +
4670 + case SB_EXTIF:
4671 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4672 + break;
4673 + }
4674 +
4675 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4676 +}
4677 +
4678 +/* mask&set gpio output bits */
4679 +uint32
4680 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4681 +{
4682 + sb_info_t *si;
4683 + uint regoff;
4684 +
4685 + si = SB_INFO(sbh);
4686 + regoff = 0;
4687 +
4688 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4689 +
4690 + /* gpios could be shared on router platforms */
4691 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4692 + mask = priority ? (sb_gpioreservation & mask) :
4693 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4694 + val &= mask;
4695 + }
4696 +
4697 + switch (si->gpioid) {
4698 + case SB_CC:
4699 + regoff = OFFSETOF(chipcregs_t, gpioout);
4700 + break;
4701 +
4702 + case SB_PCI:
4703 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4704 + break;
4705 +
4706 + case SB_EXTIF:
4707 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4708 + break;
4709 + }
4710 +
4711 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4712 +}
4713 +
4714 +/* reserve one gpio */
4715 +uint32
4716 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4717 +{
4718 + sb_info_t *si;
4719 +
4720 + si = SB_INFO(sbh);
4721 +
4722 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4723 +
4724 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4725 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4726 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4727 + return -1;
4728 + }
4729 + /* make sure only one bit is set */
4730 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4731 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4732 + return -1;
4733 + }
4734 +
4735 + /* already reserved */
4736 + if (sb_gpioreservation & gpio_bitmask)
4737 + return -1;
4738 + /* set reservation */
4739 + sb_gpioreservation |= gpio_bitmask;
4740 +
4741 + return sb_gpioreservation;
4742 +}
4743 +
4744 +/* release one gpio */
4745 +/*
4746 + * releasing the gpio doesn't change the current value on the GPIO last write value
4747 + * persists till some one overwrites it
4748 +*/
4749 +
4750 +uint32
4751 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4752 +{
4753 + sb_info_t *si;
4754 +
4755 + si = SB_INFO(sbh);
4756 +
4757 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4758 +
4759 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4760 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4761 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4762 + return -1;
4763 + }
4764 + /* make sure only one bit is set */
4765 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4766 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4767 + return -1;
4768 + }
4769 +
4770 + /* already released */
4771 + if (!(sb_gpioreservation & gpio_bitmask))
4772 + return -1;
4773 +
4774 + /* clear reservation */
4775 + sb_gpioreservation &= ~gpio_bitmask;
4776 +
4777 + return sb_gpioreservation;
4778 +}
4779 +
4780 +/* return the current gpioin register value */
4781 +uint32
4782 +sb_gpioin(sb_t *sbh)
4783 +{
4784 + sb_info_t *si;
4785 + uint regoff;
4786 +
4787 + si = SB_INFO(sbh);
4788 + regoff = 0;
4789 +
4790 + switch (si->gpioid) {
4791 + case SB_CC:
4792 + regoff = OFFSETOF(chipcregs_t, gpioin);
4793 + break;
4794 +
4795 + case SB_PCI:
4796 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4797 + break;
4798 +
4799 + case SB_EXTIF:
4800 + regoff = OFFSETOF(extifregs_t, gpioin);
4801 + break;
4802 + }
4803 +
4804 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4805 +}
4806 +
4807 +/* mask&set gpio interrupt polarity bits */
4808 +uint32
4809 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4810 +{
4811 + sb_info_t *si;
4812 + uint regoff;
4813 +
4814 + si = SB_INFO(sbh);
4815 + regoff = 0;
4816 +
4817 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4818 +
4819 + /* gpios could be shared on router platforms */
4820 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4821 + mask = priority ? (sb_gpioreservation & mask) :
4822 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4823 + val &= mask;
4824 + }
4825 +
4826 + switch (si->gpioid) {
4827 + case SB_CC:
4828 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4829 + break;
4830 +
4831 + case SB_PCI:
4832 + /* pci gpio implementation does not support interrupt polarity */
4833 + ASSERT(0);
4834 + break;
4835 +
4836 + case SB_EXTIF:
4837 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4838 + break;
4839 + }
4840 +
4841 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4842 +}
4843 +
4844 +/* mask&set gpio interrupt mask bits */
4845 +uint32
4846 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4847 +{
4848 + sb_info_t *si;
4849 + uint regoff;
4850 +
4851 + si = SB_INFO(sbh);
4852 + regoff = 0;
4853 +
4854 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4855 +
4856 + /* gpios could be shared on router platforms */
4857 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4858 + mask = priority ? (sb_gpioreservation & mask) :
4859 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4860 + val &= mask;
4861 + }
4862 +
4863 + switch (si->gpioid) {
4864 + case SB_CC:
4865 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4866 + break;
4867 +
4868 + case SB_PCI:
4869 + /* pci gpio implementation does not support interrupt mask */
4870 + ASSERT(0);
4871 + break;
4872 +
4873 + case SB_EXTIF:
4874 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4875 + break;
4876 + }
4877 +
4878 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4879 +}
4880 +
4881 +/* assign the gpio to an led */
4882 +uint32
4883 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4884 +{
4885 + sb_info_t *si;
4886 +
4887 + si = SB_INFO(sbh);
4888 + if (si->sb.ccrev < 16)
4889 + return -1;
4890 +
4891 + /* gpio led powersave reg */
4892 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4893 +}
4894 +
4895 +/* mask&set gpio timer val */
4896 +uint32
4897 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4898 +{
4899 + sb_info_t *si;
4900 + si = SB_INFO(sbh);
4901 +
4902 + if (si->sb.ccrev < 16)
4903 + return -1;
4904 +
4905 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4906 +}
4907 +
4908 +
4909 +/* return the slow clock source - LPO, XTAL, or PCI */
4910 +static uint
4911 +sb_slowclk_src(sb_info_t *si)
4912 +{
4913 + chipcregs_t *cc;
4914 +
4915 +
4916 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4917 +
4918 + if (si->sb.ccrev < 6) {
4919 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4920 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4921 + return (SCC_SS_PCI);
4922 + else
4923 + return (SCC_SS_XTAL);
4924 + } else if (si->sb.ccrev < 10) {
4925 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4926 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4927 + } else /* Insta-clock */
4928 + return (SCC_SS_XTAL);
4929 +}
4930 +
4931 +/* return the ILP (slowclock) min or max frequency */
4932 +static uint
4933 +sb_slowclk_freq(sb_info_t *si, bool max)
4934 +{
4935 + chipcregs_t *cc;
4936 + uint32 slowclk;
4937 + uint div;
4938 +
4939 +
4940 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4941 +
4942 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4943 +
4944 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4945 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4946 +
4947 + slowclk = sb_slowclk_src(si);
4948 + if (si->sb.ccrev < 6) {
4949 + if (slowclk == SCC_SS_PCI)
4950 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4951 + else
4952 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4953 + } else if (si->sb.ccrev < 10) {
4954 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4955 + if (slowclk == SCC_SS_LPO)
4956 + return (max? LPOMAXFREQ : LPOMINFREQ);
4957 + else if (slowclk == SCC_SS_XTAL)
4958 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4959 + else if (slowclk == SCC_SS_PCI)
4960 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4961 + else
4962 + ASSERT(0);
4963 + } else {
4964 + /* Chipc rev 10 is InstaClock */
4965 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4966 + div = 4 * (div + 1);
4967 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4968 + }
4969 + return (0);
4970 +}
4971 +
4972 +static void
4973 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4974 +{
4975 + chipcregs_t * cc;
4976 + uint slowmaxfreq, pll_delay, slowclk;
4977 + uint pll_on_delay, fref_sel_delay;
4978 +
4979 + pll_delay = PLL_DELAY;
4980 +
4981 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4982 + * since the xtal will also be powered down by dynamic clk control logic.
4983 + */
4984 + slowclk = sb_slowclk_src(si);
4985 + if (slowclk != SCC_SS_XTAL)
4986 + pll_delay += XTAL_ON_DELAY;
4987 +
4988 + /* Starting with 4318 it is ILP that is used for the delays */
4989 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4990 +
4991 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4992 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4993 +
4994 + cc = (chipcregs_t *)chipcregs;
4995 + W_REG(&cc->pll_on_delay, pll_on_delay);
4996 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4997 +}
4998 +
4999 +int
5000 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
5001 +{
5002 + sb_info_t *si;
5003 + uint origidx;
5004 + chipcregs_t *cc;
5005 + uint intr_val = 0;
5006 + uint err = 0;
5007 +
5008 + si = SB_INFO(sbh);
5009 +
5010 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
5011 + if (si->sb.ccrev < 6)
5012 + return 1;
5013 +
5014 + /* chipcommon cores rev10 are a whole new ball game */
5015 + if (si->sb.ccrev >= 10)
5016 + return 1;
5017 +
5018 + if (set && ((*div % 4) || (*div < 4)))
5019 + return 2;
5020 +
5021 + INTR_OFF(si, intr_val);
5022 + origidx = si->curidx;
5023 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5024 + ASSERT(cc != NULL);
5025 +
5026 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
5027 + err = 3;
5028 + goto done;
5029 + }
5030 +
5031 + if (set) {
5032 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
5033 + sb_clkctl_setdelay(sbh, (void *)cc);
5034 + } else
5035 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
5036 +
5037 +done:
5038 + sb_setcoreidx(sbh, origidx);
5039 + INTR_RESTORE(si, intr_val);
5040 + return err;
5041 +}
5042 +
5043 +/* initialize power control delay registers */
5044 +void sb_clkctl_init(sb_t *sbh)
5045 +{
5046 + sb_info_t *si;
5047 + uint origidx;
5048 + chipcregs_t *cc;
5049 +
5050 + si = SB_INFO(sbh);
5051 +
5052 + origidx = si->curidx;
5053 +
5054 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5055 + return;
5056 +
5057 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5058 + goto done;
5059 +
5060 + /* set all Instaclk chip ILP to 1 MHz */
5061 + if (si->sb.ccrev >= 10)
5062 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5063 +
5064 + sb_clkctl_setdelay(si, (void *)cc);
5065 +
5066 +done:
5067 + sb_setcoreidx(sbh, origidx);
5068 +}
5069 +void sb_pwrctl_init(sb_t *sbh)
5070 +{
5071 +sb_clkctl_init(sbh);
5072 +}
5073 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5074 +uint16
5075 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5076 +{
5077 + sb_info_t *si;
5078 + uint origidx;
5079 + chipcregs_t *cc;
5080 + uint slowminfreq;
5081 + uint16 fpdelay;
5082 + uint intr_val = 0;
5083 +
5084 + si = SB_INFO(sbh);
5085 + fpdelay = 0;
5086 + origidx = si->curidx;
5087 +
5088 + INTR_OFF(si, intr_val);
5089 +
5090 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5091 + goto done;
5092 +
5093 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5094 + goto done;
5095 +
5096 + slowminfreq = sb_slowclk_freq(si, FALSE);
5097 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5098 +
5099 +done:
5100 + sb_setcoreidx(sbh, origidx);
5101 + INTR_RESTORE(si, intr_val);
5102 + return (fpdelay);
5103 +}
5104 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5105 +{
5106 +return sb_clkctl_fast_pwrup_delay(sbh);
5107 +}
5108 +/* turn primary xtal and/or pll off/on */
5109 +int
5110 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5111 +{
5112 + sb_info_t *si;
5113 + uint32 in, out, outen;
5114 +
5115 + si = SB_INFO(sbh);
5116 +
5117 + switch (BUSTYPE(si->sb.bustype)) {
5118 + case PCI_BUS:
5119 +
5120 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5121 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5122 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5123 +
5124 + /*
5125 + * Avoid glitching the clock if GPRS is already using it.
5126 + * We can't actually read the state of the PLLPD so we infer it
5127 + * by the value of XTAL_PU which *is* readable via gpioin.
5128 + */
5129 + if (on && (in & PCI_CFG_GPIO_XTAL))
5130 + return (0);
5131 +
5132 + if (what & XTAL)
5133 + outen |= PCI_CFG_GPIO_XTAL;
5134 + if (what & PLL)
5135 + outen |= PCI_CFG_GPIO_PLL;
5136 +
5137 + if (on) {
5138 + /* turn primary xtal on */
5139 + if (what & XTAL) {
5140 + out |= PCI_CFG_GPIO_XTAL;
5141 + if (what & PLL)
5142 + out |= PCI_CFG_GPIO_PLL;
5143 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5144 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5145 + OSL_DELAY(XTAL_ON_DELAY);
5146 + }
5147 +
5148 + /* turn pll on */
5149 + if (what & PLL) {
5150 + out &= ~PCI_CFG_GPIO_PLL;
5151 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5152 + OSL_DELAY(2000);
5153 + }
5154 + } else {
5155 + if (what & XTAL)
5156 + out &= ~PCI_CFG_GPIO_XTAL;
5157 + if (what & PLL)
5158 + out |= PCI_CFG_GPIO_PLL;
5159 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5160 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5161 + }
5162 +
5163 + default:
5164 + return (-1);
5165 + }
5166 +
5167 + return (0);
5168 +}
5169 +
5170 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5171 +{
5172 +return sb_clkctl_xtal(sbh,what,on);
5173 +}
5174 +
5175 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5176 +/* returns true if ignore pll off is set and false if it is not */
5177 +bool
5178 +sb_clkctl_clk(sb_t *sbh, uint mode)
5179 +{
5180 + sb_info_t *si;
5181 + uint origidx;
5182 + chipcregs_t *cc;
5183 + uint32 scc;
5184 + bool forcefastclk=FALSE;
5185 + uint intr_val = 0;
5186 +
5187 + si = SB_INFO(sbh);
5188 +
5189 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5190 + if (si->sb.ccrev < 6)
5191 + return (FALSE);
5192 +
5193 + /* chipcommon cores rev10 are a whole new ball game */
5194 + if (si->sb.ccrev >= 10)
5195 + return (FALSE);
5196 +
5197 + INTR_OFF(si, intr_val);
5198 +
5199 + origidx = si->curidx;
5200 +
5201 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5202 + ASSERT(cc != NULL);
5203 +
5204 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5205 + goto done;
5206 +
5207 + switch (mode) {
5208 + case CLK_FAST: /* force fast (pll) clock */
5209 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5210 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5211 +
5212 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5213 + break;
5214 +
5215 + case CLK_DYNAMIC: /* enable dynamic clock control */
5216 + scc = R_REG(&cc->slow_clk_ctl);
5217 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5218 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5219 + scc |= SCC_XC;
5220 + W_REG(&cc->slow_clk_ctl, scc);
5221 +
5222 + /* for dynamic control, we have to release our xtal_pu "force on" */
5223 + if (scc & SCC_XC)
5224 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5225 + break;
5226 +
5227 + default:
5228 + ASSERT(0);
5229 + }
5230 +
5231 + /* Is the h/w forcing the use of the fast clk */
5232 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5233 +
5234 +done:
5235 + sb_setcoreidx(sbh, origidx);
5236 + INTR_RESTORE(si, intr_val);
5237 + return (forcefastclk);
5238 +}
5239 +
5240 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5241 +{
5242 +return sb_clkctl_clk(sbh, mode);
5243 +}
5244 +/* register driver interrupt disabling and restoring callback functions */
5245 +void
5246 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5247 +{
5248 + sb_info_t *si;
5249 +
5250 + si = SB_INFO(sbh);
5251 + si->intr_arg = intr_arg;
5252 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5253 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5254 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5255 + /* save current core id. when this function called, the current core
5256 + * must be the core which provides driver functions(il, et, wl, etc.)
5257 + */
5258 + si->dev_coreid = si->coreid[si->curidx];
5259 +}
5260 +
5261 +
5262 +void
5263 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5264 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5265 +{
5266 + uint vendor, core, unit;
5267 + uint chip, chippkg;
5268 + char varname[8];
5269 + uint8 class, subclass, progif;
5270 +
5271 + vendor = sb_corevendor(sbh);
5272 + core = sb_coreid(sbh);
5273 + unit = sb_coreunit(sbh);
5274 +
5275 + chip = BCMINIT(sb_chip)(sbh);
5276 + chippkg = BCMINIT(sb_chippkg)(sbh);
5277 +
5278 + progif = 0;
5279 +
5280 + /* Known vendor translations */
5281 + switch (vendor) {
5282 + case SB_VEND_BCM:
5283 + vendor = VENDOR_BROADCOM;
5284 + break;
5285 + }
5286 +
5287 + /* Determine class based on known core codes */
5288 + switch (core) {
5289 + case SB_ILINE20:
5290 + class = PCI_CLASS_NET;
5291 + subclass = PCI_NET_ETHER;
5292 + core = BCM47XX_ILINE_ID;
5293 + break;
5294 + case SB_ENET:
5295 + class = PCI_CLASS_NET;
5296 + subclass = PCI_NET_ETHER;
5297 + core = BCM47XX_ENET_ID;
5298 + break;
5299 + case SB_SDRAM:
5300 + case SB_MEMC:
5301 + class = PCI_CLASS_MEMORY;
5302 + subclass = PCI_MEMORY_RAM;
5303 + break;
5304 + case SB_PCI:
5305 + class = PCI_CLASS_BRIDGE;
5306 + subclass = PCI_BRIDGE_PCI;
5307 + break;
5308 + case SB_MIPS:
5309 + case SB_MIPS33:
5310 + class = PCI_CLASS_CPU;
5311 + subclass = PCI_CPU_MIPS;
5312 + break;
5313 + case SB_CODEC:
5314 + class = PCI_CLASS_COMM;
5315 + subclass = PCI_COMM_MODEM;
5316 + core = BCM47XX_V90_ID;
5317 + break;
5318 + case SB_USB:
5319 + class = PCI_CLASS_SERIAL;
5320 + subclass = PCI_SERIAL_USB;
5321 + progif = 0x10; /* OHCI */
5322 + core = BCM47XX_USB_ID;
5323 + break;
5324 + case SB_USB11H:
5325 + class = PCI_CLASS_SERIAL;
5326 + subclass = PCI_SERIAL_USB;
5327 + progif = 0x10; /* OHCI */
5328 + core = BCM47XX_USBH_ID;
5329 + break;
5330 + case SB_USB11D:
5331 + class = PCI_CLASS_SERIAL;
5332 + subclass = PCI_SERIAL_USB;
5333 + core = BCM47XX_USBD_ID;
5334 + break;
5335 + case SB_IPSEC:
5336 + class = PCI_CLASS_CRYPT;
5337 + subclass = PCI_CRYPT_NETWORK;
5338 + core = BCM47XX_IPSEC_ID;
5339 + break;
5340 + case SB_ROBO:
5341 + class = PCI_CLASS_NET;
5342 + subclass = PCI_NET_OTHER;
5343 + core = BCM47XX_ROBO_ID;
5344 + break;
5345 + case SB_EXTIF:
5346 + case SB_CC:
5347 + class = PCI_CLASS_MEMORY;
5348 + subclass = PCI_MEMORY_FLASH;
5349 + break;
5350 + case SB_D11:
5351 + class = PCI_CLASS_NET;
5352 + subclass = PCI_NET_OTHER;
5353 + /* Let an nvram variable override this */
5354 + sprintf(varname, "wl%did", unit);
5355 + if ((core = getintvar(NULL, varname)) == 0) {
5356 + if (chip == BCM4712_DEVICE_ID) {
5357 + if (chippkg == BCM4712SMALL_PKG_ID)
5358 + core = BCM4306_D11G_ID;
5359 + else
5360 + core = BCM4306_D11DUAL_ID;
5361 + }
5362 + }
5363 + break;
5364 +
5365 + default:
5366 + class = subclass = progif = 0xff;
5367 + break;
5368 + }
5369 +
5370 + *pcivendor = (uint16)vendor;
5371 + *pcidevice = (uint16)core;
5372 + *pciclass = class;
5373 + *pcisubclass = subclass;
5374 + *pciprogif = progif;
5375 +}
5376 +
5377 +/* Fix chip's configuration. The current core may be changed upon return */
5378 +static int
5379 +sb_pci_fixcfg(sb_info_t *si)
5380 +{
5381 + uint origidx, pciidx;
5382 + sbpciregs_t *pciregs;
5383 + uint16 val16, *reg16;
5384 +
5385 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5386 +
5387 + /* Fix PCI(e) SROM shadow area */
5388 + /* save the current index */
5389 + origidx = sb_coreidx(&si->sb);
5390 +
5391 + if (si->sb.buscoretype == SB_PCI) {
5392 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5393 + ASSERT(pciregs);
5394 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5395 + }
5396 + else {
5397 + ASSERT(0);
5398 + return -1;
5399 + }
5400 + pciidx = sb_coreidx(&si->sb);
5401 + val16 = R_REG(reg16);
5402 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5403 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5404 + W_REG(reg16, val16);
5405 + }
5406 +
5407 + /* restore the original index */
5408 + sb_setcoreidx(&si->sb, origidx);
5409 +
5410 + return 0;
5411 +}
5412 +
5413 +EXPORT_SYMBOL(sb_boardtype);
5414 +EXPORT_SYMBOL(sb_boardvendor);
5415 +EXPORT_SYMBOL(sb_gpiocontrol);
5416 +EXPORT_SYMBOL(sb_gpioin);
5417 +EXPORT_SYMBOL(sb_gpiointmask);
5418 +EXPORT_SYMBOL(sb_gpiointpolarity);
5419 +EXPORT_SYMBOL(sb_gpioled);
5420 +EXPORT_SYMBOL(sb_gpioout);
5421 +EXPORT_SYMBOL(sb_gpioouten);
5422 +EXPORT_SYMBOL(sb_gpiorelease);
5423 +EXPORT_SYMBOL(sb_gpioreserve);
5424 +EXPORT_SYMBOL(sb_gpiosetcore);
5425 +EXPORT_SYMBOL(sb_gpiotimerval);
5426 +EXPORT_SYMBOL(sb_watchdog);
5427 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5428 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5429 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2006-10-15 23:29:14.000000000 +0200
5430 @@ -0,0 +1,418 @@
5431 +/*
5432 + * Broadcom SiliconBackplane chipcommon serial flash interface
5433 + *
5434 + * Copyright 2005, Broadcom Corporation
5435 + * All Rights Reserved.
5436 + *
5437 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5438 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5439 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5440 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5441 + *
5442 + * $Id$
5443 + */
5444 +
5445 +#include <osl.h>
5446 +#include <typedefs.h>
5447 +#include <sbconfig.h>
5448 +#include <sbchipc.h>
5449 +#include <mipsinc.h>
5450 +#include <bcmutils.h>
5451 +#include <bcmdevs.h>
5452 +#include <sflash.h>
5453 +
5454 +/* Private global state */
5455 +static struct sflash sflash;
5456 +
5457 +/* Issue a serial flash command */
5458 +static INLINE void
5459 +sflash_cmd(chipcregs_t *cc, uint opcode)
5460 +{
5461 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5462 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5463 +}
5464 +
5465 +/* Initialize serial flash access */
5466 +struct sflash *
5467 +sflash_init(chipcregs_t *cc)
5468 +{
5469 + uint32 id, id2;
5470 +
5471 + bzero(&sflash, sizeof(sflash));
5472 +
5473 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5474 +
5475 + switch (sflash.type) {
5476 + case SFLASH_ST:
5477 + /* Probe for ST chips */
5478 + sflash_cmd(cc, SFLASH_ST_DP);
5479 + sflash_cmd(cc, SFLASH_ST_RES);
5480 + id = R_REG(&cc->flashdata);
5481 + switch (id) {
5482 + case 0x11:
5483 + /* ST M25P20 2 Mbit Serial Flash */
5484 + sflash.blocksize = 64 * 1024;
5485 + sflash.numblocks = 4;
5486 + break;
5487 + case 0x12:
5488 + /* ST M25P40 4 Mbit Serial Flash */
5489 + sflash.blocksize = 64 * 1024;
5490 + sflash.numblocks = 8;
5491 + break;
5492 + case 0x13:
5493 + /* ST M25P80 8 Mbit Serial Flash */
5494 + sflash.blocksize = 64 * 1024;
5495 + sflash.numblocks = 16;
5496 + break;
5497 + case 0x14:
5498 + /* ST M25P16 16 Mbit Serial Flash */
5499 + sflash.blocksize = 64 * 1024;
5500 + sflash.numblocks = 32;
5501 + break;
5502 + case 0x15:
5503 + /* ST M25P32 32 Mbit Serial Flash */
5504 + sflash.blocksize = 64 * 1024;
5505 + sflash.numblocks = 64;
5506 + break;
5507 + case 0xbf:
5508 + W_REG(&cc->flashaddress, 1);
5509 + sflash_cmd(cc, SFLASH_ST_RES);
5510 + id2 = R_REG(&cc->flashdata);
5511 + if (id2 == 0x44) {
5512 + /* SST M25VF80 4 Mbit Serial Flash */
5513 + sflash.blocksize = 64 * 1024;
5514 + sflash.numblocks = 8;
5515 + }
5516 + break;
5517 + }
5518 + break;
5519 +
5520 + case SFLASH_AT:
5521 + /* Probe for Atmel chips */
5522 + sflash_cmd(cc, SFLASH_AT_STATUS);
5523 + id = R_REG(&cc->flashdata) & 0x3c;
5524 + switch (id) {
5525 + case 0xc:
5526 + /* Atmel AT45DB011 1Mbit Serial Flash */
5527 + sflash.blocksize = 256;
5528 + sflash.numblocks = 512;
5529 + break;
5530 + case 0x14:
5531 + /* Atmel AT45DB021 2Mbit Serial Flash */
5532 + sflash.blocksize = 256;
5533 + sflash.numblocks = 1024;
5534 + break;
5535 + case 0x1c:
5536 + /* Atmel AT45DB041 4Mbit Serial Flash */
5537 + sflash.blocksize = 256;
5538 + sflash.numblocks = 2048;
5539 + break;
5540 + case 0x24:
5541 + /* Atmel AT45DB081 8Mbit Serial Flash */
5542 + sflash.blocksize = 256;
5543 + sflash.numblocks = 4096;
5544 + break;
5545 + case 0x2c:
5546 + /* Atmel AT45DB161 16Mbit Serial Flash */
5547 + sflash.blocksize = 512;
5548 + sflash.numblocks = 4096;
5549 + break;
5550 + case 0x34:
5551 + /* Atmel AT45DB321 32Mbit Serial Flash */
5552 + sflash.blocksize = 512;
5553 + sflash.numblocks = 8192;
5554 + break;
5555 + case 0x3c:
5556 + /* Atmel AT45DB642 64Mbit Serial Flash */
5557 + sflash.blocksize = 1024;
5558 + sflash.numblocks = 8192;
5559 + break;
5560 + }
5561 + break;
5562 + }
5563 +
5564 + sflash.size = sflash.blocksize * sflash.numblocks;
5565 + return sflash.size ? &sflash : NULL;
5566 +}
5567 +
5568 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5569 +int
5570 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5571 +{
5572 + int cnt;
5573 + uint32 *from, *to;
5574 +
5575 + if (!len)
5576 + return 0;
5577 +
5578 + if ((offset + len) > sflash.size)
5579 + return -22;
5580 +
5581 + if ((len >= 4) && (offset & 3))
5582 + cnt = 4 - (offset & 3);
5583 + else if ((len >= 4) && ((uint32)buf & 3))
5584 + cnt = 4 - ((uint32)buf & 3);
5585 + else
5586 + cnt = len;
5587 +
5588 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5589 + to = (uint32 *)buf;
5590 +
5591 + if (cnt < 4) {
5592 + bcopy(from, to, cnt);
5593 + return cnt;
5594 + }
5595 +
5596 + while (cnt >= 4) {
5597 + *to++ = *from++;
5598 + cnt -= 4;
5599 + }
5600 +
5601 + return (len - cnt);
5602 +}
5603 +
5604 +/* Poll for command completion. Returns zero when complete. */
5605 +int
5606 +sflash_poll(chipcregs_t *cc, uint offset)
5607 +{
5608 + if (offset >= sflash.size)
5609 + return -22;
5610 +
5611 + switch (sflash.type) {
5612 + case SFLASH_ST:
5613 + /* Check for ST Write In Progress bit */
5614 + sflash_cmd(cc, SFLASH_ST_RDSR);
5615 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5616 + case SFLASH_AT:
5617 + /* Check for Atmel Ready bit */
5618 + sflash_cmd(cc, SFLASH_AT_STATUS);
5619 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5620 + }
5621 +
5622 + return 0;
5623 +}
5624 +
5625 +/* Write len bytes starting at offset into buf. Returns number of bytes
5626 + * written. Caller should poll for completion.
5627 + */
5628 +int
5629 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5630 +{
5631 + struct sflash *sfl;
5632 + int ret = 0;
5633 + bool is4712b0;
5634 + uint32 page, byte, mask;
5635 +
5636 + if (!len)
5637 + return 0;
5638 +
5639 + if ((offset + len) > sflash.size)
5640 + return -22;
5641 +
5642 + sfl = &sflash;
5643 + switch (sfl->type) {
5644 + case SFLASH_ST:
5645 + mask = R_REG(&cc->chipid);
5646 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5647 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5648 + /* Enable writes */
5649 + sflash_cmd(cc, SFLASH_ST_WREN);
5650 + if (is4712b0) {
5651 + mask = 1 << 14;
5652 + W_REG(&cc->flashaddress, offset);
5653 + W_REG(&cc->flashdata, *buf++);
5654 + /* Set chip select */
5655 + OR_REG(&cc->gpioout, mask);
5656 + /* Issue a page program with the first byte */
5657 + sflash_cmd(cc, SFLASH_ST_PP);
5658 + ret = 1;
5659 + offset++;
5660 + len--;
5661 + while (len > 0) {
5662 + if ((offset & 255) == 0) {
5663 + /* Page boundary, drop cs and return */
5664 + AND_REG(&cc->gpioout, ~mask);
5665 + if (!sflash_poll(cc, offset)) {
5666 + /* Flash rejected command */
5667 + return -11;
5668 + }
5669 + return ret;
5670 + } else {
5671 + /* Write single byte */
5672 + sflash_cmd(cc, *buf++);
5673 + }
5674 + ret++;
5675 + offset++;
5676 + len--;
5677 + }
5678 + /* All done, drop cs if needed */
5679 + if ((offset & 255) != 1) {
5680 + /* Drop cs */
5681 + AND_REG(&cc->gpioout, ~mask);
5682 + if (!sflash_poll(cc, offset)) {
5683 + /* Flash rejected command */
5684 + return -12;
5685 + }
5686 + }
5687 + } else {
5688 + ret = 1;
5689 + W_REG(&cc->flashaddress, offset);
5690 + W_REG(&cc->flashdata, *buf);
5691 + /* Page program */
5692 + sflash_cmd(cc, SFLASH_ST_PP);
5693 + }
5694 + break;
5695 + case SFLASH_AT:
5696 + mask = sfl->blocksize - 1;
5697 + page = (offset & ~mask) << 1;
5698 + byte = offset & mask;
5699 + /* Read main memory page into buffer 1 */
5700 + if (byte || len < sfl->blocksize) {
5701 + W_REG(&cc->flashaddress, page);
5702 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5703 + /* 250 us for AT45DB321B */
5704 + SPINWAIT(sflash_poll(cc, offset), 1000);
5705 + ASSERT(!sflash_poll(cc, offset));
5706 + }
5707 + /* Write into buffer 1 */
5708 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5709 + W_REG(&cc->flashaddress, byte++);
5710 + W_REG(&cc->flashdata, *buf++);
5711 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5712 + }
5713 + /* Write buffer 1 into main memory page */
5714 + W_REG(&cc->flashaddress, page);
5715 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5716 + break;
5717 + }
5718 +
5719 + return ret;
5720 +}
5721 +
5722 +/* Erase a region. Returns number of bytes scheduled for erasure.
5723 + * Caller should poll for completion.
5724 + */
5725 +int
5726 +sflash_erase(chipcregs_t *cc, uint offset)
5727 +{
5728 + struct sflash *sfl;
5729 +
5730 + if (offset >= sflash.size)
5731 + return -22;
5732 +
5733 + sfl = &sflash;
5734 + switch (sfl->type) {
5735 + case SFLASH_ST:
5736 + sflash_cmd(cc, SFLASH_ST_WREN);
5737 + W_REG(&cc->flashaddress, offset);
5738 + sflash_cmd(cc, SFLASH_ST_SE);
5739 + return sfl->blocksize;
5740 + case SFLASH_AT:
5741 + W_REG(&cc->flashaddress, offset << 1);
5742 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5743 + return sfl->blocksize;
5744 + }
5745 +
5746 + return 0;
5747 +}
5748 +
5749 +/*
5750 + * writes the appropriate range of flash, a NULL buf simply erases
5751 + * the region of flash
5752 + */
5753 +int
5754 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5755 +{
5756 + struct sflash *sfl;
5757 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5758 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5759 + uint blk_offset, blk_len, copied;
5760 + int bytes, ret = 0;
5761 +
5762 + /* Check address range */
5763 + if (len <= 0)
5764 + return 0;
5765 +
5766 + sfl = &sflash;
5767 + if ((offset + len) > sfl->size)
5768 + return -1;
5769 +
5770 + blocksize = sfl->blocksize;
5771 + mask = blocksize - 1;
5772 +
5773 + /* Allocate a block of mem */
5774 + if (!(block = MALLOC(NULL, blocksize)))
5775 + return -1;
5776 +
5777 + while (len) {
5778 + /* Align offset */
5779 + cur_offset = offset & ~mask;
5780 + cur_length = blocksize;
5781 + cur_ptr = block;
5782 +
5783 + remainder = blocksize - (offset & mask);
5784 + if (len < remainder)
5785 + cur_retlen = len;
5786 + else
5787 + cur_retlen = remainder;
5788 +
5789 + /* buf == NULL means erase only */
5790 + if (buf) {
5791 + /* Copy existing data into holding block if necessary */
5792 + if ((offset & mask) || (len < blocksize)) {
5793 + blk_offset = cur_offset;
5794 + blk_len = cur_length;
5795 + blk_ptr = cur_ptr;
5796 +
5797 + /* Copy entire block */
5798 + while(blk_len) {
5799 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5800 + blk_offset += copied;
5801 + blk_len -= copied;
5802 + blk_ptr += copied;
5803 + }
5804 + }
5805 +
5806 + /* Copy input data into holding block */
5807 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5808 + }
5809 +
5810 + /* Erase block */
5811 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5812 + goto done;
5813 + while (sflash_poll(cc, (uint) cur_offset));
5814 +
5815 + /* buf == NULL means erase only */
5816 + if (!buf) {
5817 + offset += cur_retlen;
5818 + len -= cur_retlen;
5819 + continue;
5820 + }
5821 +
5822 + /* Write holding block */
5823 + while (cur_length > 0) {
5824 + if ((bytes = sflash_write(cc,
5825 + (uint) cur_offset,
5826 + (uint) cur_length,
5827 + (uchar *) cur_ptr)) < 0) {
5828 + ret = bytes;
5829 + goto done;
5830 + }
5831 + while (sflash_poll(cc, (uint) cur_offset));
5832 + cur_offset += bytes;
5833 + cur_length -= bytes;
5834 + cur_ptr += bytes;
5835 + }
5836 +
5837 + offset += cur_retlen;
5838 + len -= cur_retlen;
5839 + buf += cur_retlen;
5840 + }
5841 +
5842 + ret = len;
5843 +done:
5844 + if (block)
5845 + MFREE(NULL, block, blocksize);
5846 + return ret;
5847 +}
5848 +
5849 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5850 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5851 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-15 23:29:14.000000000 +0200
5852 @@ -0,0 +1,391 @@
5853 +/*
5854 + * Broadcom device-specific manifest constants.
5855 + *
5856 + * Copyright 2005, Broadcom Corporation
5857 + * All Rights Reserved.
5858 + *
5859 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5860 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5861 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5862 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5863 + * $Id$
5864 + */
5865 +
5866 +#ifndef _BCMDEVS_H
5867 +#define _BCMDEVS_H
5868 +
5869 +
5870 +/* Known PCI vendor Id's */
5871 +#define VENDOR_EPIGRAM 0xfeda
5872 +#define VENDOR_BROADCOM 0x14e4
5873 +#define VENDOR_3COM 0x10b7
5874 +#define VENDOR_NETGEAR 0x1385
5875 +#define VENDOR_DIAMOND 0x1092
5876 +#define VENDOR_DELL 0x1028
5877 +#define VENDOR_HP 0x0e11
5878 +#define VENDOR_APPLE 0x106b
5879 +
5880 +/* PCI Device Id's */
5881 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5882 +#define BCM4211_DEVICE_ID 0x4211
5883 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5884 +#define BCM4231_DEVICE_ID 0x4231
5885 +
5886 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5887 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5888 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5889 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5890 +
5891 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5892 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5893 +
5894 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5895 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5896 +
5897 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5898 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5899 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5900 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5901 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5902 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5903 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5904 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5905 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5906 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5907 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5908 +
5909 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5910 +
5911 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5912 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5913 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5914 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5915 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5916 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5917 +
5918 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5919 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5920 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5921 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5922 +
5923 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5924 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5925 +
5926 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5927 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5928 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5929 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5930 +
5931 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5932 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5933 +#define BCM4306_D11G_ID2 0x4325
5934 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5935 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5936 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5937 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5938 +
5939 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5940 +
5941 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5942 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5943 +
5944 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5945 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5946 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5947 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5948 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5949 +
5950 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5951 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5952 +
5953 +
5954 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5955 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5956 +
5957 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5958 +
5959 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5960 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5961 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5962 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5963 +
5964 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5965 +
5966 +/* Address map */
5967 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5968 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5969 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5970 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5971 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5972 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5973 +
5974 +/* Core register space */
5975 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5976 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5977 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5978 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5979 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5980 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5981 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5982 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5983 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5984 +
5985 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5986 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5987 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5988 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5989 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5990 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5991 +
5992 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5993 +
5994 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5995 +
5996 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5997 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5998 +
5999 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
6000 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
6001 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
6002 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
6003 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
6004 +
6005 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
6006 +
6007 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
6008 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
6009 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
6010 +
6011 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
6012 +
6013 +/* PCMCIA vendor Id's */
6014 +
6015 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
6016 +
6017 +/* SDIO vendor Id's */
6018 +#define VENDOR_BROADCOM_SDIO 0x00BF
6019 +
6020 +
6021 +/* boardflags */
6022 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
6023 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
6024 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
6025 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
6026 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
6027 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
6028 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
6029 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
6030 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
6031 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
6032 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
6033 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
6034 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
6035 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
6036 +
6037 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6038 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6039 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
6040 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
6041 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6042 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6043 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6044 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6045 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6046 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6047 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6048 +
6049 +/* Bus types */
6050 +#define SB_BUS 0 /* Silicon Backplane */
6051 +#define PCI_BUS 1 /* PCI target */
6052 +#define PCMCIA_BUS 2 /* PCMCIA target */
6053 +#define SDIO_BUS 3 /* SDIO target */
6054 +#define JTAG_BUS 4 /* JTAG */
6055 +
6056 +/* Allows optimization for single-bus support */
6057 +#ifdef BCMBUSTYPE
6058 +#define BUSTYPE(bus) (BCMBUSTYPE)
6059 +#else
6060 +#define BUSTYPE(bus) (bus)
6061 +#endif
6062 +
6063 +/* power control defines */
6064 +#define PLL_DELAY 150 /* us pll on delay */
6065 +#define FREF_DELAY 200 /* us fref change delay */
6066 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6067 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6068 +
6069 +/* Reference Board Types */
6070 +
6071 +#define BU4710_BOARD 0x0400
6072 +#define VSIM4710_BOARD 0x0401
6073 +#define QT4710_BOARD 0x0402
6074 +
6075 +#define BU4610_BOARD 0x0403
6076 +#define VSIM4610_BOARD 0x0404
6077 +
6078 +#define BU4307_BOARD 0x0405
6079 +#define BCM94301CB_BOARD 0x0406
6080 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6081 +#define BCM94301MP_BOARD 0x0407
6082 +#define BCM94307MP_BOARD 0x0408
6083 +#define BCMAP4307_BOARD 0x0409
6084 +
6085 +#define BU4309_BOARD 0x040a
6086 +#define BCM94309CB_BOARD 0x040b
6087 +#define BCM94309MP_BOARD 0x040c
6088 +#define BCM4309AP_BOARD 0x040d
6089 +
6090 +#define BCM94302MP_BOARD 0x040e
6091 +
6092 +#define VSIM4310_BOARD 0x040f
6093 +#define BU4711_BOARD 0x0410
6094 +#define BCM94310U_BOARD 0x0411
6095 +#define BCM94310AP_BOARD 0x0412
6096 +#define BCM94310MP_BOARD 0x0414
6097 +
6098 +#define BU4306_BOARD 0x0416
6099 +#define BCM94306CB_BOARD 0x0417
6100 +#define BCM94306MP_BOARD 0x0418
6101 +
6102 +#define BCM94710D_BOARD 0x041a
6103 +#define BCM94710R1_BOARD 0x041b
6104 +#define BCM94710R4_BOARD 0x041c
6105 +#define BCM94710AP_BOARD 0x041d
6106 +
6107 +
6108 +#define BU2050_BOARD 0x041f
6109 +
6110 +
6111 +#define BCM94309G_BOARD 0x0421
6112 +
6113 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6114 +
6115 +#define BU4704_BOARD 0x0423
6116 +#define BU4702_BOARD 0x0424
6117 +
6118 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6119 +
6120 +#define BU4317_BOARD 0x0426
6121 +
6122 +
6123 +#define BCM94702MN_BOARD 0x0428
6124 +
6125 +/* BCM4702 1U CompactPCI Board */
6126 +#define BCM94702CPCI_BOARD 0x0429
6127 +
6128 +/* BCM4702 with BCM95380 VLAN Router */
6129 +#define BCM95380RR_BOARD 0x042a
6130 +
6131 +/* cb4306 with SiGe PA */
6132 +#define BCM94306CBSG_BOARD 0x042b
6133 +
6134 +/* mp4301 with 2050 radio */
6135 +#define BCM94301MPL_BOARD 0x042c
6136 +
6137 +/* cb4306 with SiGe PA */
6138 +#define PCSG94306_BOARD 0x042d
6139 +
6140 +/* bu4704 with sdram */
6141 +#define BU4704SD_BOARD 0x042e
6142 +
6143 +/* Dual 11a/11g Router */
6144 +#define BCM94704AGR_BOARD 0x042f
6145 +
6146 +/* 11a-only minipci */
6147 +#define BCM94308MP_BOARD 0x0430
6148 +
6149 +
6150 +
6151 +/* BCM94317 boards */
6152 +#define BCM94317CB_BOARD 0x0440
6153 +#define BCM94317MP_BOARD 0x0441
6154 +#define BCM94317PCMCIA_BOARD 0x0442
6155 +#define BCM94317SDIO_BOARD 0x0443
6156 +
6157 +#define BU4712_BOARD 0x0444
6158 +#define BU4712SD_BOARD 0x045d
6159 +#define BU4712L_BOARD 0x045f
6160 +
6161 +/* BCM4712 boards */
6162 +#define BCM94712AP_BOARD 0x0445
6163 +#define BCM94712P_BOARD 0x0446
6164 +
6165 +/* BCM4318 boards */
6166 +#define BU4318_BOARD 0x0447
6167 +#define CB4318_BOARD 0x0448
6168 +#define MPG4318_BOARD 0x0449
6169 +#define MP4318_BOARD 0x044a
6170 +#define SD4318_BOARD 0x044b
6171 +
6172 +/* BCM63XX boards */
6173 +#define BCM96338_BOARD 0x6338
6174 +#define BCM96345_BOARD 0x6345
6175 +#define BCM96348_BOARD 0x6348
6176 +
6177 +/* Another mp4306 with SiGe */
6178 +#define BCM94306P_BOARD 0x044c
6179 +
6180 +/* CF-like 4317 modules */
6181 +#define BCM94317CF_BOARD 0x044d
6182 +
6183 +/* mp4303 */
6184 +#define BCM94303MP_BOARD 0x044e
6185 +
6186 +/* mpsgh4306 */
6187 +#define BCM94306MPSGH_BOARD 0x044f
6188 +
6189 +/* BRCM 4306 w/ Front End Modules */
6190 +#define BCM94306MPM 0x0450
6191 +#define BCM94306MPL 0x0453
6192 +
6193 +/* 4712agr */
6194 +#define BCM94712AGR_BOARD 0x0451
6195 +
6196 +/* The real CF 4317 board */
6197 +#define CFI4317_BOARD 0x0452
6198 +
6199 +/* pcmcia 4303 */
6200 +#define PC4303_BOARD 0x0454
6201 +
6202 +/* 5350K */
6203 +#define BCM95350K_BOARD 0x0455
6204 +
6205 +/* 5350R */
6206 +#define BCM95350R_BOARD 0x0456
6207 +
6208 +/* 4306mplna */
6209 +#define BCM94306MPLNA_BOARD 0x0457
6210 +
6211 +/* 4320 boards */
6212 +#define BU4320_BOARD 0x0458
6213 +#define BU4320S_BOARD 0x0459
6214 +#define BCM94320PH_BOARD 0x045a
6215 +
6216 +/* 4306mph */
6217 +#define BCM94306MPH_BOARD 0x045b
6218 +
6219 +/* 4306pciv */
6220 +#define BCM94306PCIV_BOARD 0x045c
6221 +
6222 +#define BU4712SD_BOARD 0x045d
6223 +
6224 +#define BCM94320PFLSH_BOARD 0x045e
6225 +
6226 +#define BU4712L_BOARD 0x045f
6227 +#define BCM94712LGR_BOARD 0x0460
6228 +#define BCM94320R_BOARD 0x0461
6229 +
6230 +#define BU5352_BOARD 0x0462
6231 +
6232 +#define BCM94318MPGH_BOARD 0x0463
6233 +
6234 +
6235 +#define BCM95352GR_BOARD 0x0467
6236 +
6237 +/* bcm95351agr */
6238 +#define BCM95351AGR_BOARD 0x0470
6239 +
6240 +/* # of GPIO pins */
6241 +#define GPIO_NUMPINS 16
6242 +
6243 +#endif /* _BCMDEVS_H */
6244 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6245 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6246 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-15 23:29:14.000000000 +0200
6247 @@ -0,0 +1,152 @@
6248 +/*
6249 + * local version of endian.h - byte order defines
6250 + *
6251 + * Copyright 2005, Broadcom Corporation
6252 + * All Rights Reserved.
6253 + *
6254 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6255 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6256 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6257 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6258 + *
6259 + * $Id$
6260 +*/
6261 +
6262 +#ifndef _BCMENDIAN_H_
6263 +#define _BCMENDIAN_H_
6264 +
6265 +#include <typedefs.h>
6266 +
6267 +/* Byte swap a 16 bit value */
6268 +#define BCMSWAP16(val) \
6269 + ((uint16)( \
6270 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6271 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6272 +
6273 +/* Byte swap a 32 bit value */
6274 +#define BCMSWAP32(val) \
6275 + ((uint32)( \
6276 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6277 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6278 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6279 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6280 +
6281 +/* 2 Byte swap a 32 bit value */
6282 +#define BCMSWAP32BY16(val) \
6283 + ((uint32)( \
6284 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6285 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6286 +
6287 +
6288 +static INLINE uint16
6289 +bcmswap16(uint16 val)
6290 +{
6291 + return BCMSWAP16(val);
6292 +}
6293 +
6294 +static INLINE uint32
6295 +bcmswap32(uint32 val)
6296 +{
6297 + return BCMSWAP32(val);
6298 +}
6299 +
6300 +static INLINE uint32
6301 +bcmswap32by16(uint32 val)
6302 +{
6303 + return BCMSWAP32BY16(val);
6304 +}
6305 +
6306 +/* buf - start of buffer of shorts to swap */
6307 +/* len - byte length of buffer */
6308 +static INLINE void
6309 +bcmswap16_buf(uint16 *buf, uint len)
6310 +{
6311 + len = len/2;
6312 +
6313 + while(len--){
6314 + *buf = bcmswap16(*buf);
6315 + buf++;
6316 + }
6317 +}
6318 +
6319 +#ifndef hton16
6320 +#ifndef IL_BIGENDIAN
6321 +#define HTON16(i) BCMSWAP16(i)
6322 +#define hton16(i) bcmswap16(i)
6323 +#define hton32(i) bcmswap32(i)
6324 +#define ntoh16(i) bcmswap16(i)
6325 +#define ntoh32(i) bcmswap32(i)
6326 +#define ltoh16(i) (i)
6327 +#define ltoh32(i) (i)
6328 +#define htol16(i) (i)
6329 +#define htol32(i) (i)
6330 +#else
6331 +#define HTON16(i) (i)
6332 +#define hton16(i) (i)
6333 +#define hton32(i) (i)
6334 +#define ntoh16(i) (i)
6335 +#define ntoh32(i) (i)
6336 +#define ltoh16(i) bcmswap16(i)
6337 +#define ltoh32(i) bcmswap32(i)
6338 +#define htol16(i) bcmswap16(i)
6339 +#define htol32(i) bcmswap32(i)
6340 +#endif
6341 +#endif
6342 +
6343 +#ifndef IL_BIGENDIAN
6344 +#define ltoh16_buf(buf, i)
6345 +#define htol16_buf(buf, i)
6346 +#else
6347 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6348 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6349 +#endif
6350 +
6351 +/*
6352 +* load 16-bit value from unaligned little endian byte array.
6353 +*/
6354 +static INLINE uint16
6355 +ltoh16_ua(uint8 *bytes)
6356 +{
6357 + return (bytes[1]<<8)+bytes[0];
6358 +}
6359 +
6360 +/*
6361 +* load 32-bit value from unaligned little endian byte array.
6362 +*/
6363 +static INLINE uint32
6364 +ltoh32_ua(uint8 *bytes)
6365 +{
6366 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6367 +}
6368 +
6369 +/*
6370 +* load 16-bit value from unaligned big(network) endian byte array.
6371 +*/
6372 +static INLINE uint16
6373 +ntoh16_ua(uint8 *bytes)
6374 +{
6375 + return (bytes[0]<<8)+bytes[1];
6376 +}
6377 +
6378 +/*
6379 +* load 32-bit value from unaligned big(network) endian byte array.
6380 +*/
6381 +static INLINE uint32
6382 +ntoh32_ua(uint8 *bytes)
6383 +{
6384 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6385 +}
6386 +
6387 +#define ltoh_ua(ptr) ( \
6388 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6389 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6390 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6391 +)
6392 +
6393 +#define ntoh_ua(ptr) ( \
6394 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6395 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6396 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6397 +)
6398 +
6399 +#endif /* _BCMENDIAN_H_ */
6400 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6401 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6402 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-15 23:29:14.000000000 +0200
6403 @@ -0,0 +1,95 @@
6404 +/*
6405 + * NVRAM variable manipulation
6406 + *
6407 + * Copyright 2005, Broadcom Corporation
6408 + * All Rights Reserved.
6409 + *
6410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6414 + *
6415 + * $Id$
6416 + */
6417 +
6418 +#ifndef _bcmnvram_h_
6419 +#define _bcmnvram_h_
6420 +
6421 +#ifndef _LANGUAGE_ASSEMBLY
6422 +
6423 +#include <typedefs.h>
6424 +
6425 +struct nvram_header {
6426 + uint32 magic;
6427 + uint32 len;
6428 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6429 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6430 + uint32 config_ncdl; /* ncdl values for memc */
6431 +};
6432 +
6433 +struct nvram_tuple {
6434 + char *name;
6435 + char *value;
6436 + struct nvram_tuple *next;
6437 +};
6438 +
6439 +/*
6440 + * Get the value of an NVRAM variable. The pointer returned may be
6441 + * invalid after a set.
6442 + * @param name name of variable to get
6443 + * @return value of variable or NULL if undefined
6444 + */
6445 +extern char * __init early_nvram_get(const char *name);
6446 +
6447 +/*
6448 + * Get the value of an NVRAM variable. The pointer returned may be
6449 + * invalid after a set.
6450 + * @param name name of variable to get
6451 + * @return value of variable or NULL if undefined
6452 + */
6453 +extern char *nvram_get(const char *name);
6454 +
6455 +/*
6456 + * Get the value of an NVRAM variable.
6457 + * @param name name of variable to get
6458 + * @return value of variable or NUL if undefined
6459 + */
6460 +#define nvram_safe_get(name) (BCMINIT(early_nvram_get)(name) ? : "")
6461 +
6462 +/*
6463 + * Match an NVRAM variable.
6464 + * @param name name of variable to match
6465 + * @param match value to compare against value of variable
6466 + * @return TRUE if variable is defined and its value is string equal
6467 + * to match or FALSE otherwise
6468 + */
6469 +static inline int
6470 +nvram_match(char *name, char *match) {
6471 + const char *value = BCMINIT(early_nvram_get)(name);
6472 + return (value && !strcmp(value, match));
6473 +}
6474 +
6475 +/*
6476 + * Inversely match an NVRAM variable.
6477 + * @param name name of variable to match
6478 + * @param match value to compare against value of variable
6479 + * @return TRUE if variable is defined and its value is not string
6480 + * equal to invmatch or FALSE otherwise
6481 + */
6482 +static inline int
6483 +nvram_invmatch(char *name, char *invmatch) {
6484 + const char *value = BCMINIT(early_nvram_get)(name);
6485 + return (value && strcmp(value, invmatch));
6486 +}
6487 +
6488 +#endif /* _LANGUAGE_ASSEMBLY */
6489 +
6490 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6491 +#define NVRAM_VERSION 1
6492 +#define NVRAM_HEADER_SIZE 20
6493 +#define NVRAM_SPACE 0x8000
6494 +
6495 +#define NVRAM_MAX_VALUE_LEN 255
6496 +#define NVRAM_MAX_PARAM_LEN 64
6497 +
6498 +#endif /* _bcmnvram_h_ */
6499 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6500 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6501 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-15 23:29:14.000000000 +0200
6502 @@ -0,0 +1,23 @@
6503 +/*
6504 + * Misc useful routines to access NIC local SROM/OTP .
6505 + *
6506 + * Copyright 2005, Broadcom Corporation
6507 + * All Rights Reserved.
6508 + *
6509 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6510 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6511 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6512 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6513 + *
6514 + * $Id$
6515 + */
6516 +
6517 +#ifndef _bcmsrom_h_
6518 +#define _bcmsrom_h_
6519 +
6520 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6521 +
6522 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6523 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6524 +
6525 +#endif /* _bcmsrom_h_ */
6526 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6527 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6528 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-15 23:29:14.000000000 +0200
6529 @@ -0,0 +1,308 @@
6530 +/*
6531 + * Misc useful os-independent macros and functions.
6532 + *
6533 + * Copyright 2005, Broadcom Corporation
6534 + * All Rights Reserved.
6535 + *
6536 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6537 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6538 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6539 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6540 + * $Id$
6541 + */
6542 +
6543 +#ifndef _bcmutils_h_
6544 +#define _bcmutils_h_
6545 +
6546 +/*** driver-only section ***/
6547 +#include <osl.h>
6548 +
6549 +#define _BCM_U 0x01 /* upper */
6550 +#define _BCM_L 0x02 /* lower */
6551 +#define _BCM_D 0x04 /* digit */
6552 +#define _BCM_C 0x08 /* cntrl */
6553 +#define _BCM_P 0x10 /* punct */
6554 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6555 +#define _BCM_X 0x40 /* hex digit */
6556 +#define _BCM_SP 0x80 /* hard space (0x20) */
6557 +
6558 +#define GPIO_PIN_NOTDEFINED 0x20
6559 +
6560 +extern unsigned char bcm_ctype[];
6561 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6562 +
6563 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6564 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6565 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6566 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6567 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6568 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6569 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6570 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6571 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6572 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6573 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6574 +
6575 +/*
6576 + * Spin at most 'us' microseconds while 'exp' is true.
6577 + * Caller should explicitly test 'exp' when this completes
6578 + * and take appropriate error action if 'exp' is still true.
6579 + */
6580 +#define SPINWAIT(exp, us) { \
6581 + uint countdown = (us) + 9; \
6582 + while ((exp) && (countdown >= 10)) {\
6583 + OSL_DELAY(10); \
6584 + countdown -= 10; \
6585 + } \
6586 +}
6587 +
6588 +/* generic osl packet queue */
6589 +struct pktq {
6590 + void *head; /* first packet to dequeue */
6591 + void *tail; /* last packet to dequeue */
6592 + uint len; /* number of queued packets */
6593 + uint maxlen; /* maximum number of queued packets */
6594 + bool priority; /* enqueue by packet priority */
6595 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6596 +};
6597 +#define DEFAULT_QLEN 128
6598 +
6599 +#define pktq_len(q) ((q)->len)
6600 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6601 +#define pktq_head(q) ((q)->head)
6602 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6603 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6604 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6605 +
6606 +/* externs */
6607 +/* packet */
6608 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6609 +extern uint pkttotlen(osl_t *osh, void *);
6610 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6611 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6612 +extern void *pktdeq(struct pktq *q);
6613 +extern void *pktdeqtail(struct pktq *q);
6614 +/* string */
6615 +extern uint bcm_atoi(char *s);
6616 +extern uchar bcm_toupper(uchar c);
6617 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6618 +extern char *bcmstrstr(char *haystack, char *needle);
6619 +extern char *bcmstrcat(char *dest, const char *src);
6620 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6621 +/* ethernet address */
6622 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6623 +extern int bcm_ether_atoe(char *p, char *ea);
6624 +/* delay */
6625 +extern void bcm_mdelay(uint ms);
6626 +/* variable access */
6627 +extern char *getvar(char *vars, char *name);
6628 +extern int getintvar(char *vars, char *name);
6629 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6630 +#define bcmlog(fmt, a1, a2)
6631 +#define bcmdumplog(buf, size) *buf = '\0'
6632 +#define bcmdumplogent(buf, idx) -1
6633 +
6634 +/*** driver/apps-shared section ***/
6635 +
6636 +#define BCME_STRLEN 64
6637 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6638 +
6639 +
6640 +/*
6641 + * error codes could be added but the defined ones shouldn't be changed/deleted
6642 + * these error codes are exposed to the user code
6643 + * when ever a new error code is added to this list
6644 + * please update errorstring table with the related error string and
6645 + * update osl files with os specific errorcode map
6646 +*/
6647 +
6648 +#define BCME_ERROR -1 /* Error generic */
6649 +#define BCME_BADARG -2 /* Bad Argument */
6650 +#define BCME_BADOPTION -3 /* Bad option */
6651 +#define BCME_NOTUP -4 /* Not up */
6652 +#define BCME_NOTDOWN -5 /* Not down */
6653 +#define BCME_NOTAP -6 /* Not AP */
6654 +#define BCME_NOTSTA -7 /* Not STA */
6655 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6656 +#define BCME_RADIOOFF -9 /* Radio Off */
6657 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6658 +#define BCME_NOCLK -11 /* No Clock*/
6659 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6660 +#define BCME_BADBAND -13 /* BAD Band */
6661 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6662 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6663 +#define BCME_BUSY -16 /* Busy*/
6664 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6665 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6666 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6667 +#define BCME_BADCHAN -20 /* BAD Channel */
6668 +#define BCME_BADADDR -21 /* BAD Address*/
6669 +#define BCME_NORESOURCE -22 /* No resources*/
6670 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6671 +#define BCME_BADLEN -24 /* Bad Length*/
6672 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6673 +#define BCME_EPERM -26 /* Not Permitted */
6674 +#define BCME_NOMEM -27 /* No Memory */
6675 +#define BCME_ASSOCIATED -28 /* Associated */
6676 +#define BCME_RANGE -29 /* Range Error*/
6677 +#define BCME_NOTFOUND -30 /* Not found */
6678 +#define BCME_LAST BCME_NOTFOUND
6679 +
6680 +#ifndef ABS
6681 +#define ABS(a) (((a)<0)?-(a):(a))
6682 +#endif
6683 +
6684 +#ifndef MIN
6685 +#define MIN(a, b) (((a)<(b))?(a):(b))
6686 +#endif
6687 +
6688 +#ifndef MAX
6689 +#define MAX(a, b) (((a)>(b))?(a):(b))
6690 +#endif
6691 +
6692 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6693 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6694 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6695 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6696 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6697 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6698 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6699 +
6700 +/* bit map related macros */
6701 +#ifndef setbit
6702 +#define NBBY 8 /* 8 bits per byte */
6703 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6704 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6705 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6706 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6707 +#endif
6708 +
6709 +#define NBITS(type) (sizeof(type) * 8)
6710 +#define NBITVAL(bits) (1 << (bits))
6711 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6712 +
6713 +/* crc defines */
6714 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6715 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6716 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6717 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6718 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6719 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6720 +
6721 +/* bcm_format_flags() bit description structure */
6722 +typedef struct bcm_bit_desc {
6723 + uint32 bit;
6724 + char* name;
6725 +} bcm_bit_desc_t;
6726 +
6727 +/* tag_ID/length/value_buffer tuple */
6728 +typedef struct bcm_tlv {
6729 + uint8 id;
6730 + uint8 len;
6731 + uint8 data[1];
6732 +} bcm_tlv_t;
6733 +
6734 +/* Check that bcm_tlv_t fits into the given buflen */
6735 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6736 +
6737 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6738 +#define ETHER_ADDR_STR_LEN 18
6739 +
6740 +/* unaligned load and store macros */
6741 +#ifdef IL_BIGENDIAN
6742 +static INLINE uint32
6743 +load32_ua(uint8 *a)
6744 +{
6745 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6746 +}
6747 +
6748 +static INLINE void
6749 +store32_ua(uint8 *a, uint32 v)
6750 +{
6751 + a[0] = (v >> 24) & 0xff;
6752 + a[1] = (v >> 16) & 0xff;
6753 + a[2] = (v >> 8) & 0xff;
6754 + a[3] = v & 0xff;
6755 +}
6756 +
6757 +static INLINE uint16
6758 +load16_ua(uint8 *a)
6759 +{
6760 + return ((a[0] << 8) | a[1]);
6761 +}
6762 +
6763 +static INLINE void
6764 +store16_ua(uint8 *a, uint16 v)
6765 +{
6766 + a[0] = (v >> 8) & 0xff;
6767 + a[1] = v & 0xff;
6768 +}
6769 +
6770 +#else
6771 +
6772 +static INLINE uint32
6773 +load32_ua(uint8 *a)
6774 +{
6775 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6776 +}
6777 +
6778 +static INLINE void
6779 +store32_ua(uint8 *a, uint32 v)
6780 +{
6781 + a[3] = (v >> 24) & 0xff;
6782 + a[2] = (v >> 16) & 0xff;
6783 + a[1] = (v >> 8) & 0xff;
6784 + a[0] = v & 0xff;
6785 +}
6786 +
6787 +static INLINE uint16
6788 +load16_ua(uint8 *a)
6789 +{
6790 + return ((a[1] << 8) | a[0]);
6791 +}
6792 +
6793 +static INLINE void
6794 +store16_ua(uint8 *a, uint16 v)
6795 +{
6796 + a[1] = (v >> 8) & 0xff;
6797 + a[0] = v & 0xff;
6798 +}
6799 +
6800 +#endif
6801 +
6802 +/* externs */
6803 +/* crc */
6804 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6805 +/* format/print */
6806 +/* IE parsing */
6807 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6808 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6809 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6810 +
6811 +/* bcmerror*/
6812 +extern const char *bcmerrorstr(int bcmerror);
6813 +
6814 +/* multi-bool data type: set of bools, mbool is true if any is set */
6815 +typedef uint32 mbool;
6816 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6817 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6818 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6819 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6820 +
6821 +/* power conversion */
6822 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6823 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6824 +
6825 +/* generic datastruct to help dump routines */
6826 +struct fielddesc {
6827 + char *nameandfmt;
6828 + uint32 offset;
6829 + uint32 len;
6830 +};
6831 +
6832 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6833 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6834 +
6835 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6836 +
6837 +#endif /* _bcmutils_h_ */
6838 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6839 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6840 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2006-10-15 23:29:14.000000000 +0200
6841 @@ -0,0 +1,85 @@
6842 +/*
6843 + * bit manipulation utility functions
6844 + *
6845 + * Copyright 2005, Broadcom Corporation
6846 + * All Rights Reserved.
6847 + *
6848 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6849 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6850 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6851 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6852 + * $Id$
6853 + */
6854 +
6855 +#ifndef _BITFUNCS_H
6856 +#define _BITFUNCS_H
6857 +
6858 +#include <typedefs.h>
6859 +
6860 +/* local prototypes */
6861 +static INLINE uint32 find_msbit(uint32 x);
6862 +
6863 +
6864 +/*
6865 + * find_msbit: returns index of most significant set bit in x, with index
6866 + * range defined as 0-31. NOTE: returns zero if input is zero.
6867 + */
6868 +
6869 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6870 +
6871 +/*
6872 + * Implementation for Pentium processors and gcc. Note that this
6873 + * instruction is actually very slow on some processors (e.g., family 5,
6874 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6875 + * implementation instead.
6876 + */
6877 +static INLINE uint32 find_msbit(uint32 x)
6878 +{
6879 + uint msbit;
6880 + __asm__("bsrl %1,%0"
6881 + :"=r" (msbit)
6882 + :"r" (x));
6883 + return msbit;
6884 +}
6885 +
6886 +#else
6887 +
6888 +/*
6889 + * Generic Implementation
6890 + */
6891 +
6892 +#define DB_POW_MASK16 0xffff0000
6893 +#define DB_POW_MASK8 0x0000ff00
6894 +#define DB_POW_MASK4 0x000000f0
6895 +#define DB_POW_MASK2 0x0000000c
6896 +#define DB_POW_MASK1 0x00000002
6897 +
6898 +static INLINE uint32 find_msbit(uint32 x)
6899 +{
6900 + uint32 temp_x = x;
6901 + uint msbit = 0;
6902 + if (temp_x & DB_POW_MASK16) {
6903 + temp_x >>= 16;
6904 + msbit = 16;
6905 + }
6906 + if (temp_x & DB_POW_MASK8) {
6907 + temp_x >>= 8;
6908 + msbit += 8;
6909 + }
6910 + if (temp_x & DB_POW_MASK4) {
6911 + temp_x >>= 4;
6912 + msbit += 4;
6913 + }
6914 + if (temp_x & DB_POW_MASK2) {
6915 + temp_x >>= 2;
6916 + msbit += 2;
6917 + }
6918 + if (temp_x & DB_POW_MASK1) {
6919 + msbit += 1;
6920 + }
6921 + return(msbit);
6922 +}
6923 +
6924 +#endif
6925 +
6926 +#endif /* _BITFUNCS_H */
6927 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6928 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6929 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2006-10-15 23:29:14.000000000 +0200
6930 @@ -0,0 +1,188 @@
6931 +/*
6932 + * flash.h: Common definitions for flash access.
6933 + *
6934 + * Copyright 2005, Broadcom Corporation
6935 + * All Rights Reserved.
6936 + *
6937 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6938 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6939 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6940 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6941 + *
6942 + * $Id$
6943 + */
6944 +
6945 +/* Types of flashes we know about */
6946 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6947 +
6948 +/* Commands to write/erase the flases */
6949 +typedef struct _flash_cmds{
6950 + flash_type_t type;
6951 + bool need_unlock;
6952 + uint16 pre_erase;
6953 + uint16 erase_block;
6954 + uint16 erase_chip;
6955 + uint16 write_word;
6956 + uint16 write_buf;
6957 + uint16 clear_csr;
6958 + uint16 read_csr;
6959 + uint16 read_id;
6960 + uint16 confirm;
6961 + uint16 read_array;
6962 +} flash_cmds_t;
6963 +
6964 +#define UNLOCK_CMD_WORDS 2
6965 +
6966 +typedef struct _unlock_cmd {
6967 + uint addr[UNLOCK_CMD_WORDS];
6968 + uint16 cmd[UNLOCK_CMD_WORDS];
6969 +} unlock_cmd_t;
6970 +
6971 +/* Flash descriptors */
6972 +typedef struct _flash_desc {
6973 + uint16 mfgid; /* Manufacturer Id */
6974 + uint16 devid; /* Device Id */
6975 + uint size; /* Total size in bytes */
6976 + uint width; /* Device width in bytes */
6977 + flash_type_t type; /* Device type old, S, J */
6978 + uint bsize; /* Block size */
6979 + uint nb; /* Number of blocks */
6980 + uint ff; /* First full block */
6981 + uint lf; /* Last full block */
6982 + uint nsub; /* Number of subblocks */
6983 + uint *subblocks; /* Offsets for subblocks */
6984 + char *desc; /* Description */
6985 +} flash_desc_t;
6986 +
6987 +
6988 +#ifdef DECLARE_FLASHES
6989 +flash_cmds_t sflash_cmd_t =
6990 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6991 +
6992 +flash_cmds_t flash_cmds[] = {
6993 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6994 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6995 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6996 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6997 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6998 + { 0 }
6999 +};
7000 +
7001 +unlock_cmd_t unlock_cmd_amd = {
7002 +#ifdef MIPSEB
7003 +/* addr: */ { 0x0aa8, 0x0556},
7004 +#else
7005 +/* addr: */ { 0x0aaa, 0x0554},
7006 +#endif
7007 +/* data: */ { 0xaa, 0x55}
7008 +};
7009 +
7010 +unlock_cmd_t unlock_cmd_sst = {
7011 +#ifdef MIPSEB
7012 +/* addr: */ { 0xaaa8, 0x5556},
7013 +#else
7014 +/* addr: */ { 0xaaaa, 0x5554},
7015 +#endif
7016 +/* data: */ { 0xaa, 0x55}
7017 +};
7018 +
7019 +#define AMD_CMD 0xaaa
7020 +#define SST_CMD 0xaaaa
7021 +
7022 +/* intel unlock block cmds */
7023 +#define INTEL_UNLOCK1 0x60
7024 +#define INTEL_UNLOCK2 0xD0
7025 +
7026 +/* Just eight blocks of 8KB byte each */
7027 +
7028 +uint blk8x8k[] = { 0x00000000,
7029 + 0x00002000,
7030 + 0x00004000,
7031 + 0x00006000,
7032 + 0x00008000,
7033 + 0x0000a000,
7034 + 0x0000c000,
7035 + 0x0000e000,
7036 + 0x00010000
7037 +};
7038 +
7039 +/* Funky AMD arrangement for 29xx800's */
7040 +uint amd800[] = { 0x00000000, /* 16KB */
7041 + 0x00004000, /* 32KB */
7042 + 0x0000c000, /* 8KB */
7043 + 0x0000e000, /* 8KB */
7044 + 0x00010000, /* 8KB */
7045 + 0x00012000, /* 8KB */
7046 + 0x00014000, /* 32KB */
7047 + 0x0001c000, /* 16KB */
7048 + 0x00020000
7049 +};
7050 +
7051 +/* AMD arrangement for 29xx160's */
7052 +uint amd4112[] = { 0x00000000, /* 32KB */
7053 + 0x00008000, /* 8KB */
7054 + 0x0000a000, /* 8KB */
7055 + 0x0000c000, /* 16KB */
7056 + 0x00010000
7057 +};
7058 +uint amd2114[] = { 0x00000000, /* 16KB */
7059 + 0x00004000, /* 8KB */
7060 + 0x00006000, /* 8KB */
7061 + 0x00008000, /* 32KB */
7062 + 0x00010000
7063 +};
7064 +
7065 +
7066 +flash_desc_t sflash_desc =
7067 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7068 +
7069 +flash_desc_t flashes[] = {
7070 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7071 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7072 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7073 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7074 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7075 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7076 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7077 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7078 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7079 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7080 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7081 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7082 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7083 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7084 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7085 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7086 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7087 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7088 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7089 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7090 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7091 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7092 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7093 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7094 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7095 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7096 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7097 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7098 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7099 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7100 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7101 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7102 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7103 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7104 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7105 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7106 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7107 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7108 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7109 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7110 +};
7111 +
7112 +#else
7113 +
7114 +extern flash_cmds_t flash_cmds[];
7115 +extern unlock_cmd_t unlock_cmd;
7116 +extern flash_desc_t flashes[];
7117 +
7118 +#endif
7119 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7120 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7121 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2006-10-15 23:29:14.000000000 +0200
7122 @@ -0,0 +1,27 @@
7123 +/*
7124 + * BCM47XX FLASH driver interface
7125 + *
7126 + * Copyright 2005, Broadcom Corporation
7127 + * All Rights Reserved.
7128 + *
7129 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7130 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7131 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7132 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7133 + * $Id$
7134 + */
7135 +
7136 +#ifndef _flashutl_h_
7137 +#define _flashutl_h_
7138 +
7139 +
7140 +#ifndef _LANGUAGE_ASSEMBLY
7141 +
7142 +int sysFlashInit(char *flash_str);
7143 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7144 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7145 +void nvWrite(unsigned short *data, unsigned int len);
7146 +
7147 +#endif /* _LANGUAGE_ASSEMBLY */
7148 +
7149 +#endif /* _flashutl_h_ */
7150 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7151 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7152 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-15 23:29:14.000000000 +0200
7153 @@ -0,0 +1,16 @@
7154 +/*
7155 + * Alternate include file for HND sbmips.h since CFE also ships with
7156 + * a sbmips.h.
7157 + *
7158 + * Copyright 2005, Broadcom Corporation
7159 + * All Rights Reserved.
7160 + *
7161 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7162 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7163 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7164 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7165 + *
7166 + * $Id$
7167 + */
7168 +
7169 +#include "sbmips.h"
7170 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7171 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7172 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2006-10-15 23:29:14.000000000 +0200
7173 @@ -0,0 +1,331 @@
7174 +/*
7175 + * Linux OS Independent Layer
7176 + *
7177 + * Copyright 2005, Broadcom Corporation
7178 + * All Rights Reserved.
7179 + *
7180 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7181 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7182 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7183 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7184 + *
7185 + * $Id$
7186 + */
7187 +
7188 +#ifndef _linux_osl_h_
7189 +#define _linux_osl_h_
7190 +
7191 +#include <typedefs.h>
7192 +
7193 +/* use current 2.4.x calling conventions */
7194 +#include <linuxver.h>
7195 +
7196 +/* assert and panic */
7197 +#ifdef __GNUC__
7198 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7199 +#if GCC_VERSION > 30100
7200 +#define ASSERT(exp) do {} while (0)
7201 +#else
7202 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7203 +#define ASSERT(exp)
7204 +#endif
7205 +#endif
7206 +
7207 +/* microsecond delay */
7208 +#define OSL_DELAY(usec) osl_delay(usec)
7209 +extern void osl_delay(uint usec);
7210 +
7211 +/* PCI configuration space access macros */
7212 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7213 + osl_pci_read_config((osh), (offset), (size))
7214 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7215 + osl_pci_write_config((osh), (offset), (size), (val))
7216 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7217 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7218 +
7219 +/* PCI device bus # and slot # */
7220 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7221 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7222 +extern uint osl_pci_bus(osl_t *osh);
7223 +extern uint osl_pci_slot(osl_t *osh);
7224 +
7225 +/* OSL initialization */
7226 +extern osl_t *osl_attach(void *pdev);
7227 +extern void osl_detach(osl_t *osh);
7228 +
7229 +/* host/bus architecture-specific byte swap */
7230 +#define BUS_SWAP32(v) (v)
7231 +
7232 +/* general purpose memory allocation */
7233 +
7234 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7235 +#define MFREE(osh, addr, size) kfree(addr);
7236 +
7237 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7238 +
7239 +extern void *osl_malloc(osl_t *osh, uint size);
7240 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7241 +extern uint osl_malloced(osl_t *osh);
7242 +extern uint osl_malloc_failed(osl_t *osh);
7243 +
7244 +/* allocate/free shared (dma-able) consistent memory */
7245 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7246 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7247 + osl_dma_alloc_consistent((osh), (size), (pap))
7248 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7249 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7250 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7251 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7252 +
7253 +/* map/unmap direction */
7254 +#define DMA_TX 1
7255 +#define DMA_RX 2
7256 +
7257 +/* register access macros */
7258 +#if defined(BCMJTAG)
7259 +#include <bcmjtag.h>
7260 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7261 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7262 +#endif
7263 +
7264 +/*
7265 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7266 + * Macros expand to calls to functions defined in linux_osl.c .
7267 + */
7268 +#ifndef BINOSL
7269 +
7270 +/* string library, kernel mode */
7271 +#define printf(fmt, args...) printk(fmt, ## args)
7272 +#include <linux/kernel.h>
7273 +#include <linux/string.h>
7274 +
7275 +/* register access macros */
7276 +#if !defined(BCMJTAG)
7277 +#ifndef IL_BIGENDIAN
7278 +#define R_REG(r) ( \
7279 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7280 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7281 + readl((volatile uint32*)(r)) \
7282 +)
7283 +#define W_REG(r, v) do { \
7284 + switch (sizeof(*(r))) { \
7285 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7286 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7287 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7288 + } \
7289 +} while (0)
7290 +#else /* IL_BIGENDIAN */
7291 +#define R_REG(r) ({ \
7292 + __typeof(*(r)) __osl_v; \
7293 + switch (sizeof(*(r))) { \
7294 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7295 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7296 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7297 + } \
7298 + __osl_v; \
7299 +})
7300 +#define W_REG(r, v) do { \
7301 + switch (sizeof(*(r))) { \
7302 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7303 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7304 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7305 + } \
7306 +} while (0)
7307 +#endif
7308 +#endif
7309 +
7310 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7311 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7312 +
7313 +/* bcopy, bcmp, and bzero */
7314 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7315 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7316 +#define bzero(b, len) memset((b), '\0', (len))
7317 +
7318 +/* uncached virtual address */
7319 +#ifdef mips
7320 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7321 +#include <asm/addrspace.h>
7322 +#else
7323 +#define OSL_UNCACHED(va) (va)
7324 +#endif
7325 +
7326 +/* get processor cycle count */
7327 +#if defined(mips)
7328 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7329 +#elif defined(__i386__)
7330 +#define OSL_GETCYCLES(x) rdtscl((x))
7331 +#else
7332 +#define OSL_GETCYCLES(x) ((x) = 0)
7333 +#endif
7334 +
7335 +/* dereference an address that may cause a bus exception */
7336 +#ifdef mips
7337 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7338 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7339 +#else
7340 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7341 +#include <asm/paccess.h>
7342 +#endif
7343 +#else
7344 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7345 +#endif
7346 +
7347 +/* map/unmap physical to virtual I/O */
7348 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7349 +#define REG_UNMAP(va) iounmap((void *)(va))
7350 +
7351 +/* shared (dma-able) memory access macros */
7352 +#define R_SM(r) *(r)
7353 +#define W_SM(r, v) (*(r) = (v))
7354 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7355 +
7356 +/* packet primitives */
7357 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7358 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7359 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7360 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7361 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7362 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7363 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7364 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7365 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7366 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7367 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7368 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7369 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7370 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7371 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7372 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7373 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7374 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7375 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7376 +extern void osl_pktfree(void *skb);
7377 +
7378 +#else /* BINOSL */
7379 +
7380 +/* string library */
7381 +#ifndef LINUX_OSL
7382 +#undef printf
7383 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7384 +#undef sprintf
7385 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7386 +#undef strcmp
7387 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7388 +#undef strncmp
7389 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7390 +#undef strlen
7391 +#define strlen(s) osl_strlen((s))
7392 +#undef strcpy
7393 +#define strcpy(d, s) osl_strcpy((d), (s))
7394 +#undef strncpy
7395 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7396 +#endif
7397 +extern int osl_printf(const char *format, ...);
7398 +extern int osl_sprintf(char *buf, const char *format, ...);
7399 +extern int osl_strcmp(const char *s1, const char *s2);
7400 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7401 +extern int osl_strlen(const char *s);
7402 +extern char* osl_strcpy(char *d, const char *s);
7403 +extern char* osl_strncpy(char *d, const char *s, uint n);
7404 +
7405 +/* register access macros */
7406 +#if !defined(BCMJTAG)
7407 +#define R_REG(r) ( \
7408 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7409 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7410 + osl_readl((volatile uint32*)(r)) \
7411 +)
7412 +#define W_REG(r, v) do { \
7413 + switch (sizeof(*(r))) { \
7414 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7415 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7416 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7417 + } \
7418 +} while (0)
7419 +#endif
7420 +
7421 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7422 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7423 +extern uint8 osl_readb(volatile uint8 *r);
7424 +extern uint16 osl_readw(volatile uint16 *r);
7425 +extern uint32 osl_readl(volatile uint32 *r);
7426 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7427 +extern void osl_writew(uint16 v, volatile uint16 *r);
7428 +extern void osl_writel(uint32 v, volatile uint32 *r);
7429 +
7430 +/* bcopy, bcmp, and bzero */
7431 +extern void bcopy(const void *src, void *dst, int len);
7432 +extern int bcmp(const void *b1, const void *b2, int len);
7433 +extern void bzero(void *b, int len);
7434 +
7435 +/* uncached virtual address */
7436 +#define OSL_UNCACHED(va) osl_uncached((va))
7437 +extern void *osl_uncached(void *va);
7438 +
7439 +/* get processor cycle count */
7440 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7441 +extern uint osl_getcycles(void);
7442 +
7443 +/* dereference an address that may target abort */
7444 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7445 +extern int osl_busprobe(uint32 *val, uint32 addr);
7446 +
7447 +/* map/unmap physical to virtual */
7448 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7449 +#define REG_UNMAP(va) osl_reg_unmap((va))
7450 +extern void *osl_reg_map(uint32 pa, uint size);
7451 +extern void osl_reg_unmap(void *va);
7452 +
7453 +/* shared (dma-able) memory access macros */
7454 +#define R_SM(r) *(r)
7455 +#define W_SM(r, v) (*(r) = (v))
7456 +#define BZERO_SM(r, len) bzero((r), (len))
7457 +
7458 +/* packet primitives */
7459 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7460 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7461 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7462 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7463 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7464 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7465 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7466 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7467 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7468 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7469 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7470 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7471 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7472 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7473 +#define PKTLINK(skb) osl_pktlink((skb))
7474 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7475 +#define PKTPRIO(skb) osl_pktprio((skb))
7476 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7477 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7478 +extern void osl_pktfree(void *skb);
7479 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7480 +extern uint osl_pktlen(osl_t *osh, void *skb);
7481 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7482 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7483 +extern void *osl_pktnext(osl_t *osh, void *skb);
7484 +extern void osl_pktsetnext(void *skb, void *x);
7485 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7486 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7487 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7488 +extern void *osl_pktdup(osl_t *osh, void *skb);
7489 +extern void *osl_pktcookie(void *skb);
7490 +extern void osl_pktsetcookie(void *skb, void *x);
7491 +extern void *osl_pktlink(void *skb);
7492 +extern void osl_pktsetlink(void *skb, void *x);
7493 +extern uint osl_pktprio(void *skb);
7494 +extern void osl_pktsetprio(void *skb, uint x);
7495 +
7496 +#endif /* BINOSL */
7497 +
7498 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7499 +extern int osl_error(int bcmerror);
7500 +
7501 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7502 +#define PKTBUFSZ 2048
7503 +
7504 +#endif /* _linux_osl_h_ */
7505 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7506 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7507 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-15 23:29:14.000000000 +0200
7508 @@ -0,0 +1,389 @@
7509 +/*
7510 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7511 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7512 + *
7513 + * Copyright 2005, Broadcom Corporation
7514 + * All Rights Reserved.
7515 + *
7516 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7517 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7518 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7519 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7520 + *
7521 + * $Id$
7522 + */
7523 +
7524 +#ifndef _linuxver_h_
7525 +#define _linuxver_h_
7526 +
7527 +#include <linux/config.h>
7528 +#include <linux/version.h>
7529 +
7530 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7531 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7532 +#ifdef __UNDEF_NO_VERSION__
7533 +#undef __NO_VERSION__
7534 +#else
7535 +#define __NO_VERSION__
7536 +#endif
7537 +#endif
7538 +
7539 +#if defined(MODULE) && defined(MODVERSIONS)
7540 +#include <linux/modversions.h>
7541 +#endif
7542 +
7543 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7544 +#include <linux/moduleparam.h>
7545 +#endif
7546 +
7547 +
7548 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7549 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7550 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7551 +#endif
7552 +
7553 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7554 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7555 +#include <linux/malloc.h>
7556 +#else
7557 +#include <linux/slab.h>
7558 +#endif
7559 +
7560 +#include <linux/types.h>
7561 +#include <linux/init.h>
7562 +#include <linux/mm.h>
7563 +#include <linux/string.h>
7564 +#include <linux/pci.h>
7565 +#include <linux/interrupt.h>
7566 +#include <linux/netdevice.h>
7567 +#include <asm/io.h>
7568 +
7569 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7570 +#include <linux/workqueue.h>
7571 +#else
7572 +#include <linux/tqueue.h>
7573 +#ifndef work_struct
7574 +#define work_struct tq_struct
7575 +#endif
7576 +#ifndef INIT_WORK
7577 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7578 +#endif
7579 +#ifndef schedule_work
7580 +#define schedule_work(_work) schedule_task((_work))
7581 +#endif
7582 +#ifndef flush_scheduled_work
7583 +#define flush_scheduled_work() flush_scheduled_tasks()
7584 +#endif
7585 +#endif
7586 +
7587 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7588 +/* Some distributions have their own 2.6.x compatibility layers */
7589 +#ifndef IRQ_NONE
7590 +typedef void irqreturn_t;
7591 +#define IRQ_NONE
7592 +#define IRQ_HANDLED
7593 +#define IRQ_RETVAL(x)
7594 +#endif
7595 +#else
7596 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7597 +#endif
7598 +
7599 +#ifndef __exit
7600 +#define __exit
7601 +#endif
7602 +#ifndef __devexit
7603 +#define __devexit
7604 +#endif
7605 +#ifndef __devinit
7606 +#define __devinit __init
7607 +#endif
7608 +#ifndef __devinitdata
7609 +#define __devinitdata
7610 +#endif
7611 +#ifndef __devexit_p
7612 +#define __devexit_p(x) x
7613 +#endif
7614 +
7615 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7616 +
7617 +#define pci_get_drvdata(dev) (dev)->sysdata
7618 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7619 +
7620 +/*
7621 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7622 + */
7623 +
7624 +struct pci_device_id {
7625 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7626 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7627 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7628 + unsigned long driver_data; /* Data private to the driver */
7629 +};
7630 +
7631 +struct pci_driver {
7632 + struct list_head node;
7633 + char *name;
7634 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7635 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7636 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7637 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7638 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7639 +};
7640 +
7641 +#define MODULE_DEVICE_TABLE(type, name)
7642 +#define PCI_ANY_ID (~0)
7643 +
7644 +/* compatpci.c */
7645 +#define pci_module_init pci_register_driver
7646 +extern int pci_register_driver(struct pci_driver *drv);
7647 +extern void pci_unregister_driver(struct pci_driver *drv);
7648 +
7649 +#endif /* PCI registration */
7650 +
7651 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7652 +#ifdef MODULE
7653 +#define module_init(x) int init_module(void) { return x(); }
7654 +#define module_exit(x) void cleanup_module(void) { x(); }
7655 +#else
7656 +#define module_init(x) __initcall(x);
7657 +#define module_exit(x) __exitcall(x);
7658 +#endif
7659 +#endif
7660 +
7661 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7662 +#define list_for_each(pos, head) \
7663 + for (pos = (head)->next; pos != (head); pos = pos->next)
7664 +#endif
7665 +
7666 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7667 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7668 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7669 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7670 +#endif
7671 +
7672 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7673 +#define pci_enable_device(dev) do { } while (0)
7674 +#endif
7675 +
7676 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7677 +#define net_device device
7678 +#endif
7679 +
7680 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7681 +
7682 +/*
7683 + * DMA mapping
7684 + *
7685 + * See linux/Documentation/DMA-mapping.txt
7686 + */
7687 +
7688 +#ifndef PCI_DMA_TODEVICE
7689 +#define PCI_DMA_TODEVICE 1
7690 +#define PCI_DMA_FROMDEVICE 2
7691 +#endif
7692 +
7693 +typedef u32 dma_addr_t;
7694 +
7695 +/* Pure 2^n version of get_order */
7696 +static inline int get_order(unsigned long size)
7697 +{
7698 + int order;
7699 +
7700 + size = (size-1) >> (PAGE_SHIFT-1);
7701 + order = -1;
7702 + do {
7703 + size >>= 1;
7704 + order++;
7705 + } while (size);
7706 + return order;
7707 +}
7708 +
7709 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7710 + dma_addr_t *dma_handle)
7711 +{
7712 + void *ret;
7713 + int gfp = GFP_ATOMIC | GFP_DMA;
7714 +
7715 + ret = (void *)__get_free_pages(gfp, get_order(size));
7716 +
7717 + if (ret != NULL) {
7718 + memset(ret, 0, size);
7719 + *dma_handle = virt_to_bus(ret);
7720 + }
7721 + return ret;
7722 +}
7723 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7724 + void *vaddr, dma_addr_t dma_handle)
7725 +{
7726 + free_pages((unsigned long)vaddr, get_order(size));
7727 +}
7728 +#ifdef ILSIM
7729 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7730 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7731 +#else
7732 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7733 +#define pci_unmap_single(cookie, address, size, dir)
7734 +#endif
7735 +
7736 +#endif /* DMA mapping */
7737 +
7738 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7739 +
7740 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7741 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7742 +
7743 +/* pcmcia-cs provides its own netdevice compatibility layer */
7744 +#ifndef _COMPAT_NETDEVICE_H
7745 +
7746 +/*
7747 + * SoftNet
7748 + *
7749 + * For pre-softnet kernels we need to tell the upper layer not to
7750 + * re-enter start_xmit() while we are in there. However softnet
7751 + * guarantees not to enter while we are in there so there is no need
7752 + * to do the netif_stop_queue() dance unless the transmit queue really
7753 + * gets stuck. This should also improve performance according to tests
7754 + * done by Aman Singla.
7755 + */
7756 +
7757 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7758 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7759 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7760 +
7761 +static inline void netif_start_queue(struct net_device *dev)
7762 +{
7763 + dev->tbusy = 0;
7764 + dev->interrupt = 0;
7765 + dev->start = 1;
7766 +}
7767 +
7768 +#define netif_queue_stopped(dev) (dev)->tbusy
7769 +#define netif_running(dev) (dev)->start
7770 +
7771 +#endif /* _COMPAT_NETDEVICE_H */
7772 +
7773 +#define netif_device_attach(dev) netif_start_queue(dev)
7774 +#define netif_device_detach(dev) netif_stop_queue(dev)
7775 +
7776 +/* 2.4.x renamed bottom halves to tasklets */
7777 +#define tasklet_struct tq_struct
7778 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7779 +{
7780 + queue_task(tasklet, &tq_immediate);
7781 + mark_bh(IMMEDIATE_BH);
7782 +}
7783 +
7784 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7785 + void (*func)(unsigned long),
7786 + unsigned long data)
7787 +{
7788 + tasklet->next = NULL;
7789 + tasklet->sync = 0;
7790 + tasklet->routine = (void (*)(void *))func;
7791 + tasklet->data = (void *)data;
7792 +}
7793 +#define tasklet_kill(tasklet) {do{} while(0);}
7794 +
7795 +/* 2.4.x introduced del_timer_sync() */
7796 +#define del_timer_sync(timer) del_timer(timer)
7797 +
7798 +#else
7799 +
7800 +#define netif_down(dev)
7801 +
7802 +#endif /* SoftNet */
7803 +
7804 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7805 +
7806 +/*
7807 + * Emit code to initialise a tq_struct's routine and data pointers
7808 + */
7809 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7810 + do { \
7811 + (_tq)->routine = _routine; \
7812 + (_tq)->data = _data; \
7813 + } while (0)
7814 +
7815 +/*
7816 + * Emit code to initialise all of a tq_struct
7817 + */
7818 +#define INIT_TQUEUE(_tq, _routine, _data) \
7819 + do { \
7820 + INIT_LIST_HEAD(&(_tq)->list); \
7821 + (_tq)->sync = 0; \
7822 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7823 + } while (0)
7824 +
7825 +#endif
7826 +
7827 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7828 +
7829 +/* Power management related routines */
7830 +
7831 +static inline int
7832 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7833 +{
7834 + int i;
7835 + if (buffer) {
7836 + for (i = 0; i < 16; i++)
7837 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7838 + }
7839 + return 0;
7840 +}
7841 +
7842 +static inline int
7843 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7844 +{
7845 + int i;
7846 +
7847 + if (buffer) {
7848 + for (i = 0; i < 16; i++)
7849 + pci_write_config_dword(dev,i * 4, buffer[i]);
7850 + }
7851 + /*
7852 + * otherwise, write the context information we know from bootup.
7853 + * This works around a problem where warm-booting from Windows
7854 + * combined with a D3(hot)->D0 transition causes PCI config
7855 + * header data to be forgotten.
7856 + */
7857 + else {
7858 + for (i = 0; i < 6; i ++)
7859 + pci_write_config_dword(dev,
7860 + PCI_BASE_ADDRESS_0 + (i * 4),
7861 + pci_resource_start(dev, i));
7862 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7863 + }
7864 + return 0;
7865 +}
7866 +
7867 +#endif /* PCI power management */
7868 +
7869 +/* Old cp0 access macros deprecated in 2.4.19 */
7870 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7871 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7872 +#endif
7873 +
7874 +/* Module refcount handled internally in 2.6.x */
7875 +#ifndef SET_MODULE_OWNER
7876 +#define SET_MODULE_OWNER(dev) do {} while (0)
7877 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7878 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7879 +#else
7880 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7881 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7882 +#endif
7883 +
7884 +#ifndef SET_NETDEV_DEV
7885 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7886 +#endif
7887 +
7888 +#ifndef HAVE_FREE_NETDEV
7889 +#define free_netdev(dev) kfree(dev)
7890 +#endif
7891 +
7892 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7893 +/* struct packet_type redefined in 2.6.x */
7894 +#define af_packet_priv data
7895 +#endif
7896 +
7897 +#endif /* _linuxver_h_ */
7898 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7899 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7900 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-15 23:29:14.000000000 +0200
7901 @@ -0,0 +1,552 @@
7902 +/*
7903 + * HND Run Time Environment for standalone MIPS programs.
7904 + *
7905 + * Copyright 2005, Broadcom Corporation
7906 + * All Rights Reserved.
7907 + *
7908 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7909 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7910 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7911 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7912 + *
7913 + * $Id$
7914 + */
7915 +
7916 +#ifndef _MISPINC_H
7917 +#define _MISPINC_H
7918 +
7919 +
7920 +/* MIPS defines */
7921 +
7922 +#ifdef _LANGUAGE_ASSEMBLY
7923 +
7924 +/*
7925 + * Symbolic register names for 32 bit ABI
7926 + */
7927 +#define zero $0 /* wired zero */
7928 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7929 +#define v0 $2 /* return value */
7930 +#define v1 $3
7931 +#define a0 $4 /* argument registers */
7932 +#define a1 $5
7933 +#define a2 $6
7934 +#define a3 $7
7935 +#define t0 $8 /* caller saved */
7936 +#define t1 $9
7937 +#define t2 $10
7938 +#define t3 $11
7939 +#define t4 $12
7940 +#define t5 $13
7941 +#define t6 $14
7942 +#define t7 $15
7943 +#define s0 $16 /* callee saved */
7944 +#define s1 $17
7945 +#define s2 $18
7946 +#define s3 $19
7947 +#define s4 $20
7948 +#define s5 $21
7949 +#define s6 $22
7950 +#define s7 $23
7951 +#define t8 $24 /* caller saved */
7952 +#define t9 $25
7953 +#define jp $25 /* PIC jump register */
7954 +#define k0 $26 /* kernel scratch */
7955 +#define k1 $27
7956 +#define gp $28 /* global pointer */
7957 +#define sp $29 /* stack pointer */
7958 +#define fp $30 /* frame pointer */
7959 +#define s8 $30 /* same like fp! */
7960 +#define ra $31 /* return address */
7961 +
7962 +
7963 +/*
7964 + * CP0 Registers
7965 + */
7966 +
7967 +#define C0_INX $0
7968 +#define C0_RAND $1
7969 +#define C0_TLBLO0 $2
7970 +#define C0_TLBLO C0_TLBLO0
7971 +#define C0_TLBLO1 $3
7972 +#define C0_CTEXT $4
7973 +#define C0_PGMASK $5
7974 +#define C0_WIRED $6
7975 +#define C0_BADVADDR $8
7976 +#define C0_COUNT $9
7977 +#define C0_TLBHI $10
7978 +#define C0_COMPARE $11
7979 +#define C0_SR $12
7980 +#define C0_STATUS C0_SR
7981 +#define C0_CAUSE $13
7982 +#define C0_EPC $14
7983 +#define C0_PRID $15
7984 +#define C0_CONFIG $16
7985 +#define C0_LLADDR $17
7986 +#define C0_WATCHLO $18
7987 +#define C0_WATCHHI $19
7988 +#define C0_XCTEXT $20
7989 +#define C0_DIAGNOSTIC $22
7990 +#define C0_BROADCOM C0_DIAGNOSTIC
7991 +#define C0_PERFORMANCE $25
7992 +#define C0_ECC $26
7993 +#define C0_CACHEERR $27
7994 +#define C0_TAGLO $28
7995 +#define C0_TAGHI $29
7996 +#define C0_ERREPC $30
7997 +#define C0_DESAVE $31
7998 +
7999 +/*
8000 + * LEAF - declare leaf routine
8001 + */
8002 +#define LEAF(symbol) \
8003 + .globl symbol; \
8004 + .align 2; \
8005 + .type symbol,@function; \
8006 + .ent symbol,0; \
8007 +symbol: .frame sp,0,ra
8008 +
8009 +/*
8010 + * END - mark end of function
8011 + */
8012 +#define END(function) \
8013 + .end function; \
8014 + .size function,.-function
8015 +
8016 +#define _ULCAST_
8017 +
8018 +#else
8019 +
8020 +/*
8021 + * The following macros are especially useful for __asm__
8022 + * inline assembler.
8023 + */
8024 +#ifndef __STR
8025 +#define __STR(x) #x
8026 +#endif
8027 +#ifndef STR
8028 +#define STR(x) __STR(x)
8029 +#endif
8030 +
8031 +#define _ULCAST_ (unsigned long)
8032 +
8033 +
8034 +/*
8035 + * CP0 Registers
8036 + */
8037 +
8038 +#define C0_INX 0 /* CP0: TLB Index */
8039 +#define C0_RAND 1 /* CP0: TLB Random */
8040 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
8041 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
8042 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
8043 +#define C0_CTEXT 4 /* CP0: Context */
8044 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
8045 +#define C0_WIRED 6 /* CP0: TLB Wired */
8046 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
8047 +#define C0_COUNT 9 /* CP0: Count */
8048 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
8049 +#define C0_COMPARE 11 /* CP0: Compare */
8050 +#define C0_SR 12 /* CP0: Processor Status */
8051 +#define C0_STATUS C0_SR /* CP0: Processor Status */
8052 +#define C0_CAUSE 13 /* CP0: Exception Cause */
8053 +#define C0_EPC 14 /* CP0: Exception PC */
8054 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
8055 +#define C0_CONFIG 16 /* CP0: Config */
8056 +#define C0_LLADDR 17 /* CP0: LLAddr */
8057 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
8058 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
8059 +#define C0_XCTEXT 20 /* CP0: XContext */
8060 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
8061 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
8062 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
8063 +#define C0_ECC 26 /* CP0: ECC */
8064 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8065 +#define C0_TAGLO 28 /* CP0: TagLo */
8066 +#define C0_TAGHI 29 /* CP0: TagHi */
8067 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8068 +#define C0_DESAVE 31 /* CP0: DebugSave */
8069 +
8070 +#endif /* _LANGUAGE_ASSEMBLY */
8071 +
8072 +/*
8073 + * Memory segments (32bit kernel mode addresses)
8074 + */
8075 +#undef KUSEG
8076 +#undef KSEG0
8077 +#undef KSEG1
8078 +#undef KSEG2
8079 +#undef KSEG3
8080 +#define KUSEG 0x00000000
8081 +#define KSEG0 0x80000000
8082 +#define KSEG1 0xa0000000
8083 +#define KSEG2 0xc0000000
8084 +#define KSEG3 0xe0000000
8085 +#define PHYSADDR_MASK 0x1fffffff
8086 +
8087 +/*
8088 + * Map an address to a certain kernel segment
8089 + */
8090 +#undef PHYSADDR
8091 +#undef KSEG0ADDR
8092 +#undef KSEG1ADDR
8093 +#undef KSEG2ADDR
8094 +#undef KSEG3ADDR
8095 +
8096 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8097 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8098 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8099 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8100 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8101 +
8102 +
8103 +#ifndef Index_Invalidate_I
8104 +/*
8105 + * Cache Operations
8106 + */
8107 +#define Index_Invalidate_I 0x00
8108 +#define Index_Writeback_Inv_D 0x01
8109 +#define Index_Invalidate_SI 0x02
8110 +#define Index_Writeback_Inv_SD 0x03
8111 +#define Index_Load_Tag_I 0x04
8112 +#define Index_Load_Tag_D 0x05
8113 +#define Index_Load_Tag_SI 0x06
8114 +#define Index_Load_Tag_SD 0x07
8115 +#define Index_Store_Tag_I 0x08
8116 +#define Index_Store_Tag_D 0x09
8117 +#define Index_Store_Tag_SI 0x0A
8118 +#define Index_Store_Tag_SD 0x0B
8119 +#define Create_Dirty_Excl_D 0x0d
8120 +#define Create_Dirty_Excl_SD 0x0f
8121 +#define Hit_Invalidate_I 0x10
8122 +#define Hit_Invalidate_D 0x11
8123 +#define Hit_Invalidate_SI 0x12
8124 +#define Hit_Invalidate_SD 0x13
8125 +#define Fill_I 0x14
8126 +#define Hit_Writeback_Inv_D 0x15
8127 + /* 0x16 is unused */
8128 +#define Hit_Writeback_Inv_SD 0x17
8129 +#define R5K_Page_Invalidate_S 0x17
8130 +#define Hit_Writeback_I 0x18
8131 +#define Hit_Writeback_D 0x19
8132 + /* 0x1a is unused */
8133 +#define Hit_Writeback_SD 0x1b
8134 + /* 0x1c is unused */
8135 + /* 0x1e is unused */
8136 +#define Hit_Set_Virtual_SI 0x1e
8137 +#define Hit_Set_Virtual_SD 0x1f
8138 +#endif
8139 +
8140 +
8141 +/*
8142 + * R4x00 interrupt enable / cause bits
8143 + */
8144 +#define IE_SW0 (_ULCAST_(1) << 8)
8145 +#define IE_SW1 (_ULCAST_(1) << 9)
8146 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8147 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8148 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8149 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8150 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8151 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8152 +
8153 +#ifndef ST0_UM
8154 +/*
8155 + * Bitfields in the mips32 cp0 status register
8156 + */
8157 +#define ST0_IE 0x00000001
8158 +#define ST0_EXL 0x00000002
8159 +#define ST0_ERL 0x00000004
8160 +#define ST0_UM 0x00000010
8161 +#define ST0_SWINT0 0x00000100
8162 +#define ST0_SWINT1 0x00000200
8163 +#define ST0_HWINT0 0x00000400
8164 +#define ST0_HWINT1 0x00000800
8165 +#define ST0_HWINT2 0x00001000
8166 +#define ST0_HWINT3 0x00002000
8167 +#define ST0_HWINT4 0x00004000
8168 +#define ST0_HWINT5 0x00008000
8169 +#define ST0_IM 0x0000ff00
8170 +#define ST0_NMI 0x00080000
8171 +#define ST0_SR 0x00100000
8172 +#define ST0_TS 0x00200000
8173 +#define ST0_BEV 0x00400000
8174 +#define ST0_RE 0x02000000
8175 +#define ST0_RP 0x08000000
8176 +#define ST0_CU 0xf0000000
8177 +#define ST0_CU0 0x10000000
8178 +#define ST0_CU1 0x20000000
8179 +#define ST0_CU2 0x40000000
8180 +#define ST0_CU3 0x80000000
8181 +#endif
8182 +
8183 +
8184 +/*
8185 + * Bitfields in the mips32 cp0 cause register
8186 + */
8187 +#define C_EXC 0x0000007c
8188 +#define C_EXC_SHIFT 2
8189 +#define C_INT 0x0000ff00
8190 +#define C_INT_SHIFT 8
8191 +#define C_SW0 (_ULCAST_(1) << 8)
8192 +#define C_SW1 (_ULCAST_(1) << 9)
8193 +#define C_IRQ0 (_ULCAST_(1) << 10)
8194 +#define C_IRQ1 (_ULCAST_(1) << 11)
8195 +#define C_IRQ2 (_ULCAST_(1) << 12)
8196 +#define C_IRQ3 (_ULCAST_(1) << 13)
8197 +#define C_IRQ4 (_ULCAST_(1) << 14)
8198 +#define C_IRQ5 (_ULCAST_(1) << 15)
8199 +#define C_WP 0x00400000
8200 +#define C_IV 0x00800000
8201 +#define C_CE 0x30000000
8202 +#define C_CE_SHIFT 28
8203 +#define C_BD 0x80000000
8204 +
8205 +/* Values in C_EXC */
8206 +#define EXC_INT 0
8207 +#define EXC_TLBM 1
8208 +#define EXC_TLBL 2
8209 +#define EXC_TLBS 3
8210 +#define EXC_AEL 4
8211 +#define EXC_AES 5
8212 +#define EXC_IBE 6
8213 +#define EXC_DBE 7
8214 +#define EXC_SYS 8
8215 +#define EXC_BPT 9
8216 +#define EXC_RI 10
8217 +#define EXC_CU 11
8218 +#define EXC_OV 12
8219 +#define EXC_TR 13
8220 +#define EXC_WATCH 23
8221 +#define EXC_MCHK 24
8222 +
8223 +
8224 +/*
8225 + * Bits in the cp0 config register.
8226 + */
8227 +#define CONF_CM_CACHABLE_NO_WA 0
8228 +#define CONF_CM_CACHABLE_WA 1
8229 +#define CONF_CM_UNCACHED 2
8230 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8231 +#define CONF_CM_CACHABLE_CE 4
8232 +#define CONF_CM_CACHABLE_COW 5
8233 +#define CONF_CM_CACHABLE_CUW 6
8234 +#define CONF_CM_CACHABLE_ACCELERATED 7
8235 +#define CONF_CM_CMASK 7
8236 +#define CONF_CU (_ULCAST_(1) << 3)
8237 +#define CONF_DB (_ULCAST_(1) << 4)
8238 +#define CONF_IB (_ULCAST_(1) << 5)
8239 +#define CONF_SE (_ULCAST_(1) << 12)
8240 +#define CONF_SC (_ULCAST_(1) << 17)
8241 +#define CONF_AC (_ULCAST_(1) << 23)
8242 +#define CONF_HALT (_ULCAST_(1) << 25)
8243 +
8244 +
8245 +/*
8246 + * Bits in the cp0 config register select 1.
8247 + */
8248 +#define CONF1_FP 0x00000001 /* FPU present */
8249 +#define CONF1_EP 0x00000002 /* EJTAG present */
8250 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8251 +#define CONF1_WR 0x00000008 /* Watch registers present */
8252 +#define CONF1_PC 0x00000010 /* Performance counters present */
8253 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8254 +#define CONF1_DA_MASK 0x00000380
8255 +#define CONF1_DA_BASE 1
8256 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8257 +#define CONF1_DL_MASK 0x00001c00
8258 +#define CONF1_DL_BASE 2
8259 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8260 +#define CONF1_DS_MASK 0x0000e000
8261 +#define CONF1_DS_BASE 64
8262 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8263 +#define CONF1_IA_MASK 0x00070000
8264 +#define CONF1_IA_BASE 1
8265 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8266 +#define CONF1_IL_MASK 0x00380000
8267 +#define CONF1_IL_BASE 2
8268 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8269 +#define CONF1_IS_MASK 0x01c00000
8270 +#define CONF1_IS_BASE 64
8271 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8272 +#define CONF1_MS_SHIFT 25
8273 +
8274 +/* PRID register */
8275 +#define PRID_COPT_MASK 0xff000000
8276 +#define PRID_COMP_MASK 0x00ff0000
8277 +#define PRID_IMP_MASK 0x0000ff00
8278 +#define PRID_REV_MASK 0x000000ff
8279 +
8280 +#define PRID_COMP_LEGACY 0x000000
8281 +#define PRID_COMP_MIPS 0x010000
8282 +#define PRID_COMP_BROADCOM 0x020000
8283 +#define PRID_COMP_ALCHEMY 0x030000
8284 +#define PRID_COMP_SIBYTE 0x040000
8285 +#define PRID_IMP_BCM4710 0x4000
8286 +#define PRID_IMP_BCM3302 0x9000
8287 +#define PRID_IMP_BCM3303 0x9100
8288 +
8289 +#define PRID_IMP_UNKNOWN 0xff00
8290 +
8291 +#define BCM330X(id) \
8292 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8293 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8294 +
8295 +/* Bits in C0_BROADCOM */
8296 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8297 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8298 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8299 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8300 +
8301 +/* PreFetch Cache aka Read Ahead Cache */
8302 +
8303 +#define PFC_CR0 0xff400000 /* control reg 0 */
8304 +#define PFC_CR1 0xff400004 /* control reg 1 */
8305 +
8306 +/* PFC operations */
8307 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8308 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8309 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8310 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8311 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8312 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8313 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8314 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8315 +#define PFC_BRR 0x40000000 /* Bus error indication */
8316 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8317 +
8318 +/* Handy defaults */
8319 +#define PFC_DISABLED 0
8320 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8321 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8322 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8323 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8324 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8325 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8326 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8327 +
8328 +
8329 +/*
8330 + * These are the UART port assignments, expressed as offsets from the base
8331 + * register. These assignments should hold for any serial port based on
8332 + * a 8250, 16450, or 16550(A).
8333 + */
8334 +
8335 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8336 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8337 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8338 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8339 +#define UART_LCR 3 /* Out: Line Control Register */
8340 +#define UART_MCR 4 /* Out: Modem Control Register */
8341 +#define UART_LSR 5 /* In: Line Status Register */
8342 +#define UART_MSR 6 /* In: Modem Status Register */
8343 +#define UART_SCR 7 /* I/O: Scratch Register */
8344 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8345 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8346 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8347 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8348 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8349 +
8350 +
8351 +#ifndef _LANGUAGE_ASSEMBLY
8352 +
8353 +/*
8354 + * Macros to access the system control coprocessor
8355 + */
8356 +
8357 +#define MFC0(source, sel) \
8358 +({ \
8359 + int __res; \
8360 + __asm__ __volatile__( \
8361 + ".set\tnoreorder\n\t" \
8362 + ".set\tnoat\n\t" \
8363 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8364 + "move\t%0,$1\n\t" \
8365 + ".set\tat\n\t" \
8366 + ".set\treorder" \
8367 + :"=r" (__res) \
8368 + : \
8369 + :"$1"); \
8370 + __res; \
8371 +})
8372 +
8373 +#define MTC0(source, sel, value) \
8374 +do { \
8375 + __asm__ __volatile__( \
8376 + ".set\tnoreorder\n\t" \
8377 + ".set\tnoat\n\t" \
8378 + "move\t$1,%z0\n\t" \
8379 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8380 + ".set\tat\n\t" \
8381 + ".set\treorder" \
8382 + : \
8383 + :"jr" (value) \
8384 + :"$1"); \
8385 +} while (0)
8386 +
8387 +#define get_c0_count() \
8388 +({ \
8389 + int __res; \
8390 + __asm__ __volatile__( \
8391 + ".set\tnoreorder\n\t" \
8392 + ".set\tnoat\n\t" \
8393 + "mfc0\t%0,$9\n\t" \
8394 + ".set\tat\n\t" \
8395 + ".set\treorder" \
8396 + :"=r" (__res)); \
8397 + __res; \
8398 +})
8399 +
8400 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8401 +{
8402 + uint lsz, sets, ways;
8403 +
8404 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8405 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8406 + lsz = CONF1_IL_BASE << lsz;
8407 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8408 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8409 + *size = lsz * sets * ways;
8410 + *lsize = lsz;
8411 +}
8412 +
8413 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8414 +{
8415 + uint lsz, sets, ways;
8416 +
8417 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8418 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8419 + lsz = CONF1_DL_BASE << lsz;
8420 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8421 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8422 + *size = lsz * sets * ways;
8423 + *lsize = lsz;
8424 +}
8425 +
8426 +#define cache_op(base, op) \
8427 + __asm__ __volatile__(" \
8428 + .set noreorder; \
8429 + .set mips3; \
8430 + cache %1, (%0); \
8431 + .set mips0; \
8432 + .set reorder" \
8433 + : \
8434 + : "r" (base), \
8435 + "i" (op));
8436 +
8437 +#define cache_unroll4(base, delta, op) \
8438 + __asm__ __volatile__(" \
8439 + .set noreorder; \
8440 + .set mips3; \
8441 + cache %1,0(%0); \
8442 + cache %1,delta(%0); \
8443 + cache %1,(2 * delta)(%0); \
8444 + cache %1,(3 * delta)(%0); \
8445 + .set mips0; \
8446 + .set reorder" \
8447 + : \
8448 + : "r" (base), \
8449 + "i" (op));
8450 +
8451 +#endif /* !_LANGUAGE_ASSEMBLY */
8452 +
8453 +#endif /* _MISPINC_H */
8454 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8455 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8456 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-15 23:29:14.000000000 +0200
8457 @@ -0,0 +1,42 @@
8458 +/*
8459 + * OS Abstraction Layer
8460 + *
8461 + * Copyright 2005, Broadcom Corporation
8462 + * All Rights Reserved.
8463 + *
8464 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8465 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8466 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8467 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8468 + * $Id$
8469 + */
8470 +
8471 +#ifndef _osl_h_
8472 +#define _osl_h_
8473 +
8474 +/* osl handle type forward declaration */
8475 +typedef struct os_handle osl_t;
8476 +
8477 +#if defined(linux)
8478 +#include <linux_osl.h>
8479 +#elif defined(NDIS)
8480 +#include <ndis_osl.h>
8481 +#elif defined(_CFE_)
8482 +#include <cfe_osl.h>
8483 +#elif defined(_HNDRTE_)
8484 +#include <hndrte_osl.h>
8485 +#elif defined(_MINOSL_)
8486 +#include <min_osl.h>
8487 +#elif PMON
8488 +#include <pmon_osl.h>
8489 +#elif defined(MACOSX)
8490 +#include <macosx_osl.h>
8491 +#else
8492 +#error "Unsupported OSL requested"
8493 +#endif
8494 +
8495 +/* handy */
8496 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8497 +#define MAXPRIO 7 /* 0-7 */
8498 +
8499 +#endif /* _osl_h_ */
8500 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8501 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8502 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-15 23:29:14.000000000 +0200
8503 @@ -0,0 +1,398 @@
8504 +/*
8505 + * pcicfg.h: PCI configuration constants and structures.
8506 + *
8507 + * Copyright 2005, Broadcom Corporation
8508 + * All Rights Reserved.
8509 + *
8510 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8511 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8512 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8513 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8514 + *
8515 + * $Id$
8516 + */
8517 +
8518 +#ifndef _h_pci_
8519 +#define _h_pci_
8520 +
8521 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8522 +#ifndef PCI_MAX_BUS
8523 +#define PCI_MAX_BUS 0x100
8524 +#endif
8525 +#ifndef PCI_MAX_DEVICES
8526 +#define PCI_MAX_DEVICES 0x20
8527 +#endif
8528 +#ifndef PCI_MAX_FUNCTION
8529 +#define PCI_MAX_FUNCTION 0x8
8530 +#endif
8531 +
8532 +#ifndef PCI_INVALID_VENDORID
8533 +#define PCI_INVALID_VENDORID 0xffff
8534 +#endif
8535 +#ifndef PCI_INVALID_DEVICEID
8536 +#define PCI_INVALID_DEVICEID 0xffff
8537 +#endif
8538 +
8539 +
8540 +/* Convert between bus-slot-function-register and config addresses */
8541 +
8542 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8543 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8544 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8545 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8546 +
8547 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8548 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8549 +#define PCICFG_FUN_MASK 7 /* Function mask */
8550 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8551 +
8552 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8553 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8554 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8555 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8556 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8557 +
8558 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8559 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8560 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8561 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8562 +
8563 +/* The actual config space */
8564 +
8565 +#define PCI_BAR_MAX 6
8566 +
8567 +#define PCI_ROM_BAR 8
8568 +
8569 +#define PCR_RSVDA_MAX 2
8570 +
8571 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8572 +
8573 +#define PCI_CAPPTR_PRESENT 0x0010
8574 +
8575 +typedef struct _pci_config_regs {
8576 + unsigned short vendor;
8577 + unsigned short device;
8578 + unsigned short command;
8579 + unsigned short status;
8580 + unsigned char rev_id;
8581 + unsigned char prog_if;
8582 + unsigned char sub_class;
8583 + unsigned char base_class;
8584 + unsigned char cache_line_size;
8585 + unsigned char latency_timer;
8586 + unsigned char header_type;
8587 + unsigned char bist;
8588 + unsigned long base[PCI_BAR_MAX];
8589 + unsigned long cardbus_cis;
8590 + unsigned short subsys_vendor;
8591 + unsigned short subsys_id;
8592 + unsigned long baserom;
8593 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8594 + unsigned char int_line;
8595 + unsigned char int_pin;
8596 + unsigned char min_gnt;
8597 + unsigned char max_lat;
8598 + unsigned char dev_dep[192];
8599 +} pci_config_regs;
8600 +
8601 +#define SZPCR (sizeof (pci_config_regs))
8602 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8603 +
8604 +/* A structure for the config registers is nice, but in most
8605 + * systems the config space is not memory mapped, so we need
8606 + * filed offsetts. :-(
8607 + */
8608 +#define PCI_CFG_VID 0
8609 +#define PCI_CFG_DID 2
8610 +#define PCI_CFG_CMD 4
8611 +#define PCI_CFG_STAT 6
8612 +#define PCI_CFG_REV 8
8613 +#define PCI_CFG_PROGIF 9
8614 +#define PCI_CFG_SUBCL 0xa
8615 +#define PCI_CFG_BASECL 0xb
8616 +#define PCI_CFG_CLSZ 0xc
8617 +#define PCI_CFG_LATTIM 0xd
8618 +#define PCI_CFG_HDR 0xe
8619 +#define PCI_CFG_BIST 0xf
8620 +#define PCI_CFG_BAR0 0x10
8621 +#define PCI_CFG_BAR1 0x14
8622 +#define PCI_CFG_BAR2 0x18
8623 +#define PCI_CFG_BAR3 0x1c
8624 +#define PCI_CFG_BAR4 0x20
8625 +#define PCI_CFG_BAR5 0x24
8626 +#define PCI_CFG_CIS 0x28
8627 +#define PCI_CFG_SVID 0x2c
8628 +#define PCI_CFG_SSID 0x2e
8629 +#define PCI_CFG_ROMBAR 0x30
8630 +#define PCI_CFG_CAPPTR 0x34
8631 +#define PCI_CFG_INT 0x3c
8632 +#define PCI_CFG_PIN 0x3d
8633 +#define PCI_CFG_MINGNT 0x3e
8634 +#define PCI_CFG_MAXLAT 0x3f
8635 +
8636 +/* Classes and subclasses */
8637 +
8638 +typedef enum {
8639 + PCI_CLASS_OLD = 0,
8640 + PCI_CLASS_DASDI,
8641 + PCI_CLASS_NET,
8642 + PCI_CLASS_DISPLAY,
8643 + PCI_CLASS_MMEDIA,
8644 + PCI_CLASS_MEMORY,
8645 + PCI_CLASS_BRIDGE,
8646 + PCI_CLASS_COMM,
8647 + PCI_CLASS_BASE,
8648 + PCI_CLASS_INPUT,
8649 + PCI_CLASS_DOCK,
8650 + PCI_CLASS_CPU,
8651 + PCI_CLASS_SERIAL,
8652 + PCI_CLASS_INTELLIGENT = 0xe,
8653 + PCI_CLASS_SATELLITE,
8654 + PCI_CLASS_CRYPT,
8655 + PCI_CLASS_DSP,
8656 + PCI_CLASS_MAX
8657 +} pci_classes;
8658 +
8659 +typedef enum {
8660 + PCI_DASDI_SCSI,
8661 + PCI_DASDI_IDE,
8662 + PCI_DASDI_FLOPPY,
8663 + PCI_DASDI_IPI,
8664 + PCI_DASDI_RAID,
8665 + PCI_DASDI_OTHER = 0x80
8666 +} pci_dasdi_subclasses;
8667 +
8668 +typedef enum {
8669 + PCI_NET_ETHER,
8670 + PCI_NET_TOKEN,
8671 + PCI_NET_FDDI,
8672 + PCI_NET_ATM,
8673 + PCI_NET_OTHER = 0x80
8674 +} pci_net_subclasses;
8675 +
8676 +typedef enum {
8677 + PCI_DISPLAY_VGA,
8678 + PCI_DISPLAY_XGA,
8679 + PCI_DISPLAY_3D,
8680 + PCI_DISPLAY_OTHER = 0x80
8681 +} pci_display_subclasses;
8682 +
8683 +typedef enum {
8684 + PCI_MMEDIA_VIDEO,
8685 + PCI_MMEDIA_AUDIO,
8686 + PCI_MMEDIA_PHONE,
8687 + PCI_MEDIA_OTHER = 0x80
8688 +} pci_mmedia_subclasses;
8689 +
8690 +typedef enum {
8691 + PCI_MEMORY_RAM,
8692 + PCI_MEMORY_FLASH,
8693 + PCI_MEMORY_OTHER = 0x80
8694 +} pci_memory_subclasses;
8695 +
8696 +typedef enum {
8697 + PCI_BRIDGE_HOST,
8698 + PCI_BRIDGE_ISA,
8699 + PCI_BRIDGE_EISA,
8700 + PCI_BRIDGE_MC,
8701 + PCI_BRIDGE_PCI,
8702 + PCI_BRIDGE_PCMCIA,
8703 + PCI_BRIDGE_NUBUS,
8704 + PCI_BRIDGE_CARDBUS,
8705 + PCI_BRIDGE_RACEWAY,
8706 + PCI_BRIDGE_OTHER = 0x80
8707 +} pci_bridge_subclasses;
8708 +
8709 +typedef enum {
8710 + PCI_COMM_UART,
8711 + PCI_COMM_PARALLEL,
8712 + PCI_COMM_MULTIUART,
8713 + PCI_COMM_MODEM,
8714 + PCI_COMM_OTHER = 0x80
8715 +} pci_comm_subclasses;
8716 +
8717 +typedef enum {
8718 + PCI_BASE_PIC,
8719 + PCI_BASE_DMA,
8720 + PCI_BASE_TIMER,
8721 + PCI_BASE_RTC,
8722 + PCI_BASE_PCI_HOTPLUG,
8723 + PCI_BASE_OTHER = 0x80
8724 +} pci_base_subclasses;
8725 +
8726 +typedef enum {
8727 + PCI_INPUT_KBD,
8728 + PCI_INPUT_PEN,
8729 + PCI_INPUT_MOUSE,
8730 + PCI_INPUT_SCANNER,
8731 + PCI_INPUT_GAMEPORT,
8732 + PCI_INPUT_OTHER = 0x80
8733 +} pci_input_subclasses;
8734 +
8735 +typedef enum {
8736 + PCI_DOCK_GENERIC,
8737 + PCI_DOCK_OTHER = 0x80
8738 +} pci_dock_subclasses;
8739 +
8740 +typedef enum {
8741 + PCI_CPU_386,
8742 + PCI_CPU_486,
8743 + PCI_CPU_PENTIUM,
8744 + PCI_CPU_ALPHA = 0x10,
8745 + PCI_CPU_POWERPC = 0x20,
8746 + PCI_CPU_MIPS = 0x30,
8747 + PCI_CPU_COPROC = 0x40,
8748 + PCI_CPU_OTHER = 0x80
8749 +} pci_cpu_subclasses;
8750 +
8751 +typedef enum {
8752 + PCI_SERIAL_IEEE1394,
8753 + PCI_SERIAL_ACCESS,
8754 + PCI_SERIAL_SSA,
8755 + PCI_SERIAL_USB,
8756 + PCI_SERIAL_FIBER,
8757 + PCI_SERIAL_SMBUS,
8758 + PCI_SERIAL_OTHER = 0x80
8759 +} pci_serial_subclasses;
8760 +
8761 +typedef enum {
8762 + PCI_INTELLIGENT_I2O,
8763 +} pci_intelligent_subclasses;
8764 +
8765 +typedef enum {
8766 + PCI_SATELLITE_TV,
8767 + PCI_SATELLITE_AUDIO,
8768 + PCI_SATELLITE_VOICE,
8769 + PCI_SATELLITE_DATA,
8770 + PCI_SATELLITE_OTHER = 0x80
8771 +} pci_satellite_subclasses;
8772 +
8773 +typedef enum {
8774 + PCI_CRYPT_NETWORK,
8775 + PCI_CRYPT_ENTERTAINMENT,
8776 + PCI_CRYPT_OTHER = 0x80
8777 +} pci_crypt_subclasses;
8778 +
8779 +typedef enum {
8780 + PCI_DSP_DPIO,
8781 + PCI_DSP_OTHER = 0x80
8782 +} pci_dsp_subclasses;
8783 +
8784 +/* Header types */
8785 +typedef enum {
8786 + PCI_HEADER_NORMAL,
8787 + PCI_HEADER_BRIDGE,
8788 + PCI_HEADER_CARDBUS
8789 +} pci_header_types;
8790 +
8791 +
8792 +/* Overlay for a PCI-to-PCI bridge */
8793 +
8794 +#define PPB_RSVDA_MAX 2
8795 +#define PPB_RSVDD_MAX 8
8796 +
8797 +typedef struct _ppb_config_regs {
8798 + unsigned short vendor;
8799 + unsigned short device;
8800 + unsigned short command;
8801 + unsigned short status;
8802 + unsigned char rev_id;
8803 + unsigned char prog_if;
8804 + unsigned char sub_class;
8805 + unsigned char base_class;
8806 + unsigned char cache_line_size;
8807 + unsigned char latency_timer;
8808 + unsigned char header_type;
8809 + unsigned char bist;
8810 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8811 + unsigned char prim_bus;
8812 + unsigned char sec_bus;
8813 + unsigned char sub_bus;
8814 + unsigned char sec_lat;
8815 + unsigned char io_base;
8816 + unsigned char io_lim;
8817 + unsigned short sec_status;
8818 + unsigned short mem_base;
8819 + unsigned short mem_lim;
8820 + unsigned short pf_mem_base;
8821 + unsigned short pf_mem_lim;
8822 + unsigned long pf_mem_base_hi;
8823 + unsigned long pf_mem_lim_hi;
8824 + unsigned short io_base_hi;
8825 + unsigned short io_lim_hi;
8826 + unsigned short subsys_vendor;
8827 + unsigned short subsys_id;
8828 + unsigned long rsvd_b;
8829 + unsigned char rsvd_c;
8830 + unsigned char int_pin;
8831 + unsigned short bridge_ctrl;
8832 + unsigned char chip_ctrl;
8833 + unsigned char diag_ctrl;
8834 + unsigned short arb_ctrl;
8835 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8836 + unsigned char dev_dep[192];
8837 +} ppb_config_regs;
8838 +
8839 +
8840 +/* PCI CAPABILITY DEFINES */
8841 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8842 +#define PCI_CAP_MSICAP_ID 0x05
8843 +
8844 +/* Data structure to define the Message Signalled Interrupt facility
8845 + * Valid for PCI and PCIE configurations */
8846 +typedef struct _pciconfig_cap_msi {
8847 + unsigned char capID;
8848 + unsigned char nextptr;
8849 + unsigned short msgctrl;
8850 + unsigned int msgaddr;
8851 +} pciconfig_cap_msi;
8852 +
8853 +/* Data structure to define the Power managment facility
8854 + * Valid for PCI and PCIE configurations */
8855 +typedef struct _pciconfig_cap_pwrmgmt {
8856 + unsigned char capID;
8857 + unsigned char nextptr;
8858 + unsigned short pme_cap;
8859 + unsigned short pme_sts_ctrl;
8860 + unsigned char pme_bridge_ext;
8861 + unsigned char data;
8862 +} pciconfig_cap_pwrmgmt;
8863 +
8864 +/* Everything below is BRCM HND proprietary */
8865 +
8866 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8867 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8868 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8869 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8870 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8871 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8872 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8873 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8874 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8875 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8876 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8877 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8878 +
8879 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8880 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8881 +
8882 +/* PCI_INT_STATUS */
8883 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8884 +
8885 +/* PCI_INT_MASK */
8886 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8887 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8888 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8889 +
8890 +/* PCI_SPROM_CONTROL */
8891 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8892 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8893 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8894 +
8895 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8896 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8897 +
8898 +/* PCI_CFG_CMD_STAT */
8899 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8900 +
8901 +#endif
8902 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8903 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8904 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2006-10-15 23:29:14.000000000 +0200
8905 @@ -0,0 +1,145 @@
8906 +/*******************************************************************************
8907 + * $Id$
8908 + * Copyright 2001-2003, Broadcom Corporation
8909 + * All Rights Reserved.
8910 + *
8911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8915 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8916 + ******************************************************************************/
8917 +
8918 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8919 +#define _NET_ETHERNET_H_
8920 +
8921 +#ifndef _TYPEDEFS_H_
8922 +#include "typedefs.h"
8923 +#endif
8924 +
8925 +#if defined(__GNUC__)
8926 +#define PACKED __attribute__((packed))
8927 +#else
8928 +#define PACKED
8929 +#endif
8930 +
8931 +/*
8932 + * The number of bytes in an ethernet (MAC) address.
8933 + */
8934 +#define ETHER_ADDR_LEN 6
8935 +
8936 +/*
8937 + * The number of bytes in the type field.
8938 + */
8939 +#define ETHER_TYPE_LEN 2
8940 +
8941 +/*
8942 + * The number of bytes in the trailing CRC field.
8943 + */
8944 +#define ETHER_CRC_LEN 4
8945 +
8946 +/*
8947 + * The length of the combined header.
8948 + */
8949 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8950 +
8951 +/*
8952 + * The minimum packet length.
8953 + */
8954 +#define ETHER_MIN_LEN 64
8955 +
8956 +/*
8957 + * The minimum packet user data length.
8958 + */
8959 +#define ETHER_MIN_DATA 46
8960 +
8961 +/*
8962 + * The maximum packet length.
8963 + */
8964 +#define ETHER_MAX_LEN 1518
8965 +
8966 +/*
8967 + * The maximum packet user data length.
8968 + */
8969 +#define ETHER_MAX_DATA 1500
8970 +
8971 +/*
8972 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8973 + */
8974 +#define VLAN_TAG 0x8100
8975 +
8976 +/*
8977 + * Located after dest & src address in ether header.
8978 + */
8979 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8980 +
8981 +/*
8982 + * 4 bytes of vlan field info.
8983 + */
8984 +#define VLAN_FIELDS_SIZE 4
8985 +
8986 +/* location of pri bits in 16-bit vlan fields */
8987 +#define VLAN_PRI_SHIFT 13
8988 +
8989 +/* 3 bits of priority */
8990 +#define VLAN_PRI_MASK 7
8991 +
8992 +/* 802.1X ethertype */
8993 +#define ETHER_TYPE_802_1X 0x888e
8994 +
8995 +/*
8996 + * A macro to validate a length with
8997 + */
8998 +#define ETHER_IS_VALID_LEN(foo) \
8999 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
9000 +
9001 +
9002 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
9003 +/*
9004 + * Structure of a 10Mb/s Ethernet header.
9005 + */
9006 +struct ether_header {
9007 + uint8 ether_dhost[ETHER_ADDR_LEN];
9008 + uint8 ether_shost[ETHER_ADDR_LEN];
9009 + uint16 ether_type;
9010 +} PACKED ;
9011 +
9012 +/*
9013 + * Structure of a 48-bit Ethernet address.
9014 + */
9015 +struct ether_addr {
9016 + uint8 octet[ETHER_ADDR_LEN];
9017 +} PACKED ;
9018 +#endif
9019 +
9020 +/*
9021 + * Takes a pointer, returns true if a 48-bit multicast address
9022 + * (including broadcast, since it is all ones)
9023 + */
9024 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
9025 +
9026 +/*
9027 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
9028 + */
9029 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9030 + ((uint8 *)(ea))[1] & \
9031 + ((uint8 *)(ea))[2] & \
9032 + ((uint8 *)(ea))[3] & \
9033 + ((uint8 *)(ea))[4] & \
9034 + ((uint8 *)(ea))[5]) == 0xff)
9035 +
9036 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9037 +
9038 +/*
9039 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9040 + */
9041 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9042 + ((uint8 *)(ea))[1] | \
9043 + ((uint8 *)(ea))[2] | \
9044 + ((uint8 *)(ea))[3] | \
9045 + ((uint8 *)(ea))[4] | \
9046 + ((uint8 *)(ea))[5]) == 0)
9047 +
9048 +#undef PACKED
9049 +
9050 +#endif /* _NET_ETHERNET_H_ */
9051 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
9052 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9053 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2006-10-15 23:29:14.000000000 +0200
9054 @@ -0,0 +1,103 @@
9055 +#ifndef _S5_H_
9056 +#define _S5_H_
9057 +/*
9058 + * Copyright 2003, Broadcom Corporation
9059 + * All Rights Reserved.
9060 + *
9061 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9062 + * and MIPS3301 (R4K) System Address Space
9063 + *
9064 + * This program is free software; you can redistribute it and/or
9065 + * modify it under the terms of the GNU General Public License as
9066 + * published by the Free Software Foundation, located in the file
9067 + * LICENSE.
9068 + *
9069 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9070 + *
9071 + */
9072 +
9073 +/* BCM5365 Address map */
9074 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9075 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9076 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9077 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9078 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9079 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9080 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9081 +
9082 +/* BCM5365 Core register space */
9083 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9084 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9085 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9086 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9087 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9088 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9089 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9090 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9091 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9092 +
9093 +/* COM Ports 1/2 */
9094 +#define BCM5365_UART (BCM5365_REG_UARTS)
9095 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9096 +
9097 +/* Registers common to MIPS33 Core used in 5365 */
9098 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9099 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9100 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9101 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9102 +
9103 +/* Internal Core Sonics Backplane Devices */
9104 +#define INTERNAL_UART_COM1 BCM5365_UART
9105 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9106 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9107 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9108 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9109 +#define SB_REG_USB BCM5365_REG_USB
9110 +#define SB_REG_PCI BCM5365_REG_PCI
9111 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9112 +#define SB_REG_MEMC BCM5365_REG_MEMC
9113 +#define SB_REG_MEMC_OFF 0x6000
9114 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9115 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9116 +
9117 +/*
9118 + * XXX
9119 + * 5365-specific backplane interrupt flag numbers. This should be done
9120 + * dynamically instead.
9121 + */
9122 +#define SBFLAG_PCI 0
9123 +#define SBFLAG_ENET0 1
9124 +#define SBFLAG_ILINE20 2
9125 +#define SBFLAG_CODEC 3
9126 +#define SBFLAG_USB 4
9127 +#define SBFLAG_EXTIF 5
9128 +#define SBFLAG_ENET1 6
9129 +
9130 +/* BCM95365 Local Bus devices */
9131 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9132 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9133 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9134 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9135 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9136 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9137 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9138 +
9139 +/* Write to DLR2416 VFD Display character RAM */
9140 +#define LED_REG(x) \
9141 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9142 +
9143 +#ifdef CONFIG_VSIM
9144 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9145 + } while (0)
9146 +#else
9147 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9148 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9149 + *((int *)0xa0002ff8) = (trval); } while (0)
9150 +#endif
9151 +
9152 +/* BCM9536R Local Bus devices */
9153 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9154 +
9155 +
9156 +
9157 +#endif /*!_S5_H_ */
9158 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9159 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9160 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-15 23:29:14.000000000 +0200
9161 @@ -0,0 +1,440 @@
9162 +/*
9163 + * SiliconBackplane Chipcommon core hardware definitions.
9164 + *
9165 + * The chipcommon core provides chip identification, SB control,
9166 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9167 + * gpio interface, extbus, and support for serial and parallel flashes.
9168 + *
9169 + * $Id$
9170 + * Copyright 2005, Broadcom Corporation
9171 + * All Rights Reserved.
9172 + *
9173 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9174 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9175 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9176 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9177 + *
9178 + */
9179 +
9180 +#ifndef _SBCHIPC_H
9181 +#define _SBCHIPC_H
9182 +
9183 +
9184 +#ifndef _LANGUAGE_ASSEMBLY
9185 +
9186 +/* cpp contortions to concatenate w/arg prescan */
9187 +#ifndef PAD
9188 +#define _PADLINE(line) pad ## line
9189 +#define _XSTR(line) _PADLINE(line)
9190 +#define PAD _XSTR(__LINE__)
9191 +#endif /* PAD */
9192 +
9193 +typedef volatile struct {
9194 + uint32 chipid; /* 0x0 */
9195 + uint32 capabilities;
9196 + uint32 corecontrol; /* corerev >= 1 */
9197 + uint32 bist;
9198 +
9199 + /* OTP */
9200 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9201 + uint32 otpcontrol;
9202 + uint32 otpprog;
9203 + uint32 PAD;
9204 +
9205 + /* Interrupt control */
9206 + uint32 intstatus; /* 0x20 */
9207 + uint32 intmask;
9208 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9209 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9210 +
9211 + /* Jtag Master */
9212 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9213 + uint32 jtagir;
9214 + uint32 jtagdr;
9215 + uint32 jtagctrl;
9216 +
9217 + /* serial flash interface registers */
9218 + uint32 flashcontrol; /* 0x40 */
9219 + uint32 flashaddress;
9220 + uint32 flashdata;
9221 + uint32 PAD[1];
9222 +
9223 + /* Silicon backplane configuration broadcast control */
9224 + uint32 broadcastaddress; /* 0x50 */
9225 + uint32 broadcastdata;
9226 + uint32 PAD[2];
9227 +
9228 + /* gpio - cleared only by power-on-reset */
9229 + uint32 gpioin; /* 0x60 */
9230 + uint32 gpioout;
9231 + uint32 gpioouten;
9232 + uint32 gpiocontrol;
9233 + uint32 gpiointpolarity;
9234 + uint32 gpiointmask;
9235 + uint32 PAD[2];
9236 +
9237 + /* Watchdog timer */
9238 + uint32 watchdog; /* 0x80 */
9239 + uint32 PAD[1];
9240 +
9241 + /*GPIO based LED powersave registers corerev >= 16*/
9242 + uint32 gpiotimerval; /*0x88 */
9243 + uint32 gpiotimeroutmask;
9244 +
9245 + /* clock control */
9246 + uint32 clockcontrol_n; /* 0x90 */
9247 + uint32 clockcontrol_sb; /* aka m0 */
9248 + uint32 clockcontrol_pci; /* aka m1 */
9249 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9250 + uint32 clockcontrol_mips; /* aka m3 */
9251 + uint32 clkdiv; /* corerev >= 3 */
9252 + uint32 PAD[2];
9253 +
9254 + /* pll delay registers (corerev >= 4) */
9255 + uint32 pll_on_delay; /* 0xb0 */
9256 + uint32 fref_sel_delay;
9257 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9258 + uint32 PAD[1];
9259 +
9260 + /* Instaclock registers (corerev >= 10) */
9261 + uint32 system_clk_ctl; /* 0xc0 */
9262 + uint32 clkstatestretch;
9263 + uint32 PAD[14];
9264 +
9265 + /* ExtBus control registers (corerev >= 3) */
9266 + uint32 pcmcia_config; /* 0x100 */
9267 + uint32 pcmcia_memwait;
9268 + uint32 pcmcia_attrwait;
9269 + uint32 pcmcia_iowait;
9270 + uint32 ide_config;
9271 + uint32 ide_memwait;
9272 + uint32 ide_attrwait;
9273 + uint32 ide_iowait;
9274 + uint32 prog_config;
9275 + uint32 prog_waitcount;
9276 + uint32 flash_config;
9277 + uint32 flash_waitcount;
9278 + uint32 PAD[116];
9279 +
9280 + /* uarts */
9281 + uint8 uart0data; /* 0x300 */
9282 + uint8 uart0imr;
9283 + uint8 uart0fcr;
9284 + uint8 uart0lcr;
9285 + uint8 uart0mcr;
9286 + uint8 uart0lsr;
9287 + uint8 uart0msr;
9288 + uint8 uart0scratch;
9289 + uint8 PAD[248]; /* corerev >= 1 */
9290 +
9291 + uint8 uart1data; /* 0x400 */
9292 + uint8 uart1imr;
9293 + uint8 uart1fcr;
9294 + uint8 uart1lcr;
9295 + uint8 uart1mcr;
9296 + uint8 uart1lsr;
9297 + uint8 uart1msr;
9298 + uint8 uart1scratch;
9299 +} chipcregs_t;
9300 +
9301 +#endif /* _LANGUAGE_ASSEMBLY */
9302 +
9303 +#define CC_CHIPID 0
9304 +#define CC_CAPABILITIES 4
9305 +#define CC_JTAGCMD 0x30
9306 +#define CC_JTAGIR 0x34
9307 +#define CC_JTAGDR 0x38
9308 +#define CC_JTAGCTRL 0x3c
9309 +#define CC_WATCHDOG 0x80
9310 +#define CC_CLKC_N 0x90
9311 +#define CC_CLKC_M0 0x94
9312 +#define CC_CLKC_M1 0x98
9313 +#define CC_CLKC_M2 0x9c
9314 +#define CC_CLKC_M3 0xa0
9315 +#define CC_CLKDIV 0xa4
9316 +#define CC_SYS_CLK_CTL 0xc0
9317 +#define CC_OTP 0x800
9318 +
9319 +/* chipid */
9320 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9321 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9322 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9323 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9324 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9325 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9326 +#define CID_CC_SHIFT 24
9327 +
9328 +/* capabilities */
9329 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9330 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9331 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9332 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9333 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9334 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9335 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9336 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9337 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9338 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9339 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9340 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9341 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9342 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9343 +
9344 +/* PLL type */
9345 +#define PLL_NONE 0x00000000
9346 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9347 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9348 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9349 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9350 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9351 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9352 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9353 +
9354 +/* corecontrol */
9355 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9356 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9357 +
9358 +/* Fields in the otpstatus register */
9359 +#define OTPS_PROGFAIL 0x80000000
9360 +#define OTPS_PROTECT 0x00000007
9361 +#define OTPS_HW_PROTECT 0x00000001
9362 +#define OTPS_SW_PROTECT 0x00000002
9363 +#define OTPS_CID_PROTECT 0x00000004
9364 +
9365 +/* Fields in the otpcontrol register */
9366 +#define OTPC_RECWAIT 0xff000000
9367 +#define OTPC_PROGWAIT 0x00ffff00
9368 +#define OTPC_PRW_SHIFT 8
9369 +#define OTPC_MAXFAIL 0x00000038
9370 +#define OTPC_VSEL 0x00000006
9371 +#define OTPC_SELVL 0x00000001
9372 +
9373 +/* Fields in otpprog */
9374 +#define OTPP_COL_MASK 0x000000ff
9375 +#define OTPP_ROW_MASK 0x0000ff00
9376 +#define OTPP_ROW_SHIFT 8
9377 +#define OTPP_READERR 0x10000000
9378 +#define OTPP_VALUE 0x20000000
9379 +#define OTPP_VALUE_SHIFT 29
9380 +#define OTPP_READ 0x40000000
9381 +#define OTPP_START 0x80000000
9382 +#define OTPP_BUSY 0x80000000
9383 +
9384 +/* jtagcmd */
9385 +#define JCMD_START 0x80000000
9386 +#define JCMD_BUSY 0x80000000
9387 +#define JCMD_PAUSE 0x40000000
9388 +#define JCMD0_ACC_MASK 0x0000f000
9389 +#define JCMD0_ACC_IRDR 0x00000000
9390 +#define JCMD0_ACC_DR 0x00001000
9391 +#define JCMD0_ACC_IR 0x00002000
9392 +#define JCMD0_ACC_RESET 0x00003000
9393 +#define JCMD0_ACC_IRPDR 0x00004000
9394 +#define JCMD0_ACC_PDR 0x00005000
9395 +#define JCMD0_IRW_MASK 0x00000f00
9396 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9397 +#define JCMD_ACC_IRDR 0x00000000
9398 +#define JCMD_ACC_DR 0x00010000
9399 +#define JCMD_ACC_IR 0x00020000
9400 +#define JCMD_ACC_RESET 0x00030000
9401 +#define JCMD_ACC_IRPDR 0x00040000
9402 +#define JCMD_ACC_PDR 0x00050000
9403 +#define JCMD_IRW_MASK 0x00001f00
9404 +#define JCMD_IRW_SHIFT 8
9405 +#define JCMD_DRW_MASK 0x0000003f
9406 +
9407 +/* jtagctrl */
9408 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9409 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9410 +#define JCTRL_EN 1 /* Enable Jtag master */
9411 +
9412 +/* Fields in clkdiv */
9413 +#define CLKD_SFLASH 0x0f000000
9414 +#define CLKD_SFLASH_SHIFT 24
9415 +#define CLKD_OTP 0x000f0000
9416 +#define CLKD_OTP_SHIFT 16
9417 +#define CLKD_JTAG 0x00000f00
9418 +#define CLKD_JTAG_SHIFT 8
9419 +#define CLKD_UART 0x000000ff
9420 +
9421 +/* intstatus/intmask */
9422 +#define CI_GPIO 0x00000001 /* gpio intr */
9423 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9424 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9425 +
9426 +/* slow_clk_ctl */
9427 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9428 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9429 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9430 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9431 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9432 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9433 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9434 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9435 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9436 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9437 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9438 +#define SCC_CD_SHIFT 16
9439 +
9440 +/* system_clk_ctl */
9441 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9442 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9443 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9444 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9445 +#define SYCC_HR 0x00000010 /* Force HT */
9446 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9447 +#define SYCC_CD_SHIFT 16
9448 +
9449 +/* gpiotimerval*/
9450 +#define GPIO_ONTIME_SHIFT 16
9451 +
9452 +/* clockcontrol_n */
9453 +#define CN_N1_MASK 0x3f /* n1 control */
9454 +#define CN_N2_MASK 0x3f00 /* n2 control */
9455 +#define CN_N2_SHIFT 8
9456 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9457 +#define CN_PLLC_SHIFT 16
9458 +
9459 +/* clockcontrol_sb/pci/uart */
9460 +#define CC_M1_MASK 0x3f /* m1 control */
9461 +#define CC_M2_MASK 0x3f00 /* m2 control */
9462 +#define CC_M2_SHIFT 8
9463 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9464 +#define CC_M3_SHIFT 16
9465 +#define CC_MC_MASK 0x1f000000 /* mux control */
9466 +#define CC_MC_SHIFT 24
9467 +
9468 +/* N3M Clock control magic field values */
9469 +#define CC_F6_2 0x02 /* A factor of 2 in */
9470 +#define CC_F6_3 0x03 /* 6-bit fields like */
9471 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9472 +#define CC_F6_5 0x09
9473 +#define CC_F6_6 0x11
9474 +#define CC_F6_7 0x21
9475 +
9476 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9477 +
9478 +#define CC_MC_BYPASS 0x08
9479 +#define CC_MC_M1 0x04
9480 +#define CC_MC_M1M2 0x02
9481 +#define CC_MC_M1M2M3 0x01
9482 +#define CC_MC_M1M3 0x11
9483 +
9484 +/* Type 2 Clock control magic field values */
9485 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9486 +#define CC_T2M2_BIAS 3 /* m2 bias */
9487 +
9488 +#define CC_T2MC_M1BYP 1
9489 +#define CC_T2MC_M2BYP 2
9490 +#define CC_T2MC_M3BYP 4
9491 +
9492 +/* Type 6 Clock control magic field values */
9493 +#define CC_T6_MMASK 1 /* bits of interest in m */
9494 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9495 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9496 +#define SB2MIPS_T6(sb) (2 * (sb))
9497 +
9498 +/* Common clock base */
9499 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9500 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9501 +
9502 +/* Clock control values for 200Mhz in 5350 */
9503 +#define CLKC_5350_N 0x0311
9504 +#define CLKC_5350_M 0x04020009
9505 +
9506 +/* Flash types in the chipcommon capabilities register */
9507 +#define FLASH_NONE 0x000 /* No flash */
9508 +#define SFLASH_ST 0x100 /* ST serial flash */
9509 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9510 +#define PFLASH 0x700 /* Parallel flash */
9511 +
9512 +/* Bits in the config registers */
9513 +#define CC_CFG_EN 0x0001 /* Enable */
9514 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9515 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9516 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9517 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9518 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9519 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9520 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9521 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9522 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9523 +
9524 +/* Start/busy bit in flashcontrol */
9525 +#define SFLASH_START 0x80000000
9526 +#define SFLASH_BUSY SFLASH_START
9527 +
9528 +/* flashcontrol opcodes for ST flashes */
9529 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9530 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9531 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9532 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9533 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9534 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9535 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9536 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9537 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9538 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9539 +
9540 +/* Status register bits for ST flashes */
9541 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9542 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9543 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9544 +#define SFLASH_ST_BP_SHIFT 2
9545 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9546 +
9547 +/* flashcontrol opcodes for Atmel flashes */
9548 +#define SFLASH_AT_READ 0x07e8
9549 +#define SFLASH_AT_PAGE_READ 0x07d2
9550 +#define SFLASH_AT_BUF1_READ
9551 +#define SFLASH_AT_BUF2_READ
9552 +#define SFLASH_AT_STATUS 0x01d7
9553 +#define SFLASH_AT_BUF1_WRITE 0x0384
9554 +#define SFLASH_AT_BUF2_WRITE 0x0387
9555 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9556 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9557 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9558 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9559 +#define SFLASH_AT_PAGE_ERASE 0x0281
9560 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9561 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9562 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9563 +#define SFLASH_AT_BUF1_LOAD 0x0253
9564 +#define SFLASH_AT_BUF2_LOAD 0x0255
9565 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9566 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9567 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9568 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9569 +
9570 +/* Status register bits for Atmel flashes */
9571 +#define SFLASH_AT_READY 0x80
9572 +#define SFLASH_AT_MISMATCH 0x40
9573 +#define SFLASH_AT_ID_MASK 0x38
9574 +#define SFLASH_AT_ID_SHIFT 3
9575 +
9576 +/* OTP regions */
9577 +#define OTP_HW_REGION OTPS_HW_PROTECT
9578 +#define OTP_SW_REGION OTPS_SW_PROTECT
9579 +#define OTP_CID_REGION OTPS_CID_PROTECT
9580 +
9581 +/* OTP regions (Byte offsets from otp size) */
9582 +#define OTP_SWLIM_OFF (-8)
9583 +#define OTP_CIDBASE_OFF 0
9584 +#define OTP_CIDLIM_OFF 8
9585 +
9586 +/* Predefined OTP words (Word offset from otp size) */
9587 +#define OTP_BOUNDARY_OFF (-4)
9588 +#define OTP_HWSIGN_OFF (-3)
9589 +#define OTP_SWSIGN_OFF (-2)
9590 +#define OTP_CIDSIGN_OFF (-1)
9591 +
9592 +#define OTP_CID_OFF 0
9593 +#define OTP_PKG_OFF 1
9594 +#define OTP_FID_OFF 2
9595 +#define OTP_RSV_OFF 3
9596 +#define OTP_LIM_OFF 4
9597 +
9598 +#define OTP_SIGNATURE 0x578a
9599 +#define OTP_MAGIC 0x4e56
9600 +
9601 +#endif /* _SBCHIPC_H */
9602 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9603 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9604 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-15 23:29:14.000000000 +0200
9605 @@ -0,0 +1,342 @@
9606 +/*
9607 + * Broadcom SiliconBackplane hardware register definitions.
9608 + *
9609 + * Copyright 2005, Broadcom Corporation
9610 + * All Rights Reserved.
9611 + *
9612 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9613 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9614 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9615 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9616 + * $Id$
9617 + */
9618 +
9619 +#ifndef _SBCONFIG_H
9620 +#define _SBCONFIG_H
9621 +
9622 +/* cpp contortions to concatenate w/arg prescan */
9623 +#ifndef PAD
9624 +#define _PADLINE(line) pad ## line
9625 +#define _XSTR(line) _PADLINE(line)
9626 +#define PAD _XSTR(__LINE__)
9627 +#endif
9628 +
9629 +/*
9630 + * SiliconBackplane Address Map.
9631 + * All regions may not exist on all chips.
9632 + */
9633 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9634 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9635 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9636 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9637 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9638 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9639 +
9640 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9641 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9642 +
9643 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9644 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9645 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9646 +
9647 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9648 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9649 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9650 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9651 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9652 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9653 +
9654 +
9655 +/* enumeration space related defs */
9656 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9657 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9658 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9659 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9660 +
9661 +/* mips address */
9662 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9663 +
9664 +/*
9665 + * Sonics Configuration Space Registers.
9666 + */
9667 +#define SBIPSFLAG 0x08
9668 +#define SBTPSFLAG 0x18
9669 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9670 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9671 +#define SBADMATCH3 0x60
9672 +#define SBADMATCH2 0x68
9673 +#define SBADMATCH1 0x70
9674 +#define SBIMSTATE 0x90
9675 +#define SBINTVEC 0x94
9676 +#define SBTMSTATELOW 0x98
9677 +#define SBTMSTATEHIGH 0x9c
9678 +#define SBBWA0 0xa0
9679 +#define SBIMCONFIGLOW 0xa8
9680 +#define SBIMCONFIGHIGH 0xac
9681 +#define SBADMATCH0 0xb0
9682 +#define SBTMCONFIGLOW 0xb8
9683 +#define SBTMCONFIGHIGH 0xbc
9684 +#define SBBCONFIG 0xc0
9685 +#define SBBSTATE 0xc8
9686 +#define SBACTCNFG 0xd8
9687 +#define SBFLAGST 0xe8
9688 +#define SBIDLOW 0xf8
9689 +#define SBIDHIGH 0xfc
9690 +
9691 +#ifndef _LANGUAGE_ASSEMBLY
9692 +
9693 +typedef volatile struct _sbconfig {
9694 + uint32 PAD[2];
9695 + uint32 sbipsflag; /* initiator port ocp slave flag */
9696 + uint32 PAD[3];
9697 + uint32 sbtpsflag; /* target port ocp slave flag */
9698 + uint32 PAD[11];
9699 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9700 + uint32 PAD;
9701 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9702 + uint32 PAD[3];
9703 + uint32 sbadmatch3; /* address match3 */
9704 + uint32 PAD;
9705 + uint32 sbadmatch2; /* address match2 */
9706 + uint32 PAD;
9707 + uint32 sbadmatch1; /* address match1 */
9708 + uint32 PAD[7];
9709 + uint32 sbimstate; /* initiator agent state */
9710 + uint32 sbintvec; /* interrupt mask */
9711 + uint32 sbtmstatelow; /* target state */
9712 + uint32 sbtmstatehigh; /* target state */
9713 + uint32 sbbwa0; /* bandwidth allocation table0 */
9714 + uint32 PAD;
9715 + uint32 sbimconfiglow; /* initiator configuration */
9716 + uint32 sbimconfighigh; /* initiator configuration */
9717 + uint32 sbadmatch0; /* address match0 */
9718 + uint32 PAD;
9719 + uint32 sbtmconfiglow; /* target configuration */
9720 + uint32 sbtmconfighigh; /* target configuration */
9721 + uint32 sbbconfig; /* broadcast configuration */
9722 + uint32 PAD;
9723 + uint32 sbbstate; /* broadcast state */
9724 + uint32 PAD[3];
9725 + uint32 sbactcnfg; /* activate configuration */
9726 + uint32 PAD[3];
9727 + uint32 sbflagst; /* current sbflags */
9728 + uint32 PAD[3];
9729 + uint32 sbidlow; /* identification */
9730 + uint32 sbidhigh; /* identification */
9731 +} sbconfig_t;
9732 +
9733 +#endif /* _LANGUAGE_ASSEMBLY */
9734 +
9735 +/* sbipsflag */
9736 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9737 +#define SBIPS_INT1_SHIFT 0
9738 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9739 +#define SBIPS_INT2_SHIFT 8
9740 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9741 +#define SBIPS_INT3_SHIFT 16
9742 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9743 +#define SBIPS_INT4_SHIFT 24
9744 +
9745 +/* sbtpsflag */
9746 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9747 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9748 +
9749 +/* sbtmerrlog */
9750 +#define SBTMEL_CM 0x00000007 /* command */
9751 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9752 +#define SBTMEL_EC 0x0f000000 /* error code */
9753 +#define SBTMEL_ME 0x80000000 /* multiple error */
9754 +
9755 +/* sbimstate */
9756 +#define SBIM_PC 0xf /* pipecount */
9757 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9758 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9759 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9760 +#define SBIM_AP_TK 0x20 /* use token only */
9761 +#define SBIM_AP_RSV 0x30 /* reserved */
9762 +#define SBIM_IBE 0x20000 /* inbanderror */
9763 +#define SBIM_TO 0x40000 /* timeout */
9764 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9765 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9766 +
9767 +/* sbtmstatelow */
9768 +#define SBTML_RESET 0x1 /* reset */
9769 +#define SBTML_REJ_MASK 0x6 /* reject */
9770 +#define SBTML_REJ_SHIFT 1
9771 +#define SBTML_CLK 0x10000 /* clock enable */
9772 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9773 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9774 +#define SBTML_PE 0x40000000 /* pme enable */
9775 +#define SBTML_BE 0x80000000 /* bist enable */
9776 +
9777 +/* sbtmstatehigh */
9778 +#define SBTMH_SERR 0x1 /* serror */
9779 +#define SBTMH_INT 0x2 /* interrupt */
9780 +#define SBTMH_BUSY 0x4 /* busy */
9781 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9782 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9783 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9784 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9785 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9786 +#define SBTMH_BISTD 0x80000000 /* bist done */
9787 +
9788 +
9789 +/* sbbwa0 */
9790 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9791 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9792 +#define SBBWA_TAB1_SHIFT 16
9793 +
9794 +/* sbimconfiglow */
9795 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9796 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9797 +#define SBIMCL_RTO_SHIFT 4
9798 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9799 +#define SBIMCL_CID_SHIFT 16
9800 +
9801 +/* sbimconfighigh */
9802 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9803 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9804 +#define SBIMCH_TEM_SHIFT 4
9805 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9806 +#define SBIMCH_BEM_SHIFT 6
9807 +
9808 +/* sbadmatch0 */
9809 +#define SBAM_TYPE_MASK 0x3 /* address type */
9810 +#define SBAM_AD64 0x4 /* reserved */
9811 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9812 +#define SBAM_ADINT0_SHIFT 3
9813 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9814 +#define SBAM_ADINT1_SHIFT 3
9815 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9816 +#define SBAM_ADINT2_SHIFT 3
9817 +#define SBAM_ADEN 0x400 /* enable */
9818 +#define SBAM_ADNEG 0x800 /* negative decode */
9819 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9820 +#define SBAM_BASE0_SHIFT 8
9821 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9822 +#define SBAM_BASE1_SHIFT 12
9823 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9824 +#define SBAM_BASE2_SHIFT 16
9825 +
9826 +/* sbtmconfiglow */
9827 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9828 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9829 +#define SBTMCL_CO_SHIFT 11
9830 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9831 +#define SBTMCL_IF_SHIFT 18
9832 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9833 +#define SBTMCL_IM_SHIFT 24
9834 +
9835 +/* sbtmconfighigh */
9836 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9837 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9838 +#define SBTMCH_RM_SHIFT 2
9839 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9840 +#define SBTMCH_SM_SHIFT 4
9841 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9842 +#define SBTMCH_EM_SHIFT 8
9843 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9844 +#define SBTMCH_IM_SHIFT 10
9845 +
9846 +/* sbbconfig */
9847 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9848 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9849 +#define SBBC_MAX0_SHIFT 16
9850 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9851 +#define SBBC_MAX1_SHIFT 20
9852 +
9853 +/* sbbstate */
9854 +#define SBBS_SRD 0x1 /* st reg disable */
9855 +#define SBBS_HRD 0x2 /* hold reg disable */
9856 +
9857 +/* sbidlow */
9858 +#define SBIDL_CS_MASK 0x3 /* config space */
9859 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9860 +#define SBIDL_AR_SHIFT 3
9861 +#define SBIDL_SYNCH 0x40 /* sync */
9862 +#define SBIDL_INIT 0x80 /* initiator */
9863 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9864 +#define SBIDL_MINLAT_SHIFT 8
9865 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9866 +#define SBIDL_MAXLAT_SHIFT 12
9867 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9868 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9869 +#define SBIDL_CW_SHIFT 18
9870 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9871 +#define SBIDL_TP_SHIFT 20
9872 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9873 +#define SBIDL_IP_SHIFT 24
9874 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9875 +#define SBIDL_RV_SHIFT 28
9876 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9877 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9878 +
9879 +/* sbidhigh */
9880 +#define SBIDH_RC_MASK 0x000f /* revision code */
9881 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9882 +#define SBIDH_RCE_SHIFT 8
9883 +#define SBCOREREV(sbidh) \
9884 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9885 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9886 +#define SBIDH_CC_SHIFT 4
9887 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9888 +#define SBIDH_VC_SHIFT 16
9889 +
9890 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9891 +
9892 +/* vendor codes */
9893 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9894 +
9895 +/* core codes */
9896 +#define SB_CC 0x800 /* chipcommon core */
9897 +#define SB_ILINE20 0x801 /* iline20 core */
9898 +#define SB_SDRAM 0x803 /* sdram core */
9899 +#define SB_PCI 0x804 /* pci core */
9900 +#define SB_MIPS 0x805 /* mips core */
9901 +#define SB_ENET 0x806 /* enet mac core */
9902 +#define SB_CODEC 0x807 /* v90 codec core */
9903 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9904 +#define SB_ADSL 0x809 /* ADSL core */
9905 +#define SB_ILINE100 0x80a /* iline100 core */
9906 +#define SB_IPSEC 0x80b /* ipsec core */
9907 +#define SB_PCMCIA 0x80d /* pcmcia core */
9908 +#define SB_SOCRAM 0x80e /* internal memory core */
9909 +#define SB_MEMC 0x80f /* memc sdram core */
9910 +#define SB_EXTIF 0x811 /* external interface core */
9911 +#define SB_D11 0x812 /* 802.11 MAC core */
9912 +#define SB_MIPS33 0x816 /* mips3302 core */
9913 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9914 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9915 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9916 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9917 +#define SB_SDIOH 0x81b /* sdio host core */
9918 +#define SB_ROBO 0x81c /* roboswitch core */
9919 +#define SB_ATA100 0x81d /* parallel ATA core */
9920 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9921 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9922 +#define SB_PCIE 0x820 /* pci express core */
9923 +#define SB_SRAMC 0x822 /* SRAM controller core */
9924 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9925 +
9926 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9927 +
9928 +/* Not really related to Silicon Backplane, but a couple of software
9929 + * conventions for the use the flash space:
9930 + */
9931 +
9932 +/* Minumum amount of flash we support */
9933 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9934 +
9935 +/* A boot/binary may have an embedded block that describes its size */
9936 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9937 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9938 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9939 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9940 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9941 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9942 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9943 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9944 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9945 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9946 +
9947 +#endif /* _SBCONFIG_H */
9948 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9949 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9950 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-15 23:29:14.000000000 +0200
9951 @@ -0,0 +1,242 @@
9952 +/*
9953 + * Hardware-specific External Interface I/O core definitions
9954 + * for the BCM47xx family of SiliconBackplane-based chips.
9955 + *
9956 + * The External Interface core supports a total of three external chip selects
9957 + * supporting external interfaces. One of the external chip selects is
9958 + * used for Flash, one is used for PCMCIA, and the other may be
9959 + * programmed to support either a synchronous interface or an
9960 + * asynchronous interface. The asynchronous interface can be used to
9961 + * support external devices such as UARTs and the BCM2019 Bluetooth
9962 + * baseband processor.
9963 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9964 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9965 + *
9966 + * Copyright 2005, Broadcom Corporation
9967 + * All Rights Reserved.
9968 + *
9969 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9970 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9971 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9972 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9973 + * $Id$
9974 + */
9975 +
9976 +#ifndef _SBEXTIF_H
9977 +#define _SBEXTIF_H
9978 +
9979 +/* external interface address space */
9980 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9981 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9982 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9983 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9984 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9985 +
9986 +/* cpp contortions to concatenate w/arg prescan */
9987 +#ifndef PAD
9988 +#define _PADLINE(line) pad ## line
9989 +#define _XSTR(line) _PADLINE(line)
9990 +#define PAD _XSTR(__LINE__)
9991 +#endif /* PAD */
9992 +
9993 +/*
9994 + * The multiple instances of output and output enable registers
9995 + * are present to allow driver software for multiple cores to control
9996 + * gpio outputs without needing to share a single register pair.
9997 + */
9998 +struct gpiouser {
9999 + uint32 out;
10000 + uint32 outen;
10001 +};
10002 +#define NGPIOUSER 5
10003 +
10004 +typedef volatile struct {
10005 + uint32 corecontrol;
10006 + uint32 extstatus;
10007 + uint32 PAD[2];
10008 +
10009 + /* pcmcia control registers */
10010 + uint32 pcmcia_config;
10011 + uint32 pcmcia_memwait;
10012 + uint32 pcmcia_attrwait;
10013 + uint32 pcmcia_iowait;
10014 +
10015 + /* programmable interface control registers */
10016 + uint32 prog_config;
10017 + uint32 prog_waitcount;
10018 +
10019 + /* flash control registers */
10020 + uint32 flash_config;
10021 + uint32 flash_waitcount;
10022 + uint32 PAD[4];
10023 +
10024 + uint32 watchdog;
10025 +
10026 + /* clock control */
10027 + uint32 clockcontrol_n;
10028 + uint32 clockcontrol_sb;
10029 + uint32 clockcontrol_pci;
10030 + uint32 clockcontrol_mii;
10031 + uint32 PAD[3];
10032 +
10033 + /* gpio */
10034 + uint32 gpioin;
10035 + struct gpiouser gpio[NGPIOUSER];
10036 + uint32 PAD;
10037 + uint32 ejtagouten;
10038 + uint32 gpiointpolarity;
10039 + uint32 gpiointmask;
10040 + uint32 PAD[153];
10041 +
10042 + uint8 uartdata;
10043 + uint8 PAD[3];
10044 + uint8 uartimer;
10045 + uint8 PAD[3];
10046 + uint8 uartfcr;
10047 + uint8 PAD[3];
10048 + uint8 uartlcr;
10049 + uint8 PAD[3];
10050 + uint8 uartmcr;
10051 + uint8 PAD[3];
10052 + uint8 uartlsr;
10053 + uint8 PAD[3];
10054 + uint8 uartmsr;
10055 + uint8 PAD[3];
10056 + uint8 uartscratch;
10057 + uint8 PAD[3];
10058 +} extifregs_t;
10059 +
10060 +/* corecontrol */
10061 +#define CC_UE (1 << 0) /* uart enable */
10062 +
10063 +/* extstatus */
10064 +#define ES_EM (1 << 0) /* endian mode (ro) */
10065 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10066 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10067 +
10068 +/* gpio bit mask */
10069 +#define GPIO_BIT0 (1 << 0)
10070 +#define GPIO_BIT1 (1 << 1)
10071 +#define GPIO_BIT2 (1 << 2)
10072 +#define GPIO_BIT3 (1 << 3)
10073 +#define GPIO_BIT4 (1 << 4)
10074 +#define GPIO_BIT5 (1 << 5)
10075 +#define GPIO_BIT6 (1 << 6)
10076 +#define GPIO_BIT7 (1 << 7)
10077 +
10078 +
10079 +/* pcmcia/prog/flash_config */
10080 +#define CF_EN (1 << 0) /* enable */
10081 +#define CF_EM_MASK 0xe /* mode */
10082 +#define CF_EM_SHIFT 1
10083 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10084 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10085 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10086 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10087 +#define CF_BS (1 << 5) /* byteswap */
10088 +#define CF_CD_MASK 0xc0 /* clock divider */
10089 +#define CF_CD_SHIFT 6
10090 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10091 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10092 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10093 +#define CF_CE (1 << 8) /* clock enable */
10094 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10095 +
10096 +/* pcmcia_memwait */
10097 +#define PM_W0_MASK 0x3f /* waitcount0 */
10098 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10099 +#define PM_W1_SHIFT 8
10100 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10101 +#define PM_W2_SHIFT 16
10102 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10103 +#define PM_W3_SHIFT 24
10104 +
10105 +/* pcmcia_attrwait */
10106 +#define PA_W0_MASK 0x3f /* waitcount0 */
10107 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10108 +#define PA_W1_SHIFT 8
10109 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10110 +#define PA_W2_SHIFT 16
10111 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10112 +#define PA_W3_SHIFT 24
10113 +
10114 +/* pcmcia_iowait */
10115 +#define PI_W0_MASK 0x3f /* waitcount0 */
10116 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10117 +#define PI_W1_SHIFT 8
10118 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10119 +#define PI_W2_SHIFT 16
10120 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10121 +#define PI_W3_SHIFT 24
10122 +
10123 +/* prog_waitcount */
10124 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10125 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10126 +#define PW_W1_SHIFT 8
10127 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10128 +#define PW_W2_SHIFT 16
10129 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10130 +#define PW_W3_SHIFT 24
10131 +
10132 +#define PW_W0 0x0000000c
10133 +#define PW_W1 0x00000a00
10134 +#define PW_W2 0x00020000
10135 +#define PW_W3 0x01000000
10136 +
10137 +/* flash_waitcount */
10138 +#define FW_W0_MASK 0x1f /* waitcount0 */
10139 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10140 +#define FW_W1_SHIFT 8
10141 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10142 +#define FW_W2_SHIFT 16
10143 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10144 +#define FW_W3_SHIFT 24
10145 +
10146 +/* watchdog */
10147 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10148 +
10149 +/* clockcontrol_n */
10150 +#define CN_N1_MASK 0x3f /* n1 control */
10151 +#define CN_N2_MASK 0x3f00 /* n2 control */
10152 +#define CN_N2_SHIFT 8
10153 +
10154 +/* clockcontrol_sb/pci/mii */
10155 +#define CC_M1_MASK 0x3f /* m1 control */
10156 +#define CC_M2_MASK 0x3f00 /* m2 control */
10157 +#define CC_M2_SHIFT 8
10158 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10159 +#define CC_M3_SHIFT 16
10160 +#define CC_MC_MASK 0x1f000000 /* mux control */
10161 +#define CC_MC_SHIFT 24
10162 +
10163 +/* Clock control default values */
10164 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10165 +#define CC_DEF_100 0x04020011
10166 +#define CC_DEF_33 0x11030011
10167 +#define CC_DEF_25 0x11050011
10168 +
10169 +/* Clock control values for 125Mhz */
10170 +#define CC_125_N 0x0802
10171 +#define CC_125_M 0x04020009
10172 +#define CC_125_M25 0x11090009
10173 +#define CC_125_M33 0x11090005
10174 +
10175 +/* Clock control magic field values */
10176 +#define CC_F6_2 0x02 /* A factor of 2 in */
10177 +#define CC_F6_3 0x03 /* 6-bit fields like */
10178 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10179 +#define CC_F6_5 0x09
10180 +#define CC_F6_6 0x11
10181 +#define CC_F6_7 0x21
10182 +
10183 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10184 +
10185 +#define CC_MC_BYPASS 0x08
10186 +#define CC_MC_M1 0x04
10187 +#define CC_MC_M1M2 0x02
10188 +#define CC_MC_M1M2M3 0x01
10189 +#define CC_MC_M1M3 0x11
10190 +
10191 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10192 +
10193 +#endif /* _SBEXTIF_H */
10194 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10195 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10196 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-15 23:29:14.000000000 +0200
10197 @@ -0,0 +1,148 @@
10198 +/*
10199 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10200 + *
10201 + * Copyright 2005, Broadcom Corporation
10202 + * All Rights Reserved.
10203 + *
10204 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10205 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10206 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10207 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10208 + *
10209 + * $Id$
10210 + */
10211 +
10212 +#ifndef _SBMEMC_H
10213 +#define _SBMEMC_H
10214 +
10215 +#ifdef _LANGUAGE_ASSEMBLY
10216 +
10217 +#define MEMC_CONTROL 0x00
10218 +#define MEMC_CONFIG 0x04
10219 +#define MEMC_REFRESH 0x08
10220 +#define MEMC_BISTSTAT 0x0c
10221 +#define MEMC_MODEBUF 0x10
10222 +#define MEMC_BKCLS 0x14
10223 +#define MEMC_PRIORINV 0x18
10224 +#define MEMC_DRAMTIM 0x1c
10225 +#define MEMC_INTSTAT 0x20
10226 +#define MEMC_INTMASK 0x24
10227 +#define MEMC_INTINFO 0x28
10228 +#define MEMC_NCDLCTL 0x30
10229 +#define MEMC_RDNCDLCOR 0x34
10230 +#define MEMC_WRNCDLCOR 0x38
10231 +#define MEMC_MISCDLYCTL 0x3c
10232 +#define MEMC_DQSGATENCDL 0x40
10233 +#define MEMC_SPARE 0x44
10234 +#define MEMC_TPADDR 0x48
10235 +#define MEMC_TPDATA 0x4c
10236 +#define MEMC_BARRIER 0x50
10237 +#define MEMC_CORE 0x54
10238 +
10239 +
10240 +#else
10241 +
10242 +/* Sonics side: MEMC core registers */
10243 +typedef volatile struct sbmemcregs {
10244 + uint32 control;
10245 + uint32 config;
10246 + uint32 refresh;
10247 + uint32 biststat;
10248 + uint32 modebuf;
10249 + uint32 bkcls;
10250 + uint32 priorinv;
10251 + uint32 dramtim;
10252 + uint32 intstat;
10253 + uint32 intmask;
10254 + uint32 intinfo;
10255 + uint32 reserved1;
10256 + uint32 ncdlctl;
10257 + uint32 rdncdlcor;
10258 + uint32 wrncdlcor;
10259 + uint32 miscdlyctl;
10260 + uint32 dqsgatencdl;
10261 + uint32 spare;
10262 + uint32 tpaddr;
10263 + uint32 tpdata;
10264 + uint32 barrier;
10265 + uint32 core;
10266 +} sbmemcregs_t;
10267 +
10268 +#endif
10269 +
10270 +/* MEMC Core Init values (OCP ID 0x80f) */
10271 +
10272 +/* For sdr: */
10273 +#define MEMC_SD_CONFIG_INIT 0x00048000
10274 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10275 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10276 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10277 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10278 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10279 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10280 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10281 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10282 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10283 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10284 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10285 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10286 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10287 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10288 +
10289 +
10290 +/* This is for SDRM8X8X4 */
10291 +#define MEMC_SDR_INIT 0x0008
10292 +#define MEMC_SDR_MODE 0x32
10293 +#define MEMC_SDR_NCDL 0x00020032
10294 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10295 +
10296 +/* For ddr: */
10297 +#define MEMC_CONFIG_INIT 0x00048000
10298 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10299 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10300 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10301 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10302 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10303 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10304 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10305 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10306 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10307 +#define MEMC_NCDLCTL_INIT 0x00002001
10308 +#define MEMC_CONTROL_INIT0 0x00000002
10309 +#define MEMC_CONTROL_INIT1 0x00000008
10310 +#define MEMC_MODEBUF_INIT0 0x00004000
10311 +#define MEMC_CONTROL_INIT2 0x00000010
10312 +#define MEMC_MODEBUF_INIT1 0x00000100
10313 +#define MEMC_CONTROL_INIT3 0x00000010
10314 +#define MEMC_CONTROL_INIT4 0x00000008
10315 +#define MEMC_REFRESH_INIT 0x0000840f
10316 +#define MEMC_CONTROL_INIT5 0x00000004
10317 +#define MEMC_MODEBUF_INIT2 0x00000000
10318 +#define MEMC_CONTROL_INIT6 0x00000010
10319 +#define MEMC_CONTROL_INIT7 0x00000001
10320 +
10321 +
10322 +/* This is for DDRM16X16X2 */
10323 +#define MEMC_DDR_INIT 0x0009
10324 +#define MEMC_DDR_MODE 0x62
10325 +#define MEMC_DDR_NCDL 0x0005050a
10326 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10327 +
10328 +/* mask for sdr/ddr calibration registers */
10329 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10330 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10331 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10332 +
10333 +/* masks for miscdlyctl registers */
10334 +#define MEMC_MISC_SM_MASK 0x30000000
10335 +#define MEMC_MISC_SM_SHIFT 28
10336 +#define MEMC_MISC_SD_MASK 0x0f000000
10337 +#define MEMC_MISC_SD_SHIFT 24
10338 +
10339 +/* hw threshhold for calculating wr/rd for sdr memc */
10340 +#define MEMC_CD_THRESHOLD 128
10341 +
10342 +/* Low bit of init register says if memc is ddr or sdr */
10343 +#define MEMC_CONFIG_DDR 0x00000001
10344 +
10345 +#endif /* _SBMEMC_H */
10346 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10347 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10348 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2006-10-15 23:37:15.000000000 +0200
10349 @@ -0,0 +1,63 @@
10350 +/*
10351 + * Broadcom SiliconBackplane MIPS definitions
10352 + *
10353 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10354 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10355 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10356 + * interface. The core revision is stored in the SB ID register in SB
10357 + * configuration space.
10358 + *
10359 + * Copyright 2005, Broadcom Corporation
10360 + * All Rights Reserved.
10361 + *
10362 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10363 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10364 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10365 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10366 + *
10367 + * $Id$
10368 + */
10369 +
10370 +#ifndef _SBMIPS_H
10371 +#define _SBMIPS_H
10372 +
10373 +#include <mipsinc.h>
10374 +
10375 +#ifndef _LANGUAGE_ASSEMBLY
10376 +
10377 +/* cpp contortions to concatenate w/arg prescan */
10378 +#ifndef PAD
10379 +#define _PADLINE(line) pad ## line
10380 +#define _XSTR(line) _PADLINE(line)
10381 +#define PAD _XSTR(__LINE__)
10382 +#endif /* PAD */
10383 +
10384 +typedef volatile struct {
10385 + uint32 corecontrol;
10386 + uint32 PAD[2];
10387 + uint32 biststatus;
10388 + uint32 PAD[4];
10389 + uint32 intstatus;
10390 + uint32 intmask;
10391 + uint32 timer;
10392 +} mipsregs_t;
10393 +
10394 +extern uint32 sb_flag(sb_t *sbh);
10395 +extern uint sb_irq(sb_t *sbh);
10396 +
10397 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10398 +
10399 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10400 +extern void sb_jtagm_disable(void *h);
10401 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10402 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10403 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10404 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10405 +extern void BCMINIT(enable_pfc)(uint32 mode);
10406 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10407 +extern uint32 BCMINIT(sb_cpu_clock)(sb_t *sbh);
10408 +
10409 +
10410 +#endif /* _LANGUAGE_ASSEMBLY */
10411 +
10412 +#endif /* _SBMIPS_H */
10413 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10414 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10415 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-15 23:29:14.000000000 +0200
10416 @@ -0,0 +1,122 @@
10417 +/*
10418 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10419 + *
10420 + * $Id$
10421 + * Copyright 2005, Broadcom Corporation
10422 + * All Rights Reserved.
10423 + *
10424 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10425 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10426 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10427 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10428 + */
10429 +
10430 +#ifndef _SBPCI_H
10431 +#define _SBPCI_H
10432 +
10433 +/* cpp contortions to concatenate w/arg prescan */
10434 +#ifndef PAD
10435 +#define _PADLINE(line) pad ## line
10436 +#define _XSTR(line) _PADLINE(line)
10437 +#define PAD _XSTR(__LINE__)
10438 +#endif
10439 +
10440 +/* Sonics side: PCI core and host control registers */
10441 +typedef struct sbpciregs {
10442 + uint32 control; /* PCI control */
10443 + uint32 PAD[3];
10444 + uint32 arbcontrol; /* PCI arbiter control */
10445 + uint32 PAD[3];
10446 + uint32 intstatus; /* Interrupt status */
10447 + uint32 intmask; /* Interrupt mask */
10448 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10449 + uint32 PAD[9];
10450 + uint32 bcastaddr; /* Sonics broadcast address */
10451 + uint32 bcastdata; /* Sonics broadcast data */
10452 + uint32 PAD[2];
10453 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10454 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10455 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10456 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10457 + uint32 PAD[36];
10458 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10459 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10460 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10461 + uint32 PAD[445];
10462 + uint16 sprom[36]; /* SPROM shadow Area */
10463 + uint32 PAD[46];
10464 +} sbpciregs_t;
10465 +
10466 +/* PCI control */
10467 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10468 +#define PCI_RST 0x02 /* Value driven out to pin */
10469 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10470 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10471 +
10472 +/* PCI arbiter control */
10473 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10474 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10475 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10476 +#define PCI_PARKID_SHIFT 1
10477 +#define PCI_PARKID_LAST 0 /* Last requestor */
10478 +#define PCI_PARKID_4710 1 /* 4710 */
10479 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10480 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10481 +
10482 +/* Interrupt status/mask */
10483 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10484 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10485 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10486 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10487 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10488 +
10489 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10490 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10491 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10492 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10493 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10494 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10495 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10496 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10497 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10498 +
10499 +/* Sonics broadcast address */
10500 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10501 +
10502 +/* Sonics to PCI translation types */
10503 +#define SBTOPCI0_MASK 0xfc000000
10504 +#define SBTOPCI1_MASK 0xfc000000
10505 +#define SBTOPCI2_MASK 0xc0000000
10506 +#define SBTOPCI_MEM 0
10507 +#define SBTOPCI_IO 1
10508 +#define SBTOPCI_CFG0 2
10509 +#define SBTOPCI_CFG1 3
10510 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10511 +#define SBTOPCI_BURST 0x8 /* burst enable */
10512 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10513 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10514 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10515 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10516 +
10517 +/* PCI core index in SROM shadow area */
10518 +#define SRSH_PI_OFFSET 0 /* first word */
10519 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10520 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10521 +
10522 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10523 +#define cap_list rsvd_a[0]
10524 +#define bar0_window dev_dep[0x80 - 0x40]
10525 +#define bar1_window dev_dep[0x84 - 0x40]
10526 +#define sprom_control dev_dep[0x88 - 0x40]
10527 +
10528 +#ifndef _LANGUAGE_ASSEMBLY
10529 +
10530 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10531 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10532 +extern void sbpci_ban(uint16 core);
10533 +extern int sbpci_init(sb_t *sbh);
10534 +extern void sbpci_check(sb_t *sbh);
10535 +
10536 +#endif /* !_LANGUAGE_ASSEMBLY */
10537 +
10538 +#endif /* _SBPCI_H */
10539 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10540 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10541 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-15 23:29:14.000000000 +0200
10542 @@ -0,0 +1,75 @@
10543 +/*
10544 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10545 + *
10546 + * Copyright 2005, Broadcom Corporation
10547 + * All Rights Reserved.
10548 + *
10549 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10550 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10551 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10552 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10553 + * $Id$
10554 + */
10555 +
10556 +#ifndef _SBSDRAM_H
10557 +#define _SBSDRAM_H
10558 +
10559 +#ifndef _LANGUAGE_ASSEMBLY
10560 +
10561 +/* Sonics side: SDRAM core registers */
10562 +typedef volatile struct sbsdramregs {
10563 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10564 + uint32 config; /* Initializes external SDRAM mode register */
10565 + uint32 refresh; /* Controls external SDRAM refresh rate */
10566 + uint32 pad1;
10567 + uint32 pad2;
10568 +} sbsdramregs_t;
10569 +
10570 +#endif
10571 +
10572 +/* SDRAM initialization control (initcontrol) register bits */
10573 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10574 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10575 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10576 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10577 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10578 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10579 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10580 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10581 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10582 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10583 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10584 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10585 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10586 +
10587 +/* SDRAM configuration (config) register bits */
10588 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10589 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10590 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10591 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10592 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10593 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10594 +
10595 +/* SDRAM refresh control (refresh) register bits */
10596 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10597 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10598 +
10599 +/* SDRAM Core default Init values (OCP ID 0x803) */
10600 +#define SDRAM_INIT MEM4MX16X2
10601 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10602 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10603 +
10604 +#define MEM1MX16 0x009 /* 2 MB */
10605 +#define MEM1MX16X2 0x409 /* 4 MB */
10606 +#define MEM2MX8X2 0x809 /* 4 MB */
10607 +#define MEM2MX8X4 0xc09 /* 8 MB */
10608 +#define MEM2MX32 0x439 /* 8 MB */
10609 +#define MEM4MX16 0x019 /* 8 MB */
10610 +#define MEM4MX16X2 0x419 /* 16 MB */
10611 +#define MEM8MX8X2 0x819 /* 16 MB */
10612 +#define MEM8MX16 0x829 /* 16 MB */
10613 +#define MEM4MX32 0x429 /* 16 MB */
10614 +#define MEM8MX8X4 0xc19 /* 32 MB */
10615 +#define MEM8MX16X2 0xc29 /* 32 MB */
10616 +
10617 +#endif /* _SBSDRAM_H */
10618 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10619 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10620 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-15 23:29:14.000000000 +0200
10621 @@ -0,0 +1,136 @@
10622 +/*
10623 + * Misc utility routines for accessing chip-specific features
10624 + * of Broadcom HNBU SiliconBackplane-based chips.
10625 + *
10626 + * Copyright 2005, Broadcom Corporation
10627 + * All Rights Reserved.
10628 + *
10629 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10630 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10631 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10632 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10633 + *
10634 + * $Id$
10635 + */
10636 +
10637 +#ifndef _sbutils_h_
10638 +#define _sbutils_h_
10639 +
10640 +/*
10641 + * Datastructure to export all chip specific common variables
10642 + * public (read-only) portion of sbutils handle returned by
10643 + * sb_attach()/sb_kattach()
10644 +*/
10645 +
10646 +struct sb_pub {
10647 +
10648 + uint bustype; /* SB_BUS, PCI_BUS */
10649 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10650 + uint buscorerev; /* buscore rev */
10651 + uint buscoreidx; /* buscore index */
10652 + int ccrev; /* chip common core rev */
10653 + uint boardtype; /* board type */
10654 + uint boardvendor; /* board vendor */
10655 + uint chip; /* chip number */
10656 + uint chiprev; /* chip revision */
10657 + uint chippkg; /* chip package option */
10658 + uint sonicsrev; /* sonics backplane rev */
10659 +};
10660 +
10661 +typedef const struct sb_pub sb_t;
10662 +
10663 +/*
10664 + * Many of the routines below take an 'sbh' handle as their first arg.
10665 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10666 + * At any one time, the sbh is logically focused on one particular sb core
10667 + * (the "current core").
10668 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10669 + */
10670 +
10671 +/* exported externs */
10672 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10673 +extern sb_t * BCMINIT(sb_kattach)(void);
10674 +extern void sb_detach(sb_t *sbh);
10675 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10676 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10677 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10678 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10679 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10680 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10681 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10682 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10683 +extern uint sb_bus(sb_t *sbh);
10684 +extern uint sb_buscoretype(sb_t *sbh);
10685 +extern uint sb_buscorerev(sb_t *sbh);
10686 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10687 +extern uint sb_coreid(sb_t *sbh);
10688 +extern uint sb_coreidx(sb_t *sbh);
10689 +extern uint sb_coreunit(sb_t *sbh);
10690 +extern uint sb_corevendor(sb_t *sbh);
10691 +extern uint sb_corerev(sb_t *sbh);
10692 +extern void *sb_osh(sb_t *sbh);
10693 +extern void *sb_coreregs(sb_t *sbh);
10694 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10695 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10696 +extern bool sb_iscoreup(sb_t *sbh);
10697 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10698 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10699 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10700 +extern void sb_commit(sb_t *sbh);
10701 +extern uint32 sb_base(uint32 admatch);
10702 +extern uint32 sb_size(uint32 admatch);
10703 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10704 +extern void sb_core_tofixup(sb_t *sbh);
10705 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10706 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10707 +extern uint32 sb_clock(sb_t *sbh);
10708 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10709 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10710 +extern void *sb_gpiosetcore(sb_t *sbh);
10711 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10712 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10713 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10714 +extern uint32 sb_gpioin(sb_t *sbh);
10715 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10716 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10717 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10718 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10719 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10720 +
10721 +extern void sb_clkctl_init(sb_t *sbh);
10722 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10723 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10724 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10725 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10726 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10727 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10728 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10729 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10730 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10731 +
10732 +
10733 +
10734 +/*
10735 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10736 +* The returned path is NULL terminated and has trailing '/'.
10737 +* Return 0 on success, nonzero otherwise.
10738 +*/
10739 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10740 +
10741 +/* clkctl xtal what flags */
10742 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10743 +#define PLL 0x2 /* main chip pll */
10744 +
10745 +/* clkctl clk mode */
10746 +#define CLK_FAST 0 /* force fast (pll) clock */
10747 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10748 +
10749 +
10750 +/* GPIO usage priorities */
10751 +#define GPIO_DRV_PRIORITY 0
10752 +#define GPIO_APP_PRIORITY 1
10753 +
10754 +/* device path */
10755 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10756 +
10757 +#endif /* _sbutils_h_ */
10758 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10759 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10760 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-15 23:29:14.000000000 +0200
10761 @@ -0,0 +1,36 @@
10762 +/*
10763 + * Broadcom SiliconBackplane chipcommon serial flash interface
10764 + *
10765 + * Copyright 2005, Broadcom Corporation
10766 + * All Rights Reserved.
10767 + *
10768 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10769 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10770 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10771 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10772 + *
10773 + * $Id$
10774 + */
10775 +
10776 +#ifndef _sflash_h_
10777 +#define _sflash_h_
10778 +
10779 +#include <typedefs.h>
10780 +#include <sbchipc.h>
10781 +
10782 +struct sflash {
10783 + uint blocksize; /* Block size */
10784 + uint numblocks; /* Number of blocks */
10785 + uint32 type; /* Type */
10786 + uint size; /* Total size in bytes */
10787 +};
10788 +
10789 +/* Utility functions */
10790 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10791 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10792 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10793 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10794 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10795 +extern struct sflash * sflash_init(chipcregs_t *cc);
10796 +
10797 +#endif /* _sflash_h_ */
10798 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10799 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10800 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-15 23:29:14.000000000 +0200
10801 @@ -0,0 +1,33 @@
10802 +/*
10803 + * TRX image file header format.
10804 + *
10805 + * Copyright 2005, Broadcom Corporation
10806 + * All Rights Reserved.
10807 + *
10808 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10809 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10810 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10811 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10812 + *
10813 + * $Id$
10814 + */
10815 +
10816 +#include <typedefs.h>
10817 +
10818 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10819 +#define TRX_VERSION 1
10820 +#define TRX_MAX_LEN 0x3A0000
10821 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10822 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10823 +#define TRX_MAX_OFFSET 3
10824 +
10825 +struct trx_header {
10826 + uint32 magic; /* "HDR0" */
10827 + uint32 len; /* Length of file including header */
10828 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10829 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10830 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10831 +};
10832 +
10833 +/* Compatibility */
10834 +typedef struct trx_header TRXHDR, *PTRXHDR;
10835 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10836 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10837 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-15 23:29:14.000000000 +0200
10838 @@ -0,0 +1,326 @@
10839 +/*
10840 + * Copyright 2005, Broadcom Corporation
10841 + * All Rights Reserved.
10842 + *
10843 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10844 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10845 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10846 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10847 + * $Id$
10848 + */
10849 +
10850 +#ifndef _TYPEDEFS_H_
10851 +#define _TYPEDEFS_H_
10852 +
10853 +
10854 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10855 + * typedef file "site_typedefs.h".
10856 + *
10857 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10858 + * section of this file makes inferences about the compile environment
10859 + * based on defined symbols and possibly compiler pragmas.
10860 + *
10861 + * Following these two sections is the "Default Typedefs"
10862 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10863 + * defined. This section has a default set of typedefs and a few
10864 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10865 + */
10866 +
10867 +#ifdef SITE_TYPEDEFS
10868 +
10869 +/*******************************************************************************
10870 + * Site Specific Typedefs
10871 + *******************************************************************************/
10872 +
10873 +#include "site_typedefs.h"
10874 +
10875 +#else
10876 +
10877 +/*******************************************************************************
10878 + * Inferred Typedefs
10879 + *******************************************************************************/
10880 +
10881 +/* Infer the compile environment based on preprocessor symbols and pramas.
10882 + * Override type definitions as needed, and include configuration dependent
10883 + * header files to define types.
10884 + */
10885 +
10886 +#ifdef __cplusplus
10887 +
10888 +#define TYPEDEF_BOOL
10889 +#ifndef FALSE
10890 +#define FALSE false
10891 +#endif
10892 +#ifndef TRUE
10893 +#define TRUE true
10894 +#endif
10895 +
10896 +#else /* ! __cplusplus */
10897 +
10898 +#if defined(_WIN32)
10899 +
10900 +#define TYPEDEF_BOOL
10901 +typedef unsigned char bool; /* consistent w/BOOL */
10902 +
10903 +#endif /* _WIN32 */
10904 +
10905 +#endif /* ! __cplusplus */
10906 +
10907 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10908 +#if defined(_WIN64)
10909 +#include <basetsd.h>
10910 +#define TYPEDEF_UINTPTR
10911 +typedef ULONG_PTR uintptr;
10912 +#endif
10913 +
10914 +#ifdef _HNDRTE_
10915 +typedef long unsigned int size_t;
10916 +#endif
10917 +
10918 +#ifdef _MSC_VER /* Microsoft C */
10919 +#define TYPEDEF_INT64
10920 +#define TYPEDEF_UINT64
10921 +typedef signed __int64 int64;
10922 +typedef unsigned __int64 uint64;
10923 +#endif
10924 +
10925 +#if defined(MACOSX) && defined(KERNEL)
10926 +#define TYPEDEF_BOOL
10927 +#endif
10928 +
10929 +
10930 +#if defined(linux)
10931 +#define TYPEDEF_UINT
10932 +#define TYPEDEF_USHORT
10933 +#define TYPEDEF_ULONG
10934 +#endif
10935 +
10936 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10937 +#define TYPEDEF_UINT
10938 +#define TYPEDEF_USHORT
10939 +#endif
10940 +
10941 +
10942 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10943 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10944 +#define TYPEDEF_INT64
10945 +#define TYPEDEF_UINT64
10946 +#endif
10947 +
10948 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10949 + * for singned or unsigned */
10950 +#if defined(__ICL)
10951 +
10952 +#define TYPEDEF_INT64
10953 +
10954 +#if defined(__STDC__)
10955 +#define TYPEDEF_UINT64
10956 +#endif
10957 +
10958 +#endif /* __ICL */
10959 +
10960 +
10961 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10962 +
10963 +/* pick up ushort & uint from standard types.h */
10964 +#if defined(linux) && defined(__KERNEL__)
10965 +
10966 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10967 +
10968 +#else
10969 +
10970 +#include <sys/types.h>
10971 +
10972 +#endif
10973 +
10974 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10975 +
10976 +#if defined(MACOSX) && defined(KERNEL)
10977 +#include <IOKit/IOTypes.h>
10978 +#endif
10979 +
10980 +
10981 +/* use the default typedefs in the next section of this file */
10982 +#define USE_TYPEDEF_DEFAULTS
10983 +
10984 +#endif /* SITE_TYPEDEFS */
10985 +
10986 +
10987 +/*******************************************************************************
10988 + * Default Typedefs
10989 + *******************************************************************************/
10990 +
10991 +#ifdef USE_TYPEDEF_DEFAULTS
10992 +#undef USE_TYPEDEF_DEFAULTS
10993 +
10994 +#ifndef TYPEDEF_BOOL
10995 +typedef /*@abstract@*/ unsigned char bool;
10996 +#endif
10997 +
10998 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10999 +
11000 +#ifndef TYPEDEF_UCHAR
11001 +typedef unsigned char uchar;
11002 +#endif
11003 +
11004 +#ifndef TYPEDEF_USHORT
11005 +typedef unsigned short ushort;
11006 +#endif
11007 +
11008 +#ifndef TYPEDEF_UINT
11009 +typedef unsigned int uint;
11010 +#endif
11011 +
11012 +#ifndef TYPEDEF_ULONG
11013 +typedef unsigned long ulong;
11014 +#endif
11015 +
11016 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
11017 +
11018 +#ifndef TYPEDEF_UINT8
11019 +typedef unsigned char uint8;
11020 +#endif
11021 +
11022 +#ifndef TYPEDEF_UINT16
11023 +typedef unsigned short uint16;
11024 +#endif
11025 +
11026 +#ifndef TYPEDEF_UINT32
11027 +typedef unsigned int uint32;
11028 +#endif
11029 +
11030 +#ifndef TYPEDEF_UINT64
11031 +typedef unsigned long long uint64;
11032 +#endif
11033 +
11034 +#ifndef TYPEDEF_UINTPTR
11035 +typedef unsigned int uintptr;
11036 +#endif
11037 +
11038 +#ifndef TYPEDEF_INT8
11039 +typedef signed char int8;
11040 +#endif
11041 +
11042 +#ifndef TYPEDEF_INT16
11043 +typedef signed short int16;
11044 +#endif
11045 +
11046 +#ifndef TYPEDEF_INT32
11047 +typedef signed int int32;
11048 +#endif
11049 +
11050 +#ifndef TYPEDEF_INT64
11051 +typedef signed long long int64;
11052 +#endif
11053 +
11054 +/*----------------------- define float32/64, float_t -----------------------*/
11055 +
11056 +#ifndef TYPEDEF_FLOAT32
11057 +typedef float float32;
11058 +#endif
11059 +
11060 +#ifndef TYPEDEF_FLOAT64
11061 +typedef double float64;
11062 +#endif
11063 +
11064 +/*
11065 + * abstracted floating point type allows for compile time selection of
11066 + * single or double precision arithmetic. Compiling with -DFLOAT32
11067 + * selects single precision; the default is double precision.
11068 + */
11069 +
11070 +#ifndef TYPEDEF_FLOAT_T
11071 +
11072 +#if defined(FLOAT32)
11073 +typedef float32 float_t;
11074 +#else /* default to double precision floating point */
11075 +typedef float64 float_t;
11076 +#endif
11077 +
11078 +#endif /* TYPEDEF_FLOAT_T */
11079 +
11080 +/*----------------------- define macro values -----------------------------*/
11081 +
11082 +#ifndef FALSE
11083 +#define FALSE 0
11084 +#endif
11085 +
11086 +#ifndef TRUE
11087 +#define TRUE 1
11088 +#endif
11089 +
11090 +#ifndef NULL
11091 +#define NULL 0
11092 +#endif
11093 +
11094 +#ifndef OFF
11095 +#define OFF 0
11096 +#endif
11097 +
11098 +#ifndef ON
11099 +#define ON 1
11100 +#endif
11101 +
11102 +#define AUTO (-1)
11103 +
11104 +/* Reclaiming text and data :
11105 + The following macros specify special linker sections that can be reclaimed
11106 + after a system is considered 'up'.
11107 + */
11108 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11109 +extern bool bcmreclaimed;
11110 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11111 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11112 +#define BCMINIT(_id) _id##_ini
11113 +#else
11114 +#define BCMINITDATA(_data) _data
11115 +#define BCMINITFN(_fn) _fn
11116 +#define BCMINIT(_id) _id
11117 +#define bcmreclaimed 0
11118 +#endif
11119 +
11120 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11121 +
11122 +#ifndef PTRSZ
11123 +#define PTRSZ sizeof (char*)
11124 +#endif
11125 +
11126 +#ifndef INLINE
11127 +
11128 +#ifdef _MSC_VER
11129 +
11130 +#define INLINE __inline
11131 +
11132 +#elif __GNUC__
11133 +
11134 +#define INLINE __inline__
11135 +
11136 +#else
11137 +
11138 +#define INLINE
11139 +
11140 +#endif /* _MSC_VER */
11141 +
11142 +#endif /* INLINE */
11143 +
11144 +#undef TYPEDEF_BOOL
11145 +#undef TYPEDEF_UCHAR
11146 +#undef TYPEDEF_USHORT
11147 +#undef TYPEDEF_UINT
11148 +#undef TYPEDEF_ULONG
11149 +#undef TYPEDEF_UINT8
11150 +#undef TYPEDEF_UINT16
11151 +#undef TYPEDEF_UINT32
11152 +#undef TYPEDEF_UINT64
11153 +#undef TYPEDEF_UINTPTR
11154 +#undef TYPEDEF_INT8
11155 +#undef TYPEDEF_INT16
11156 +#undef TYPEDEF_INT32
11157 +#undef TYPEDEF_INT64
11158 +#undef TYPEDEF_FLOAT32
11159 +#undef TYPEDEF_FLOAT64
11160 +#undef TYPEDEF_FLOAT_T
11161 +
11162 +#endif /* USE_TYPEDEF_DEFAULTS */
11163 +
11164 +#endif /* _TYPEDEFS_H_ */
11165 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11166 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11167 +++ linux.dev/arch/mips/bcm947xx/irq.c 2006-10-15 23:29:14.000000000 +0200
11168 @@ -0,0 +1,64 @@
11169 +/*
11170 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11171 + *
11172 + * This program is free software; you can redistribute it and/or modify it
11173 + * under the terms of the GNU General Public License as published by the
11174 + * Free Software Foundation; either version 2 of the License, or (at your
11175 + * option) any later version.
11176 + *
11177 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11178 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11179 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11180 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11181 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11182 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11183 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11184 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11185 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11186 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11187 + *
11188 + * You should have received a copy of the GNU General Public License along
11189 + * with this program; if not, write to the Free Software Foundation, Inc.,
11190 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11191 + */
11192 +
11193 +#include <linux/config.h>
11194 +#include <linux/errno.h>
11195 +#include <linux/init.h>
11196 +#include <linux/interrupt.h>
11197 +#include <linux/irq.h>
11198 +#include <linux/module.h>
11199 +#include <linux/smp.h>
11200 +#include <linux/types.h>
11201 +
11202 +#include <asm/cpu.h>
11203 +#include <asm/io.h>
11204 +#include <asm/irq.h>
11205 +#include <asm/irq_cpu.h>
11206 +
11207 +void plat_irq_dispatch(struct pt_regs *regs)
11208 +{
11209 + u32 cause;
11210 +
11211 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11212 +
11213 + clear_c0_status(cause);
11214 +
11215 + if (cause & CAUSEF_IP7)
11216 + do_IRQ(7, regs);
11217 + if (cause & CAUSEF_IP2)
11218 + do_IRQ(2, regs);
11219 + if (cause & CAUSEF_IP3)
11220 + do_IRQ(3, regs);
11221 + if (cause & CAUSEF_IP4)
11222 + do_IRQ(4, regs);
11223 + if (cause & CAUSEF_IP5)
11224 + do_IRQ(5, regs);
11225 + if (cause & CAUSEF_IP6)
11226 + do_IRQ(6, regs);
11227 +}
11228 +
11229 +void __init arch_init_irq(void)
11230 +{
11231 + mips_cpu_irq_init(0);
11232 +}
11233 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
11234 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
11235 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-15 23:29:14.000000000 +0200
11236 @@ -0,0 +1,6 @@
11237 +#
11238 +# Makefile for the BCM47xx specific kernel interface routines
11239 +# under Linux.
11240 +#
11241 +
11242 +obj-y := irq.o prom.o setup.o time.o pci.o
11243 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11244 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11245 +++ linux.dev/arch/mips/bcm947xx/pci.c 2006-10-15 23:29:14.000000000 +0200
11246 @@ -0,0 +1,215 @@
11247 +#include <linux/kernel.h>
11248 +#include <linux/init.h>
11249 +#include <linux/pci.h>
11250 +#include <linux/types.h>
11251 +
11252 +#include <asm/cpu.h>
11253 +#include <asm/io.h>
11254 +
11255 +#include <typedefs.h>
11256 +#include <osl.h>
11257 +#include <sbutils.h>
11258 +#include <sbmips.h>
11259 +#include <sbconfig.h>
11260 +#include <sbpci.h>
11261 +#include <bcmdevs.h>
11262 +#include <pcicfg.h>
11263 +
11264 +extern sb_t *sbh;
11265 +extern spinlock_t sbh_lock;
11266 +
11267 +
11268 +static int
11269 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11270 + int reg, int size, u32 *val)
11271 +{
11272 + int ret;
11273 + unsigned long flags;
11274 +
11275 + spin_lock_irqsave(&sbh_lock, flags);
11276 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11277 + spin_unlock_irqrestore(&sbh_lock, flags);
11278 +
11279 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11280 +}
11281 +
11282 +static int
11283 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11284 + int reg, int size, u32 val)
11285 +{
11286 + int ret;
11287 + unsigned long flags;
11288 +
11289 + spin_lock_irqsave(&sbh_lock, flags);
11290 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11291 + spin_unlock_irqrestore(&sbh_lock, flags);
11292 +
11293 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11294 +}
11295 +
11296 +
11297 +static struct pci_ops sb_pci_ops = {
11298 + .read = sb_pci_read_config,
11299 + .write = sb_pci_write_config,
11300 +};
11301 +
11302 +static struct resource sb_pci_mem_resource = {
11303 + .name = "SB PCI Memory resources",
11304 + .start = SB_ENUM_BASE,
11305 + .end = SB_ENUM_LIM - 1,
11306 + .flags = IORESOURCE_MEM,
11307 +};
11308 +
11309 +static struct resource sb_pci_io_resource = {
11310 + .name = "SB PCI I/O resources",
11311 + .start = 0x000,
11312 + .end = 0x0FF,
11313 + .flags = IORESOURCE_IO,
11314 +};
11315 +
11316 +static struct pci_controller bcm47xx_sb_pci_controller = {
11317 + .pci_ops = &sb_pci_ops,
11318 + .mem_resource = &sb_pci_mem_resource,
11319 + .io_resource = &sb_pci_io_resource,
11320 +};
11321 +
11322 +static struct resource ext_pci_mem_resource = {
11323 + .name = "Ext PCI Memory resources",
11324 + .start = 0x40000000,
11325 + .end = 0x7fffffff,
11326 + .flags = IORESOURCE_MEM,
11327 +};
11328 +
11329 +static struct resource ext_pci_io_resource = {
11330 + .name = "Ext PCI I/O resources",
11331 + .start = 0x100,
11332 + .end = 0x1FF,
11333 + .flags = IORESOURCE_IO,
11334 +};
11335 +
11336 +static struct pci_controller bcm47xx_ext_pci_controller = {
11337 + .pci_ops = &sb_pci_ops,
11338 + .io_resource = &ext_pci_io_resource,
11339 + .mem_resource = &ext_pci_mem_resource,
11340 + .mem_offset = 0x24000000,
11341 +};
11342 +
11343 +void bcm47xx_pci_init(void)
11344 +{
11345 + unsigned long flags;
11346 +
11347 + spin_lock_irqsave(&sbh_lock, flags);
11348 + sbpci_init(sbh);
11349 + spin_unlock_irqrestore(&sbh_lock, flags);
11350 +
11351 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11352 +
11353 + register_pci_controller(&bcm47xx_sb_pci_controller);
11354 + register_pci_controller(&bcm47xx_ext_pci_controller);
11355 +}
11356 +
11357 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11358 +{
11359 + u8 irq;
11360 +
11361 + if (dev->bus->number == 1)
11362 + return 2;
11363 +
11364 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11365 + return irq + 2;
11366 +}
11367 +
11368 +u32 pci_iobase = 0x100;
11369 +u32 pci_membase = SB_PCI_DMA;
11370 +
11371 +static void bcm47xx_fixup_device(struct pci_dev *d)
11372 +{
11373 + struct resource *res;
11374 + int pos, size;
11375 + u32 *base;
11376 +
11377 + if (d->bus->number == 0)
11378 + return;
11379 +
11380 + printk("PCI: Fixing up device %s\n", pci_name(d));
11381 +
11382 + /* Fix up resource bases */
11383 + for (pos = 0; pos < 6; pos++) {
11384 + res = &d->resource[pos];
11385 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11386 + if (res->end) {
11387 + size = res->end - res->start + 1;
11388 + if (*base & (size - 1))
11389 + *base = (*base + size) & ~(size - 1);
11390 + res->start = *base;
11391 + res->end = res->start + size - 1;
11392 + *base += size;
11393 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11394 + }
11395 + /* Fix up PCI bridge BAR0 only */
11396 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11397 + break;
11398 + }
11399 + /* Fix up interrupt lines */
11400 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11401 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11402 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11403 +}
11404 +
11405 +
11406 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11407 +{
11408 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11409 + return;
11410 +
11411 + printk("PCI: fixing up bridge\n");
11412 +
11413 + /* Enable PCI bridge bus mastering and memory space */
11414 + pci_set_master(dev);
11415 + pcibios_enable_device(dev, ~0);
11416 +
11417 + /* Enable PCI bridge BAR1 prefetch and burst */
11418 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11419 +}
11420 +
11421 +/* Do platform specific device initialization at pci_enable_device() time */
11422 +int pcibios_plat_dev_init(struct pci_dev *dev)
11423 +{
11424 + uint coreidx;
11425 + unsigned long flags;
11426 +
11427 + bcm47xx_fixup_device(dev);
11428 +
11429 + /* These cores come out of reset enabled */
11430 + if ((dev->bus->number != 0) ||
11431 + (dev->device == SB_MIPS) ||
11432 + (dev->device == SB_MIPS33) ||
11433 + (dev->device == SB_EXTIF) ||
11434 + (dev->device == SB_CC))
11435 + return 0;
11436 +
11437 + /* Do a core reset */
11438 + spin_lock_irqsave(&sbh_lock, flags);
11439 + coreidx = sb_coreidx(sbh);
11440 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11441 + /*
11442 + * The USB core requires a special bit to be set during core
11443 + * reset to enable host (OHCI) mode. Resetting the SB core in
11444 + * pcibios_enable_device() is a hack for compatibility with
11445 + * vanilla usb-ohci so that it does not have to know about
11446 + * SB. A driver that wants to use the USB core in device mode
11447 + * should know about SB and should reset the bit back to 0
11448 + * after calling pcibios_enable_device().
11449 + */
11450 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11451 + sb_core_reset(sbh, 1 << 29);
11452 + } else {
11453 + sb_core_reset(sbh, 0);
11454 + }
11455 + sb_setcoreidx(sbh, coreidx);
11456 + spin_unlock_irqrestore(&sbh_lock, flags);
11457 +
11458 + return 0;
11459 +}
11460 +
11461 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11462 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11463 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11464 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-15 23:29:14.000000000 +0200
11465 @@ -0,0 +1,59 @@
11466 +/*
11467 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11468 + *
11469 + * This program is free software; you can redistribute it and/or modify it
11470 + * under the terms of the GNU General Public License as published by the
11471 + * Free Software Foundation; either version 2 of the License, or (at your
11472 + * option) any later version.
11473 + *
11474 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11475 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11476 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11477 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11478 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11479 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11480 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11481 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11482 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11483 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11484 + *
11485 + * You should have received a copy of the GNU General Public License along
11486 + * with this program; if not, write to the Free Software Foundation, Inc.,
11487 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11488 + */
11489 +
11490 +#include <linux/init.h>
11491 +#include <linux/mm.h>
11492 +#include <linux/sched.h>
11493 +#include <linux/bootmem.h>
11494 +
11495 +#include <asm/addrspace.h>
11496 +#include <asm/bootinfo.h>
11497 +#include <asm/pmon.h>
11498 +
11499 +const char *get_system_type(void)
11500 +{
11501 + return "Broadcom BCM47xx";
11502 +}
11503 +
11504 +void __init prom_init(void)
11505 +{
11506 + unsigned long mem;
11507 +
11508 + mips_machgroup = MACH_GROUP_BRCM;
11509 + mips_machtype = MACH_BCM47XX;
11510 +
11511 + /* Figure out memory size by finding aliases */
11512 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11513 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11514 + *(unsigned long *)(prom_init))
11515 + break;
11516 + }
11517 +
11518 + add_memory_region(0, mem, BOOT_MEM_RAM);
11519 +}
11520 +
11521 +unsigned long __init prom_free_prom_memory(void)
11522 +{
11523 + return 0;
11524 +}
11525 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11526 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11527 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-15 23:29:14.000000000 +0200
11528 @@ -0,0 +1,158 @@
11529 +/*
11530 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11531 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11532 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11533 + *
11534 + * This program is free software; you can redistribute it and/or modify it
11535 + * under the terms of the GNU General Public License as published by the
11536 + * Free Software Foundation; either version 2 of the License, or (at your
11537 + * option) any later version.
11538 + *
11539 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11540 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11541 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11542 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11543 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11544 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11545 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11546 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11547 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11548 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11549 + *
11550 + * You should have received a copy of the GNU General Public License along
11551 + * with this program; if not, write to the Free Software Foundation, Inc.,
11552 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11553 + */
11554 +
11555 +#include <linux/init.h>
11556 +#include <linux/types.h>
11557 +#include <linux/tty.h>
11558 +#include <linux/serial.h>
11559 +#include <linux/serial_core.h>
11560 +#include <linux/serial_reg.h>
11561 +#include <asm/bootinfo.h>
11562 +#include <asm/time.h>
11563 +#include <asm/reboot.h>
11564 +#include <linux/pm.h>
11565 +
11566 +#include <typedefs.h>
11567 +#include <osl.h>
11568 +#include <sbutils.h>
11569 +#include <sbmips.h>
11570 +#include <sbpci.h>
11571 +#include <sbconfig.h>
11572 +#include <bcmdevs.h>
11573 +#include <bcmutils.h>
11574 +#include <bcmnvram.h>
11575 +
11576 +extern void bcm47xx_pci_init(void);
11577 +extern void bcm47xx_time_init(void);
11578 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11579 +void *sbh;
11580 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11581 +int boardflags;
11582 +
11583 +static int ser_line = 0;
11584 +
11585 +typedef struct {
11586 + void *regs;
11587 + uint irq;
11588 + uint baud_base;
11589 + uint reg_shift;
11590 +} serial_port;
11591 +
11592 +static serial_port ports[4];
11593 +static int num_ports = 0;
11594 +
11595 +static void
11596 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11597 +{
11598 + ports[num_ports].regs = regs;
11599 + ports[num_ports].irq = irq;
11600 + ports[num_ports].baud_base = baud_base;
11601 + ports[num_ports].reg_shift = reg_shift;
11602 + num_ports++;
11603 +}
11604 +
11605 +static void
11606 +do_serial_add(serial_port *port)
11607 +{
11608 + void *regs;
11609 + uint irq;
11610 + uint baud_base;
11611 + uint reg_shift;
11612 + struct uart_port s;
11613 +
11614 + regs = port->regs;
11615 + irq = port->irq;
11616 + baud_base = port->baud_base;
11617 + reg_shift = port->reg_shift;
11618 +
11619 + memset(&s, 0, sizeof(s));
11620 +
11621 + s.line = ser_line++;
11622 + s.membase = regs;
11623 + s.irq = irq + 2;
11624 + s.uartclk = baud_base;
11625 + s.flags = ASYNC_BOOT_AUTOCONF;
11626 + s.iotype = SERIAL_IO_MEM;
11627 + s.regshift = reg_shift;
11628 +
11629 + if (early_serial_setup(&s) != 0) {
11630 + printk(KERN_ERR "Serial setup failed!\n");
11631 + }
11632 +}
11633 +
11634 +static void bcm47xx_machine_restart(char *command)
11635 +{
11636 + printk("Please stand by while rebooting the system...\n");
11637 +
11638 + /* Set the watchdog timer to reset immediately */
11639 + local_irq_disable();
11640 + sb_watchdog(sbh, 1);
11641 + while (1);
11642 +}
11643 +
11644 +static void bcm47xx_machine_halt(void)
11645 +{
11646 + /* Disable interrupts and watchdog and spin forever */
11647 + local_irq_disable();
11648 + sb_watchdog(sbh, 0);
11649 + while (1);
11650 +}
11651 +
11652 +void __init plat_setup(void)
11653 +{
11654 + char *s;
11655 + int i;
11656 +
11657 + sbh = (void *) sb_kattach();
11658 + sb_mips_init(sbh);
11659 +
11660 + bcm47xx_pci_init();
11661 +
11662 + sb_serial_init(sbh, serial_add);
11663 + boardflags = getintvar(NULL, "boardflags");
11664 +
11665 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11666 + s = early_nvram_get("kernel_args");
11667 + if (!s) s = "";
11668 + if (!strncmp(s, "console=ttyS1", 13)) {
11669 + for (i = num_ports; i; i--)
11670 + do_serial_add(&ports[i - 1]);
11671 + } else {
11672 + for (i = 0; i < num_ports; i++)
11673 + do_serial_add(&ports[i]);
11674 + }
11675 +
11676 + _machine_restart = bcm47xx_machine_restart;
11677 + _machine_halt = bcm47xx_machine_halt;
11678 + pm_power_off = bcm47xx_machine_halt;
11679 +
11680 + board_time_init = bcm47xx_time_init;
11681 + board_timer_setup = bcm47xx_timer_setup;
11682 +}
11683 +
11684 +EXPORT_SYMBOL(sbh);
11685 +EXPORT_SYMBOL(sbh_lock);
11686 +EXPORT_SYMBOL(boardflags);
11687 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11688 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11689 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-15 23:38:36.000000000 +0200
11690 @@ -0,0 +1,65 @@
11691 +/*
11692 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11693 + *
11694 + * This program is free software; you can redistribute it and/or modify it
11695 + * under the terms of the GNU General Public License as published by the
11696 + * Free Software Foundation; either version 2 of the License, or (at your
11697 + * option) any later version.
11698 + *
11699 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11700 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11701 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11702 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11703 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11704 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11705 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11706 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11707 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11708 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11709 + *
11710 + * You should have received a copy of the GNU General Public License along
11711 + * with this program; if not, write to the Free Software Foundation, Inc.,
11712 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11713 + */
11714 +
11715 +#include <linux/config.h>
11716 +#include <linux/init.h>
11717 +#include <linux/kernel.h>
11718 +#include <linux/sched.h>
11719 +#include <linux/serial_reg.h>
11720 +#include <linux/interrupt.h>
11721 +#include <asm/addrspace.h>
11722 +#include <asm/io.h>
11723 +#include <asm/time.h>
11724 +#include <typedefs.h>
11725 +#include <osl.h>
11726 +#include <sbutils.h>
11727 +#include <sbmips.h>
11728 +
11729 +extern sb_t *sbh;
11730 +
11731 +void __init
11732 +bcm47xx_time_init(void)
11733 +{
11734 + unsigned int hz;
11735 +
11736 + /*
11737 + * Use deterministic values for initial counter interrupt
11738 + * so that calibrate delay avoids encountering a counter wrap.
11739 + */
11740 + write_c0_count(0);
11741 + write_c0_compare(0xffff);
11742 +
11743 + hz = sb_cpu_clock(sbh);
11744 +
11745 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11746 + mips_hpt_frequency = hz / 2;
11747 +
11748 +}
11749 +
11750 +void __init
11751 +bcm47xx_timer_setup(struct irqaction *irq)
11752 +{
11753 + /* Enable the timer interrupt */
11754 + setup_irq(7, irq);
11755 +}
11756 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
11757 --- linux.old/arch/mips/Kconfig 2006-10-15 23:32:44.000000000 +0200
11758 +++ linux.dev/arch/mips/Kconfig 2006-10-15 23:29:14.000000000 +0200
11759 @@ -245,6 +245,17 @@
11760 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
11761 Olivetti M700-10 workstations.
11762
11763 +config BCM947XX
11764 + bool "Support for BCM947xx based boards"
11765 + select DMA_NONCOHERENT
11766 + select HW_HAS_PCI
11767 + select IRQ_CPU
11768 + select SYS_HAS_CPU_MIPS32_R1
11769 + select SYS_SUPPORTS_32BIT_KERNEL
11770 + select SYS_SUPPORTS_LITTLE_ENDIAN
11771 + help
11772 + Support for BCM947xx based boards
11773 +
11774 config LASAT
11775 bool "LASAT Networks platforms"
11776 select DMA_NONCOHERENT
11777 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11778 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-15 23:32:44.000000000 +0200
11779 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-15 23:29:14.000000000 +0200
11780 @@ -691,6 +691,28 @@
11781 }
11782
11783
11784 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11785 +{
11786 + decode_config1(c);
11787 + switch (c->processor_id & 0xff00) {
11788 + case PRID_IMP_BCM3302:
11789 + c->cputype = CPU_BCM3302;
11790 + c->isa_level = MIPS_CPU_ISA_M32R1;
11791 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11792 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11793 + break;
11794 + case PRID_IMP_BCM4710:
11795 + c->cputype = CPU_BCM4710;
11796 + c->isa_level = MIPS_CPU_ISA_M32R1;
11797 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11798 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11799 + break;
11800 + default:
11801 + c->cputype = CPU_UNKNOWN;
11802 + break;
11803 + }
11804 +}
11805 +
11806 __init void cpu_probe(void)
11807 {
11808 struct cpuinfo_mips *c = &current_cpu_data;
11809 @@ -713,6 +735,9 @@
11810 case PRID_COMP_SIBYTE:
11811 cpu_probe_sibyte(c);
11812 break;
11813 + case PRID_COMP_BROADCOM:
11814 + cpu_probe_broadcom(c);
11815 + break;
11816 case PRID_COMP_SANDCRAFT:
11817 cpu_probe_sandcraft(c);
11818 break;
11819 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11820 --- linux.old/arch/mips/kernel/head.S 2006-10-15 23:32:44.000000000 +0200
11821 +++ linux.dev/arch/mips/kernel/head.S 2006-10-15 23:29:14.000000000 +0200
11822 @@ -133,6 +133,11 @@
11823 j kernel_entry
11824 nop
11825
11826 +#ifdef CONFIG_BCM4710
11827 +#undef eret
11828 +#define eret nop; nop; eret
11829 +#endif
11830 +
11831 /*
11832 * Reserved space for exception handlers.
11833 * Necessary for machines which link their kernels at KSEG0.
11834 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11835 --- linux.old/arch/mips/kernel/proc.c 2006-10-15 23:32:44.000000000 +0200
11836 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-15 23:29:14.000000000 +0200
11837 @@ -84,6 +84,8 @@
11838 [CPU_VR4181] = "NEC VR4181",
11839 [CPU_VR4181A] = "NEC VR4181A",
11840 [CPU_SR71000] = "Sandcraft SR71000",
11841 + [CPU_BCM3302] = "Broadcom BCM3302",
11842 + [CPU_BCM4710] = "Broadcom BCM4710",
11843 [CPU_PR4450] = "Philips PR4450",
11844 };
11845
11846 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
11847 --- linux.old/arch/mips/Makefile 2006-10-15 23:32:44.000000000 +0200
11848 +++ linux.dev/arch/mips/Makefile 2006-10-15 23:29:14.000000000 +0200
11849 @@ -565,6 +565,13 @@
11850 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
11851
11852 #
11853 +# Broadcom BCM47XX boards
11854 +#
11855 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
11856 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
11857 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
11858 +
11859 +#
11860 # SNI RM200 PCI
11861 #
11862 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
11863 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11864 --- linux.old/arch/mips/mm/tlbex.c 2006-10-15 23:32:44.000000000 +0200
11865 +++ linux.dev/arch/mips/mm/tlbex.c 2006-10-15 23:31:06.000000000 +0200
11866 @@ -882,6 +882,8 @@
11867 case CPU_4KSC:
11868 case CPU_20KC:
11869 case CPU_25KF:
11870 + case CPU_BCM3302:
11871 + case CPU_BCM4710:
11872 tlbw(p);
11873 break;
11874
11875 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11876 --- linux.old/include/asm-mips/bootinfo.h 2006-10-15 23:32:44.000000000 +0200
11877 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-15 23:29:14.000000000 +0200
11878 @@ -218,6 +218,12 @@
11879 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11880 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11881
11882 +/*
11883 + * Valid machtype for group Broadcom
11884 + */
11885 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11886 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11887 +
11888 #define CL_SIZE COMMAND_LINE_SIZE
11889
11890 const char *get_system_type(void);
11891 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11892 --- linux.old/include/asm-mips/cpu.h 2006-10-15 23:32:44.000000000 +0200
11893 +++ linux.dev/include/asm-mips/cpu.h 2006-10-15 23:29:14.000000000 +0200
11894 @@ -104,6 +104,13 @@
11895 #define PRID_IMP_SR71000 0x0400
11896
11897 /*
11898 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11899 + */
11900 +
11901 +#define PRID_IMP_BCM4710 0x4000
11902 +#define PRID_IMP_BCM3302 0x9000
11903 +
11904 +/*
11905 * Definitions for 7:0 on legacy processors
11906 */
11907
11908 @@ -200,7 +207,9 @@
11909 #define CPU_SB1A 62
11910 #define CPU_74K 63
11911 #define CPU_R14000 64
11912 -#define CPU_LAST 64
11913 +#define CPU_BCM3302 65
11914 +#define CPU_BCM4710 66
11915 +#define CPU_LAST 66
11916
11917 /*
11918 * ISA Level encodings
11919 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11920 --- linux.old/include/linux/pci_ids.h 2006-10-15 23:32:44.000000000 +0200
11921 +++ linux.dev/include/linux/pci_ids.h 2006-10-15 23:29:14.000000000 +0200
11922 @@ -1906,6 +1906,7 @@
11923 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11924 #define PCI_DEVICE_ID_BCM4401 0x4401
11925 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11926 +#define PCI_DEVICE_ID_BCM4713 0x4713
11927
11928 #define PCI_VENDOR_ID_TOPIC 0x151f
11929 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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