1 --- linux-mips-cvs/arch/mips/mm/c-r4k.c 2004-11-03 17:43:07.000000000 +0100
2 +++ linux-cache/arch/mips/mm/c-r4k.c 2005-03-06 23:39:53.000000000 +0100
4 c->options |= MIPS_CPU_SUBSET_CACHES;
7 +#if defined(CONFIG_BCM4310)
8 +static void __init _change_cachability(u32 cm)
10 + struct cpuinfo_mips *c = ¤t_cpu_data;
12 + change_c0_config(CONF_CM_CMASK, cm);
13 + if ((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) ==
14 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) {
15 + cm = read_c0_diag();
24 +static void (*change_cachability)(u32);
27 static inline void coherency_setup(void)
29 +#if defined(CONFIG_BCM4310)
30 + change_cachability = (void (*)(u32)) KSEG1ADDR((unsigned long)(_change_cachability));
31 + change_cachability(CONF_CM_DEFAULT);
33 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
37 * c0_status.cu=0 specifies that updates by the sc instruction use