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ath9k: fix crash issues caused by the ar9300 support patch
[openwrt.git] / package / mac80211 / patches / 300-ar9300_support.patch
1 --- a/drivers/net/wireless/ath/ath9k/Makefile
2 +++ b/drivers/net/wireless/ath/ath9k/Makefile
3 @@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
4
5 obj-$(CONFIG_ATH9K) += ath9k.o
6
7 -ath9k_hw-y:= hw.o \
8 +ath9k_hw-y:= \
9 + ar9002_hw.o \
10 + ar9003_hw.o \
11 + hw.o \
12 + ar9003_phy.o \
13 + ar9002_phy.o \
14 + ar5008_phy.o \
15 + ar9002_calib.o \
16 + ar9003_calib.o \
17 + calib.o \
18 eeprom.o \
19 eeprom_def.o \
20 eeprom_4k.o \
21 eeprom_9287.o \
22 - calib.o \
23 ani.o \
24 - phy.o \
25 btcoex.o \
26 mac.o \
27 + ar9002_mac.o \
28 + ar9003_mac.o \
29 + ar9003_eeprom.o
30
31 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
32
33 --- a/drivers/net/wireless/ath/ath9k/ani.c
34 +++ b/drivers/net/wireless/ath/ath9k/ani.c
35 @@ -15,6 +15,7 @@
36 */
37
38 #include "hw.h"
39 +#include "hw-ops.h"
40
41 static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43 @@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(
44 return 0;
45 }
46
47 -static bool ath9k_hw_ani_control(struct ath_hw *ah,
48 - enum ath9k_ani_cmd cmd, int param)
49 -{
50 - struct ar5416AniState *aniState = ah->curani;
51 - struct ath_common *common = ath9k_hw_common(ah);
52 -
53 - switch (cmd & ah->ani_function) {
54 - case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
55 - u32 level = param;
56 -
57 - if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
58 - ath_print(common, ATH_DBG_ANI,
59 - "level out of range (%u > %u)\n",
60 - level,
61 - (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
62 - return false;
63 - }
64 -
65 - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
66 - AR_PHY_DESIRED_SZ_TOT_DES,
67 - ah->totalSizeDesired[level]);
68 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 - AR_PHY_AGC_CTL1_COARSE_LOW,
70 - ah->coarse_low[level]);
71 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
72 - AR_PHY_AGC_CTL1_COARSE_HIGH,
73 - ah->coarse_high[level]);
74 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
75 - AR_PHY_FIND_SIG_FIRPWR,
76 - ah->firpwr[level]);
77 -
78 - if (level > aniState->noiseImmunityLevel)
79 - ah->stats.ast_ani_niup++;
80 - else if (level < aniState->noiseImmunityLevel)
81 - ah->stats.ast_ani_nidown++;
82 - aniState->noiseImmunityLevel = level;
83 - break;
84 - }
85 - case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
86 - const int m1ThreshLow[] = { 127, 50 };
87 - const int m2ThreshLow[] = { 127, 40 };
88 - const int m1Thresh[] = { 127, 0x4d };
89 - const int m2Thresh[] = { 127, 0x40 };
90 - const int m2CountThr[] = { 31, 16 };
91 - const int m2CountThrLow[] = { 63, 48 };
92 - u32 on = param ? 1 : 0;
93 -
94 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
95 - AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
96 - m1ThreshLow[on]);
97 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
98 - AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
99 - m2ThreshLow[on]);
100 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
101 - AR_PHY_SFCORR_M1_THRESH,
102 - m1Thresh[on]);
103 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
104 - AR_PHY_SFCORR_M2_THRESH,
105 - m2Thresh[on]);
106 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
107 - AR_PHY_SFCORR_M2COUNT_THR,
108 - m2CountThr[on]);
109 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
110 - AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
111 - m2CountThrLow[on]);
112 -
113 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
114 - AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
115 - m1ThreshLow[on]);
116 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
117 - AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
118 - m2ThreshLow[on]);
119 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 - AR_PHY_SFCORR_EXT_M1_THRESH,
121 - m1Thresh[on]);
122 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
123 - AR_PHY_SFCORR_EXT_M2_THRESH,
124 - m2Thresh[on]);
125 -
126 - if (on)
127 - REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
128 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
129 - else
130 - REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
131 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
132 -
133 - if (!on != aniState->ofdmWeakSigDetectOff) {
134 - if (on)
135 - ah->stats.ast_ani_ofdmon++;
136 - else
137 - ah->stats.ast_ani_ofdmoff++;
138 - aniState->ofdmWeakSigDetectOff = !on;
139 - }
140 - break;
141 - }
142 - case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
143 - const int weakSigThrCck[] = { 8, 6 };
144 - u32 high = param ? 1 : 0;
145 -
146 - REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
147 - AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
148 - weakSigThrCck[high]);
149 - if (high != aniState->cckWeakSigThreshold) {
150 - if (high)
151 - ah->stats.ast_ani_cckhigh++;
152 - else
153 - ah->stats.ast_ani_ccklow++;
154 - aniState->cckWeakSigThreshold = high;
155 - }
156 - break;
157 - }
158 - case ATH9K_ANI_FIRSTEP_LEVEL:{
159 - const int firstep[] = { 0, 4, 8 };
160 - u32 level = param;
161 -
162 - if (level >= ARRAY_SIZE(firstep)) {
163 - ath_print(common, ATH_DBG_ANI,
164 - "level out of range (%u > %u)\n",
165 - level,
166 - (unsigned) ARRAY_SIZE(firstep));
167 - return false;
168 - }
169 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
170 - AR_PHY_FIND_SIG_FIRSTEP,
171 - firstep[level]);
172 - if (level > aniState->firstepLevel)
173 - ah->stats.ast_ani_stepup++;
174 - else if (level < aniState->firstepLevel)
175 - ah->stats.ast_ani_stepdown++;
176 - aniState->firstepLevel = level;
177 - break;
178 - }
179 - case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
180 - const int cycpwrThr1[] =
181 - { 2, 4, 6, 8, 10, 12, 14, 16 };
182 - u32 level = param;
183 -
184 - if (level >= ARRAY_SIZE(cycpwrThr1)) {
185 - ath_print(common, ATH_DBG_ANI,
186 - "level out of range (%u > %u)\n",
187 - level,
188 - (unsigned) ARRAY_SIZE(cycpwrThr1));
189 - return false;
190 - }
191 - REG_RMW_FIELD(ah, AR_PHY_TIMING5,
192 - AR_PHY_TIMING5_CYCPWR_THR1,
193 - cycpwrThr1[level]);
194 - if (level > aniState->spurImmunityLevel)
195 - ah->stats.ast_ani_spurup++;
196 - else if (level < aniState->spurImmunityLevel)
197 - ah->stats.ast_ani_spurdown++;
198 - aniState->spurImmunityLevel = level;
199 - break;
200 - }
201 - case ATH9K_ANI_PRESENT:
202 - break;
203 - default:
204 - ath_print(common, ATH_DBG_ANI,
205 - "invalid cmd %u\n", cmd);
206 - return false;
207 - }
208 -
209 - ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
210 - ath_print(common, ATH_DBG_ANI,
211 - "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
212 - "ofdmWeakSigDetectOff=%d\n",
213 - aniState->noiseImmunityLevel,
214 - aniState->spurImmunityLevel,
215 - !aniState->ofdmWeakSigDetectOff);
216 - ath_print(common, ATH_DBG_ANI,
217 - "cckWeakSigThreshold=%d, "
218 - "firstepLevel=%d, listenTime=%d\n",
219 - aniState->cckWeakSigThreshold,
220 - aniState->firstepLevel,
221 - aniState->listenTime);
222 - ath_print(common, ATH_DBG_ANI,
223 - "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
224 - aniState->cycleCount,
225 - aniState->ofdmPhyErrCount,
226 - aniState->cckPhyErrCount);
227 -
228 - return true;
229 -}
230 -
231 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
232 struct ath9k_mib_stats *stats)
233 {
234 --- /dev/null
235 +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
236 @@ -0,0 +1,742 @@
237 +/*
238 + * Copyright (c) 2008-2009 Atheros Communications Inc.
239 + *
240 + * Permission to use, copy, modify, and/or distribute this software for any
241 + * purpose with or without fee is hereby granted, provided that the above
242 + * copyright notice and this permission notice appear in all copies.
243 + *
244 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
245 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
246 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
247 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
248 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
249 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
250 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
251 + */
252 +
253 +#ifndef INITVALS_AR5008_H
254 +#define INITVALS_AR5008_H
255 +
256 +static const u32 ar5416Modes[][6] = {
257 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
258 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
259 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
260 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
261 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
262 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
263 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
264 + { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
265 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
266 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
267 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
268 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
269 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
270 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
271 + { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
272 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
273 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
274 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
275 + { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
276 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
277 + { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
278 + { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
279 + { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
280 + { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
281 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
282 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
283 + { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
284 + { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
285 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
286 + { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
287 + { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
288 + { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
289 + { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
290 + { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
291 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
292 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
293 + { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
294 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
295 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
296 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
297 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
298 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
299 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
300 + { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
301 + { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
302 + { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
303 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
304 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
305 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
306 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
307 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
308 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
309 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
310 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
311 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
312 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
313 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
314 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
315 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
316 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
317 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
318 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
319 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
320 +};
321 +
322 +static const u32 ar5416Common[][2] = {
323 + { 0x0000000c, 0x00000000 },
324 + { 0x00000030, 0x00020015 },
325 + { 0x00000034, 0x00000005 },
326 + { 0x00000040, 0x00000000 },
327 + { 0x00000044, 0x00000008 },
328 + { 0x00000048, 0x00000008 },
329 + { 0x0000004c, 0x00000010 },
330 + { 0x00000050, 0x00000000 },
331 + { 0x00000054, 0x0000001f },
332 + { 0x00000800, 0x00000000 },
333 + { 0x00000804, 0x00000000 },
334 + { 0x00000808, 0x00000000 },
335 + { 0x0000080c, 0x00000000 },
336 + { 0x00000810, 0x00000000 },
337 + { 0x00000814, 0x00000000 },
338 + { 0x00000818, 0x00000000 },
339 + { 0x0000081c, 0x00000000 },
340 + { 0x00000820, 0x00000000 },
341 + { 0x00000824, 0x00000000 },
342 + { 0x00001040, 0x002ffc0f },
343 + { 0x00001044, 0x002ffc0f },
344 + { 0x00001048, 0x002ffc0f },
345 + { 0x0000104c, 0x002ffc0f },
346 + { 0x00001050, 0x002ffc0f },
347 + { 0x00001054, 0x002ffc0f },
348 + { 0x00001058, 0x002ffc0f },
349 + { 0x0000105c, 0x002ffc0f },
350 + { 0x00001060, 0x002ffc0f },
351 + { 0x00001064, 0x002ffc0f },
352 + { 0x00001230, 0x00000000 },
353 + { 0x00001270, 0x00000000 },
354 + { 0x00001038, 0x00000000 },
355 + { 0x00001078, 0x00000000 },
356 + { 0x000010b8, 0x00000000 },
357 + { 0x000010f8, 0x00000000 },
358 + { 0x00001138, 0x00000000 },
359 + { 0x00001178, 0x00000000 },
360 + { 0x000011b8, 0x00000000 },
361 + { 0x000011f8, 0x00000000 },
362 + { 0x00001238, 0x00000000 },
363 + { 0x00001278, 0x00000000 },
364 + { 0x000012b8, 0x00000000 },
365 + { 0x000012f8, 0x00000000 },
366 + { 0x00001338, 0x00000000 },
367 + { 0x00001378, 0x00000000 },
368 + { 0x000013b8, 0x00000000 },
369 + { 0x000013f8, 0x00000000 },
370 + { 0x00001438, 0x00000000 },
371 + { 0x00001478, 0x00000000 },
372 + { 0x000014b8, 0x00000000 },
373 + { 0x000014f8, 0x00000000 },
374 + { 0x00001538, 0x00000000 },
375 + { 0x00001578, 0x00000000 },
376 + { 0x000015b8, 0x00000000 },
377 + { 0x000015f8, 0x00000000 },
378 + { 0x00001638, 0x00000000 },
379 + { 0x00001678, 0x00000000 },
380 + { 0x000016b8, 0x00000000 },
381 + { 0x000016f8, 0x00000000 },
382 + { 0x00001738, 0x00000000 },
383 + { 0x00001778, 0x00000000 },
384 + { 0x000017b8, 0x00000000 },
385 + { 0x000017f8, 0x00000000 },
386 + { 0x0000103c, 0x00000000 },
387 + { 0x0000107c, 0x00000000 },
388 + { 0x000010bc, 0x00000000 },
389 + { 0x000010fc, 0x00000000 },
390 + { 0x0000113c, 0x00000000 },
391 + { 0x0000117c, 0x00000000 },
392 + { 0x000011bc, 0x00000000 },
393 + { 0x000011fc, 0x00000000 },
394 + { 0x0000123c, 0x00000000 },
395 + { 0x0000127c, 0x00000000 },
396 + { 0x000012bc, 0x00000000 },
397 + { 0x000012fc, 0x00000000 },
398 + { 0x0000133c, 0x00000000 },
399 + { 0x0000137c, 0x00000000 },
400 + { 0x000013bc, 0x00000000 },
401 + { 0x000013fc, 0x00000000 },
402 + { 0x0000143c, 0x00000000 },
403 + { 0x0000147c, 0x00000000 },
404 + { 0x00004030, 0x00000002 },
405 + { 0x0000403c, 0x00000002 },
406 + { 0x00007010, 0x00000000 },
407 + { 0x00007038, 0x000004c2 },
408 + { 0x00008004, 0x00000000 },
409 + { 0x00008008, 0x00000000 },
410 + { 0x0000800c, 0x00000000 },
411 + { 0x00008018, 0x00000700 },
412 + { 0x00008020, 0x00000000 },
413 + { 0x00008038, 0x00000000 },
414 + { 0x0000803c, 0x00000000 },
415 + { 0x00008048, 0x40000000 },
416 + { 0x00008054, 0x00000000 },
417 + { 0x00008058, 0x00000000 },
418 + { 0x0000805c, 0x000fc78f },
419 + { 0x00008060, 0x0000000f },
420 + { 0x00008064, 0x00000000 },
421 + { 0x000080c0, 0x2a82301a },
422 + { 0x000080c4, 0x05dc01e0 },
423 + { 0x000080c8, 0x1f402710 },
424 + { 0x000080cc, 0x01f40000 },
425 + { 0x000080d0, 0x00001e00 },
426 + { 0x000080d4, 0x00000000 },
427 + { 0x000080d8, 0x00400000 },
428 + { 0x000080e0, 0xffffffff },
429 + { 0x000080e4, 0x0000ffff },
430 + { 0x000080e8, 0x003f3f3f },
431 + { 0x000080ec, 0x00000000 },
432 + { 0x000080f0, 0x00000000 },
433 + { 0x000080f4, 0x00000000 },
434 + { 0x000080f8, 0x00000000 },
435 + { 0x000080fc, 0x00020000 },
436 + { 0x00008100, 0x00020000 },
437 + { 0x00008104, 0x00000001 },
438 + { 0x00008108, 0x00000052 },
439 + { 0x0000810c, 0x00000000 },
440 + { 0x00008110, 0x00000168 },
441 + { 0x00008118, 0x000100aa },
442 + { 0x0000811c, 0x00003210 },
443 + { 0x00008124, 0x00000000 },
444 + { 0x00008128, 0x00000000 },
445 + { 0x0000812c, 0x00000000 },
446 + { 0x00008130, 0x00000000 },
447 + { 0x00008134, 0x00000000 },
448 + { 0x00008138, 0x00000000 },
449 + { 0x0000813c, 0x00000000 },
450 + { 0x00008144, 0xffffffff },
451 + { 0x00008168, 0x00000000 },
452 + { 0x0000816c, 0x00000000 },
453 + { 0x00008170, 0x32143320 },
454 + { 0x00008174, 0xfaa4fa50 },
455 + { 0x00008178, 0x00000100 },
456 + { 0x0000817c, 0x00000000 },
457 + { 0x000081c4, 0x00000000 },
458 + { 0x000081ec, 0x00000000 },
459 + { 0x000081f0, 0x00000000 },
460 + { 0x000081f4, 0x00000000 },
461 + { 0x000081f8, 0x00000000 },
462 + { 0x000081fc, 0x00000000 },
463 + { 0x00008200, 0x00000000 },
464 + { 0x00008204, 0x00000000 },
465 + { 0x00008208, 0x00000000 },
466 + { 0x0000820c, 0x00000000 },
467 + { 0x00008210, 0x00000000 },
468 + { 0x00008214, 0x00000000 },
469 + { 0x00008218, 0x00000000 },
470 + { 0x0000821c, 0x00000000 },
471 + { 0x00008220, 0x00000000 },
472 + { 0x00008224, 0x00000000 },
473 + { 0x00008228, 0x00000000 },
474 + { 0x0000822c, 0x00000000 },
475 + { 0x00008230, 0x00000000 },
476 + { 0x00008234, 0x00000000 },
477 + { 0x00008238, 0x00000000 },
478 + { 0x0000823c, 0x00000000 },
479 + { 0x00008240, 0x00100000 },
480 + { 0x00008244, 0x0010f400 },
481 + { 0x00008248, 0x00000100 },
482 + { 0x0000824c, 0x0001e800 },
483 + { 0x00008250, 0x00000000 },
484 + { 0x00008254, 0x00000000 },
485 + { 0x00008258, 0x00000000 },
486 + { 0x0000825c, 0x400000ff },
487 + { 0x00008260, 0x00080922 },
488 + { 0x00008264, 0xa8000010 },
489 + { 0x00008270, 0x00000000 },
490 + { 0x00008274, 0x40000000 },
491 + { 0x00008278, 0x003e4180 },
492 + { 0x0000827c, 0x00000000 },
493 + { 0x00008284, 0x0000002c },
494 + { 0x00008288, 0x0000002c },
495 + { 0x0000828c, 0x00000000 },
496 + { 0x00008294, 0x00000000 },
497 + { 0x00008298, 0x00000000 },
498 + { 0x00008300, 0x00000000 },
499 + { 0x00008304, 0x00000000 },
500 + { 0x00008308, 0x00000000 },
501 + { 0x0000830c, 0x00000000 },
502 + { 0x00008310, 0x00000000 },
503 + { 0x00008314, 0x00000000 },
504 + { 0x00008318, 0x00000000 },
505 + { 0x00008328, 0x00000000 },
506 + { 0x0000832c, 0x00000007 },
507 + { 0x00008330, 0x00000302 },
508 + { 0x00008334, 0x00000e00 },
509 + { 0x00008338, 0x00070000 },
510 + { 0x0000833c, 0x00000000 },
511 + { 0x00008340, 0x000107ff },
512 + { 0x00009808, 0x00000000 },
513 + { 0x0000980c, 0xad848e19 },
514 + { 0x00009810, 0x7d14e000 },
515 + { 0x00009814, 0x9c0a9f6b },
516 + { 0x0000981c, 0x00000000 },
517 + { 0x0000982c, 0x0000a000 },
518 + { 0x00009830, 0x00000000 },
519 + { 0x0000983c, 0x00200400 },
520 + { 0x00009840, 0x206a002e },
521 + { 0x0000984c, 0x1284233c },
522 + { 0x00009854, 0x00000859 },
523 + { 0x00009900, 0x00000000 },
524 + { 0x00009904, 0x00000000 },
525 + { 0x00009908, 0x00000000 },
526 + { 0x0000990c, 0x00000000 },
527 + { 0x0000991c, 0x10000fff },
528 + { 0x00009920, 0x05100000 },
529 + { 0x0000a920, 0x05100000 },
530 + { 0x0000b920, 0x05100000 },
531 + { 0x00009928, 0x00000001 },
532 + { 0x0000992c, 0x00000004 },
533 + { 0x00009934, 0x1e1f2022 },
534 + { 0x00009938, 0x0a0b0c0d },
535 + { 0x0000993c, 0x00000000 },
536 + { 0x00009948, 0x9280b212 },
537 + { 0x0000994c, 0x00020028 },
538 + { 0x00009954, 0x5d50e188 },
539 + { 0x00009958, 0x00081fff },
540 + { 0x0000c95c, 0x004b6a8e },
541 + { 0x0000c968, 0x000003ce },
542 + { 0x00009970, 0x190fb515 },
543 + { 0x00009974, 0x00000000 },
544 + { 0x00009978, 0x00000001 },
545 + { 0x0000997c, 0x00000000 },
546 + { 0x00009980, 0x00000000 },
547 + { 0x00009984, 0x00000000 },
548 + { 0x00009988, 0x00000000 },
549 + { 0x0000998c, 0x00000000 },
550 + { 0x00009990, 0x00000000 },
551 + { 0x00009994, 0x00000000 },
552 + { 0x00009998, 0x00000000 },
553 + { 0x0000999c, 0x00000000 },
554 + { 0x000099a0, 0x00000000 },
555 + { 0x000099a4, 0x00000001 },
556 + { 0x000099a8, 0x001fff00 },
557 + { 0x000099ac, 0x00000000 },
558 + { 0x000099b0, 0x03051000 },
559 + { 0x000099dc, 0x00000000 },
560 + { 0x000099e0, 0x00000200 },
561 + { 0x000099e4, 0xaaaaaaaa },
562 + { 0x000099e8, 0x3c466478 },
563 + { 0x000099ec, 0x000000aa },
564 + { 0x000099fc, 0x00001042 },
565 + { 0x00009b00, 0x00000000 },
566 + { 0x00009b04, 0x00000001 },
567 + { 0x00009b08, 0x00000002 },
568 + { 0x00009b0c, 0x00000003 },
569 + { 0x00009b10, 0x00000004 },
570 + { 0x00009b14, 0x00000005 },
571 + { 0x00009b18, 0x00000008 },
572 + { 0x00009b1c, 0x00000009 },
573 + { 0x00009b20, 0x0000000a },
574 + { 0x00009b24, 0x0000000b },
575 + { 0x00009b28, 0x0000000c },
576 + { 0x00009b2c, 0x0000000d },
577 + { 0x00009b30, 0x00000010 },
578 + { 0x00009b34, 0x00000011 },
579 + { 0x00009b38, 0x00000012 },
580 + { 0x00009b3c, 0x00000013 },
581 + { 0x00009b40, 0x00000014 },
582 + { 0x00009b44, 0x00000015 },
583 + { 0x00009b48, 0x00000018 },
584 + { 0x00009b4c, 0x00000019 },
585 + { 0x00009b50, 0x0000001a },
586 + { 0x00009b54, 0x0000001b },
587 + { 0x00009b58, 0x0000001c },
588 + { 0x00009b5c, 0x0000001d },
589 + { 0x00009b60, 0x00000020 },
590 + { 0x00009b64, 0x00000021 },
591 + { 0x00009b68, 0x00000022 },
592 + { 0x00009b6c, 0x00000023 },
593 + { 0x00009b70, 0x00000024 },
594 + { 0x00009b74, 0x00000025 },
595 + { 0x00009b78, 0x00000028 },
596 + { 0x00009b7c, 0x00000029 },
597 + { 0x00009b80, 0x0000002a },
598 + { 0x00009b84, 0x0000002b },
599 + { 0x00009b88, 0x0000002c },
600 + { 0x00009b8c, 0x0000002d },
601 + { 0x00009b90, 0x00000030 },
602 + { 0x00009b94, 0x00000031 },
603 + { 0x00009b98, 0x00000032 },
604 + { 0x00009b9c, 0x00000033 },
605 + { 0x00009ba0, 0x00000034 },
606 + { 0x00009ba4, 0x00000035 },
607 + { 0x00009ba8, 0x00000035 },
608 + { 0x00009bac, 0x00000035 },
609 + { 0x00009bb0, 0x00000035 },
610 + { 0x00009bb4, 0x00000035 },
611 + { 0x00009bb8, 0x00000035 },
612 + { 0x00009bbc, 0x00000035 },
613 + { 0x00009bc0, 0x00000035 },
614 + { 0x00009bc4, 0x00000035 },
615 + { 0x00009bc8, 0x00000035 },
616 + { 0x00009bcc, 0x00000035 },
617 + { 0x00009bd0, 0x00000035 },
618 + { 0x00009bd4, 0x00000035 },
619 + { 0x00009bd8, 0x00000035 },
620 + { 0x00009bdc, 0x00000035 },
621 + { 0x00009be0, 0x00000035 },
622 + { 0x00009be4, 0x00000035 },
623 + { 0x00009be8, 0x00000035 },
624 + { 0x00009bec, 0x00000035 },
625 + { 0x00009bf0, 0x00000035 },
626 + { 0x00009bf4, 0x00000035 },
627 + { 0x00009bf8, 0x00000010 },
628 + { 0x00009bfc, 0x0000001a },
629 + { 0x0000a210, 0x40806333 },
630 + { 0x0000a214, 0x00106c10 },
631 + { 0x0000a218, 0x009c4060 },
632 + { 0x0000a220, 0x018830c6 },
633 + { 0x0000a224, 0x00000400 },
634 + { 0x0000a228, 0x00000bb5 },
635 + { 0x0000a22c, 0x00000011 },
636 + { 0x0000a234, 0x20202020 },
637 + { 0x0000a238, 0x20202020 },
638 + { 0x0000a23c, 0x13c889af },
639 + { 0x0000a240, 0x38490a20 },
640 + { 0x0000a244, 0x00007bb6 },
641 + { 0x0000a248, 0x0fff3ffc },
642 + { 0x0000a24c, 0x00000001 },
643 + { 0x0000a250, 0x0000a000 },
644 + { 0x0000a254, 0x00000000 },
645 + { 0x0000a258, 0x0cc75380 },
646 + { 0x0000a25c, 0x0f0f0f01 },
647 + { 0x0000a260, 0xdfa91f01 },
648 + { 0x0000a268, 0x00000000 },
649 + { 0x0000a26c, 0x0e79e5c6 },
650 + { 0x0000b26c, 0x0e79e5c6 },
651 + { 0x0000c26c, 0x0e79e5c6 },
652 + { 0x0000d270, 0x00820820 },
653 + { 0x0000a278, 0x1ce739ce },
654 + { 0x0000a27c, 0x051701ce },
655 + { 0x0000a338, 0x00000000 },
656 + { 0x0000a33c, 0x00000000 },
657 + { 0x0000a340, 0x00000000 },
658 + { 0x0000a344, 0x00000000 },
659 + { 0x0000a348, 0x3fffffff },
660 + { 0x0000a34c, 0x3fffffff },
661 + { 0x0000a350, 0x3fffffff },
662 + { 0x0000a354, 0x0003ffff },
663 + { 0x0000a358, 0x79a8aa1f },
664 + { 0x0000d35c, 0x07ffffef },
665 + { 0x0000d360, 0x0fffffe7 },
666 + { 0x0000d364, 0x17ffffe5 },
667 + { 0x0000d368, 0x1fffffe4 },
668 + { 0x0000d36c, 0x37ffffe3 },
669 + { 0x0000d370, 0x3fffffe3 },
670 + { 0x0000d374, 0x57ffffe3 },
671 + { 0x0000d378, 0x5fffffe2 },
672 + { 0x0000d37c, 0x7fffffe2 },
673 + { 0x0000d380, 0x7f3c7bba },
674 + { 0x0000d384, 0xf3307ff0 },
675 + { 0x0000a388, 0x08000000 },
676 + { 0x0000a38c, 0x20202020 },
677 + { 0x0000a390, 0x20202020 },
678 + { 0x0000a394, 0x1ce739ce },
679 + { 0x0000a398, 0x000001ce },
680 + { 0x0000a39c, 0x00000001 },
681 + { 0x0000a3a0, 0x00000000 },
682 + { 0x0000a3a4, 0x00000000 },
683 + { 0x0000a3a8, 0x00000000 },
684 + { 0x0000a3ac, 0x00000000 },
685 + { 0x0000a3b0, 0x00000000 },
686 + { 0x0000a3b4, 0x00000000 },
687 + { 0x0000a3b8, 0x00000000 },
688 + { 0x0000a3bc, 0x00000000 },
689 + { 0x0000a3c0, 0x00000000 },
690 + { 0x0000a3c4, 0x00000000 },
691 + { 0x0000a3c8, 0x00000246 },
692 + { 0x0000a3cc, 0x20202020 },
693 + { 0x0000a3d0, 0x20202020 },
694 + { 0x0000a3d4, 0x20202020 },
695 + { 0x0000a3dc, 0x1ce739ce },
696 + { 0x0000a3e0, 0x000001ce },
697 +};
698 +
699 +static const u32 ar5416Bank0[][2] = {
700 + { 0x000098b0, 0x1e5795e5 },
701 + { 0x000098e0, 0x02008020 },
702 +};
703 +
704 +static const u32 ar5416BB_RfGain[][3] = {
705 + { 0x00009a00, 0x00000000, 0x00000000 },
706 + { 0x00009a04, 0x00000040, 0x00000040 },
707 + { 0x00009a08, 0x00000080, 0x00000080 },
708 + { 0x00009a0c, 0x000001a1, 0x00000141 },
709 + { 0x00009a10, 0x000001e1, 0x00000181 },
710 + { 0x00009a14, 0x00000021, 0x000001c1 },
711 + { 0x00009a18, 0x00000061, 0x00000001 },
712 + { 0x00009a1c, 0x00000168, 0x00000041 },
713 + { 0x00009a20, 0x000001a8, 0x000001a8 },
714 + { 0x00009a24, 0x000001e8, 0x000001e8 },
715 + { 0x00009a28, 0x00000028, 0x00000028 },
716 + { 0x00009a2c, 0x00000068, 0x00000068 },
717 + { 0x00009a30, 0x00000189, 0x000000a8 },
718 + { 0x00009a34, 0x000001c9, 0x00000169 },
719 + { 0x00009a38, 0x00000009, 0x000001a9 },
720 + { 0x00009a3c, 0x00000049, 0x000001e9 },
721 + { 0x00009a40, 0x00000089, 0x00000029 },
722 + { 0x00009a44, 0x00000170, 0x00000069 },
723 + { 0x00009a48, 0x000001b0, 0x00000190 },
724 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
725 + { 0x00009a50, 0x00000030, 0x00000010 },
726 + { 0x00009a54, 0x00000070, 0x00000050 },
727 + { 0x00009a58, 0x00000191, 0x00000090 },
728 + { 0x00009a5c, 0x000001d1, 0x00000151 },
729 + { 0x00009a60, 0x00000011, 0x00000191 },
730 + { 0x00009a64, 0x00000051, 0x000001d1 },
731 + { 0x00009a68, 0x00000091, 0x00000011 },
732 + { 0x00009a6c, 0x000001b8, 0x00000051 },
733 + { 0x00009a70, 0x000001f8, 0x00000198 },
734 + { 0x00009a74, 0x00000038, 0x000001d8 },
735 + { 0x00009a78, 0x00000078, 0x00000018 },
736 + { 0x00009a7c, 0x00000199, 0x00000058 },
737 + { 0x00009a80, 0x000001d9, 0x00000098 },
738 + { 0x00009a84, 0x00000019, 0x00000159 },
739 + { 0x00009a88, 0x00000059, 0x00000199 },
740 + { 0x00009a8c, 0x00000099, 0x000001d9 },
741 + { 0x00009a90, 0x000000d9, 0x00000019 },
742 + { 0x00009a94, 0x000000f9, 0x00000059 },
743 + { 0x00009a98, 0x000000f9, 0x00000099 },
744 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
745 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
746 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
747 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
748 + { 0x00009aac, 0x000000f9, 0x000000f9 },
749 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
750 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
751 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
752 + { 0x00009abc, 0x000000f9, 0x000000f9 },
753 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
754 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
755 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
756 + { 0x00009acc, 0x000000f9, 0x000000f9 },
757 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
758 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
759 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
760 + { 0x00009adc, 0x000000f9, 0x000000f9 },
761 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
762 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
763 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
764 + { 0x00009aec, 0x000000f9, 0x000000f9 },
765 + { 0x00009af0, 0x000000f9, 0x000000f9 },
766 + { 0x00009af4, 0x000000f9, 0x000000f9 },
767 + { 0x00009af8, 0x000000f9, 0x000000f9 },
768 + { 0x00009afc, 0x000000f9, 0x000000f9 },
769 +};
770 +
771 +static const u32 ar5416Bank1[][2] = {
772 + { 0x000098b0, 0x02108421 },
773 + { 0x000098ec, 0x00000008 },
774 +};
775 +
776 +static const u32 ar5416Bank2[][2] = {
777 + { 0x000098b0, 0x0e73ff17 },
778 + { 0x000098e0, 0x00000420 },
779 +};
780 +
781 +static const u32 ar5416Bank3[][3] = {
782 + { 0x000098f0, 0x01400018, 0x01c00018 },
783 +};
784 +
785 +static const u32 ar5416Bank6[][3] = {
786 +
787 + { 0x0000989c, 0x00000000, 0x00000000 },
788 + { 0x0000989c, 0x00000000, 0x00000000 },
789 + { 0x0000989c, 0x00000000, 0x00000000 },
790 + { 0x0000989c, 0x00e00000, 0x00e00000 },
791 + { 0x0000989c, 0x005e0000, 0x005e0000 },
792 + { 0x0000989c, 0x00120000, 0x00120000 },
793 + { 0x0000989c, 0x00620000, 0x00620000 },
794 + { 0x0000989c, 0x00020000, 0x00020000 },
795 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
796 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
797 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
798 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
799 + { 0x0000989c, 0x005f0000, 0x005f0000 },
800 + { 0x0000989c, 0x00870000, 0x00870000 },
801 + { 0x0000989c, 0x00f90000, 0x00f90000 },
802 + { 0x0000989c, 0x007b0000, 0x007b0000 },
803 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
804 + { 0x0000989c, 0x00f50000, 0x00f50000 },
805 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
806 + { 0x0000989c, 0x00110000, 0x00110000 },
807 + { 0x0000989c, 0x006100a8, 0x006100a8 },
808 + { 0x0000989c, 0x004210a2, 0x004210a2 },
809 + { 0x0000989c, 0x0014008f, 0x0014008f },
810 + { 0x0000989c, 0x00c40003, 0x00c40003 },
811 + { 0x0000989c, 0x003000f2, 0x003000f2 },
812 + { 0x0000989c, 0x00440016, 0x00440016 },
813 + { 0x0000989c, 0x00410040, 0x00410040 },
814 + { 0x0000989c, 0x0001805e, 0x0001805e },
815 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
816 + { 0x0000989c, 0x000000f1, 0x000000f1 },
817 + { 0x0000989c, 0x00002081, 0x00002081 },
818 + { 0x0000989c, 0x000000d4, 0x000000d4 },
819 + { 0x000098d0, 0x0000000f, 0x0010000f },
820 +};
821 +
822 +static const u32 ar5416Bank6TPC[][3] = {
823 + { 0x0000989c, 0x00000000, 0x00000000 },
824 + { 0x0000989c, 0x00000000, 0x00000000 },
825 + { 0x0000989c, 0x00000000, 0x00000000 },
826 + { 0x0000989c, 0x00e00000, 0x00e00000 },
827 + { 0x0000989c, 0x005e0000, 0x005e0000 },
828 + { 0x0000989c, 0x00120000, 0x00120000 },
829 + { 0x0000989c, 0x00620000, 0x00620000 },
830 + { 0x0000989c, 0x00020000, 0x00020000 },
831 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
832 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
833 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
834 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
835 + { 0x0000989c, 0x005f0000, 0x005f0000 },
836 + { 0x0000989c, 0x00870000, 0x00870000 },
837 + { 0x0000989c, 0x00f90000, 0x00f90000 },
838 + { 0x0000989c, 0x007b0000, 0x007b0000 },
839 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
840 + { 0x0000989c, 0x00f50000, 0x00f50000 },
841 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
842 + { 0x0000989c, 0x00110000, 0x00110000 },
843 + { 0x0000989c, 0x006100a8, 0x006100a8 },
844 + { 0x0000989c, 0x00423022, 0x00423022 },
845 + { 0x0000989c, 0x201400df, 0x201400df },
846 + { 0x0000989c, 0x00c40002, 0x00c40002 },
847 + { 0x0000989c, 0x003000f2, 0x003000f2 },
848 + { 0x0000989c, 0x00440016, 0x00440016 },
849 + { 0x0000989c, 0x00410040, 0x00410040 },
850 + { 0x0000989c, 0x0001805e, 0x0001805e },
851 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
852 + { 0x0000989c, 0x000000e1, 0x000000e1 },
853 + { 0x0000989c, 0x00007081, 0x00007081 },
854 + { 0x0000989c, 0x000000d4, 0x000000d4 },
855 + { 0x000098d0, 0x0000000f, 0x0010000f },
856 +};
857 +
858 +static const u32 ar5416Bank7[][2] = {
859 + { 0x0000989c, 0x00000500 },
860 + { 0x0000989c, 0x00000800 },
861 + { 0x000098cc, 0x0000000e },
862 +};
863 +
864 +static const u32 ar5416Addac[][2] = {
865 + {0x0000989c, 0x00000000 },
866 + {0x0000989c, 0x00000003 },
867 + {0x0000989c, 0x00000000 },
868 + {0x0000989c, 0x0000000c },
869 + {0x0000989c, 0x00000000 },
870 + {0x0000989c, 0x00000030 },
871 + {0x0000989c, 0x00000000 },
872 + {0x0000989c, 0x00000000 },
873 + {0x0000989c, 0x00000000 },
874 + {0x0000989c, 0x00000000 },
875 + {0x0000989c, 0x00000000 },
876 + {0x0000989c, 0x00000000 },
877 + {0x0000989c, 0x00000000 },
878 + {0x0000989c, 0x00000000 },
879 + {0x0000989c, 0x00000000 },
880 + {0x0000989c, 0x00000000 },
881 + {0x0000989c, 0x00000000 },
882 + {0x0000989c, 0x00000000 },
883 + {0x0000989c, 0x00000060 },
884 + {0x0000989c, 0x00000000 },
885 + {0x0000989c, 0x00000000 },
886 + {0x0000989c, 0x00000000 },
887 + {0x0000989c, 0x00000000 },
888 + {0x0000989c, 0x00000000 },
889 + {0x0000989c, 0x00000000 },
890 + {0x0000989c, 0x00000000 },
891 + {0x0000989c, 0x00000000 },
892 + {0x0000989c, 0x00000000 },
893 + {0x0000989c, 0x00000000 },
894 + {0x0000989c, 0x00000000 },
895 + {0x0000989c, 0x00000000 },
896 + {0x0000989c, 0x00000058 },
897 + {0x0000989c, 0x00000000 },
898 + {0x0000989c, 0x00000000 },
899 + {0x0000989c, 0x00000000 },
900 + {0x0000989c, 0x00000000 },
901 + {0x000098cc, 0x00000000 },
902 +};
903 +
904 +static const u32 ar5416Modes_9100[][6] = {
905 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
906 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
907 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
908 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
909 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
910 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
911 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
912 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
913 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
914 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
915 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
916 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
917 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
918 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
919 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
920 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
921 + { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
922 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
923 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
924 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
925 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
926 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
927 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
928 + { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
929 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
930 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
931 + { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
932 + { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
933 + { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
934 + { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
935 +#ifdef TB243
936 + { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
937 + { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
938 + { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
939 + { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
940 +#else
941 + { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
942 + { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
943 + { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
944 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
945 +#endif
946 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
947 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
948 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
949 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
950 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
951 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
952 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
953 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
954 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
955 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
956 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
957 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
958 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
959 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
960 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
961 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
962 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
963 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
964 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
965 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
966 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
967 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
968 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
969 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
970 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
971 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
972 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
973 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
974 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
975 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
976 +};
977 +
978 +#endif /* INITVALS_AR5008_H */
979 --- /dev/null
980 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
981 @@ -0,0 +1,1347 @@
982 +/*
983 + * Copyright (c) 2008-2010 Atheros Communications Inc.
984 + *
985 + * Permission to use, copy, modify, and/or distribute this software for any
986 + * purpose with or without fee is hereby granted, provided that the above
987 + * copyright notice and this permission notice appear in all copies.
988 + *
989 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
990 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
991 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
992 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
993 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
994 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
995 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
996 + */
997 +
998 +#include "hw.h"
999 +#include "hw-ops.h"
1000 +#include "../regd.h"
1001 +#include "ar9002_phy.h"
1002 +
1003 +/* All code below is for non single-chip solutions */
1004 +
1005 +/**
1006 + * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
1007 + * @rfbuf:
1008 + * @reg32:
1009 + * @numBits:
1010 + * @firstBit:
1011 + * @column:
1012 + *
1013 + * Performs analog "swizzling" of parameters into their location.
1014 + * Used on external AR2133/AR5133 radios.
1015 + */
1016 +static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
1017 + u32 numBits, u32 firstBit,
1018 + u32 column)
1019 +{
1020 + u32 tmp32, mask, arrayEntry, lastBit;
1021 + int32_t bitPosition, bitsLeft;
1022 +
1023 + tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
1024 + arrayEntry = (firstBit - 1) / 8;
1025 + bitPosition = (firstBit - 1) % 8;
1026 + bitsLeft = numBits;
1027 + while (bitsLeft > 0) {
1028 + lastBit = (bitPosition + bitsLeft > 8) ?
1029 + 8 : bitPosition + bitsLeft;
1030 + mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
1031 + (column * 8);
1032 + rfBuf[arrayEntry] &= ~mask;
1033 + rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
1034 + (column * 8)) & mask;
1035 + bitsLeft -= 8 - bitPosition;
1036 + tmp32 = tmp32 >> (8 - bitPosition);
1037 + bitPosition = 0;
1038 + arrayEntry++;
1039 + }
1040 +}
1041 +
1042 +/*
1043 + * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
1044 + * rf_pwd_icsyndiv.
1045 + *
1046 + * Theoretical Rules:
1047 + * if 2 GHz band
1048 + * if forceBiasAuto
1049 + * if synth_freq < 2412
1050 + * bias = 0
1051 + * else if 2412 <= synth_freq <= 2422
1052 + * bias = 1
1053 + * else // synth_freq > 2422
1054 + * bias = 2
1055 + * else if forceBias > 0
1056 + * bias = forceBias & 7
1057 + * else
1058 + * no change, use value from ini file
1059 + * else
1060 + * no change, invalid band
1061 + *
1062 + * 1st Mod:
1063 + * 2422 also uses value of 2
1064 + * <approved>
1065 + *
1066 + * 2nd Mod:
1067 + * Less than 2412 uses value of 0, 2412 and above uses value of 2
1068 + */
1069 +static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
1070 +{
1071 + struct ath_common *common = ath9k_hw_common(ah);
1072 + u32 tmp_reg;
1073 + int reg_writes = 0;
1074 + u32 new_bias = 0;
1075 +
1076 + if (!AR_SREV_5416(ah) || synth_freq >= 3000)
1077 + return;
1078 +
1079 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1080 +
1081 + if (synth_freq < 2412)
1082 + new_bias = 0;
1083 + else if (synth_freq < 2422)
1084 + new_bias = 1;
1085 + else
1086 + new_bias = 2;
1087 +
1088 + /* pre-reverse this field */
1089 + tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
1090 +
1091 + ath_print(common, ATH_DBG_CONFIG,
1092 + "Force rf_pwd_icsyndiv to %1d on %4d\n",
1093 + new_bias, synth_freq);
1094 +
1095 + /* swizzle rf_pwd_icsyndiv */
1096 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
1097 +
1098 + /* write Bank 6 with new params */
1099 + REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
1100 +}
1101 +
1102 +/**
1103 + * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
1104 + * @ah: atheros hardware stucture
1105 + * @chan:
1106 + *
1107 + * For the external AR2133/AR5133 radios, takes the MHz channel value and set
1108 + * the channel value. Assumes writes enabled to analog bus and bank6 register
1109 + * cache in ah->analogBank6Data.
1110 + */
1111 +static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
1112 +{
1113 + struct ath_common *common = ath9k_hw_common(ah);
1114 + u32 channelSel = 0;
1115 + u32 bModeSynth = 0;
1116 + u32 aModeRefSel = 0;
1117 + u32 reg32 = 0;
1118 + u16 freq;
1119 + struct chan_centers centers;
1120 +
1121 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1122 + freq = centers.synth_center;
1123 +
1124 + if (freq < 4800) {
1125 + u32 txctl;
1126 +
1127 + if (((freq - 2192) % 5) == 0) {
1128 + channelSel = ((freq - 672) * 2 - 3040) / 10;
1129 + bModeSynth = 0;
1130 + } else if (((freq - 2224) % 5) == 0) {
1131 + channelSel = ((freq - 704) * 2 - 3040) / 10;
1132 + bModeSynth = 1;
1133 + } else {
1134 + ath_print(common, ATH_DBG_FATAL,
1135 + "Invalid channel %u MHz\n", freq);
1136 + return -EINVAL;
1137 + }
1138 +
1139 + channelSel = (channelSel << 2) & 0xff;
1140 + channelSel = ath9k_hw_reverse_bits(channelSel, 8);
1141 +
1142 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1143 + if (freq == 2484) {
1144 +
1145 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1146 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1147 + } else {
1148 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1149 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
1150 + }
1151 +
1152 + } else if ((freq % 20) == 0 && freq >= 5120) {
1153 + channelSel =
1154 + ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
1155 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1156 + } else if ((freq % 10) == 0) {
1157 + channelSel =
1158 + ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
1159 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1160 + aModeRefSel = ath9k_hw_reverse_bits(2, 2);
1161 + else
1162 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1163 + } else if ((freq % 5) == 0) {
1164 + channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
1165 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1166 + } else {
1167 + ath_print(common, ATH_DBG_FATAL,
1168 + "Invalid channel %u MHz\n", freq);
1169 + return -EINVAL;
1170 + }
1171 +
1172 + ar5008_hw_force_bias(ah, freq);
1173 +
1174 + reg32 =
1175 + (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
1176 + (1 << 5) | 0x1;
1177 +
1178 + REG_WRITE(ah, AR_PHY(0x37), reg32);
1179 +
1180 + ah->curchan = chan;
1181 + ah->curchan_rad_index = -1;
1182 +
1183 + return 0;
1184 +}
1185 +
1186 +/**
1187 + * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
1188 + * @ah: atheros hardware structure
1189 + * @chan:
1190 + *
1191 + * For non single-chip solutions. Converts to baseband spur frequency given the
1192 + * input channel frequency and compute register settings below.
1193 + */
1194 +static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
1195 + struct ath9k_channel *chan)
1196 +{
1197 + int bb_spur = AR_NO_SPUR;
1198 + int bin, cur_bin;
1199 + int spur_freq_sd;
1200 + int spur_delta_phase;
1201 + int denominator;
1202 + int upper, lower, cur_vit_mask;
1203 + int tmp, new;
1204 + int i;
1205 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1206 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1207 + };
1208 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1209 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1210 + };
1211 + int inc[4] = { 0, 100, 0, 0 };
1212 +
1213 + int8_t mask_m[123];
1214 + int8_t mask_p[123];
1215 + int8_t mask_amt;
1216 + int tmp_mask;
1217 + int cur_bb_spur;
1218 + bool is2GHz = IS_CHAN_2GHZ(chan);
1219 +
1220 + memset(&mask_m, 0, sizeof(int8_t) * 123);
1221 + memset(&mask_p, 0, sizeof(int8_t) * 123);
1222 +
1223 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1224 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1225 + if (AR_NO_SPUR == cur_bb_spur)
1226 + break;
1227 + cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1228 + if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1229 + bb_spur = cur_bb_spur;
1230 + break;
1231 + }
1232 + }
1233 +
1234 + if (AR_NO_SPUR == bb_spur)
1235 + return;
1236 +
1237 + bin = bb_spur * 32;
1238 +
1239 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1240 + new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1241 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1242 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1243 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1244 +
1245 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1246 +
1247 + new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1248 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1249 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1250 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1251 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1252 + REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1253 +
1254 + spur_delta_phase = ((bb_spur * 524288) / 100) &
1255 + AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1256 +
1257 + denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1258 + spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1259 +
1260 + new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1261 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1262 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1263 + REG_WRITE(ah, AR_PHY_TIMING11, new);
1264 +
1265 + cur_bin = -6000;
1266 + upper = bin + 100;
1267 + lower = bin - 100;
1268 +
1269 + for (i = 0; i < 4; i++) {
1270 + int pilot_mask = 0;
1271 + int chan_mask = 0;
1272 + int bp = 0;
1273 + for (bp = 0; bp < 30; bp++) {
1274 + if ((cur_bin > lower) && (cur_bin < upper)) {
1275 + pilot_mask = pilot_mask | 0x1 << bp;
1276 + chan_mask = chan_mask | 0x1 << bp;
1277 + }
1278 + cur_bin += 100;
1279 + }
1280 + cur_bin += inc[i];
1281 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1282 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1283 + }
1284 +
1285 + cur_vit_mask = 6100;
1286 + upper = bin + 120;
1287 + lower = bin - 120;
1288 +
1289 + for (i = 0; i < 123; i++) {
1290 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1291 +
1292 + /* workaround for gcc bug #37014 */
1293 + volatile int tmp_v = abs(cur_vit_mask - bin);
1294 +
1295 + if (tmp_v < 75)
1296 + mask_amt = 1;
1297 + else
1298 + mask_amt = 0;
1299 + if (cur_vit_mask < 0)
1300 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1301 + else
1302 + mask_p[cur_vit_mask / 100] = mask_amt;
1303 + }
1304 + cur_vit_mask -= 100;
1305 + }
1306 +
1307 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1308 + | (mask_m[48] << 26) | (mask_m[49] << 24)
1309 + | (mask_m[50] << 22) | (mask_m[51] << 20)
1310 + | (mask_m[52] << 18) | (mask_m[53] << 16)
1311 + | (mask_m[54] << 14) | (mask_m[55] << 12)
1312 + | (mask_m[56] << 10) | (mask_m[57] << 8)
1313 + | (mask_m[58] << 6) | (mask_m[59] << 4)
1314 + | (mask_m[60] << 2) | (mask_m[61] << 0);
1315 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1316 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1317 +
1318 + tmp_mask = (mask_m[31] << 28)
1319 + | (mask_m[32] << 26) | (mask_m[33] << 24)
1320 + | (mask_m[34] << 22) | (mask_m[35] << 20)
1321 + | (mask_m[36] << 18) | (mask_m[37] << 16)
1322 + | (mask_m[48] << 14) | (mask_m[39] << 12)
1323 + | (mask_m[40] << 10) | (mask_m[41] << 8)
1324 + | (mask_m[42] << 6) | (mask_m[43] << 4)
1325 + | (mask_m[44] << 2) | (mask_m[45] << 0);
1326 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1327 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1328 +
1329 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1330 + | (mask_m[18] << 26) | (mask_m[18] << 24)
1331 + | (mask_m[20] << 22) | (mask_m[20] << 20)
1332 + | (mask_m[22] << 18) | (mask_m[22] << 16)
1333 + | (mask_m[24] << 14) | (mask_m[24] << 12)
1334 + | (mask_m[25] << 10) | (mask_m[26] << 8)
1335 + | (mask_m[27] << 6) | (mask_m[28] << 4)
1336 + | (mask_m[29] << 2) | (mask_m[30] << 0);
1337 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1338 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1339 +
1340 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1341 + | (mask_m[2] << 26) | (mask_m[3] << 24)
1342 + | (mask_m[4] << 22) | (mask_m[5] << 20)
1343 + | (mask_m[6] << 18) | (mask_m[7] << 16)
1344 + | (mask_m[8] << 14) | (mask_m[9] << 12)
1345 + | (mask_m[10] << 10) | (mask_m[11] << 8)
1346 + | (mask_m[12] << 6) | (mask_m[13] << 4)
1347 + | (mask_m[14] << 2) | (mask_m[15] << 0);
1348 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1349 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1350 +
1351 + tmp_mask = (mask_p[15] << 28)
1352 + | (mask_p[14] << 26) | (mask_p[13] << 24)
1353 + | (mask_p[12] << 22) | (mask_p[11] << 20)
1354 + | (mask_p[10] << 18) | (mask_p[9] << 16)
1355 + | (mask_p[8] << 14) | (mask_p[7] << 12)
1356 + | (mask_p[6] << 10) | (mask_p[5] << 8)
1357 + | (mask_p[4] << 6) | (mask_p[3] << 4)
1358 + | (mask_p[2] << 2) | (mask_p[1] << 0);
1359 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1360 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1361 +
1362 + tmp_mask = (mask_p[30] << 28)
1363 + | (mask_p[29] << 26) | (mask_p[28] << 24)
1364 + | (mask_p[27] << 22) | (mask_p[26] << 20)
1365 + | (mask_p[25] << 18) | (mask_p[24] << 16)
1366 + | (mask_p[23] << 14) | (mask_p[22] << 12)
1367 + | (mask_p[21] << 10) | (mask_p[20] << 8)
1368 + | (mask_p[19] << 6) | (mask_p[18] << 4)
1369 + | (mask_p[17] << 2) | (mask_p[16] << 0);
1370 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1371 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1372 +
1373 + tmp_mask = (mask_p[45] << 28)
1374 + | (mask_p[44] << 26) | (mask_p[43] << 24)
1375 + | (mask_p[42] << 22) | (mask_p[41] << 20)
1376 + | (mask_p[40] << 18) | (mask_p[39] << 16)
1377 + | (mask_p[38] << 14) | (mask_p[37] << 12)
1378 + | (mask_p[36] << 10) | (mask_p[35] << 8)
1379 + | (mask_p[34] << 6) | (mask_p[33] << 4)
1380 + | (mask_p[32] << 2) | (mask_p[31] << 0);
1381 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1382 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1383 +
1384 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1385 + | (mask_p[59] << 26) | (mask_p[58] << 24)
1386 + | (mask_p[57] << 22) | (mask_p[56] << 20)
1387 + | (mask_p[55] << 18) | (mask_p[54] << 16)
1388 + | (mask_p[53] << 14) | (mask_p[52] << 12)
1389 + | (mask_p[51] << 10) | (mask_p[50] << 8)
1390 + | (mask_p[49] << 6) | (mask_p[48] << 4)
1391 + | (mask_p[47] << 2) | (mask_p[46] << 0);
1392 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1393 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1394 +}
1395 +
1396 +/**
1397 + * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
1398 + * @ah: atheros hardware structure
1399 + *
1400 + * Only required for older devices with external AR2133/AR5133 radios.
1401 + */
1402 +static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
1403 +{
1404 +#define ATH_ALLOC_BANK(bank, size) do { \
1405 + bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
1406 + if (!bank) { \
1407 + ath_print(common, ATH_DBG_FATAL, \
1408 + "Cannot allocate RF banks\n"); \
1409 + return -ENOMEM; \
1410 + } \
1411 + } while (0);
1412 +
1413 + struct ath_common *common = ath9k_hw_common(ah);
1414 +
1415 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1416 +
1417 + ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
1418 + ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
1419 + ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
1420 + ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
1421 + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
1422 + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
1423 + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
1424 + ATH_ALLOC_BANK(ah->addac5416_21,
1425 + ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
1426 + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
1427 +
1428 + return 0;
1429 +#undef ATH_ALLOC_BANK
1430 +}
1431 +
1432 +
1433 +/**
1434 + * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
1435 + * @ah: atheros hardware struture
1436 + * For the external AR2133/AR5133 radios banks.
1437 + */
1438 +static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
1439 +{
1440 +#define ATH_FREE_BANK(bank) do { \
1441 + kfree(bank); \
1442 + bank = NULL; \
1443 + } while (0);
1444 +
1445 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1446 +
1447 + ATH_FREE_BANK(ah->analogBank0Data);
1448 + ATH_FREE_BANK(ah->analogBank1Data);
1449 + ATH_FREE_BANK(ah->analogBank2Data);
1450 + ATH_FREE_BANK(ah->analogBank3Data);
1451 + ATH_FREE_BANK(ah->analogBank6Data);
1452 + ATH_FREE_BANK(ah->analogBank6TPCData);
1453 + ATH_FREE_BANK(ah->analogBank7Data);
1454 + ATH_FREE_BANK(ah->addac5416_21);
1455 + ATH_FREE_BANK(ah->bank6Temp);
1456 +
1457 +#undef ATH_FREE_BANK
1458 +}
1459 +
1460 +/* *
1461 + * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
1462 + * @ah: atheros hardware structure
1463 + * @chan:
1464 + * @modesIndex:
1465 + *
1466 + * Used for the external AR2133/AR5133 radios.
1467 + *
1468 + * Reads the EEPROM header info from the device structure and programs
1469 + * all rf registers. This routine requires access to the analog
1470 + * rf device. This is not required for single-chip devices.
1471 + */
1472 +static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
1473 + struct ath9k_channel *chan,
1474 + u16 modesIndex)
1475 +{
1476 + u32 eepMinorRev;
1477 + u32 ob5GHz = 0, db5GHz = 0;
1478 + u32 ob2GHz = 0, db2GHz = 0;
1479 + int regWrites = 0;
1480 +
1481 + /*
1482 + * Software does not need to program bank data
1483 + * for single chip devices, that is AR9280 or anything
1484 + * after that.
1485 + */
1486 + if (AR_SREV_9280_10_OR_LATER(ah))
1487 + return true;
1488 +
1489 + /* Setup rf parameters */
1490 + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
1491 +
1492 + /* Setup Bank 0 Write */
1493 + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
1494 +
1495 + /* Setup Bank 1 Write */
1496 + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
1497 +
1498 + /* Setup Bank 2 Write */
1499 + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
1500 +
1501 + /* Setup Bank 6 Write */
1502 + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
1503 + modesIndex);
1504 + {
1505 + int i;
1506 + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
1507 + ah->analogBank6Data[i] =
1508 + INI_RA(&ah->iniBank6TPC, i, modesIndex);
1509 + }
1510 + }
1511 +
1512 + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
1513 + if (eepMinorRev >= 2) {
1514 + if (IS_CHAN_2GHZ(chan)) {
1515 + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
1516 + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
1517 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1518 + ob2GHz, 3, 197, 0);
1519 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1520 + db2GHz, 3, 194, 0);
1521 + } else {
1522 + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
1523 + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
1524 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1525 + ob5GHz, 3, 203, 0);
1526 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1527 + db5GHz, 3, 200, 0);
1528 + }
1529 + }
1530 +
1531 + /* Setup Bank 7 Setup */
1532 + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
1533 +
1534 + /* Write Analog registers */
1535 + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
1536 + regWrites);
1537 + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
1538 + regWrites);
1539 + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
1540 + regWrites);
1541 + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
1542 + regWrites);
1543 + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
1544 + regWrites);
1545 + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
1546 + regWrites);
1547 +
1548 + return true;
1549 +}
1550 +
1551 +static void ar5008_hw_init_bb(struct ath_hw *ah,
1552 + struct ath9k_channel *chan)
1553 +{
1554 + u32 synthDelay;
1555 +
1556 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1557 + if (IS_CHAN_B(chan))
1558 + synthDelay = (4 * synthDelay) / 22;
1559 + else
1560 + synthDelay /= 10;
1561 +
1562 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1563 +
1564 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1565 +}
1566 +
1567 +static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
1568 +{
1569 + int rx_chainmask, tx_chainmask;
1570 +
1571 + rx_chainmask = ah->rxchainmask;
1572 + tx_chainmask = ah->txchainmask;
1573 +
1574 + switch (rx_chainmask) {
1575 + case 0x5:
1576 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1577 + AR_PHY_SWAP_ALT_CHAIN);
1578 + case 0x3:
1579 + if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1580 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1581 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1582 + break;
1583 + }
1584 + case 0x1:
1585 + case 0x2:
1586 + case 0x7:
1587 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1588 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1589 + break;
1590 + default:
1591 + break;
1592 + }
1593 +
1594 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1595 + if (tx_chainmask == 0x5) {
1596 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1597 + AR_PHY_SWAP_ALT_CHAIN);
1598 + }
1599 + if (AR_SREV_9100(ah))
1600 + REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1601 + REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1602 +}
1603 +
1604 +static void ar5008_hw_override_ini(struct ath_hw *ah,
1605 + struct ath9k_channel *chan)
1606 +{
1607 + u32 val;
1608 +
1609 + /*
1610 + * Set the RX_ABORT and RX_DIS and clear if off only after
1611 + * RXE is set for MAC. This prevents frames with corrupted
1612 + * descriptor status.
1613 + */
1614 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1615 +
1616 + if (AR_SREV_9280_10_OR_LATER(ah)) {
1617 + val = REG_READ(ah, AR_PCU_MISC_MODE2);
1618 +
1619 + if (!AR_SREV_9271(ah))
1620 + val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1621 +
1622 + if (AR_SREV_9287_10_OR_LATER(ah))
1623 + val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1624 +
1625 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1626 + }
1627 +
1628 + if (!AR_SREV_5416_20_OR_LATER(ah) ||
1629 + AR_SREV_9280_10_OR_LATER(ah))
1630 + return;
1631 + /*
1632 + * Disable BB clock gating
1633 + * Necessary to avoid issues on AR5416 2.0
1634 + */
1635 + REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1636 +
1637 + /*
1638 + * Disable RIFS search on some chips to avoid baseband
1639 + * hang issues.
1640 + */
1641 + if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1642 + val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1643 + val &= ~AR_PHY_RIFS_INIT_DELAY;
1644 + REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1645 + }
1646 +}
1647 +
1648 +static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
1649 + struct ath9k_channel *chan)
1650 +{
1651 + u32 phymode;
1652 + u32 enableDacFifo = 0;
1653 +
1654 + if (AR_SREV_9285_10_OR_LATER(ah))
1655 + enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1656 + AR_PHY_FC_ENABLE_DAC_FIFO);
1657 +
1658 + phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1659 + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1660 +
1661 + if (IS_CHAN_HT40(chan)) {
1662 + phymode |= AR_PHY_FC_DYN2040_EN;
1663 +
1664 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1665 + (chan->chanmode == CHANNEL_G_HT40PLUS))
1666 + phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1667 +
1668 + }
1669 + REG_WRITE(ah, AR_PHY_TURBO, phymode);
1670 +
1671 + ath9k_hw_set11nmac2040(ah);
1672 +
1673 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1674 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1675 +}
1676 +
1677 +
1678 +static int ar5008_hw_process_ini(struct ath_hw *ah,
1679 + struct ath9k_channel *chan)
1680 +{
1681 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1682 + int i, regWrites = 0;
1683 + struct ieee80211_channel *channel = chan->chan;
1684 + u32 modesIndex, freqIndex;
1685 +
1686 + switch (chan->chanmode) {
1687 + case CHANNEL_A:
1688 + case CHANNEL_A_HT20:
1689 + modesIndex = 1;
1690 + freqIndex = 1;
1691 + break;
1692 + case CHANNEL_A_HT40PLUS:
1693 + case CHANNEL_A_HT40MINUS:
1694 + modesIndex = 2;
1695 + freqIndex = 1;
1696 + break;
1697 + case CHANNEL_G:
1698 + case CHANNEL_G_HT20:
1699 + case CHANNEL_B:
1700 + modesIndex = 4;
1701 + freqIndex = 2;
1702 + break;
1703 + case CHANNEL_G_HT40PLUS:
1704 + case CHANNEL_G_HT40MINUS:
1705 + modesIndex = 3;
1706 + freqIndex = 2;
1707 + break;
1708 +
1709 + default:
1710 + return -EINVAL;
1711 + }
1712 +
1713 + if (AR_SREV_9287_12_OR_LATER(ah)) {
1714 + /* Enable ASYNC FIFO */
1715 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1716 + AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1717 + REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1718 + REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1719 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1720 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1721 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1722 + }
1723 +
1724 + /*
1725 + * Set correct baseband to analog shift setting to
1726 + * access analog chips.
1727 + */
1728 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
1729 +
1730 + /* Write ADDAC shifts */
1731 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1732 + ah->eep_ops->set_addac(ah, chan);
1733 +
1734 + if (AR_SREV_5416_22_OR_LATER(ah)) {
1735 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1736 + } else {
1737 + struct ar5416IniArray temp;
1738 + u32 addacSize =
1739 + sizeof(u32) * ah->iniAddac.ia_rows *
1740 + ah->iniAddac.ia_columns;
1741 +
1742 + /* For AR5416 2.0/2.1 */
1743 + memcpy(ah->addac5416_21,
1744 + ah->iniAddac.ia_array, addacSize);
1745 +
1746 + /* override CLKDRV value at [row, column] = [31, 1] */
1747 + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1748 +
1749 + temp.ia_array = ah->addac5416_21;
1750 + temp.ia_columns = ah->iniAddac.ia_columns;
1751 + temp.ia_rows = ah->iniAddac.ia_rows;
1752 + REG_WRITE_ARRAY(&temp, 1, regWrites);
1753 + }
1754 +
1755 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1756 +
1757 + for (i = 0; i < ah->iniModes.ia_rows; i++) {
1758 + u32 reg = INI_RA(&ah->iniModes, i, 0);
1759 + u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1760 +
1761 + if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1762 + val &= ~AR_AN_TOP2_PWDCLKIND;
1763 +
1764 + REG_WRITE(ah, reg, val);
1765 +
1766 + if (reg >= 0x7800 && reg < 0x78a0
1767 + && ah->config.analog_shiftreg) {
1768 + udelay(100);
1769 + }
1770 +
1771 + DO_DELAY(regWrites);
1772 + }
1773 +
1774 + if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1775 + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1776 +
1777 + if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1778 + AR_SREV_9287_10_OR_LATER(ah))
1779 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1780 +
1781 + if (AR_SREV_9271_10(ah))
1782 + REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1783 + modesIndex, regWrites);
1784 +
1785 + /* Write common array parameters */
1786 + for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1787 + u32 reg = INI_RA(&ah->iniCommon, i, 0);
1788 + u32 val = INI_RA(&ah->iniCommon, i, 1);
1789 +
1790 + REG_WRITE(ah, reg, val);
1791 +
1792 + if (reg >= 0x7800 && reg < 0x78a0
1793 + && ah->config.analog_shiftreg) {
1794 + udelay(100);
1795 + }
1796 +
1797 + DO_DELAY(regWrites);
1798 + }
1799 +
1800 + if (AR_SREV_9271(ah)) {
1801 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1802 + REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1803 + modesIndex, regWrites);
1804 + else
1805 + REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1806 + modesIndex, regWrites);
1807 + }
1808 +
1809 + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1810 +
1811 + if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1812 + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1813 + regWrites);
1814 + }
1815 +
1816 + ar5008_hw_override_ini(ah, chan);
1817 + ar5008_hw_set_channel_regs(ah, chan);
1818 + ar5008_hw_init_chain_masks(ah);
1819 + ath9k_olc_init(ah);
1820 +
1821 + /* Set TX power */
1822 + ah->eep_ops->set_txpower(ah, chan,
1823 + ath9k_regd_get_ctl(regulatory, chan),
1824 + channel->max_antenna_gain * 2,
1825 + channel->max_power * 2,
1826 + min((u32) MAX_RATE_POWER,
1827 + (u32) regulatory->power_limit));
1828 +
1829 + /* Write analog registers */
1830 + if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1831 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1832 + "ar5416SetRfRegs failed\n");
1833 + return -EIO;
1834 + }
1835 +
1836 + return 0;
1837 +}
1838 +
1839 +static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1840 +{
1841 + u32 rfMode = 0;
1842 +
1843 + if (chan == NULL)
1844 + return;
1845 +
1846 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1847 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1848 +
1849 + if (!AR_SREV_9280_10_OR_LATER(ah))
1850 + rfMode |= (IS_CHAN_5GHZ(chan)) ?
1851 + AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1852 +
1853 + if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
1854 + && IS_CHAN_A_5MHZ_SPACED(chan))
1855 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1856 +
1857 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
1858 +}
1859 +
1860 +static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
1861 +{
1862 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1863 +}
1864 +
1865 +static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
1866 + struct ath9k_channel *chan)
1867 +{
1868 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
1869 + u32 clockMhzScaled = 0x64000000;
1870 + struct chan_centers centers;
1871 +
1872 + if (IS_CHAN_HALF_RATE(chan))
1873 + clockMhzScaled = clockMhzScaled >> 1;
1874 + else if (IS_CHAN_QUARTER_RATE(chan))
1875 + clockMhzScaled = clockMhzScaled >> 2;
1876 +
1877 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1878 + coef_scaled = clockMhzScaled / centers.synth_center;
1879 +
1880 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1881 + &ds_coef_exp);
1882 +
1883 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1884 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1885 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1886 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1887 +
1888 + coef_scaled = (9 * coef_scaled) / 10;
1889 +
1890 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1891 + &ds_coef_exp);
1892 +
1893 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1894 + AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1895 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1896 + AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1897 +}
1898 +
1899 +static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
1900 +{
1901 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1902 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1903 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1904 +}
1905 +
1906 +static void ar5008_hw_rfbus_done(struct ath_hw *ah)
1907 +{
1908 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1909 + if (IS_CHAN_B(ah->curchan))
1910 + synthDelay = (4 * synthDelay) / 22;
1911 + else
1912 + synthDelay /= 10;
1913 +
1914 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1915 +
1916 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1917 +}
1918 +
1919 +static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
1920 +{
1921 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1922 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1923 +
1924 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1925 + AR_GPIO_INPUT_MUX2_RFSILENT);
1926 +
1927 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1928 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1929 +}
1930 +
1931 +static void ar5008_restore_chainmask(struct ath_hw *ah)
1932 +{
1933 + int rx_chainmask = ah->rxchainmask;
1934 +
1935 + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1936 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1937 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1938 + }
1939 +}
1940 +
1941 +static void ar5008_set_diversity(struct ath_hw *ah, bool value)
1942 +{
1943 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1944 + if (value)
1945 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1946 + else
1947 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1948 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1949 +}
1950 +
1951 +static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1952 + struct ath9k_channel *chan)
1953 +{
1954 + if (chan && IS_CHAN_5GHZ(chan))
1955 + return 0x1450;
1956 + return 0x1458;
1957 +}
1958 +
1959 +static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1960 + struct ath9k_channel *chan)
1961 +{
1962 + u32 pll;
1963 +
1964 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1965 +
1966 + if (chan && IS_CHAN_HALF_RATE(chan))
1967 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1968 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1969 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1970 +
1971 + if (chan && IS_CHAN_5GHZ(chan))
1972 + pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1973 + else
1974 + pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1975 +
1976 + return pll;
1977 +}
1978 +
1979 +static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1980 + struct ath9k_channel *chan)
1981 +{
1982 + u32 pll;
1983 +
1984 + pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1985 +
1986 + if (chan && IS_CHAN_HALF_RATE(chan))
1987 + pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1988 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
1989 + pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1990 +
1991 + if (chan && IS_CHAN_5GHZ(chan))
1992 + pll |= SM(0xa, AR_RTC_PLL_DIV);
1993 + else
1994 + pll |= SM(0xb, AR_RTC_PLL_DIV);
1995 +
1996 + return pll;
1997 +}
1998 +
1999 +static bool ar5008_hw_ani_control(struct ath_hw *ah,
2000 + enum ath9k_ani_cmd cmd, int param)
2001 +{
2002 + struct ar5416AniState *aniState = ah->curani;
2003 + struct ath_common *common = ath9k_hw_common(ah);
2004 +
2005 + switch (cmd & ah->ani_function) {
2006 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2007 + u32 level = param;
2008 +
2009 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
2010 + ath_print(common, ATH_DBG_ANI,
2011 + "level out of range (%u > %u)\n",
2012 + level,
2013 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
2014 + return false;
2015 + }
2016 +
2017 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2018 + AR_PHY_DESIRED_SZ_TOT_DES,
2019 + ah->totalSizeDesired[level]);
2020 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2021 + AR_PHY_AGC_CTL1_COARSE_LOW,
2022 + ah->coarse_low[level]);
2023 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2024 + AR_PHY_AGC_CTL1_COARSE_HIGH,
2025 + ah->coarse_high[level]);
2026 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2027 + AR_PHY_FIND_SIG_FIRPWR,
2028 + ah->firpwr[level]);
2029 +
2030 + if (level > aniState->noiseImmunityLevel)
2031 + ah->stats.ast_ani_niup++;
2032 + else if (level < aniState->noiseImmunityLevel)
2033 + ah->stats.ast_ani_nidown++;
2034 + aniState->noiseImmunityLevel = level;
2035 + break;
2036 + }
2037 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2038 + const int m1ThreshLow[] = { 127, 50 };
2039 + const int m2ThreshLow[] = { 127, 40 };
2040 + const int m1Thresh[] = { 127, 0x4d };
2041 + const int m2Thresh[] = { 127, 0x40 };
2042 + const int m2CountThr[] = { 31, 16 };
2043 + const int m2CountThrLow[] = { 63, 48 };
2044 + u32 on = param ? 1 : 0;
2045 +
2046 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2047 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2048 + m1ThreshLow[on]);
2049 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2050 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2051 + m2ThreshLow[on]);
2052 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2053 + AR_PHY_SFCORR_M1_THRESH,
2054 + m1Thresh[on]);
2055 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2056 + AR_PHY_SFCORR_M2_THRESH,
2057 + m2Thresh[on]);
2058 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2059 + AR_PHY_SFCORR_M2COUNT_THR,
2060 + m2CountThr[on]);
2061 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2062 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2063 + m2CountThrLow[on]);
2064 +
2065 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2066 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2067 + m1ThreshLow[on]);
2068 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2069 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2070 + m2ThreshLow[on]);
2071 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2072 + AR_PHY_SFCORR_EXT_M1_THRESH,
2073 + m1Thresh[on]);
2074 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2075 + AR_PHY_SFCORR_EXT_M2_THRESH,
2076 + m2Thresh[on]);
2077 +
2078 + if (on)
2079 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2080 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2081 + else
2082 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2083 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2084 +
2085 + if (!on != aniState->ofdmWeakSigDetectOff) {
2086 + if (on)
2087 + ah->stats.ast_ani_ofdmon++;
2088 + else
2089 + ah->stats.ast_ani_ofdmoff++;
2090 + aniState->ofdmWeakSigDetectOff = !on;
2091 + }
2092 + break;
2093 + }
2094 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2095 + const int weakSigThrCck[] = { 8, 6 };
2096 + u32 high = param ? 1 : 0;
2097 +
2098 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2099 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2100 + weakSigThrCck[high]);
2101 + if (high != aniState->cckWeakSigThreshold) {
2102 + if (high)
2103 + ah->stats.ast_ani_cckhigh++;
2104 + else
2105 + ah->stats.ast_ani_ccklow++;
2106 + aniState->cckWeakSigThreshold = high;
2107 + }
2108 + break;
2109 + }
2110 + case ATH9K_ANI_FIRSTEP_LEVEL:{
2111 + const int firstep[] = { 0, 4, 8 };
2112 + u32 level = param;
2113 +
2114 + if (level >= ARRAY_SIZE(firstep)) {
2115 + ath_print(common, ATH_DBG_ANI,
2116 + "level out of range (%u > %u)\n",
2117 + level,
2118 + (unsigned) ARRAY_SIZE(firstep));
2119 + return false;
2120 + }
2121 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2122 + AR_PHY_FIND_SIG_FIRSTEP,
2123 + firstep[level]);
2124 + if (level > aniState->firstepLevel)
2125 + ah->stats.ast_ani_stepup++;
2126 + else if (level < aniState->firstepLevel)
2127 + ah->stats.ast_ani_stepdown++;
2128 + aniState->firstepLevel = level;
2129 + break;
2130 + }
2131 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2132 + const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
2133 + u32 level = param;
2134 +
2135 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
2136 + ath_print(common, ATH_DBG_ANI,
2137 + "level out of range (%u > %u)\n",
2138 + level,
2139 + (unsigned) ARRAY_SIZE(cycpwrThr1));
2140 + return false;
2141 + }
2142 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2143 + AR_PHY_TIMING5_CYCPWR_THR1,
2144 + cycpwrThr1[level]);
2145 + if (level > aniState->spurImmunityLevel)
2146 + ah->stats.ast_ani_spurup++;
2147 + else if (level < aniState->spurImmunityLevel)
2148 + ah->stats.ast_ani_spurdown++;
2149 + aniState->spurImmunityLevel = level;
2150 + break;
2151 + }
2152 + case ATH9K_ANI_PRESENT:
2153 + break;
2154 + default:
2155 + ath_print(common, ATH_DBG_ANI,
2156 + "invalid cmd %u\n", cmd);
2157 + return false;
2158 + }
2159 +
2160 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
2161 + ath_print(common, ATH_DBG_ANI,
2162 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2163 + "ofdmWeakSigDetectOff=%d\n",
2164 + aniState->noiseImmunityLevel,
2165 + aniState->spurImmunityLevel,
2166 + !aniState->ofdmWeakSigDetectOff);
2167 + ath_print(common, ATH_DBG_ANI,
2168 + "cckWeakSigThreshold=%d, "
2169 + "firstepLevel=%d, listenTime=%d\n",
2170 + aniState->cckWeakSigThreshold,
2171 + aniState->firstepLevel,
2172 + aniState->listenTime);
2173 + ath_print(common, ATH_DBG_ANI,
2174 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2175 + aniState->cycleCount,
2176 + aniState->ofdmPhyErrCount,
2177 + aniState->cckPhyErrCount);
2178 +
2179 + return true;
2180 +}
2181 +
2182 +static void ar5008_hw_do_getnf(struct ath_hw *ah,
2183 + int16_t nfarray[NUM_NF_READINGS])
2184 +{
2185 + struct ath_common *common = ath9k_hw_common(ah);
2186 + int16_t nf;
2187 +
2188 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
2189 + if (nf & 0x100)
2190 + nf = 0 - ((nf ^ 0x1ff) + 1);
2191 + ath_print(common, ATH_DBG_CALIBRATE,
2192 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
2193 + nfarray[0] = nf;
2194 +
2195 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
2196 + if (nf & 0x100)
2197 + nf = 0 - ((nf ^ 0x1ff) + 1);
2198 + ath_print(common, ATH_DBG_CALIBRATE,
2199 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
2200 + nfarray[1] = nf;
2201 +
2202 + nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
2203 + if (nf & 0x100)
2204 + nf = 0 - ((nf ^ 0x1ff) + 1);
2205 + ath_print(common, ATH_DBG_CALIBRATE,
2206 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
2207 + nfarray[2] = nf;
2208 +
2209 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
2210 + if (nf & 0x100)
2211 + nf = 0 - ((nf ^ 0x1ff) + 1);
2212 + ath_print(common, ATH_DBG_CALIBRATE,
2213 + "NF calibrated [ext] [chain 0] is %d\n", nf);
2214 + nfarray[3] = nf;
2215 +
2216 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
2217 + if (nf & 0x100)
2218 + nf = 0 - ((nf ^ 0x1ff) + 1);
2219 + ath_print(common, ATH_DBG_CALIBRATE,
2220 + "NF calibrated [ext] [chain 1] is %d\n", nf);
2221 + nfarray[4] = nf;
2222 +
2223 + nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
2224 + if (nf & 0x100)
2225 + nf = 0 - ((nf ^ 0x1ff) + 1);
2226 + ath_print(common, ATH_DBG_CALIBRATE,
2227 + "NF calibrated [ext] [chain 2] is %d\n", nf);
2228 + nfarray[5] = nf;
2229 +}
2230 +
2231 +static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
2232 +{
2233 + struct ath9k_nfcal_hist *h;
2234 + int i, j;
2235 + int32_t val;
2236 + const u32 ar5416_cca_regs[6] = {
2237 + AR_PHY_CCA,
2238 + AR_PHY_CH1_CCA,
2239 + AR_PHY_CH2_CCA,
2240 + AR_PHY_EXT_CCA,
2241 + AR_PHY_CH1_EXT_CCA,
2242 + AR_PHY_CH2_EXT_CCA
2243 + };
2244 + u8 chainmask, rx_chain_status;
2245 +
2246 + rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
2247 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2248 + chainmask = 0x9;
2249 + else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
2250 + if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
2251 + chainmask = 0x1B;
2252 + else
2253 + chainmask = 0x09;
2254 + } else {
2255 + if (rx_chain_status & 0x4)
2256 + chainmask = 0x3F;
2257 + else if (rx_chain_status & 0x2)
2258 + chainmask = 0x1B;
2259 + else
2260 + chainmask = 0x09;
2261 + }
2262 +
2263 + h = ah->nfCalHist;
2264 +
2265 + for (i = 0; i < NUM_NF_READINGS; i++) {
2266 + if (chainmask & (1 << i)) {
2267 + val = REG_READ(ah, ar5416_cca_regs[i]);
2268 + val &= 0xFFFFFE00;
2269 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
2270 + REG_WRITE(ah, ar5416_cca_regs[i], val);
2271 + }
2272 + }
2273 +
2274 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
2275 + AR_PHY_AGC_CONTROL_ENABLE_NF);
2276 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
2277 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2278 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2279 +
2280 + for (j = 0; j < 5; j++) {
2281 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
2282 + AR_PHY_AGC_CONTROL_NF) == 0)
2283 + break;
2284 + udelay(50);
2285 + }
2286 +
2287 + for (i = 0; i < NUM_NF_READINGS; i++) {
2288 + if (chainmask & (1 << i)) {
2289 + val = REG_READ(ah, ar5416_cca_regs[i]);
2290 + val &= 0xFFFFFE00;
2291 + val |= (((u32) (-50) << 1) & 0x1ff);
2292 + REG_WRITE(ah, ar5416_cca_regs[i], val);
2293 + }
2294 + }
2295 +}
2296 +
2297 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
2298 +{
2299 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2300 +
2301 + priv_ops->rf_set_freq = ar5008_hw_set_channel;
2302 + priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
2303 +
2304 + priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
2305 + priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
2306 + priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
2307 + priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
2308 + priv_ops->init_bb = ar5008_hw_init_bb;
2309 + priv_ops->process_ini = ar5008_hw_process_ini;
2310 + priv_ops->set_rfmode = ar5008_hw_set_rfmode;
2311 + priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
2312 + priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
2313 + priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2314 + priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2315 + priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
2316 + priv_ops->restore_chainmask = ar5008_restore_chainmask;
2317 + priv_ops->set_diversity = ar5008_set_diversity;
2318 + priv_ops->ani_control = ar5008_hw_ani_control;
2319 + priv_ops->do_getnf = ar5008_hw_do_getnf;
2320 + priv_ops->loadnf = ar5008_hw_loadnf;
2321 +
2322 + if (AR_SREV_9100(ah))
2323 + priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2324 + else if (AR_SREV_9160_10_OR_LATER(ah))
2325 + priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2326 + else
2327 + priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2328 +}
2329 --- /dev/null
2330 +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2331 @@ -0,0 +1,1254 @@
2332 +
2333 +static const u32 ar5416Common_9100[][2] = {
2334 + { 0x0000000c, 0x00000000 },
2335 + { 0x00000030, 0x00020015 },
2336 + { 0x00000034, 0x00000005 },
2337 + { 0x00000040, 0x00000000 },
2338 + { 0x00000044, 0x00000008 },
2339 + { 0x00000048, 0x00000008 },
2340 + { 0x0000004c, 0x00000010 },
2341 + { 0x00000050, 0x00000000 },
2342 + { 0x00000054, 0x0000001f },
2343 + { 0x00000800, 0x00000000 },
2344 + { 0x00000804, 0x00000000 },
2345 + { 0x00000808, 0x00000000 },
2346 + { 0x0000080c, 0x00000000 },
2347 + { 0x00000810, 0x00000000 },
2348 + { 0x00000814, 0x00000000 },
2349 + { 0x00000818, 0x00000000 },
2350 + { 0x0000081c, 0x00000000 },
2351 + { 0x00000820, 0x00000000 },
2352 + { 0x00000824, 0x00000000 },
2353 + { 0x00001040, 0x002ffc0f },
2354 + { 0x00001044, 0x002ffc0f },
2355 + { 0x00001048, 0x002ffc0f },
2356 + { 0x0000104c, 0x002ffc0f },
2357 + { 0x00001050, 0x002ffc0f },
2358 + { 0x00001054, 0x002ffc0f },
2359 + { 0x00001058, 0x002ffc0f },
2360 + { 0x0000105c, 0x002ffc0f },
2361 + { 0x00001060, 0x002ffc0f },
2362 + { 0x00001064, 0x002ffc0f },
2363 + { 0x00001230, 0x00000000 },
2364 + { 0x00001270, 0x00000000 },
2365 + { 0x00001038, 0x00000000 },
2366 + { 0x00001078, 0x00000000 },
2367 + { 0x000010b8, 0x00000000 },
2368 + { 0x000010f8, 0x00000000 },
2369 + { 0x00001138, 0x00000000 },
2370 + { 0x00001178, 0x00000000 },
2371 + { 0x000011b8, 0x00000000 },
2372 + { 0x000011f8, 0x00000000 },
2373 + { 0x00001238, 0x00000000 },
2374 + { 0x00001278, 0x00000000 },
2375 + { 0x000012b8, 0x00000000 },
2376 + { 0x000012f8, 0x00000000 },
2377 + { 0x00001338, 0x00000000 },
2378 + { 0x00001378, 0x00000000 },
2379 + { 0x000013b8, 0x00000000 },
2380 + { 0x000013f8, 0x00000000 },
2381 + { 0x00001438, 0x00000000 },
2382 + { 0x00001478, 0x00000000 },
2383 + { 0x000014b8, 0x00000000 },
2384 + { 0x000014f8, 0x00000000 },
2385 + { 0x00001538, 0x00000000 },
2386 + { 0x00001578, 0x00000000 },
2387 + { 0x000015b8, 0x00000000 },
2388 + { 0x000015f8, 0x00000000 },
2389 + { 0x00001638, 0x00000000 },
2390 + { 0x00001678, 0x00000000 },
2391 + { 0x000016b8, 0x00000000 },
2392 + { 0x000016f8, 0x00000000 },
2393 + { 0x00001738, 0x00000000 },
2394 + { 0x00001778, 0x00000000 },
2395 + { 0x000017b8, 0x00000000 },
2396 + { 0x000017f8, 0x00000000 },
2397 + { 0x0000103c, 0x00000000 },
2398 + { 0x0000107c, 0x00000000 },
2399 + { 0x000010bc, 0x00000000 },
2400 + { 0x000010fc, 0x00000000 },
2401 + { 0x0000113c, 0x00000000 },
2402 + { 0x0000117c, 0x00000000 },
2403 + { 0x000011bc, 0x00000000 },
2404 + { 0x000011fc, 0x00000000 },
2405 + { 0x0000123c, 0x00000000 },
2406 + { 0x0000127c, 0x00000000 },
2407 + { 0x000012bc, 0x00000000 },
2408 + { 0x000012fc, 0x00000000 },
2409 + { 0x0000133c, 0x00000000 },
2410 + { 0x0000137c, 0x00000000 },
2411 + { 0x000013bc, 0x00000000 },
2412 + { 0x000013fc, 0x00000000 },
2413 + { 0x0000143c, 0x00000000 },
2414 + { 0x0000147c, 0x00000000 },
2415 + { 0x00020010, 0x00000003 },
2416 + { 0x00020038, 0x000004c2 },
2417 + { 0x00008004, 0x00000000 },
2418 + { 0x00008008, 0x00000000 },
2419 + { 0x0000800c, 0x00000000 },
2420 + { 0x00008018, 0x00000700 },
2421 + { 0x00008020, 0x00000000 },
2422 + { 0x00008038, 0x00000000 },
2423 + { 0x0000803c, 0x00000000 },
2424 + { 0x00008048, 0x40000000 },
2425 + { 0x00008054, 0x00004000 },
2426 + { 0x00008058, 0x00000000 },
2427 + { 0x0000805c, 0x000fc78f },
2428 + { 0x00008060, 0x0000000f },
2429 + { 0x00008064, 0x00000000 },
2430 + { 0x000080c0, 0x2a82301a },
2431 + { 0x000080c4, 0x05dc01e0 },
2432 + { 0x000080c8, 0x1f402710 },
2433 + { 0x000080cc, 0x01f40000 },
2434 + { 0x000080d0, 0x00001e00 },
2435 + { 0x000080d4, 0x00000000 },
2436 + { 0x000080d8, 0x00400000 },
2437 + { 0x000080e0, 0xffffffff },
2438 + { 0x000080e4, 0x0000ffff },
2439 + { 0x000080e8, 0x003f3f3f },
2440 + { 0x000080ec, 0x00000000 },
2441 + { 0x000080f0, 0x00000000 },
2442 + { 0x000080f4, 0x00000000 },
2443 + { 0x000080f8, 0x00000000 },
2444 + { 0x000080fc, 0x00020000 },
2445 + { 0x00008100, 0x00020000 },
2446 + { 0x00008104, 0x00000001 },
2447 + { 0x00008108, 0x00000052 },
2448 + { 0x0000810c, 0x00000000 },
2449 + { 0x00008110, 0x00000168 },
2450 + { 0x00008118, 0x000100aa },
2451 + { 0x0000811c, 0x00003210 },
2452 + { 0x00008120, 0x08f04800 },
2453 + { 0x00008124, 0x00000000 },
2454 + { 0x00008128, 0x00000000 },
2455 + { 0x0000812c, 0x00000000 },
2456 + { 0x00008130, 0x00000000 },
2457 + { 0x00008134, 0x00000000 },
2458 + { 0x00008138, 0x00000000 },
2459 + { 0x0000813c, 0x00000000 },
2460 + { 0x00008144, 0x00000000 },
2461 + { 0x00008168, 0x00000000 },
2462 + { 0x0000816c, 0x00000000 },
2463 + { 0x00008170, 0x32143320 },
2464 + { 0x00008174, 0xfaa4fa50 },
2465 + { 0x00008178, 0x00000100 },
2466 + { 0x0000817c, 0x00000000 },
2467 + { 0x000081c4, 0x00000000 },
2468 + { 0x000081d0, 0x00003210 },
2469 + { 0x000081ec, 0x00000000 },
2470 + { 0x000081f0, 0x00000000 },
2471 + { 0x000081f4, 0x00000000 },
2472 + { 0x000081f8, 0x00000000 },
2473 + { 0x000081fc, 0x00000000 },
2474 + { 0x00008200, 0x00000000 },
2475 + { 0x00008204, 0x00000000 },
2476 + { 0x00008208, 0x00000000 },
2477 + { 0x0000820c, 0x00000000 },
2478 + { 0x00008210, 0x00000000 },
2479 + { 0x00008214, 0x00000000 },
2480 + { 0x00008218, 0x00000000 },
2481 + { 0x0000821c, 0x00000000 },
2482 + { 0x00008220, 0x00000000 },
2483 + { 0x00008224, 0x00000000 },
2484 + { 0x00008228, 0x00000000 },
2485 + { 0x0000822c, 0x00000000 },
2486 + { 0x00008230, 0x00000000 },
2487 + { 0x00008234, 0x00000000 },
2488 + { 0x00008238, 0x00000000 },
2489 + { 0x0000823c, 0x00000000 },
2490 + { 0x00008240, 0x00100000 },
2491 + { 0x00008244, 0x0010f400 },
2492 + { 0x00008248, 0x00000100 },
2493 + { 0x0000824c, 0x0001e800 },
2494 + { 0x00008250, 0x00000000 },
2495 + { 0x00008254, 0x00000000 },
2496 + { 0x00008258, 0x00000000 },
2497 + { 0x0000825c, 0x400000ff },
2498 + { 0x00008260, 0x00080922 },
2499 + { 0x00008270, 0x00000000 },
2500 + { 0x00008274, 0x40000000 },
2501 + { 0x00008278, 0x003e4180 },
2502 + { 0x0000827c, 0x00000000 },
2503 + { 0x00008284, 0x0000002c },
2504 + { 0x00008288, 0x0000002c },
2505 + { 0x0000828c, 0x00000000 },
2506 + { 0x00008294, 0x00000000 },
2507 + { 0x00008298, 0x00000000 },
2508 + { 0x00008300, 0x00000000 },
2509 + { 0x00008304, 0x00000000 },
2510 + { 0x00008308, 0x00000000 },
2511 + { 0x0000830c, 0x00000000 },
2512 + { 0x00008310, 0x00000000 },
2513 + { 0x00008314, 0x00000000 },
2514 + { 0x00008318, 0x00000000 },
2515 + { 0x00008328, 0x00000000 },
2516 + { 0x0000832c, 0x00000007 },
2517 + { 0x00008330, 0x00000302 },
2518 + { 0x00008334, 0x00000e00 },
2519 + { 0x00008338, 0x00000000 },
2520 + { 0x0000833c, 0x00000000 },
2521 + { 0x00008340, 0x000107ff },
2522 + { 0x00009808, 0x00000000 },
2523 + { 0x0000980c, 0xad848e19 },
2524 + { 0x00009810, 0x7d14e000 },
2525 + { 0x00009814, 0x9c0a9f6b },
2526 + { 0x0000981c, 0x00000000 },
2527 + { 0x0000982c, 0x0000a000 },
2528 + { 0x00009830, 0x00000000 },
2529 + { 0x0000983c, 0x00200400 },
2530 + { 0x00009840, 0x206a01ae },
2531 + { 0x0000984c, 0x1284233c },
2532 + { 0x00009854, 0x00000859 },
2533 + { 0x00009900, 0x00000000 },
2534 + { 0x00009904, 0x00000000 },
2535 + { 0x00009908, 0x00000000 },
2536 + { 0x0000990c, 0x00000000 },
2537 + { 0x0000991c, 0x10000fff },
2538 + { 0x00009920, 0x05100000 },
2539 + { 0x0000a920, 0x05100000 },
2540 + { 0x0000b920, 0x05100000 },
2541 + { 0x00009928, 0x00000001 },
2542 + { 0x0000992c, 0x00000004 },
2543 + { 0x00009934, 0x1e1f2022 },
2544 + { 0x00009938, 0x0a0b0c0d },
2545 + { 0x0000993c, 0x00000000 },
2546 + { 0x00009948, 0x9280b212 },
2547 + { 0x0000994c, 0x00020028 },
2548 + { 0x0000c95c, 0x004b6a8e },
2549 + { 0x0000c968, 0x000003ce },
2550 + { 0x00009970, 0x190fb515 },
2551 + { 0x00009974, 0x00000000 },
2552 + { 0x00009978, 0x00000001 },
2553 + { 0x0000997c, 0x00000000 },
2554 + { 0x00009980, 0x00000000 },
2555 + { 0x00009984, 0x00000000 },
2556 + { 0x00009988, 0x00000000 },
2557 + { 0x0000998c, 0x00000000 },
2558 + { 0x00009990, 0x00000000 },
2559 + { 0x00009994, 0x00000000 },
2560 + { 0x00009998, 0x00000000 },
2561 + { 0x0000999c, 0x00000000 },
2562 + { 0x000099a0, 0x00000000 },
2563 + { 0x000099a4, 0x00000001 },
2564 + { 0x000099a8, 0x201fff00 },
2565 + { 0x000099ac, 0x006f0000 },
2566 + { 0x000099b0, 0x03051000 },
2567 + { 0x000099dc, 0x00000000 },
2568 + { 0x000099e0, 0x00000200 },
2569 + { 0x000099e4, 0xaaaaaaaa },
2570 + { 0x000099e8, 0x3c466478 },
2571 + { 0x000099ec, 0x0cc80caa },
2572 + { 0x000099fc, 0x00001042 },
2573 + { 0x00009b00, 0x00000000 },
2574 + { 0x00009b04, 0x00000001 },
2575 + { 0x00009b08, 0x00000002 },
2576 + { 0x00009b0c, 0x00000003 },
2577 + { 0x00009b10, 0x00000004 },
2578 + { 0x00009b14, 0x00000005 },
2579 + { 0x00009b18, 0x00000008 },
2580 + { 0x00009b1c, 0x00000009 },
2581 + { 0x00009b20, 0x0000000a },
2582 + { 0x00009b24, 0x0000000b },
2583 + { 0x00009b28, 0x0000000c },
2584 + { 0x00009b2c, 0x0000000d },
2585 + { 0x00009b30, 0x00000010 },
2586 + { 0x00009b34, 0x00000011 },
2587 + { 0x00009b38, 0x00000012 },
2588 + { 0x00009b3c, 0x00000013 },
2589 + { 0x00009b40, 0x00000014 },
2590 + { 0x00009b44, 0x00000015 },
2591 + { 0x00009b48, 0x00000018 },
2592 + { 0x00009b4c, 0x00000019 },
2593 + { 0x00009b50, 0x0000001a },
2594 + { 0x00009b54, 0x0000001b },
2595 + { 0x00009b58, 0x0000001c },
2596 + { 0x00009b5c, 0x0000001d },
2597 + { 0x00009b60, 0x00000020 },
2598 + { 0x00009b64, 0x00000021 },
2599 + { 0x00009b68, 0x00000022 },
2600 + { 0x00009b6c, 0x00000023 },
2601 + { 0x00009b70, 0x00000024 },
2602 + { 0x00009b74, 0x00000025 },
2603 + { 0x00009b78, 0x00000028 },
2604 + { 0x00009b7c, 0x00000029 },
2605 + { 0x00009b80, 0x0000002a },
2606 + { 0x00009b84, 0x0000002b },
2607 + { 0x00009b88, 0x0000002c },
2608 + { 0x00009b8c, 0x0000002d },
2609 + { 0x00009b90, 0x00000030 },
2610 + { 0x00009b94, 0x00000031 },
2611 + { 0x00009b98, 0x00000032 },
2612 + { 0x00009b9c, 0x00000033 },
2613 + { 0x00009ba0, 0x00000034 },
2614 + { 0x00009ba4, 0x00000035 },
2615 + { 0x00009ba8, 0x00000035 },
2616 + { 0x00009bac, 0x00000035 },
2617 + { 0x00009bb0, 0x00000035 },
2618 + { 0x00009bb4, 0x00000035 },
2619 + { 0x00009bb8, 0x00000035 },
2620 + { 0x00009bbc, 0x00000035 },
2621 + { 0x00009bc0, 0x00000035 },
2622 + { 0x00009bc4, 0x00000035 },
2623 + { 0x00009bc8, 0x00000035 },
2624 + { 0x00009bcc, 0x00000035 },
2625 + { 0x00009bd0, 0x00000035 },
2626 + { 0x00009bd4, 0x00000035 },
2627 + { 0x00009bd8, 0x00000035 },
2628 + { 0x00009bdc, 0x00000035 },
2629 + { 0x00009be0, 0x00000035 },
2630 + { 0x00009be4, 0x00000035 },
2631 + { 0x00009be8, 0x00000035 },
2632 + { 0x00009bec, 0x00000035 },
2633 + { 0x00009bf0, 0x00000035 },
2634 + { 0x00009bf4, 0x00000035 },
2635 + { 0x00009bf8, 0x00000010 },
2636 + { 0x00009bfc, 0x0000001a },
2637 + { 0x0000a210, 0x40806333 },
2638 + { 0x0000a214, 0x00106c10 },
2639 + { 0x0000a218, 0x009c4060 },
2640 + { 0x0000a220, 0x018830c6 },
2641 + { 0x0000a224, 0x00000400 },
2642 + { 0x0000a228, 0x001a0bb5 },
2643 + { 0x0000a22c, 0x00000000 },
2644 + { 0x0000a234, 0x20202020 },
2645 + { 0x0000a238, 0x20202020 },
2646 + { 0x0000a23c, 0x13c889ae },
2647 + { 0x0000a240, 0x38490a20 },
2648 + { 0x0000a244, 0x00007bb6 },
2649 + { 0x0000a248, 0x0fff3ffc },
2650 + { 0x0000a24c, 0x00000001 },
2651 + { 0x0000a250, 0x0000a000 },
2652 + { 0x0000a254, 0x00000000 },
2653 + { 0x0000a258, 0x0cc75380 },
2654 + { 0x0000a25c, 0x0f0f0f01 },
2655 + { 0x0000a260, 0xdfa91f01 },
2656 + { 0x0000a268, 0x00000001 },
2657 + { 0x0000a26c, 0x0ebae9c6 },
2658 + { 0x0000b26c, 0x0ebae9c6 },
2659 + { 0x0000c26c, 0x0ebae9c6 },
2660 + { 0x0000d270, 0x00820820 },
2661 + { 0x0000a278, 0x1ce739ce },
2662 + { 0x0000a27c, 0x050701ce },
2663 + { 0x0000a338, 0x00000000 },
2664 + { 0x0000a33c, 0x00000000 },
2665 + { 0x0000a340, 0x00000000 },
2666 + { 0x0000a344, 0x00000000 },
2667 + { 0x0000a348, 0x3fffffff },
2668 + { 0x0000a34c, 0x3fffffff },
2669 + { 0x0000a350, 0x3fffffff },
2670 + { 0x0000a354, 0x0003ffff },
2671 + { 0x0000a358, 0x79a8aa33 },
2672 + { 0x0000d35c, 0x07ffffef },
2673 + { 0x0000d360, 0x0fffffe7 },
2674 + { 0x0000d364, 0x17ffffe5 },
2675 + { 0x0000d368, 0x1fffffe4 },
2676 + { 0x0000d36c, 0x37ffffe3 },
2677 + { 0x0000d370, 0x3fffffe3 },
2678 + { 0x0000d374, 0x57ffffe3 },
2679 + { 0x0000d378, 0x5fffffe2 },
2680 + { 0x0000d37c, 0x7fffffe2 },
2681 + { 0x0000d380, 0x7f3c7bba },
2682 + { 0x0000d384, 0xf3307ff0 },
2683 + { 0x0000a388, 0x0c000000 },
2684 + { 0x0000a38c, 0x20202020 },
2685 + { 0x0000a390, 0x20202020 },
2686 + { 0x0000a394, 0x1ce739ce },
2687 + { 0x0000a398, 0x000001ce },
2688 + { 0x0000a39c, 0x00000001 },
2689 + { 0x0000a3a0, 0x00000000 },
2690 + { 0x0000a3a4, 0x00000000 },
2691 + { 0x0000a3a8, 0x00000000 },
2692 + { 0x0000a3ac, 0x00000000 },
2693 + { 0x0000a3b0, 0x00000000 },
2694 + { 0x0000a3b4, 0x00000000 },
2695 + { 0x0000a3b8, 0x00000000 },
2696 + { 0x0000a3bc, 0x00000000 },
2697 + { 0x0000a3c0, 0x00000000 },
2698 + { 0x0000a3c4, 0x00000000 },
2699 + { 0x0000a3c8, 0x00000246 },
2700 + { 0x0000a3cc, 0x20202020 },
2701 + { 0x0000a3d0, 0x20202020 },
2702 + { 0x0000a3d4, 0x20202020 },
2703 + { 0x0000a3dc, 0x1ce739ce },
2704 + { 0x0000a3e0, 0x000001ce },
2705 +};
2706 +
2707 +static const u32 ar5416Bank0_9100[][2] = {
2708 + { 0x000098b0, 0x1e5795e5 },
2709 + { 0x000098e0, 0x02008020 },
2710 +};
2711 +
2712 +static const u32 ar5416BB_RfGain_9100[][3] = {
2713 + { 0x00009a00, 0x00000000, 0x00000000 },
2714 + { 0x00009a04, 0x00000040, 0x00000040 },
2715 + { 0x00009a08, 0x00000080, 0x00000080 },
2716 + { 0x00009a0c, 0x000001a1, 0x00000141 },
2717 + { 0x00009a10, 0x000001e1, 0x00000181 },
2718 + { 0x00009a14, 0x00000021, 0x000001c1 },
2719 + { 0x00009a18, 0x00000061, 0x00000001 },
2720 + { 0x00009a1c, 0x00000168, 0x00000041 },
2721 + { 0x00009a20, 0x000001a8, 0x000001a8 },
2722 + { 0x00009a24, 0x000001e8, 0x000001e8 },
2723 + { 0x00009a28, 0x00000028, 0x00000028 },
2724 + { 0x00009a2c, 0x00000068, 0x00000068 },
2725 + { 0x00009a30, 0x00000189, 0x000000a8 },
2726 + { 0x00009a34, 0x000001c9, 0x00000169 },
2727 + { 0x00009a38, 0x00000009, 0x000001a9 },
2728 + { 0x00009a3c, 0x00000049, 0x000001e9 },
2729 + { 0x00009a40, 0x00000089, 0x00000029 },
2730 + { 0x00009a44, 0x00000170, 0x00000069 },
2731 + { 0x00009a48, 0x000001b0, 0x00000190 },
2732 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
2733 + { 0x00009a50, 0x00000030, 0x00000010 },
2734 + { 0x00009a54, 0x00000070, 0x00000050 },
2735 + { 0x00009a58, 0x00000191, 0x00000090 },
2736 + { 0x00009a5c, 0x000001d1, 0x00000151 },
2737 + { 0x00009a60, 0x00000011, 0x00000191 },
2738 + { 0x00009a64, 0x00000051, 0x000001d1 },
2739 + { 0x00009a68, 0x00000091, 0x00000011 },
2740 + { 0x00009a6c, 0x000001b8, 0x00000051 },
2741 + { 0x00009a70, 0x000001f8, 0x00000198 },
2742 + { 0x00009a74, 0x00000038, 0x000001d8 },
2743 + { 0x00009a78, 0x00000078, 0x00000018 },
2744 + { 0x00009a7c, 0x00000199, 0x00000058 },
2745 + { 0x00009a80, 0x000001d9, 0x00000098 },
2746 + { 0x00009a84, 0x00000019, 0x00000159 },
2747 + { 0x00009a88, 0x00000059, 0x00000199 },
2748 + { 0x00009a8c, 0x00000099, 0x000001d9 },
2749 + { 0x00009a90, 0x000000d9, 0x00000019 },
2750 + { 0x00009a94, 0x000000f9, 0x00000059 },
2751 + { 0x00009a98, 0x000000f9, 0x00000099 },
2752 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
2753 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
2754 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
2755 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
2756 + { 0x00009aac, 0x000000f9, 0x000000f9 },
2757 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
2758 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
2759 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
2760 + { 0x00009abc, 0x000000f9, 0x000000f9 },
2761 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
2762 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
2763 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
2764 + { 0x00009acc, 0x000000f9, 0x000000f9 },
2765 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
2766 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
2767 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
2768 + { 0x00009adc, 0x000000f9, 0x000000f9 },
2769 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
2770 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
2771 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
2772 + { 0x00009aec, 0x000000f9, 0x000000f9 },
2773 + { 0x00009af0, 0x000000f9, 0x000000f9 },
2774 + { 0x00009af4, 0x000000f9, 0x000000f9 },
2775 + { 0x00009af8, 0x000000f9, 0x000000f9 },
2776 + { 0x00009afc, 0x000000f9, 0x000000f9 },
2777 +};
2778 +
2779 +static const u32 ar5416Bank1_9100[][2] = {
2780 + { 0x000098b0, 0x02108421},
2781 + { 0x000098ec, 0x00000008},
2782 +};
2783 +
2784 +static const u32 ar5416Bank2_9100[][2] = {
2785 + { 0x000098b0, 0x0e73ff17},
2786 + { 0x000098e0, 0x00000420},
2787 +};
2788 +
2789 +static const u32 ar5416Bank3_9100[][3] = {
2790 + { 0x000098f0, 0x01400018, 0x01c00018 },
2791 +};
2792 +
2793 +static const u32 ar5416Bank6_9100[][3] = {
2794 +
2795 + { 0x0000989c, 0x00000000, 0x00000000 },
2796 + { 0x0000989c, 0x00000000, 0x00000000 },
2797 + { 0x0000989c, 0x00000000, 0x00000000 },
2798 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2799 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2800 + { 0x0000989c, 0x00120000, 0x00120000 },
2801 + { 0x0000989c, 0x00620000, 0x00620000 },
2802 + { 0x0000989c, 0x00020000, 0x00020000 },
2803 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2804 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2805 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2806 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2807 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2808 + { 0x0000989c, 0x00870000, 0x00870000 },
2809 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2810 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2811 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2812 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2813 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2814 + { 0x0000989c, 0x00110000, 0x00110000 },
2815 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2816 + { 0x0000989c, 0x004210a2, 0x004210a2 },
2817 + { 0x0000989c, 0x0014000f, 0x0014000f },
2818 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2819 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2820 + { 0x0000989c, 0x00440016, 0x00440016 },
2821 + { 0x0000989c, 0x00410040, 0x00410040 },
2822 + { 0x0000989c, 0x000180d6, 0x000180d6 },
2823 + { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
2824 + { 0x0000989c, 0x000000b1, 0x000000b1 },
2825 + { 0x0000989c, 0x00002000, 0x00002000 },
2826 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2827 + { 0x000098d0, 0x0000000f, 0x0010000f },
2828 +};
2829 +
2830 +
2831 +static const u32 ar5416Bank6TPC_9100[][3] = {
2832 +
2833 + { 0x0000989c, 0x00000000, 0x00000000 },
2834 + { 0x0000989c, 0x00000000, 0x00000000 },
2835 + { 0x0000989c, 0x00000000, 0x00000000 },
2836 + { 0x0000989c, 0x00e00000, 0x00e00000 },
2837 + { 0x0000989c, 0x005e0000, 0x005e0000 },
2838 + { 0x0000989c, 0x00120000, 0x00120000 },
2839 + { 0x0000989c, 0x00620000, 0x00620000 },
2840 + { 0x0000989c, 0x00020000, 0x00020000 },
2841 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2842 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2843 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2844 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
2845 + { 0x0000989c, 0x005f0000, 0x005f0000 },
2846 + { 0x0000989c, 0x00870000, 0x00870000 },
2847 + { 0x0000989c, 0x00f90000, 0x00f90000 },
2848 + { 0x0000989c, 0x007b0000, 0x007b0000 },
2849 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
2850 + { 0x0000989c, 0x00f50000, 0x00f50000 },
2851 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
2852 + { 0x0000989c, 0x00110000, 0x00110000 },
2853 + { 0x0000989c, 0x006100a8, 0x006100a8 },
2854 + { 0x0000989c, 0x00423022, 0x00423022 },
2855 + { 0x0000989c, 0x2014008f, 0x2014008f },
2856 + { 0x0000989c, 0x00c40002, 0x00c40002 },
2857 + { 0x0000989c, 0x003000f2, 0x003000f2 },
2858 + { 0x0000989c, 0x00440016, 0x00440016 },
2859 + { 0x0000989c, 0x00410040, 0x00410040 },
2860 + { 0x0000989c, 0x0001805e, 0x0001805e },
2861 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
2862 + { 0x0000989c, 0x000000e1, 0x000000e1 },
2863 + { 0x0000989c, 0x00007080, 0x00007080 },
2864 + { 0x0000989c, 0x000000d4, 0x000000d4 },
2865 + { 0x000098d0, 0x0000000f, 0x0010000f },
2866 +};
2867 +
2868 +static const u32 ar5416Bank7_9100[][2] = {
2869 + { 0x0000989c, 0x00000500 },
2870 + { 0x0000989c, 0x00000800 },
2871 + { 0x000098cc, 0x0000000e },
2872 +};
2873 +
2874 +static const u32 ar5416Addac_9100[][2] = {
2875 + {0x0000989c, 0x00000000 },
2876 + {0x0000989c, 0x00000000 },
2877 + {0x0000989c, 0x00000000 },
2878 + {0x0000989c, 0x00000000 },
2879 + {0x0000989c, 0x00000000 },
2880 + {0x0000989c, 0x00000000 },
2881 + {0x0000989c, 0x00000000 },
2882 + {0x0000989c, 0x00000010 },
2883 + {0x0000989c, 0x00000000 },
2884 + {0x0000989c, 0x00000000 },
2885 + {0x0000989c, 0x00000000 },
2886 + {0x0000989c, 0x00000000 },
2887 + {0x0000989c, 0x00000000 },
2888 + {0x0000989c, 0x00000000 },
2889 + {0x0000989c, 0x00000000 },
2890 + {0x0000989c, 0x00000000 },
2891 + {0x0000989c, 0x00000000 },
2892 + {0x0000989c, 0x00000000 },
2893 + {0x0000989c, 0x00000000 },
2894 + {0x0000989c, 0x00000000 },
2895 + {0x0000989c, 0x00000000 },
2896 + {0x0000989c, 0x000000c0 },
2897 + {0x0000989c, 0x00000015 },
2898 + {0x0000989c, 0x00000000 },
2899 + {0x0000989c, 0x00000000 },
2900 + {0x0000989c, 0x00000000 },
2901 + {0x0000989c, 0x00000000 },
2902 + {0x0000989c, 0x00000000 },
2903 + {0x0000989c, 0x00000000 },
2904 + {0x0000989c, 0x00000000 },
2905 + {0x0000989c, 0x00000000 },
2906 + {0x000098cc, 0x00000000 },
2907 +};
2908 +
2909 +static const u32 ar5416Modes_9160[][6] = {
2910 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
2911 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
2912 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
2913 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
2914 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
2915 + { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
2916 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
2917 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
2918 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2919 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
2920 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2921 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
2922 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
2923 + { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2924 + { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2925 + { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
2926 + { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
2927 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
2928 + { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
2929 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
2930 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
2931 + { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
2932 + { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
2933 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
2934 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
2935 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
2936 + { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
2937 + { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2938 + { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2939 + { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
2940 + { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
2941 + { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
2942 + { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
2943 + { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
2944 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
2945 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
2946 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
2947 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
2948 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2949 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2950 + { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
2951 + { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
2952 + { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2953 + { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2954 + { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
2955 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
2956 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
2957 + { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
2958 + { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
2959 + { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
2960 + { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
2961 + { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
2962 + { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
2963 + { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
2964 + { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
2965 + { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
2966 + { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
2967 + { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
2968 + { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
2969 + { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2970 + { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2971 + { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2972 +};
2973 +
2974 +static const u32 ar5416Common_9160[][2] = {
2975 + { 0x0000000c, 0x00000000 },
2976 + { 0x00000030, 0x00020015 },
2977 + { 0x00000034, 0x00000005 },
2978 + { 0x00000040, 0x00000000 },
2979 + { 0x00000044, 0x00000008 },
2980 + { 0x00000048, 0x00000008 },
2981 + { 0x0000004c, 0x00000010 },
2982 + { 0x00000050, 0x00000000 },
2983 + { 0x00000054, 0x0000001f },
2984 + { 0x00000800, 0x00000000 },
2985 + { 0x00000804, 0x00000000 },
2986 + { 0x00000808, 0x00000000 },
2987 + { 0x0000080c, 0x00000000 },
2988 + { 0x00000810, 0x00000000 },
2989 + { 0x00000814, 0x00000000 },
2990 + { 0x00000818, 0x00000000 },
2991 + { 0x0000081c, 0x00000000 },
2992 + { 0x00000820, 0x00000000 },
2993 + { 0x00000824, 0x00000000 },
2994 + { 0x00001040, 0x002ffc0f },
2995 + { 0x00001044, 0x002ffc0f },
2996 + { 0x00001048, 0x002ffc0f },
2997 + { 0x0000104c, 0x002ffc0f },
2998 + { 0x00001050, 0x002ffc0f },
2999 + { 0x00001054, 0x002ffc0f },
3000 + { 0x00001058, 0x002ffc0f },
3001 + { 0x0000105c, 0x002ffc0f },
3002 + { 0x00001060, 0x002ffc0f },
3003 + { 0x00001064, 0x002ffc0f },
3004 + { 0x00001230, 0x00000000 },
3005 + { 0x00001270, 0x00000000 },
3006 + { 0x00001038, 0x00000000 },
3007 + { 0x00001078, 0x00000000 },
3008 + { 0x000010b8, 0x00000000 },
3009 + { 0x000010f8, 0x00000000 },
3010 + { 0x00001138, 0x00000000 },
3011 + { 0x00001178, 0x00000000 },
3012 + { 0x000011b8, 0x00000000 },
3013 + { 0x000011f8, 0x00000000 },
3014 + { 0x00001238, 0x00000000 },
3015 + { 0x00001278, 0x00000000 },
3016 + { 0x000012b8, 0x00000000 },
3017 + { 0x000012f8, 0x00000000 },
3018 + { 0x00001338, 0x00000000 },
3019 + { 0x00001378, 0x00000000 },
3020 + { 0x000013b8, 0x00000000 },
3021 + { 0x000013f8, 0x00000000 },
3022 + { 0x00001438, 0x00000000 },
3023 + { 0x00001478, 0x00000000 },
3024 + { 0x000014b8, 0x00000000 },
3025 + { 0x000014f8, 0x00000000 },
3026 + { 0x00001538, 0x00000000 },
3027 + { 0x00001578, 0x00000000 },
3028 + { 0x000015b8, 0x00000000 },
3029 + { 0x000015f8, 0x00000000 },
3030 + { 0x00001638, 0x00000000 },
3031 + { 0x00001678, 0x00000000 },
3032 + { 0x000016b8, 0x00000000 },
3033 + { 0x000016f8, 0x00000000 },
3034 + { 0x00001738, 0x00000000 },
3035 + { 0x00001778, 0x00000000 },
3036 + { 0x000017b8, 0x00000000 },
3037 + { 0x000017f8, 0x00000000 },
3038 + { 0x0000103c, 0x00000000 },
3039 + { 0x0000107c, 0x00000000 },
3040 + { 0x000010bc, 0x00000000 },
3041 + { 0x000010fc, 0x00000000 },
3042 + { 0x0000113c, 0x00000000 },
3043 + { 0x0000117c, 0x00000000 },
3044 + { 0x000011bc, 0x00000000 },
3045 + { 0x000011fc, 0x00000000 },
3046 + { 0x0000123c, 0x00000000 },
3047 + { 0x0000127c, 0x00000000 },
3048 + { 0x000012bc, 0x00000000 },
3049 + { 0x000012fc, 0x00000000 },
3050 + { 0x0000133c, 0x00000000 },
3051 + { 0x0000137c, 0x00000000 },
3052 + { 0x000013bc, 0x00000000 },
3053 + { 0x000013fc, 0x00000000 },
3054 + { 0x0000143c, 0x00000000 },
3055 + { 0x0000147c, 0x00000000 },
3056 + { 0x00004030, 0x00000002 },
3057 + { 0x0000403c, 0x00000002 },
3058 + { 0x00007010, 0x00000020 },
3059 + { 0x00007038, 0x000004c2 },
3060 + { 0x00008004, 0x00000000 },
3061 + { 0x00008008, 0x00000000 },
3062 + { 0x0000800c, 0x00000000 },
3063 + { 0x00008018, 0x00000700 },
3064 + { 0x00008020, 0x00000000 },
3065 + { 0x00008038, 0x00000000 },
3066 + { 0x0000803c, 0x00000000 },
3067 + { 0x00008048, 0x40000000 },
3068 + { 0x00008054, 0x00000000 },
3069 + { 0x00008058, 0x00000000 },
3070 + { 0x0000805c, 0x000fc78f },
3071 + { 0x00008060, 0x0000000f },
3072 + { 0x00008064, 0x00000000 },
3073 + { 0x000080c0, 0x2a82301a },
3074 + { 0x000080c4, 0x05dc01e0 },
3075 + { 0x000080c8, 0x1f402710 },
3076 + { 0x000080cc, 0x01f40000 },
3077 + { 0x000080d0, 0x00001e00 },
3078 + { 0x000080d4, 0x00000000 },
3079 + { 0x000080d8, 0x00400000 },
3080 + { 0x000080e0, 0xffffffff },
3081 + { 0x000080e4, 0x0000ffff },
3082 + { 0x000080e8, 0x003f3f3f },
3083 + { 0x000080ec, 0x00000000 },
3084 + { 0x000080f0, 0x00000000 },
3085 + { 0x000080f4, 0x00000000 },
3086 + { 0x000080f8, 0x00000000 },
3087 + { 0x000080fc, 0x00020000 },
3088 + { 0x00008100, 0x00020000 },
3089 + { 0x00008104, 0x00000001 },
3090 + { 0x00008108, 0x00000052 },
3091 + { 0x0000810c, 0x00000000 },
3092 + { 0x00008110, 0x00000168 },
3093 + { 0x00008118, 0x000100aa },
3094 + { 0x0000811c, 0x00003210 },
3095 + { 0x00008120, 0x08f04800 },
3096 + { 0x00008124, 0x00000000 },
3097 + { 0x00008128, 0x00000000 },
3098 + { 0x0000812c, 0x00000000 },
3099 + { 0x00008130, 0x00000000 },
3100 + { 0x00008134, 0x00000000 },
3101 + { 0x00008138, 0x00000000 },
3102 + { 0x0000813c, 0x00000000 },
3103 + { 0x00008144, 0xffffffff },
3104 + { 0x00008168, 0x00000000 },
3105 + { 0x0000816c, 0x00000000 },
3106 + { 0x00008170, 0x32143320 },
3107 + { 0x00008174, 0xfaa4fa50 },
3108 + { 0x00008178, 0x00000100 },
3109 + { 0x0000817c, 0x00000000 },
3110 + { 0x000081c4, 0x00000000 },
3111 + { 0x000081d0, 0x00003210 },
3112 + { 0x000081ec, 0x00000000 },
3113 + { 0x000081f0, 0x00000000 },
3114 + { 0x000081f4, 0x00000000 },
3115 + { 0x000081f8, 0x00000000 },
3116 + { 0x000081fc, 0x00000000 },
3117 + { 0x00008200, 0x00000000 },
3118 + { 0x00008204, 0x00000000 },
3119 + { 0x00008208, 0x00000000 },
3120 + { 0x0000820c, 0x00000000 },
3121 + { 0x00008210, 0x00000000 },
3122 + { 0x00008214, 0x00000000 },
3123 + { 0x00008218, 0x00000000 },
3124 + { 0x0000821c, 0x00000000 },
3125 + { 0x00008220, 0x00000000 },
3126 + { 0x00008224, 0x00000000 },
3127 + { 0x00008228, 0x00000000 },
3128 + { 0x0000822c, 0x00000000 },
3129 + { 0x00008230, 0x00000000 },
3130 + { 0x00008234, 0x00000000 },
3131 + { 0x00008238, 0x00000000 },
3132 + { 0x0000823c, 0x00000000 },
3133 + { 0x00008240, 0x00100000 },
3134 + { 0x00008244, 0x0010f400 },
3135 + { 0x00008248, 0x00000100 },
3136 + { 0x0000824c, 0x0001e800 },
3137 + { 0x00008250, 0x00000000 },
3138 + { 0x00008254, 0x00000000 },
3139 + { 0x00008258, 0x00000000 },
3140 + { 0x0000825c, 0x400000ff },
3141 + { 0x00008260, 0x00080922 },
3142 + { 0x00008270, 0x00000000 },
3143 + { 0x00008274, 0x40000000 },
3144 + { 0x00008278, 0x003e4180 },
3145 + { 0x0000827c, 0x00000000 },
3146 + { 0x00008284, 0x0000002c },
3147 + { 0x00008288, 0x0000002c },
3148 + { 0x0000828c, 0x00000000 },
3149 + { 0x00008294, 0x00000000 },
3150 + { 0x00008298, 0x00000000 },
3151 + { 0x00008300, 0x00000000 },
3152 + { 0x00008304, 0x00000000 },
3153 + { 0x00008308, 0x00000000 },
3154 + { 0x0000830c, 0x00000000 },
3155 + { 0x00008310, 0x00000000 },
3156 + { 0x00008314, 0x00000000 },
3157 + { 0x00008318, 0x00000000 },
3158 + { 0x00008328, 0x00000000 },
3159 + { 0x0000832c, 0x00000007 },
3160 + { 0x00008330, 0x00000302 },
3161 + { 0x00008334, 0x00000e00 },
3162 + { 0x00008338, 0x00ff0000 },
3163 + { 0x0000833c, 0x00000000 },
3164 + { 0x00008340, 0x000107ff },
3165 + { 0x00009808, 0x00000000 },
3166 + { 0x0000980c, 0xad848e19 },
3167 + { 0x00009810, 0x7d14e000 },
3168 + { 0x00009814, 0x9c0a9f6b },
3169 + { 0x0000981c, 0x00000000 },
3170 + { 0x0000982c, 0x0000a000 },
3171 + { 0x00009830, 0x00000000 },
3172 + { 0x0000983c, 0x00200400 },
3173 + { 0x00009840, 0x206a01ae },
3174 + { 0x0000984c, 0x1284233c },
3175 + { 0x00009854, 0x00000859 },
3176 + { 0x00009900, 0x00000000 },
3177 + { 0x00009904, 0x00000000 },
3178 + { 0x00009908, 0x00000000 },
3179 + { 0x0000990c, 0x00000000 },
3180 + { 0x0000991c, 0x10000fff },
3181 + { 0x00009920, 0x05100000 },
3182 + { 0x0000a920, 0x05100000 },
3183 + { 0x0000b920, 0x05100000 },
3184 + { 0x00009928, 0x00000001 },
3185 + { 0x0000992c, 0x00000004 },
3186 + { 0x00009934, 0x1e1f2022 },
3187 + { 0x00009938, 0x0a0b0c0d },
3188 + { 0x0000993c, 0x00000000 },
3189 + { 0x00009948, 0x9280b212 },
3190 + { 0x0000994c, 0x00020028 },
3191 + { 0x00009954, 0x5f3ca3de },
3192 + { 0x00009958, 0x2108ecff },
3193 + { 0x00009940, 0x00750604 },
3194 + { 0x0000c95c, 0x004b6a8e },
3195 + { 0x00009970, 0x190fb515 },
3196 + { 0x00009974, 0x00000000 },
3197 + { 0x00009978, 0x00000001 },
3198 + { 0x0000997c, 0x00000000 },
3199 + { 0x00009980, 0x00000000 },
3200 + { 0x00009984, 0x00000000 },
3201 + { 0x00009988, 0x00000000 },
3202 + { 0x0000998c, 0x00000000 },
3203 + { 0x00009990, 0x00000000 },
3204 + { 0x00009994, 0x00000000 },
3205 + { 0x00009998, 0x00000000 },
3206 + { 0x0000999c, 0x00000000 },
3207 + { 0x000099a0, 0x00000000 },
3208 + { 0x000099a4, 0x00000001 },
3209 + { 0x000099a8, 0x201fff00 },
3210 + { 0x000099ac, 0x006f0000 },
3211 + { 0x000099b0, 0x03051000 },
3212 + { 0x000099dc, 0x00000000 },
3213 + { 0x000099e0, 0x00000200 },
3214 + { 0x000099e4, 0xaaaaaaaa },
3215 + { 0x000099e8, 0x3c466478 },
3216 + { 0x000099ec, 0x0cc80caa },
3217 + { 0x000099fc, 0x00001042 },
3218 + { 0x00009b00, 0x00000000 },
3219 + { 0x00009b04, 0x00000001 },
3220 + { 0x00009b08, 0x00000002 },
3221 + { 0x00009b0c, 0x00000003 },
3222 + { 0x00009b10, 0x00000004 },
3223 + { 0x00009b14, 0x00000005 },
3224 + { 0x00009b18, 0x00000008 },
3225 + { 0x00009b1c, 0x00000009 },
3226 + { 0x00009b20, 0x0000000a },
3227 + { 0x00009b24, 0x0000000b },
3228 + { 0x00009b28, 0x0000000c },
3229 + { 0x00009b2c, 0x0000000d },
3230 + { 0x00009b30, 0x00000010 },
3231 + { 0x00009b34, 0x00000011 },
3232 + { 0x00009b38, 0x00000012 },
3233 + { 0x00009b3c, 0x00000013 },
3234 + { 0x00009b40, 0x00000014 },
3235 + { 0x00009b44, 0x00000015 },
3236 + { 0x00009b48, 0x00000018 },
3237 + { 0x00009b4c, 0x00000019 },
3238 + { 0x00009b50, 0x0000001a },
3239 + { 0x00009b54, 0x0000001b },
3240 + { 0x00009b58, 0x0000001c },
3241 + { 0x00009b5c, 0x0000001d },
3242 + { 0x00009b60, 0x00000020 },
3243 + { 0x00009b64, 0x00000021 },
3244 + { 0x00009b68, 0x00000022 },
3245 + { 0x00009b6c, 0x00000023 },
3246 + { 0x00009b70, 0x00000024 },
3247 + { 0x00009b74, 0x00000025 },
3248 + { 0x00009b78, 0x00000028 },
3249 + { 0x00009b7c, 0x00000029 },
3250 + { 0x00009b80, 0x0000002a },
3251 + { 0x00009b84, 0x0000002b },
3252 + { 0x00009b88, 0x0000002c },
3253 + { 0x00009b8c, 0x0000002d },
3254 + { 0x00009b90, 0x00000030 },
3255 + { 0x00009b94, 0x00000031 },
3256 + { 0x00009b98, 0x00000032 },
3257 + { 0x00009b9c, 0x00000033 },
3258 + { 0x00009ba0, 0x00000034 },
3259 + { 0x00009ba4, 0x00000035 },
3260 + { 0x00009ba8, 0x00000035 },
3261 + { 0x00009bac, 0x00000035 },
3262 + { 0x00009bb0, 0x00000035 },
3263 + { 0x00009bb4, 0x00000035 },
3264 + { 0x00009bb8, 0x00000035 },
3265 + { 0x00009bbc, 0x00000035 },
3266 + { 0x00009bc0, 0x00000035 },
3267 + { 0x00009bc4, 0x00000035 },
3268 + { 0x00009bc8, 0x00000035 },
3269 + { 0x00009bcc, 0x00000035 },
3270 + { 0x00009bd0, 0x00000035 },
3271 + { 0x00009bd4, 0x00000035 },
3272 + { 0x00009bd8, 0x00000035 },
3273 + { 0x00009bdc, 0x00000035 },
3274 + { 0x00009be0, 0x00000035 },
3275 + { 0x00009be4, 0x00000035 },
3276 + { 0x00009be8, 0x00000035 },
3277 + { 0x00009bec, 0x00000035 },
3278 + { 0x00009bf0, 0x00000035 },
3279 + { 0x00009bf4, 0x00000035 },
3280 + { 0x00009bf8, 0x00000010 },
3281 + { 0x00009bfc, 0x0000001a },
3282 + { 0x0000a210, 0x40806333 },
3283 + { 0x0000a214, 0x00106c10 },
3284 + { 0x0000a218, 0x009c4060 },
3285 + { 0x0000a220, 0x018830c6 },
3286 + { 0x0000a224, 0x00000400 },
3287 + { 0x0000a228, 0x001a0bb5 },
3288 + { 0x0000a22c, 0x00000000 },
3289 + { 0x0000a234, 0x20202020 },
3290 + { 0x0000a238, 0x20202020 },
3291 + { 0x0000a23c, 0x13c889af },
3292 + { 0x0000a240, 0x38490a20 },
3293 + { 0x0000a244, 0x00007bb6 },
3294 + { 0x0000a248, 0x0fff3ffc },
3295 + { 0x0000a24c, 0x00000001 },
3296 + { 0x0000a250, 0x0000e000 },
3297 + { 0x0000a254, 0x00000000 },
3298 + { 0x0000a258, 0x0cc75380 },
3299 + { 0x0000a25c, 0x0f0f0f01 },
3300 + { 0x0000a260, 0xdfa91f01 },
3301 + { 0x0000a268, 0x00000001 },
3302 + { 0x0000a26c, 0x0ebae9c6 },
3303 + { 0x0000b26c, 0x0ebae9c6 },
3304 + { 0x0000c26c, 0x0ebae9c6 },
3305 + { 0x0000d270, 0x00820820 },
3306 + { 0x0000a278, 0x1ce739ce },
3307 + { 0x0000a27c, 0x050701ce },
3308 + { 0x0000a338, 0x00000000 },
3309 + { 0x0000a33c, 0x00000000 },
3310 + { 0x0000a340, 0x00000000 },
3311 + { 0x0000a344, 0x00000000 },
3312 + { 0x0000a348, 0x3fffffff },
3313 + { 0x0000a34c, 0x3fffffff },
3314 + { 0x0000a350, 0x3fffffff },
3315 + { 0x0000a354, 0x0003ffff },
3316 + { 0x0000a358, 0x79bfaa03 },
3317 + { 0x0000d35c, 0x07ffffef },
3318 + { 0x0000d360, 0x0fffffe7 },
3319 + { 0x0000d364, 0x17ffffe5 },
3320 + { 0x0000d368, 0x1fffffe4 },
3321 + { 0x0000d36c, 0x37ffffe3 },
3322 + { 0x0000d370, 0x3fffffe3 },
3323 + { 0x0000d374, 0x57ffffe3 },
3324 + { 0x0000d378, 0x5fffffe2 },
3325 + { 0x0000d37c, 0x7fffffe2 },
3326 + { 0x0000d380, 0x7f3c7bba },
3327 + { 0x0000d384, 0xf3307ff0 },
3328 + { 0x0000a388, 0x0c000000 },
3329 + { 0x0000a38c, 0x20202020 },
3330 + { 0x0000a390, 0x20202020 },
3331 + { 0x0000a394, 0x1ce739ce },
3332 + { 0x0000a398, 0x000001ce },
3333 + { 0x0000a39c, 0x00000001 },
3334 + { 0x0000a3a0, 0x00000000 },
3335 + { 0x0000a3a4, 0x00000000 },
3336 + { 0x0000a3a8, 0x00000000 },
3337 + { 0x0000a3ac, 0x00000000 },
3338 + { 0x0000a3b0, 0x00000000 },
3339 + { 0x0000a3b4, 0x00000000 },
3340 + { 0x0000a3b8, 0x00000000 },
3341 + { 0x0000a3bc, 0x00000000 },
3342 + { 0x0000a3c0, 0x00000000 },
3343 + { 0x0000a3c4, 0x00000000 },
3344 + { 0x0000a3c8, 0x00000246 },
3345 + { 0x0000a3cc, 0x20202020 },
3346 + { 0x0000a3d0, 0x20202020 },
3347 + { 0x0000a3d4, 0x20202020 },
3348 + { 0x0000a3dc, 0x1ce739ce },
3349 + { 0x0000a3e0, 0x000001ce },
3350 +};
3351 +
3352 +static const u32 ar5416Bank0_9160[][2] = {
3353 + { 0x000098b0, 0x1e5795e5 },
3354 + { 0x000098e0, 0x02008020 },
3355 +};
3356 +
3357 +static const u32 ar5416BB_RfGain_9160[][3] = {
3358 + { 0x00009a00, 0x00000000, 0x00000000 },
3359 + { 0x00009a04, 0x00000040, 0x00000040 },
3360 + { 0x00009a08, 0x00000080, 0x00000080 },
3361 + { 0x00009a0c, 0x000001a1, 0x00000141 },
3362 + { 0x00009a10, 0x000001e1, 0x00000181 },
3363 + { 0x00009a14, 0x00000021, 0x000001c1 },
3364 + { 0x00009a18, 0x00000061, 0x00000001 },
3365 + { 0x00009a1c, 0x00000168, 0x00000041 },
3366 + { 0x00009a20, 0x000001a8, 0x000001a8 },
3367 + { 0x00009a24, 0x000001e8, 0x000001e8 },
3368 + { 0x00009a28, 0x00000028, 0x00000028 },
3369 + { 0x00009a2c, 0x00000068, 0x00000068 },
3370 + { 0x00009a30, 0x00000189, 0x000000a8 },
3371 + { 0x00009a34, 0x000001c9, 0x00000169 },
3372 + { 0x00009a38, 0x00000009, 0x000001a9 },
3373 + { 0x00009a3c, 0x00000049, 0x000001e9 },
3374 + { 0x00009a40, 0x00000089, 0x00000029 },
3375 + { 0x00009a44, 0x00000170, 0x00000069 },
3376 + { 0x00009a48, 0x000001b0, 0x00000190 },
3377 + { 0x00009a4c, 0x000001f0, 0x000001d0 },
3378 + { 0x00009a50, 0x00000030, 0x00000010 },
3379 + { 0x00009a54, 0x00000070, 0x00000050 },
3380 + { 0x00009a58, 0x00000191, 0x00000090 },
3381 + { 0x00009a5c, 0x000001d1, 0x00000151 },
3382 + { 0x00009a60, 0x00000011, 0x00000191 },
3383 + { 0x00009a64, 0x00000051, 0x000001d1 },
3384 + { 0x00009a68, 0x00000091, 0x00000011 },
3385 + { 0x00009a6c, 0x000001b8, 0x00000051 },
3386 + { 0x00009a70, 0x000001f8, 0x00000198 },
3387 + { 0x00009a74, 0x00000038, 0x000001d8 },
3388 + { 0x00009a78, 0x00000078, 0x00000018 },
3389 + { 0x00009a7c, 0x00000199, 0x00000058 },
3390 + { 0x00009a80, 0x000001d9, 0x00000098 },
3391 + { 0x00009a84, 0x00000019, 0x00000159 },
3392 + { 0x00009a88, 0x00000059, 0x00000199 },
3393 + { 0x00009a8c, 0x00000099, 0x000001d9 },
3394 + { 0x00009a90, 0x000000d9, 0x00000019 },
3395 + { 0x00009a94, 0x000000f9, 0x00000059 },
3396 + { 0x00009a98, 0x000000f9, 0x00000099 },
3397 + { 0x00009a9c, 0x000000f9, 0x000000d9 },
3398 + { 0x00009aa0, 0x000000f9, 0x000000f9 },
3399 + { 0x00009aa4, 0x000000f9, 0x000000f9 },
3400 + { 0x00009aa8, 0x000000f9, 0x000000f9 },
3401 + { 0x00009aac, 0x000000f9, 0x000000f9 },
3402 + { 0x00009ab0, 0x000000f9, 0x000000f9 },
3403 + { 0x00009ab4, 0x000000f9, 0x000000f9 },
3404 + { 0x00009ab8, 0x000000f9, 0x000000f9 },
3405 + { 0x00009abc, 0x000000f9, 0x000000f9 },
3406 + { 0x00009ac0, 0x000000f9, 0x000000f9 },
3407 + { 0x00009ac4, 0x000000f9, 0x000000f9 },
3408 + { 0x00009ac8, 0x000000f9, 0x000000f9 },
3409 + { 0x00009acc, 0x000000f9, 0x000000f9 },
3410 + { 0x00009ad0, 0x000000f9, 0x000000f9 },
3411 + { 0x00009ad4, 0x000000f9, 0x000000f9 },
3412 + { 0x00009ad8, 0x000000f9, 0x000000f9 },
3413 + { 0x00009adc, 0x000000f9, 0x000000f9 },
3414 + { 0x00009ae0, 0x000000f9, 0x000000f9 },
3415 + { 0x00009ae4, 0x000000f9, 0x000000f9 },
3416 + { 0x00009ae8, 0x000000f9, 0x000000f9 },
3417 + { 0x00009aec, 0x000000f9, 0x000000f9 },
3418 + { 0x00009af0, 0x000000f9, 0x000000f9 },
3419 + { 0x00009af4, 0x000000f9, 0x000000f9 },
3420 + { 0x00009af8, 0x000000f9, 0x000000f9 },
3421 + { 0x00009afc, 0x000000f9, 0x000000f9 },
3422 +};
3423 +
3424 +static const u32 ar5416Bank1_9160[][2] = {
3425 + { 0x000098b0, 0x02108421 },
3426 + { 0x000098ec, 0x00000008 },
3427 +};
3428 +
3429 +static const u32 ar5416Bank2_9160[][2] = {
3430 + { 0x000098b0, 0x0e73ff17 },
3431 + { 0x000098e0, 0x00000420 },
3432 +};
3433 +
3434 +static const u32 ar5416Bank3_9160[][3] = {
3435 + { 0x000098f0, 0x01400018, 0x01c00018 },
3436 +};
3437 +
3438 +static const u32 ar5416Bank6_9160[][3] = {
3439 + { 0x0000989c, 0x00000000, 0x00000000 },
3440 + { 0x0000989c, 0x00000000, 0x00000000 },
3441 + { 0x0000989c, 0x00000000, 0x00000000 },
3442 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3443 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3444 + { 0x0000989c, 0x00120000, 0x00120000 },
3445 + { 0x0000989c, 0x00620000, 0x00620000 },
3446 + { 0x0000989c, 0x00020000, 0x00020000 },
3447 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3448 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3449 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3450 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3451 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3452 + { 0x0000989c, 0x00870000, 0x00870000 },
3453 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3454 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3455 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3456 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3457 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3458 + { 0x0000989c, 0x00110000, 0x00110000 },
3459 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3460 + { 0x0000989c, 0x004210a2, 0x004210a2 },
3461 + { 0x0000989c, 0x0014008f, 0x0014008f },
3462 + { 0x0000989c, 0x00c40003, 0x00c40003 },
3463 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3464 + { 0x0000989c, 0x00440016, 0x00440016 },
3465 + { 0x0000989c, 0x00410040, 0x00410040 },
3466 + { 0x0000989c, 0x0001805e, 0x0001805e },
3467 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3468 + { 0x0000989c, 0x000000f1, 0x000000f1 },
3469 + { 0x0000989c, 0x00002081, 0x00002081 },
3470 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3471 + { 0x000098d0, 0x0000000f, 0x0010000f },
3472 +};
3473 +
3474 +static const u32 ar5416Bank6TPC_9160[][3] = {
3475 + { 0x0000989c, 0x00000000, 0x00000000 },
3476 + { 0x0000989c, 0x00000000, 0x00000000 },
3477 + { 0x0000989c, 0x00000000, 0x00000000 },
3478 + { 0x0000989c, 0x00e00000, 0x00e00000 },
3479 + { 0x0000989c, 0x005e0000, 0x005e0000 },
3480 + { 0x0000989c, 0x00120000, 0x00120000 },
3481 + { 0x0000989c, 0x00620000, 0x00620000 },
3482 + { 0x0000989c, 0x00020000, 0x00020000 },
3483 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3484 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3485 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3486 + { 0x0000989c, 0x40ff0000, 0x40ff0000 },
3487 + { 0x0000989c, 0x005f0000, 0x005f0000 },
3488 + { 0x0000989c, 0x00870000, 0x00870000 },
3489 + { 0x0000989c, 0x00f90000, 0x00f90000 },
3490 + { 0x0000989c, 0x007b0000, 0x007b0000 },
3491 + { 0x0000989c, 0x00ff0000, 0x00ff0000 },
3492 + { 0x0000989c, 0x00f50000, 0x00f50000 },
3493 + { 0x0000989c, 0x00dc0000, 0x00dc0000 },
3494 + { 0x0000989c, 0x00110000, 0x00110000 },
3495 + { 0x0000989c, 0x006100a8, 0x006100a8 },
3496 + { 0x0000989c, 0x00423022, 0x00423022 },
3497 + { 0x0000989c, 0x2014008f, 0x2014008f },
3498 + { 0x0000989c, 0x00c40002, 0x00c40002 },
3499 + { 0x0000989c, 0x003000f2, 0x003000f2 },
3500 + { 0x0000989c, 0x00440016, 0x00440016 },
3501 + { 0x0000989c, 0x00410040, 0x00410040 },
3502 + { 0x0000989c, 0x0001805e, 0x0001805e },
3503 + { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
3504 + { 0x0000989c, 0x000000e1, 0x000000e1 },
3505 + { 0x0000989c, 0x00007080, 0x00007080 },
3506 + { 0x0000989c, 0x000000d4, 0x000000d4 },
3507 + { 0x000098d0, 0x0000000f, 0x0010000f },
3508 +};
3509 +
3510 +static const u32 ar5416Bank7_9160[][2] = {
3511 + { 0x0000989c, 0x00000500 },
3512 + { 0x0000989c, 0x00000800 },
3513 + { 0x000098cc, 0x0000000e },
3514 +};
3515 +
3516 +static u32 ar5416Addac_9160[][2] = {
3517 + {0x0000989c, 0x00000000 },
3518 + {0x0000989c, 0x00000000 },
3519 + {0x0000989c, 0x00000000 },
3520 + {0x0000989c, 0x00000000 },
3521 + {0x0000989c, 0x00000000 },
3522 + {0x0000989c, 0x00000000 },
3523 + {0x0000989c, 0x000000c0 },
3524 + {0x0000989c, 0x00000018 },
3525 + {0x0000989c, 0x00000004 },
3526 + {0x0000989c, 0x00000000 },
3527 + {0x0000989c, 0x00000000 },
3528 + {0x0000989c, 0x00000000 },
3529 + {0x0000989c, 0x00000000 },
3530 + {0x0000989c, 0x00000000 },
3531 + {0x0000989c, 0x00000000 },
3532 + {0x0000989c, 0x00000000 },
3533 + {0x0000989c, 0x00000000 },
3534 + {0x0000989c, 0x00000000 },
3535 + {0x0000989c, 0x00000000 },
3536 + {0x0000989c, 0x00000000 },
3537 + {0x0000989c, 0x00000000 },
3538 + {0x0000989c, 0x000000c0 },
3539 + {0x0000989c, 0x00000019 },
3540 + {0x0000989c, 0x00000004 },
3541 + {0x0000989c, 0x00000000 },
3542 + {0x0000989c, 0x00000000 },
3543 + {0x0000989c, 0x00000000 },
3544 + {0x0000989c, 0x00000004 },
3545 + {0x0000989c, 0x00000003 },
3546 + {0x0000989c, 0x00000008 },
3547 + {0x0000989c, 0x00000000 },
3548 + {0x000098cc, 0x00000000 },
3549 +};
3550 +
3551 +static u32 ar5416Addac_91601_1[][2] = {
3552 + {0x0000989c, 0x00000000 },
3553 + {0x0000989c, 0x00000000 },
3554 + {0x0000989c, 0x00000000 },
3555 + {0x0000989c, 0x00000000 },
3556 + {0x0000989c, 0x00000000 },
3557 + {0x0000989c, 0x00000000 },
3558 + {0x0000989c, 0x000000c0 },
3559 + {0x0000989c, 0x00000018 },
3560 + {0x0000989c, 0x00000004 },
3561 + {0x0000989c, 0x00000000 },
3562 + {0x0000989c, 0x00000000 },
3563 + {0x0000989c, 0x00000000 },
3564 + {0x0000989c, 0x00000000 },
3565 + {0x0000989c, 0x00000000 },
3566 + {0x0000989c, 0x00000000 },
3567 + {0x0000989c, 0x00000000 },
3568 + {0x0000989c, 0x00000000 },
3569 + {0x0000989c, 0x00000000 },
3570 + {0x0000989c, 0x00000000 },
3571 + {0x0000989c, 0x00000000 },
3572 + {0x0000989c, 0x00000000 },
3573 + {0x0000989c, 0x000000c0 },
3574 + {0x0000989c, 0x00000019 },
3575 + {0x0000989c, 0x00000004 },
3576 + {0x0000989c, 0x00000000 },
3577 + {0x0000989c, 0x00000000 },
3578 + {0x0000989c, 0x00000000 },
3579 + {0x0000989c, 0x00000000 },
3580 + {0x0000989c, 0x00000000 },
3581 + {0x0000989c, 0x00000000 },
3582 + {0x0000989c, 0x00000000 },
3583 + {0x000098cc, 0x00000000 },
3584 +};
3585 +
3586 --- /dev/null
3587 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3588 @@ -0,0 +1,995 @@
3589 +/*
3590 + * Copyright (c) 2008-2010 Atheros Communications Inc.
3591 + *
3592 + * Permission to use, copy, modify, and/or distribute this software for any
3593 + * purpose with or without fee is hereby granted, provided that the above
3594 + * copyright notice and this permission notice appear in all copies.
3595 + *
3596 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3597 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3598 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3599 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3600 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3601 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3602 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3603 + */
3604 +
3605 +#include "hw.h"
3606 +#include "hw-ops.h"
3607 +#include "ar9002_phy.h"
3608 +
3609 +#define AR9285_CLCAL_REDO_THRESH 1
3610 +
3611 +static void ar9002_hw_setup_calibration(struct ath_hw *ah,
3612 + struct ath9k_cal_list *currCal)
3613 +{
3614 + struct ath_common *common = ath9k_hw_common(ah);
3615 +
3616 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
3617 + AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
3618 + currCal->calData->calCountMax);
3619 +
3620 + switch (currCal->calData->calType) {
3621 + case IQ_MISMATCH_CAL:
3622 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
3623 + ath_print(common, ATH_DBG_CALIBRATE,
3624 + "starting IQ Mismatch Calibration\n");
3625 + break;
3626 + case ADC_GAIN_CAL:
3627 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
3628 + ath_print(common, ATH_DBG_CALIBRATE,
3629 + "starting ADC Gain Calibration\n");
3630 + break;
3631 + case ADC_DC_CAL:
3632 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
3633 + ath_print(common, ATH_DBG_CALIBRATE,
3634 + "starting ADC DC Calibration\n");
3635 + break;
3636 + case ADC_DC_INIT_CAL:
3637 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
3638 + ath_print(common, ATH_DBG_CALIBRATE,
3639 + "starting Init ADC DC Calibration\n");
3640 + break;
3641 + case TEMP_COMP_CAL:
3642 + break; /* Not supported */
3643 + }
3644 +
3645 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3646 + AR_PHY_TIMING_CTRL4_DO_CAL);
3647 +}
3648 +
3649 +static bool ar9002_hw_per_calibration(struct ath_hw *ah,
3650 + struct ath9k_channel *ichan,
3651 + u8 rxchainmask,
3652 + struct ath9k_cal_list *currCal)
3653 +{
3654 + bool iscaldone = false;
3655 +
3656 + if (currCal->calState == CAL_RUNNING) {
3657 + if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
3658 + AR_PHY_TIMING_CTRL4_DO_CAL)) {
3659 +
3660 + currCal->calData->calCollect(ah);
3661 + ah->cal_samples++;
3662 +
3663 + if (ah->cal_samples >=
3664 + currCal->calData->calNumSamples) {
3665 + int i, numChains = 0;
3666 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3667 + if (rxchainmask & (1 << i))
3668 + numChains++;
3669 + }
3670 +
3671 + currCal->calData->calPostProc(ah, numChains);
3672 + ichan->CalValid |= currCal->calData->calType;
3673 + currCal->calState = CAL_DONE;
3674 + iscaldone = true;
3675 + } else {
3676 + ar9002_hw_setup_calibration(ah, currCal);
3677 + }
3678 + }
3679 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
3680 + ath9k_hw_reset_calibration(ah, currCal);
3681 + }
3682 +
3683 + return iscaldone;
3684 +}
3685 +
3686 +/* Assumes you are talking about the currently configured channel */
3687 +static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
3688 + enum ath9k_cal_types calType)
3689 +{
3690 + struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3691 +
3692 + switch (calType & ah->supp_cals) {
3693 + case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
3694 + return true;
3695 + case ADC_GAIN_CAL:
3696 + case ADC_DC_CAL:
3697 + if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
3698 + conf_is_ht20(conf)))
3699 + return true;
3700 + break;
3701 + }
3702 + return false;
3703 +}
3704 +
3705 +static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
3706 +{
3707 + int i;
3708 +
3709 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3710 + ah->totalPowerMeasI[i] +=
3711 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3712 + ah->totalPowerMeasQ[i] +=
3713 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3714 + ah->totalIqCorrMeas[i] +=
3715 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3716 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3717 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
3718 + ah->cal_samples, i, ah->totalPowerMeasI[i],
3719 + ah->totalPowerMeasQ[i],
3720 + ah->totalIqCorrMeas[i]);
3721 + }
3722 +}
3723 +
3724 +static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
3725 +{
3726 + int i;
3727 +
3728 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3729 + ah->totalAdcIOddPhase[i] +=
3730 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3731 + ah->totalAdcIEvenPhase[i] +=
3732 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3733 + ah->totalAdcQOddPhase[i] +=
3734 + REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3735 + ah->totalAdcQEvenPhase[i] +=
3736 + REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3737 +
3738 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3739 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3740 + "oddq=0x%08x; evenq=0x%08x;\n",
3741 + ah->cal_samples, i,
3742 + ah->totalAdcIOddPhase[i],
3743 + ah->totalAdcIEvenPhase[i],
3744 + ah->totalAdcQOddPhase[i],
3745 + ah->totalAdcQEvenPhase[i]);
3746 + }
3747 +}
3748 +
3749 +static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
3750 +{
3751 + int i;
3752 +
3753 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3754 + ah->totalAdcDcOffsetIOddPhase[i] +=
3755 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3756 + ah->totalAdcDcOffsetIEvenPhase[i] +=
3757 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3758 + ah->totalAdcDcOffsetQOddPhase[i] +=
3759 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3760 + ah->totalAdcDcOffsetQEvenPhase[i] +=
3761 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3762 +
3763 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3764 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3765 + "oddq=0x%08x; evenq=0x%08x;\n",
3766 + ah->cal_samples, i,
3767 + ah->totalAdcDcOffsetIOddPhase[i],
3768 + ah->totalAdcDcOffsetIEvenPhase[i],
3769 + ah->totalAdcDcOffsetQOddPhase[i],
3770 + ah->totalAdcDcOffsetQEvenPhase[i]);
3771 + }
3772 +}
3773 +
3774 +static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
3775 +{
3776 + struct ath_common *common = ath9k_hw_common(ah);
3777 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
3778 + u32 qCoffDenom, iCoffDenom;
3779 + int32_t qCoff, iCoff;
3780 + int iqCorrNeg, i;
3781 +
3782 + for (i = 0; i < numChains; i++) {
3783 + powerMeasI = ah->totalPowerMeasI[i];
3784 + powerMeasQ = ah->totalPowerMeasQ[i];
3785 + iqCorrMeas = ah->totalIqCorrMeas[i];
3786 +
3787 + ath_print(common, ATH_DBG_CALIBRATE,
3788 + "Starting IQ Cal and Correction for Chain %d\n",
3789 + i);
3790 +
3791 + ath_print(common, ATH_DBG_CALIBRATE,
3792 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
3793 + i, ah->totalIqCorrMeas[i]);
3794 +
3795 + iqCorrNeg = 0;
3796 +
3797 + if (iqCorrMeas > 0x80000000) {
3798 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
3799 + iqCorrNeg = 1;
3800 + }
3801 +
3802 + ath_print(common, ATH_DBG_CALIBRATE,
3803 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
3804 + ath_print(common, ATH_DBG_CALIBRATE,
3805 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
3806 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
3807 + iqCorrNeg);
3808 +
3809 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
3810 + qCoffDenom = powerMeasQ / 64;
3811 +
3812 + if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
3813 + (qCoffDenom != 0)) {
3814 + iCoff = iqCorrMeas / iCoffDenom;
3815 + qCoff = powerMeasI / qCoffDenom - 64;
3816 + ath_print(common, ATH_DBG_CALIBRATE,
3817 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
3818 + ath_print(common, ATH_DBG_CALIBRATE,
3819 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
3820 +
3821 + iCoff = iCoff & 0x3f;
3822 + ath_print(common, ATH_DBG_CALIBRATE,
3823 + "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
3824 + if (iqCorrNeg == 0x0)
3825 + iCoff = 0x40 - iCoff;
3826 +
3827 + if (qCoff > 15)
3828 + qCoff = 15;
3829 + else if (qCoff <= -16)
3830 + qCoff = 16;
3831 +
3832 + ath_print(common, ATH_DBG_CALIBRATE,
3833 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
3834 + i, iCoff, qCoff);
3835 +
3836 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3837 + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
3838 + iCoff);
3839 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3840 + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
3841 + qCoff);
3842 + ath_print(common, ATH_DBG_CALIBRATE,
3843 + "IQ Cal and Correction done for Chain %d\n",
3844 + i);
3845 + }
3846 + }
3847 +
3848 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3849 + AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
3850 +}
3851 +
3852 +static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
3853 +{
3854 + struct ath_common *common = ath9k_hw_common(ah);
3855 + u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
3856 + u32 qGainMismatch, iGainMismatch, val, i;
3857 +
3858 + for (i = 0; i < numChains; i++) {
3859 + iOddMeasOffset = ah->totalAdcIOddPhase[i];
3860 + iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
3861 + qOddMeasOffset = ah->totalAdcQOddPhase[i];
3862 + qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
3863 +
3864 + ath_print(common, ATH_DBG_CALIBRATE,
3865 + "Starting ADC Gain Cal for Chain %d\n", i);
3866 +
3867 + ath_print(common, ATH_DBG_CALIBRATE,
3868 + "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
3869 + iOddMeasOffset);
3870 + ath_print(common, ATH_DBG_CALIBRATE,
3871 + "Chn %d pwr_meas_even_i = 0x%08x\n", i,
3872 + iEvenMeasOffset);
3873 + ath_print(common, ATH_DBG_CALIBRATE,
3874 + "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
3875 + qOddMeasOffset);
3876 + ath_print(common, ATH_DBG_CALIBRATE,
3877 + "Chn %d pwr_meas_even_q = 0x%08x\n", i,
3878 + qEvenMeasOffset);
3879 +
3880 + if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
3881 + iGainMismatch =
3882 + ((iEvenMeasOffset * 32) /
3883 + iOddMeasOffset) & 0x3f;
3884 + qGainMismatch =
3885 + ((qOddMeasOffset * 32) /
3886 + qEvenMeasOffset) & 0x3f;
3887 +
3888 + ath_print(common, ATH_DBG_CALIBRATE,
3889 + "Chn %d gain_mismatch_i = 0x%08x\n", i,
3890 + iGainMismatch);
3891 + ath_print(common, ATH_DBG_CALIBRATE,
3892 + "Chn %d gain_mismatch_q = 0x%08x\n", i,
3893 + qGainMismatch);
3894 +
3895 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3896 + val &= 0xfffff000;
3897 + val |= (qGainMismatch) | (iGainMismatch << 6);
3898 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3899 +
3900 + ath_print(common, ATH_DBG_CALIBRATE,
3901 + "ADC Gain Cal done for Chain %d\n", i);
3902 + }
3903 + }
3904 +
3905 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3906 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3907 + AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
3908 +}
3909 +
3910 +static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
3911 +{
3912 + struct ath_common *common = ath9k_hw_common(ah);
3913 + u32 iOddMeasOffset, iEvenMeasOffset, val, i;
3914 + int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
3915 + const struct ath9k_percal_data *calData =
3916 + ah->cal_list_curr->calData;
3917 + u32 numSamples =
3918 + (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
3919 +
3920 + for (i = 0; i < numChains; i++) {
3921 + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
3922 + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
3923 + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
3924 + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
3925 +
3926 + ath_print(common, ATH_DBG_CALIBRATE,
3927 + "Starting ADC DC Offset Cal for Chain %d\n", i);
3928 +
3929 + ath_print(common, ATH_DBG_CALIBRATE,
3930 + "Chn %d pwr_meas_odd_i = %d\n", i,
3931 + iOddMeasOffset);
3932 + ath_print(common, ATH_DBG_CALIBRATE,
3933 + "Chn %d pwr_meas_even_i = %d\n", i,
3934 + iEvenMeasOffset);
3935 + ath_print(common, ATH_DBG_CALIBRATE,
3936 + "Chn %d pwr_meas_odd_q = %d\n", i,
3937 + qOddMeasOffset);
3938 + ath_print(common, ATH_DBG_CALIBRATE,
3939 + "Chn %d pwr_meas_even_q = %d\n", i,
3940 + qEvenMeasOffset);
3941 +
3942 + iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
3943 + numSamples) & 0x1ff;
3944 + qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
3945 + numSamples) & 0x1ff;
3946 +
3947 + ath_print(common, ATH_DBG_CALIBRATE,
3948 + "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
3949 + iDcMismatch);
3950 + ath_print(common, ATH_DBG_CALIBRATE,
3951 + "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
3952 + qDcMismatch);
3953 +
3954 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
3955 + val &= 0xc0000fff;
3956 + val |= (qDcMismatch << 12) | (iDcMismatch << 21);
3957 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
3958 +
3959 + ath_print(common, ATH_DBG_CALIBRATE,
3960 + "ADC DC Offset Cal done for Chain %d\n", i);
3961 + }
3962 +
3963 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
3964 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
3965 + AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
3966 +}
3967 +
3968 +static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
3969 +{
3970 + u32 rddata;
3971 + int32_t delta, currPDADC, slope;
3972 +
3973 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
3974 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
3975 +
3976 + if (ah->initPDADC == 0 || currPDADC == 0) {
3977 + /*
3978 + * Zero value indicates that no frames have been transmitted
3979 + * yet, can't do temperature compensation until frames are
3980 + * transmitted.
3981 + */
3982 + return;
3983 + } else {
3984 + slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
3985 +
3986 + if (slope == 0) { /* to avoid divide by zero case */
3987 + delta = 0;
3988 + } else {
3989 + delta = ((currPDADC - ah->initPDADC)*4) / slope;
3990 + }
3991 + REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
3992 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3993 + REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
3994 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
3995 + }
3996 +}
3997 +
3998 +static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
3999 +{
4000 + u32 rddata, i;
4001 + int delta, currPDADC, regval;
4002 +
4003 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4004 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4005 +
4006 + if (ah->initPDADC == 0 || currPDADC == 0)
4007 + return;
4008 +
4009 + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
4010 + delta = (currPDADC - ah->initPDADC + 4) / 8;
4011 + else
4012 + delta = (currPDADC - ah->initPDADC + 5) / 10;
4013 +
4014 + if (delta != ah->PDADCdelta) {
4015 + ah->PDADCdelta = delta;
4016 + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
4017 + regval = ah->originalGain[i] - delta;
4018 + if (regval < 0)
4019 + regval = 0;
4020 +
4021 + REG_RMW_FIELD(ah,
4022 + AR_PHY_TX_GAIN_TBL1 + i * 4,
4023 + AR_PHY_TX_GAIN, regval);
4024 + }
4025 + }
4026 +}
4027 +
4028 +static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4029 +{
4030 + u32 regVal;
4031 + unsigned int i;
4032 + u32 regList[][2] = {
4033 + { 0x786c, 0 },
4034 + { 0x7854, 0 },
4035 + { 0x7820, 0 },
4036 + { 0x7824, 0 },
4037 + { 0x7868, 0 },
4038 + { 0x783c, 0 },
4039 + { 0x7838, 0 } ,
4040 + { 0x7828, 0 } ,
4041 + };
4042 +
4043 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4044 + regList[i][1] = REG_READ(ah, regList[i][0]);
4045 +
4046 + regVal = REG_READ(ah, 0x7834);
4047 + regVal &= (~(0x1));
4048 + REG_WRITE(ah, 0x7834, regVal);
4049 + regVal = REG_READ(ah, 0x9808);
4050 + regVal |= (0x1 << 27);
4051 + REG_WRITE(ah, 0x9808, regVal);
4052 +
4053 + /* 786c,b23,1, pwddac=1 */
4054 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4055 + /* 7854, b5,1, pdrxtxbb=1 */
4056 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4057 + /* 7854, b7,1, pdv2i=1 */
4058 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4059 + /* 7854, b8,1, pddacinterface=1 */
4060 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4061 + /* 7824,b12,0, offcal=0 */
4062 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4063 + /* 7838, b1,0, pwddb=0 */
4064 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4065 + /* 7820,b11,0, enpacal=0 */
4066 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4067 + /* 7820,b25,1, pdpadrv1=0 */
4068 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4069 + /* 7820,b24,0, pdpadrv2=0 */
4070 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4071 + /* 7820,b23,0, pdpaout=0 */
4072 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4073 + /* 783c,b14-16,7, padrvgn2tab_0=7 */
4074 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4075 + /*
4076 + * 7838,b29-31,0, padrvgn1tab_0=0
4077 + * does not matter since we turn it off
4078 + */
4079 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4080 +
4081 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
4082 +
4083 + /* Set:
4084 + * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
4085 + * txon=1,paon=1,oscon=1,synthon_force=1
4086 + */
4087 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4088 + udelay(30);
4089 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
4090 +
4091 + /* find off_6_1; */
4092 + for (i = 6; i > 0; i--) {
4093 + regVal = REG_READ(ah, 0x7834);
4094 + regVal |= (1 << (20 + i));
4095 + REG_WRITE(ah, 0x7834, regVal);
4096 + udelay(1);
4097 + /* regVal = REG_READ(ah, 0x7834); */
4098 + regVal &= (~(0x1 << (20 + i)));
4099 + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
4100 + << (20 + i));
4101 + REG_WRITE(ah, 0x7834, regVal);
4102 + }
4103 +
4104 + regVal = (regVal >> 20) & 0x7f;
4105 +
4106 + /* Update PA cal info */
4107 + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
4108 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4109 + ah->pacal_info.max_skipcount =
4110 + 2 * ah->pacal_info.max_skipcount;
4111 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4112 + } else {
4113 + ah->pacal_info.max_skipcount = 1;
4114 + ah->pacal_info.skipcount = 0;
4115 + ah->pacal_info.prev_offset = regVal;
4116 + }
4117 +
4118 + regVal = REG_READ(ah, 0x7834);
4119 + regVal |= 0x1;
4120 + REG_WRITE(ah, 0x7834, regVal);
4121 + regVal = REG_READ(ah, 0x9808);
4122 + regVal &= (~(0x1 << 27));
4123 + REG_WRITE(ah, 0x9808, regVal);
4124 +
4125 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4126 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4127 +}
4128 +
4129 +static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4130 +{
4131 + struct ath_common *common = ath9k_hw_common(ah);
4132 + u32 regVal;
4133 + int i, offset, offs_6_1, offs_0;
4134 + u32 ccomp_org, reg_field;
4135 + u32 regList[][2] = {
4136 + { 0x786c, 0 },
4137 + { 0x7854, 0 },
4138 + { 0x7820, 0 },
4139 + { 0x7824, 0 },
4140 + { 0x7868, 0 },
4141 + { 0x783c, 0 },
4142 + { 0x7838, 0 },
4143 + };
4144 +
4145 + ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
4146 +
4147 + /* PA CAL is not needed for high power solution */
4148 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
4149 + AR5416_EEP_TXGAIN_HIGH_POWER)
4150 + return;
4151 +
4152 + if (AR_SREV_9285_11(ah)) {
4153 + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
4154 + udelay(10);
4155 + }
4156 +
4157 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4158 + regList[i][1] = REG_READ(ah, regList[i][0]);
4159 +
4160 + regVal = REG_READ(ah, 0x7834);
4161 + regVal &= (~(0x1));
4162 + REG_WRITE(ah, 0x7834, regVal);
4163 + regVal = REG_READ(ah, 0x9808);
4164 + regVal |= (0x1 << 27);
4165 + REG_WRITE(ah, 0x9808, regVal);
4166 +
4167 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4168 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4169 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4170 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4171 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4172 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4173 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4174 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4175 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4176 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4177 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4178 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4179 + ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
4180 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
4181 +
4182 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4183 + udelay(30);
4184 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
4185 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
4186 +
4187 + for (i = 6; i > 0; i--) {
4188 + regVal = REG_READ(ah, 0x7834);
4189 + regVal |= (1 << (19 + i));
4190 + REG_WRITE(ah, 0x7834, regVal);
4191 + udelay(1);
4192 + regVal = REG_READ(ah, 0x7834);
4193 + regVal &= (~(0x1 << (19 + i)));
4194 + reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
4195 + regVal |= (reg_field << (19 + i));
4196 + REG_WRITE(ah, 0x7834, regVal);
4197 + }
4198 +
4199 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
4200 + udelay(1);
4201 + reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
4202 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
4203 + offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
4204 + offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
4205 +
4206 + offset = (offs_6_1<<1) | offs_0;
4207 + offset = offset - 0;
4208 + offs_6_1 = offset>>1;
4209 + offs_0 = offset & 1;
4210 +
4211 + if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
4212 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4213 + ah->pacal_info.max_skipcount =
4214 + 2 * ah->pacal_info.max_skipcount;
4215 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4216 + } else {
4217 + ah->pacal_info.max_skipcount = 1;
4218 + ah->pacal_info.skipcount = 0;
4219 + ah->pacal_info.prev_offset = offset;
4220 + }
4221 +
4222 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
4223 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
4224 +
4225 + regVal = REG_READ(ah, 0x7834);
4226 + regVal |= 0x1;
4227 + REG_WRITE(ah, 0x7834, regVal);
4228 + regVal = REG_READ(ah, 0x9808);
4229 + regVal &= (~(0x1 << 27));
4230 + REG_WRITE(ah, 0x9808, regVal);
4231 +
4232 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4233 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4234 +
4235 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
4236 +
4237 + if (AR_SREV_9285_11(ah))
4238 + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
4239 +
4240 +}
4241 +
4242 +static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4243 +{
4244 + if (AR_SREV_9271(ah)) {
4245 + if (is_reset || !ah->pacal_info.skipcount)
4246 + ar9271_hw_pa_cal(ah, is_reset);
4247 + else
4248 + ah->pacal_info.skipcount--;
4249 + } else if (AR_SREV_9285_11_OR_LATER(ah)) {
4250 + if (is_reset || !ah->pacal_info.skipcount)
4251 + ar9285_hw_pa_cal(ah, is_reset);
4252 + else
4253 + ah->pacal_info.skipcount--;
4254 + }
4255 +}
4256 +
4257 +static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
4258 +{
4259 + if (OLC_FOR_AR9287_10_LATER)
4260 + ar9287_hw_olc_temp_compensation(ah);
4261 + else if (OLC_FOR_AR9280_20_LATER)
4262 + ar9280_hw_olc_temp_compensation(ah);
4263 +}
4264 +
4265 +static bool ar9002_hw_calibrate(struct ath_hw *ah,
4266 + struct ath9k_channel *chan,
4267 + u8 rxchainmask,
4268 + bool longcal)
4269 +{
4270 + bool iscaldone = true;
4271 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
4272 +
4273 + if (currCal &&
4274 + (currCal->calState == CAL_RUNNING ||
4275 + currCal->calState == CAL_WAITING)) {
4276 + iscaldone = ar9002_hw_per_calibration(ah, chan,
4277 + rxchainmask, currCal);
4278 + if (iscaldone) {
4279 + ah->cal_list_curr = currCal = currCal->calNext;
4280 +
4281 + if (currCal->calState == CAL_WAITING) {
4282 + iscaldone = false;
4283 + ath9k_hw_reset_calibration(ah, currCal);
4284 + }
4285 + }
4286 + }
4287 +
4288 + /* Do NF cal only at longer intervals */
4289 + if (longcal) {
4290 + /* Do periodic PAOffset Cal */
4291 + ar9002_hw_pa_cal(ah, false);
4292 + ar9002_hw_olc_temp_compensation(ah);
4293 +
4294 + /*
4295 + * Get the value from the previous NF cal and update
4296 + * history buffer.
4297 + */
4298 + ath9k_hw_getnf(ah, chan);
4299 +
4300 + /*
4301 + * Load the NF from history buffer of the current channel.
4302 + * NF is slow time-variant, so it is OK to use a historical
4303 + * value.
4304 + */
4305 + ath9k_hw_loadnf(ah, ah->curchan);
4306 +
4307 + ath9k_hw_start_nfcal(ah);
4308 + }
4309 +
4310 + return iscaldone;
4311 +}
4312 +
4313 +/* Carrier leakage Calibration fix */
4314 +static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4315 +{
4316 + struct ath_common *common = ath9k_hw_common(ah);
4317 +
4318 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4319 + if (IS_CHAN_HT20(chan)) {
4320 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4321 + REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4322 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4323 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4324 + REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4325 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4326 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
4327 + AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
4328 + ath_print(common, ATH_DBG_CALIBRATE, "offset "
4329 + "calibration failed to complete in "
4330 + "1ms; noisy ??\n");
4331 + return false;
4332 + }
4333 + REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4334 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4335 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4336 + }
4337 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4338 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4339 + REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4340 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4341 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4342 + 0, AH_WAIT_TIMEOUT)) {
4343 + ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
4344 + "failed to complete in 1ms; noisy ??\n");
4345 + return false;
4346 + }
4347 +
4348 + REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4349 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4350 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4351 +
4352 + return true;
4353 +}
4354 +
4355 +static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
4356 +{
4357 + int i;
4358 + u_int32_t txgain_max;
4359 + u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
4360 + u_int32_t reg_clc_I0, reg_clc_Q0;
4361 + u_int32_t i0_num = 0;
4362 + u_int32_t q0_num = 0;
4363 + u_int32_t total_num = 0;
4364 + u_int32_t reg_rf2g5_org;
4365 + bool retv = true;
4366 +
4367 + if (!(ar9285_hw_cl_cal(ah, chan)))
4368 + return false;
4369 +
4370 + txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
4371 + AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
4372 +
4373 + for (i = 0; i < (txgain_max+1); i++) {
4374 + clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
4375 + AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
4376 + if (!(gain_mask & (1 << clc_gain))) {
4377 + gain_mask |= (1 << clc_gain);
4378 + clc_num++;
4379 + }
4380 + }
4381 +
4382 + for (i = 0; i < clc_num; i++) {
4383 + reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4384 + & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
4385 + reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4386 + & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
4387 + if (reg_clc_I0 == 0)
4388 + i0_num++;
4389 +
4390 + if (reg_clc_Q0 == 0)
4391 + q0_num++;
4392 + }
4393 + total_num = i0_num + q0_num;
4394 + if (total_num > AR9285_CLCAL_REDO_THRESH) {
4395 + reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
4396 + if (AR_SREV_9285E_20(ah)) {
4397 + REG_WRITE(ah, AR9285_RF2G5,
4398 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4399 + AR9285_RF2G5_IC50TX_XE_SET);
4400 + } else {
4401 + REG_WRITE(ah, AR9285_RF2G5,
4402 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4403 + AR9285_RF2G5_IC50TX_SET);
4404 + }
4405 + retv = ar9285_hw_cl_cal(ah, chan);
4406 + REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
4407 + }
4408 + return retv;
4409 +}
4410 +
4411 +static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4412 +{
4413 + struct ath_common *common = ath9k_hw_common(ah);
4414 +
4415 + if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
4416 + if (!ar9285_hw_clc(ah, chan))
4417 + return false;
4418 + } else {
4419 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4420 + if (!AR_SREV_9287_10_OR_LATER(ah))
4421 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
4422 + AR_PHY_ADC_CTL_OFF_PWDADC);
4423 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
4424 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4425 + }
4426 +
4427 + /* Calibrate the AGC */
4428 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4429 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
4430 + AR_PHY_AGC_CONTROL_CAL);
4431 +
4432 + /* Poll for offset calibration complete */
4433 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
4434 + AR_PHY_AGC_CONTROL_CAL,
4435 + 0, AH_WAIT_TIMEOUT)) {
4436 + ath_print(common, ATH_DBG_CALIBRATE,
4437 + "offset calibration failed to "
4438 + "complete in 1ms; noisy environment?\n");
4439 + return false;
4440 + }
4441 +
4442 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4443 + if (!AR_SREV_9287_10_OR_LATER(ah))
4444 + REG_SET_BIT(ah, AR_PHY_ADC_CTL,
4445 + AR_PHY_ADC_CTL_OFF_PWDADC);
4446 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4447 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4448 + }
4449 + }
4450 +
4451 + /* Do PA Calibration */
4452 + ar9002_hw_pa_cal(ah, true);
4453 +
4454 + /* Do NF Calibration after DC offset and other calibrations */
4455 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4456 + REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
4457 +
4458 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
4459 +
4460 + /* Enable IQ, ADC Gain and ADC DC offset CALs */
4461 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
4462 + if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
4463 + INIT_CAL(&ah->adcgain_caldata);
4464 + INSERT_CAL(ah, &ah->adcgain_caldata);
4465 + ath_print(common, ATH_DBG_CALIBRATE,
4466 + "enabling ADC Gain Calibration.\n");
4467 + }
4468 + if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
4469 + INIT_CAL(&ah->adcdc_caldata);
4470 + INSERT_CAL(ah, &ah->adcdc_caldata);
4471 + ath_print(common, ATH_DBG_CALIBRATE,
4472 + "enabling ADC DC Calibration.\n");
4473 + }
4474 + if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
4475 + INIT_CAL(&ah->iq_caldata);
4476 + INSERT_CAL(ah, &ah->iq_caldata);
4477 + ath_print(common, ATH_DBG_CALIBRATE,
4478 + "enabling IQ Calibration.\n");
4479 + }
4480 +
4481 + ah->cal_list_curr = ah->cal_list;
4482 +
4483 + if (ah->cal_list_curr)
4484 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
4485 + }
4486 +
4487 + chan->CalValid = 0;
4488 +
4489 + return true;
4490 +}
4491 +
4492 +static const struct ath9k_percal_data iq_cal_multi_sample = {
4493 + IQ_MISMATCH_CAL,
4494 + MAX_CAL_SAMPLES,
4495 + PER_MIN_LOG_COUNT,
4496 + ar9002_hw_iqcal_collect,
4497 + ar9002_hw_iqcalibrate
4498 +};
4499 +static const struct ath9k_percal_data iq_cal_single_sample = {
4500 + IQ_MISMATCH_CAL,
4501 + MIN_CAL_SAMPLES,
4502 + PER_MAX_LOG_COUNT,
4503 + ar9002_hw_iqcal_collect,
4504 + ar9002_hw_iqcalibrate
4505 +};
4506 +static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
4507 + ADC_GAIN_CAL,
4508 + MAX_CAL_SAMPLES,
4509 + PER_MIN_LOG_COUNT,
4510 + ar9002_hw_adc_gaincal_collect,
4511 + ar9002_hw_adc_gaincal_calibrate
4512 +};
4513 +static const struct ath9k_percal_data adc_gain_cal_single_sample = {
4514 + ADC_GAIN_CAL,
4515 + MIN_CAL_SAMPLES,
4516 + PER_MAX_LOG_COUNT,
4517 + ar9002_hw_adc_gaincal_collect,
4518 + ar9002_hw_adc_gaincal_calibrate
4519 +};
4520 +static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
4521 + ADC_DC_CAL,
4522 + MAX_CAL_SAMPLES,
4523 + PER_MIN_LOG_COUNT,
4524 + ar9002_hw_adc_dccal_collect,
4525 + ar9002_hw_adc_dccal_calibrate
4526 +};
4527 +static const struct ath9k_percal_data adc_dc_cal_single_sample = {
4528 + ADC_DC_CAL,
4529 + MIN_CAL_SAMPLES,
4530 + PER_MAX_LOG_COUNT,
4531 + ar9002_hw_adc_dccal_collect,
4532 + ar9002_hw_adc_dccal_calibrate
4533 +};
4534 +static const struct ath9k_percal_data adc_init_dc_cal = {
4535 + ADC_DC_INIT_CAL,
4536 + MIN_CAL_SAMPLES,
4537 + INIT_LOG_COUNT,
4538 + ar9002_hw_adc_dccal_collect,
4539 + ar9002_hw_adc_dccal_calibrate
4540 +};
4541 +
4542 +static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
4543 +{
4544 + if (AR_SREV_9100(ah)) {
4545 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4546 + ah->supp_cals = IQ_MISMATCH_CAL;
4547 + return;
4548 + }
4549 +
4550 + if (AR_SREV_9160_10_OR_LATER(ah)) {
4551 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4552 + ah->iq_caldata.calData = &iq_cal_single_sample;
4553 + ah->adcgain_caldata.calData =
4554 + &adc_gain_cal_single_sample;
4555 + ah->adcdc_caldata.calData =
4556 + &adc_dc_cal_single_sample;
4557 + ah->adcdc_calinitdata.calData =
4558 + &adc_init_dc_cal;
4559 + } else {
4560 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4561 + ah->adcgain_caldata.calData =
4562 + &adc_gain_cal_multi_sample;
4563 + ah->adcdc_caldata.calData =
4564 + &adc_dc_cal_multi_sample;
4565 + ah->adcdc_calinitdata.calData =
4566 + &adc_init_dc_cal;
4567 + }
4568 + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
4569 + }
4570 +}
4571 +
4572 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
4573 +{
4574 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
4575 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
4576 +
4577 + priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
4578 + priv_ops->init_cal = ar9002_hw_init_cal;
4579 + priv_ops->setup_calibration = ar9002_hw_setup_calibration;
4580 + priv_ops->iscal_supported = ar9002_hw_iscal_supported;
4581 +
4582 + ops->calibrate = ar9002_hw_calibrate;
4583 +}
4584 --- /dev/null
4585 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
4586 @@ -0,0 +1,588 @@
4587 +/*
4588 + * Copyright (c) 2008-2010 Atheros Communications Inc.
4589 + *
4590 + * Permission to use, copy, modify, and/or distribute this software for any
4591 + * purpose with or without fee is hereby granted, provided that the above
4592 + * copyright notice and this permission notice appear in all copies.
4593 + *
4594 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4595 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4596 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4597 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4598 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4599 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4600 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4601 + */
4602 +
4603 +#include "hw.h"
4604 +#include "ar5008_initvals.h"
4605 +#include "ar9001_initvals.h"
4606 +#include "ar9002_initvals.h"
4607 +
4608 +/* General hardware code for the A5008/AR9001/AR9002 hadware families */
4609 +
4610 +static bool ar9002_hw_macversion_supported(u32 macversion)
4611 +{
4612 + switch (macversion) {
4613 + case AR_SREV_VERSION_5416_PCI:
4614 + case AR_SREV_VERSION_5416_PCIE:
4615 + case AR_SREV_VERSION_9160:
4616 + case AR_SREV_VERSION_9100:
4617 + case AR_SREV_VERSION_9280:
4618 + case AR_SREV_VERSION_9285:
4619 + case AR_SREV_VERSION_9287:
4620 + case AR_SREV_VERSION_9271:
4621 + return true;
4622 + default:
4623 + break;
4624 + }
4625 + return false;
4626 +}
4627 +
4628 +static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
4629 +{
4630 + if (AR_SREV_9271(ah)) {
4631 + INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
4632 + ARRAY_SIZE(ar9271Modes_9271), 6);
4633 + INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
4634 + ARRAY_SIZE(ar9271Common_9271), 2);
4635 + INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
4636 + ar9271Common_normal_cck_fir_coeff_9271,
4637 + ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
4638 + INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
4639 + ar9271Common_japan_2484_cck_fir_coeff_9271,
4640 + ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
4641 + INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
4642 + ar9271Modes_9271_1_0_only,
4643 + ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
4644 + INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
4645 + ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
4646 + INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
4647 + ar9271Modes_high_power_tx_gain_9271,
4648 + ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
4649 + INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
4650 + ar9271Modes_normal_power_tx_gain_9271,
4651 + ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
4652 + return;
4653 + }
4654 +
4655 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4656 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
4657 + ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
4658 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
4659 + ARRAY_SIZE(ar9287Common_9287_1_1), 2);
4660 + if (ah->config.pcie_clock_req)
4661 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4662 + ar9287PciePhy_clkreq_off_L1_9287_1_1,
4663 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
4664 + else
4665 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4666 + ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
4667 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
4668 + 2);
4669 + } else if (AR_SREV_9287_10_OR_LATER(ah)) {
4670 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
4671 + ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
4672 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
4673 + ARRAY_SIZE(ar9287Common_9287_1_0), 2);
4674 +
4675 + if (ah->config.pcie_clock_req)
4676 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4677 + ar9287PciePhy_clkreq_off_L1_9287_1_0,
4678 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
4679 + else
4680 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4681 + ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
4682 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
4683 + 2);
4684 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4685 +
4686 +
4687 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
4688 + ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
4689 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
4690 + ARRAY_SIZE(ar9285Common_9285_1_2), 2);
4691 +
4692 + if (ah->config.pcie_clock_req) {
4693 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4694 + ar9285PciePhy_clkreq_off_L1_9285_1_2,
4695 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
4696 + } else {
4697 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4698 + ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
4699 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
4700 + 2);
4701 + }
4702 + } else if (AR_SREV_9285_10_OR_LATER(ah)) {
4703 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
4704 + ARRAY_SIZE(ar9285Modes_9285), 6);
4705 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
4706 + ARRAY_SIZE(ar9285Common_9285), 2);
4707 +
4708 + if (ah->config.pcie_clock_req) {
4709 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4710 + ar9285PciePhy_clkreq_off_L1_9285,
4711 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
4712 + } else {
4713 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4714 + ar9285PciePhy_clkreq_always_on_L1_9285,
4715 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
4716 + }
4717 + } else if (AR_SREV_9280_20_OR_LATER(ah)) {
4718 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
4719 + ARRAY_SIZE(ar9280Modes_9280_2), 6);
4720 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
4721 + ARRAY_SIZE(ar9280Common_9280_2), 2);
4722 +
4723 + if (ah->config.pcie_clock_req) {
4724 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4725 + ar9280PciePhy_clkreq_off_L1_9280,
4726 + ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
4727 + } else {
4728 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4729 + ar9280PciePhy_clkreq_always_on_L1_9280,
4730 + ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
4731 + }
4732 + INIT_INI_ARRAY(&ah->iniModesAdditional,
4733 + ar9280Modes_fast_clock_9280_2,
4734 + ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
4735 + } else if (AR_SREV_9280_10_OR_LATER(ah)) {
4736 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
4737 + ARRAY_SIZE(ar9280Modes_9280), 6);
4738 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
4739 + ARRAY_SIZE(ar9280Common_9280), 2);
4740 + } else if (AR_SREV_9160_10_OR_LATER(ah)) {
4741 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
4742 + ARRAY_SIZE(ar5416Modes_9160), 6);
4743 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
4744 + ARRAY_SIZE(ar5416Common_9160), 2);
4745 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
4746 + ARRAY_SIZE(ar5416Bank0_9160), 2);
4747 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
4748 + ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
4749 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
4750 + ARRAY_SIZE(ar5416Bank1_9160), 2);
4751 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
4752 + ARRAY_SIZE(ar5416Bank2_9160), 2);
4753 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
4754 + ARRAY_SIZE(ar5416Bank3_9160), 3);
4755 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
4756 + ARRAY_SIZE(ar5416Bank6_9160), 3);
4757 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
4758 + ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
4759 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
4760 + ARRAY_SIZE(ar5416Bank7_9160), 2);
4761 + if (AR_SREV_9160_11(ah)) {
4762 + INIT_INI_ARRAY(&ah->iniAddac,
4763 + ar5416Addac_91601_1,
4764 + ARRAY_SIZE(ar5416Addac_91601_1), 2);
4765 + } else {
4766 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
4767 + ARRAY_SIZE(ar5416Addac_9160), 2);
4768 + }
4769 + } else if (AR_SREV_9100_OR_LATER(ah)) {
4770 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
4771 + ARRAY_SIZE(ar5416Modes_9100), 6);
4772 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
4773 + ARRAY_SIZE(ar5416Common_9100), 2);
4774 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
4775 + ARRAY_SIZE(ar5416Bank0_9100), 2);
4776 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
4777 + ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
4778 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
4779 + ARRAY_SIZE(ar5416Bank1_9100), 2);
4780 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
4781 + ARRAY_SIZE(ar5416Bank2_9100), 2);
4782 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
4783 + ARRAY_SIZE(ar5416Bank3_9100), 3);
4784 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
4785 + ARRAY_SIZE(ar5416Bank6_9100), 3);
4786 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
4787 + ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
4788 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
4789 + ARRAY_SIZE(ar5416Bank7_9100), 2);
4790 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
4791 + ARRAY_SIZE(ar5416Addac_9100), 2);
4792 + } else {
4793 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
4794 + ARRAY_SIZE(ar5416Modes), 6);
4795 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
4796 + ARRAY_SIZE(ar5416Common), 2);
4797 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
4798 + ARRAY_SIZE(ar5416Bank0), 2);
4799 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
4800 + ARRAY_SIZE(ar5416BB_RfGain), 3);
4801 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
4802 + ARRAY_SIZE(ar5416Bank1), 2);
4803 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
4804 + ARRAY_SIZE(ar5416Bank2), 2);
4805 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
4806 + ARRAY_SIZE(ar5416Bank3), 3);
4807 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
4808 + ARRAY_SIZE(ar5416Bank6), 3);
4809 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
4810 + ARRAY_SIZE(ar5416Bank6TPC), 3);
4811 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
4812 + ARRAY_SIZE(ar5416Bank7), 2);
4813 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
4814 + ARRAY_SIZE(ar5416Addac), 2);
4815 + }
4816 +}
4817 +
4818 +/* Support for Japan ch.14 (2484) spread */
4819 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
4820 +{
4821 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4822 + INIT_INI_ARRAY(&ah->iniCckfirNormal,
4823 + ar9287Common_normal_cck_fir_coeff_92871_1,
4824 + ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1),
4825 + 2);
4826 + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
4827 + ar9287Common_japan_2484_cck_fir_coeff_92871_1,
4828 + ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1),
4829 + 2);
4830 + }
4831 +}
4832 +
4833 +static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
4834 +{
4835 + u32 rxgain_type;
4836 +
4837 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
4838 + AR5416_EEP_MINOR_VER_17) {
4839 + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
4840 +
4841 + if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
4842 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4843 + ar9280Modes_backoff_13db_rxgain_9280_2,
4844 + ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
4845 + else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
4846 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4847 + ar9280Modes_backoff_23db_rxgain_9280_2,
4848 + ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
4849 + else
4850 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4851 + ar9280Modes_original_rxgain_9280_2,
4852 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4853 + } else {
4854 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4855 + ar9280Modes_original_rxgain_9280_2,
4856 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4857 + }
4858 +}
4859 +
4860 +static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
4861 +{
4862 + u32 txgain_type;
4863 +
4864 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
4865 + AR5416_EEP_MINOR_VER_19) {
4866 + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4867 +
4868 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
4869 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4870 + ar9280Modes_high_power_tx_gain_9280_2,
4871 + ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
4872 + else
4873 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4874 + ar9280Modes_original_tx_gain_9280_2,
4875 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4876 + } else {
4877 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4878 + ar9280Modes_original_tx_gain_9280_2,
4879 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4880 + }
4881 +}
4882 +
4883 +static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
4884 +{
4885 + if (AR_SREV_9287_11_OR_LATER(ah))
4886 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4887 + ar9287Modes_rx_gain_9287_1_1,
4888 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
4889 + else if (AR_SREV_9287_10(ah))
4890 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4891 + ar9287Modes_rx_gain_9287_1_0,
4892 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
4893 + else if (AR_SREV_9280_20(ah))
4894 + ar9280_20_hw_init_rxgain_ini(ah);
4895 +
4896 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4897 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4898 + ar9287Modes_tx_gain_9287_1_1,
4899 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
4900 + } else if (AR_SREV_9287_10(ah)) {
4901 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4902 + ar9287Modes_tx_gain_9287_1_0,
4903 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
4904 + } else if (AR_SREV_9280_20(ah)) {
4905 + ar9280_20_hw_init_txgain_ini(ah);
4906 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4907 + u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4908 +
4909 + /* txgain table */
4910 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
4911 + if (AR_SREV_9285E_20(ah)) {
4912 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4913 + ar9285Modes_XE2_0_high_power,
4914 + ARRAY_SIZE(
4915 + ar9285Modes_XE2_0_high_power), 6);
4916 + } else {
4917 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4918 + ar9285Modes_high_power_tx_gain_9285_1_2,
4919 + ARRAY_SIZE(
4920 + ar9285Modes_high_power_tx_gain_9285_1_2), 6);
4921 + }
4922 + } else {
4923 + if (AR_SREV_9285E_20(ah)) {
4924 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4925 + ar9285Modes_XE2_0_normal_power,
4926 + ARRAY_SIZE(
4927 + ar9285Modes_XE2_0_normal_power), 6);
4928 + } else {
4929 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4930 + ar9285Modes_original_tx_gain_9285_1_2,
4931 + ARRAY_SIZE(
4932 + ar9285Modes_original_tx_gain_9285_1_2), 6);
4933 + }
4934 + }
4935 + }
4936 +}
4937 +
4938 +/*
4939 + * Helper for ASPM support.
4940 + *
4941 + * Disable PLL when in L0s as well as receiver clock when in L1.
4942 + * This power saving option must be enabled through the SerDes.
4943 + *
4944 + * Programming the SerDes must go through the same 288 bit serial shift
4945 + * register as the other analog registers. Hence the 9 writes.
4946 + */
4947 +static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
4948 + int restore,
4949 + int power_off)
4950 +{
4951 + u8 i;
4952 + u32 val;
4953 +
4954 + if (ah->is_pciexpress != true)
4955 + return;
4956 +
4957 + /* Do not touch SerDes registers */
4958 + if (ah->config.pcie_powersave_enable == 2)
4959 + return;
4960 +
4961 + /* Nothing to do on restore for 11N */
4962 + if (!restore) {
4963 + if (AR_SREV_9280_20_OR_LATER(ah)) {
4964 + /*
4965 + * AR9280 2.0 or later chips use SerDes values from the
4966 + * initvals.h initialized depending on chipset during
4967 + * __ath9k_hw_init()
4968 + */
4969 + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
4970 + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
4971 + INI_RA(&ah->iniPcieSerdes, i, 1));
4972 + }
4973 + } else if (AR_SREV_9280(ah) &&
4974 + (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
4975 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
4976 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
4977 +
4978 + /* RX shut off when elecidle is asserted */
4979 + REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
4980 + REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
4981 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
4982 +
4983 + /* Shut off CLKREQ active in L1 */
4984 + if (ah->config.pcie_clock_req)
4985 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
4986 + else
4987 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
4988 +
4989 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
4990 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
4991 + REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
4992 +
4993 + /* Load the new settings */
4994 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
4995 +
4996 + } else {
4997 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
4998 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
4999 +
5000 + /* RX shut off when elecidle is asserted */
5001 + REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
5002 + REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
5003 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
5004 +
5005 + /*
5006 + * Ignore ah->ah_config.pcie_clock_req setting for
5007 + * pre-AR9280 11n
5008 + */
5009 + REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
5010 +
5011 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
5012 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5013 + REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
5014 +
5015 + /* Load the new settings */
5016 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5017 + }
5018 +
5019 + udelay(1000);
5020 +
5021 + /* set bit 19 to allow forcing of pcie core into L1 state */
5022 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
5023 +
5024 + /* Several PCIe massages to ensure proper behaviour */
5025 + if (ah->config.pcie_waen) {
5026 + val = ah->config.pcie_waen;
5027 + if (!power_off)
5028 + val &= (~AR_WA_D3_L1_DISABLE);
5029 + } else {
5030 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5031 + AR_SREV_9287(ah)) {
5032 + val = AR9285_WA_DEFAULT;
5033 + if (!power_off)
5034 + val &= (~AR_WA_D3_L1_DISABLE);
5035 + } else if (AR_SREV_9280(ah)) {
5036 + /*
5037 + * On AR9280 chips bit 22 of 0x4004 needs to be
5038 + * set otherwise card may disappear.
5039 + */
5040 + val = AR9280_WA_DEFAULT;
5041 + if (!power_off)
5042 + val &= (~AR_WA_D3_L1_DISABLE);
5043 + } else
5044 + val = AR_WA_DEFAULT;
5045 + }
5046 +
5047 + REG_WRITE(ah, AR_WA, val);
5048 + }
5049 +
5050 + if (power_off) {
5051 + /*
5052 + * Set PCIe workaround bits
5053 + * bit 14 in WA register (disable L1) should only
5054 + * be set when device enters D3 and be cleared
5055 + * when device comes back to D0.
5056 + */
5057 + if (ah->config.pcie_waen) {
5058 + if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
5059 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5060 + } else {
5061 + if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5062 + AR_SREV_9287(ah)) &&
5063 + (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
5064 + (AR_SREV_9280(ah) &&
5065 + (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
5066 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5067 + }
5068 + }
5069 + }
5070 +}
5071 +
5072 +static int ar9002_hw_get_radiorev(struct ath_hw *ah)
5073 +{
5074 + u32 val;
5075 + int i;
5076 +
5077 + REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
5078 +
5079 + for (i = 0; i < 8; i++)
5080 + REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
5081 + val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
5082 + val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
5083 +
5084 + return ath9k_hw_reverse_bits(val, 8);
5085 +}
5086 +
5087 +int ar9002_hw_rf_claim(struct ath_hw *ah)
5088 +{
5089 + u32 val;
5090 +
5091 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
5092 +
5093 + val = ar9002_hw_get_radiorev(ah);
5094 + switch (val & AR_RADIO_SREV_MAJOR) {
5095 + case 0:
5096 + val = AR_RAD5133_SREV_MAJOR;
5097 + break;
5098 + case AR_RAD5133_SREV_MAJOR:
5099 + case AR_RAD5122_SREV_MAJOR:
5100 + case AR_RAD2133_SREV_MAJOR:
5101 + case AR_RAD2122_SREV_MAJOR:
5102 + break;
5103 + default:
5104 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
5105 + "Radio Chip Rev 0x%02X not supported\n",
5106 + val & AR_RADIO_SREV_MAJOR);
5107 + return -EOPNOTSUPP;
5108 + }
5109 +
5110 + ah->hw_version.analog5GhzRev = val;
5111 +
5112 + return 0;
5113 +}
5114 +
5115 +/*
5116 + * Enable ASYNC FIFO
5117 + *
5118 + * If Async FIFO is enabled, the following counters change as MAC now runs
5119 + * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
5120 + *
5121 + * The values below tested for ht40 2 chain.
5122 + * Overwrite the delay/timeouts initialized in process ini.
5123 + */
5124 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
5125 +{
5126 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5127 + REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
5128 + AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
5129 + REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
5130 + AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
5131 + REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
5132 + AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
5133 +
5134 + REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
5135 + REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
5136 +
5137 + REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
5138 + AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
5139 + REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
5140 + AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
5141 + }
5142 +}
5143 +
5144 +/*
5145 + * We don't enable WEP aggregation on mac80211 but we keep this
5146 + * around for HAL unification purposes.
5147 + */
5148 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
5149 +{
5150 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5151 + REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
5152 + AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
5153 + }
5154 +}
5155 +
5156 +/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
5157 +void ar9002_hw_attach_ops(struct ath_hw *ah)
5158 +{
5159 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
5160 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
5161 +
5162 + priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
5163 + priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
5164 + priv_ops->macversion_supported = ar9002_hw_macversion_supported;
5165 +
5166 + ops->config_pci_powersave = ar9002_hw_configpcipowersave;
5167 +
5168 + ar5008_hw_attach_phy_ops(ah);
5169 + if (AR_SREV_9280_10_OR_LATER(ah))
5170 + ar9002_hw_attach_phy_ops(ah);
5171 +
5172 + ar9002_hw_attach_calib_ops(ah);
5173 + ar9002_hw_attach_mac_ops(ah);
5174 +}
5175 --- /dev/null
5176 +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
5177 @@ -0,0 +1,5230 @@
5178 +/*
5179 + * Copyright (c) 2010 Atheros Communications Inc.
5180 + *
5181 + * Permission to use, copy, modify, and/or distribute this software for any
5182 + * purpose with or without fee is hereby granted, provided that the above
5183 + * copyright notice and this permission notice appear in all copies.
5184 + *
5185 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5186 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5187 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5188 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5189 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5190 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5191 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5192 + */
5193 +
5194 +#ifndef INITVALS_9002_10_H
5195 +#define INITVALS_9002_10_H
5196 +
5197 +static const u32 ar9280Modes_9280[][6] = {
5198 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
5199 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
5200 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
5201 + { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
5202 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
5203 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
5204 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
5205 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
5206 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5207 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
5208 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5209 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
5210 + { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
5211 + { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
5212 + { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
5213 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
5214 + { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
5215 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
5216 + { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
5217 + { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
5218 + { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
5219 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
5220 + { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
5221 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
5222 + { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
5223 + { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
5224 + { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5225 + { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5226 + { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
5227 + { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
5228 + { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
5229 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
5230 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
5231 + { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
5232 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
5233 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
5234 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5235 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5236 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
5237 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
5238 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
5239 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
5240 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
5241 + { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
5242 + { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
5243 + { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
5244 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
5245 + { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
5246 + { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
5247 + { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
5248 + { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
5249 + { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
5250 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
5251 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
5252 + { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
5253 + { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
5254 + { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
5255 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
5256 + { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
5257 + { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
5258 + { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
5259 + { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
5260 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
5261 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
5262 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
5263 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
5264 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
5265 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
5266 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
5267 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
5268 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
5269 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
5270 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
5271 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
5272 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
5273 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
5274 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
5275 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
5276 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
5277 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
5278 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
5279 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
5280 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
5281 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
5282 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
5283 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
5284 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
5285 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
5286 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
5287 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
5288 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
5289 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
5290 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
5291 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
5292 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
5293 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
5294 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
5295 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
5296 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
5297 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
5298 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
5299 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
5300 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
5301 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
5302 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
5303 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
5304 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
5305 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
5306 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
5307 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
5308 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
5309 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
5310 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
5311 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
5312 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
5313 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
5314 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
5315 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
5316 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
5317 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
5318 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
5319 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
5320 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
5321 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
5322 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
5323 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
5324 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
5325 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
5326 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
5327 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
5328 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
5329 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
5330 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
5331 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
5332 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
5333 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
5334 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
5335 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
5336 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
5337 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
5338 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5339 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5340 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5341 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5342 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5343 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5344 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5345 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5346 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5347 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5348 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5349 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5350 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5351 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5352 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5353 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5354 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5355 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5356 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5357 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5358 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5359 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5360 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5361 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5362 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5363 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
5364 + { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
5365 + { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
5366 + { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
5367 + { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
5368 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
5369 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
5370 + { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
5371 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5372 + { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
5373 + { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
5374 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
5375 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
5376 + { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
5377 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
5378 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
5379 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
5380 + { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
5381 + { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
5382 + { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
5383 + { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
5384 + { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
5385 + { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
5386 + { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
5387 + { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
5388 + { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
5389 + { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
5390 + { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
5391 + { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
5392 + { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
5393 + { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
5394 + { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
5395 + { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
5396 + { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
5397 +};
5398 +
5399 +static const u32 ar9280Common_9280[][2] = {
5400 + { 0x0000000c, 0x00000000 },
5401 + { 0x00000030, 0x00020015 },
5402 + { 0x00000034, 0x00000005 },
5403 + { 0x00000040, 0x00000000 },
5404 + { 0x00000044, 0x00000008 },
5405 + { 0x00000048, 0x00000008 },
5406 + { 0x0000004c, 0x00000010 },
5407 + { 0x00000050, 0x00000000 },
5408 + { 0x00000054, 0x0000001f },
5409 + { 0x00000800, 0x00000000 },
5410 + { 0x00000804, 0x00000000 },
5411 + { 0x00000808, 0x00000000 },
5412 + { 0x0000080c, 0x00000000 },
5413 + { 0x00000810, 0x00000000 },
5414 + { 0x00000814, 0x00000000 },
5415 + { 0x00000818, 0x00000000 },
5416 + { 0x0000081c, 0x00000000 },
5417 + { 0x00000820, 0x00000000 },
5418 + { 0x00000824, 0x00000000 },
5419 + { 0x00001040, 0x002ffc0f },
5420 + { 0x00001044, 0x002ffc0f },
5421 + { 0x00001048, 0x002ffc0f },
5422 + { 0x0000104c, 0x002ffc0f },
5423 + { 0x00001050, 0x002ffc0f },
5424 + { 0x00001054, 0x002ffc0f },
5425 + { 0x00001058, 0x002ffc0f },
5426 + { 0x0000105c, 0x002ffc0f },
5427 + { 0x00001060, 0x002ffc0f },
5428 + { 0x00001064, 0x002ffc0f },
5429 + { 0x00001230, 0x00000000 },
5430 + { 0x00001270, 0x00000000 },
5431 + { 0x00001038, 0x00000000 },
5432 + { 0x00001078, 0x00000000 },
5433 + { 0x000010b8, 0x00000000 },
5434 + { 0x000010f8, 0x00000000 },
5435 + { 0x00001138, 0x00000000 },
5436 + { 0x00001178, 0x00000000 },
5437 + { 0x000011b8, 0x00000000 },
5438 + { 0x000011f8, 0x00000000 },
5439 + { 0x00001238, 0x00000000 },
5440 + { 0x00001278, 0x00000000 },
5441 + { 0x000012b8, 0x00000000 },
5442 + { 0x000012f8, 0x00000000 },
5443 + { 0x00001338, 0x00000000 },
5444 + { 0x00001378, 0x00000000 },
5445 + { 0x000013b8, 0x00000000 },
5446 + { 0x000013f8, 0x00000000 },
5447 + { 0x00001438, 0x00000000 },
5448 + { 0x00001478, 0x00000000 },
5449 + { 0x000014b8, 0x00000000 },
5450 + { 0x000014f8, 0x00000000 },
5451 + { 0x00001538, 0x00000000 },
5452 + { 0x00001578, 0x00000000 },
5453 + { 0x000015b8, 0x00000000 },
5454 + { 0x000015f8, 0x00000000 },
5455 + { 0x00001638, 0x00000000 },
5456 + { 0x00001678, 0x00000000 },
5457 + { 0x000016b8, 0x00000000 },
5458 + { 0x000016f8, 0x00000000 },
5459 + { 0x00001738, 0x00000000 },
5460 + { 0x00001778, 0x00000000 },
5461 + { 0x000017b8, 0x00000000 },
5462 + { 0x000017f8, 0x00000000 },
5463 + { 0x0000103c, 0x00000000 },
5464 + { 0x0000107c, 0x00000000 },
5465 + { 0x000010bc, 0x00000000 },
5466 + { 0x000010fc, 0x00000000 },
5467 + { 0x0000113c, 0x00000000 },
5468 + { 0x0000117c, 0x00000000 },
5469 + { 0x000011bc, 0x00000000 },
5470 + { 0x000011fc, 0x00000000 },
5471 + { 0x0000123c, 0x00000000 },
5472 + { 0x0000127c, 0x00000000 },
5473 + { 0x000012bc, 0x00000000 },
5474 + { 0x000012fc, 0x00000000 },
5475 + { 0x0000133c, 0x00000000 },
5476 + { 0x0000137c, 0x00000000 },
5477 + { 0x000013bc, 0x00000000 },
5478 + { 0x000013fc, 0x00000000 },
5479 + { 0x0000143c, 0x00000000 },
5480 + { 0x0000147c, 0x00000000 },
5481 + { 0x00004030, 0x00000002 },
5482 + { 0x0000403c, 0x00000002 },
5483 + { 0x00004024, 0x0000001f },
5484 + { 0x00007010, 0x00000033 },
5485 + { 0x00007038, 0x000004c2 },
5486 + { 0x00008004, 0x00000000 },
5487 + { 0x00008008, 0x00000000 },
5488 + { 0x0000800c, 0x00000000 },
5489 + { 0x00008018, 0x00000700 },
5490 + { 0x00008020, 0x00000000 },
5491 + { 0x00008038, 0x00000000 },
5492 + { 0x0000803c, 0x00000000 },
5493 + { 0x00008048, 0x40000000 },
5494 + { 0x00008054, 0x00000000 },
5495 + { 0x00008058, 0x00000000 },
5496 + { 0x0000805c, 0x000fc78f },
5497 + { 0x00008060, 0x0000000f },
5498 + { 0x00008064, 0x00000000 },
5499 + { 0x00008070, 0x00000000 },
5500 + { 0x000080c0, 0x2a82301a },
5501 + { 0x000080c4, 0x05dc01e0 },
5502 + { 0x000080c8, 0x1f402710 },
5503 + { 0x000080cc, 0x01f40000 },
5504 + { 0x000080d0, 0x00001e00 },
5505 + { 0x000080d4, 0x00000000 },
5506 + { 0x000080d8, 0x00400000 },
5507 + { 0x000080e0, 0xffffffff },
5508 + { 0x000080e4, 0x0000ffff },
5509 + { 0x000080e8, 0x003f3f3f },
5510 + { 0x000080ec, 0x00000000 },
5511 + { 0x000080f0, 0x00000000 },
5512 + { 0x000080f4, 0x00000000 },
5513 + { 0x000080f8, 0x00000000 },
5514 + { 0x000080fc, 0x00020000 },
5515 + { 0x00008100, 0x00020000 },
5516 + { 0x00008104, 0x00000001 },
5517 + { 0x00008108, 0x00000052 },
5518 + { 0x0000810c, 0x00000000 },
5519 + { 0x00008110, 0x00000168 },
5520 + { 0x00008118, 0x000100aa },
5521 + { 0x0000811c, 0x00003210 },
5522 + { 0x00008120, 0x08f04800 },
5523 + { 0x00008124, 0x00000000 },
5524 + { 0x00008128, 0x00000000 },
5525 + { 0x0000812c, 0x00000000 },
5526 + { 0x00008130, 0x00000000 },
5527 + { 0x00008134, 0x00000000 },
5528 + { 0x00008138, 0x00000000 },
5529 + { 0x0000813c, 0x00000000 },
5530 + { 0x00008144, 0x00000000 },
5531 + { 0x00008168, 0x00000000 },
5532 + { 0x0000816c, 0x00000000 },
5533 + { 0x00008170, 0x32143320 },
5534 + { 0x00008174, 0xfaa4fa50 },
5535 + { 0x00008178, 0x00000100 },
5536 + { 0x0000817c, 0x00000000 },
5537 + { 0x000081c4, 0x00000000 },
5538 + { 0x000081d0, 0x00003210 },
5539 + { 0x000081ec, 0x00000000 },
5540 + { 0x000081f0, 0x00000000 },
5541 + { 0x000081f4, 0x00000000 },
5542 + { 0x000081f8, 0x00000000 },
5543 + { 0x000081fc, 0x00000000 },
5544 + { 0x00008200, 0x00000000 },
5545 + { 0x00008204, 0x00000000 },
5546 + { 0x00008208, 0x00000000 },
5547 + { 0x0000820c, 0x00000000 },
5548 + { 0x00008210, 0x00000000 },
5549 + { 0x00008214, 0x00000000 },
5550 + { 0x00008218, 0x00000000 },
5551 + { 0x0000821c, 0x00000000 },
5552 + { 0x00008220, 0x00000000 },
5553 + { 0x00008224, 0x00000000 },
5554 + { 0x00008228, 0x00000000 },
5555 + { 0x0000822c, 0x00000000 },
5556 + { 0x00008230, 0x00000000 },
5557 + { 0x00008234, 0x00000000 },
5558 + { 0x00008238, 0x00000000 },
5559 + { 0x0000823c, 0x00000000 },
5560 + { 0x00008240, 0x00100000 },
5561 + { 0x00008244, 0x0010f400 },
5562 + { 0x00008248, 0x00000100 },
5563 + { 0x0000824c, 0x0001e800 },
5564 + { 0x00008250, 0x00000000 },
5565 + { 0x00008254, 0x00000000 },
5566 + { 0x00008258, 0x00000000 },
5567 + { 0x0000825c, 0x400000ff },
5568 + { 0x00008260, 0x00080922 },
5569 + { 0x00008270, 0x00000000 },
5570 + { 0x00008274, 0x40000000 },
5571 + { 0x00008278, 0x003e4180 },
5572 + { 0x0000827c, 0x00000000 },
5573 + { 0x00008284, 0x0000002c },
5574 + { 0x00008288, 0x0000002c },
5575 + { 0x0000828c, 0x00000000 },
5576 + { 0x00008294, 0x00000000 },
5577 + { 0x00008298, 0x00000000 },
5578 + { 0x00008300, 0x00000000 },
5579 + { 0x00008304, 0x00000000 },
5580 + { 0x00008308, 0x00000000 },
5581 + { 0x0000830c, 0x00000000 },
5582 + { 0x00008310, 0x00000000 },
5583 + { 0x00008314, 0x00000000 },
5584 + { 0x00008318, 0x00000000 },
5585 + { 0x00008328, 0x00000000 },
5586 + { 0x0000832c, 0x00000007 },
5587 + { 0x00008330, 0x00000302 },
5588 + { 0x00008334, 0x00000e00 },
5589 + { 0x00008338, 0x00000000 },
5590 + { 0x0000833c, 0x00000000 },
5591 + { 0x00008340, 0x000107ff },
5592 + { 0x00008344, 0x00000000 },
5593 + { 0x00009808, 0x00000000 },
5594 + { 0x0000980c, 0xaf268e30 },
5595 + { 0x00009810, 0xfd14e000 },
5596 + { 0x00009814, 0x9c0a9f6b },
5597 + { 0x0000981c, 0x00000000 },
5598 + { 0x0000982c, 0x0000a000 },
5599 + { 0x00009830, 0x00000000 },
5600 + { 0x0000983c, 0x00200400 },
5601 + { 0x00009840, 0x206a01ae },
5602 + { 0x0000984c, 0x0040233c },
5603 + { 0x0000a84c, 0x0040233c },
5604 + { 0x00009854, 0x00000044 },
5605 + { 0x00009900, 0x00000000 },
5606 + { 0x00009904, 0x00000000 },
5607 + { 0x00009908, 0x00000000 },
5608 + { 0x0000990c, 0x00000000 },
5609 + { 0x0000991c, 0x10000fff },
5610 + { 0x00009920, 0x04900000 },
5611 + { 0x0000a920, 0x04900000 },
5612 + { 0x00009928, 0x00000001 },
5613 + { 0x0000992c, 0x00000004 },
5614 + { 0x00009934, 0x1e1f2022 },
5615 + { 0x00009938, 0x0a0b0c0d },
5616 + { 0x0000993c, 0x00000000 },
5617 + { 0x00009948, 0x9280c00a },
5618 + { 0x0000994c, 0x00020028 },
5619 + { 0x00009954, 0xe250a51e },
5620 + { 0x00009958, 0x3388ffff },
5621 + { 0x00009940, 0x00781204 },
5622 + { 0x0000c95c, 0x004b6a8e },
5623 + { 0x0000c968, 0x000003ce },
5624 + { 0x00009970, 0x190fb514 },
5625 + { 0x00009974, 0x00000000 },
5626 + { 0x00009978, 0x00000001 },
5627 + { 0x0000997c, 0x00000000 },
5628 + { 0x00009980, 0x00000000 },
5629 + { 0x00009984, 0x00000000 },
5630 + { 0x00009988, 0x00000000 },
5631 + { 0x0000998c, 0x00000000 },
5632 + { 0x00009990, 0x00000000 },
5633 + { 0x00009994, 0x00000000 },
5634 + { 0x00009998, 0x00000000 },
5635 + { 0x0000999c, 0x00000000 },
5636 + { 0x000099a0, 0x00000000 },
5637 + { 0x000099a4, 0x00000001 },
5638 + { 0x000099a8, 0x201fff00 },
5639 + { 0x000099ac, 0x006f00c4 },
5640 + { 0x000099b0, 0x03051000 },
5641 + { 0x000099b4, 0x00000820 },
5642 + { 0x000099dc, 0x00000000 },
5643 + { 0x000099e0, 0x00000000 },
5644 + { 0x000099e4, 0xaaaaaaaa },
5645 + { 0x000099e8, 0x3c466478 },
5646 + { 0x000099ec, 0x0cc80caa },
5647 + { 0x000099fc, 0x00001042 },
5648 + { 0x0000a210, 0x4080a333 },
5649 + { 0x0000a214, 0x40206c10 },
5650 + { 0x0000a218, 0x009c4060 },
5651 + { 0x0000a220, 0x01834061 },
5652 + { 0x0000a224, 0x00000400 },
5653 + { 0x0000a228, 0x000003b5 },
5654 + { 0x0000a22c, 0x23277200 },
5655 + { 0x0000a234, 0x20202020 },
5656 + { 0x0000a238, 0x20202020 },
5657 + { 0x0000a23c, 0x13c889af },
5658 + { 0x0000a240, 0x38490a20 },
5659 + { 0x0000a244, 0x00007bb6 },
5660 + { 0x0000a248, 0x0fff3ffc },
5661 + { 0x0000a24c, 0x00000001 },
5662 + { 0x0000a250, 0x001da000 },
5663 + { 0x0000a254, 0x00000000 },
5664 + { 0x0000a258, 0x0cdbd380 },
5665 + { 0x0000a25c, 0x0f0f0f01 },
5666 + { 0x0000a260, 0xdfa91f01 },
5667 + { 0x0000a268, 0x00000000 },
5668 + { 0x0000a26c, 0x0ebae9c6 },
5669 + { 0x0000b26c, 0x0ebae9c6 },
5670 + { 0x0000d270, 0x00820820 },
5671 + { 0x0000a278, 0x1ce739ce },
5672 + { 0x0000a27c, 0x050701ce },
5673 + { 0x0000a358, 0x7999aa0f },
5674 + { 0x0000d35c, 0x07ffffef },
5675 + { 0x0000d360, 0x0fffffe7 },
5676 + { 0x0000d364, 0x17ffffe5 },
5677 + { 0x0000d368, 0x1fffffe4 },
5678 + { 0x0000d36c, 0x37ffffe3 },
5679 + { 0x0000d370, 0x3fffffe3 },
5680 + { 0x0000d374, 0x57ffffe3 },
5681 + { 0x0000d378, 0x5fffffe2 },
5682 + { 0x0000d37c, 0x7fffffe2 },
5683 + { 0x0000d380, 0x7f3c7bba },
5684 + { 0x0000d384, 0xf3307ff0 },
5685 + { 0x0000a388, 0x0c000000 },
5686 + { 0x0000a38c, 0x20202020 },
5687 + { 0x0000a390, 0x20202020 },
5688 + { 0x0000a394, 0x1ce739ce },
5689 + { 0x0000a398, 0x000001ce },
5690 + { 0x0000a39c, 0x00000001 },
5691 + { 0x0000a3a0, 0x00000000 },
5692 + { 0x0000a3a4, 0x00000000 },
5693 + { 0x0000a3a8, 0x00000000 },
5694 + { 0x0000a3ac, 0x00000000 },
5695 + { 0x0000a3b0, 0x00000000 },
5696 + { 0x0000a3b4, 0x00000000 },
5697 + { 0x0000a3b8, 0x00000000 },
5698 + { 0x0000a3bc, 0x00000000 },
5699 + { 0x0000a3c0, 0x00000000 },
5700 + { 0x0000a3c4, 0x00000000 },
5701 + { 0x0000a3c8, 0x00000246 },
5702 + { 0x0000a3cc, 0x20202020 },
5703 + { 0x0000a3d0, 0x20202020 },
5704 + { 0x0000a3d4, 0x20202020 },
5705 + { 0x0000a3dc, 0x1ce739ce },
5706 + { 0x0000a3e0, 0x000001ce },
5707 + { 0x0000a3e4, 0x00000000 },
5708 + { 0x0000a3e8, 0x18c43433 },
5709 + { 0x0000a3ec, 0x00f38081 },
5710 + { 0x00007800, 0x00040000 },
5711 + { 0x00007804, 0xdb005012 },
5712 + { 0x00007808, 0x04924914 },
5713 + { 0x0000780c, 0x21084210 },
5714 + { 0x00007810, 0x6d801300 },
5715 + { 0x00007814, 0x0019beff },
5716 + { 0x00007818, 0x07e40000 },
5717 + { 0x0000781c, 0x00492000 },
5718 + { 0x00007820, 0x92492480 },
5719 + { 0x00007824, 0x00040000 },
5720 + { 0x00007828, 0xdb005012 },
5721 + { 0x0000782c, 0x04924914 },
5722 + { 0x00007830, 0x21084210 },
5723 + { 0x00007834, 0x6d801300 },
5724 + { 0x00007838, 0x0019beff },
5725 + { 0x0000783c, 0x07e40000 },
5726 + { 0x00007840, 0x00492000 },
5727 + { 0x00007844, 0x92492480 },
5728 + { 0x00007848, 0x00120000 },
5729 + { 0x00007850, 0x54214514 },
5730 + { 0x00007858, 0x92592692 },
5731 + { 0x00007860, 0x52802000 },
5732 + { 0x00007864, 0x0a8e370e },
5733 + { 0x00007868, 0xc0102850 },
5734 + { 0x0000786c, 0x812d4000 },
5735 + { 0x00007874, 0x001b6db0 },
5736 + { 0x00007878, 0x00376b63 },
5737 + { 0x0000787c, 0x06db6db6 },
5738 + { 0x00007880, 0x006d8000 },
5739 + { 0x00007884, 0xffeffffe },
5740 + { 0x00007888, 0xffeffffe },
5741 + { 0x00007890, 0x00060aeb },
5742 + { 0x00007894, 0x5a108000 },
5743 + { 0x00007898, 0x2a850160 },
5744 +};
5745 +
5746 +/* XXX 9280 2 */
5747 +static const u32 ar9280Modes_9280_2[][6] = {
5748 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
5749 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
5750 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
5751 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
5752 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
5753 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
5754 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
5755 + { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
5756 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
5757 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
5758 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
5759 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
5760 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
5761 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
5762 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
5763 + { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
5764 + { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
5765 + { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
5766 + { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
5767 + { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
5768 + { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
5769 + { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
5770 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
5771 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
5772 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
5773 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
5774 + { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
5775 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
5776 + { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5777 + { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
5778 + { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
5779 + { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
5780 + { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
5781 + { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
5782 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
5783 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
5784 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
5785 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
5786 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
5787 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5788 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5789 + { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
5790 + { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
5791 + { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
5792 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
5793 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
5794 + { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
5795 + { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
5796 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
5797 + { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
5798 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5799 + { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
5800 +};
5801 +
5802 +static const u32 ar9280Common_9280_2[][2] = {
5803 + { 0x0000000c, 0x00000000 },
5804 + { 0x00000030, 0x00020015 },
5805 + { 0x00000034, 0x00000005 },
5806 + { 0x00000040, 0x00000000 },
5807 + { 0x00000044, 0x00000008 },
5808 + { 0x00000048, 0x00000008 },
5809 + { 0x0000004c, 0x00000010 },
5810 + { 0x00000050, 0x00000000 },
5811 + { 0x00000054, 0x0000001f },
5812 + { 0x00000800, 0x00000000 },
5813 + { 0x00000804, 0x00000000 },
5814 + { 0x00000808, 0x00000000 },
5815 + { 0x0000080c, 0x00000000 },
5816 + { 0x00000810, 0x00000000 },
5817 + { 0x00000814, 0x00000000 },
5818 + { 0x00000818, 0x00000000 },
5819 + { 0x0000081c, 0x00000000 },
5820 + { 0x00000820, 0x00000000 },
5821 + { 0x00000824, 0x00000000 },
5822 + { 0x00001040, 0x002ffc0f },
5823 + { 0x00001044, 0x002ffc0f },
5824 + { 0x00001048, 0x002ffc0f },
5825 + { 0x0000104c, 0x002ffc0f },
5826 + { 0x00001050, 0x002ffc0f },
5827 + { 0x00001054, 0x002ffc0f },
5828 + { 0x00001058, 0x002ffc0f },
5829 + { 0x0000105c, 0x002ffc0f },
5830 + { 0x00001060, 0x002ffc0f },
5831 + { 0x00001064, 0x002ffc0f },
5832 + { 0x00001230, 0x00000000 },
5833 + { 0x00001270, 0x00000000 },
5834 + { 0x00001038, 0x00000000 },
5835 + { 0x00001078, 0x00000000 },
5836 + { 0x000010b8, 0x00000000 },
5837 + { 0x000010f8, 0x00000000 },
5838 + { 0x00001138, 0x00000000 },
5839 + { 0x00001178, 0x00000000 },
5840 + { 0x000011b8, 0x00000000 },
5841 + { 0x000011f8, 0x00000000 },
5842 + { 0x00001238, 0x00000000 },
5843 + { 0x00001278, 0x00000000 },
5844 + { 0x000012b8, 0x00000000 },
5845 + { 0x000012f8, 0x00000000 },
5846 + { 0x00001338, 0x00000000 },
5847 + { 0x00001378, 0x00000000 },
5848 + { 0x000013b8, 0x00000000 },
5849 + { 0x000013f8, 0x00000000 },
5850 + { 0x00001438, 0x00000000 },
5851 + { 0x00001478, 0x00000000 },
5852 + { 0x000014b8, 0x00000000 },
5853 + { 0x000014f8, 0x00000000 },
5854 + { 0x00001538, 0x00000000 },
5855 + { 0x00001578, 0x00000000 },
5856 + { 0x000015b8, 0x00000000 },
5857 + { 0x000015f8, 0x00000000 },
5858 + { 0x00001638, 0x00000000 },
5859 + { 0x00001678, 0x00000000 },
5860 + { 0x000016b8, 0x00000000 },
5861 + { 0x000016f8, 0x00000000 },
5862 + { 0x00001738, 0x00000000 },
5863 + { 0x00001778, 0x00000000 },
5864 + { 0x000017b8, 0x00000000 },
5865 + { 0x000017f8, 0x00000000 },
5866 + { 0x0000103c, 0x00000000 },
5867 + { 0x0000107c, 0x00000000 },
5868 + { 0x000010bc, 0x00000000 },
5869 + { 0x000010fc, 0x00000000 },
5870 + { 0x0000113c, 0x00000000 },
5871 + { 0x0000117c, 0x00000000 },
5872 + { 0x000011bc, 0x00000000 },
5873 + { 0x000011fc, 0x00000000 },
5874 + { 0x0000123c, 0x00000000 },
5875 + { 0x0000127c, 0x00000000 },
5876 + { 0x000012bc, 0x00000000 },
5877 + { 0x000012fc, 0x00000000 },
5878 + { 0x0000133c, 0x00000000 },
5879 + { 0x0000137c, 0x00000000 },
5880 + { 0x000013bc, 0x00000000 },
5881 + { 0x000013fc, 0x00000000 },
5882 + { 0x0000143c, 0x00000000 },
5883 + { 0x0000147c, 0x00000000 },
5884 + { 0x00004030, 0x00000002 },
5885 + { 0x0000403c, 0x00000002 },
5886 + { 0x00004024, 0x0000001f },
5887 + { 0x00004060, 0x00000000 },
5888 + { 0x00004064, 0x00000000 },
5889 + { 0x00007010, 0x00000033 },
5890 + { 0x00007034, 0x00000002 },
5891 + { 0x00007038, 0x000004c2 },
5892 + { 0x00008004, 0x00000000 },
5893 + { 0x00008008, 0x00000000 },
5894 + { 0x0000800c, 0x00000000 },
5895 + { 0x00008018, 0x00000700 },
5896 + { 0x00008020, 0x00000000 },
5897 + { 0x00008038, 0x00000000 },
5898 + { 0x0000803c, 0x00000000 },
5899 + { 0x00008048, 0x40000000 },
5900 + { 0x00008054, 0x00000000 },
5901 + { 0x00008058, 0x00000000 },
5902 + { 0x0000805c, 0x000fc78f },
5903 + { 0x00008060, 0x0000000f },
5904 + { 0x00008064, 0x00000000 },
5905 + { 0x00008070, 0x00000000 },
5906 + { 0x000080c0, 0x2a80001a },
5907 + { 0x000080c4, 0x05dc01e0 },
5908 + { 0x000080c8, 0x1f402710 },
5909 + { 0x000080cc, 0x01f40000 },
5910 + { 0x000080d0, 0x00001e00 },
5911 + { 0x000080d4, 0x00000000 },
5912 + { 0x000080d8, 0x00400000 },
5913 + { 0x000080e0, 0xffffffff },
5914 + { 0x000080e4, 0x0000ffff },
5915 + { 0x000080e8, 0x003f3f3f },
5916 + { 0x000080ec, 0x00000000 },
5917 + { 0x000080f0, 0x00000000 },
5918 + { 0x000080f4, 0x00000000 },
5919 + { 0x000080f8, 0x00000000 },
5920 + { 0x000080fc, 0x00020000 },
5921 + { 0x00008100, 0x00020000 },
5922 + { 0x00008104, 0x00000001 },
5923 + { 0x00008108, 0x00000052 },
5924 + { 0x0000810c, 0x00000000 },
5925 + { 0x00008110, 0x00000168 },
5926 + { 0x00008118, 0x000100aa },
5927 + { 0x0000811c, 0x00003210 },
5928 + { 0x00008124, 0x00000000 },
5929 + { 0x00008128, 0x00000000 },
5930 + { 0x0000812c, 0x00000000 },
5931 + { 0x00008130, 0x00000000 },
5932 + { 0x00008134, 0x00000000 },
5933 + { 0x00008138, 0x00000000 },
5934 + { 0x0000813c, 0x00000000 },
5935 + { 0x00008144, 0xffffffff },
5936 + { 0x00008168, 0x00000000 },
5937 + { 0x0000816c, 0x00000000 },
5938 + { 0x00008170, 0x32143320 },
5939 + { 0x00008174, 0xfaa4fa50 },
5940 + { 0x00008178, 0x00000100 },
5941 + { 0x0000817c, 0x00000000 },
5942 + { 0x000081c0, 0x00000000 },
5943 + { 0x000081ec, 0x00000000 },
5944 + { 0x000081f0, 0x00000000 },
5945 + { 0x000081f4, 0x00000000 },
5946 + { 0x000081f8, 0x00000000 },
5947 + { 0x000081fc, 0x00000000 },
5948 + { 0x00008200, 0x00000000 },
5949 + { 0x00008204, 0x00000000 },
5950 + { 0x00008208, 0x00000000 },
5951 + { 0x0000820c, 0x00000000 },
5952 + { 0x00008210, 0x00000000 },
5953 + { 0x00008214, 0x00000000 },
5954 + { 0x00008218, 0x00000000 },
5955 + { 0x0000821c, 0x00000000 },
5956 + { 0x00008220, 0x00000000 },
5957 + { 0x00008224, 0x00000000 },
5958 + { 0x00008228, 0x00000000 },
5959 + { 0x0000822c, 0x00000000 },
5960 + { 0x00008230, 0x00000000 },
5961 + { 0x00008234, 0x00000000 },
5962 + { 0x00008238, 0x00000000 },
5963 + { 0x0000823c, 0x00000000 },
5964 + { 0x00008240, 0x00100000 },
5965 + { 0x00008244, 0x0010f400 },
5966 + { 0x00008248, 0x00000100 },
5967 + { 0x0000824c, 0x0001e800 },
5968 + { 0x00008250, 0x00000000 },
5969 + { 0x00008254, 0x00000000 },
5970 + { 0x00008258, 0x00000000 },
5971 + { 0x0000825c, 0x400000ff },
5972 + { 0x00008260, 0x00080922 },
5973 + { 0x00008264, 0xa8a00010 },
5974 + { 0x00008270, 0x00000000 },
5975 + { 0x00008274, 0x40000000 },
5976 + { 0x00008278, 0x003e4180 },
5977 + { 0x0000827c, 0x00000000 },
5978 + { 0x00008284, 0x0000002c },
5979 + { 0x00008288, 0x0000002c },
5980 + { 0x0000828c, 0x00000000 },
5981 + { 0x00008294, 0x00000000 },
5982 + { 0x00008298, 0x00000000 },
5983 + { 0x0000829c, 0x00000000 },
5984 + { 0x00008300, 0x00000040 },
5985 + { 0x00008314, 0x00000000 },
5986 + { 0x00008328, 0x00000000 },
5987 + { 0x0000832c, 0x00000007 },
5988 + { 0x00008330, 0x00000302 },
5989 + { 0x00008334, 0x00000e00 },
5990 + { 0x00008338, 0x00ff0000 },
5991 + { 0x0000833c, 0x00000000 },
5992 + { 0x00008340, 0x000107ff },
5993 + { 0x00008344, 0x00481043 },
5994 + { 0x00009808, 0x00000000 },
5995 + { 0x0000980c, 0xafa68e30 },
5996 + { 0x00009810, 0xfd14e000 },
5997 + { 0x00009814, 0x9c0a9f6b },
5998 + { 0x0000981c, 0x00000000 },
5999 + { 0x0000982c, 0x0000a000 },
6000 + { 0x00009830, 0x00000000 },
6001 + { 0x0000983c, 0x00200400 },
6002 + { 0x0000984c, 0x0040233c },
6003 + { 0x0000a84c, 0x0040233c },
6004 + { 0x00009854, 0x00000044 },
6005 + { 0x00009900, 0x00000000 },
6006 + { 0x00009904, 0x00000000 },
6007 + { 0x00009908, 0x00000000 },
6008 + { 0x0000990c, 0x00000000 },
6009 + { 0x00009910, 0x01002310 },
6010 + { 0x0000991c, 0x10000fff },
6011 + { 0x00009920, 0x04900000 },
6012 + { 0x0000a920, 0x04900000 },
6013 + { 0x00009928, 0x00000001 },
6014 + { 0x0000992c, 0x00000004 },
6015 + { 0x00009934, 0x1e1f2022 },
6016 + { 0x00009938, 0x0a0b0c0d },
6017 + { 0x0000993c, 0x00000000 },
6018 + { 0x00009948, 0x9280c00a },
6019 + { 0x0000994c, 0x00020028 },
6020 + { 0x00009954, 0x5f3ca3de },
6021 + { 0x00009958, 0x2108ecff },
6022 + { 0x00009940, 0x14750604 },
6023 + { 0x0000c95c, 0x004b6a8e },
6024 + { 0x00009970, 0x190fb515 },
6025 + { 0x00009974, 0x00000000 },
6026 + { 0x00009978, 0x00000001 },
6027 + { 0x0000997c, 0x00000000 },
6028 + { 0x00009980, 0x00000000 },
6029 + { 0x00009984, 0x00000000 },
6030 + { 0x00009988, 0x00000000 },
6031 + { 0x0000998c, 0x00000000 },
6032 + { 0x00009990, 0x00000000 },
6033 + { 0x00009994, 0x00000000 },
6034 + { 0x00009998, 0x00000000 },
6035 + { 0x0000999c, 0x00000000 },
6036 + { 0x000099a0, 0x00000000 },
6037 + { 0x000099a4, 0x00000001 },
6038 + { 0x000099a8, 0x201fff00 },
6039 + { 0x000099ac, 0x006f0000 },
6040 + { 0x000099b0, 0x03051000 },
6041 + { 0x000099b4, 0x00000820 },
6042 + { 0x000099dc, 0x00000000 },
6043 + { 0x000099e0, 0x00000000 },
6044 + { 0x000099e4, 0xaaaaaaaa },
6045 + { 0x000099e8, 0x3c466478 },
6046 + { 0x000099ec, 0x0cc80caa },
6047 + { 0x000099f0, 0x00000000 },
6048 + { 0x000099fc, 0x00001042 },
6049 + { 0x0000a208, 0x803e4788 },
6050 + { 0x0000a210, 0x4080a333 },
6051 + { 0x0000a214, 0x40206c10 },
6052 + { 0x0000a218, 0x009c4060 },
6053 + { 0x0000a220, 0x01834061 },
6054 + { 0x0000a224, 0x00000400 },
6055 + { 0x0000a228, 0x000003b5 },
6056 + { 0x0000a22c, 0x233f7180 },
6057 + { 0x0000a234, 0x20202020 },
6058 + { 0x0000a238, 0x20202020 },
6059 + { 0x0000a240, 0x38490a20 },
6060 + { 0x0000a244, 0x00007bb6 },
6061 + { 0x0000a248, 0x0fff3ffc },
6062 + { 0x0000a24c, 0x00000000 },
6063 + { 0x0000a254, 0x00000000 },
6064 + { 0x0000a258, 0x0cdbd380 },
6065 + { 0x0000a25c, 0x0f0f0f01 },
6066 + { 0x0000a260, 0xdfa91f01 },
6067 + { 0x0000a268, 0x00000000 },
6068 + { 0x0000a26c, 0x0e79e5c6 },
6069 + { 0x0000b26c, 0x0e79e5c6 },
6070 + { 0x0000d270, 0x00820820 },
6071 + { 0x0000a278, 0x1ce739ce },
6072 + { 0x0000d35c, 0x07ffffef },
6073 + { 0x0000d360, 0x0fffffe7 },
6074 + { 0x0000d364, 0x17ffffe5 },
6075 + { 0x0000d368, 0x1fffffe4 },
6076 + { 0x0000d36c, 0x37ffffe3 },
6077 + { 0x0000d370, 0x3fffffe3 },
6078 + { 0x0000d374, 0x57ffffe3 },
6079 + { 0x0000d378, 0x5fffffe2 },
6080 + { 0x0000d37c, 0x7fffffe2 },
6081 + { 0x0000d380, 0x7f3c7bba },
6082 + { 0x0000d384, 0xf3307ff0 },
6083 + { 0x0000a38c, 0x20202020 },
6084 + { 0x0000a390, 0x20202020 },
6085 + { 0x0000a394, 0x1ce739ce },
6086 + { 0x0000a398, 0x000001ce },
6087 + { 0x0000a39c, 0x00000001 },
6088 + { 0x0000a3a0, 0x00000000 },
6089 + { 0x0000a3a4, 0x00000000 },
6090 + { 0x0000a3a8, 0x00000000 },
6091 + { 0x0000a3ac, 0x00000000 },
6092 + { 0x0000a3b0, 0x00000000 },
6093 + { 0x0000a3b4, 0x00000000 },
6094 + { 0x0000a3b8, 0x00000000 },
6095 + { 0x0000a3bc, 0x00000000 },
6096 + { 0x0000a3c0, 0x00000000 },
6097 + { 0x0000a3c4, 0x00000000 },
6098 + { 0x0000a3c8, 0x00000246 },
6099 + { 0x0000a3cc, 0x20202020 },
6100 + { 0x0000a3d0, 0x20202020 },
6101 + { 0x0000a3d4, 0x20202020 },
6102 + { 0x0000a3dc, 0x1ce739ce },
6103 + { 0x0000a3e0, 0x000001ce },
6104 + { 0x0000a3e4, 0x00000000 },
6105 + { 0x0000a3e8, 0x18c43433 },
6106 + { 0x0000a3ec, 0x00f70081 },
6107 + { 0x00007800, 0x00040000 },
6108 + { 0x00007804, 0xdb005012 },
6109 + { 0x00007808, 0x04924914 },
6110 + { 0x0000780c, 0x21084210 },
6111 + { 0x00007810, 0x6d801300 },
6112 + { 0x00007818, 0x07e41000 },
6113 + { 0x00007824, 0x00040000 },
6114 + { 0x00007828, 0xdb005012 },
6115 + { 0x0000782c, 0x04924914 },
6116 + { 0x00007830, 0x21084210 },
6117 + { 0x00007834, 0x6d801300 },
6118 + { 0x0000783c, 0x07e40000 },
6119 + { 0x00007848, 0x00100000 },
6120 + { 0x0000784c, 0x773f0567 },
6121 + { 0x00007850, 0x54214514 },
6122 + { 0x00007854, 0x12035828 },
6123 + { 0x00007858, 0x9259269a },
6124 + { 0x00007860, 0x52802000 },
6125 + { 0x00007864, 0x0a8e370e },
6126 + { 0x00007868, 0xc0102850 },
6127 + { 0x0000786c, 0x812d4000 },
6128 + { 0x00007870, 0x807ec400 },
6129 + { 0x00007874, 0x001b6db0 },
6130 + { 0x00007878, 0x00376b63 },
6131 + { 0x0000787c, 0x06db6db6 },
6132 + { 0x00007880, 0x006d8000 },
6133 + { 0x00007884, 0xffeffffe },
6134 + { 0x00007888, 0xffeffffe },
6135 + { 0x0000788c, 0x00010000 },
6136 + { 0x00007890, 0x02060aeb },
6137 + { 0x00007898, 0x2a850160 },
6138 +};
6139 +
6140 +static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
6141 + { 0x00001030, 0x00000268, 0x000004d0 },
6142 + { 0x00001070, 0x0000018c, 0x00000318 },
6143 + { 0x000010b0, 0x00000fd0, 0x00001fa0 },
6144 + { 0x00008014, 0x044c044c, 0x08980898 },
6145 + { 0x0000801c, 0x148ec02b, 0x148ec057 },
6146 + { 0x00008318, 0x000044c0, 0x00008980 },
6147 + { 0x00009820, 0x02020200, 0x02020200 },
6148 + { 0x00009824, 0x01000f0f, 0x01000f0f },
6149 + { 0x00009828, 0x0b020001, 0x0b020001 },
6150 + { 0x00009834, 0x00000f0f, 0x00000f0f },
6151 + { 0x00009844, 0x03721821, 0x03721821 },
6152 + { 0x00009914, 0x00000898, 0x00001130 },
6153 + { 0x00009918, 0x0000000b, 0x00000016 },
6154 +};
6155 +
6156 +static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
6157 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6158 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6159 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6160 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6161 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6162 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6163 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6164 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6165 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6166 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6167 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6168 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6169 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6170 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6171 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6172 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6173 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6174 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6175 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6176 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6177 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6178 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6179 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6180 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6181 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6182 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6183 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6184 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6185 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6186 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6187 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6188 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6189 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6190 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6191 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6192 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6193 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6194 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6195 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6196 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6197 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6198 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6199 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6200 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6201 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6202 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6203 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6204 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6205 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
6206 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
6207 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
6208 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
6209 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
6210 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
6211 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
6212 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
6213 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
6214 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
6215 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
6216 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
6217 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
6218 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
6219 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
6220 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
6221 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
6222 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
6223 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
6224 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
6225 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
6226 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
6227 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
6228 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
6229 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
6230 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
6231 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
6232 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
6233 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
6234 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
6235 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
6236 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
6237 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6238 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6239 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6240 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6241 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6242 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6243 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6244 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6245 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6246 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6247 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6248 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6249 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6250 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6251 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6252 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6253 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6254 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6255 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6256 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6257 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6258 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6259 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6260 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6261 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6262 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6263 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6264 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6265 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6266 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6267 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6268 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6269 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6270 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6271 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6272 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6273 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6274 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6275 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6276 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6277 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6278 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6279 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6280 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6281 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6282 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6283 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6284 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
6285 + { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
6286 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
6287 +};
6288 +
6289 +static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
6290 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6291 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6292 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6293 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6294 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6295 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6296 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6297 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6298 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6299 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6300 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6301 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6302 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6303 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6304 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6305 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6306 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6307 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6308 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6309 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6310 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6311 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6312 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6313 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6314 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6315 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6316 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6317 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6318 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6319 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6320 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6321 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6322 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6323 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6324 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6325 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6326 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6327 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6328 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6329 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6330 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6331 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6332 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6333 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6334 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6335 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6336 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6337 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6338 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
6339 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
6340 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
6341 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
6342 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
6343 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
6344 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
6345 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
6346 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
6347 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
6348 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
6349 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
6350 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
6351 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
6352 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
6353 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
6354 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
6355 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
6356 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
6357 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
6358 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
6359 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
6360 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
6361 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
6362 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
6363 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
6364 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
6365 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
6366 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
6367 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
6368 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
6369 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
6370 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
6371 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
6372 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
6373 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
6374 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
6375 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
6376 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
6377 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
6378 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
6379 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
6380 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
6381 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
6382 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
6383 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
6384 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
6385 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
6386 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
6387 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
6388 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
6389 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
6390 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
6391 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
6392 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6393 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6394 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6395 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6396 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6397 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6398 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6399 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6400 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6401 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6402 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6403 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6404 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6405 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6406 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6407 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6408 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6409 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6410 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6411 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6412 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6413 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6414 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6415 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6416 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6417 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
6418 + { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
6419 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
6420 +};
6421 +
6422 +static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
6423 + { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
6424 + { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
6425 + { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
6426 + { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
6427 + { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
6428 + { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
6429 + { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
6430 + { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
6431 + { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
6432 + { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
6433 + { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
6434 + { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
6435 + { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
6436 + { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
6437 + { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
6438 + { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
6439 + { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
6440 + { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
6441 + { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
6442 + { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
6443 + { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
6444 + { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
6445 + { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
6446 + { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
6447 + { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
6448 + { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
6449 + { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
6450 + { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
6451 + { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
6452 + { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
6453 + { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
6454 + { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
6455 + { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
6456 + { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
6457 + { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
6458 + { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
6459 + { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
6460 + { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
6461 + { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
6462 + { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
6463 + { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
6464 + { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
6465 + { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
6466 + { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
6467 + { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
6468 + { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
6469 + { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
6470 + { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
6471 + { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
6472 + { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
6473 + { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
6474 + { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
6475 + { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
6476 + { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
6477 + { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
6478 + { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
6479 + { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
6480 + { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
6481 + { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
6482 + { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
6483 + { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
6484 + { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
6485 + { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
6486 + { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
6487 + { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
6488 + { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
6489 + { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
6490 + { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
6491 + { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
6492 + { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
6493 + { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
6494 + { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
6495 + { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
6496 + { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
6497 + { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
6498 + { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
6499 + { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
6500 + { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
6501 + { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
6502 + { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
6503 + { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
6504 + { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
6505 + { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
6506 + { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
6507 + { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
6508 + { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
6509 + { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
6510 + { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
6511 + { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
6512 + { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
6513 + { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
6514 + { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
6515 + { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
6516 + { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
6517 + { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
6518 + { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
6519 + { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
6520 + { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
6521 + { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
6522 + { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
6523 + { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
6524 + { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
6525 + { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6526 + { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6527 + { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6528 + { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6529 + { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6530 + { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6531 + { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6532 + { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6533 + { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6534 + { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6535 + { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6536 + { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6537 + { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6538 + { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6539 + { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6540 + { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6541 + { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6542 + { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6543 + { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6544 + { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6545 + { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6546 + { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6547 + { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6548 + { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6549 + { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6550 + { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
6551 + { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
6552 + { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
6553 +};
6554 +
6555 +static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
6556 + { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
6557 + { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
6558 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6559 + { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
6560 + { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
6561 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
6562 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
6563 + { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
6564 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
6565 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
6566 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
6567 + { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
6568 + { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
6569 + { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
6570 + { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
6571 + { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
6572 + { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
6573 + { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
6574 + { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
6575 + { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
6576 + { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
6577 + { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
6578 + { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
6579 + { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
6580 + { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
6581 + { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
6582 + { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
6583 + { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
6584 + { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
6585 + { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
6586 +};
6587 +
6588 +static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
6589 + { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
6590 + { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
6591 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6592 + { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
6593 + { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
6594 + { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
6595 + { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
6596 + { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
6597 + { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
6598 + { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
6599 + { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
6600 + { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
6601 + { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
6602 + { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
6603 + { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
6604 + { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
6605 + { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
6606 + { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
6607 + { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
6608 + { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
6609 + { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
6610 + { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
6611 + { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
6612 + { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
6613 + { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
6614 + { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
6615 + { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
6616 + { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
6617 + { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
6618 + { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
6619 +};
6620 +
6621 +static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
6622 + {0x00004040, 0x9248fd00 },
6623 + {0x00004040, 0x24924924 },
6624 + {0x00004040, 0xa8000019 },
6625 + {0x00004040, 0x13160820 },
6626 + {0x00004040, 0xe5980560 },
6627 + {0x00004040, 0xc01dcffc },
6628 + {0x00004040, 0x1aaabe41 },
6629 + {0x00004040, 0xbe105554 },
6630 + {0x00004040, 0x00043007 },
6631 + {0x00004044, 0x00000000 },
6632 +};
6633 +
6634 +static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
6635 + {0x00004040, 0x9248fd00 },
6636 + {0x00004040, 0x24924924 },
6637 + {0x00004040, 0xa8000019 },
6638 + {0x00004040, 0x13160820 },
6639 + {0x00004040, 0xe5980560 },
6640 + {0x00004040, 0xc01dcffd },
6641 + {0x00004040, 0x1aaabe41 },
6642 + {0x00004040, 0xbe105554 },
6643 + {0x00004040, 0x00043007 },
6644 + {0x00004044, 0x00000000 },
6645 +};
6646 +
6647 +/* AR9285 Revsion 10*/
6648 +static const u_int32_t ar9285Modes_9285[][6] = {
6649 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6650 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6651 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
6652 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
6653 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
6654 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
6655 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6656 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6657 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6658 + { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6659 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
6660 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6661 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6662 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
6663 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
6664 + { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
6665 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
6666 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
6667 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
6668 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
6669 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6670 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6671 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6672 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6673 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6674 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
6675 + { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
6676 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6677 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6678 + { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
6679 + { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6680 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6681 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6682 + { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
6683 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6684 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6685 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6686 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6687 + { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
6688 + { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
6689 + { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
6690 + { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
6691 + { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
6692 + { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
6693 + { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
6694 + { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6695 + { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
6696 + { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
6697 + { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
6698 + { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
6699 + { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
6700 + { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
6701 + { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
6702 + { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
6703 + { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
6704 + { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
6705 + { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
6706 + { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
6707 + { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
6708 + { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
6709 + { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
6710 + { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
6711 + { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
6712 + { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
6713 + { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
6714 + { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
6715 + { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
6716 + { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
6717 + { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
6718 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
6719 + { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
6720 + { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
6721 + { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
6722 + { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
6723 + { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
6724 + { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
6725 + { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
6726 + { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
6727 + { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
6728 + { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
6729 + { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
6730 + { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
6731 + { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6732 + { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
6733 + { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
6734 + { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
6735 + { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
6736 + { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
6737 + { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
6738 + { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
6739 + { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
6740 + { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
6741 + { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
6742 + { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
6743 + { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
6744 + { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
6745 + { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
6746 + { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
6747 + { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
6748 + { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
6749 + { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
6750 + { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
6751 + { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
6752 + { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
6753 + { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
6754 + { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
6755 + { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
6756 + { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
6757 + { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
6758 + { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
6759 + { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
6760 + { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
6761 + { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
6762 + { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
6763 + { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
6764 + { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
6765 + { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
6766 + { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
6767 + { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
6768 + { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
6769 + { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
6770 + { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
6771 + { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
6772 + { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
6773 + { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
6774 + { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
6775 + { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
6776 + { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6777 + { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6778 + { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6779 + { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6780 + { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6781 + { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6782 + { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6783 + { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6784 + { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6785 + { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6786 + { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6787 + { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6788 + { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6789 + { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6790 + { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6791 + { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6792 + { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6793 + { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6794 + { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6795 + { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6796 + { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6797 + { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6798 + { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6799 + { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6800 + { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6801 + { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6802 + { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6803 + { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6804 + { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6805 + { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6806 + { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6807 + { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6808 + { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6809 + { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6810 + { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6811 + { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6812 + { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6813 + { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6814 + { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
6815 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
6816 + { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
6817 + { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
6818 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
6819 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
6820 + { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
6821 + { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
6822 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
6823 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
6824 + { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6825 + { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
6826 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
6827 + { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
6828 + { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
6829 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
6830 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
6831 + { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
6832 + { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
6833 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
6834 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
6835 + { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
6836 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
6837 + { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
6838 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
6839 + { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
6840 + { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
6841 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
6842 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
6843 + { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
6844 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
6845 + { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
6846 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
6847 + { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
6848 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
6849 + { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
6850 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
6851 + { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
6852 + { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
6853 + { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
6854 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
6855 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
6856 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
6857 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
6858 + { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
6859 + { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
6860 + { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6861 + { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
6862 + { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
6863 + { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
6864 + { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
6865 + { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
6866 + { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
6867 + { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
6868 + { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
6869 + { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
6870 + { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
6871 + { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
6872 + { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
6873 + { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
6874 + { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
6875 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
6876 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
6877 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
6878 + { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
6879 + { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
6880 + { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
6881 + { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
6882 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
6883 + { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
6884 + { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
6885 + { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
6886 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
6887 + { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
6888 + { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
6889 + { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
6890 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
6891 + { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
6892 + { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
6893 + { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
6894 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
6895 + { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
6896 + { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
6897 + { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
6898 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
6899 + { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
6900 + { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
6901 + { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
6902 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
6903 + { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
6904 + { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6905 + { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6906 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6907 + { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6908 + { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6909 + { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6910 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6911 + { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6912 + { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6913 + { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6914 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6915 + { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6916 + { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6917 + { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6918 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6919 + { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6920 + { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6921 + { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6922 + { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6923 + { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6924 + { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6925 + { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6926 + { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6927 + { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6928 + { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6929 + { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6930 + { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6931 + { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6932 + { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6933 + { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6934 + { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6935 + { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6936 + { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6937 + { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6938 + { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6939 + { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6940 + { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6941 + { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6942 + { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
6943 + { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
6944 + { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
6945 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
6946 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
6947 + { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
6948 + { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
6949 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6950 + { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
6951 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
6952 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
6953 + { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
6954 + { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
6955 + { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
6956 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
6957 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
6958 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
6959 + { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
6960 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
6961 + { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
6962 + { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
6963 + { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
6964 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
6965 + { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
6966 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
6967 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6968 +};
6969 +
6970 +static const u_int32_t ar9285Common_9285[][2] = {
6971 + { 0x0000000c, 0x00000000 },
6972 + { 0x00000030, 0x00020045 },
6973 + { 0x00000034, 0x00000005 },
6974 + { 0x00000040, 0x00000000 },
6975 + { 0x00000044, 0x00000008 },
6976 + { 0x00000048, 0x00000008 },
6977 + { 0x0000004c, 0x00000010 },
6978 + { 0x00000050, 0x00000000 },
6979 + { 0x00000054, 0x0000001f },
6980 + { 0x00000800, 0x00000000 },
6981 + { 0x00000804, 0x00000000 },
6982 + { 0x00000808, 0x00000000 },
6983 + { 0x0000080c, 0x00000000 },
6984 + { 0x00000810, 0x00000000 },
6985 + { 0x00000814, 0x00000000 },
6986 + { 0x00000818, 0x00000000 },
6987 + { 0x0000081c, 0x00000000 },
6988 + { 0x00000820, 0x00000000 },
6989 + { 0x00000824, 0x00000000 },
6990 + { 0x00001040, 0x002ffc0f },
6991 + { 0x00001044, 0x002ffc0f },
6992 + { 0x00001048, 0x002ffc0f },
6993 + { 0x0000104c, 0x002ffc0f },
6994 + { 0x00001050, 0x002ffc0f },
6995 + { 0x00001054, 0x002ffc0f },
6996 + { 0x00001058, 0x002ffc0f },
6997 + { 0x0000105c, 0x002ffc0f },
6998 + { 0x00001060, 0x002ffc0f },
6999 + { 0x00001064, 0x002ffc0f },
7000 + { 0x00001230, 0x00000000 },
7001 + { 0x00001270, 0x00000000 },
7002 + { 0x00001038, 0x00000000 },
7003 + { 0x00001078, 0x00000000 },
7004 + { 0x000010b8, 0x00000000 },
7005 + { 0x000010f8, 0x00000000 },
7006 + { 0x00001138, 0x00000000 },
7007 + { 0x00001178, 0x00000000 },
7008 + { 0x000011b8, 0x00000000 },
7009 + { 0x000011f8, 0x00000000 },
7010 + { 0x00001238, 0x00000000 },
7011 + { 0x00001278, 0x00000000 },
7012 + { 0x000012b8, 0x00000000 },
7013 + { 0x000012f8, 0x00000000 },
7014 + { 0x00001338, 0x00000000 },
7015 + { 0x00001378, 0x00000000 },
7016 + { 0x000013b8, 0x00000000 },
7017 + { 0x000013f8, 0x00000000 },
7018 + { 0x00001438, 0x00000000 },
7019 + { 0x00001478, 0x00000000 },
7020 + { 0x000014b8, 0x00000000 },
7021 + { 0x000014f8, 0x00000000 },
7022 + { 0x00001538, 0x00000000 },
7023 + { 0x00001578, 0x00000000 },
7024 + { 0x000015b8, 0x00000000 },
7025 + { 0x000015f8, 0x00000000 },
7026 + { 0x00001638, 0x00000000 },
7027 + { 0x00001678, 0x00000000 },
7028 + { 0x000016b8, 0x00000000 },
7029 + { 0x000016f8, 0x00000000 },
7030 + { 0x00001738, 0x00000000 },
7031 + { 0x00001778, 0x00000000 },
7032 + { 0x000017b8, 0x00000000 },
7033 + { 0x000017f8, 0x00000000 },
7034 + { 0x0000103c, 0x00000000 },
7035 + { 0x0000107c, 0x00000000 },
7036 + { 0x000010bc, 0x00000000 },
7037 + { 0x000010fc, 0x00000000 },
7038 + { 0x0000113c, 0x00000000 },
7039 + { 0x0000117c, 0x00000000 },
7040 + { 0x000011bc, 0x00000000 },
7041 + { 0x000011fc, 0x00000000 },
7042 + { 0x0000123c, 0x00000000 },
7043 + { 0x0000127c, 0x00000000 },
7044 + { 0x000012bc, 0x00000000 },
7045 + { 0x000012fc, 0x00000000 },
7046 + { 0x0000133c, 0x00000000 },
7047 + { 0x0000137c, 0x00000000 },
7048 + { 0x000013bc, 0x00000000 },
7049 + { 0x000013fc, 0x00000000 },
7050 + { 0x0000143c, 0x00000000 },
7051 + { 0x0000147c, 0x00000000 },
7052 + { 0x00004030, 0x00000002 },
7053 + { 0x0000403c, 0x00000002 },
7054 + { 0x00004024, 0x0000001f },
7055 + { 0x00004060, 0x00000000 },
7056 + { 0x00004064, 0x00000000 },
7057 + { 0x00007010, 0x00000031 },
7058 + { 0x00007034, 0x00000002 },
7059 + { 0x00007038, 0x000004c2 },
7060 + { 0x00008004, 0x00000000 },
7061 + { 0x00008008, 0x00000000 },
7062 + { 0x0000800c, 0x00000000 },
7063 + { 0x00008018, 0x00000700 },
7064 + { 0x00008020, 0x00000000 },
7065 + { 0x00008038, 0x00000000 },
7066 + { 0x0000803c, 0x00000000 },
7067 + { 0x00008048, 0x00000000 },
7068 + { 0x00008054, 0x00000000 },
7069 + { 0x00008058, 0x00000000 },
7070 + { 0x0000805c, 0x000fc78f },
7071 + { 0x00008060, 0x0000000f },
7072 + { 0x00008064, 0x00000000 },
7073 + { 0x00008070, 0x00000000 },
7074 + { 0x000080c0, 0x2a80001a },
7075 + { 0x000080c4, 0x05dc01e0 },
7076 + { 0x000080c8, 0x1f402710 },
7077 + { 0x000080cc, 0x01f40000 },
7078 + { 0x000080d0, 0x00001e00 },
7079 + { 0x000080d4, 0x00000000 },
7080 + { 0x000080d8, 0x00400000 },
7081 + { 0x000080e0, 0xffffffff },
7082 + { 0x000080e4, 0x0000ffff },
7083 + { 0x000080e8, 0x003f3f3f },
7084 + { 0x000080ec, 0x00000000 },
7085 + { 0x000080f0, 0x00000000 },
7086 + { 0x000080f4, 0x00000000 },
7087 + { 0x000080f8, 0x00000000 },
7088 + { 0x000080fc, 0x00020000 },
7089 + { 0x00008100, 0x00020000 },
7090 + { 0x00008104, 0x00000001 },
7091 + { 0x00008108, 0x00000052 },
7092 + { 0x0000810c, 0x00000000 },
7093 + { 0x00008110, 0x00000168 },
7094 + { 0x00008118, 0x000100aa },
7095 + { 0x0000811c, 0x00003210 },
7096 + { 0x00008120, 0x08f04800 },
7097 + { 0x00008124, 0x00000000 },
7098 + { 0x00008128, 0x00000000 },
7099 + { 0x0000812c, 0x00000000 },
7100 + { 0x00008130, 0x00000000 },
7101 + { 0x00008134, 0x00000000 },
7102 + { 0x00008138, 0x00000000 },
7103 + { 0x0000813c, 0x00000000 },
7104 + { 0x00008144, 0x00000000 },
7105 + { 0x00008168, 0x00000000 },
7106 + { 0x0000816c, 0x00000000 },
7107 + { 0x00008170, 0x32143320 },
7108 + { 0x00008174, 0xfaa4fa50 },
7109 + { 0x00008178, 0x00000100 },
7110 + { 0x0000817c, 0x00000000 },
7111 + { 0x000081c0, 0x00000000 },
7112 + { 0x000081d0, 0x00003210 },
7113 + { 0x000081ec, 0x00000000 },
7114 + { 0x000081f0, 0x00000000 },
7115 + { 0x000081f4, 0x00000000 },
7116 + { 0x000081f8, 0x00000000 },
7117 + { 0x000081fc, 0x00000000 },
7118 + { 0x00008200, 0x00000000 },
7119 + { 0x00008204, 0x00000000 },
7120 + { 0x00008208, 0x00000000 },
7121 + { 0x0000820c, 0x00000000 },
7122 + { 0x00008210, 0x00000000 },
7123 + { 0x00008214, 0x00000000 },
7124 + { 0x00008218, 0x00000000 },
7125 + { 0x0000821c, 0x00000000 },
7126 + { 0x00008220, 0x00000000 },
7127 + { 0x00008224, 0x00000000 },
7128 + { 0x00008228, 0x00000000 },
7129 + { 0x0000822c, 0x00000000 },
7130 + { 0x00008230, 0x00000000 },
7131 + { 0x00008234, 0x00000000 },
7132 + { 0x00008238, 0x00000000 },
7133 + { 0x0000823c, 0x00000000 },
7134 + { 0x00008240, 0x00100000 },
7135 + { 0x00008244, 0x0010f400 },
7136 + { 0x00008248, 0x00000100 },
7137 + { 0x0000824c, 0x0001e800 },
7138 + { 0x00008250, 0x00000000 },
7139 + { 0x00008254, 0x00000000 },
7140 + { 0x00008258, 0x00000000 },
7141 + { 0x0000825c, 0x400000ff },
7142 + { 0x00008260, 0x00080922 },
7143 + { 0x00008264, 0xa8a00010 },
7144 + { 0x00008270, 0x00000000 },
7145 + { 0x00008274, 0x40000000 },
7146 + { 0x00008278, 0x003e4180 },
7147 + { 0x0000827c, 0x00000000 },
7148 + { 0x00008284, 0x0000002c },
7149 + { 0x00008288, 0x0000002c },
7150 + { 0x0000828c, 0x00000000 },
7151 + { 0x00008294, 0x00000000 },
7152 + { 0x00008298, 0x00000000 },
7153 + { 0x0000829c, 0x00000000 },
7154 + { 0x00008300, 0x00000040 },
7155 + { 0x00008314, 0x00000000 },
7156 + { 0x00008328, 0x00000000 },
7157 + { 0x0000832c, 0x00000001 },
7158 + { 0x00008330, 0x00000302 },
7159 + { 0x00008334, 0x00000e00 },
7160 + { 0x00008338, 0x00000000 },
7161 + { 0x0000833c, 0x00000000 },
7162 + { 0x00008340, 0x00010380 },
7163 + { 0x00008344, 0x00481043 },
7164 + { 0x00009808, 0x00000000 },
7165 + { 0x0000980c, 0xafe68e30 },
7166 + { 0x00009810, 0xfd14e000 },
7167 + { 0x00009814, 0x9c0a9f6b },
7168 + { 0x0000981c, 0x00000000 },
7169 + { 0x0000982c, 0x0000a000 },
7170 + { 0x00009830, 0x00000000 },
7171 + { 0x0000983c, 0x00200400 },
7172 + { 0x0000984c, 0x0040233c },
7173 + { 0x00009854, 0x00000044 },
7174 + { 0x00009900, 0x00000000 },
7175 + { 0x00009904, 0x00000000 },
7176 + { 0x00009908, 0x00000000 },
7177 + { 0x0000990c, 0x00000000 },
7178 + { 0x00009910, 0x01002310 },
7179 + { 0x0000991c, 0x10000fff },
7180 + { 0x00009920, 0x04900000 },
7181 + { 0x00009928, 0x00000001 },
7182 + { 0x0000992c, 0x00000004 },
7183 + { 0x00009934, 0x1e1f2022 },
7184 + { 0x00009938, 0x0a0b0c0d },
7185 + { 0x0000993c, 0x00000000 },
7186 + { 0x00009940, 0x14750604 },
7187 + { 0x00009948, 0x9280c00a },
7188 + { 0x0000994c, 0x00020028 },
7189 + { 0x00009954, 0x5f3ca3de },
7190 + { 0x00009958, 0x2108ecff },
7191 + { 0x00009968, 0x000003ce },
7192 + { 0x00009970, 0x1927b515 },
7193 + { 0x00009974, 0x00000000 },
7194 + { 0x00009978, 0x00000001 },
7195 + { 0x0000997c, 0x00000000 },
7196 + { 0x00009980, 0x00000000 },
7197 + { 0x00009984, 0x00000000 },
7198 + { 0x00009988, 0x00000000 },
7199 + { 0x0000998c, 0x00000000 },
7200 + { 0x00009990, 0x00000000 },
7201 + { 0x00009994, 0x00000000 },
7202 + { 0x00009998, 0x00000000 },
7203 + { 0x0000999c, 0x00000000 },
7204 + { 0x000099a0, 0x00000000 },
7205 + { 0x000099a4, 0x00000001 },
7206 + { 0x000099a8, 0x201fff00 },
7207 + { 0x000099ac, 0x2def0a00 },
7208 + { 0x000099b0, 0x03051000 },
7209 + { 0x000099b4, 0x00000820 },
7210 + { 0x000099dc, 0x00000000 },
7211 + { 0x000099e0, 0x00000000 },
7212 + { 0x000099e4, 0xaaaaaaaa },
7213 + { 0x000099e8, 0x3c466478 },
7214 + { 0x000099ec, 0x0cc80caa },
7215 + { 0x000099f0, 0x00000000 },
7216 + { 0x0000a208, 0x803e6788 },
7217 + { 0x0000a210, 0x4080a333 },
7218 + { 0x0000a214, 0x00206c10 },
7219 + { 0x0000a218, 0x009c4060 },
7220 + { 0x0000a220, 0x01834061 },
7221 + { 0x0000a224, 0x00000400 },
7222 + { 0x0000a228, 0x000003b5 },
7223 + { 0x0000a22c, 0x00000000 },
7224 + { 0x0000a234, 0x20202020 },
7225 + { 0x0000a238, 0x20202020 },
7226 + { 0x0000a244, 0x00000000 },
7227 + { 0x0000a248, 0xfffffffc },
7228 + { 0x0000a24c, 0x00000000 },
7229 + { 0x0000a254, 0x00000000 },
7230 + { 0x0000a258, 0x0ccb5380 },
7231 + { 0x0000a25c, 0x15151501 },
7232 + { 0x0000a260, 0xdfa90f01 },
7233 + { 0x0000a268, 0x00000000 },
7234 + { 0x0000a26c, 0x0ebae9e6 },
7235 + { 0x0000d270, 0x0d820820 },
7236 + { 0x0000a278, 0x39ce739c },
7237 + { 0x0000a27c, 0x050e039c },
7238 + { 0x0000d35c, 0x07ffffef },
7239 + { 0x0000d360, 0x0fffffe7 },
7240 + { 0x0000d364, 0x17ffffe5 },
7241 + { 0x0000d368, 0x1fffffe4 },
7242 + { 0x0000d36c, 0x37ffffe3 },
7243 + { 0x0000d370, 0x3fffffe3 },
7244 + { 0x0000d374, 0x57ffffe3 },
7245 + { 0x0000d378, 0x5fffffe2 },
7246 + { 0x0000d37c, 0x7fffffe2 },
7247 + { 0x0000d380, 0x7f3c7bba },
7248 + { 0x0000d384, 0xf3307ff0 },
7249 + { 0x0000a388, 0x0c000000 },
7250 + { 0x0000a38c, 0x20202020 },
7251 + { 0x0000a390, 0x20202020 },
7252 + { 0x0000a394, 0x39ce739c },
7253 + { 0x0000a398, 0x0000039c },
7254 + { 0x0000a39c, 0x00000001 },
7255 + { 0x0000a3a0, 0x00000000 },
7256 + { 0x0000a3a4, 0x00000000 },
7257 + { 0x0000a3a8, 0x00000000 },
7258 + { 0x0000a3ac, 0x00000000 },
7259 + { 0x0000a3b0, 0x00000000 },
7260 + { 0x0000a3b4, 0x00000000 },
7261 + { 0x0000a3b8, 0x00000000 },
7262 + { 0x0000a3bc, 0x00000000 },
7263 + { 0x0000a3c0, 0x00000000 },
7264 + { 0x0000a3c4, 0x00000000 },
7265 + { 0x0000a3cc, 0x20202020 },
7266 + { 0x0000a3d0, 0x20202020 },
7267 + { 0x0000a3d4, 0x20202020 },
7268 + { 0x0000a3dc, 0x39ce739c },
7269 + { 0x0000a3e0, 0x0000039c },
7270 + { 0x0000a3e4, 0x00000000 },
7271 + { 0x0000a3e8, 0x18c43433 },
7272 + { 0x0000a3ec, 0x00f70081 },
7273 + { 0x00007800, 0x00140000 },
7274 + { 0x00007804, 0x0e4548d8 },
7275 + { 0x00007808, 0x54214514 },
7276 + { 0x0000780c, 0x02025820 },
7277 + { 0x00007810, 0x71c0d388 },
7278 + { 0x00007814, 0x924934a8 },
7279 + { 0x0000781c, 0x00000000 },
7280 + { 0x00007820, 0x00000c04 },
7281 + { 0x00007824, 0x00d86fff },
7282 + { 0x00007828, 0x26d2491b },
7283 + { 0x0000782c, 0x6e36d97b },
7284 + { 0x00007830, 0xedb6d96c },
7285 + { 0x00007834, 0x71400086 },
7286 + { 0x00007838, 0xfac68800 },
7287 + { 0x0000783c, 0x0001fffe },
7288 + { 0x00007840, 0xffeb1a20 },
7289 + { 0x00007844, 0x000c0db6 },
7290 + { 0x00007848, 0x6db61b6f },
7291 + { 0x0000784c, 0x6d9b66db },
7292 + { 0x00007850, 0x6d8c6dba },
7293 + { 0x00007854, 0x00040000 },
7294 + { 0x00007858, 0xdb003012 },
7295 + { 0x0000785c, 0x04924914 },
7296 + { 0x00007860, 0x21084210 },
7297 + { 0x00007864, 0xf7d7ffde },
7298 + { 0x00007868, 0xc2034080 },
7299 + { 0x0000786c, 0x48609eb4 },
7300 + { 0x00007870, 0x10142c00 },
7301 +};
7302 +
7303 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
7304 + {0x00004040, 0x9248fd00 },
7305 + {0x00004040, 0x24924924 },
7306 + {0x00004040, 0xa8000019 },
7307 + {0x00004040, 0x13160820 },
7308 + {0x00004040, 0xe5980560 },
7309 + {0x00004040, 0xc01dcffd },
7310 + {0x00004040, 0x1aaabe41 },
7311 + {0x00004040, 0xbe105554 },
7312 + {0x00004040, 0x00043007 },
7313 + {0x00004044, 0x00000000 },
7314 +};
7315 +
7316 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
7317 + {0x00004040, 0x9248fd00 },
7318 + {0x00004040, 0x24924924 },
7319 + {0x00004040, 0xa8000019 },
7320 + {0x00004040, 0x13160820 },
7321 + {0x00004040, 0xe5980560 },
7322 + {0x00004040, 0xc01dcffc },
7323 + {0x00004040, 0x1aaabe41 },
7324 + {0x00004040, 0xbe105554 },
7325 + {0x00004040, 0x00043007 },
7326 + {0x00004044, 0x00000000 },
7327 +};
7328 +
7329 +/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
7330 +static const u_int32_t ar9285Modes_9285_1_2[][6] = {
7331 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7332 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
7333 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
7334 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
7335 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
7336 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
7337 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
7338 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
7339 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
7340 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
7341 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
7342 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7343 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
7344 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
7345 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
7346 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
7347 + { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
7348 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
7349 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
7350 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
7351 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
7352 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
7353 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
7354 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
7355 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
7356 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
7357 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
7358 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
7359 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
7360 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7361 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7362 + { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
7363 + { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
7364 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
7365 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
7366 + { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
7367 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
7368 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
7369 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7370 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7371 + { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
7372 + { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
7373 + { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
7374 + { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
7375 + { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
7376 + { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
7377 + { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
7378 + { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
7379 + { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
7380 + { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
7381 + { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
7382 + { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
7383 + { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
7384 + { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
7385 + { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
7386 + { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
7387 + { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
7388 + { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
7389 + { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
7390 + { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
7391 + { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
7392 + { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
7393 + { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
7394 + { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
7395 + { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
7396 + { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
7397 + { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
7398 + { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
7399 + { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
7400 + { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
7401 + { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
7402 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
7403 + { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
7404 + { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
7405 + { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
7406 + { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
7407 + { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
7408 + { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
7409 + { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
7410 + { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
7411 + { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
7412 + { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
7413 + { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
7414 + { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
7415 + { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
7416 + { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
7417 + { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
7418 + { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
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7626 + { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
7627 + { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
7628 + { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
7629 + { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
7630 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
7631 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
7632 + { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
7633 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
7634 +};
7635 +
7636 +static const u_int32_t ar9285Common_9285_1_2[][2] = {
7637 + { 0x0000000c, 0x00000000 },
7638 + { 0x00000030, 0x00020045 },
7639 + { 0x00000034, 0x00000005 },
7640 + { 0x00000040, 0x00000000 },
7641 + { 0x00000044, 0x00000008 },
7642 + { 0x00000048, 0x00000008 },
7643 + { 0x0000004c, 0x00000010 },
7644 + { 0x00000050, 0x00000000 },
7645 + { 0x00000054, 0x0000001f },
7646 + { 0x00000800, 0x00000000 },
7647 + { 0x00000804, 0x00000000 },
7648 + { 0x00000808, 0x00000000 },
7649 + { 0x0000080c, 0x00000000 },
7650 + { 0x00000810, 0x00000000 },
7651 + { 0x00000814, 0x00000000 },
7652 + { 0x00000818, 0x00000000 },
7653 + { 0x0000081c, 0x00000000 },
7654 + { 0x00000820, 0x00000000 },
7655 + { 0x00000824, 0x00000000 },
7656 + { 0x00001040, 0x002ffc0f },
7657 + { 0x00001044, 0x002ffc0f },
7658 + { 0x00001048, 0x002ffc0f },
7659 + { 0x0000104c, 0x002ffc0f },
7660 + { 0x00001050, 0x002ffc0f },
7661 + { 0x00001054, 0x002ffc0f },
7662 + { 0x00001058, 0x002ffc0f },
7663 + { 0x0000105c, 0x002ffc0f },
7664 + { 0x00001060, 0x002ffc0f },
7665 + { 0x00001064, 0x002ffc0f },
7666 + { 0x00001230, 0x00000000 },
7667 + { 0x00001270, 0x00000000 },
7668 + { 0x00001038, 0x00000000 },
7669 + { 0x00001078, 0x00000000 },
7670 + { 0x000010b8, 0x00000000 },
7671 + { 0x000010f8, 0x00000000 },
7672 + { 0x00001138, 0x00000000 },
7673 + { 0x00001178, 0x00000000 },
7674 + { 0x000011b8, 0x00000000 },
7675 + { 0x000011f8, 0x00000000 },
7676 + { 0x00001238, 0x00000000 },
7677 + { 0x00001278, 0x00000000 },
7678 + { 0x000012b8, 0x00000000 },
7679 + { 0x000012f8, 0x00000000 },
7680 + { 0x00001338, 0x00000000 },
7681 + { 0x00001378, 0x00000000 },
7682 + { 0x000013b8, 0x00000000 },
7683 + { 0x000013f8, 0x00000000 },
7684 + { 0x00001438, 0x00000000 },
7685 + { 0x00001478, 0x00000000 },
7686 + { 0x000014b8, 0x00000000 },
7687 + { 0x000014f8, 0x00000000 },
7688 + { 0x00001538, 0x00000000 },
7689 + { 0x00001578, 0x00000000 },
7690 + { 0x000015b8, 0x00000000 },
7691 + { 0x000015f8, 0x00000000 },
7692 + { 0x00001638, 0x00000000 },
7693 + { 0x00001678, 0x00000000 },
7694 + { 0x000016b8, 0x00000000 },
7695 + { 0x000016f8, 0x00000000 },
7696 + { 0x00001738, 0x00000000 },
7697 + { 0x00001778, 0x00000000 },
7698 + { 0x000017b8, 0x00000000 },
7699 + { 0x000017f8, 0x00000000 },
7700 + { 0x0000103c, 0x00000000 },
7701 + { 0x0000107c, 0x00000000 },
7702 + { 0x000010bc, 0x00000000 },
7703 + { 0x000010fc, 0x00000000 },
7704 + { 0x0000113c, 0x00000000 },
7705 + { 0x0000117c, 0x00000000 },
7706 + { 0x000011bc, 0x00000000 },
7707 + { 0x000011fc, 0x00000000 },
7708 + { 0x0000123c, 0x00000000 },
7709 + { 0x0000127c, 0x00000000 },
7710 + { 0x000012bc, 0x00000000 },
7711 + { 0x000012fc, 0x00000000 },
7712 + { 0x0000133c, 0x00000000 },
7713 + { 0x0000137c, 0x00000000 },
7714 + { 0x000013bc, 0x00000000 },
7715 + { 0x000013fc, 0x00000000 },
7716 + { 0x0000143c, 0x00000000 },
7717 + { 0x0000147c, 0x00000000 },
7718 + { 0x00004030, 0x00000002 },
7719 + { 0x0000403c, 0x00000002 },
7720 + { 0x00004024, 0x0000001f },
7721 + { 0x00004060, 0x00000000 },
7722 + { 0x00004064, 0x00000000 },
7723 + { 0x00007010, 0x00000031 },
7724 + { 0x00007034, 0x00000002 },
7725 + { 0x00007038, 0x000004c2 },
7726 + { 0x00008004, 0x00000000 },
7727 + { 0x00008008, 0x00000000 },
7728 + { 0x0000800c, 0x00000000 },
7729 + { 0x00008018, 0x00000700 },
7730 + { 0x00008020, 0x00000000 },
7731 + { 0x00008038, 0x00000000 },
7732 + { 0x0000803c, 0x00000000 },
7733 + { 0x00008048, 0x00000000 },
7734 + { 0x00008054, 0x00000000 },
7735 + { 0x00008058, 0x00000000 },
7736 + { 0x0000805c, 0x000fc78f },
7737 + { 0x00008060, 0x0000000f },
7738 + { 0x00008064, 0x00000000 },
7739 + { 0x00008070, 0x00000000 },
7740 + { 0x000080c0, 0x2a80001a },
7741 + { 0x000080c4, 0x05dc01e0 },
7742 + { 0x000080c8, 0x1f402710 },
7743 + { 0x000080cc, 0x01f40000 },
7744 + { 0x000080d0, 0x00001e00 },
7745 + { 0x000080d4, 0x00000000 },
7746 + { 0x000080d8, 0x00400000 },
7747 + { 0x000080e0, 0xffffffff },
7748 + { 0x000080e4, 0x0000ffff },
7749 + { 0x000080e8, 0x003f3f3f },
7750 + { 0x000080ec, 0x00000000 },
7751 + { 0x000080f0, 0x00000000 },
7752 + { 0x000080f4, 0x00000000 },
7753 + { 0x000080f8, 0x00000000 },
7754 + { 0x000080fc, 0x00020000 },
7755 + { 0x00008100, 0x00020000 },
7756 + { 0x00008104, 0x00000001 },
7757 + { 0x00008108, 0x00000052 },
7758 + { 0x0000810c, 0x00000000 },
7759 + { 0x00008110, 0x00000168 },
7760 + { 0x00008118, 0x000100aa },
7761 + { 0x0000811c, 0x00003210 },
7762 + { 0x00008120, 0x08f04810 },
7763 + { 0x00008124, 0x00000000 },
7764 + { 0x00008128, 0x00000000 },
7765 + { 0x0000812c, 0x00000000 },
7766 + { 0x00008130, 0x00000000 },
7767 + { 0x00008134, 0x00000000 },
7768 + { 0x00008138, 0x00000000 },
7769 + { 0x0000813c, 0x00000000 },
7770 + { 0x00008144, 0xffffffff },
7771 + { 0x00008168, 0x00000000 },
7772 + { 0x0000816c, 0x00000000 },
7773 + { 0x00008170, 0x32143320 },
7774 + { 0x00008174, 0xfaa4fa50 },
7775 + { 0x00008178, 0x00000100 },
7776 + { 0x0000817c, 0x00000000 },
7777 + { 0x000081c0, 0x00000000 },
7778 + { 0x000081d0, 0x0000320a },
7779 + { 0x000081ec, 0x00000000 },
7780 + { 0x000081f0, 0x00000000 },
7781 + { 0x000081f4, 0x00000000 },
7782 + { 0x000081f8, 0x00000000 },
7783 + { 0x000081fc, 0x00000000 },
7784 + { 0x00008200, 0x00000000 },
7785 + { 0x00008204, 0x00000000 },
7786 + { 0x00008208, 0x00000000 },
7787 + { 0x0000820c, 0x00000000 },
7788 + { 0x00008210, 0x00000000 },
7789 + { 0x00008214, 0x00000000 },
7790 + { 0x00008218, 0x00000000 },
7791 + { 0x0000821c, 0x00000000 },
7792 + { 0x00008220, 0x00000000 },
7793 + { 0x00008224, 0x00000000 },
7794 + { 0x00008228, 0x00000000 },
7795 + { 0x0000822c, 0x00000000 },
7796 + { 0x00008230, 0x00000000 },
7797 + { 0x00008234, 0x00000000 },
7798 + { 0x00008238, 0x00000000 },
7799 + { 0x0000823c, 0x00000000 },
7800 + { 0x00008240, 0x00100000 },
7801 + { 0x00008244, 0x0010f400 },
7802 + { 0x00008248, 0x00000100 },
7803 + { 0x0000824c, 0x0001e800 },
7804 + { 0x00008250, 0x00000000 },
7805 + { 0x00008254, 0x00000000 },
7806 + { 0x00008258, 0x00000000 },
7807 + { 0x0000825c, 0x400000ff },
7808 + { 0x00008260, 0x00080922 },
7809 + { 0x00008264, 0x88a00010 },
7810 + { 0x00008270, 0x00000000 },
7811 + { 0x00008274, 0x40000000 },
7812 + { 0x00008278, 0x003e4180 },
7813 + { 0x0000827c, 0x00000000 },
7814 + { 0x00008284, 0x0000002c },
7815 + { 0x00008288, 0x0000002c },
7816 + { 0x0000828c, 0x00000000 },
7817 + { 0x00008294, 0x00000000 },
7818 + { 0x00008298, 0x00000000 },
7819 + { 0x0000829c, 0x00000000 },
7820 + { 0x00008300, 0x00000040 },
7821 + { 0x00008314, 0x00000000 },
7822 + { 0x00008328, 0x00000000 },
7823 + { 0x0000832c, 0x00000001 },
7824 + { 0x00008330, 0x00000302 },
7825 + { 0x00008334, 0x00000e00 },
7826 + { 0x00008338, 0x00ff0000 },
7827 + { 0x0000833c, 0x00000000 },
7828 + { 0x00008340, 0x00010380 },
7829 + { 0x00008344, 0x00481043 },
7830 + { 0x00009808, 0x00000000 },
7831 + { 0x0000980c, 0xafe68e30 },
7832 + { 0x00009810, 0xfd14e000 },
7833 + { 0x00009814, 0x9c0a9f6b },
7834 + { 0x0000981c, 0x00000000 },
7835 + { 0x0000982c, 0x0000a000 },
7836 + { 0x00009830, 0x00000000 },
7837 + { 0x0000983c, 0x00200400 },
7838 + { 0x0000984c, 0x0040233c },
7839 + { 0x00009854, 0x00000044 },
7840 + { 0x00009900, 0x00000000 },
7841 + { 0x00009904, 0x00000000 },
7842 + { 0x00009908, 0x00000000 },
7843 + { 0x0000990c, 0x00000000 },
7844 + { 0x00009910, 0x01002310 },
7845 + { 0x0000991c, 0x10000fff },
7846 + { 0x00009920, 0x04900000 },
7847 + { 0x00009928, 0x00000001 },
7848 + { 0x0000992c, 0x00000004 },
7849 + { 0x00009934, 0x1e1f2022 },
7850 + { 0x00009938, 0x0a0b0c0d },
7851 + { 0x0000993c, 0x00000000 },
7852 + { 0x00009940, 0x14750604 },
7853 + { 0x00009948, 0x9280c00a },
7854 + { 0x0000994c, 0x00020028 },
7855 + { 0x00009954, 0x5f3ca3de },
7856 + { 0x00009958, 0x2108ecff },
7857 + { 0x00009968, 0x000003ce },
7858 + { 0x00009970, 0x192bb514 },
7859 + { 0x00009974, 0x00000000 },
7860 + { 0x00009978, 0x00000001 },
7861 + { 0x0000997c, 0x00000000 },
7862 + { 0x00009980, 0x00000000 },
7863 + { 0x00009984, 0x00000000 },
7864 + { 0x00009988, 0x00000000 },
7865 + { 0x0000998c, 0x00000000 },
7866 + { 0x00009990, 0x00000000 },
7867 + { 0x00009994, 0x00000000 },
7868 + { 0x00009998, 0x00000000 },
7869 + { 0x0000999c, 0x00000000 },
7870 + { 0x000099a0, 0x00000000 },
7871 + { 0x000099a4, 0x00000001 },
7872 + { 0x000099a8, 0x201fff00 },
7873 + { 0x000099ac, 0x2def0400 },
7874 + { 0x000099b0, 0x03051000 },
7875 + { 0x000099b4, 0x00000820 },
7876 + { 0x000099dc, 0x00000000 },
7877 + { 0x000099e0, 0x00000000 },
7878 + { 0x000099e4, 0xaaaaaaaa },
7879 + { 0x000099e8, 0x3c466478 },
7880 + { 0x000099ec, 0x0cc80caa },
7881 + { 0x000099f0, 0x00000000 },
7882 + { 0x0000a208, 0x803e68c8 },
7883 + { 0x0000a210, 0x4080a333 },
7884 + { 0x0000a214, 0x00206c10 },
7885 + { 0x0000a218, 0x009c4060 },
7886 + { 0x0000a220, 0x01834061 },
7887 + { 0x0000a224, 0x00000400 },
7888 + { 0x0000a228, 0x000003b5 },
7889 + { 0x0000a22c, 0x00000000 },
7890 + { 0x0000a234, 0x20202020 },
7891 + { 0x0000a238, 0x20202020 },
7892 + { 0x0000a244, 0x00000000 },
7893 + { 0x0000a248, 0xfffffffc },
7894 + { 0x0000a24c, 0x00000000 },
7895 + { 0x0000a254, 0x00000000 },
7896 + { 0x0000a258, 0x0ccb5380 },
7897 + { 0x0000a25c, 0x15151501 },
7898 + { 0x0000a260, 0xdfa90f01 },
7899 + { 0x0000a268, 0x00000000 },
7900 + { 0x0000a26c, 0x0ebae9e6 },
7901 + { 0x0000d270, 0x0d820820 },
7902 + { 0x0000d35c, 0x07ffffef },
7903 + { 0x0000d360, 0x0fffffe7 },
7904 + { 0x0000d364, 0x17ffffe5 },
7905 + { 0x0000d368, 0x1fffffe4 },
7906 + { 0x0000d36c, 0x37ffffe3 },
7907 + { 0x0000d370, 0x3fffffe3 },
7908 + { 0x0000d374, 0x57ffffe3 },
7909 + { 0x0000d378, 0x5fffffe2 },
7910 + { 0x0000d37c, 0x7fffffe2 },
7911 + { 0x0000d380, 0x7f3c7bba },
7912 + { 0x0000d384, 0xf3307ff0 },
7913 + { 0x0000a388, 0x0c000000 },
7914 + { 0x0000a38c, 0x20202020 },
7915 + { 0x0000a390, 0x20202020 },
7916 + { 0x0000a39c, 0x00000001 },
7917 + { 0x0000a3a0, 0x00000000 },
7918 + { 0x0000a3a4, 0x00000000 },
7919 + { 0x0000a3a8, 0x00000000 },
7920 + { 0x0000a3ac, 0x00000000 },
7921 + { 0x0000a3b0, 0x00000000 },
7922 + { 0x0000a3b4, 0x00000000 },
7923 + { 0x0000a3b8, 0x00000000 },
7924 + { 0x0000a3bc, 0x00000000 },
7925 + { 0x0000a3c0, 0x00000000 },
7926 + { 0x0000a3c4, 0x00000000 },
7927 + { 0x0000a3cc, 0x20202020 },
7928 + { 0x0000a3d0, 0x20202020 },
7929 + { 0x0000a3d4, 0x20202020 },
7930 + { 0x0000a3e4, 0x00000000 },
7931 + { 0x0000a3e8, 0x18c43433 },
7932 + { 0x0000a3ec, 0x00f70081 },
7933 + { 0x00007800, 0x00140000 },
7934 + { 0x00007804, 0x0e4548d8 },
7935 + { 0x00007808, 0x54214514 },
7936 + { 0x0000780c, 0x02025830 },
7937 + { 0x00007810, 0x71c0d388 },
7938 + { 0x0000781c, 0x00000000 },
7939 + { 0x00007824, 0x00d86fff },
7940 + { 0x0000782c, 0x6e36d97b },
7941 + { 0x00007834, 0x71400087 },
7942 + { 0x00007844, 0x000c0db6 },
7943 + { 0x00007848, 0x6db6246f },
7944 + { 0x0000784c, 0x6d9b66db },
7945 + { 0x00007850, 0x6d8c6dba },
7946 + { 0x00007854, 0x00040000 },
7947 + { 0x00007858, 0xdb003012 },
7948 + { 0x0000785c, 0x04924914 },
7949 + { 0x00007860, 0x21084210 },
7950 + { 0x00007864, 0xf7d7ffde },
7951 + { 0x00007868, 0xc2034080 },
7952 + { 0x00007870, 0x10142c00 },
7953 +};
7954 +
7955 +static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
7956 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7957 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7958 + { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
7959 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
7960 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
7961 + { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
7962 + { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
7963 + { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
7964 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
7965 + { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
7966 + { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
7967 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
7968 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
7969 + { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
7970 + { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
7971 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
7972 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
7973 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7974 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7975 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7976 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7977 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7978 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
7979 + { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
7980 + { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
7981 + { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
7982 + { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
7983 + { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
7984 + { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
7985 + { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
7986 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
7987 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
7988 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7989 + { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
7990 + { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7991 + { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
7992 + { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
7993 + { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
7994 +};
7995 +
7996 +static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
7997 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
7998 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7999 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
8000 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
8001 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
8002 + { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
8003 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
8004 + { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
8005 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
8006 + { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
8007 + { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
8008 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
8009 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
8010 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
8011 + { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
8012 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8013 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8014 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8015 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8016 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8017 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8018 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8019 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8020 + { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
8021 + { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
8022 + { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
8023 + { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
8024 + { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
8025 + { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
8026 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
8027 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
8028 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
8029 + { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8030 + { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
8031 + { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8032 + { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8033 + { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8034 + { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8035 +};
8036 +
8037 +static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
8038 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8039 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
8040 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
8041 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
8042 + { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
8043 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
8044 + { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
8045 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
8046 + { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
8047 + { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
8048 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
8049 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
8050 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
8051 + { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
8052 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8053 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8054 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8055 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8056 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8057 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8058 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8059 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8060 + { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
8061 + { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
8062 + { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
8063 + { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
8064 + { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
8065 + { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
8066 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
8067 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
8068 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
8069 + { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8070 + { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
8071 + { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8072 + { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8073 + { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
8074 + { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
8075 +};
8076 +
8077 +static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
8078 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8079 + { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
8080 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
8081 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
8082 + { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
8083 + { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
8084 + { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
8085 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
8086 + { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
8087 + { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
8088 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
8089 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
8090 + { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
8091 + { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
8092 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
8093 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
8094 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8095 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8096 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8097 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8098 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8099 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
8100 + { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
8101 + { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
8102 + { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
8103 + { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
8104 + { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
8105 + { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
8106 + { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
8107 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
8108 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
8109 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8110 + { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
8111 + { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8112 + { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
8113 + { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
8114 + { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
8115 +};
8116 +
8117 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
8118 + {0x00004040, 0x9248fd00 },
8119 + {0x00004040, 0x24924924 },
8120 + {0x00004040, 0xa8000019 },
8121 + {0x00004040, 0x13160820 },
8122 + {0x00004040, 0xe5980560 },
8123 + {0x00004040, 0xc01dcffd },
8124 + {0x00004040, 0x1aaabe41 },
8125 + {0x00004040, 0xbe105554 },
8126 + {0x00004040, 0x00043007 },
8127 + {0x00004044, 0x00000000 },
8128 +};
8129 +
8130 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
8131 + {0x00004040, 0x9248fd00 },
8132 + {0x00004040, 0x24924924 },
8133 + {0x00004040, 0xa8000019 },
8134 + {0x00004040, 0x13160820 },
8135 + {0x00004040, 0xe5980560 },
8136 + {0x00004040, 0xc01dcffc },
8137 + {0x00004040, 0x1aaabe41 },
8138 + {0x00004040, 0xbe105554 },
8139 + {0x00004040, 0x00043007 },
8140 + {0x00004044, 0x00000000 },
8141 +};
8142 +
8143 +/* AR9287 Revision 10 */
8144 +static const u_int32_t ar9287Modes_9287_1_0[][6] = {
8145 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8146 + { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
8147 + { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
8148 + { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
8149 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
8150 + { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
8151 + { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
8152 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
8153 + { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
8154 + { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
8155 + { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
8156 + { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
8157 + { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
8158 + { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
8159 + { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
8160 + { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
8161 + { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
8162 + { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
8163 + { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
8164 + { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
8165 + { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
8166 + { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
8167 + { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
8168 + { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
8169 + { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
8170 + { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
8171 + { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
8172 + { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
8173 + { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
8174 + { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8175 + { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8176 + { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
8177 + { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
8178 + { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
8179 + { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
8180 + { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
8181 + { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
8182 + { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8183 + { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8184 + { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
8185 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
8186 + { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
8187 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
8188 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8189 +};
8190 +
8191 +static const u_int32_t ar9287Common_9287_1_0[][2] = {
8192 + { 0x0000000c, 0x00000000 },
8193 + { 0x00000030, 0x00020015 },
8194 + { 0x00000034, 0x00000005 },
8195 + { 0x00000040, 0x00000000 },
8196 + { 0x00000044, 0x00000008 },
8197 + { 0x00000048, 0x00000008 },
8198 + { 0x0000004c, 0x00000010 },
8199 + { 0x00000050, 0x00000000 },
8200 + { 0x00000054, 0x0000001f },
8201 + { 0x00000800, 0x00000000 },
8202 + { 0x00000804, 0x00000000 },
8203 + { 0x00000808, 0x00000000 },
8204 + { 0x0000080c, 0x00000000 },
8205 + { 0x00000810, 0x00000000 },
8206 + { 0x00000814, 0x00000000 },
8207 + { 0x00000818, 0x00000000 },
8208 + { 0x0000081c, 0x00000000 },
8209 + { 0x00000820, 0x00000000 },
8210 + { 0x00000824, 0x00000000 },
8211 + { 0x00001040, 0x002ffc0f },
8212 + { 0x00001044, 0x002ffc0f },
8213 + { 0x00001048, 0x002ffc0f },
8214 + { 0x0000104c, 0x002ffc0f },
8215 + { 0x00001050, 0x002ffc0f },
8216 + { 0x00001054, 0x002ffc0f },
8217 + { 0x00001058, 0x002ffc0f },
8218 + { 0x0000105c, 0x002ffc0f },
8219 + { 0x00001060, 0x002ffc0f },
8220 + { 0x00001064, 0x002ffc0f },
8221 + { 0x00001230, 0x00000000 },
8222 + { 0x00001270, 0x00000000 },
8223 + { 0x00001038, 0x00000000 },
8224 + { 0x00001078, 0x00000000 },
8225 + { 0x000010b8, 0x00000000 },
8226 + { 0x000010f8, 0x00000000 },
8227 + { 0x00001138, 0x00000000 },
8228 + { 0x00001178, 0x00000000 },
8229 + { 0x000011b8, 0x00000000 },
8230 + { 0x000011f8, 0x00000000 },
8231 + { 0x00001238, 0x00000000 },
8232 + { 0x00001278, 0x00000000 },
8233 + { 0x000012b8, 0x00000000 },
8234 + { 0x000012f8, 0x00000000 },
8235 + { 0x00001338, 0x00000000 },
8236 + { 0x00001378, 0x00000000 },
8237 + { 0x000013b8, 0x00000000 },
8238 + { 0x000013f8, 0x00000000 },
8239 + { 0x00001438, 0x00000000 },
8240 + { 0x00001478, 0x00000000 },
8241 + { 0x000014b8, 0x00000000 },
8242 + { 0x000014f8, 0x00000000 },
8243 + { 0x00001538, 0x00000000 },
8244 + { 0x00001578, 0x00000000 },
8245 + { 0x000015b8, 0x00000000 },
8246 + { 0x000015f8, 0x00000000 },
8247 + { 0x00001638, 0x00000000 },
8248 + { 0x00001678, 0x00000000 },
8249 + { 0x000016b8, 0x00000000 },
8250 + { 0x000016f8, 0x00000000 },
8251 + { 0x00001738, 0x00000000 },
8252 + { 0x00001778, 0x00000000 },
8253 + { 0x000017b8, 0x00000000 },
8254 + { 0x000017f8, 0x00000000 },
8255 + { 0x0000103c, 0x00000000 },
8256 + { 0x0000107c, 0x00000000 },
8257 + { 0x000010bc, 0x00000000 },
8258 + { 0x000010fc, 0x00000000 },
8259 + { 0x0000113c, 0x00000000 },
8260 + { 0x0000117c, 0x00000000 },
8261 + { 0x000011bc, 0x00000000 },
8262 + { 0x000011fc, 0x00000000 },
8263 + { 0x0000123c, 0x00000000 },
8264 + { 0x0000127c, 0x00000000 },
8265 + { 0x000012bc, 0x00000000 },
8266 + { 0x000012fc, 0x00000000 },
8267 + { 0x0000133c, 0x00000000 },
8268 + { 0x0000137c, 0x00000000 },
8269 + { 0x000013bc, 0x00000000 },
8270 + { 0x000013fc, 0x00000000 },
8271 + { 0x0000143c, 0x00000000 },
8272 + { 0x0000147c, 0x00000000 },
8273 + { 0x00004030, 0x00000002 },
8274 + { 0x0000403c, 0x00000002 },
8275 + { 0x00004024, 0x0000001f },
8276 + { 0x00004060, 0x00000000 },
8277 + { 0x00004064, 0x00000000 },
8278 + { 0x00007010, 0x00000033 },
8279 + { 0x00007020, 0x00000000 },
8280 + { 0x00007034, 0x00000002 },
8281 + { 0x00007038, 0x000004c2 },
8282 + { 0x00008004, 0x00000000 },
8283 + { 0x00008008, 0x00000000 },
8284 + { 0x0000800c, 0x00000000 },
8285 + { 0x00008018, 0x00000700 },
8286 + { 0x00008020, 0x00000000 },
8287 + { 0x00008038, 0x00000000 },
8288 + { 0x0000803c, 0x00000000 },
8289 + { 0x00008048, 0x40000000 },
8290 + { 0x00008054, 0x00000000 },
8291 + { 0x00008058, 0x00000000 },
8292 + { 0x0000805c, 0x000fc78f },
8293 + { 0x00008060, 0x0000000f },
8294 + { 0x00008064, 0x00000000 },
8295 + { 0x00008070, 0x00000000 },
8296 + { 0x000080c0, 0x2a80001a },
8297 + { 0x000080c4, 0x05dc01e0 },
8298 + { 0x000080c8, 0x1f402710 },
8299 + { 0x000080cc, 0x01f40000 },
8300 + { 0x000080d0, 0x00001e00 },
8301 + { 0x000080d4, 0x00000000 },
8302 + { 0x000080d8, 0x00400000 },
8303 + { 0x000080e0, 0xffffffff },
8304 + { 0x000080e4, 0x0000ffff },
8305 + { 0x000080e8, 0x003f3f3f },
8306 + { 0x000080ec, 0x00000000 },
8307 + { 0x000080f0, 0x00000000 },
8308 + { 0x000080f4, 0x00000000 },
8309 + { 0x000080f8, 0x00000000 },
8310 + { 0x000080fc, 0x00020000 },
8311 + { 0x00008100, 0x00020000 },
8312 + { 0x00008104, 0x00000001 },
8313 + { 0x00008108, 0x00000052 },
8314 + { 0x0000810c, 0x00000000 },
8315 + { 0x00008110, 0x00000168 },
8316 + { 0x00008118, 0x000100aa },
8317 + { 0x0000811c, 0x00003210 },
8318 + { 0x00008124, 0x00000000 },
8319 + { 0x00008128, 0x00000000 },
8320 + { 0x0000812c, 0x00000000 },
8321 + { 0x00008130, 0x00000000 },
8322 + { 0x00008134, 0x00000000 },
8323 + { 0x00008138, 0x00000000 },
8324 + { 0x0000813c, 0x00000000 },
8325 + { 0x00008144, 0xffffffff },
8326 + { 0x00008168, 0x00000000 },
8327 + { 0x0000816c, 0x00000000 },
8328 + { 0x00008170, 0x18487320 },
8329 + { 0x00008174, 0xfaa4fa50 },
8330 + { 0x00008178, 0x00000100 },
8331 + { 0x0000817c, 0x00000000 },
8332 + { 0x000081c0, 0x00000000 },
8333 + { 0x000081c4, 0x00000000 },
8334 + { 0x000081d4, 0x00000000 },
8335 + { 0x000081ec, 0x00000000 },
8336 + { 0x000081f0, 0x00000000 },
8337 + { 0x000081f4, 0x00000000 },
8338 + { 0x000081f8, 0x00000000 },
8339 + { 0x000081fc, 0x00000000 },
8340 + { 0x00008200, 0x00000000 },
8341 + { 0x00008204, 0x00000000 },
8342 + { 0x00008208, 0x00000000 },
8343 + { 0x0000820c, 0x00000000 },
8344 + { 0x00008210, 0x00000000 },
8345 + { 0x00008214, 0x00000000 },
8346 + { 0x00008218, 0x00000000 },
8347 + { 0x0000821c, 0x00000000 },
8348 + { 0x00008220, 0x00000000 },
8349 + { 0x00008224, 0x00000000 },
8350 + { 0x00008228, 0x00000000 },
8351 + { 0x0000822c, 0x00000000 },
8352 + { 0x00008230, 0x00000000 },
8353 + { 0x00008234, 0x00000000 },
8354 + { 0x00008238, 0x00000000 },
8355 + { 0x0000823c, 0x00000000 },
8356 + { 0x00008240, 0x00100000 },
8357 + { 0x00008244, 0x0010f400 },
8358 + { 0x00008248, 0x00000100 },
8359 + { 0x0000824c, 0x0001e800 },
8360 + { 0x00008250, 0x00000000 },
8361 + { 0x00008254, 0x00000000 },
8362 + { 0x00008258, 0x00000000 },
8363 + { 0x0000825c, 0x400000ff },
8364 + { 0x00008260, 0x00080922 },
8365 + { 0x00008264, 0xa8a00010 },
8366 + { 0x00008270, 0x00000000 },
8367 + { 0x00008274, 0x40000000 },
8368 + { 0x00008278, 0x003e4180 },
8369 + { 0x0000827c, 0x00000000 },
8370 + { 0x00008284, 0x0000002c },
8371 + { 0x00008288, 0x0000002c },
8372 + { 0x0000828c, 0x000000ff },
8373 + { 0x00008294, 0x00000000 },
8374 + { 0x00008298, 0x00000000 },
8375 + { 0x0000829c, 0x00000000 },
8376 + { 0x00008300, 0x00000040 },
8377 + { 0x00008314, 0x00000000 },
8378 + { 0x00008328, 0x00000000 },
8379 + { 0x0000832c, 0x00000007 },
8380 + { 0x00008330, 0x00000302 },
8381 + { 0x00008334, 0x00000e00 },
8382 + { 0x00008338, 0x00ff0000 },
8383 + { 0x0000833c, 0x00000000 },
8384 + { 0x00008340, 0x000107ff },
8385 + { 0x00008344, 0x01c81043 },
8386 + { 0x00008360, 0xffffffff },
8387 + { 0x00008364, 0xffffffff },
8388 + { 0x00008368, 0x00000000 },
8389 + { 0x00008370, 0x00000000 },
8390 + { 0x00008374, 0x000000ff },
8391 + { 0x00008378, 0x00000000 },
8392 + { 0x0000837c, 0x00000000 },
8393 + { 0x00008380, 0xffffffff },
8394 + { 0x00008384, 0xffffffff },
8395 + { 0x00008390, 0x0fffffff },
8396 + { 0x00008394, 0x0fffffff },
8397 + { 0x00008398, 0x00000000 },
8398 + { 0x0000839c, 0x00000000 },
8399 + { 0x000083a0, 0x00000000 },
8400 + { 0x00009808, 0x00000000 },
8401 + { 0x0000980c, 0xafe68e30 },
8402 + { 0x00009810, 0xfd14e000 },
8403 + { 0x00009814, 0x9c0a9f6b },
8404 + { 0x0000981c, 0x00000000 },
8405 + { 0x0000982c, 0x0000a000 },
8406 + { 0x00009830, 0x00000000 },
8407 + { 0x0000983c, 0x00200400 },
8408 + { 0x0000984c, 0x0040233c },
8409 + { 0x0000a84c, 0x0040233c },
8410 + { 0x00009854, 0x00000044 },
8411 + { 0x00009900, 0x00000000 },
8412 + { 0x00009904, 0x00000000 },
8413 + { 0x00009908, 0x00000000 },
8414 + { 0x0000990c, 0x00000000 },
8415 + { 0x00009910, 0x10002310 },
8416 + { 0x0000991c, 0x10000fff },
8417 + { 0x00009920, 0x04900000 },
8418 + { 0x0000a920, 0x04900000 },
8419 + { 0x00009928, 0x00000001 },
8420 + { 0x0000992c, 0x00000004 },
8421 + { 0x00009930, 0x00000000 },
8422 + { 0x0000a930, 0x00000000 },
8423 + { 0x00009934, 0x1e1f2022 },
8424 + { 0x00009938, 0x0a0b0c0d },
8425 + { 0x0000993c, 0x00000000 },
8426 + { 0x00009948, 0x9280c00a },
8427 + { 0x0000994c, 0x00020028 },
8428 + { 0x00009954, 0x5f3ca3de },
8429 + { 0x00009958, 0x0108ecff },
8430 + { 0x00009940, 0x14750604 },
8431 + { 0x0000c95c, 0x004b6a8e },
8432 + { 0x00009970, 0x990bb515 },
8433 + { 0x00009974, 0x00000000 },
8434 + { 0x00009978, 0x00000001 },
8435 + { 0x0000997c, 0x00000000 },
8436 + { 0x000099a0, 0x00000000 },
8437 + { 0x000099a4, 0x00000001 },
8438 + { 0x000099a8, 0x201fff00 },
8439 + { 0x000099ac, 0x0c6f0000 },
8440 + { 0x000099b0, 0x03051000 },
8441 + { 0x000099b4, 0x00000820 },
8442 + { 0x000099c4, 0x06336f77 },
8443 + { 0x000099c8, 0x6af65329 },
8444 + { 0x000099cc, 0x08f186c8 },
8445 + { 0x000099d0, 0x00046384 },
8446 + { 0x000099dc, 0x00000000 },
8447 + { 0x000099e0, 0x00000000 },
8448 + { 0x000099e4, 0xaaaaaaaa },
8449 + { 0x000099e8, 0x3c466478 },
8450 + { 0x000099ec, 0x0cc80caa },
8451 + { 0x000099f0, 0x00000000 },
8452 + { 0x000099fc, 0x00001042 },
8453 + { 0x0000a1f4, 0x00fffeff },
8454 + { 0x0000a1f8, 0x00f5f9ff },
8455 + { 0x0000a1fc, 0xb79f6427 },
8456 + { 0x0000a208, 0x803e4788 },
8457 + { 0x0000a210, 0x4080a333 },
8458 + { 0x0000a214, 0x40206c10 },
8459 + { 0x0000a218, 0x009c4060 },
8460 + { 0x0000a220, 0x01834061 },
8461 + { 0x0000a224, 0x00000400 },
8462 + { 0x0000a228, 0x000003b5 },
8463 + { 0x0000a22c, 0x233f7180 },
8464 + { 0x0000a234, 0x20202020 },
8465 + { 0x0000a238, 0x20202020 },
8466 + { 0x0000a23c, 0x13c889af },
8467 + { 0x0000a240, 0x38490a20 },
8468 + { 0x0000a244, 0x00000000 },
8469 + { 0x0000a248, 0xfffffffc },
8470 + { 0x0000a24c, 0x00000000 },
8471 + { 0x0000a254, 0x00000000 },
8472 + { 0x0000a258, 0x0cdbd380 },
8473 + { 0x0000a25c, 0x0f0f0f01 },
8474 + { 0x0000a260, 0xdfa91f01 },
8475 + { 0x0000a264, 0x00418a11 },
8476 + { 0x0000b264, 0x00418a11 },
8477 + { 0x0000a268, 0x00000000 },
8478 + { 0x0000a26c, 0x0e79e5c6 },
8479 + { 0x0000b26c, 0x0e79e5c6 },
8480 + { 0x0000d270, 0x00820820 },
8481 + { 0x0000a278, 0x1ce739ce },
8482 + { 0x0000a27c, 0x050701ce },
8483 + { 0x0000d35c, 0x07ffffef },
8484 + { 0x0000d360, 0x0fffffe7 },
8485 + { 0x0000d364, 0x17ffffe5 },
8486 + { 0x0000d368, 0x1fffffe4 },
8487 + { 0x0000d36c, 0x37ffffe3 },
8488 + { 0x0000d370, 0x3fffffe3 },
8489 + { 0x0000d374, 0x57ffffe3 },
8490 + { 0x0000d378, 0x5fffffe2 },
8491 + { 0x0000d37c, 0x7fffffe2 },
8492 + { 0x0000d380, 0x7f3c7bba },
8493 + { 0x0000d384, 0xf3307ff0 },
8494 + { 0x0000a388, 0x0c000000 },
8495 + { 0x0000a38c, 0x20202020 },
8496 + { 0x0000a390, 0x20202020 },
8497 + { 0x0000a394, 0x1ce739ce },
8498 + { 0x0000a398, 0x000001ce },
8499 + { 0x0000b398, 0x000001ce },
8500 + { 0x0000a39c, 0x00000001 },
8501 + { 0x0000a3c8, 0x00000246 },
8502 + { 0x0000a3cc, 0x20202020 },
8503 + { 0x0000a3d0, 0x20202020 },
8504 + { 0x0000a3d4, 0x20202020 },
8505 + { 0x0000a3dc, 0x1ce739ce },
8506 + { 0x0000a3e0, 0x000001ce },
8507 + { 0x0000a3e4, 0x00000000 },
8508 + { 0x0000a3e8, 0x18c43433 },
8509 + { 0x0000a3ec, 0x00f70081 },
8510 + { 0x0000a3f0, 0x01036a1e },
8511 + { 0x0000a3f4, 0x00000000 },
8512 + { 0x0000b3f4, 0x00000000 },
8513 + { 0x0000a7d8, 0x00000001 },
8514 + { 0x00007800, 0x00000800 },
8515 + { 0x00007804, 0x6c35ffb0 },
8516 + { 0x00007808, 0x6db6c000 },
8517 + { 0x0000780c, 0x6db6cb30 },
8518 + { 0x00007810, 0x6db6cb6c },
8519 + { 0x00007814, 0x0501e200 },
8520 + { 0x00007818, 0x0094128d },
8521 + { 0x0000781c, 0x976ee392 },
8522 + { 0x00007820, 0xf75ff6fc },
8523 + { 0x00007824, 0x00040000 },
8524 + { 0x00007828, 0xdb003012 },
8525 + { 0x0000782c, 0x04924914 },
8526 + { 0x00007830, 0x21084210 },
8527 + { 0x00007834, 0x00140000 },
8528 + { 0x00007838, 0x0e4548d8 },
8529 + { 0x0000783c, 0x54214514 },
8530 + { 0x00007840, 0x02025820 },
8531 + { 0x00007844, 0x71c0d388 },
8532 + { 0x00007848, 0x934934a8 },
8533 + { 0x00007850, 0x00000000 },
8534 + { 0x00007854, 0x00000800 },
8535 + { 0x00007858, 0x6c35ffb0 },
8536 + { 0x0000785c, 0x6db6c000 },
8537 + { 0x00007860, 0x6db6cb2c },
8538 + { 0x00007864, 0x6db6cb6c },
8539 + { 0x00007868, 0x0501e200 },
8540 + { 0x0000786c, 0x0094128d },
8541 + { 0x00007870, 0x976ee392 },
8542 + { 0x00007874, 0xf75ff6fc },
8543 + { 0x00007878, 0x00040000 },
8544 + { 0x0000787c, 0xdb003012 },
8545 + { 0x00007880, 0x04924914 },
8546 + { 0x00007884, 0x21084210 },
8547 + { 0x00007888, 0x001b6db0 },
8548 + { 0x0000788c, 0x00376b63 },
8549 + { 0x00007890, 0x06db6db6 },
8550 + { 0x00007894, 0x006d8000 },
8551 + { 0x00007898, 0x48100000 },
8552 + { 0x0000789c, 0x00000000 },
8553 + { 0x000078a0, 0x08000000 },
8554 + { 0x000078a4, 0x0007ffd8 },
8555 + { 0x000078a8, 0x0007ffd8 },
8556 + { 0x000078ac, 0x001c0020 },
8557 + { 0x000078b0, 0x000611eb },
8558 + { 0x000078b4, 0x40008080 },
8559 + { 0x000078b8, 0x2a850160 },
8560 +};
8561 +
8562 +static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
8563 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8564 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8565 + { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
8566 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
8567 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
8568 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
8569 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
8570 + { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
8571 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
8572 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
8573 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
8574 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
8575 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
8576 + { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
8577 + { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
8578 + { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
8579 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
8580 + { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
8581 + { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
8582 + { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
8583 + { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
8584 + { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
8585 + { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
8586 + { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
8587 + { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
8588 + { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
8589 + { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
8590 + { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
8591 + { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
8592 + { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
8593 + { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
8594 + { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
8595 + { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
8596 + { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
8597 + { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
8598 + { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
8599 + { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8600 + { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8601 + { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8602 + { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8603 + { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8604 + { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8605 + { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8606 + { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8607 + { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
8608 + { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
8609 +};
8610 +
8611 +
8612 +static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
8613 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8614 + { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
8615 + { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
8616 + { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
8617 + { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
8618 + { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
8619 + { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
8620 + { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
8621 + { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
8622 + { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
8623 + { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
8624 + { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
8625 + { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
8626 + { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
8627 + { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
8628 + { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
8629 + { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
8630 + { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
8631 + { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
8632 + { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
8633 + { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
8634 + { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
8635 + { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
8636 + { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
8637 + { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
8638 + { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
8639 + { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
8640 + { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
8641 + { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
8642 + { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
8643 + { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
8644 + { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
8645 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
8646 + { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
8647 + { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
8648 + { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
8649 + { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
8650 + { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
8651 + { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
8652 + { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
8653 + { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
8654 + { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
8655 + { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
8656 + { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
8657 + { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
8658 + { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
8659 + { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
8660 + { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
8661 + { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
8662 + { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
8663 + { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
8664 + { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
8665 + { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
8666 + { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
8667 + { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
8668 + { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
8669 + { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
8670 + { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
8671 + { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
8672 + { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
8673 + { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
8674 + { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
8675 + { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
8676 + { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
8677 + { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
8678 + { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
8679 + { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
8680 + { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
8681 + { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
8682 + { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
8683 + { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
8684 + { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
8685 + { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
8686 + { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
8687 + { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
8688 + { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
8689 + { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
8690 + { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
8691 + { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
8692 + { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
8693 + { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
8694 + { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
8695 + { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
8696 + { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
8697 + { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
8698 + { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
8699 + { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
8700 + { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
8701 + { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
8702 + { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
8703 + { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
8704 + { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
8705 + { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
8706 + { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
8707 + { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
8708 + { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
8709 + { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
8710 + { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
8711 + { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
8712 + { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
8713 + { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
8714 + { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
8715 + { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
8716 + { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
8717 + { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8718 + { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8719 + { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8720 + { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8721 + { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8722 + { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8723 + { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8724 + { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8725 + { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8726 + { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8727 + { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8728 + { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8729 + { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8730 + { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8731 + { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8732 + { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8733 + { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8734 + { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8735 + { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8736 + { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8737 + { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8738 + { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8739 + { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8740 + { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8741 + { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8742 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
8743 + { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
8744 + { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
8745 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
8746 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
8747 + { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
8748 + { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
8749 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
8750 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
8751 + { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
8752 + { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
8753 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
8754 + { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
8755 + { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
8756 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
8757 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
8758 + { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
8759 + { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
8760 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
8761 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
8762 + { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
8763 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
8764 + { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
8765 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
8766 + { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
8767 + { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
8768 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
8769 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
8770 + { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
8771 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
8772 + { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
8773 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
8774 + { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
8775 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
8776 + { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
8777 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
8778 + { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
8779 + { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
8780 + { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
8781 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
8782 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
8783 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
8784 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
8785 + { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
8786 + { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
8787 + { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
8788 + { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
8789 + { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
8790 + { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
8791 + { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
8792 + { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
8793 + { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
8794 + { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
8795 + { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
8796 + { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
8797 + { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
8798 + { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
8799 + { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
8800 + { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
8801 + { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
8802 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
8803 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
8804 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
8805 + { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
8806 + { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
8807 + { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
8808 + { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
8809 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
8810 + { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
8811 + { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
8812 + { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
8813 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
8814 + { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
8815 + { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
8816 + { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
8817 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
8818 + { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
8819 + { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
8820 + { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
8821 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
8822 + { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
8823 + { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
8824 + { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
8825 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
8826 + { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
8827 + { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
8828 + { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
8829 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
8830 + { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
8831 + { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
8832 + { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
8833 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
8834 + { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
8835 + { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
8836 + { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
8837 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
8838 + { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
8839 + { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
8840 + { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
8841 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
8842 + { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
8843 + { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
8844 + { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
8845 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8846 + { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8847 + { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8848 + { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8849 + { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8850 + { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8851 + { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8852 + { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8853 + { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8854 + { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8855 + { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8856 + { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8857 + { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8858 + { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8859 + { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8860 + { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8861 + { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8862 + { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8863 + { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8864 + { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8865 + { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8866 + { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8867 + { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8868 + { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8869 + { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
8870 + { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
8871 + { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
8872 +};
8873 +
8874 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
8875 + {0x00004040, 0x9248fd00 },
8876 + {0x00004040, 0x24924924 },
8877 + {0x00004040, 0xa8000019 },
8878 + {0x00004040, 0x13160820 },
8879 + {0x00004040, 0xe5980560 },
8880 + {0x00004040, 0xc01dcffd },
8881 + {0x00004040, 0x1aaabe41 },
8882 + {0x00004040, 0xbe105554 },
8883 + {0x00004040, 0x00043007 },
8884 + {0x00004044, 0x00000000 },
8885 +};
8886 +
8887 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
8888 + {0x00004040, 0x9248fd00 },
8889 + {0x00004040, 0x24924924 },
8890 + {0x00004040, 0xa8000019 },
8891 + {0x00004040, 0x13160820 },
8892 + {0x00004040, 0xe5980560 },
8893 + {0x00004040, 0xc01dcffc },
8894 + {0x00004040, 0x1aaabe41 },
8895 + {0x00004040, 0xbe105554 },
8896 + {0x00004040, 0x00043007 },
8897 + {0x00004044, 0x00000000 },
8898 +};
8899 +
8900 +/* AR9287 Revision 11 */
8901 +
8902 +static const u_int32_t ar9287Modes_9287_1_1[][6] = {
8903 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8904 + { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
8905 + { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
8906 + { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
8907 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
8908 + { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
8909 + { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
8910 + { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
8911 + { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
8912 + { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
8913 + { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
8914 + { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
8915 + { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
8916 + { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
8917 + { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
8918 + { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
8919 + { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
8920 + { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
8921 + { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
8922 + { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
8923 + { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
8924 + { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
8925 + { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
8926 + { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
8927 + { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
8928 + { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
8929 + { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
8930 + { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
8931 + { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
8932 + { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8933 + { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
8934 + { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
8935 + { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
8936 + { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
8937 + { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
8938 + { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
8939 + { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
8940 + { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8941 + { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8942 + { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
8943 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
8944 + { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
8945 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
8946 + { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
8947 +};
8948 +
8949 +static const u_int32_t ar9287Common_9287_1_1[][2] = {
8950 + { 0x0000000c, 0x00000000 },
8951 + { 0x00000030, 0x00020015 },
8952 + { 0x00000034, 0x00000005 },
8953 + { 0x00000040, 0x00000000 },
8954 + { 0x00000044, 0x00000008 },
8955 + { 0x00000048, 0x00000008 },
8956 + { 0x0000004c, 0x00000010 },
8957 + { 0x00000050, 0x00000000 },
8958 + { 0x00000054, 0x0000001f },
8959 + { 0x00000800, 0x00000000 },
8960 + { 0x00000804, 0x00000000 },
8961 + { 0x00000808, 0x00000000 },
8962 + { 0x0000080c, 0x00000000 },
8963 + { 0x00000810, 0x00000000 },
8964 + { 0x00000814, 0x00000000 },
8965 + { 0x00000818, 0x00000000 },
8966 + { 0x0000081c, 0x00000000 },
8967 + { 0x00000820, 0x00000000 },
8968 + { 0x00000824, 0x00000000 },
8969 + { 0x00001040, 0x002ffc0f },
8970 + { 0x00001044, 0x002ffc0f },
8971 + { 0x00001048, 0x002ffc0f },
8972 + { 0x0000104c, 0x002ffc0f },
8973 + { 0x00001050, 0x002ffc0f },
8974 + { 0x00001054, 0x002ffc0f },
8975 + { 0x00001058, 0x002ffc0f },
8976 + { 0x0000105c, 0x002ffc0f },
8977 + { 0x00001060, 0x002ffc0f },
8978 + { 0x00001064, 0x002ffc0f },
8979 + { 0x00001230, 0x00000000 },
8980 + { 0x00001270, 0x00000000 },
8981 + { 0x00001038, 0x00000000 },
8982 + { 0x00001078, 0x00000000 },
8983 + { 0x000010b8, 0x00000000 },
8984 + { 0x000010f8, 0x00000000 },
8985 + { 0x00001138, 0x00000000 },
8986 + { 0x00001178, 0x00000000 },
8987 + { 0x000011b8, 0x00000000 },
8988 + { 0x000011f8, 0x00000000 },
8989 + { 0x00001238, 0x00000000 },
8990 + { 0x00001278, 0x00000000 },
8991 + { 0x000012b8, 0x00000000 },
8992 + { 0x000012f8, 0x00000000 },
8993 + { 0x00001338, 0x00000000 },
8994 + { 0x00001378, 0x00000000 },
8995 + { 0x000013b8, 0x00000000 },
8996 + { 0x000013f8, 0x00000000 },
8997 + { 0x00001438, 0x00000000 },
8998 + { 0x00001478, 0x00000000 },
8999 + { 0x000014b8, 0x00000000 },
9000 + { 0x000014f8, 0x00000000 },
9001 + { 0x00001538, 0x00000000 },
9002 + { 0x00001578, 0x00000000 },
9003 + { 0x000015b8, 0x00000000 },
9004 + { 0x000015f8, 0x00000000 },
9005 + { 0x00001638, 0x00000000 },
9006 + { 0x00001678, 0x00000000 },
9007 + { 0x000016b8, 0x00000000 },
9008 + { 0x000016f8, 0x00000000 },
9009 + { 0x00001738, 0x00000000 },
9010 + { 0x00001778, 0x00000000 },
9011 + { 0x000017b8, 0x00000000 },
9012 + { 0x000017f8, 0x00000000 },
9013 + { 0x0000103c, 0x00000000 },
9014 + { 0x0000107c, 0x00000000 },
9015 + { 0x000010bc, 0x00000000 },
9016 + { 0x000010fc, 0x00000000 },
9017 + { 0x0000113c, 0x00000000 },
9018 + { 0x0000117c, 0x00000000 },
9019 + { 0x000011bc, 0x00000000 },
9020 + { 0x000011fc, 0x00000000 },
9021 + { 0x0000123c, 0x00000000 },
9022 + { 0x0000127c, 0x00000000 },
9023 + { 0x000012bc, 0x00000000 },
9024 + { 0x000012fc, 0x00000000 },
9025 + { 0x0000133c, 0x00000000 },
9026 + { 0x0000137c, 0x00000000 },
9027 + { 0x000013bc, 0x00000000 },
9028 + { 0x000013fc, 0x00000000 },
9029 + { 0x0000143c, 0x00000000 },
9030 + { 0x0000147c, 0x00000000 },
9031 + { 0x00004030, 0x00000002 },
9032 + { 0x0000403c, 0x00000002 },
9033 + { 0x00004024, 0x0000001f },
9034 + { 0x00004060, 0x00000000 },
9035 + { 0x00004064, 0x00000000 },
9036 + { 0x00007010, 0x00000033 },
9037 + { 0x00007020, 0x00000000 },
9038 + { 0x00007034, 0x00000002 },
9039 + { 0x00007038, 0x000004c2 },
9040 + { 0x00008004, 0x00000000 },
9041 + { 0x00008008, 0x00000000 },
9042 + { 0x0000800c, 0x00000000 },
9043 + { 0x00008018, 0x00000700 },
9044 + { 0x00008020, 0x00000000 },
9045 + { 0x00008038, 0x00000000 },
9046 + { 0x0000803c, 0x00000000 },
9047 + { 0x00008048, 0x40000000 },
9048 + { 0x00008054, 0x00000000 },
9049 + { 0x00008058, 0x00000000 },
9050 + { 0x0000805c, 0x000fc78f },
9051 + { 0x00008060, 0x0000000f },
9052 + { 0x00008064, 0x00000000 },
9053 + { 0x00008070, 0x00000000 },
9054 + { 0x000080c0, 0x2a80001a },
9055 + { 0x000080c4, 0x05dc01e0 },
9056 + { 0x000080c8, 0x1f402710 },
9057 + { 0x000080cc, 0x01f40000 },
9058 + { 0x000080d0, 0x00001e00 },
9059 + { 0x000080d4, 0x00000000 },
9060 + { 0x000080d8, 0x00400000 },
9061 + { 0x000080e0, 0xffffffff },
9062 + { 0x000080e4, 0x0000ffff },
9063 + { 0x000080e8, 0x003f3f3f },
9064 + { 0x000080ec, 0x00000000 },
9065 + { 0x000080f0, 0x00000000 },
9066 + { 0x000080f4, 0x00000000 },
9067 + { 0x000080f8, 0x00000000 },
9068 + { 0x000080fc, 0x00020000 },
9069 + { 0x00008100, 0x00020000 },
9070 + { 0x00008104, 0x00000001 },
9071 + { 0x00008108, 0x00000052 },
9072 + { 0x0000810c, 0x00000000 },
9073 + { 0x00008110, 0x00000168 },
9074 + { 0x00008118, 0x000100aa },
9075 + { 0x0000811c, 0x00003210 },
9076 + { 0x00008124, 0x00000000 },
9077 + { 0x00008128, 0x00000000 },
9078 + { 0x0000812c, 0x00000000 },
9079 + { 0x00008130, 0x00000000 },
9080 + { 0x00008134, 0x00000000 },
9081 + { 0x00008138, 0x00000000 },
9082 + { 0x0000813c, 0x00000000 },
9083 + { 0x00008144, 0xffffffff },
9084 + { 0x00008168, 0x00000000 },
9085 + { 0x0000816c, 0x00000000 },
9086 + { 0x00008170, 0x18487320 },
9087 + { 0x00008174, 0xfaa4fa50 },
9088 + { 0x00008178, 0x00000100 },
9089 + { 0x0000817c, 0x00000000 },
9090 + { 0x000081c0, 0x00000000 },
9091 + { 0x000081c4, 0x00000000 },
9092 + { 0x000081d4, 0x00000000 },
9093 + { 0x000081ec, 0x00000000 },
9094 + { 0x000081f0, 0x00000000 },
9095 + { 0x000081f4, 0x00000000 },
9096 + { 0x000081f8, 0x00000000 },
9097 + { 0x000081fc, 0x00000000 },
9098 + { 0x00008200, 0x00000000 },
9099 + { 0x00008204, 0x00000000 },
9100 + { 0x00008208, 0x00000000 },
9101 + { 0x0000820c, 0x00000000 },
9102 + { 0x00008210, 0x00000000 },
9103 + { 0x00008214, 0x00000000 },
9104 + { 0x00008218, 0x00000000 },
9105 + { 0x0000821c, 0x00000000 },
9106 + { 0x00008220, 0x00000000 },
9107 + { 0x00008224, 0x00000000 },
9108 + { 0x00008228, 0x00000000 },
9109 + { 0x0000822c, 0x00000000 },
9110 + { 0x00008230, 0x00000000 },
9111 + { 0x00008234, 0x00000000 },
9112 + { 0x00008238, 0x00000000 },
9113 + { 0x0000823c, 0x00000000 },
9114 + { 0x00008240, 0x00100000 },
9115 + { 0x00008244, 0x0010f400 },
9116 + { 0x00008248, 0x00000100 },
9117 + { 0x0000824c, 0x0001e800 },
9118 + { 0x00008250, 0x00000000 },
9119 + { 0x00008254, 0x00000000 },
9120 + { 0x00008258, 0x00000000 },
9121 + { 0x0000825c, 0x400000ff },
9122 + { 0x00008260, 0x00080922 },
9123 + { 0x00008264, 0x88a00010 },
9124 + { 0x00008270, 0x00000000 },
9125 + { 0x00008274, 0x40000000 },
9126 + { 0x00008278, 0x003e4180 },
9127 + { 0x0000827c, 0x00000000 },
9128 + { 0x00008284, 0x0000002c },
9129 + { 0x00008288, 0x0000002c },
9130 + { 0x0000828c, 0x000000ff },
9131 + { 0x00008294, 0x00000000 },
9132 + { 0x00008298, 0x00000000 },
9133 + { 0x0000829c, 0x00000000 },
9134 + { 0x00008300, 0x00000040 },
9135 + { 0x00008314, 0x00000000 },
9136 + { 0x00008328, 0x00000000 },
9137 + { 0x0000832c, 0x00000007 },
9138 + { 0x00008330, 0x00000302 },
9139 + { 0x00008334, 0x00000e00 },
9140 + { 0x00008338, 0x00ff0000 },
9141 + { 0x0000833c, 0x00000000 },
9142 + { 0x00008340, 0x000107ff },
9143 + { 0x00008344, 0x01c81043 },
9144 + { 0x00008360, 0xffffffff },
9145 + { 0x00008364, 0xffffffff },
9146 + { 0x00008368, 0x00000000 },
9147 + { 0x00008370, 0x00000000 },
9148 + { 0x00008374, 0x000000ff },
9149 + { 0x00008378, 0x00000000 },
9150 + { 0x0000837c, 0x00000000 },
9151 + { 0x00008380, 0xffffffff },
9152 + { 0x00008384, 0xffffffff },
9153 + { 0x00008390, 0x0fffffff },
9154 + { 0x00008394, 0x0fffffff },
9155 + { 0x00008398, 0x00000000 },
9156 + { 0x0000839c, 0x00000000 },
9157 + { 0x000083a0, 0x00000000 },
9158 + { 0x00009808, 0x00000000 },
9159 + { 0x0000980c, 0xafe68e30 },
9160 + { 0x00009810, 0xfd14e000 },
9161 + { 0x00009814, 0x9c0a9f6b },
9162 + { 0x0000981c, 0x00000000 },
9163 + { 0x0000982c, 0x0000a000 },
9164 + { 0x00009830, 0x00000000 },
9165 + { 0x0000983c, 0x00200400 },
9166 + { 0x0000984c, 0x0040233c },
9167 + { 0x0000a84c, 0x0040233c },
9168 + { 0x00009854, 0x00000044 },
9169 + { 0x00009900, 0x00000000 },
9170 + { 0x00009904, 0x00000000 },
9171 + { 0x00009908, 0x00000000 },
9172 + { 0x0000990c, 0x00000000 },
9173 + { 0x00009910, 0x10002310 },
9174 + { 0x0000991c, 0x10000fff },
9175 + { 0x00009920, 0x04900000 },
9176 + { 0x0000a920, 0x04900000 },
9177 + { 0x00009928, 0x00000001 },
9178 + { 0x0000992c, 0x00000004 },
9179 + { 0x00009930, 0x00000000 },
9180 + { 0x0000a930, 0x00000000 },
9181 + { 0x00009934, 0x1e1f2022 },
9182 + { 0x00009938, 0x0a0b0c0d },
9183 + { 0x0000993c, 0x00000000 },
9184 + { 0x00009948, 0x9280c00a },
9185 + { 0x0000994c, 0x00020028 },
9186 + { 0x00009954, 0x5f3ca3de },
9187 + { 0x00009958, 0x0108ecff },
9188 + { 0x00009940, 0x14750604 },
9189 + { 0x0000c95c, 0x004b6a8e },
9190 + { 0x00009970, 0x990bb514 },
9191 + { 0x00009974, 0x00000000 },
9192 + { 0x00009978, 0x00000001 },
9193 + { 0x0000997c, 0x00000000 },
9194 + { 0x000099a0, 0x00000000 },
9195 + { 0x000099a4, 0x00000001 },
9196 + { 0x000099a8, 0x201fff00 },
9197 + { 0x000099ac, 0x0c6f0000 },
9198 + { 0x000099b0, 0x03051000 },
9199 + { 0x000099b4, 0x00000820 },
9200 + { 0x000099c4, 0x06336f77 },
9201 + { 0x000099c8, 0x6af6532f },
9202 + { 0x000099cc, 0x08f186c8 },
9203 + { 0x000099d0, 0x00046384 },
9204 + { 0x000099dc, 0x00000000 },
9205 + { 0x000099e0, 0x00000000 },
9206 + { 0x000099e4, 0xaaaaaaaa },
9207 + { 0x000099e8, 0x3c466478 },
9208 + { 0x000099ec, 0x0cc80caa },
9209 + { 0x000099f0, 0x00000000 },
9210 + { 0x000099fc, 0x00001042 },
9211 + { 0x0000a208, 0x803e4788 },
9212 + { 0x0000a210, 0x4080a333 },
9213 + { 0x0000a214, 0x40206c10 },
9214 + { 0x0000a218, 0x009c4060 },
9215 + { 0x0000a220, 0x01834061 },
9216 + { 0x0000a224, 0x00000400 },
9217 + { 0x0000a228, 0x000003b5 },
9218 + { 0x0000a22c, 0x233f7180 },
9219 + { 0x0000a234, 0x20202020 },
9220 + { 0x0000a238, 0x20202020 },
9221 + { 0x0000a23c, 0x13c889af },
9222 + { 0x0000a240, 0x38490a20 },
9223 + { 0x0000a244, 0x00000000 },
9224 + { 0x0000a248, 0xfffffffc },
9225 + { 0x0000a24c, 0x00000000 },
9226 + { 0x0000a254, 0x00000000 },
9227 + { 0x0000a258, 0x0cdbd380 },
9228 + { 0x0000a25c, 0x0f0f0f01 },
9229 + { 0x0000a260, 0xdfa91f01 },
9230 + { 0x0000a264, 0x00418a11 },
9231 + { 0x0000b264, 0x00418a11 },
9232 + { 0x0000a268, 0x00000000 },
9233 + { 0x0000a26c, 0x0e79e5c6 },
9234 + { 0x0000b26c, 0x0e79e5c6 },
9235 + { 0x0000d270, 0x00820820 },
9236 + { 0x0000a278, 0x1ce739ce },
9237 + { 0x0000a27c, 0x050701ce },
9238 + { 0x0000d35c, 0x07ffffef },
9239 + { 0x0000d360, 0x0fffffe7 },
9240 + { 0x0000d364, 0x17ffffe5 },
9241 + { 0x0000d368, 0x1fffffe4 },
9242 + { 0x0000d36c, 0x37ffffe3 },
9243 + { 0x0000d370, 0x3fffffe3 },
9244 + { 0x0000d374, 0x57ffffe3 },
9245 + { 0x0000d378, 0x5fffffe2 },
9246 + { 0x0000d37c, 0x7fffffe2 },
9247 + { 0x0000d380, 0x7f3c7bba },
9248 + { 0x0000d384, 0xf3307ff0 },
9249 + { 0x0000a388, 0x0c000000 },
9250 + { 0x0000a38c, 0x20202020 },
9251 + { 0x0000a390, 0x20202020 },
9252 + { 0x0000a394, 0x1ce739ce },
9253 + { 0x0000a398, 0x000001ce },
9254 + { 0x0000b398, 0x000001ce },
9255 + { 0x0000a39c, 0x00000001 },
9256 + { 0x0000a3c8, 0x00000246 },
9257 + { 0x0000a3cc, 0x20202020 },
9258 + { 0x0000a3d0, 0x20202020 },
9259 + { 0x0000a3d4, 0x20202020 },
9260 + { 0x0000a3dc, 0x1ce739ce },
9261 + { 0x0000a3e0, 0x000001ce },
9262 + { 0x0000a3e4, 0x00000000 },
9263 + { 0x0000a3e8, 0x18c43433 },
9264 + { 0x0000a3ec, 0x00f70081 },
9265 + { 0x0000a3f0, 0x01036a1e },
9266 + { 0x0000a3f4, 0x00000000 },
9267 + { 0x0000b3f4, 0x00000000 },
9268 + { 0x0000a7d8, 0x000003f1 },
9269 + { 0x00007800, 0x00000800 },
9270 + { 0x00007804, 0x6c35ffd2 },
9271 + { 0x00007808, 0x6db6c000 },
9272 + { 0x0000780c, 0x6db6cb30 },
9273 + { 0x00007810, 0x6db6cb6c },
9274 + { 0x00007814, 0x0501e200 },
9275 + { 0x00007818, 0x0094128d },
9276 + { 0x0000781c, 0x976ee392 },
9277 + { 0x00007820, 0xf75ff6fc },
9278 + { 0x00007824, 0x00040000 },
9279 + { 0x00007828, 0xdb003012 },
9280 + { 0x0000782c, 0x04924914 },
9281 + { 0x00007830, 0x21084210 },
9282 + { 0x00007834, 0x00140000 },
9283 + { 0x00007838, 0x0e4548d8 },
9284 + { 0x0000783c, 0x54214514 },
9285 + { 0x00007840, 0x02025830 },
9286 + { 0x00007844, 0x71c0d388 },
9287 + { 0x00007848, 0x934934a8 },
9288 + { 0x00007850, 0x00000000 },
9289 + { 0x00007854, 0x00000800 },
9290 + { 0x00007858, 0x6c35ffd2 },
9291 + { 0x0000785c, 0x6db6c000 },
9292 + { 0x00007860, 0x6db6cb30 },
9293 + { 0x00007864, 0x6db6cb6c },
9294 + { 0x00007868, 0x0501e200 },
9295 + { 0x0000786c, 0x0094128d },
9296 + { 0x00007870, 0x976ee392 },
9297 + { 0x00007874, 0xf75ff6fc },
9298 + { 0x00007878, 0x00040000 },
9299 + { 0x0000787c, 0xdb003012 },
9300 + { 0x00007880, 0x04924914 },
9301 + { 0x00007884, 0x21084210 },
9302 + { 0x00007888, 0x001b6db0 },
9303 + { 0x0000788c, 0x00376b63 },
9304 + { 0x00007890, 0x06db6db6 },
9305 + { 0x00007894, 0x006d8000 },
9306 + { 0x00007898, 0x48100000 },
9307 + { 0x0000789c, 0x00000000 },
9308 + { 0x000078a0, 0x08000000 },
9309 + { 0x000078a4, 0x0007ffd8 },
9310 + { 0x000078a8, 0x0007ffd8 },
9311 + { 0x000078ac, 0x001c0020 },
9312 + { 0x000078b0, 0x00060aeb },
9313 + { 0x000078b4, 0x40008080 },
9314 + { 0x000078b8, 0x2a850160 },
9315 +};
9316 +
9317 +/*
9318 + * For Japanese regulatory requirements, 2484 MHz requires the following three
9319 + * registers be programmed differently from the channel between 2412 and
9320 + * 2472 MHz.
9321 + */
9322 +static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
9323 + { 0x0000a1f4, 0x00fffeff },
9324 + { 0x0000a1f8, 0x00f5f9ff },
9325 + { 0x0000a1fc, 0xb79f6427 },
9326 +};
9327 +
9328 +static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
9329 + { 0x0000a1f4, 0x00000000 },
9330 + { 0x0000a1f8, 0xefff0301 },
9331 + { 0x0000a1fc, 0xca9228ee },
9332 +};
9333 +
9334 +static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
9335 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9336 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9337 + { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
9338 + { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
9339 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
9340 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
9341 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
9342 + { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
9343 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
9344 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
9345 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
9346 + { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
9347 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
9348 + { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
9349 + { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
9350 + { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
9351 + { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
9352 + { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
9353 + { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
9354 + { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
9355 + { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
9356 + { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
9357 + { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
9358 + { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
9359 + { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
9360 + { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
9361 + { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
9362 + { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
9363 + { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
9364 + { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
9365 + { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
9366 + { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
9367 + { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
9368 + { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
9369 + { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
9370 + { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9371 + { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9372 + { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9373 + { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9374 + { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9375 + { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9376 + { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9377 + { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9378 + { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9379 + { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
9380 + { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
9381 +};
9382 +
9383 +static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
9384 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9385 + { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
9386 + { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
9387 + { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
9388 + { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
9389 + { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
9390 + { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
9391 + { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
9392 + { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
9393 + { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
9394 + { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
9395 + { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
9396 + { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
9397 + { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
9398 + { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
9399 + { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
9400 + { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
9401 + { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
9402 + { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
9403 + { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
9404 + { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
9405 + { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
9406 + { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
9407 + { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
9408 + { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
9409 + { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
9410 + { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
9411 + { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
9412 + { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
9413 + { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
9414 + { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
9415 + { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
9416 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
9417 + { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
9418 + { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
9419 + { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
9420 + { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
9421 + { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
9422 + { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
9423 + { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
9424 + { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
9425 + { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
9426 + { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
9427 + { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
9428 + { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
9429 + { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
9430 + { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
9431 + { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
9432 + { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
9433 + { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
9434 + { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
9435 + { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
9436 + { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
9437 + { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
9438 + { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
9439 + { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
9440 + { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
9441 + { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
9442 + { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
9443 + { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
9444 + { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
9445 + { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
9446 + { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
9447 + { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
9448 + { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
9449 + { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
9450 + { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
9451 + { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
9452 + { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
9453 + { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
9454 + { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
9455 + { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
9456 + { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
9457 + { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
9458 + { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
9459 + { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
9460 + { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
9461 + { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
9462 + { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
9463 + { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
9464 + { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
9465 + { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
9466 + { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
9467 + { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
9468 + { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
9469 + { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
9470 + { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
9471 + { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
9472 + { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
9473 + { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
9474 + { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
9475 + { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
9476 + { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
9477 + { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
9478 + { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
9479 + { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
9480 + { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
9481 + { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
9482 + { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
9483 + { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
9484 + { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
9485 + { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
9486 + { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
9487 + { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
9488 + { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9489 + { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9490 + { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9491 + { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9492 + { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9493 + { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9494 + { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9495 + { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9496 + { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9497 + { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9498 + { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9499 + { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9500 + { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9501 + { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9502 + { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9503 + { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9504 + { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9505 + { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9506 + { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9507 + { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9508 + { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9509 + { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9510 + { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9511 + { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9512 + { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9513 + { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
9514 + { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
9515 + { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
9516 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
9517 + { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
9518 + { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
9519 + { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
9520 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
9521 + { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
9522 + { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
9523 + { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
9524 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
9525 + { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
9526 + { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
9527 + { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
9528 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
9529 + { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
9530 + { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
9531 + { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
9532 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
9533 + { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
9534 + { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
9535 + { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
9536 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
9537 + { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
9538 + { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
9539 + { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
9540 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
9541 + { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
9542 + { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
9543 + { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
9544 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
9545 + { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
9546 + { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
9547 + { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
9548 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
9549 + { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
9550 + { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
9551 + { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
9552 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
9553 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
9554 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
9555 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
9556 + { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
9557 + { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
9558 + { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
9559 + { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
9560 + { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
9561 + { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
9562 + { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
9563 + { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
9564 + { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
9565 + { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
9566 + { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
9567 + { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
9568 + { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
9569 + { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
9570 + { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
9571 + { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
9572 + { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
9573 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
9574 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
9575 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
9576 + { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
9577 + { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
9578 + { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
9579 + { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
9580 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
9581 + { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
9582 + { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
9583 + { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
9584 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
9585 + { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
9586 + { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
9587 + { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
9588 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
9589 + { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
9590 + { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
9591 + { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
9592 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
9593 + { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
9594 + { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
9595 + { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
9596 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
9597 + { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
9598 + { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
9599 + { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
9600 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
9601 + { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
9602 + { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
9603 + { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
9604 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
9605 + { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
9606 + { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
9607 + { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
9608 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
9609 + { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
9610 + { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
9611 + { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
9612 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
9613 + { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
9614 + { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
9615 + { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
9616 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9617 + { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9618 + { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9619 + { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9620 + { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9621 + { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9622 + { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9623 + { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9624 + { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9625 + { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9626 + { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9627 + { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9628 + { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9629 + { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9630 + { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9631 + { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9632 + { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9633 + { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9634 + { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9635 + { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9636 + { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9637 + { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9638 + { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9639 + { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9640 + { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
9641 + { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
9642 + { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
9643 +};
9644 +
9645 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
9646 + {0x00004040, 0x9248fd00 },
9647 + {0x00004040, 0x24924924 },
9648 + {0x00004040, 0xa8000019 },
9649 + {0x00004040, 0x13160820 },
9650 + {0x00004040, 0xe5980560 },
9651 + {0x00004040, 0xc01dcffd },
9652 + {0x00004040, 0x1aaabe41 },
9653 + {0x00004040, 0xbe105554 },
9654 + {0x00004040, 0x00043007 },
9655 + {0x00004044, 0x00000000 },
9656 +};
9657 +
9658 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
9659 + {0x00004040, 0x9248fd00 },
9660 + {0x00004040, 0x24924924 },
9661 + {0x00004040, 0xa8000019 },
9662 + {0x00004040, 0x13160820 },
9663 + {0x00004040, 0xe5980560 },
9664 + {0x00004040, 0xc01dcffc },
9665 + {0x00004040, 0x1aaabe41 },
9666 + {0x00004040, 0xbe105554 },
9667 + {0x00004040, 0x00043007 },
9668 + {0x00004044, 0x00000000 },
9669 +};
9670 +
9671 +
9672 +/* AR9271 initialization values automaticaly created: 06/04/09 */
9673 +static const u_int32_t ar9271Modes_9271[][6] = {
9674 + { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
9675 + { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
9676 + { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
9677 + { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
9678 + { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
9679 + { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
9680 + { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
9681 + { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
9682 + { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
9683 + { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
9684 + { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
9685 + { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
9686 + { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
9687 + { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
9688 + { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
9689 + { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
9690 + { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
9691 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
9692 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
9693 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
9694 + { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
9695 + { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
9696 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
9697 + { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
9698 + { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
9699 + { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
9700 + { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
9701 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
9702 + { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
9703 + { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9704 + { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9705 + { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
9706 + { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
9707 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
9708 + { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
9709 + { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
9710 + { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
9711 + { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
9712 + { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9713 + { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
9714 + { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
9715 + { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
9716 + { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
9717 + { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
9718 + { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
9719 + { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
9720 + { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
9721 + { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
9722 + { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
9723 + { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
9724 + { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
9725 + { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
9726 + { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
9727 + { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
9728 + { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
9729 + { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
9730 + { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
9731 + { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
9732 + { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
9733 + { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
9734 + { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
9735 + { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
9736 + { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
9737 + { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
9738 + { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
9739 + { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
9740 + { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
9741 + { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
9742 + { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
9743 + { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
9744 + { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
9745 + { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
9746 + { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
9747 + { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
9748 + { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
9749 + { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
9750 + { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
9751 + { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
9752 + { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
9753 + { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
9754 + { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
9755 + { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
9756 + { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
9757 + { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
9758 + { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
9759 + { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
9760 + { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
9761 + { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
9762 + { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
9763 + { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
9764 + { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
9765 + { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
9766 + { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
9767 + { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
9768 + { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
9769 + { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
9770 + { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
9771 + { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
9772 + { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
9773 + { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
9774 + { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
9775 + { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
9776 + { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
9777 + { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
9778 + { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
9779 + { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
9780 + { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
9781 + { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
9782 + { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
9783 + { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
9784 + { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
9785 + { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
9786 + { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
9787 + { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
9788 + { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
9789 + { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
9790 + { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
9791 + { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
9792 + { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
9793 + { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
9794 + { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
9795 + { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
9796 + { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
9797 + { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
9798 + { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
9799 + { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
9800 + { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
9801 + { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
9802 + { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
9803 + { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9804 + { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9805 + { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9806 + { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9807 + { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9808 + { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9809 + { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9810 + { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9811 + { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9812 + { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9813 + { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9814 + { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9815 + { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9816 + { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9817 + { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9818 + { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9819 + { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9820 + { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9821 + { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9822 + { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9823 + { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9824 + { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9825 + { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9826 + { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9827 + { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9828 + { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9829 + { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9830 + { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9831 + { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9832 + { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9833 + { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9834 + { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9835 + { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9836 + { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9837 + { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9838 + { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9839 + { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9840 + { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9841 + { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9842 + { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
9843 + { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
9844 + { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
9845 + { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
9846 + { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
9847 + { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
9848 + { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
9849 + { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
9850 + { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
9851 + { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
9852 + { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
9853 + { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
9854 + { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
9855 + { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
9856 + { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
9857 + { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
9858 + { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
9859 + { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
9860 + { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
9861 + { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
9862 + { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
9863 + { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
9864 + { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
9865 + { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
9866 + { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
9867 + { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
9868 + { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
9869 + { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
9870 + { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
9871 + { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
9872 + { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
9873 + { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
9874 + { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
9875 + { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
9876 + { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
9877 + { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
9878 + { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
9879 + { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
9880 + { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
9881 + { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
9882 + { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
9883 + { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
9884 + { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
9885 + { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
9886 + { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
9887 + { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
9888 + { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
9889 + { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
9890 + { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
9891 + { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
9892 + { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
9893 + { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
9894 + { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
9895 + { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
9896 + { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
9897 + { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
9898 + { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
9899 + { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
9900 + { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
9901 + { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
9902 + { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
9903 + { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
9904 + { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
9905 + { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
9906 + { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
9907 + { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
9908 + { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
9909 + { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
9910 + { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
9911 + { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
9912 + { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
9913 + { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
9914 + { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
9915 + { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
9916 + { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
9917 + { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
9918 + { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
9919 + { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
9920 + { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
9921 + { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
9922 + { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
9923 + { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
9924 + { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
9925 + { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
9926 + { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
9927 + { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
9928 + { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
9929 + { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
9930 + { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
9931 + { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9932 + { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9933 + { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9934 + { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9935 + { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9936 + { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9937 + { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9938 + { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9939 + { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9940 + { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9941 + { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9942 + { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9943 + { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9944 + { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9945 + { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9946 + { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9947 + { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9948 + { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9949 + { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9950 + { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9951 + { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9952 + { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9953 + { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9954 + { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9955 + { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9956 + { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9957 + { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9958 + { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9959 + { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9960 + { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9961 + { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9962 + { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9963 + { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9964 + { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9965 + { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9966 + { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9967 + { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9968 + { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9969 + { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
9970 + { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
9971 + { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
9972 + { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
9973 + { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
9974 + { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
9975 + { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
9976 + { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
9977 +};
9978 +
9979 +static const u_int32_t ar9271Common_9271[][2] = {
9980 + { 0x0000000c, 0x00000000 },
9981 + { 0x00000030, 0x00020045 },
9982 + { 0x00000034, 0x00000005 },
9983 + { 0x00000040, 0x00000000 },
9984 + { 0x00000044, 0x00000008 },
9985 + { 0x00000048, 0x00000008 },
9986 + { 0x0000004c, 0x00000010 },
9987 + { 0x00000050, 0x00000000 },
9988 + { 0x00000054, 0x0000001f },
9989 + { 0x00000800, 0x00000000 },
9990 + { 0x00000804, 0x00000000 },
9991 + { 0x00000808, 0x00000000 },
9992 + { 0x0000080c, 0x00000000 },
9993 + { 0x00000810, 0x00000000 },
9994 + { 0x00000814, 0x00000000 },
9995 + { 0x00000818, 0x00000000 },
9996 + { 0x0000081c, 0x00000000 },
9997 + { 0x00000820, 0x00000000 },
9998 + { 0x00000824, 0x00000000 },
9999 + { 0x00001040, 0x002ffc0f },
10000 + { 0x00001044, 0x002ffc0f },
10001 + { 0x00001048, 0x002ffc0f },
10002 + { 0x0000104c, 0x002ffc0f },
10003 + { 0x00001050, 0x002ffc0f },
10004 + { 0x00001054, 0x002ffc0f },
10005 + { 0x00001058, 0x002ffc0f },
10006 + { 0x0000105c, 0x002ffc0f },
10007 + { 0x00001060, 0x002ffc0f },
10008 + { 0x00001064, 0x002ffc0f },
10009 + { 0x00001230, 0x00000000 },
10010 + { 0x00001270, 0x00000000 },
10011 + { 0x00001038, 0x00000000 },
10012 + { 0x00001078, 0x00000000 },
10013 + { 0x000010b8, 0x00000000 },
10014 + { 0x000010f8, 0x00000000 },
10015 + { 0x00001138, 0x00000000 },
10016 + { 0x00001178, 0x00000000 },
10017 + { 0x000011b8, 0x00000000 },
10018 + { 0x000011f8, 0x00000000 },
10019 + { 0x00001238, 0x00000000 },
10020 + { 0x00001278, 0x00000000 },
10021 + { 0x000012b8, 0x00000000 },
10022 + { 0x000012f8, 0x00000000 },
10023 + { 0x00001338, 0x00000000 },
10024 + { 0x00001378, 0x00000000 },
10025 + { 0x000013b8, 0x00000000 },
10026 + { 0x000013f8, 0x00000000 },
10027 + { 0x00001438, 0x00000000 },
10028 + { 0x00001478, 0x00000000 },
10029 + { 0x000014b8, 0x00000000 },
10030 + { 0x000014f8, 0x00000000 },
10031 + { 0x00001538, 0x00000000 },
10032 + { 0x00001578, 0x00000000 },
10033 + { 0x000015b8, 0x00000000 },
10034 + { 0x000015f8, 0x00000000 },
10035 + { 0x00001638, 0x00000000 },
10036 + { 0x00001678, 0x00000000 },
10037 + { 0x000016b8, 0x00000000 },
10038 + { 0x000016f8, 0x00000000 },
10039 + { 0x00001738, 0x00000000 },
10040 + { 0x00001778, 0x00000000 },
10041 + { 0x000017b8, 0x00000000 },
10042 + { 0x000017f8, 0x00000000 },
10043 + { 0x0000103c, 0x00000000 },
10044 + { 0x0000107c, 0x00000000 },
10045 + { 0x000010bc, 0x00000000 },
10046 + { 0x000010fc, 0x00000000 },
10047 + { 0x0000113c, 0x00000000 },
10048 + { 0x0000117c, 0x00000000 },
10049 + { 0x000011bc, 0x00000000 },
10050 + { 0x000011fc, 0x00000000 },
10051 + { 0x0000123c, 0x00000000 },
10052 + { 0x0000127c, 0x00000000 },
10053 + { 0x000012bc, 0x00000000 },
10054 + { 0x000012fc, 0x00000000 },
10055 + { 0x0000133c, 0x00000000 },
10056 + { 0x0000137c, 0x00000000 },
10057 + { 0x000013bc, 0x00000000 },
10058 + { 0x000013fc, 0x00000000 },
10059 + { 0x0000143c, 0x00000000 },
10060 + { 0x0000147c, 0x00000000 },
10061 + { 0x00004030, 0x00000002 },
10062 + { 0x0000403c, 0x00000002 },
10063 + { 0x00004024, 0x0000001f },
10064 + { 0x00004060, 0x00000000 },
10065 + { 0x00004064, 0x00000000 },
10066 + { 0x00008004, 0x00000000 },
10067 + { 0x00008008, 0x00000000 },
10068 + { 0x0000800c, 0x00000000 },
10069 + { 0x00008018, 0x00000700 },
10070 + { 0x00008020, 0x00000000 },
10071 + { 0x00008038, 0x00000000 },
10072 + { 0x0000803c, 0x00000000 },
10073 + { 0x00008048, 0x00000000 },
10074 + { 0x00008054, 0x00000000 },
10075 + { 0x00008058, 0x00000000 },
10076 + { 0x0000805c, 0x000fc78f },
10077 + { 0x00008060, 0x0000000f },
10078 + { 0x00008064, 0x00000000 },
10079 + { 0x00008070, 0x00000000 },
10080 + { 0x000080b0, 0x00000000 },
10081 + { 0x000080b4, 0x00000000 },
10082 + { 0x000080b8, 0x00000000 },
10083 + { 0x000080bc, 0x00000000 },
10084 + { 0x000080c0, 0x2a80001a },
10085 + { 0x000080c4, 0x05dc01e0 },
10086 + { 0x000080c8, 0x1f402710 },
10087 + { 0x000080cc, 0x01f40000 },
10088 + { 0x000080d0, 0x00001e00 },
10089 + { 0x000080d4, 0x00000000 },
10090 + { 0x000080d8, 0x00400000 },
10091 + { 0x000080e0, 0xffffffff },
10092 + { 0x000080e4, 0x0000ffff },
10093 + { 0x000080e8, 0x003f3f3f },
10094 + { 0x000080ec, 0x00000000 },
10095 + { 0x000080f0, 0x00000000 },
10096 + { 0x000080f4, 0x00000000 },
10097 + { 0x000080f8, 0x00000000 },
10098 + { 0x000080fc, 0x00020000 },
10099 + { 0x00008100, 0x00020000 },
10100 + { 0x00008104, 0x00000001 },
10101 + { 0x00008108, 0x00000052 },
10102 + { 0x0000810c, 0x00000000 },
10103 + { 0x00008110, 0x00000168 },
10104 + { 0x00008118, 0x000100aa },
10105 + { 0x0000811c, 0x00003210 },
10106 + { 0x00008120, 0x08f04810 },
10107 + { 0x00008124, 0x00000000 },
10108 + { 0x00008128, 0x00000000 },
10109 + { 0x0000812c, 0x00000000 },
10110 + { 0x00008130, 0x00000000 },
10111 + { 0x00008134, 0x00000000 },
10112 + { 0x00008138, 0x00000000 },
10113 + { 0x0000813c, 0x00000000 },
10114 + { 0x00008144, 0xffffffff },
10115 + { 0x00008168, 0x00000000 },
10116 + { 0x0000816c, 0x00000000 },
10117 + { 0x00008170, 0x32143320 },
10118 + { 0x00008174, 0xfaa4fa50 },
10119 + { 0x00008178, 0x00000100 },
10120 + { 0x0000817c, 0x00000000 },
10121 + { 0x000081c0, 0x00000000 },
10122 + { 0x000081d0, 0x0000320a },
10123 + { 0x000081ec, 0x00000000 },
10124 + { 0x000081f0, 0x00000000 },
10125 + { 0x000081f4, 0x00000000 },
10126 + { 0x000081f8, 0x00000000 },
10127 + { 0x000081fc, 0x00000000 },
10128 + { 0x00008200, 0x00000000 },
10129 + { 0x00008204, 0x00000000 },
10130 + { 0x00008208, 0x00000000 },
10131 + { 0x0000820c, 0x00000000 },
10132 + { 0x00008210, 0x00000000 },
10133 + { 0x00008214, 0x00000000 },
10134 + { 0x00008218, 0x00000000 },
10135 + { 0x0000821c, 0x00000000 },
10136 + { 0x00008220, 0x00000000 },
10137 + { 0x00008224, 0x00000000 },
10138 + { 0x00008228, 0x00000000 },
10139 + { 0x0000822c, 0x00000000 },
10140 + { 0x00008230, 0x00000000 },
10141 + { 0x00008234, 0x00000000 },
10142 + { 0x00008238, 0x00000000 },
10143 + { 0x0000823c, 0x00000000 },
10144 + { 0x00008240, 0x00100000 },
10145 + { 0x00008244, 0x0010f400 },
10146 + { 0x00008248, 0x00000100 },
10147 + { 0x0000824c, 0x0001e800 },
10148 + { 0x00008250, 0x00000000 },
10149 + { 0x00008254, 0x00000000 },
10150 + { 0x00008258, 0x00000000 },
10151 + { 0x0000825c, 0x400000ff },
10152 + { 0x00008260, 0x00080922 },
10153 + { 0x00008264, 0xa8a00010 },
10154 + { 0x00008270, 0x00000000 },
10155 + { 0x00008274, 0x40000000 },
10156 + { 0x00008278, 0x003e4180 },
10157 + { 0x0000827c, 0x00000000 },
10158 + { 0x00008284, 0x0000002c },
10159 + { 0x00008288, 0x0000002c },
10160 + { 0x0000828c, 0x00000000 },
10161 + { 0x00008294, 0x00000000 },
10162 + { 0x00008298, 0x00000000 },
10163 + { 0x0000829c, 0x00000000 },
10164 + { 0x00008300, 0x00000040 },
10165 + { 0x00008314, 0x00000000 },
10166 + { 0x00008328, 0x00000000 },
10167 + { 0x0000832c, 0x00000001 },
10168 + { 0x00008330, 0x00000302 },
10169 + { 0x00008334, 0x00000e00 },
10170 + { 0x00008338, 0x00ff0000 },
10171 + { 0x0000833c, 0x00000000 },
10172 + { 0x00008340, 0x00010380 },
10173 + { 0x00008344, 0x00581043 },
10174 + { 0x00007010, 0x00000030 },
10175 + { 0x00007034, 0x00000002 },
10176 + { 0x00007038, 0x000004c2 },
10177 + { 0x00007800, 0x00140000 },
10178 + { 0x00007804, 0x0e4548d8 },
10179 + { 0x00007808, 0x54214514 },
10180 + { 0x0000780c, 0x02025820 },
10181 + { 0x00007810, 0x71c0d388 },
10182 + { 0x00007814, 0x924934a8 },
10183 + { 0x0000781c, 0x00000000 },
10184 + { 0x00007828, 0x66964300 },
10185 + { 0x0000782c, 0x8db6d961 },
10186 + { 0x00007830, 0x8db6d96c },
10187 + { 0x00007834, 0x6140008b },
10188 + { 0x0000783c, 0x72ee0a72 },
10189 + { 0x00007840, 0xbbfffffc },
10190 + { 0x00007844, 0x000c0db6 },
10191 + { 0x00007848, 0x6db61b6f },
10192 + { 0x0000784c, 0x6d9b66db },
10193 + { 0x00007850, 0x6d8c6dba },
10194 + { 0x00007854, 0x00040000 },
10195 + { 0x00007858, 0xdb003012 },
10196 + { 0x0000785c, 0x04924914 },
10197 + { 0x00007860, 0x21084210 },
10198 + { 0x00007864, 0xf7d7ffde },
10199 + { 0x00007868, 0xc2034080 },
10200 + { 0x00007870, 0x10142c00 },
10201 + { 0x00009808, 0x00000000 },
10202 + { 0x0000980c, 0xafe68e30 },
10203 + { 0x00009810, 0xfd14e000 },
10204 + { 0x00009814, 0x9c0a9f6b },
10205 + { 0x0000981c, 0x00000000 },
10206 + { 0x0000982c, 0x0000a000 },
10207 + { 0x00009830, 0x00000000 },
10208 + { 0x0000983c, 0x00200400 },
10209 + { 0x0000984c, 0x0040233c },
10210 + { 0x00009854, 0x00000044 },
10211 + { 0x00009900, 0x00000000 },
10212 + { 0x00009904, 0x00000000 },
10213 + { 0x00009908, 0x00000000 },
10214 + { 0x0000990c, 0x00000000 },
10215 + { 0x0000991c, 0x10000fff },
10216 + { 0x00009920, 0x04900000 },
10217 + { 0x00009928, 0x00000001 },
10218 + { 0x0000992c, 0x00000004 },
10219 + { 0x00009934, 0x1e1f2022 },
10220 + { 0x00009938, 0x0a0b0c0d },
10221 + { 0x0000993c, 0x00000000 },
10222 + { 0x00009940, 0x14750604 },
10223 + { 0x00009948, 0x9280c00a },
10224 + { 0x0000994c, 0x00020028 },
10225 + { 0x00009954, 0x5f3ca3de },
10226 + { 0x00009958, 0x0108ecff },
10227 + { 0x00009968, 0x000003ce },
10228 + { 0x00009970, 0x192bb514 },
10229 + { 0x00009974, 0x00000000 },
10230 + { 0x00009978, 0x00000001 },
10231 + { 0x0000997c, 0x00000000 },
10232 + { 0x00009980, 0x00000000 },
10233 + { 0x00009984, 0x00000000 },
10234 + { 0x00009988, 0x00000000 },
10235 + { 0x0000998c, 0x00000000 },
10236 + { 0x00009990, 0x00000000 },
10237 + { 0x00009994, 0x00000000 },
10238 + { 0x00009998, 0x00000000 },
10239 + { 0x0000999c, 0x00000000 },
10240 + { 0x000099a0, 0x00000000 },
10241 + { 0x000099a4, 0x00000001 },
10242 + { 0x000099a8, 0x201fff00 },
10243 + { 0x000099ac, 0x2def0400 },
10244 + { 0x000099b0, 0x03051000 },
10245 + { 0x000099b4, 0x00000820 },
10246 + { 0x000099dc, 0x00000000 },
10247 + { 0x000099e0, 0x00000000 },
10248 + { 0x000099e4, 0xaaaaaaaa },
10249 + { 0x000099e8, 0x3c466478 },
10250 + { 0x000099ec, 0x0cc80caa },
10251 + { 0x000099f0, 0x00000000 },
10252 + { 0x0000a208, 0x803e68c8 },
10253 + { 0x0000a210, 0x4080a333 },
10254 + { 0x0000a214, 0x00206c10 },
10255 + { 0x0000a218, 0x009c4060 },
10256 + { 0x0000a220, 0x01834061 },
10257 + { 0x0000a224, 0x00000400 },
10258 + { 0x0000a228, 0x000003b5 },
10259 + { 0x0000a22c, 0x00000000 },
10260 + { 0x0000a234, 0x20202020 },
10261 + { 0x0000a238, 0x20202020 },
10262 + { 0x0000a244, 0x00000000 },
10263 + { 0x0000a248, 0xfffffffc },
10264 + { 0x0000a24c, 0x00000000 },
10265 + { 0x0000a254, 0x00000000 },
10266 + { 0x0000a258, 0x0ccb5380 },
10267 + { 0x0000a25c, 0x15151501 },
10268 + { 0x0000a260, 0xdfa90f01 },
10269 + { 0x0000a268, 0x00000000 },
10270 + { 0x0000a26c, 0x0ebae9e6 },
10271 + { 0x0000a388, 0x0c000000 },
10272 + { 0x0000a38c, 0x20202020 },
10273 + { 0x0000a390, 0x20202020 },
10274 + { 0x0000a39c, 0x00000001 },
10275 + { 0x0000a3a0, 0x00000000 },
10276 + { 0x0000a3a4, 0x00000000 },
10277 + { 0x0000a3a8, 0x00000000 },
10278 + { 0x0000a3ac, 0x00000000 },
10279 + { 0x0000a3b0, 0x00000000 },
10280 + { 0x0000a3b4, 0x00000000 },
10281 + { 0x0000a3b8, 0x00000000 },
10282 + { 0x0000a3bc, 0x00000000 },
10283 + { 0x0000a3c0, 0x00000000 },
10284 + { 0x0000a3c4, 0x00000000 },
10285 + { 0x0000a3cc, 0x20202020 },
10286 + { 0x0000a3d0, 0x20202020 },
10287 + { 0x0000a3d4, 0x20202020 },
10288 + { 0x0000a3e4, 0x00000000 },
10289 + { 0x0000a3e8, 0x18c43433 },
10290 + { 0x0000a3ec, 0x00f70081 },
10291 + { 0x0000a3f0, 0x01036a2f },
10292 + { 0x0000a3f4, 0x00000000 },
10293 + { 0x0000d270, 0x0d820820 },
10294 + { 0x0000d35c, 0x07ffffef },
10295 + { 0x0000d360, 0x0fffffe7 },
10296 + { 0x0000d364, 0x17ffffe5 },
10297 + { 0x0000d368, 0x1fffffe4 },
10298 + { 0x0000d36c, 0x37ffffe3 },
10299 + { 0x0000d370, 0x3fffffe3 },
10300 + { 0x0000d374, 0x57ffffe3 },
10301 + { 0x0000d378, 0x5fffffe2 },
10302 + { 0x0000d37c, 0x7fffffe2 },
10303 + { 0x0000d380, 0x7f3c7bba },
10304 + { 0x0000d384, 0xf3307ff0 },
10305 +};
10306 +
10307 +static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
10308 + { 0x0000a1f4, 0x00fffeff },
10309 + { 0x0000a1f8, 0x00f5f9ff },
10310 + { 0x0000a1fc, 0xb79f6427 },
10311 +};
10312 +
10313 +static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
10314 + { 0x0000a1f4, 0x00000000 },
10315 + { 0x0000a1f8, 0xefff0301 },
10316 + { 0x0000a1fc, 0xca9228ee },
10317 +};
10318 +
10319 +static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
10320 + { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
10321 + { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
10322 +};
10323 +
10324 +static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
10325 + { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
10326 + { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
10327 + { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
10328 + { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
10329 + { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
10330 + { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
10331 + { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
10332 + { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
10333 +};
10334 +
10335 +static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
10336 + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
10337 + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
10338 + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
10339 + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
10340 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
10341 + { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
10342 + { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
10343 + { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
10344 + { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
10345 + { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
10346 + { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
10347 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
10348 + { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
10349 + { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
10350 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
10351 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
10352 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10353 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10354 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10355 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10356 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10357 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10358 + { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
10359 + { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
10360 + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
10361 + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
10362 + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
10363 + { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10364 + { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
10365 + { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10366 + { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
10367 + { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
10368 + { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
10369 +};
10370 +
10371 +static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
10372 + { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
10373 + { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
10374 + { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
10375 + { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
10376 + { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
10377 + { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
10378 + { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
10379 + { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
10380 + { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
10381 + { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
10382 + { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
10383 + { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
10384 + { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
10385 + { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
10386 + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
10387 + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
10388 + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10389 + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10390 + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10391 + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10392 + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10393 + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
10394 + { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
10395 + { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
10396 + { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
10397 + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
10398 + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
10399 + { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
10400 + { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
10401 + { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
10402 + { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
10403 + { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
10404 + { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
10405 +};
10406 +
10407 +#endif /* INITVALS_9002_10_H */
10408 --- /dev/null
10409 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
10410 @@ -0,0 +1,480 @@
10411 +/*
10412 + * Copyright (c) 2008-2009 Atheros Communications Inc.
10413 + *
10414 + * Permission to use, copy, modify, and/or distribute this software for any
10415 + * purpose with or without fee is hereby granted, provided that the above
10416 + * copyright notice and this permission notice appear in all copies.
10417 + *
10418 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10419 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10420 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10421 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10422 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
10423 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
10424 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
10425 + */
10426 +
10427 +#include "hw.h"
10428 +
10429 +#define AR_BufLen 0x00000fff
10430 +
10431 +static void ar9002_hw_rx_enable(struct ath_hw *ah)
10432 +{
10433 + REG_WRITE(ah, AR_CR, AR_CR_RXE);
10434 +}
10435 +
10436 +static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
10437 +{
10438 + ((struct ath_desc*) ds)->ds_link = ds_link;
10439 +}
10440 +
10441 +static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
10442 +{
10443 + *ds_link = &((struct ath_desc *)ds)->ds_link;
10444 +}
10445 +
10446 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
10447 +{
10448 + u32 isr = 0;
10449 + u32 mask2 = 0;
10450 + struct ath9k_hw_capabilities *pCap = &ah->caps;
10451 + u32 sync_cause = 0;
10452 + bool fatal_int = false;
10453 + struct ath_common *common = ath9k_hw_common(ah);
10454 +
10455 + if (!AR_SREV_9100(ah)) {
10456 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
10457 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
10458 + == AR_RTC_STATUS_ON) {
10459 + isr = REG_READ(ah, AR_ISR);
10460 + }
10461 + }
10462 +
10463 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
10464 + AR_INTR_SYNC_DEFAULT;
10465 +
10466 + *masked = 0;
10467 +
10468 + if (!isr && !sync_cause)
10469 + return false;
10470 + } else {
10471 + *masked = 0;
10472 + isr = REG_READ(ah, AR_ISR);
10473 + }
10474 +
10475 + if (isr) {
10476 + if (isr & AR_ISR_BCNMISC) {
10477 + u32 isr2;
10478 + isr2 = REG_READ(ah, AR_ISR_S2);
10479 + if (isr2 & AR_ISR_S2_TIM)
10480 + mask2 |= ATH9K_INT_TIM;
10481 + if (isr2 & AR_ISR_S2_DTIM)
10482 + mask2 |= ATH9K_INT_DTIM;
10483 + if (isr2 & AR_ISR_S2_DTIMSYNC)
10484 + mask2 |= ATH9K_INT_DTIMSYNC;
10485 + if (isr2 & (AR_ISR_S2_CABEND))
10486 + mask2 |= ATH9K_INT_CABEND;
10487 + if (isr2 & AR_ISR_S2_GTT)
10488 + mask2 |= ATH9K_INT_GTT;
10489 + if (isr2 & AR_ISR_S2_CST)
10490 + mask2 |= ATH9K_INT_CST;
10491 + if (isr2 & AR_ISR_S2_TSFOOR)
10492 + mask2 |= ATH9K_INT_TSFOOR;
10493 + }
10494 +
10495 + isr = REG_READ(ah, AR_ISR_RAC);
10496 + if (isr == 0xffffffff) {
10497 + *masked = 0;
10498 + return false;
10499 + }
10500 +
10501 + *masked = isr & ATH9K_INT_COMMON;
10502 +
10503 + if (ah->config.rx_intr_mitigation) {
10504 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
10505 + *masked |= ATH9K_INT_RX;
10506 + }
10507 +
10508 + if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
10509 + *masked |= ATH9K_INT_RX;
10510 + if (isr &
10511 + (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
10512 + AR_ISR_TXEOL)) {
10513 + u32 s0_s, s1_s;
10514 +
10515 + *masked |= ATH9K_INT_TX;
10516 +
10517 + s0_s = REG_READ(ah, AR_ISR_S0_S);
10518 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
10519 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
10520 +
10521 + s1_s = REG_READ(ah, AR_ISR_S1_S);
10522 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
10523 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
10524 + }
10525 +
10526 + if (isr & AR_ISR_RXORN) {
10527 + ath_print(common, ATH_DBG_INTERRUPT,
10528 + "receive FIFO overrun interrupt\n");
10529 + }
10530 +
10531 + if (!AR_SREV_9100(ah)) {
10532 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
10533 + u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
10534 + if (isr5 & AR_ISR_S5_TIM_TIMER)
10535 + *masked |= ATH9K_INT_TIM_TIMER;
10536 + }
10537 + }
10538 +
10539 + *masked |= mask2;
10540 + }
10541 +
10542 + if (AR_SREV_9100(ah))
10543 + return true;
10544 +
10545 + if (isr & AR_ISR_GENTMR) {
10546 + u32 s5_s;
10547 +
10548 + s5_s = REG_READ(ah, AR_ISR_S5_S);
10549 + if (isr & AR_ISR_GENTMR) {
10550 + ah->intr_gen_timer_trigger =
10551 + MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
10552 +
10553 + ah->intr_gen_timer_thresh =
10554 + MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
10555 +
10556 + if (ah->intr_gen_timer_trigger)
10557 + *masked |= ATH9K_INT_GENTIMER;
10558 +
10559 + }
10560 + }
10561 +
10562 + if (sync_cause) {
10563 + fatal_int =
10564 + (sync_cause &
10565 + (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
10566 + ? true : false;
10567 +
10568 + if (fatal_int) {
10569 + if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
10570 + ath_print(common, ATH_DBG_ANY,
10571 + "received PCI FATAL interrupt\n");
10572 + }
10573 + if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
10574 + ath_print(common, ATH_DBG_ANY,
10575 + "received PCI PERR interrupt\n");
10576 + }
10577 + *masked |= ATH9K_INT_FATAL;
10578 + }
10579 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
10580 + ath_print(common, ATH_DBG_INTERRUPT,
10581 + "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
10582 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
10583 + REG_WRITE(ah, AR_RC, 0);
10584 + *masked |= ATH9K_INT_FATAL;
10585 + }
10586 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
10587 + ath_print(common, ATH_DBG_INTERRUPT,
10588 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
10589 + }
10590 +
10591 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
10592 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
10593 + }
10594 +
10595 + return true;
10596 +}
10597 +
10598 +static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
10599 + bool is_firstseg, bool is_lastseg,
10600 + const void *ds0, dma_addr_t buf_addr,
10601 + unsigned int qcu)
10602 +{
10603 + struct ar5416_desc *ads = AR5416DESC(ds);
10604 +
10605 + ads->ds_data = buf_addr;
10606 +
10607 + if (is_firstseg) {
10608 + ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
10609 + } else if (is_lastseg) {
10610 + ads->ds_ctl0 = 0;
10611 + ads->ds_ctl1 = seglen;
10612 + ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
10613 + ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
10614 + } else {
10615 + ads->ds_ctl0 = 0;
10616 + ads->ds_ctl1 = seglen | AR_TxMore;
10617 + ads->ds_ctl2 = 0;
10618 + ads->ds_ctl3 = 0;
10619 + }
10620 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
10621 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
10622 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
10623 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
10624 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
10625 +}
10626 +
10627 +static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
10628 + struct ath_tx_status *ts)
10629 +{
10630 + struct ar5416_desc *ads = AR5416DESC(ds);
10631 +
10632 + if ((ads->ds_txstatus9 & AR_TxDone) == 0)
10633 + return -EINPROGRESS;
10634 +
10635 + ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
10636 + ts->ts_tstamp = ads->AR_SendTimestamp;
10637 + ts->ts_status = 0;
10638 + ts->ts_flags = 0;
10639 +
10640 + if (ads->ds_txstatus1 & AR_FrmXmitOK)
10641 + ts->ts_status |= ATH9K_TX_ACKED;
10642 + if (ads->ds_txstatus1 & AR_ExcessiveRetries)
10643 + ts->ts_status |= ATH9K_TXERR_XRETRY;
10644 + if (ads->ds_txstatus1 & AR_Filtered)
10645 + ts->ts_status |= ATH9K_TXERR_FILT;
10646 + if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
10647 + ts->ts_status |= ATH9K_TXERR_FIFO;
10648 + ath9k_hw_updatetxtriglevel(ah, true);
10649 + }
10650 + if (ads->ds_txstatus9 & AR_TxOpExceeded)
10651 + ts->ts_status |= ATH9K_TXERR_XTXOP;
10652 + if (ads->ds_txstatus1 & AR_TxTimerExpired)
10653 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
10654 +
10655 + if (ads->ds_txstatus1 & AR_DescCfgErr)
10656 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
10657 + if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
10658 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
10659 + ath9k_hw_updatetxtriglevel(ah, true);
10660 + }
10661 + if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
10662 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
10663 + ath9k_hw_updatetxtriglevel(ah, true);
10664 + }
10665 + if (ads->ds_txstatus0 & AR_TxBaStatus) {
10666 + ts->ts_flags |= ATH9K_TX_BA;
10667 + ts->ba_low = ads->AR_BaBitmapLow;
10668 + ts->ba_high = ads->AR_BaBitmapHigh;
10669 + }
10670 +
10671 + ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
10672 + switch (ts->ts_rateindex) {
10673 + case 0:
10674 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
10675 + break;
10676 + case 1:
10677 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
10678 + break;
10679 + case 2:
10680 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
10681 + break;
10682 + case 3:
10683 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
10684 + break;
10685 + }
10686 +
10687 + ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
10688 + ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
10689 + ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
10690 + ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
10691 + ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
10692 + ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
10693 + ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
10694 + ts->evm0 = ads->AR_TxEVM0;
10695 + ts->evm1 = ads->AR_TxEVM1;
10696 + ts->evm2 = ads->AR_TxEVM2;
10697 + ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
10698 + ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
10699 + ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
10700 + ts->ts_antenna = 0;
10701 +
10702 + return 0;
10703 +}
10704 +
10705 +static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
10706 + u32 pktLen, enum ath9k_pkt_type type,
10707 + u32 txPower, u32 keyIx,
10708 + enum ath9k_key_type keyType, u32 flags)
10709 +{
10710 + struct ar5416_desc *ads = AR5416DESC(ds);
10711 +
10712 + txPower += ah->txpower_indexoffset;
10713 + if (txPower > 63)
10714 + txPower = 63;
10715 +
10716 + ads->ds_ctl0 = (pktLen & AR_FrameLen)
10717 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
10718 + | SM(txPower, AR_XmitPower)
10719 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
10720 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
10721 + | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
10722 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
10723 +
10724 + ads->ds_ctl1 =
10725 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
10726 + | SM(type, AR_FrameType)
10727 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
10728 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
10729 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
10730 +
10731 + ads->ds_ctl6 = SM(keyType, AR_EncrType);
10732 +
10733 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
10734 + ads->ds_ctl8 = 0;
10735 + ads->ds_ctl9 = 0;
10736 + ads->ds_ctl10 = 0;
10737 + ads->ds_ctl11 = 0;
10738 + }
10739 +}
10740 +
10741 +static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
10742 + void *lastds,
10743 + u32 durUpdateEn, u32 rtsctsRate,
10744 + u32 rtsctsDuration,
10745 + struct ath9k_11n_rate_series series[],
10746 + u32 nseries, u32 flags)
10747 +{
10748 + struct ar5416_desc *ads = AR5416DESC(ds);
10749 + struct ar5416_desc *last_ads = AR5416DESC(lastds);
10750 + u32 ds_ctl0;
10751 +
10752 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
10753 + ds_ctl0 = ads->ds_ctl0;
10754 +
10755 + if (flags & ATH9K_TXDESC_RTSENA) {
10756 + ds_ctl0 &= ~AR_CTSEnable;
10757 + ds_ctl0 |= AR_RTSEnable;
10758 + } else {
10759 + ds_ctl0 &= ~AR_RTSEnable;
10760 + ds_ctl0 |= AR_CTSEnable;
10761 + }
10762 +
10763 + ads->ds_ctl0 = ds_ctl0;
10764 + } else {
10765 + ads->ds_ctl0 =
10766 + (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
10767 + }
10768 +
10769 + ads->ds_ctl2 = set11nTries(series, 0)
10770 + | set11nTries(series, 1)
10771 + | set11nTries(series, 2)
10772 + | set11nTries(series, 3)
10773 + | (durUpdateEn ? AR_DurUpdateEna : 0)
10774 + | SM(0, AR_BurstDur);
10775 +
10776 + ads->ds_ctl3 = set11nRate(series, 0)
10777 + | set11nRate(series, 1)
10778 + | set11nRate(series, 2)
10779 + | set11nRate(series, 3);
10780 +
10781 + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
10782 + | set11nPktDurRTSCTS(series, 1);
10783 +
10784 + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
10785 + | set11nPktDurRTSCTS(series, 3);
10786 +
10787 + ads->ds_ctl7 = set11nRateFlags(series, 0)
10788 + | set11nRateFlags(series, 1)
10789 + | set11nRateFlags(series, 2)
10790 + | set11nRateFlags(series, 3)
10791 + | SM(rtsctsRate, AR_RTSCTSRate);
10792 + last_ads->ds_ctl2 = ads->ds_ctl2;
10793 + last_ads->ds_ctl3 = ads->ds_ctl3;
10794 +}
10795 +
10796 +static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
10797 + u32 aggrLen)
10798 +{
10799 + struct ar5416_desc *ads = AR5416DESC(ds);
10800 +
10801 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
10802 + ads->ds_ctl6 &= ~AR_AggrLen;
10803 + ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
10804 +}
10805 +
10806 +static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
10807 + u32 numDelims)
10808 +{
10809 + struct ar5416_desc *ads = AR5416DESC(ds);
10810 + unsigned int ctl6;
10811 +
10812 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
10813 +
10814 + ctl6 = ads->ds_ctl6;
10815 + ctl6 &= ~AR_PadDelim;
10816 + ctl6 |= SM(numDelims, AR_PadDelim);
10817 + ads->ds_ctl6 = ctl6;
10818 +}
10819 +
10820 +static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
10821 +{
10822 + struct ar5416_desc *ads = AR5416DESC(ds);
10823 +
10824 + ads->ds_ctl1 |= AR_IsAggr;
10825 + ads->ds_ctl1 &= ~AR_MoreAggr;
10826 + ads->ds_ctl6 &= ~AR_PadDelim;
10827 +}
10828 +
10829 +static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
10830 +{
10831 + struct ar5416_desc *ads = AR5416DESC(ds);
10832 +
10833 + ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
10834 +}
10835 +
10836 +static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
10837 + u32 burstDuration)
10838 +{
10839 + struct ar5416_desc *ads = AR5416DESC(ds);
10840 +
10841 + ads->ds_ctl2 &= ~AR_BurstDur;
10842 + ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
10843 +}
10844 +
10845 +static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
10846 + u32 vmf)
10847 +{
10848 + struct ar5416_desc *ads = AR5416DESC(ds);
10849 +
10850 + if (vmf)
10851 + ads->ds_ctl0 |= AR_VirtMoreFrag;
10852 + else
10853 + ads->ds_ctl0 &= ~AR_VirtMoreFrag;
10854 +}
10855 +
10856 +void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
10857 + u32 size, u32 flags)
10858 +{
10859 + struct ar5416_desc *ads = AR5416DESC(ds);
10860 + struct ath9k_hw_capabilities *pCap = &ah->caps;
10861 +
10862 + ads->ds_ctl1 = size & AR_BufLen;
10863 + if (flags & ATH9K_RXDESC_INTREQ)
10864 + ads->ds_ctl1 |= AR_RxIntrReq;
10865 +
10866 + ads->ds_rxstatus8 &= ~AR_RxDone;
10867 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
10868 + memset(&(ads->u), 0, sizeof(ads->u));
10869 +}
10870 +EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
10871 +
10872 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
10873 +{
10874 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
10875 +
10876 + ops->rx_enable = ar9002_hw_rx_enable;
10877 + ops->set_desc_link = ar9002_hw_set_desc_link;
10878 + ops->get_desc_link = ar9002_hw_get_desc_link;
10879 + ops->get_isr = ar9002_hw_get_isr;
10880 + ops->fill_txdesc = ar9002_hw_fill_txdesc;
10881 + ops->proc_txdesc = ar9002_hw_proc_txdesc;
10882 + ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
10883 + ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
10884 + ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
10885 + ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
10886 + ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
10887 + ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
10888 + ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
10889 + ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
10890 +}
10891 --- /dev/null
10892 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
10893 @@ -0,0 +1,534 @@
10894 +/*
10895 + * Copyright (c) 2008-2010 Atheros Communications Inc.
10896 + *
10897 + * Permission to use, copy, modify, and/or distribute this software for any
10898 + * purpose with or without fee is hereby granted, provided that the above
10899 + * copyright notice and this permission notice appear in all copies.
10900 + *
10901 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10902 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10903 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10904 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
10905 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
10906 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
10907 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
10908 + */
10909 +
10910 +/**
10911 + * DOC: Programming Atheros 802.11n analog front end radios
10912 + *
10913 + * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
10914 + * devices have either an external AR2133 analog front end radio for single
10915 + * band 2.4 GHz communication or an AR5133 analog front end radio for dual
10916 + * band 2.4 GHz / 5 GHz communication.
10917 + *
10918 + * All devices after the AR5416 and AR5418 family starting with the AR9280
10919 + * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
10920 + * into a single-chip and require less programming.
10921 + *
10922 + * The following single-chips exist with a respective embedded radio:
10923 + *
10924 + * AR9280 - 11n dual-band 2x2 MIMO for PCIe
10925 + * AR9281 - 11n single-band 1x2 MIMO for PCIe
10926 + * AR9285 - 11n single-band 1x1 for PCIe
10927 + * AR9287 - 11n single-band 2x2 MIMO for PCIe
10928 + *
10929 + * AR9220 - 11n dual-band 2x2 MIMO for PCI
10930 + * AR9223 - 11n single-band 2x2 MIMO for PCI
10931 + *
10932 + * AR9287 - 11n single-band 1x1 MIMO for USB
10933 + */
10934 +
10935 +#include "hw.h"
10936 +#include "ar9002_phy.h"
10937 +
10938 +/**
10939 + * ar9002_hw_set_channel - set channel on single-chip device
10940 + * @ah: atheros hardware structure
10941 + * @chan:
10942 + *
10943 + * This is the function to change channel on single-chip devices, that is
10944 + * all devices after ar9280.
10945 + *
10946 + * This function takes the channel value in MHz and sets
10947 + * hardware channel value. Assumes writes have been enabled to analog bus.
10948 + *
10949 + * Actual Expression,
10950 + *
10951 + * For 2GHz channel,
10952 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
10953 + * (freq_ref = 40MHz)
10954 + *
10955 + * For 5GHz channel,
10956 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
10957 + * (freq_ref = 40MHz/(24>>amodeRefSel))
10958 + */
10959 +static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
10960 +{
10961 + u16 bMode, fracMode, aModeRefSel = 0;
10962 + u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
10963 + struct chan_centers centers;
10964 + u32 refDivA = 24;
10965 +
10966 + ath9k_hw_get_channel_centers(ah, chan, &centers);
10967 + freq = centers.synth_center;
10968 +
10969 + reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
10970 + reg32 &= 0xc0000000;
10971 +
10972 + if (freq < 4800) { /* 2 GHz, fractional mode */
10973 + u32 txctl;
10974 + int regWrites = 0;
10975 +
10976 + bMode = 1;
10977 + fracMode = 1;
10978 + aModeRefSel = 0;
10979 + channelSel = CHANSEL_2G(freq);
10980 +
10981 + if (AR_SREV_9287_11_OR_LATER(ah)) {
10982 + if (freq == 2484) {
10983 + /* Enable channel spreading for channel 14 */
10984 + REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
10985 + 1, regWrites);
10986 + } else {
10987 + REG_WRITE_ARRAY(&ah->iniCckfirNormal,
10988 + 1, regWrites);
10989 + }
10990 + } else {
10991 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
10992 + if (freq == 2484) {
10993 + /* Enable channel spreading for channel 14 */
10994 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
10995 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
10996 + } else {
10997 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
10998 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
10999 + }
11000 + }
11001 + } else {
11002 + bMode = 0;
11003 + fracMode = 0;
11004 +
11005 + switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
11006 + case 0:
11007 + if ((freq % 20) == 0)
11008 + aModeRefSel = 3;
11009 + else if ((freq % 10) == 0)
11010 + aModeRefSel = 2;
11011 + if (aModeRefSel)
11012 + break;
11013 + case 1:
11014 + default:
11015 + aModeRefSel = 0;
11016 + /*
11017 + * Enable 2G (fractional) mode for channels
11018 + * which are 5MHz spaced.
11019 + */
11020 + fracMode = 1;
11021 + refDivA = 1;
11022 + channelSel = CHANSEL_5G(freq);
11023 +
11024 + /* RefDivA setting */
11025 + REG_RMW_FIELD(ah, AR_AN_SYNTH9,
11026 + AR_AN_SYNTH9_REFDIVA, refDivA);
11027 +
11028 + }
11029 +
11030 + if (!fracMode) {
11031 + ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
11032 + channelSel = ndiv & 0x1ff;
11033 + channelFrac = (ndiv & 0xfffffe00) * 2;
11034 + channelSel = (channelSel << 17) | channelFrac;
11035 + }
11036 + }
11037 +
11038 + reg32 = reg32 |
11039 + (bMode << 29) |
11040 + (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
11041 +
11042 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
11043 +
11044 + ah->curchan = chan;
11045 + ah->curchan_rad_index = -1;
11046 +
11047 + return 0;
11048 +}
11049 +
11050 +/**
11051 + * ar9002_hw_spur_mitigate - convert baseband spur frequency
11052 + * @ah: atheros hardware structure
11053 + * @chan:
11054 + *
11055 + * For single-chip solutions. Converts to baseband spur frequency given the
11056 + * input channel frequency and compute register settings below.
11057 + */
11058 +static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
11059 + struct ath9k_channel *chan)
11060 +{
11061 + int bb_spur = AR_NO_SPUR;
11062 + int freq;
11063 + int bin, cur_bin;
11064 + int bb_spur_off, spur_subchannel_sd;
11065 + int spur_freq_sd;
11066 + int spur_delta_phase;
11067 + int denominator;
11068 + int upper, lower, cur_vit_mask;
11069 + int tmp, newVal;
11070 + int i;
11071 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
11072 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
11073 + };
11074 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
11075 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
11076 + };
11077 + int inc[4] = { 0, 100, 0, 0 };
11078 + struct chan_centers centers;
11079 +
11080 + int8_t mask_m[123];
11081 + int8_t mask_p[123];
11082 + int8_t mask_amt;
11083 + int tmp_mask;
11084 + int cur_bb_spur;
11085 + bool is2GHz = IS_CHAN_2GHZ(chan);
11086 +
11087 + memset(&mask_m, 0, sizeof(int8_t) * 123);
11088 + memset(&mask_p, 0, sizeof(int8_t) * 123);
11089 +
11090 + ath9k_hw_get_channel_centers(ah, chan, &centers);
11091 + freq = centers.synth_center;
11092 +
11093 + ah->config.spurmode = SPUR_ENABLE_EEPROM;
11094 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
11095 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
11096 +
11097 + if (is2GHz)
11098 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
11099 + else
11100 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
11101 +
11102 + if (AR_NO_SPUR == cur_bb_spur)
11103 + break;
11104 + cur_bb_spur = cur_bb_spur - freq;
11105 +
11106 + if (IS_CHAN_HT40(chan)) {
11107 + if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
11108 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
11109 + bb_spur = cur_bb_spur;
11110 + break;
11111 + }
11112 + } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
11113 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
11114 + bb_spur = cur_bb_spur;
11115 + break;
11116 + }
11117 + }
11118 +
11119 + if (AR_NO_SPUR == bb_spur) {
11120 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
11121 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
11122 + return;
11123 + } else {
11124 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
11125 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
11126 + }
11127 +
11128 + bin = bb_spur * 320;
11129 +
11130 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
11131 +
11132 + newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
11133 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
11134 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
11135 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
11136 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
11137 +
11138 + newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
11139 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
11140 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
11141 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
11142 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
11143 + REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
11144 +
11145 + if (IS_CHAN_HT40(chan)) {
11146 + if (bb_spur < 0) {
11147 + spur_subchannel_sd = 1;
11148 + bb_spur_off = bb_spur + 10;
11149 + } else {
11150 + spur_subchannel_sd = 0;
11151 + bb_spur_off = bb_spur - 10;
11152 + }
11153 + } else {
11154 + spur_subchannel_sd = 0;
11155 + bb_spur_off = bb_spur;
11156 + }
11157 +
11158 + if (IS_CHAN_HT40(chan))
11159 + spur_delta_phase =
11160 + ((bb_spur * 262144) /
11161 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
11162 + else
11163 + spur_delta_phase =
11164 + ((bb_spur * 524288) /
11165 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
11166 +
11167 + denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
11168 + spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
11169 +
11170 + newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
11171 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
11172 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
11173 + REG_WRITE(ah, AR_PHY_TIMING11, newVal);
11174 +
11175 + newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
11176 + REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
11177 +
11178 + cur_bin = -6000;
11179 + upper = bin + 100;
11180 + lower = bin - 100;
11181 +
11182 + for (i = 0; i < 4; i++) {
11183 + int pilot_mask = 0;
11184 + int chan_mask = 0;
11185 + int bp = 0;
11186 + for (bp = 0; bp < 30; bp++) {
11187 + if ((cur_bin > lower) && (cur_bin < upper)) {
11188 + pilot_mask = pilot_mask | 0x1 << bp;
11189 + chan_mask = chan_mask | 0x1 << bp;
11190 + }
11191 + cur_bin += 100;
11192 + }
11193 + cur_bin += inc[i];
11194 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
11195 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
11196 + }
11197 +
11198 + cur_vit_mask = 6100;
11199 + upper = bin + 120;
11200 + lower = bin - 120;
11201 +
11202 + for (i = 0; i < 123; i++) {
11203 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
11204 +
11205 + /* workaround for gcc bug #37014 */
11206 + volatile int tmp_v = abs(cur_vit_mask - bin);
11207 +
11208 + if (tmp_v < 75)
11209 + mask_amt = 1;
11210 + else
11211 + mask_amt = 0;
11212 + if (cur_vit_mask < 0)
11213 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
11214 + else
11215 + mask_p[cur_vit_mask / 100] = mask_amt;
11216 + }
11217 + cur_vit_mask -= 100;
11218 + }
11219 +
11220 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
11221 + | (mask_m[48] << 26) | (mask_m[49] << 24)
11222 + | (mask_m[50] << 22) | (mask_m[51] << 20)
11223 + | (mask_m[52] << 18) | (mask_m[53] << 16)
11224 + | (mask_m[54] << 14) | (mask_m[55] << 12)
11225 + | (mask_m[56] << 10) | (mask_m[57] << 8)
11226 + | (mask_m[58] << 6) | (mask_m[59] << 4)
11227 + | (mask_m[60] << 2) | (mask_m[61] << 0);
11228 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
11229 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
11230 +
11231 + tmp_mask = (mask_m[31] << 28)
11232 + | (mask_m[32] << 26) | (mask_m[33] << 24)
11233 + | (mask_m[34] << 22) | (mask_m[35] << 20)
11234 + | (mask_m[36] << 18) | (mask_m[37] << 16)
11235 + | (mask_m[48] << 14) | (mask_m[39] << 12)
11236 + | (mask_m[40] << 10) | (mask_m[41] << 8)
11237 + | (mask_m[42] << 6) | (mask_m[43] << 4)
11238 + | (mask_m[44] << 2) | (mask_m[45] << 0);
11239 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
11240 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
11241 +
11242 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
11243 + | (mask_m[18] << 26) | (mask_m[18] << 24)
11244 + | (mask_m[20] << 22) | (mask_m[20] << 20)
11245 + | (mask_m[22] << 18) | (mask_m[22] << 16)
11246 + | (mask_m[24] << 14) | (mask_m[24] << 12)
11247 + | (mask_m[25] << 10) | (mask_m[26] << 8)
11248 + | (mask_m[27] << 6) | (mask_m[28] << 4)
11249 + | (mask_m[29] << 2) | (mask_m[30] << 0);
11250 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
11251 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
11252 +
11253 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
11254 + | (mask_m[2] << 26) | (mask_m[3] << 24)
11255 + | (mask_m[4] << 22) | (mask_m[5] << 20)
11256 + | (mask_m[6] << 18) | (mask_m[7] << 16)
11257 + | (mask_m[8] << 14) | (mask_m[9] << 12)
11258 + | (mask_m[10] << 10) | (mask_m[11] << 8)
11259 + | (mask_m[12] << 6) | (mask_m[13] << 4)
11260 + | (mask_m[14] << 2) | (mask_m[15] << 0);
11261 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
11262 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
11263 +
11264 + tmp_mask = (mask_p[15] << 28)
11265 + | (mask_p[14] << 26) | (mask_p[13] << 24)
11266 + | (mask_p[12] << 22) | (mask_p[11] << 20)
11267 + | (mask_p[10] << 18) | (mask_p[9] << 16)
11268 + | (mask_p[8] << 14) | (mask_p[7] << 12)
11269 + | (mask_p[6] << 10) | (mask_p[5] << 8)
11270 + | (mask_p[4] << 6) | (mask_p[3] << 4)
11271 + | (mask_p[2] << 2) | (mask_p[1] << 0);
11272 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
11273 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
11274 +
11275 + tmp_mask = (mask_p[30] << 28)
11276 + | (mask_p[29] << 26) | (mask_p[28] << 24)
11277 + | (mask_p[27] << 22) | (mask_p[26] << 20)
11278 + | (mask_p[25] << 18) | (mask_p[24] << 16)
11279 + | (mask_p[23] << 14) | (mask_p[22] << 12)
11280 + | (mask_p[21] << 10) | (mask_p[20] << 8)
11281 + | (mask_p[19] << 6) | (mask_p[18] << 4)
11282 + | (mask_p[17] << 2) | (mask_p[16] << 0);
11283 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
11284 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
11285 +
11286 + tmp_mask = (mask_p[45] << 28)
11287 + | (mask_p[44] << 26) | (mask_p[43] << 24)
11288 + | (mask_p[42] << 22) | (mask_p[41] << 20)
11289 + | (mask_p[40] << 18) | (mask_p[39] << 16)
11290 + | (mask_p[38] << 14) | (mask_p[37] << 12)
11291 + | (mask_p[36] << 10) | (mask_p[35] << 8)
11292 + | (mask_p[34] << 6) | (mask_p[33] << 4)
11293 + | (mask_p[32] << 2) | (mask_p[31] << 0);
11294 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
11295 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
11296 +
11297 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
11298 + | (mask_p[59] << 26) | (mask_p[58] << 24)
11299 + | (mask_p[57] << 22) | (mask_p[56] << 20)
11300 + | (mask_p[55] << 18) | (mask_p[54] << 16)
11301 + | (mask_p[53] << 14) | (mask_p[52] << 12)
11302 + | (mask_p[51] << 10) | (mask_p[50] << 8)
11303 + | (mask_p[49] << 6) | (mask_p[48] << 4)
11304 + | (mask_p[47] << 2) | (mask_p[46] << 0);
11305 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
11306 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
11307 +}
11308 +
11309 +static void ar9002_olc_init(struct ath_hw *ah)
11310 +{
11311 + u32 i;
11312 +
11313 + if (!OLC_FOR_AR9280_20_LATER)
11314 + return;
11315 +
11316 + if (OLC_FOR_AR9287_10_LATER) {
11317 + REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
11318 + AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
11319 + ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
11320 + AR9287_AN_TXPC0_TXPCMODE,
11321 + AR9287_AN_TXPC0_TXPCMODE_S,
11322 + AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
11323 + udelay(100);
11324 + } else {
11325 + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
11326 + ah->originalGain[i] =
11327 + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
11328 + AR_PHY_TX_GAIN);
11329 + ah->PDADCdelta = 0;
11330 + }
11331 +}
11332 +
11333 +static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
11334 + struct ath9k_channel *chan)
11335 +{
11336 + u32 pll;
11337 +
11338 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
11339 +
11340 + if (chan && IS_CHAN_HALF_RATE(chan))
11341 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
11342 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
11343 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
11344 +
11345 + if (chan && IS_CHAN_5GHZ(chan)) {
11346 + pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
11347 +
11348 +
11349 + if (AR_SREV_9280_20(ah)) {
11350 + if (((chan->channel % 20) == 0)
11351 + || ((chan->channel % 10) == 0))
11352 + pll = 0x2850;
11353 + else
11354 + pll = 0x142c;
11355 + }
11356 + } else {
11357 + pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
11358 + }
11359 +
11360 + return pll;
11361 +}
11362 +
11363 +static void ar9002_hw_do_getnf(struct ath_hw *ah,
11364 + int16_t nfarray[NUM_NF_READINGS])
11365 +{
11366 + struct ath_common *common = ath9k_hw_common(ah);
11367 + int16_t nf;
11368 +
11369 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
11370 +
11371 + if (nf & 0x100)
11372 + nf = 0 - ((nf ^ 0x1ff) + 1);
11373 + ath_print(common, ATH_DBG_CALIBRATE,
11374 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
11375 +
11376 + if (AR_SREV_9271(ah) && (nf >= -114))
11377 + nf = -116;
11378 +
11379 + nfarray[0] = nf;
11380 +
11381 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
11382 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
11383 + AR9280_PHY_CH1_MINCCA_PWR);
11384 +
11385 + if (nf & 0x100)
11386 + nf = 0 - ((nf ^ 0x1ff) + 1);
11387 + ath_print(common, ATH_DBG_CALIBRATE,
11388 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
11389 + nfarray[1] = nf;
11390 + }
11391 +
11392 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
11393 + if (nf & 0x100)
11394 + nf = 0 - ((nf ^ 0x1ff) + 1);
11395 + ath_print(common, ATH_DBG_CALIBRATE,
11396 + "NF calibrated [ext] [chain 0] is %d\n", nf);
11397 +
11398 + if (AR_SREV_9271(ah) && (nf >= -114))
11399 + nf = -116;
11400 +
11401 + nfarray[3] = nf;
11402 +
11403 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
11404 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
11405 + AR9280_PHY_CH1_EXT_MINCCA_PWR);
11406 +
11407 + if (nf & 0x100)
11408 + nf = 0 - ((nf ^ 0x1ff) + 1);
11409 + ath_print(common, ATH_DBG_CALIBRATE,
11410 + "NF calibrated [ext] [chain 1] is %d\n", nf);
11411 + nfarray[4] = nf;
11412 + }
11413 +}
11414 +
11415 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
11416 +{
11417 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
11418 +
11419 + priv_ops->set_rf_regs = NULL;
11420 + priv_ops->rf_alloc_ext_banks = NULL;
11421 + priv_ops->rf_free_ext_banks = NULL;
11422 + priv_ops->rf_set_freq = ar9002_hw_set_channel;
11423 + priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
11424 + priv_ops->olc_init = ar9002_olc_init;
11425 + priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
11426 + priv_ops->do_getnf = ar9002_hw_do_getnf;
11427 +}
11428 --- /dev/null
11429 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
11430 @@ -0,0 +1,572 @@
11431 +/*
11432 + * Copyright (c) 2008-2010 Atheros Communications Inc.
11433 + *
11434 + * Permission to use, copy, modify, and/or distribute this software for any
11435 + * purpose with or without fee is hereby granted, provided that the above
11436 + * copyright notice and this permission notice appear in all copies.
11437 + *
11438 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11439 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11440 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11441 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11442 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
11443 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
11444 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
11445 + */
11446 +#ifndef AR9002_PHY_H
11447 +#define AR9002_PHY_H
11448 +
11449 +#define AR_PHY_TEST 0x9800
11450 +#define PHY_AGC_CLR 0x10000000
11451 +#define RFSILENT_BB 0x00002000
11452 +
11453 +#define AR_PHY_TURBO 0x9804
11454 +#define AR_PHY_FC_TURBO_MODE 0x00000001
11455 +#define AR_PHY_FC_TURBO_SHORT 0x00000002
11456 +#define AR_PHY_FC_DYN2040_EN 0x00000004
11457 +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
11458 +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
11459 +/* For 25 MHz channel spacing -- not used but supported by hw */
11460 +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
11461 +#define AR_PHY_FC_HT_EN 0x00000040
11462 +#define AR_PHY_FC_SHORT_GI_40 0x00000080
11463 +#define AR_PHY_FC_WALSH 0x00000100
11464 +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
11465 +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
11466 +
11467 +#define AR_PHY_TEST2 0x9808
11468 +
11469 +#define AR_PHY_TIMING2 0x9810
11470 +#define AR_PHY_TIMING3 0x9814
11471 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
11472 +#define AR_PHY_TIMING3_DSC_MAN_S 17
11473 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
11474 +#define AR_PHY_TIMING3_DSC_EXP_S 13
11475 +
11476 +#define AR_PHY_CHIP_ID_REV_0 0x80
11477 +#define AR_PHY_CHIP_ID_REV_1 0x81
11478 +#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
11479 +
11480 +#define AR_PHY_ACTIVE 0x981C
11481 +#define AR_PHY_ACTIVE_EN 0x00000001
11482 +#define AR_PHY_ACTIVE_DIS 0x00000000
11483 +
11484 +#define AR_PHY_RF_CTL2 0x9824
11485 +#define AR_PHY_TX_END_DATA_START 0x000000FF
11486 +#define AR_PHY_TX_END_DATA_START_S 0
11487 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
11488 +#define AR_PHY_TX_END_PA_ON_S 8
11489 +
11490 +#define AR_PHY_RF_CTL3 0x9828
11491 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
11492 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
11493 +
11494 +#define AR_PHY_ADC_CTL 0x982C
11495 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
11496 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
11497 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
11498 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
11499 +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
11500 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
11501 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
11502 +
11503 +#define AR_PHY_ADC_SERIAL_CTL 0x9830
11504 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
11505 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
11506 +
11507 +#define AR_PHY_RF_CTL4 0x9834
11508 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
11509 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
11510 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
11511 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
11512 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
11513 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
11514 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
11515 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
11516 +
11517 +#define AR_PHY_TSTDAC_CONST 0x983c
11518 +
11519 +#define AR_PHY_SETTLING 0x9844
11520 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
11521 +#define AR_PHY_SETTLING_SWITCH_S 7
11522 +
11523 +#define AR_PHY_RXGAIN 0x9848
11524 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
11525 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
11526 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
11527 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
11528 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
11529 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
11530 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
11531 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
11532 +
11533 +#define AR_PHY_DESIRED_SZ 0x9850
11534 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
11535 +#define AR_PHY_DESIRED_SZ_ADC_S 0
11536 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
11537 +#define AR_PHY_DESIRED_SZ_PGA_S 8
11538 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
11539 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
11540 +
11541 +#define AR_PHY_FIND_SIG 0x9858
11542 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
11543 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
11544 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
11545 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
11546 +
11547 +#define AR_PHY_AGC_CTL1 0x985C
11548 +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
11549 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
11550 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
11551 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
11552 +
11553 +#define AR_PHY_CCA 0x9864
11554 +#define AR_PHY_MINCCA_PWR 0x0FF80000
11555 +#define AR_PHY_MINCCA_PWR_S 19
11556 +#define AR_PHY_CCA_THRESH62 0x0007F000
11557 +#define AR_PHY_CCA_THRESH62_S 12
11558 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
11559 +#define AR9280_PHY_MINCCA_PWR_S 20
11560 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
11561 +#define AR9280_PHY_CCA_THRESH62_S 12
11562 +
11563 +#define AR_PHY_SFCORR_LOW 0x986C
11564 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
11565 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
11566 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
11567 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
11568 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
11569 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
11570 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
11571 +
11572 +#define AR_PHY_SFCORR 0x9868
11573 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
11574 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
11575 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
11576 +#define AR_PHY_SFCORR_M1_THRESH_S 17
11577 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
11578 +#define AR_PHY_SFCORR_M2_THRESH_S 24
11579 +
11580 +#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
11581 +#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
11582 +#define AR_PHY_SYNTH_CONTROL 0x9874
11583 +#define AR_PHY_SLEEP_SCAL 0x9878
11584 +
11585 +#define AR_PHY_PLL_CTL 0x987c
11586 +#define AR_PHY_PLL_CTL_40 0xaa
11587 +#define AR_PHY_PLL_CTL_40_5413 0x04
11588 +#define AR_PHY_PLL_CTL_44 0xab
11589 +#define AR_PHY_PLL_CTL_44_2133 0xeb
11590 +#define AR_PHY_PLL_CTL_40_2133 0xea
11591 +
11592 +#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
11593 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
11594 +#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
11595 +#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
11596 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
11597 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
11598 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
11599 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
11600 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
11601 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
11602 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
11603 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
11604 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
11605 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
11606 +
11607 +#define AR_PHY_RX_DELAY 0x9914
11608 +#define AR_PHY_SEARCH_START_DELAY 0x9918
11609 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
11610 +
11611 +#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
11612 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
11613 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
11614 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
11615 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
11616 +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
11617 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
11618 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
11619 +#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
11620 +
11621 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
11622 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
11623 +#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
11624 +#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
11625 +
11626 +#define AR_PHY_TIMING5 0x9924
11627 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
11628 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
11629 +
11630 +#define AR_PHY_POWER_TX_RATE1 0x9934
11631 +#define AR_PHY_POWER_TX_RATE2 0x9938
11632 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
11633 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
11634 +
11635 +#define AR_PHY_FRAME_CTL 0x9944
11636 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
11637 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
11638 +
11639 +#define AR_PHY_TXPWRADJ 0x994C
11640 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
11641 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
11642 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
11643 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
11644 +
11645 +#define AR_PHY_RADAR_EXT 0x9940
11646 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
11647 +
11648 +#define AR_PHY_RADAR_0 0x9954
11649 +#define AR_PHY_RADAR_0_ENA 0x00000001
11650 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
11651 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
11652 +#define AR_PHY_RADAR_0_INBAND_S 1
11653 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
11654 +#define AR_PHY_RADAR_0_PRSSI_S 6
11655 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
11656 +#define AR_PHY_RADAR_0_HEIGHT_S 12
11657 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
11658 +#define AR_PHY_RADAR_0_RRSSI_S 18
11659 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
11660 +#define AR_PHY_RADAR_0_FIRPWR_S 24
11661 +
11662 +#define AR_PHY_RADAR_1 0x9958
11663 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
11664 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
11665 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
11666 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
11667 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
11668 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
11669 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
11670 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
11671 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
11672 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
11673 +#define AR_PHY_RADAR_1_MAXLEN_S 0
11674 +
11675 +#define AR_PHY_SWITCH_CHAIN_0 0x9960
11676 +#define AR_PHY_SWITCH_COM 0x9964
11677 +
11678 +#define AR_PHY_SIGMA_DELTA 0x996C
11679 +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
11680 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
11681 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
11682 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3
11683 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
11684 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8
11685 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
11686 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
11687 +
11688 +#define AR_PHY_RESTART 0x9970
11689 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
11690 +#define AR_PHY_RESTART_DIV_GC_S 18
11691 +
11692 +#define AR_PHY_RFBUS_REQ 0x997C
11693 +#define AR_PHY_RFBUS_REQ_EN 0x00000001
11694 +
11695 +#define AR_PHY_TIMING7 0x9980
11696 +#define AR_PHY_TIMING8 0x9984
11697 +#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
11698 +#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
11699 +
11700 +#define AR_PHY_BIN_MASK2_1 0x9988
11701 +#define AR_PHY_BIN_MASK2_2 0x998c
11702 +#define AR_PHY_BIN_MASK2_3 0x9990
11703 +#define AR_PHY_BIN_MASK2_4 0x9994
11704 +
11705 +#define AR_PHY_BIN_MASK_1 0x9900
11706 +#define AR_PHY_BIN_MASK_2 0x9904
11707 +#define AR_PHY_BIN_MASK_3 0x9908
11708 +
11709 +#define AR_PHY_MASK_CTL 0x990c
11710 +
11711 +#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
11712 +#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
11713 +
11714 +#define AR_PHY_TIMING9 0x9998
11715 +#define AR_PHY_TIMING10 0x999c
11716 +#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
11717 +#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
11718 +
11719 +#define AR_PHY_TIMING11 0x99a0
11720 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
11721 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
11722 +#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
11723 +#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
11724 +
11725 +#define AR_PHY_RX_CHAINMASK 0x99a4
11726 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
11727 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
11728 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
11729 +
11730 +#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
11731 +#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
11732 +#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
11733 +#define AR_PHY_9285_ANT_DIV_CTL_S 24
11734 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
11735 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
11736 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
11737 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
11738 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
11739 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
11740 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
11741 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
11742 +#define AR_PHY_9285_ANT_DIV_LNA1 2
11743 +#define AR_PHY_9285_ANT_DIV_LNA2 1
11744 +#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
11745 +#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
11746 +#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
11747 +#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
11748 +
11749 +#define AR_PHY_EXT_CCA0 0x99b8
11750 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
11751 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
11752 +
11753 +#define AR_PHY_EXT_CCA 0x99bc
11754 +#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
11755 +#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
11756 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
11757 +#define AR_PHY_EXT_CCA_THRESH62_S 16
11758 +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
11759 +#define AR_PHY_EXT_MINCCA_PWR_S 23
11760 +#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
11761 +#define AR9280_PHY_EXT_MINCCA_PWR_S 16
11762 +
11763 +#define AR_PHY_SFCORR_EXT 0x99c0
11764 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
11765 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
11766 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
11767 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
11768 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
11769 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
11770 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
11771 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
11772 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
11773 +
11774 +#define AR_PHY_HALFGI 0x99D0
11775 +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
11776 +#define AR_PHY_HALFGI_DSC_MAN_S 4
11777 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
11778 +#define AR_PHY_HALFGI_DSC_EXP_S 0
11779 +
11780 +#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
11781 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
11782 +
11783 +#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
11784 +
11785 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
11786 +#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
11787 +
11788 +#define AR_PHY_M_SLEEP 0x99f0
11789 +#define AR_PHY_REFCLKDLY 0x99f4
11790 +#define AR_PHY_REFCLKPD 0x99f8
11791 +
11792 +#define AR_PHY_CALMODE 0x99f0
11793 +
11794 +#define AR_PHY_CALMODE_IQ 0x00000000
11795 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
11796 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
11797 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
11798 +
11799 +#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
11800 +#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
11801 +#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
11802 +#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
11803 +
11804 +#define AR_PHY_CURRENT_RSSI 0x9c1c
11805 +#define AR9280_PHY_CURRENT_RSSI 0x9c3c
11806 +
11807 +#define AR_PHY_RFBUS_GRANT 0x9C20
11808 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001
11809 +
11810 +#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
11811 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
11812 +
11813 +#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
11814 +
11815 +#define AR_PHY_MODE 0xA200
11816 +#define AR_PHY_MODE_ASYNCFIFO 0x80
11817 +#define AR_PHY_MODE_AR2133 0x08
11818 +#define AR_PHY_MODE_AR5111 0x00
11819 +#define AR_PHY_MODE_AR5112 0x08
11820 +#define AR_PHY_MODE_DYNAMIC 0x04
11821 +#define AR_PHY_MODE_RF2GHZ 0x02
11822 +#define AR_PHY_MODE_RF5GHZ 0x00
11823 +#define AR_PHY_MODE_CCK 0x01
11824 +#define AR_PHY_MODE_OFDM 0x00
11825 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
11826 +
11827 +#define AR_PHY_CCK_TX_CTRL 0xA204
11828 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
11829 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
11830 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
11831 +
11832 +#define AR_PHY_CCK_DETECT 0xA208
11833 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
11834 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
11835 +/* [12:6] settling time for antenna switch */
11836 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
11837 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
11838 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
11839 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
11840 +
11841 +#define AR_PHY_GAIN_2GHZ 0xA20C
11842 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
11843 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
11844 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
11845 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
11846 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
11847 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
11848 +
11849 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
11850 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
11851 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
11852 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
11853 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
11854 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
11855 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
11856 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
11857 +
11858 +#define AR_PHY_CCK_RXCTRL4 0xA21C
11859 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
11860 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
11861 +
11862 +#define AR_PHY_DAG_CTRLCCK 0xA228
11863 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
11864 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
11865 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
11866 +
11867 +#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
11868 +#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
11869 +
11870 +#define AR_PHY_POWER_TX_RATE3 0xA234
11871 +#define AR_PHY_POWER_TX_RATE4 0xA238
11872 +
11873 +#define AR_PHY_SCRM_SEQ_XR 0xA23C
11874 +#define AR_PHY_HEADER_DETECT_XR 0xA240
11875 +#define AR_PHY_CHIRP_DETECTED_XR 0xA244
11876 +#define AR_PHY_BLUETOOTH 0xA254
11877 +
11878 +#define AR_PHY_TPCRG1 0xA258
11879 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
11880 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
11881 +
11882 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
11883 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
11884 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
11885 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
11886 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
11887 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
11888 +
11889 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
11890 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
11891 +
11892 +#define AR_PHY_TX_PWRCTRL4 0xa264
11893 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
11894 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
11895 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
11896 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
11897 +
11898 +#define AR_PHY_TX_PWRCTRL6_0 0xa270
11899 +#define AR_PHY_TX_PWRCTRL6_1 0xb270
11900 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
11901 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
11902 +
11903 +#define AR_PHY_TX_PWRCTRL7 0xa274
11904 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
11905 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
11906 +
11907 +#define AR_PHY_TX_PWRCTRL9 0xa27C
11908 +#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
11909 +#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
11910 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
11911 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
11912 +
11913 +#define AR_PHY_TX_GAIN_TBL1 0xa300
11914 +#define AR_PHY_TX_GAIN 0x0007F000
11915 +#define AR_PHY_TX_GAIN_S 12
11916 +
11917 +#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
11918 +#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
11919 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
11920 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
11921 +
11922 +#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
11923 +#define AR_PHY_MASK2_M_31_45 0xa3a4
11924 +#define AR_PHY_MASK2_M_16_30 0xa3a8
11925 +#define AR_PHY_MASK2_M_00_15 0xa3ac
11926 +#define AR_PHY_MASK2_P_15_01 0xa3b8
11927 +#define AR_PHY_MASK2_P_30_16 0xa3bc
11928 +#define AR_PHY_MASK2_P_45_31 0xa3c0
11929 +#define AR_PHY_MASK2_P_61_45 0xa3c4
11930 +#define AR_PHY_SPUR_REG 0x994c
11931 +
11932 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
11933 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
11934 +
11935 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
11936 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
11937 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
11938 +#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
11939 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
11940 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
11941 +
11942 +#define AR_PHY_PILOT_MASK_01_30 0xa3b0
11943 +#define AR_PHY_PILOT_MASK_31_60 0xa3b4
11944 +
11945 +#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
11946 +#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
11947 +
11948 +#define AR_PHY_ANALOG_SWAP 0xa268
11949 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
11950 +
11951 +#define AR_PHY_TPCRG5 0xA26C
11952 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
11953 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
11954 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
11955 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
11956 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
11957 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
11958 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
11959 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
11960 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
11961 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
11962 +
11963 +/* Carrier leak calibration control, do it after AGC calibration */
11964 +#define AR_PHY_CL_CAL_CTL 0xA358
11965 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
11966 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
11967 +
11968 +#define AR_PHY_POWER_TX_RATE5 0xA38C
11969 +#define AR_PHY_POWER_TX_RATE6 0xA390
11970 +
11971 +#define AR_PHY_CAL_CHAINMASK 0xA39C
11972 +
11973 +#define AR_PHY_POWER_TX_SUB 0xA3C8
11974 +#define AR_PHY_POWER_TX_RATE7 0xA3CC
11975 +#define AR_PHY_POWER_TX_RATE8 0xA3D0
11976 +#define AR_PHY_POWER_TX_RATE9 0xA3D4
11977 +
11978 +#define AR_PHY_XPA_CFG 0xA3D8
11979 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
11980 +#define AR_PHY_FORCE_XPA_CFG_S 0
11981 +
11982 +#define AR_PHY_CH1_CCA 0xa864
11983 +#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
11984 +#define AR_PHY_CH1_MINCCA_PWR_S 19
11985 +#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
11986 +#define AR9280_PHY_CH1_MINCCA_PWR_S 20
11987 +
11988 +#define AR_PHY_CH2_CCA 0xb864
11989 +#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
11990 +#define AR_PHY_CH2_MINCCA_PWR_S 19
11991 +
11992 +#define AR_PHY_CH1_EXT_CCA 0xa9bc
11993 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
11994 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
11995 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
11996 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
11997 +
11998 +#define AR_PHY_CH2_EXT_CCA 0xb9bc
11999 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
12000 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
12001 +
12002 +#endif
12003 --- /dev/null
12004 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
12005 @@ -0,0 +1,802 @@
12006 +/*
12007 + * Copyright (c) 2010 Atheros Communications Inc.
12008 + *
12009 + * Permission to use, copy, modify, and/or distribute this software for any
12010 + * purpose with or without fee is hereby granted, provided that the above
12011 + * copyright notice and this permission notice appear in all copies.
12012 + *
12013 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12014 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12015 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12016 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12017 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12018 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
12019 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
12020 + */
12021 +
12022 +#include "hw.h"
12023 +#include "hw-ops.h"
12024 +#include "ar9003_phy.h"
12025 +
12026 +static void ar9003_hw_setup_calibration(struct ath_hw *ah,
12027 + struct ath9k_cal_list *currCal)
12028 +{
12029 + struct ath_common *common = ath9k_hw_common(ah);
12030 +
12031 + /* Select calibration to run */
12032 + switch (currCal->calData->calType) {
12033 + case IQ_MISMATCH_CAL:
12034 + /*
12035 + * Start calibration with
12036 + * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
12037 + */
12038 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
12039 + AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
12040 + currCal->calData->calCountMax);
12041 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
12042 +
12043 + ath_print(common, ATH_DBG_CALIBRATE,
12044 + "starting IQ Mismatch Calibration\n");
12045 +
12046 + /* Kick-off cal */
12047 + REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
12048 + break;
12049 + case TEMP_COMP_CAL:
12050 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
12051 + AR_PHY_65NM_CH0_THERM_LOCAL, 1);
12052 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
12053 + AR_PHY_65NM_CH0_THERM_START, 1);
12054 +
12055 + ath_print(common, ATH_DBG_CALIBRATE,
12056 + "starting Temperature Compensation Calibration\n");
12057 + break;
12058 + case ADC_DC_INIT_CAL:
12059 + case ADC_GAIN_CAL:
12060 + case ADC_DC_CAL:
12061 + /* Not yet */
12062 + break;
12063 + }
12064 +}
12065 +
12066 +/*
12067 + * Generic calibration routine.
12068 + * Recalibrate the lower PHY chips to account for temperature/environment
12069 + * changes.
12070 + */
12071 +static bool ar9003_hw_per_calibration(struct ath_hw *ah,
12072 + struct ath9k_channel *ichan,
12073 + u8 rxchainmask,
12074 + struct ath9k_cal_list *currCal)
12075 +{
12076 + /* Cal is assumed not done until explicitly set below */
12077 + bool iscaldone = false;
12078 +
12079 + /* Calibration in progress. */
12080 + if (currCal->calState == CAL_RUNNING) {
12081 + /* Check to see if it has finished. */
12082 + if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
12083 + /*
12084 + * Accumulate cal measures for active chains
12085 + */
12086 + currCal->calData->calCollect(ah);
12087 + ah->cal_samples++;
12088 +
12089 + if (ah->cal_samples >=
12090 + currCal->calData->calNumSamples) {
12091 + unsigned int i, numChains = 0;
12092 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
12093 + if (rxchainmask & (1 << i))
12094 + numChains++;
12095 + }
12096 +
12097 + /*
12098 + * Process accumulated data
12099 + */
12100 + currCal->calData->calPostProc(ah, numChains);
12101 +
12102 + /* Calibration has finished. */
12103 + ichan->CalValid |= currCal->calData->calType;
12104 + currCal->calState = CAL_DONE;
12105 + iscaldone = true;
12106 + } else {
12107 + /*
12108 + * Set-up collection of another sub-sample until we
12109 + * get desired number
12110 + */
12111 + ar9003_hw_setup_calibration(ah, currCal);
12112 + }
12113 + }
12114 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
12115 + /* If current cal is marked invalid in channel, kick it off */
12116 + ath9k_hw_reset_calibration(ah, currCal);
12117 + }
12118 +
12119 + return iscaldone;
12120 +}
12121 +
12122 +static bool ar9003_hw_calibrate(struct ath_hw *ah,
12123 + struct ath9k_channel *chan,
12124 + u8 rxchainmask,
12125 + bool longcal)
12126 +{
12127 + bool iscaldone = true;
12128 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
12129 +
12130 + /*
12131 + * For given calibration:
12132 + * 1. Call generic cal routine
12133 + * 2. When this cal is done (isCalDone) if we have more cals waiting
12134 + * (eg after reset), mask this to upper layers by not propagating
12135 + * isCalDone if it is set to TRUE.
12136 + * Instead, change isCalDone to FALSE and setup the waiting cal(s)
12137 + * to be run.
12138 + */
12139 + if (currCal &&
12140 + (currCal->calState == CAL_RUNNING ||
12141 + currCal->calState == CAL_WAITING)) {
12142 + iscaldone = ar9003_hw_per_calibration(ah, chan,
12143 + rxchainmask, currCal);
12144 + if (iscaldone) {
12145 + ah->cal_list_curr = currCal = currCal->calNext;
12146 +
12147 + if (currCal->calState == CAL_WAITING) {
12148 + iscaldone = false;
12149 + ath9k_hw_reset_calibration(ah, currCal);
12150 + }
12151 + }
12152 + }
12153 +
12154 + /* Do NF cal only at longer intervals */
12155 + if (longcal) {
12156 + /*
12157 + * Load the NF from history buffer of the current channel.
12158 + * NF is slow time-variant, so it is OK to use a historical
12159 + * value.
12160 + */
12161 + ath9k_hw_loadnf(ah, ah->curchan);
12162 +
12163 + /* start NF calibration, without updating BB NF register */
12164 + ath9k_hw_start_nfcal(ah);
12165 + }
12166 +
12167 + return iscaldone;
12168 +}
12169 +
12170 +static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
12171 +{
12172 + int i;
12173 +
12174 + /* Accumulate IQ cal measures for active chains */
12175 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
12176 + ah->totalPowerMeasI[i] +=
12177 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
12178 + ah->totalPowerMeasQ[i] +=
12179 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
12180 + ah->totalIqCorrMeas[i] +=
12181 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
12182 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
12183 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
12184 + ah->cal_samples, i, ah->totalPowerMeasI[i],
12185 + ah->totalPowerMeasQ[i],
12186 + ah->totalIqCorrMeas[i]);
12187 + }
12188 +}
12189 +
12190 +static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
12191 +{
12192 + struct ath_common *common = ath9k_hw_common(ah);
12193 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
12194 + u32 qCoffDenom, iCoffDenom;
12195 + int32_t qCoff, iCoff;
12196 + int iqCorrNeg, i;
12197 + const u_int32_t offset_array[3] = {
12198 + AR_PHY_RX_IQCAL_CORR_B0,
12199 + AR_PHY_RX_IQCAL_CORR_B1,
12200 + AR_PHY_RX_IQCAL_CORR_B2,
12201 + };
12202 +
12203 + for (i = 0; i < numChains; i++) {
12204 + powerMeasI = ah->totalPowerMeasI[i];
12205 + powerMeasQ = ah->totalPowerMeasQ[i];
12206 + iqCorrMeas = ah->totalIqCorrMeas[i];
12207 +
12208 + ath_print(common, ATH_DBG_CALIBRATE,
12209 + "Starting IQ Cal and Correction for Chain %d\n",
12210 + i);
12211 +
12212 + ath_print(common, ATH_DBG_CALIBRATE,
12213 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
12214 + i, ah->totalIqCorrMeas[i]);
12215 +
12216 + iqCorrNeg = 0;
12217 +
12218 + if (iqCorrMeas > 0x80000000) {
12219 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
12220 + iqCorrNeg = 1;
12221 + }
12222 +
12223 + ath_print(common, ATH_DBG_CALIBRATE,
12224 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
12225 + ath_print(common, ATH_DBG_CALIBRATE,
12226 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
12227 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
12228 + iqCorrNeg);
12229 +
12230 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
12231 + qCoffDenom = powerMeasQ / 64;
12232 +
12233 + if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
12234 + iCoff = iqCorrMeas / iCoffDenom;
12235 + qCoff = powerMeasI / qCoffDenom - 64;
12236 + ath_print(common, ATH_DBG_CALIBRATE,
12237 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
12238 + ath_print(common, ATH_DBG_CALIBRATE,
12239 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
12240 +
12241 + /* Force bounds on iCoff */
12242 + if (iCoff >= 63)
12243 + iCoff = 63;
12244 + else if (iCoff <= -63)
12245 + iCoff = -63;
12246 +
12247 + /* Negate iCoff if iqCorrNeg == 0 */
12248 + if (iqCorrNeg == 0x0)
12249 + iCoff = -iCoff;
12250 +
12251 + /* Force bounds on qCoff */
12252 + if (qCoff >= 63)
12253 + qCoff = 63;
12254 + else if (qCoff <= -63)
12255 + qCoff = -63;
12256 +
12257 + iCoff = iCoff & 0x7f;
12258 + qCoff = qCoff & 0x7f;
12259 +
12260 + ath_print(common, ATH_DBG_CALIBRATE,
12261 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
12262 + i, iCoff, qCoff);
12263 + ath_print(common, ATH_DBG_CALIBRATE,
12264 + "Register offset (0x%04x) "
12265 + "before update = 0x%x\n",
12266 + offset_array[i],
12267 + REG_READ(ah, offset_array[i]));
12268 +
12269 + REG_RMW_FIELD(ah, offset_array[i],
12270 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
12271 + iCoff);
12272 + REG_RMW_FIELD(ah, offset_array[i],
12273 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
12274 + qCoff);
12275 + ath_print(common, ATH_DBG_CALIBRATE,
12276 + "Register offset (0x%04x) QI COFF "
12277 + "(bitfields 0x%08x) after update = 0x%x\n",
12278 + offset_array[i],
12279 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
12280 + REG_READ(ah, offset_array[i]));
12281 + ath_print(common, ATH_DBG_CALIBRATE,
12282 + "Register offset (0x%04x) QQ COFF "
12283 + "(bitfields 0x%08x) after update = 0x%x\n",
12284 + offset_array[i],
12285 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
12286 + REG_READ(ah, offset_array[i]));
12287 +
12288 + ath_print(common, ATH_DBG_CALIBRATE,
12289 + "IQ Cal and Correction done for Chain %d\n",
12290 + i);
12291 + }
12292 + }
12293 +
12294 + REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
12295 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
12296 + ath_print(common, ATH_DBG_CALIBRATE,
12297 + "IQ Cal and Correction (offset 0x%04x) enabled "
12298 + "(bit position 0x%08x). New Value 0x%08x\n",
12299 + (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
12300 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
12301 + REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
12302 +}
12303 +
12304 +static const struct ath9k_percal_data iq_cal_single_sample = {
12305 + IQ_MISMATCH_CAL,
12306 + MIN_CAL_SAMPLES,
12307 + PER_MAX_LOG_COUNT,
12308 + ar9003_hw_iqcal_collect,
12309 + ar9003_hw_iqcalibrate
12310 +};
12311 +
12312 +static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
12313 +{
12314 + ah->iq_caldata.calData = &iq_cal_single_sample;
12315 + ah->supp_cals = IQ_MISMATCH_CAL;
12316 +}
12317 +
12318 +static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
12319 + enum ath9k_cal_types calType)
12320 +{
12321 + switch (calType & ah->supp_cals) {
12322 + case IQ_MISMATCH_CAL:
12323 + /*
12324 + * XXX: Run IQ Mismatch for non-CCK only
12325 + * Note that CHANNEL_B is never set though.
12326 + */
12327 + return true;
12328 + case ADC_GAIN_CAL:
12329 + case ADC_DC_CAL:
12330 + return false;
12331 + case TEMP_COMP_CAL:
12332 + return true;
12333 + }
12334 +
12335 + return false;
12336 +}
12337 +
12338 +/*
12339 + * solve 4x4 linear equation used in loopback iq cal.
12340 + */
12341 +static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
12342 + s32 sin_2phi_1,
12343 + s32 cos_2phi_1,
12344 + s32 sin_2phi_2,
12345 + s32 cos_2phi_2,
12346 + s32 mag_a0_d0,
12347 + s32 phs_a0_d0,
12348 + s32 mag_a1_d0,
12349 + s32 phs_a1_d0,
12350 + s32 solved_eq[])
12351 +{
12352 + s32 f1 = cos_2phi_1 - cos_2phi_2,
12353 + f3 = sin_2phi_1 - sin_2phi_2,
12354 + f2;
12355 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
12356 + const s32 result_shift = 1 << 15;
12357 + struct ath_common *common = ath9k_hw_common(ah);
12358 +
12359 + f2 = (f1 * f1 + f3 * f3) / result_shift;
12360 +
12361 + if (!f2) {
12362 + ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
12363 + return false;
12364 + }
12365 +
12366 + /* mag mismatch, tx */
12367 + mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
12368 + /* phs mismatch, tx */
12369 + phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
12370 +
12371 + mag_tx = (mag_tx / f2);
12372 + phs_tx = (phs_tx / f2);
12373 +
12374 + /* mag mismatch, rx */
12375 + mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
12376 + result_shift;
12377 + /* phs mismatch, rx */
12378 + phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
12379 + result_shift;
12380 +
12381 + solved_eq[0] = mag_tx;
12382 + solved_eq[1] = phs_tx;
12383 + solved_eq[2] = mag_rx;
12384 + solved_eq[3] = phs_rx;
12385 +
12386 + return true;
12387 +}
12388 +
12389 +static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
12390 +{
12391 + s32 abs_i = abs(in_re),
12392 + abs_q = abs(in_im),
12393 + max_abs, min_abs;
12394 +
12395 + if (abs_i > abs_q) {
12396 + max_abs = abs_i;
12397 + min_abs = abs_q;
12398 + } else {
12399 + max_abs = abs_q;
12400 + min_abs = abs_i;
12401 + }
12402 +
12403 + return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
12404 +}
12405 +
12406 +#define DELPT 32
12407 +
12408 +static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
12409 + s32 chain_idx,
12410 + const s32 iq_res[],
12411 + s32 iqc_coeff[])
12412 +{
12413 + s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
12414 + i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
12415 + i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
12416 + i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
12417 + s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
12418 + phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
12419 + sin_2phi_1, cos_2phi_1,
12420 + sin_2phi_2, cos_2phi_2;
12421 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
12422 + s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
12423 + q_q_coff, q_i_coff;
12424 + const s32 res_scale = 1 << 15;
12425 + const s32 delpt_shift = 1 << 8;
12426 + s32 mag1, mag2;
12427 + struct ath_common *common = ath9k_hw_common(ah);
12428 +
12429 + i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
12430 + i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
12431 + iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
12432 +
12433 + if (i2_m_q2_a0_d0 > 0x800)
12434 + i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
12435 +
12436 + if (i2_p_q2_a0_d0 > 0x800)
12437 + i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
12438 +
12439 + if (iq_corr_a0_d0 > 0x800)
12440 + iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
12441 +
12442 + i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
12443 + i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
12444 + iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
12445 +
12446 + if (i2_m_q2_a0_d1 > 0x800)
12447 + i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
12448 +
12449 + if (i2_p_q2_a0_d1 > 0x800)
12450 + i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
12451 +
12452 + if (iq_corr_a0_d1 > 0x800)
12453 + iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
12454 +
12455 + i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
12456 + i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
12457 + iq_corr_a1_d0 = iq_res[4] & 0xfff;
12458 +
12459 + if (i2_m_q2_a1_d0 > 0x800)
12460 + i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
12461 +
12462 + if (i2_p_q2_a1_d0 > 0x800)
12463 + i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
12464 +
12465 + if (iq_corr_a1_d0 > 0x800)
12466 + iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
12467 +
12468 + i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
12469 + i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
12470 + iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
12471 +
12472 + if (i2_m_q2_a1_d1 > 0x800)
12473 + i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
12474 +
12475 + if (i2_p_q2_a1_d1 > 0x800)
12476 + i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
12477 +
12478 + if (iq_corr_a1_d1 > 0x800)
12479 + iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
12480 +
12481 + if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
12482 + (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
12483 + ath_print(common, ATH_DBG_CALIBRATE,
12484 + "Divide by 0:\na0_d0=%d\n"
12485 + "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
12486 + i2_p_q2_a0_d0, i2_p_q2_a0_d1,
12487 + i2_p_q2_a1_d0, i2_p_q2_a1_d1);
12488 + return false;
12489 + }
12490 +
12491 + mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
12492 + phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
12493 +
12494 + mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
12495 + phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
12496 +
12497 + mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
12498 + phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
12499 +
12500 + mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
12501 + phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
12502 +
12503 + /* w/o analog phase shift */
12504 + sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
12505 + /* w/o analog phase shift */
12506 + cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
12507 + /* w/ analog phase shift */
12508 + sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
12509 + /* w/ analog phase shift */
12510 + cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
12511 +
12512 + /*
12513 + * force sin^2 + cos^2 = 1;
12514 + * find magnitude by approximation
12515 + */
12516 + mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
12517 + mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
12518 +
12519 + if ((mag1 == 0) || (mag2 == 0)) {
12520 + ath_print(common, ATH_DBG_CALIBRATE,
12521 + "Divide by 0: mag1=%d, mag2=%d\n",
12522 + mag1, mag2);
12523 + return false;
12524 + }
12525 +
12526 + /* normalization sin and cos by mag */
12527 + sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
12528 + cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
12529 + sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
12530 + cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
12531 +
12532 + /* calculate IQ mismatch */
12533 + if (!ar9003_hw_solve_iq_cal(ah,
12534 + sin_2phi_1, cos_2phi_1,
12535 + sin_2phi_2, cos_2phi_2,
12536 + mag_a0_d0, phs_a0_d0,
12537 + mag_a1_d0,
12538 + phs_a1_d0, solved_eq)) {
12539 + ath_print(common, ATH_DBG_CALIBRATE,
12540 + "Call to ar9003_hw_solve_iq_cal() failed.\n");
12541 + return false;
12542 + }
12543 +
12544 + mag_tx = solved_eq[0];
12545 + phs_tx = solved_eq[1];
12546 + mag_rx = solved_eq[2];
12547 + phs_rx = solved_eq[3];
12548 +
12549 + ath_print(common, ATH_DBG_CALIBRATE,
12550 + "chain %d: mag mismatch=%d phase mismatch=%d\n",
12551 + chain_idx, mag_tx/res_scale, phs_tx/res_scale);
12552 +
12553 + if (res_scale == mag_tx) {
12554 + ath_print(common, ATH_DBG_CALIBRATE,
12555 + "Divide by 0: mag_tx=%d, res_scale=%d\n",
12556 + mag_tx, res_scale);
12557 + return false;
12558 + }
12559 +
12560 + /* calculate and quantize Tx IQ correction factor */
12561 + mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
12562 + phs_corr_tx = -phs_tx;
12563 +
12564 + q_q_coff = (mag_corr_tx * 128 / res_scale);
12565 + q_i_coff = (phs_corr_tx * 256 / res_scale);
12566 +
12567 + ath_print(common, ATH_DBG_CALIBRATE,
12568 + "tx chain %d: mag corr=%d phase corr=%d\n",
12569 + chain_idx, q_q_coff, q_i_coff);
12570 +
12571 + if (q_i_coff < -63)
12572 + q_i_coff = -63;
12573 + if (q_i_coff > 63)
12574 + q_i_coff = 63;
12575 + if (q_q_coff < -63)
12576 + q_q_coff = -63;
12577 + if (q_q_coff > 63)
12578 + q_q_coff = 63;
12579 +
12580 + iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
12581 +
12582 + ath_print(common, ATH_DBG_CALIBRATE,
12583 + "tx chain %d: iq corr coeff=%x\n",
12584 + chain_idx, iqc_coeff[0]);
12585 +
12586 + if (-mag_rx == res_scale) {
12587 + ath_print(common, ATH_DBG_CALIBRATE,
12588 + "Divide by 0: mag_rx=%d, res_scale=%d\n",
12589 + mag_rx, res_scale);
12590 + return false;
12591 + }
12592 +
12593 + /* calculate and quantize Rx IQ correction factors */
12594 + mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
12595 + phs_corr_rx = -phs_rx;
12596 +
12597 + q_q_coff = (mag_corr_rx * 128 / res_scale);
12598 + q_i_coff = (phs_corr_rx * 256 / res_scale);
12599 +
12600 + ath_print(common, ATH_DBG_CALIBRATE,
12601 + "rx chain %d: mag corr=%d phase corr=%d\n",
12602 + chain_idx, q_q_coff, q_i_coff);
12603 +
12604 + if (q_i_coff < -63)
12605 + q_i_coff = -63;
12606 + if (q_i_coff > 63)
12607 + q_i_coff = 63;
12608 + if (q_q_coff < -63)
12609 + q_q_coff = -63;
12610 + if (q_q_coff > 63)
12611 + q_q_coff = 63;
12612 +
12613 + iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
12614 +
12615 + ath_print(common, ATH_DBG_CALIBRATE,
12616 + "rx chain %d: iq corr coeff=%x\n",
12617 + chain_idx, iqc_coeff[1]);
12618 +
12619 + return true;
12620 +}
12621 +
12622 +static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
12623 +{
12624 + struct ath_common *common = ath9k_hw_common(ah);
12625 + const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
12626 + AR_PHY_TX_IQCAL_STATUS_B0,
12627 + AR_PHY_TX_IQCAL_STATUS_B1,
12628 + AR_PHY_TX_IQCAL_STATUS_B2,
12629 + };
12630 + const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
12631 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
12632 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
12633 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
12634 + };
12635 + const u32 rx_corr[AR9300_MAX_CHAINS] = {
12636 + AR_PHY_RX_IQCAL_CORR_B0,
12637 + AR_PHY_RX_IQCAL_CORR_B1,
12638 + AR_PHY_RX_IQCAL_CORR_B2,
12639 + };
12640 + const u_int32_t chan_info_tab[] = {
12641 + AR_PHY_CHAN_INFO_TAB_0,
12642 + AR_PHY_CHAN_INFO_TAB_1,
12643 + AR_PHY_CHAN_INFO_TAB_2,
12644 + };
12645 + s32 iq_res[6];
12646 + s32 iqc_coeff[2];
12647 + s32 i, j;
12648 + u32 num_chains = 0;
12649 +
12650 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
12651 + if (ah->txchainmask & (1 << i))
12652 + num_chains++;
12653 + }
12654 +
12655 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
12656 + AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
12657 + DELPT);
12658 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
12659 + AR_PHY_TX_IQCAL_START_DO_CAL,
12660 + AR_PHY_TX_IQCAL_START_DO_CAL);
12661 +
12662 + if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
12663 + AR_PHY_TX_IQCAL_START_DO_CAL,
12664 + 0, AH_WAIT_TIMEOUT)) {
12665 + ath_print(common, ATH_DBG_CALIBRATE,
12666 + "Tx IQ Cal not complete.\n");
12667 + goto TX_IQ_CAL_FAILED;
12668 + }
12669 +
12670 + for (i = 0; i < num_chains; i++) {
12671 + ath_print(common, ATH_DBG_CALIBRATE,
12672 + "Doing Tx IQ Cal for chain %d.\n", i);
12673 +
12674 + if (REG_READ(ah, txiqcal_status[i]) &
12675 + AR_PHY_TX_IQCAL_STATUS_FAILED) {
12676 + ath_print(common, ATH_DBG_CALIBRATE,
12677 + "Tx IQ Cal failed for chain %d.\n", i);
12678 + goto TX_IQ_CAL_FAILED;
12679 + }
12680 +
12681 + for (j = 0; j < 3; j++) {
12682 + u_int8_t idx = 2 * j,
12683 + offset = 4 * j;
12684 +
12685 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
12686 + AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
12687 +
12688 + /* 32 bits */
12689 + iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
12690 +
12691 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
12692 + AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
12693 +
12694 + /* 16 bits */
12695 + iq_res[idx+1] = 0xffff & REG_READ(ah,
12696 + chan_info_tab[i] +
12697 + offset);
12698 +
12699 + ath_print(common, ATH_DBG_CALIBRATE,
12700 + "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
12701 + idx, iq_res[idx], idx+1, iq_res[idx+1]);
12702 + }
12703 +
12704 + if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
12705 + ath_print(common, ATH_DBG_CALIBRATE,
12706 + "Failed in calculation of IQ correction.\n");
12707 + goto TX_IQ_CAL_FAILED;
12708 + }
12709 +
12710 + ath_print(common, ATH_DBG_CALIBRATE,
12711 + "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
12712 + iqc_coeff[0], iqc_coeff[1]);
12713 +
12714 + REG_RMW_FIELD(ah, tx_corr_coeff[i],
12715 + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
12716 + iqc_coeff[0]);
12717 + REG_RMW_FIELD(ah, rx_corr[i],
12718 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
12719 + iqc_coeff[1] >> 7);
12720 + REG_RMW_FIELD(ah, rx_corr[i],
12721 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
12722 + iqc_coeff[1]);
12723 + }
12724 +
12725 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
12726 + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
12727 + REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
12728 + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
12729 +
12730 + return;
12731 +
12732 +TX_IQ_CAL_FAILED:
12733 + ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
12734 + return;
12735 +}
12736 +
12737 +static bool ar9003_hw_init_cal(struct ath_hw *ah,
12738 + struct ath9k_channel *chan)
12739 +{
12740 + struct ath_common *common = ath9k_hw_common(ah);
12741 +
12742 + /*
12743 + * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
12744 + * running AGC/TxIQ cals
12745 + */
12746 + ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
12747 +
12748 + /* Calibrate the AGC */
12749 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
12750 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
12751 + AR_PHY_AGC_CONTROL_CAL);
12752 +
12753 + /* Poll for offset calibration complete */
12754 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
12755 + 0, AH_WAIT_TIMEOUT)) {
12756 + ath_print(common, ATH_DBG_CALIBRATE,
12757 + "offset calibration failed to "
12758 + "complete in 1ms; noisy environment?\n");
12759 + return false;
12760 + }
12761 +
12762 + /* Do Tx IQ Calibration */
12763 + ar9003_hw_tx_iq_cal(ah);
12764 +
12765 + /* Revert chainmasks to their original values before NF cal */
12766 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
12767 +
12768 + /* Initialize list pointers */
12769 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
12770 +
12771 + if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
12772 + INIT_CAL(&ah->iq_caldata);
12773 + INSERT_CAL(ah, &ah->iq_caldata);
12774 + ath_print(common, ATH_DBG_CALIBRATE,
12775 + "enabling IQ Calibration.\n");
12776 + }
12777 +
12778 + if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
12779 + INIT_CAL(&ah->tempCompCalData);
12780 + INSERT_CAL(ah, &ah->tempCompCalData);
12781 + ath_print(common, ATH_DBG_CALIBRATE,
12782 + "enabling Temperature Compensation Calibration.\n");
12783 + }
12784 +
12785 + /* Initialize current pointer to first element in list */
12786 + ah->cal_list_curr = ah->cal_list;
12787 +
12788 + if (ah->cal_list_curr)
12789 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
12790 +
12791 + chan->CalValid = 0;
12792 +
12793 + return true;
12794 +}
12795 +
12796 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
12797 +{
12798 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
12799 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
12800 +
12801 + priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
12802 + priv_ops->init_cal = ar9003_hw_init_cal;
12803 + priv_ops->setup_calibration = ar9003_hw_setup_calibration;
12804 + priv_ops->iscal_supported = ar9003_hw_iscal_supported;
12805 +
12806 + ops->calibrate = ar9003_hw_calibrate;
12807 +}
12808 --- /dev/null
12809 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
12810 @@ -0,0 +1,1856 @@
12811 +/*
12812 + * Copyright (c) 2010 Atheros Communications Inc.
12813 + *
12814 + * Permission to use, copy, modify, and/or distribute this software for any
12815 + * purpose with or without fee is hereby granted, provided that the above
12816 + * copyright notice and this permission notice appear in all copies.
12817 + *
12818 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12819 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12820 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12821 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12822 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12823 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
12824 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
12825 + */
12826 +
12827 +#include "hw.h"
12828 +#include "ar9003_phy.h"
12829 +#include "ar9003_eeprom.h"
12830 +
12831 +#define COMP_HDR_LEN 4
12832 +#define COMP_CKSUM_LEN 2
12833 +
12834 +#define AR_CH0_TOP (0x00016288)
12835 +#define AR_CH0_TOP_XPABIASLVL (0x3)
12836 +#define AR_CH0_TOP_XPABIASLVL_S (8)
12837 +
12838 +#define AR_CH0_THERM (0x00016290)
12839 +#define AR_CH0_THERM_SPARE (0x3f)
12840 +#define AR_CH0_THERM_SPARE_S (0)
12841 +
12842 +#define AR_SWITCH_TABLE_COM_ALL (0xffff)
12843 +#define AR_SWITCH_TABLE_COM_ALL_S (0)
12844 +
12845 +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
12846 +#define AR_SWITCH_TABLE_COM2_ALL_S (0)
12847 +
12848 +#define AR_SWITCH_TABLE_ALL (0xfff)
12849 +#define AR_SWITCH_TABLE_ALL_S (0)
12850 +
12851 +static const struct ar9300_eeprom ar9300_default = {
12852 + .eepromVersion = 2,
12853 + .templateVersion = 2,
12854 + .macAddr = {1, 2, 3, 4, 5, 6},
12855 + .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12856 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
12857 + .baseEepHeader = {
12858 + .regDmn = {0, 0x1f},
12859 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
12860 + .opCapFlags = {
12861 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
12862 + .eepMisc = 0,
12863 + },
12864 + .rfSilent = 0,
12865 + .blueToothOptions = 0,
12866 + .deviceCap = 0,
12867 + .deviceType = 5, /* takes lower byte in eeprom location */
12868 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
12869 + .params_for_tuning_caps = {0, 0},
12870 + .featureEnable = 0x0c,
12871 + /*
12872 + * bit0 - enable tx temp comp - disabled
12873 + * bit1 - enable tx volt comp - disabled
12874 + * bit2 - enable fastClock - enabled
12875 + * bit3 - enable doubling - enabled
12876 + * bit4 - enable internal regulator - disabled
12877 + */
12878 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
12879 + .eepromWriteEnableGpio = 3,
12880 + .wlanDisableGpio = 0,
12881 + .wlanLedGpio = 8,
12882 + .rxBandSelectGpio = 0xff,
12883 + .txrxgain = 0,
12884 + .swreg = 0,
12885 + },
12886 + .modalHeader2G = {
12887 + /* ar9300_modal_eep_header 2g */
12888 + /* 4 idle,t1,t2,b(4 bits per setting) */
12889 + .antCtrlCommon = 0x110,
12890 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
12891 + .antCtrlCommon2 = 0x22222,
12892 +
12893 + /*
12894 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
12895 + * rx1, rx12, b (2 bits each)
12896 + */
12897 + .antCtrlChain = {0x150, 0x150, 0x150},
12898 +
12899 + /*
12900 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
12901 + * for ar9280 (0xa20c/b20c 5:0)
12902 + */
12903 + .xatten1DB = {0, 0, 0},
12904 +
12905 + /*
12906 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
12907 + * for ar9280 (0xa20c/b20c 16:12
12908 + */
12909 + .xatten1Margin = {0, 0, 0},
12910 + .tempSlope = 36,
12911 + .voltSlope = 0,
12912 +
12913 + /*
12914 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
12915 + * channels in usual fbin coding format
12916 + */
12917 + .spurChans = {0, 0, 0, 0, 0},
12918 +
12919 + /*
12920 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
12921 + * if the register is per chain
12922 + */
12923 + .noiseFloorThreshCh = {-1, 0, 0},
12924 + .ob = {1, 1, 1},/* 3 chain */
12925 + .db_stage2 = {1, 1, 1}, /* 3 chain */
12926 + .db_stage3 = {0, 0, 0},
12927 + .db_stage4 = {0, 0, 0},
12928 + .xpaBiasLvl = 0,
12929 + .txFrameToDataStart = 0x0e,
12930 + .txFrameToPaOn = 0x0e,
12931 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
12932 + .antennaGain = 0,
12933 + .switchSettling = 0x2c,
12934 + .adcDesiredSize = -30,
12935 + .txEndToXpaOff = 0,
12936 + .txEndToRxOn = 0x2,
12937 + .txFrameToXpaOn = 0xe,
12938 + .thresh62 = 28,
12939 + .futureModal = { /* [32] */
12940 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12941 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
12942 + },
12943 + },
12944 + .calFreqPier2G = {
12945 + FREQ2FBIN(2412, 1),
12946 + FREQ2FBIN(2437, 1),
12947 + FREQ2FBIN(2472, 1),
12948 + },
12949 + /* ar9300_cal_data_per_freq_op_loop 2g */
12950 + .calPierData2G = {
12951 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
12952 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
12953 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
12954 + },
12955 + .calTarget_freqbin_Cck = {
12956 + FREQ2FBIN(2412, 1),
12957 + FREQ2FBIN(2484, 1),
12958 + },
12959 + .calTarget_freqbin_2G = {
12960 + FREQ2FBIN(2412, 1),
12961 + FREQ2FBIN(2437, 1),
12962 + FREQ2FBIN(2472, 1)
12963 + },
12964 + .calTarget_freqbin_2GHT20 = {
12965 + FREQ2FBIN(2412, 1),
12966 + FREQ2FBIN(2437, 1),
12967 + FREQ2FBIN(2472, 1)
12968 + },
12969 + .calTarget_freqbin_2GHT40 = {
12970 + FREQ2FBIN(2412, 1),
12971 + FREQ2FBIN(2437, 1),
12972 + FREQ2FBIN(2472, 1)
12973 + },
12974 + .calTargetPowerCck = {
12975 + /* 1L-5L,5S,11L,11S */
12976 + { {36, 36, 36, 36} },
12977 + { {36, 36, 36, 36} },
12978 + },
12979 + .calTargetPower2G = {
12980 + /* 6-24,36,48,54 */
12981 + { {32, 32, 28, 24} },
12982 + { {32, 32, 28, 24} },
12983 + { {32, 32, 28, 24} },
12984 + },
12985 + .calTargetPower2GHT20 = {
12986 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12987 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12988 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12989 + },
12990 + .calTargetPower2GHT40 = {
12991 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12992 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12993 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
12994 + },
12995 + .ctlIndex_2G = {
12996 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
12997 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
12998 + },
12999 + .ctl_freqbin_2G = {
13000 + {
13001 + FREQ2FBIN(2412, 1),
13002 + FREQ2FBIN(2417, 1),
13003 + FREQ2FBIN(2457, 1),
13004 + FREQ2FBIN(2462, 1)
13005 + },
13006 + {
13007 + FREQ2FBIN(2412, 1),
13008 + FREQ2FBIN(2417, 1),
13009 + FREQ2FBIN(2462, 1),
13010 + 0xFF,
13011 + },
13012 +
13013 + {
13014 + FREQ2FBIN(2412, 1),
13015 + FREQ2FBIN(2417, 1),
13016 + FREQ2FBIN(2462, 1),
13017 + 0xFF,
13018 + },
13019 + {
13020 + FREQ2FBIN(2422, 1),
13021 + FREQ2FBIN(2427, 1),
13022 + FREQ2FBIN(2447, 1),
13023 + FREQ2FBIN(2452, 1)
13024 + },
13025 +
13026 + {
13027 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13028 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13029 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13030 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
13031 + },
13032 +
13033 + {
13034 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13035 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13036 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13037 + 0,
13038 + },
13039 +
13040 + {
13041 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13042 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13043 + FREQ2FBIN(2472, 1),
13044 + 0,
13045 + },
13046 +
13047 + {
13048 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
13049 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
13050 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
13051 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
13052 + },
13053 +
13054 + {
13055 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13056 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13057 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13058 + },
13059 +
13060 + {
13061 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13062 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13063 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13064 + 0
13065 + },
13066 +
13067 + {
13068 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
13069 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
13070 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
13071 + 0
13072 + },
13073 +
13074 + {
13075 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
13076 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
13077 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
13078 + /* Data[11].ctlEdges[3].bChannel */
13079 + FREQ2FBIN(2462, 1),
13080 + }
13081 + },
13082 + .ctlPowerData_2G = {
13083 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13084 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13085 + { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
13086 +
13087 + { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
13088 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13089 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13090 +
13091 + { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
13092 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13093 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13094 +
13095 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
13096 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
13097 + },
13098 + .modalHeader5G = {
13099 + /* 4 idle,t1,t2,b (4 bits per setting) */
13100 + .antCtrlCommon = 0x110,
13101 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
13102 + .antCtrlCommon2 = 0x22222,
13103 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
13104 + .antCtrlChain = {
13105 + 0x000, 0x000, 0x000,
13106 + },
13107 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
13108 + .xatten1DB = {0, 0, 0},
13109 +
13110 + /*
13111 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
13112 + * for merlin (0xa20c/b20c 16:12
13113 + */
13114 + .xatten1Margin = {0, 0, 0},
13115 + .tempSlope = 68,
13116 + .voltSlope = 0,
13117 + /* spurChans spur channels in usual fbin coding format */
13118 + .spurChans = {0, 0, 0, 0, 0},
13119 + /* noiseFloorThreshCh Check if the register is per chain */
13120 + .noiseFloorThreshCh = {-1, 0, 0},
13121 + .ob = {3, 3, 3}, /* 3 chain */
13122 + .db_stage2 = {3, 3, 3}, /* 3 chain */
13123 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
13124 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
13125 + .xpaBiasLvl = 0,
13126 + .txFrameToDataStart = 0x0e,
13127 + .txFrameToPaOn = 0x0e,
13128 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
13129 + .antennaGain = 0,
13130 + .switchSettling = 0x2d,
13131 + .adcDesiredSize = -30,
13132 + .txEndToXpaOff = 0,
13133 + .txEndToRxOn = 0x2,
13134 + .txFrameToXpaOn = 0xe,
13135 + .thresh62 = 28,
13136 + .futureModal = {
13137 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13138 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
13139 + },
13140 + },
13141 + .calFreqPier5G = {
13142 + FREQ2FBIN(5180, 0),
13143 + FREQ2FBIN(5220, 0),
13144 + FREQ2FBIN(5320, 0),
13145 + FREQ2FBIN(5400, 0),
13146 + FREQ2FBIN(5500, 0),
13147 + FREQ2FBIN(5600, 0),
13148 + FREQ2FBIN(5725, 0),
13149 + FREQ2FBIN(5825, 0)
13150 + },
13151 + .calPierData5G = {
13152 + {
13153 + {0, 0, 0, 0, 0},
13154 + {0, 0, 0, 0, 0},
13155 + {0, 0, 0, 0, 0},
13156 + {0, 0, 0, 0, 0},
13157 + {0, 0, 0, 0, 0},
13158 + {0, 0, 0, 0, 0},
13159 + {0, 0, 0, 0, 0},
13160 + {0, 0, 0, 0, 0},
13161 + },
13162 + {
13163 + {0, 0, 0, 0, 0},
13164 + {0, 0, 0, 0, 0},
13165 + {0, 0, 0, 0, 0},
13166 + {0, 0, 0, 0, 0},
13167 + {0, 0, 0, 0, 0},
13168 + {0, 0, 0, 0, 0},
13169 + {0, 0, 0, 0, 0},
13170 + {0, 0, 0, 0, 0},
13171 + },
13172 + {
13173 + {0, 0, 0, 0, 0},
13174 + {0, 0, 0, 0, 0},
13175 + {0, 0, 0, 0, 0},
13176 + {0, 0, 0, 0, 0},
13177 + {0, 0, 0, 0, 0},
13178 + {0, 0, 0, 0, 0},
13179 + {0, 0, 0, 0, 0},
13180 + {0, 0, 0, 0, 0},
13181 + },
13182 +
13183 + },
13184 + .calTarget_freqbin_5G = {
13185 + FREQ2FBIN(5180, 0),
13186 + FREQ2FBIN(5220, 0),
13187 + FREQ2FBIN(5320, 0),
13188 + FREQ2FBIN(5400, 0),
13189 + FREQ2FBIN(5500, 0),
13190 + FREQ2FBIN(5600, 0),
13191 + FREQ2FBIN(5725, 0),
13192 + FREQ2FBIN(5825, 0)
13193 + },
13194 + .calTarget_freqbin_5GHT20 = {
13195 + FREQ2FBIN(5180, 0),
13196 + FREQ2FBIN(5240, 0),
13197 + FREQ2FBIN(5320, 0),
13198 + FREQ2FBIN(5500, 0),
13199 + FREQ2FBIN(5700, 0),
13200 + FREQ2FBIN(5745, 0),
13201 + FREQ2FBIN(5725, 0),
13202 + FREQ2FBIN(5825, 0)
13203 + },
13204 + .calTarget_freqbin_5GHT40 = {
13205 + FREQ2FBIN(5180, 0),
13206 + FREQ2FBIN(5240, 0),
13207 + FREQ2FBIN(5320, 0),
13208 + FREQ2FBIN(5500, 0),
13209 + FREQ2FBIN(5700, 0),
13210 + FREQ2FBIN(5745, 0),
13211 + FREQ2FBIN(5725, 0),
13212 + FREQ2FBIN(5825, 0)
13213 + },
13214 + .calTargetPower5G = {
13215 + /* 6-24,36,48,54 */
13216 + { {20, 20, 20, 10} },
13217 + { {20, 20, 20, 10} },
13218 + { {20, 20, 20, 10} },
13219 + { {20, 20, 20, 10} },
13220 + { {20, 20, 20, 10} },
13221 + { {20, 20, 20, 10} },
13222 + { {20, 20, 20, 10} },
13223 + { {20, 20, 20, 10} },
13224 + },
13225 + .calTargetPower5GHT20 = {
13226 + /*
13227 + * 0_8_16,1-3_9-11_17-19,
13228 + * 4,5,6,7,12,13,14,15,20,21,22,23
13229 + */
13230 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13231 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13232 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13233 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13234 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13235 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13236 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13237 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13238 + },
13239 + .calTargetPower5GHT40 = {
13240 + /*
13241 + * 0_8_16,1-3_9-11_17-19,
13242 + * 4,5,6,7,12,13,14,15,20,21,22,23
13243 + */
13244 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13245 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13246 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13247 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13248 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13249 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13250 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13251 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
13252 + },
13253 + .ctlIndex_5G = {
13254 + 0x10, 0x16, 0x18, 0x40, 0x46,
13255 + 0x48, 0x30, 0x36, 0x38
13256 + },
13257 + .ctl_freqbin_5G = {
13258 + {
13259 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13260 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13261 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
13262 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13263 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
13264 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13265 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13266 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13267 + },
13268 + {
13269 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13270 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13271 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
13272 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13273 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
13274 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13275 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13276 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13277 + },
13278 +
13279 + {
13280 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13281 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
13282 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
13283 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
13284 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
13285 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
13286 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
13287 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
13288 + },
13289 +
13290 + {
13291 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13292 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
13293 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
13294 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
13295 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
13296 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13297 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
13298 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
13299 + },
13300 +
13301 + {
13302 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13303 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13304 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
13305 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
13306 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
13307 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
13308 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
13309 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
13310 + },
13311 +
13312 + {
13313 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13314 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
13315 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
13316 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
13317 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
13318 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
13319 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
13320 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
13321 + },
13322 +
13323 + {
13324 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13325 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
13326 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
13327 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
13328 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
13329 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
13330 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
13331 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
13332 + },
13333 +
13334 + {
13335 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
13336 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
13337 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
13338 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
13339 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
13340 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
13341 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
13342 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
13343 + },
13344 +
13345 + {
13346 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
13347 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
13348 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
13349 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
13350 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
13351 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
13352 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
13353 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
13354 + }
13355 + },
13356 + .ctlPowerData_5G = {
13357 + {
13358 + {
13359 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13360 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13361 + }
13362 + },
13363 + {
13364 + {
13365 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13366 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13367 + }
13368 + },
13369 + {
13370 + {
13371 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
13372 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13373 + }
13374 + },
13375 + {
13376 + {
13377 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
13378 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
13379 + }
13380 + },
13381 + {
13382 + {
13383 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13384 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
13385 + }
13386 + },
13387 + {
13388 + {
13389 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13390 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
13391 + }
13392 + },
13393 + {
13394 + {
13395 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13396 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
13397 + }
13398 + },
13399 + {
13400 + {
13401 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
13402 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
13403 + }
13404 + },
13405 + {
13406 + {
13407 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
13408 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
13409 + }
13410 + },
13411 + }
13412 +};
13413 +
13414 +static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
13415 +{
13416 + return 0;
13417 +}
13418 +
13419 +static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
13420 + enum eeprom_param param)
13421 +{
13422 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13423 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
13424 +
13425 + switch (param) {
13426 + case EEP_MAC_LSW:
13427 + return eep->macAddr[0] << 8 | eep->macAddr[1];
13428 + case EEP_MAC_MID:
13429 + return eep->macAddr[2] << 8 | eep->macAddr[3];
13430 + case EEP_MAC_MSW:
13431 + return eep->macAddr[4] << 8 | eep->macAddr[5];
13432 + case EEP_REG_0:
13433 + return pBase->regDmn[0];
13434 + case EEP_REG_1:
13435 + return pBase->regDmn[1];
13436 + case EEP_OP_CAP:
13437 + return pBase->deviceCap;
13438 + case EEP_OP_MODE:
13439 + return pBase->opCapFlags.opFlags;
13440 + case EEP_RF_SILENT:
13441 + return pBase->rfSilent;
13442 + case EEP_TX_MASK:
13443 + return (pBase->txrxMask >> 4) & 0xf;
13444 + case EEP_RX_MASK:
13445 + return pBase->txrxMask & 0xf;
13446 + case EEP_DRIVE_STRENGTH:
13447 +#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
13448 + return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
13449 + case EEP_INTERNAL_REGULATOR:
13450 + /* Bit 4 is internal regulator flag */
13451 + return (pBase->featureEnable & 0x10) >> 4;
13452 + case EEP_SWREG:
13453 + return pBase->swreg;
13454 + default:
13455 + return 0;
13456 + }
13457 +}
13458 +
13459 +#ifdef __BIG_ENDIAN
13460 +static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
13461 +{
13462 + u32 dword;
13463 + u16 word;
13464 + int i;
13465 +
13466 + word = swab16(eep->baseEepHeader.regDmn[0]);
13467 + eep->baseEepHeader.regDmn[0] = word;
13468 +
13469 + word = swab16(eep->baseEepHeader.regDmn[1]);
13470 + eep->baseEepHeader.regDmn[1] = word;
13471 +
13472 + dword = swab32(eep->modalHeader2G.antCtrlCommon);
13473 + eep->modalHeader2G.antCtrlCommon = dword;
13474 +
13475 + dword = swab32(eep->modalHeader2G.antCtrlCommon2);
13476 + eep->modalHeader2G.antCtrlCommon2 = dword;
13477 +
13478 + dword = swab32(eep->modalHeader5G.antCtrlCommon);
13479 + eep->modalHeader5G.antCtrlCommon = dword;
13480 +
13481 + dword = swab32(eep->modalHeader5G.antCtrlCommon2);
13482 + eep->modalHeader5G.antCtrlCommon2 = dword;
13483 +
13484 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
13485 + word = swab16(eep->modalHeader2G.antCtrlChain[i]);
13486 + eep->modalHeader2G.antCtrlChain[i] = word;
13487 +
13488 + word = swab16(eep->modalHeader5G.antCtrlChain[i]);
13489 + eep->modalHeader5G.antCtrlChain[i] = word;
13490 + }
13491 +}
13492 +#endif
13493 +
13494 +static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
13495 + long address, u8 *buffer, int many)
13496 +{
13497 + int i;
13498 + u8 value[2];
13499 + unsigned long eepAddr;
13500 + unsigned long byteAddr;
13501 + u16 *svalue;
13502 + struct ath_common *common = ath9k_hw_common(ah);
13503 +
13504 + if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
13505 + ath_print(common, ATH_DBG_EEPROM,
13506 + "eeprom address not in range\n");
13507 + return false;
13508 + }
13509 +
13510 + for (i = 0; i < many; i++) {
13511 + eepAddr = (u16) (address + i) / 2;
13512 + byteAddr = (u16) (address + i) % 2;
13513 + svalue = (u16 *) value;
13514 + if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
13515 + ath_print(common, ATH_DBG_EEPROM,
13516 + "unable to read eeprom region\n");
13517 + return false;
13518 + }
13519 + *svalue = le16_to_cpu(*svalue);
13520 + buffer[i] = value[byteAddr];
13521 + }
13522 +
13523 + return true;
13524 +}
13525 +
13526 +static bool ar9300_read_eeprom(struct ath_hw *ah,
13527 + int address, u8 *buffer, int many)
13528 +{
13529 + int it;
13530 +
13531 + for (it = 0; it < many; it++)
13532 + if (!ar9300_hw_read_eeprom(ah,
13533 + (address - it),
13534 + (buffer + it), 1))
13535 + return false;
13536 + return true;
13537 +}
13538 +
13539 +static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
13540 + int *length, int *major, int *minor)
13541 +{
13542 + unsigned long value[4];
13543 +
13544 + value[0] = best[0];
13545 + value[1] = best[1];
13546 + value[2] = best[2];
13547 + value[3] = best[3];
13548 + *code = ((value[0] >> 5) & 0x0007);
13549 + *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
13550 + *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
13551 + *major = (value[2] & 0x000f);
13552 + *minor = (value[3] & 0x00ff);
13553 +}
13554 +
13555 +static u16 ar9300_comp_cksum(u8 *data, int dsize)
13556 +{
13557 + int it, checksum = 0;
13558 +
13559 + for (it = 0; it < dsize; it++) {
13560 + checksum += data[it];
13561 + checksum &= 0xffff;
13562 + }
13563 +
13564 + return checksum;
13565 +}
13566 +
13567 +static bool ar9300_uncompress_block(struct ath_hw *ah,
13568 + u8 *mptr,
13569 + int mdataSize,
13570 + u8 *block,
13571 + int size)
13572 +{
13573 + int it;
13574 + int spot;
13575 + int offset;
13576 + int length;
13577 + struct ath_common *common = ath9k_hw_common(ah);
13578 +
13579 + spot = 0;
13580 +
13581 + for (it = 0; it < size; it += (length+2)) {
13582 + offset = block[it];
13583 + offset &= 0xff;
13584 + spot += offset;
13585 + length = block[it+1];
13586 + length &= 0xff;
13587 +
13588 + if (length > 0 && spot >= 0 && spot+length < mdataSize) {
13589 + ath_print(common, ATH_DBG_EEPROM,
13590 + "Restore at %d: spot=%d "
13591 + "offset=%d length=%d\n",
13592 + it, spot, offset, length);
13593 + memcpy(&mptr[spot], &block[it+2], length);
13594 + spot += length;
13595 + } else if (length > 0) {
13596 + ath_print(common, ATH_DBG_EEPROM,
13597 + "Bad restore at %d: spot=%d "
13598 + "offset=%d length=%d\n",
13599 + it, spot, offset, length);
13600 + return false;
13601 + }
13602 + }
13603 + return true;
13604 +}
13605 +
13606 +static int ar9300_compress_decision(struct ath_hw *ah,
13607 + int it,
13608 + int code,
13609 + int reference,
13610 + u8 *mptr,
13611 + u8 *word, int length, int mdata_size)
13612 +{
13613 + struct ath_common *common = ath9k_hw_common(ah);
13614 + u8 *dptr;
13615 +
13616 + switch (code) {
13617 + case _CompressNone:
13618 + if (length != mdata_size) {
13619 + ath_print(common, ATH_DBG_EEPROM,
13620 + "EEPROM structure size mismatch"
13621 + "memory=%d eeprom=%d\n", mdata_size, length);
13622 + return -1;
13623 + }
13624 + memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
13625 + ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
13626 + " uncompressed, length %d\n", it, length);
13627 + break;
13628 + case _CompressBlock:
13629 + if (reference == 0) {
13630 + dptr = mptr;
13631 + } else {
13632 + if (reference != 2) {
13633 + ath_print(common, ATH_DBG_EEPROM,
13634 + "cant find reference eeprom"
13635 + "struct %d\n", reference);
13636 + return -1;
13637 + }
13638 + memcpy(mptr, &ar9300_default, mdata_size);
13639 + }
13640 + ath_print(common, ATH_DBG_EEPROM,
13641 + "restore eeprom %d: block, reference %d,"
13642 + " length %d\n", it, reference, length);
13643 + ar9300_uncompress_block(ah, mptr, mdata_size,
13644 + (u8 *) (word + COMP_HDR_LEN), length);
13645 + break;
13646 + default:
13647 + ath_print(common, ATH_DBG_EEPROM, "unknown compression"
13648 + " code %d\n", code);
13649 + return -1;
13650 + }
13651 + return 0;
13652 +}
13653 +
13654 +/*
13655 + * Read the configuration data from the eeprom.
13656 + * The data can be put in any specified memory buffer.
13657 + *
13658 + * Returns -1 on error.
13659 + * Returns address of next memory location on success.
13660 + */
13661 +static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
13662 + u8 *mptr, int mdata_size)
13663 +{
13664 +#define MDEFAULT 15
13665 +#define MSTATE 100
13666 + int cptr;
13667 + u8 *word;
13668 + int code;
13669 + int reference, length, major, minor;
13670 + int osize;
13671 + int it;
13672 + u16 checksum, mchecksum;
13673 + struct ath_common *common = ath9k_hw_common(ah);
13674 +
13675 + word = kzalloc(2048, GFP_KERNEL);
13676 + if (!word)
13677 + return -1;
13678 +
13679 + memcpy(mptr, &ar9300_default, mdata_size);
13680 +
13681 + cptr = AR9300_BASE_ADDR;
13682 + for (it = 0; it < MSTATE; it++) {
13683 + if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
13684 + goto fail;
13685 +
13686 + if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
13687 + word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
13688 + && word[2] == 0xff && word[3] == 0xff))
13689 + break;
13690 +
13691 + ar9300_comp_hdr_unpack(word, &code, &reference,
13692 + &length, &major, &minor);
13693 + ath_print(common, ATH_DBG_EEPROM,
13694 + "Found block at %x: code=%d ref=%d"
13695 + "length=%d major=%d minor=%d\n", cptr, code,
13696 + reference, length, major, minor);
13697 + if (length >= 1024) {
13698 + ath_print(common, ATH_DBG_EEPROM,
13699 + "Skipping bad header\n");
13700 + cptr -= COMP_HDR_LEN;
13701 + continue;
13702 + }
13703 +
13704 + osize = length;
13705 + ar9300_read_eeprom(ah, cptr, word,
13706 + COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
13707 + checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
13708 + mchecksum = word[COMP_HDR_LEN + osize] |
13709 + (word[COMP_HDR_LEN + osize + 1] << 8);
13710 + ath_print(common, ATH_DBG_EEPROM,
13711 + "checksum %x %x\n", checksum, mchecksum);
13712 + if (checksum == mchecksum) {
13713 + ar9300_compress_decision(ah, it, code, reference, mptr,
13714 + word, length, mdata_size);
13715 + } else {
13716 + ath_print(common, ATH_DBG_EEPROM,
13717 + "skipping block with bad checksum\n");
13718 + }
13719 + cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
13720 + }
13721 +
13722 + kfree(word);
13723 + return cptr;
13724 +
13725 +fail:
13726 + kfree(word);
13727 + return -1;
13728 +}
13729 +
13730 +/*
13731 + * Restore the configuration structure by reading the eeprom.
13732 + * This function destroys any existing in-memory structure
13733 + * content.
13734 + */
13735 +static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
13736 +{
13737 + u8 *mptr = NULL;
13738 + int mdata_size;
13739 +
13740 + mptr = (u8 *) &ah->eeprom.ar9300_eep;
13741 + mdata_size = sizeof(struct ar9300_eeprom);
13742 +
13743 + if (mptr && mdata_size > 0) {
13744 + /* At this point, mptr points to the eeprom data structure
13745 + * in it's "default" state. If this is big endian, swap the
13746 + * data structures back to "little endian"
13747 + */
13748 + /* First swap, default to Little Endian */
13749 +#ifdef __BIG_ENDIAN
13750 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
13751 +#endif
13752 + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
13753 + return true;
13754 +
13755 + /* Second Swap, back to Big Endian */
13756 +#ifdef __BIG_ENDIAN
13757 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
13758 +#endif
13759 + }
13760 + return false;
13761 +}
13762 +
13763 +/* XXX: review hardware docs */
13764 +static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
13765 +{
13766 + return ah->eeprom.ar9300_eep.eepromVersion;
13767 +}
13768 +
13769 +/* XXX: could be read from the eepromVersion, not sure yet */
13770 +static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
13771 +{
13772 + return 0;
13773 +}
13774 +
13775 +static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
13776 + enum ieee80211_band freq_band)
13777 +{
13778 + return 1;
13779 +}
13780 +
13781 +static u16 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
13782 + struct ath9k_channel *chan)
13783 +{
13784 + return -EINVAL;
13785 +}
13786 +
13787 +static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
13788 +{
13789 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13790 +
13791 + if (is2ghz)
13792 + return eep->modalHeader2G.xpaBiasLvl;
13793 + else
13794 + return eep->modalHeader5G.xpaBiasLvl;
13795 +}
13796 +
13797 +static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
13798 +{
13799 + int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
13800 + REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
13801 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
13802 + ((bias >> 2) & 0x3));
13803 +}
13804 +
13805 +static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
13806 +{
13807 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13808 +
13809 + if (is2ghz)
13810 + return eep->modalHeader2G.antCtrlCommon;
13811 + else
13812 + return eep->modalHeader5G.antCtrlCommon;
13813 +}
13814 +
13815 +static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
13816 +{
13817 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13818 +
13819 + if (is2ghz)
13820 + return eep->modalHeader2G.antCtrlCommon2;
13821 + else
13822 + return eep->modalHeader5G.antCtrlCommon2;
13823 +}
13824 +
13825 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
13826 + int chain,
13827 + bool is2ghz)
13828 +{
13829 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
13830 +
13831 + if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
13832 + if (is2ghz)
13833 + return eep->modalHeader2G.antCtrlChain[chain];
13834 + else
13835 + return eep->modalHeader5G.antCtrlChain[chain];
13836 + }
13837 +
13838 + return 0;
13839 +}
13840 +
13841 +static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
13842 +{
13843 + u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
13844 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
13845 +
13846 + value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
13847 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
13848 +
13849 + value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
13850 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
13851 +
13852 + value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
13853 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
13854 +
13855 + value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
13856 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
13857 +}
13858 +
13859 +static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
13860 +{
13861 + int drive_strength;
13862 + unsigned long reg;
13863 +
13864 + drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
13865 +
13866 + if (!drive_strength)
13867 + return;
13868 +
13869 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
13870 + reg &= ~0x00ffffc0;
13871 + reg |= 0x5 << 21;
13872 + reg |= 0x5 << 18;
13873 + reg |= 0x5 << 15;
13874 + reg |= 0x5 << 12;
13875 + reg |= 0x5 << 9;
13876 + reg |= 0x5 << 6;
13877 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
13878 +
13879 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
13880 + reg &= ~0xffffffe0;
13881 + reg |= 0x5 << 29;
13882 + reg |= 0x5 << 26;
13883 + reg |= 0x5 << 23;
13884 + reg |= 0x5 << 20;
13885 + reg |= 0x5 << 17;
13886 + reg |= 0x5 << 14;
13887 + reg |= 0x5 << 11;
13888 + reg |= 0x5 << 8;
13889 + reg |= 0x5 << 5;
13890 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
13891 +
13892 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
13893 + reg &= ~0xff800000;
13894 + reg |= 0x5 << 29;
13895 + reg |= 0x5 << 26;
13896 + reg |= 0x5 << 23;
13897 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
13898 +}
13899 +
13900 +static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
13901 +{
13902 + int internal_regulator =
13903 + ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
13904 +
13905 + if (internal_regulator) {
13906 + /* Internal regulator is ON. Write swreg register. */
13907 + int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
13908 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
13909 + REG_READ(ah, AR_RTC_REG_CONTROL1) &
13910 + (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
13911 + REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
13912 + /* Set REG_CONTROL1.SWREG_PROGRAM */
13913 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
13914 + REG_READ(ah,
13915 + AR_RTC_REG_CONTROL1) |
13916 + AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
13917 + } else {
13918 + REG_WRITE(ah, AR_RTC_SLEEP_CLK,
13919 + (REG_READ(ah,
13920 + AR_RTC_SLEEP_CLK) |
13921 + AR_RTC_FORCE_SWREG_PRD));
13922 + }
13923 +}
13924 +
13925 +static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
13926 + struct ath9k_channel *chan)
13927 +{
13928 + ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
13929 + ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
13930 + ar9003_hw_drive_strength_apply(ah);
13931 + ar9003_hw_internal_regulator_apply(ah);
13932 +}
13933 +
13934 +static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
13935 + struct ath9k_channel *chan)
13936 +{
13937 +}
13938 +
13939 +/*
13940 + * Returns the interpolated y value corresponding to the specified x value
13941 + * from the np ordered pairs of data (px,py).
13942 + * The pairs do not have to be in any order.
13943 + * If the specified x value is less than any of the px,
13944 + * the returned y value is equal to the py for the lowest px.
13945 + * If the specified x value is greater than any of the px,
13946 + * the returned y value is equal to the py for the highest px.
13947 + */
13948 +static int ar9003_hw_power_interpolate(int32_t x,
13949 + int32_t *px, int32_t *py, u_int16_t np)
13950 +{
13951 + int ip = 0;
13952 + int lx = 0, ly = 0, lhave = 0;
13953 + int hx = 0, hy = 0, hhave = 0;
13954 + int dx = 0;
13955 + int y = 0;
13956 +
13957 + lhave = 0;
13958 + hhave = 0;
13959 +
13960 + /* identify best lower and higher x calibration measurement */
13961 + for (ip = 0; ip < np; ip++) {
13962 + dx = x - px[ip];
13963 +
13964 + /* this measurement is higher than our desired x */
13965 + if (dx <= 0) {
13966 + if (!hhave || dx > (x - hx)) {
13967 + /* new best higher x measurement */
13968 + hx = px[ip];
13969 + hy = py[ip];
13970 + hhave = 1;
13971 + }
13972 + }
13973 + /* this measurement is lower than our desired x */
13974 + if (dx >= 0) {
13975 + if (!lhave || dx < (x - lx)) {
13976 + /* new best lower x measurement */
13977 + lx = px[ip];
13978 + ly = py[ip];
13979 + lhave = 1;
13980 + }
13981 + }
13982 + }
13983 +
13984 + /* the low x is good */
13985 + if (lhave) {
13986 + /* so is the high x */
13987 + if (hhave) {
13988 + /* they're the same, so just pick one */
13989 + if (hx == lx)
13990 + y = ly;
13991 + else /* interpolate */
13992 + y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
13993 + } else /* only low is good, use it */
13994 + y = ly;
13995 + } else if (hhave) /* only high is good, use it */
13996 + y = hy;
13997 + else /* nothing is good,this should never happen unless np=0, ???? */
13998 + y = -(1 << 30);
13999 + return y;
14000 +}
14001 +
14002 +static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
14003 + u16 rateIndex, u16 freq, bool is2GHz)
14004 +{
14005 + u16 numPiers, i;
14006 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
14007 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
14008 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14009 + struct cal_tgt_pow_legacy *pEepromTargetPwr;
14010 + u8 *pFreqBin;
14011 +
14012 + if (is2GHz) {
14013 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14014 + pEepromTargetPwr = eep->calTargetPower2G;
14015 + pFreqBin = eep->calTarget_freqbin_2G;
14016 + } else {
14017 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14018 + pEepromTargetPwr = eep->calTargetPower5G;
14019 + pFreqBin = eep->calTarget_freqbin_5G;
14020 + }
14021 +
14022 + /*
14023 + * create array of channels and targetpower from
14024 + * targetpower piers stored on eeprom
14025 + */
14026 + for (i = 0; i < numPiers; i++) {
14027 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
14028 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14029 + }
14030 +
14031 + /* interpolate to get target power for given frequency */
14032 + return (u8) ar9003_hw_power_interpolate((s32) freq,
14033 + freqArray,
14034 + targetPowerArray, numPiers);
14035 +}
14036 +
14037 +static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
14038 + u16 rateIndex,
14039 + u16 freq, bool is2GHz)
14040 +{
14041 + u16 numPiers, i;
14042 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
14043 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
14044 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14045 + struct cal_tgt_pow_ht *pEepromTargetPwr;
14046 + u8 *pFreqBin;
14047 +
14048 + if (is2GHz) {
14049 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14050 + pEepromTargetPwr = eep->calTargetPower2GHT20;
14051 + pFreqBin = eep->calTarget_freqbin_2GHT20;
14052 + } else {
14053 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
14054 + pEepromTargetPwr = eep->calTargetPower5GHT20;
14055 + pFreqBin = eep->calTarget_freqbin_5GHT20;
14056 + }
14057 +
14058 + /*
14059 + * create array of channels and targetpower
14060 + * from targetpower piers stored on eeprom
14061 + */
14062 + for (i = 0; i < numPiers; i++) {
14063 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
14064 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14065 + }
14066 +
14067 + /* interpolate to get target power for given frequency */
14068 + return (u8) ar9003_hw_power_interpolate((s32) freq,
14069 + freqArray,
14070 + targetPowerArray, numPiers);
14071 +}
14072 +
14073 +static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
14074 + u16 rateIndex,
14075 + u16 freq, bool is2GHz)
14076 +{
14077 + u16 numPiers, i;
14078 + s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
14079 + s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
14080 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14081 + struct cal_tgt_pow_ht *pEepromTargetPwr;
14082 + u8 *pFreqBin;
14083 +
14084 + if (is2GHz) {
14085 + numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
14086 + pEepromTargetPwr = eep->calTargetPower2GHT40;
14087 + pFreqBin = eep->calTarget_freqbin_2GHT40;
14088 + } else {
14089 + numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
14090 + pEepromTargetPwr = eep->calTargetPower5GHT40;
14091 + pFreqBin = eep->calTarget_freqbin_5GHT40;
14092 + }
14093 +
14094 + /*
14095 + * create array of channels and targetpower from
14096 + * targetpower piers stored on eeprom
14097 + */
14098 + for (i = 0; i < numPiers; i++) {
14099 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
14100 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14101 + }
14102 +
14103 + /* interpolate to get target power for given frequency */
14104 + return (u8) ar9003_hw_power_interpolate((s32) freq,
14105 + freqArray,
14106 + targetPowerArray, numPiers);
14107 +}
14108 +
14109 +static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
14110 + u16 rateIndex, u16 freq)
14111 +{
14112 + u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
14113 + s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
14114 + s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
14115 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14116 + struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
14117 + u8 *pFreqBin = eep->calTarget_freqbin_Cck;
14118 +
14119 + /*
14120 + * create array of channels and targetpower from
14121 + * targetpower piers stored on eeprom
14122 + */
14123 + for (i = 0; i < numPiers; i++) {
14124 + freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
14125 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
14126 + }
14127 +
14128 + /* interpolate to get target power for given frequency */
14129 + return (u8) ar9003_hw_power_interpolate((s32) freq,
14130 + freqArray,
14131 + targetPowerArray, numPiers);
14132 +}
14133 +
14134 +/* Set tx power registers to array of values passed in */
14135 +static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
14136 +{
14137 +#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
14138 + /* make sure forced gain is not set */
14139 + REG_WRITE(ah, 0xa458, 0);
14140 +
14141 + /* Write the OFDM power per rate set */
14142 +
14143 + /* 6 (LSB), 9, 12, 18 (MSB) */
14144 + REG_WRITE(ah, 0xa3c0,
14145 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
14146 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
14147 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
14148 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
14149 +
14150 + /* 24 (LSB), 36, 48, 54 (MSB) */
14151 + REG_WRITE(ah, 0xa3c4,
14152 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
14153 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
14154 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
14155 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
14156 +
14157 + /* Write the CCK power per rate set */
14158 +
14159 + /* 1L (LSB), reserved, 2L, 2S (MSB) */
14160 + REG_WRITE(ah, 0xa3c8,
14161 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
14162 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
14163 + /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
14164 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
14165 +
14166 + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
14167 + REG_WRITE(ah, 0xa3cc,
14168 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
14169 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
14170 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
14171 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
14172 + );
14173 +
14174 + /* Write the HT20 power per rate set */
14175 +
14176 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
14177 + REG_WRITE(ah, 0xa3d0,
14178 + POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
14179 + POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
14180 + POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
14181 + POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
14182 + );
14183 +
14184 + /* 6 (LSB), 7, 12, 13 (MSB) */
14185 + REG_WRITE(ah, 0xa3d4,
14186 + POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
14187 + POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
14188 + POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
14189 + POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
14190 + );
14191 +
14192 + /* 14 (LSB), 15, 20, 21 */
14193 + REG_WRITE(ah, 0xa3e4,
14194 + POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
14195 + POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
14196 + POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
14197 + POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
14198 + );
14199 +
14200 + /* Mixed HT20 and HT40 rates */
14201 +
14202 + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
14203 + REG_WRITE(ah, 0xa3e8,
14204 + POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
14205 + POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
14206 + POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
14207 + POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
14208 + );
14209 +
14210 + /*
14211 + * Write the HT40 power per rate set
14212 + * correct PAR difference between HT40 and HT20/LEGACY
14213 + * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
14214 + */
14215 + REG_WRITE(ah, 0xa3d8,
14216 + POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
14217 + POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
14218 + POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
14219 + POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
14220 + );
14221 +
14222 + /* 6 (LSB), 7, 12, 13 (MSB) */
14223 + REG_WRITE(ah, 0xa3dc,
14224 + POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
14225 + POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
14226 + POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
14227 + POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
14228 + );
14229 +
14230 + /* 14 (LSB), 15, 20, 21 */
14231 + REG_WRITE(ah, 0xa3ec,
14232 + POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
14233 + POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
14234 + POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
14235 + POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
14236 + );
14237 +
14238 + return 0;
14239 +#undef POW_SM
14240 +}
14241 +
14242 +static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq)
14243 +{
14244 + u8 targetPowerValT2[ar9300RateSize];
14245 + /* XXX: hard code for now, need to get from eeprom struct */
14246 + u8 ht40PowerIncForPdadc = 0;
14247 + bool is2GHz = false;
14248 + unsigned int i = 0;
14249 + struct ath_common *common = ath9k_hw_common(ah);
14250 +
14251 + if (freq < 4000)
14252 + is2GHz = true;
14253 +
14254 + targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
14255 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
14256 + is2GHz);
14257 + targetPowerValT2[ALL_TARGET_LEGACY_36] =
14258 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
14259 + is2GHz);
14260 + targetPowerValT2[ALL_TARGET_LEGACY_48] =
14261 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
14262 + is2GHz);
14263 + targetPowerValT2[ALL_TARGET_LEGACY_54] =
14264 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
14265 + is2GHz);
14266 + targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
14267 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
14268 + freq);
14269 + targetPowerValT2[ALL_TARGET_LEGACY_5S] =
14270 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
14271 + targetPowerValT2[ALL_TARGET_LEGACY_11L] =
14272 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
14273 + targetPowerValT2[ALL_TARGET_LEGACY_11S] =
14274 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
14275 + targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
14276 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
14277 + is2GHz);
14278 + targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
14279 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
14280 + freq, is2GHz);
14281 + targetPowerValT2[ALL_TARGET_HT20_4] =
14282 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
14283 + is2GHz);
14284 + targetPowerValT2[ALL_TARGET_HT20_5] =
14285 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
14286 + is2GHz);
14287 + targetPowerValT2[ALL_TARGET_HT20_6] =
14288 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
14289 + is2GHz);
14290 + targetPowerValT2[ALL_TARGET_HT20_7] =
14291 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
14292 + is2GHz);
14293 + targetPowerValT2[ALL_TARGET_HT20_12] =
14294 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
14295 + is2GHz);
14296 + targetPowerValT2[ALL_TARGET_HT20_13] =
14297 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
14298 + is2GHz);
14299 + targetPowerValT2[ALL_TARGET_HT20_14] =
14300 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
14301 + is2GHz);
14302 + targetPowerValT2[ALL_TARGET_HT20_15] =
14303 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
14304 + is2GHz);
14305 + targetPowerValT2[ALL_TARGET_HT20_20] =
14306 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
14307 + is2GHz);
14308 + targetPowerValT2[ALL_TARGET_HT20_21] =
14309 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
14310 + is2GHz);
14311 + targetPowerValT2[ALL_TARGET_HT20_22] =
14312 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
14313 + is2GHz);
14314 + targetPowerValT2[ALL_TARGET_HT20_23] =
14315 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
14316 + is2GHz);
14317 + targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
14318 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
14319 + is2GHz) + ht40PowerIncForPdadc;
14320 + targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
14321 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
14322 + freq,
14323 + is2GHz) + ht40PowerIncForPdadc;
14324 + targetPowerValT2[ALL_TARGET_HT40_4] =
14325 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
14326 + is2GHz) + ht40PowerIncForPdadc;
14327 + targetPowerValT2[ALL_TARGET_HT40_5] =
14328 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
14329 + is2GHz) + ht40PowerIncForPdadc;
14330 + targetPowerValT2[ALL_TARGET_HT40_6] =
14331 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
14332 + is2GHz) + ht40PowerIncForPdadc;
14333 + targetPowerValT2[ALL_TARGET_HT40_7] =
14334 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
14335 + is2GHz) + ht40PowerIncForPdadc;
14336 + targetPowerValT2[ALL_TARGET_HT40_12] =
14337 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
14338 + is2GHz) + ht40PowerIncForPdadc;
14339 + targetPowerValT2[ALL_TARGET_HT40_13] =
14340 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
14341 + is2GHz) + ht40PowerIncForPdadc;
14342 + targetPowerValT2[ALL_TARGET_HT40_14] =
14343 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
14344 + is2GHz) + ht40PowerIncForPdadc;
14345 + targetPowerValT2[ALL_TARGET_HT40_15] =
14346 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
14347 + is2GHz) + ht40PowerIncForPdadc;
14348 + targetPowerValT2[ALL_TARGET_HT40_20] =
14349 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
14350 + is2GHz) + ht40PowerIncForPdadc;
14351 + targetPowerValT2[ALL_TARGET_HT40_21] =
14352 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
14353 + is2GHz) + ht40PowerIncForPdadc;
14354 + targetPowerValT2[ALL_TARGET_HT40_22] =
14355 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
14356 + is2GHz) + ht40PowerIncForPdadc;
14357 + targetPowerValT2[ALL_TARGET_HT40_23] =
14358 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
14359 + is2GHz) + ht40PowerIncForPdadc;
14360 +
14361 + while (i < ar9300RateSize) {
14362 + ath_print(common, ATH_DBG_EEPROM,
14363 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14364 + i++;
14365 +
14366 + ath_print(common, ATH_DBG_EEPROM,
14367 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14368 + i++;
14369 +
14370 + ath_print(common, ATH_DBG_EEPROM,
14371 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
14372 + i++;
14373 +
14374 + ath_print(common, ATH_DBG_EEPROM,
14375 + "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
14376 + i++;
14377 + }
14378 +
14379 + /* Write target power array to registers */
14380 + ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
14381 +}
14382 +
14383 +static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
14384 + int mode,
14385 + int ipier,
14386 + int ichain,
14387 + int *pfrequency,
14388 + int *pcorrection,
14389 + int *ptemperature, int *pvoltage)
14390 +{
14391 + u8 *pCalPier;
14392 + struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
14393 + int is2GHz;
14394 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14395 + struct ath_common *common = ath9k_hw_common(ah);
14396 +
14397 + if (ichain >= AR9300_MAX_CHAINS) {
14398 + ath_print(common, ATH_DBG_EEPROM,
14399 + "Invalid chain index, must be less than %d\n",
14400 + AR9300_MAX_CHAINS);
14401 + return -1;
14402 + }
14403 +
14404 + if (mode) { /* 5GHz */
14405 + if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
14406 + ath_print(common, ATH_DBG_EEPROM,
14407 + "Invalid 5GHz cal pier index, must "
14408 + "be less than %d\n",
14409 + AR9300_NUM_5G_CAL_PIERS);
14410 + return -1;
14411 + }
14412 + pCalPier = &(eep->calFreqPier5G[ipier]);
14413 + pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
14414 + is2GHz = 0;
14415 + } else {
14416 + if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
14417 + ath_print(common, ATH_DBG_EEPROM,
14418 + "Invalid 2GHz cal pier index, must "
14419 + "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
14420 + return -1;
14421 + }
14422 +
14423 + pCalPier = &(eep->calFreqPier2G[ipier]);
14424 + pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
14425 + is2GHz = 1;
14426 + }
14427 +
14428 + *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
14429 + *pcorrection = pCalPierStruct->refPower;
14430 + *ptemperature = pCalPierStruct->tempMeas;
14431 + *pvoltage = pCalPierStruct->voltMeas;
14432 +
14433 + return 0;
14434 +}
14435 +
14436 +static int ar9003_hw_power_control_override(struct ath_hw *ah,
14437 + int frequency,
14438 + int *correction,
14439 + int *voltage, int *temperature)
14440 +{
14441 + int tempSlope = 0;
14442 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14443 +
14444 + REG_RMW(ah, AR_PHY_TPC_11_B0,
14445 + (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14446 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14447 + REG_RMW(ah, AR_PHY_TPC_11_B1,
14448 + (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14449 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14450 + REG_RMW(ah, AR_PHY_TPC_11_B2,
14451 + (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
14452 + AR_PHY_TPC_OLPC_GAIN_DELTA);
14453 +
14454 + /* enable open loop power control on chip */
14455 + REG_RMW(ah, AR_PHY_TPC_6_B0,
14456 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14457 + AR_PHY_TPC_6_ERROR_EST_MODE);
14458 + REG_RMW(ah, AR_PHY_TPC_6_B1,
14459 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14460 + AR_PHY_TPC_6_ERROR_EST_MODE);
14461 + REG_RMW(ah, AR_PHY_TPC_6_B2,
14462 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
14463 + AR_PHY_TPC_6_ERROR_EST_MODE);
14464 +
14465 + /*
14466 + * enable temperature compensation
14467 + * Need to use register names
14468 + */
14469 + if (frequency < 4000)
14470 + tempSlope = eep->modalHeader2G.tempSlope;
14471 + else
14472 + tempSlope = eep->modalHeader5G.tempSlope;
14473 +
14474 + REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
14475 + REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
14476 + temperature[0]);
14477 +
14478 + return 0;
14479 +}
14480 +
14481 +/* Apply the recorded correction values. */
14482 +static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
14483 +{
14484 + int ichain, ipier, npier;
14485 + int mode;
14486 + int lfrequency[AR9300_MAX_CHAINS],
14487 + lcorrection[AR9300_MAX_CHAINS],
14488 + ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
14489 + int hfrequency[AR9300_MAX_CHAINS],
14490 + hcorrection[AR9300_MAX_CHAINS],
14491 + htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
14492 + int fdiff;
14493 + int correction[AR9300_MAX_CHAINS],
14494 + voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
14495 + int pfrequency, pcorrection, ptemperature, pvoltage;
14496 + struct ath_common *common = ath9k_hw_common(ah);
14497 +
14498 + mode = (frequency >= 4000);
14499 + if (mode)
14500 + npier = AR9300_NUM_5G_CAL_PIERS;
14501 + else
14502 + npier = AR9300_NUM_2G_CAL_PIERS;
14503 +
14504 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14505 + lfrequency[ichain] = 0;
14506 + hfrequency[ichain] = 100000;
14507 + }
14508 + /* identify best lower and higher frequency calibration measurement */
14509 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14510 + for (ipier = 0; ipier < npier; ipier++) {
14511 + if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
14512 + &pfrequency, &pcorrection,
14513 + &ptemperature, &pvoltage)) {
14514 + fdiff = frequency - pfrequency;
14515 +
14516 + /*
14517 + * this measurement is higher than
14518 + * our desired frequency
14519 + */
14520 + if (fdiff <= 0) {
14521 + if (hfrequency[ichain] <= 0 ||
14522 + hfrequency[ichain] >= 100000 ||
14523 + fdiff >
14524 + (frequency - hfrequency[ichain])) {
14525 + /*
14526 + * new best higher
14527 + * frequency measurement
14528 + */
14529 + hfrequency[ichain] = pfrequency;
14530 + hcorrection[ichain] =
14531 + pcorrection;
14532 + htemperature[ichain] =
14533 + ptemperature;
14534 + hvoltage[ichain] = pvoltage;
14535 + }
14536 + }
14537 + if (fdiff >= 0) {
14538 + if (lfrequency[ichain] <= 0
14539 + || fdiff <
14540 + (frequency - lfrequency[ichain])) {
14541 + /*
14542 + * new best lower
14543 + * frequency measurement
14544 + */
14545 + lfrequency[ichain] = pfrequency;
14546 + lcorrection[ichain] =
14547 + pcorrection;
14548 + ltemperature[ichain] =
14549 + ptemperature;
14550 + lvoltage[ichain] = pvoltage;
14551 + }
14552 + }
14553 + }
14554 + }
14555 + }
14556 +
14557 + /* interpolate */
14558 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
14559 + ath_print(common, ATH_DBG_EEPROM,
14560 + "ch=%d f=%d low=%d %d h=%d %d\n",
14561 + ichain, frequency, lfrequency[ichain],
14562 + lcorrection[ichain], hfrequency[ichain],
14563 + hcorrection[ichain]);
14564 + /* they're the same, so just pick one */
14565 + if (hfrequency[ichain] == lfrequency[ichain]) {
14566 + correction[ichain] = lcorrection[ichain];
14567 + voltage[ichain] = lvoltage[ichain];
14568 + temperature[ichain] = ltemperature[ichain];
14569 + }
14570 + /* the low frequency is good */
14571 + else if (frequency - lfrequency[ichain] < 1000) {
14572 + /* so is the high frequency, interpolate */
14573 + if (hfrequency[ichain] - frequency < 1000) {
14574 +
14575 + correction[ichain] = lcorrection[ichain] +
14576 + (((frequency - lfrequency[ichain]) *
14577 + (hcorrection[ichain] -
14578 + lcorrection[ichain])) /
14579 + (hfrequency[ichain] - lfrequency[ichain]));
14580 +
14581 + temperature[ichain] = ltemperature[ichain] +
14582 + (((frequency - lfrequency[ichain]) *
14583 + (htemperature[ichain] -
14584 + ltemperature[ichain])) /
14585 + (hfrequency[ichain] - lfrequency[ichain]));
14586 +
14587 + voltage[ichain] =
14588 + lvoltage[ichain] +
14589 + (((frequency -
14590 + lfrequency[ichain]) * (hvoltage[ichain] -
14591 + lvoltage[ichain]))
14592 + / (hfrequency[ichain] -
14593 + lfrequency[ichain]));
14594 + }
14595 + /* only low is good, use it */
14596 + else {
14597 + correction[ichain] = lcorrection[ichain];
14598 + temperature[ichain] = ltemperature[ichain];
14599 + voltage[ichain] = lvoltage[ichain];
14600 + }
14601 + }
14602 + /* only high is good, use it */
14603 + else if (hfrequency[ichain] - frequency < 1000) {
14604 + correction[ichain] = hcorrection[ichain];
14605 + temperature[ichain] = htemperature[ichain];
14606 + voltage[ichain] = hvoltage[ichain];
14607 + } else { /* nothing is good, presume 0???? */
14608 + correction[ichain] = 0;
14609 + temperature[ichain] = 0;
14610 + voltage[ichain] = 0;
14611 + }
14612 + }
14613 +
14614 + ar9003_hw_power_control_override(ah, frequency, correction, voltage,
14615 + temperature);
14616 +
14617 + ath_print(common, ATH_DBG_EEPROM,
14618 + "for frequency=%d, calibration correction = %d %d %d\n",
14619 + frequency, correction[0], correction[1], correction[2]);
14620 +
14621 + return 0;
14622 +}
14623 +
14624 +static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
14625 + struct ath9k_channel *chan, u16 cfgCtl,
14626 + u8 twiceAntennaReduction,
14627 + u8 twiceMaxRegulatoryPower,
14628 + u8 powerLimit)
14629 +{
14630 + ar9003_hw_set_target_power_eeprom(ah, chan->channel);
14631 + ar9003_hw_calibration_apply(ah, chan->channel);
14632 +}
14633 +
14634 +static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
14635 + u16 i, bool is2GHz)
14636 +{
14637 + return AR_NO_SPUR;
14638 +}
14639 +
14640 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
14641 +{
14642 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14643 +
14644 + return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
14645 +}
14646 +
14647 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
14648 +{
14649 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
14650 +
14651 + return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
14652 +}
14653 +
14654 +const struct eeprom_ops eep_ar9300_ops = {
14655 + .check_eeprom = ath9k_hw_ar9300_check_eeprom,
14656 + .get_eeprom = ath9k_hw_ar9300_get_eeprom,
14657 + .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
14658 + .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
14659 + .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
14660 + .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
14661 + .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
14662 + .set_board_values = ath9k_hw_ar9300_set_board_values,
14663 + .set_addac = ath9k_hw_ar9300_set_addac,
14664 + .set_txpower = ath9k_hw_ar9300_set_txpower,
14665 + .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
14666 +};
14667 --- /dev/null
14668 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
14669 @@ -0,0 +1,323 @@
14670 +#ifndef AR9003_EEPROM_H
14671 +#define AR9003_EEPROM_H
14672 +
14673 +#include <linux/types.h>
14674 +
14675 +#define AR9300_EEP_VER 0xD000
14676 +#define AR9300_EEP_VER_MINOR_MASK 0xFFF
14677 +#define AR9300_EEP_MINOR_VER_1 0x1
14678 +#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
14679 +
14680 +/* 16-bit offset location start of calibration struct */
14681 +#define AR9300_EEP_START_LOC 256
14682 +#define AR9300_NUM_5G_CAL_PIERS 8
14683 +#define AR9300_NUM_2G_CAL_PIERS 3
14684 +#define AR9300_NUM_5G_20_TARGET_POWERS 8
14685 +#define AR9300_NUM_5G_40_TARGET_POWERS 8
14686 +#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
14687 +#define AR9300_NUM_2G_20_TARGET_POWERS 3
14688 +#define AR9300_NUM_2G_40_TARGET_POWERS 3
14689 +/* #define AR9300_NUM_CTLS 21 */
14690 +#define AR9300_NUM_CTLS_5G 9
14691 +#define AR9300_NUM_CTLS_2G 12
14692 +#define AR9300_CTL_MODE_M 0xF
14693 +#define AR9300_NUM_BAND_EDGES_5G 8
14694 +#define AR9300_NUM_BAND_EDGES_2G 4
14695 +#define AR9300_NUM_PD_GAINS 4
14696 +#define AR9300_PD_GAINS_IN_MASK 4
14697 +#define AR9300_PD_GAIN_ICEPTS 5
14698 +#define AR9300_EEPROM_MODAL_SPURS 5
14699 +#define AR9300_MAX_RATE_POWER 63
14700 +#define AR9300_NUM_PDADC_VALUES 128
14701 +#define AR9300_NUM_RATES 16
14702 +#define AR9300_BCHAN_UNUSED 0xFF
14703 +#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
14704 +#define AR9300_OPFLAGS_11A 0x01
14705 +#define AR9300_OPFLAGS_11G 0x02
14706 +#define AR9300_OPFLAGS_5G_HT40 0x04
14707 +#define AR9300_OPFLAGS_2G_HT40 0x08
14708 +#define AR9300_OPFLAGS_5G_HT20 0x10
14709 +#define AR9300_OPFLAGS_2G_HT20 0x20
14710 +#define AR9300_EEPMISC_BIG_ENDIAN 0x01
14711 +#define AR9300_EEPMISC_WOW 0x02
14712 +#define AR9300_CUSTOMER_DATA_SIZE 20
14713 +
14714 +#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
14715 +#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
14716 +#define AR9300_MAX_CHAINS 3
14717 +#define AR9300_ANT_16S 25
14718 +#define AR9300_FUTURE_MODAL_SZ 6
14719 +
14720 +#define AR9300_NUM_ANT_CHAIN_FIELDS 7
14721 +#define AR9300_NUM_ANT_COMMON_FIELDS 4
14722 +#define AR9300_SIZE_ANT_CHAIN_FIELD 3
14723 +#define AR9300_SIZE_ANT_COMMON_FIELD 4
14724 +#define AR9300_ANT_CHAIN_MASK 0x7
14725 +#define AR9300_ANT_COMMON_MASK 0xf
14726 +#define AR9300_CHAIN_0_IDX 0
14727 +#define AR9300_CHAIN_1_IDX 1
14728 +#define AR9300_CHAIN_2_IDX 2
14729 +
14730 +#define AR928X_NUM_ANT_CHAIN_FIELDS 6
14731 +#define AR928X_SIZE_ANT_CHAIN_FIELD 2
14732 +#define AR928X_ANT_CHAIN_MASK 0x3
14733 +
14734 +/* Delta from which to start power to pdadc table */
14735 +/* This offset is used in both open loop and closed loop power control
14736 + * schemes. In open loop power control, it is not really needed, but for
14737 + * the "sake of consistency" it was kept. For certain AP designs, this
14738 + * value is overwritten by the value in the flag "pwrTableOffset" just
14739 + * before writing the pdadc vs pwr into the chip registers.
14740 + */
14741 +#define AR9300_PWR_TABLE_OFFSET 0
14742 +
14743 +/* enable flags for voltage and temp compensation */
14744 +#define ENABLE_TEMP_COMPENSATION 0x01
14745 +#define ENABLE_VOLT_COMPENSATION 0x02
14746 +/* byte addressable */
14747 +#define AR9300_EEPROM_SIZE (16*1024)
14748 +#define FIXED_CCA_THRESHOLD 15
14749 +
14750 +#define AR9300_BASE_ADDR 0x3ff
14751 +
14752 +enum targetPowerHTRates {
14753 + HT_TARGET_RATE_0_8_16,
14754 + HT_TARGET_RATE_1_3_9_11_17_19,
14755 + HT_TARGET_RATE_4,
14756 + HT_TARGET_RATE_5,
14757 + HT_TARGET_RATE_6,
14758 + HT_TARGET_RATE_7,
14759 + HT_TARGET_RATE_12,
14760 + HT_TARGET_RATE_13,
14761 + HT_TARGET_RATE_14,
14762 + HT_TARGET_RATE_15,
14763 + HT_TARGET_RATE_20,
14764 + HT_TARGET_RATE_21,
14765 + HT_TARGET_RATE_22,
14766 + HT_TARGET_RATE_23
14767 +};
14768 +
14769 +enum targetPowerLegacyRates {
14770 + LEGACY_TARGET_RATE_6_24,
14771 + LEGACY_TARGET_RATE_36,
14772 + LEGACY_TARGET_RATE_48,
14773 + LEGACY_TARGET_RATE_54
14774 +};
14775 +
14776 +enum targetPowerCckRates {
14777 + LEGACY_TARGET_RATE_1L_5L,
14778 + LEGACY_TARGET_RATE_5S,
14779 + LEGACY_TARGET_RATE_11L,
14780 + LEGACY_TARGET_RATE_11S
14781 +};
14782 +
14783 +enum ar9300_Rates {
14784 + ALL_TARGET_LEGACY_6_24,
14785 + ALL_TARGET_LEGACY_36,
14786 + ALL_TARGET_LEGACY_48,
14787 + ALL_TARGET_LEGACY_54,
14788 + ALL_TARGET_LEGACY_1L_5L,
14789 + ALL_TARGET_LEGACY_5S,
14790 + ALL_TARGET_LEGACY_11L,
14791 + ALL_TARGET_LEGACY_11S,
14792 + ALL_TARGET_HT20_0_8_16,
14793 + ALL_TARGET_HT20_1_3_9_11_17_19,
14794 + ALL_TARGET_HT20_4,
14795 + ALL_TARGET_HT20_5,
14796 + ALL_TARGET_HT20_6,
14797 + ALL_TARGET_HT20_7,
14798 + ALL_TARGET_HT20_12,
14799 + ALL_TARGET_HT20_13,
14800 + ALL_TARGET_HT20_14,
14801 + ALL_TARGET_HT20_15,
14802 + ALL_TARGET_HT20_20,
14803 + ALL_TARGET_HT20_21,
14804 + ALL_TARGET_HT20_22,
14805 + ALL_TARGET_HT20_23,
14806 + ALL_TARGET_HT40_0_8_16,
14807 + ALL_TARGET_HT40_1_3_9_11_17_19,
14808 + ALL_TARGET_HT40_4,
14809 + ALL_TARGET_HT40_5,
14810 + ALL_TARGET_HT40_6,
14811 + ALL_TARGET_HT40_7,
14812 + ALL_TARGET_HT40_12,
14813 + ALL_TARGET_HT40_13,
14814 + ALL_TARGET_HT40_14,
14815 + ALL_TARGET_HT40_15,
14816 + ALL_TARGET_HT40_20,
14817 + ALL_TARGET_HT40_21,
14818 + ALL_TARGET_HT40_22,
14819 + ALL_TARGET_HT40_23,
14820 + ar9300RateSize,
14821 +};
14822 +
14823 +
14824 +struct eepFlags {
14825 + u8 opFlags;
14826 + u8 eepMisc;
14827 +} __packed;
14828 +
14829 +enum CompressAlgorithm {
14830 + _CompressNone = 0,
14831 + _CompressLzma,
14832 + _CompressPairs,
14833 + _CompressBlock,
14834 + _Compress4,
14835 + _Compress5,
14836 + _Compress6,
14837 + _Compress7,
14838 +};
14839 +
14840 +struct ar9300_base_eep_hdr {
14841 + u16 regDmn[2];
14842 + /* 4 bits tx and 4 bits rx */
14843 + u8 txrxMask;
14844 + struct eepFlags opCapFlags;
14845 + u8 rfSilent;
14846 + u8 blueToothOptions;
14847 + u8 deviceCap;
14848 + /* takes lower byte in eeprom location */
14849 + u8 deviceType;
14850 + /* offset in dB to be added to beginning
14851 + * of pdadc table in calibration
14852 + */
14853 + int8_t pwrTableOffset;
14854 + u8 params_for_tuning_caps[2];
14855 + /*
14856 + * bit0 - enable tx temp comp
14857 + * bit1 - enable tx volt comp
14858 + * bit2 - enable fastClock - default to 1
14859 + * bit3 - enable doubling - default to 1
14860 + * bit4 - enable internal regulator - default to 1
14861 + */
14862 + u8 featureEnable;
14863 + /* misc flags: bit0 - turn down drivestrength */
14864 + u8 miscConfiguration;
14865 + u8 eepromWriteEnableGpio;
14866 + u8 wlanDisableGpio;
14867 + u8 wlanLedGpio;
14868 + u8 rxBandSelectGpio;
14869 + u8 txrxgain;
14870 + /* SW controlled internal regulator fields */
14871 + u32 swreg;
14872 +} __packed;
14873 +
14874 +struct ar9300_modal_eep_header {
14875 + /* 4 idle, t1, t2, b (4 bits per setting) */
14876 + u32 antCtrlCommon;
14877 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
14878 + u32 antCtrlCommon2;
14879 + /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
14880 + u16 antCtrlChain[AR9300_MAX_CHAINS];
14881 + /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
14882 + u8 xatten1DB[AR9300_MAX_CHAINS];
14883 + /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
14884 + u8 xatten1Margin[AR9300_MAX_CHAINS];
14885 + int8_t tempSlope;
14886 + int8_t voltSlope;
14887 + /* spur channels in usual fbin coding format */
14888 + u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
14889 + /* 3 Check if the register is per chain */
14890 + int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
14891 + u8 ob[AR9300_MAX_CHAINS];
14892 + u8 db_stage2[AR9300_MAX_CHAINS];
14893 + u8 db_stage3[AR9300_MAX_CHAINS];
14894 + u8 db_stage4[AR9300_MAX_CHAINS];
14895 + u8 xpaBiasLvl;
14896 + u8 txFrameToDataStart;
14897 + u8 txFrameToPaOn;
14898 + u8 txClip;
14899 + int8_t antennaGain;
14900 + u8 switchSettling;
14901 + int8_t adcDesiredSize;
14902 + u8 txEndToXpaOff;
14903 + u8 txEndToRxOn;
14904 + u8 txFrameToXpaOn;
14905 + u8 thresh62;
14906 + u8 futureModal[32];
14907 +} __packed;
14908 +
14909 +struct ar9300_cal_data_per_freq_op_loop {
14910 + int8_t refPower;
14911 + /* pdadc voltage at power measurement */
14912 + u8 voltMeas;
14913 + /* pcdac used for power measurement */
14914 + u8 tempMeas;
14915 + /* range is -60 to -127 create a mapping equation 1db resolution */
14916 + int8_t rxNoisefloorCal;
14917 + /*range is same as noisefloor */
14918 + int8_t rxNoisefloorPower;
14919 + /* temp measured when noisefloor cal was performed */
14920 + u8 rxTempMeas;
14921 +} __packed;
14922 +
14923 +struct cal_tgt_pow_legacy {
14924 + u8 tPow2x[4];
14925 +} __packed;
14926 +
14927 +struct cal_tgt_pow_ht {
14928 + u8 tPow2x[14];
14929 +} __packed;
14930 +
14931 +struct cal_ctl_edge_pwr {
14932 + u8 tPower:6,
14933 + flag:2;
14934 +} __packed;
14935 +
14936 +struct cal_ctl_data_2g {
14937 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14938 +} __packed;
14939 +
14940 +struct cal_ctl_data_5g {
14941 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
14942 +} __packed;
14943 +
14944 +struct ar9300_eeprom {
14945 + u8 eepromVersion;
14946 + u8 templateVersion;
14947 + u8 macAddr[6];
14948 + u8 custData[AR9300_CUSTOMER_DATA_SIZE];
14949 +
14950 + struct ar9300_base_eep_hdr baseEepHeader;
14951 +
14952 + struct ar9300_modal_eep_header modalHeader2G;
14953 + u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
14954 + struct ar9300_cal_data_per_freq_op_loop
14955 + calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
14956 + u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
14957 + u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
14958 + u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
14959 + u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
14960 + struct cal_tgt_pow_legacy
14961 + calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
14962 + struct cal_tgt_pow_legacy
14963 + calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
14964 + struct cal_tgt_pow_ht
14965 + calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
14966 + struct cal_tgt_pow_ht
14967 + calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
14968 + u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
14969 + u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
14970 + struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
14971 + struct ar9300_modal_eep_header modalHeader5G;
14972 + u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
14973 + struct ar9300_cal_data_per_freq_op_loop
14974 + calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
14975 + u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
14976 + u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
14977 + u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
14978 + struct cal_tgt_pow_legacy
14979 + calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
14980 + struct cal_tgt_pow_ht
14981 + calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
14982 + struct cal_tgt_pow_ht
14983 + calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
14984 + u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
14985 + u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
14986 + struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
14987 +} __packed;
14988 +
14989 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
14990 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
14991 +
14992 +#endif
14993 --- /dev/null
14994 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
14995 @@ -0,0 +1,205 @@
14996 +/*
14997 + * Copyright (c) 2008-2010 Atheros Communications Inc.
14998 + *
14999 + * Permission to use, copy, modify, and/or distribute this software for any
15000 + * purpose with or without fee is hereby granted, provided that the above
15001 + * copyright notice and this permission notice appear in all copies.
15002 + *
15003 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15004 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15005 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15006 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15007 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15008 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15009 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15010 + */
15011 +
15012 +#include "hw.h"
15013 +#include "ar9003_mac.h"
15014 +#include "ar9003_initvals.h"
15015 +
15016 +/* General hardware code for the AR9003 hadware family */
15017 +
15018 +static bool ar9003_hw_macversion_supported(u32 macversion)
15019 +{
15020 + switch (macversion) {
15021 + case AR_SREV_VERSION_9300:
15022 + return true;
15023 + default:
15024 + break;
15025 + }
15026 + return false;
15027 +}
15028 +
15029 +/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
15030 +/*
15031 + * XXX: move TX/RX gain INI to its own init_mode_gain_regs after
15032 + * ensuring it does not affect hardware bring up
15033 + */
15034 +static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
15035 +{
15036 + /* mac */
15037 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
15038 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
15039 + ar9300_2p0_mac_core,
15040 + ARRAY_SIZE(ar9300_2p0_mac_core), 2);
15041 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
15042 + ar9300_2p0_mac_postamble,
15043 + ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
15044 +
15045 + /* bb */
15046 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
15047 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
15048 + ar9300_2p0_baseband_core,
15049 + ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
15050 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
15051 + ar9300_2p0_baseband_postamble,
15052 + ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
15053 +
15054 + /* radio */
15055 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
15056 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
15057 + ar9300_2p0_radio_core,
15058 + ARRAY_SIZE(ar9300_2p0_radio_core), 2);
15059 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
15060 + ar9300_2p0_radio_postamble,
15061 + ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
15062 +
15063 + /* soc */
15064 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
15065 + ar9300_2p0_soc_preamble,
15066 + ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
15067 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
15068 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
15069 + ar9300_2p0_soc_postamble,
15070 + ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
15071 +
15072 + /* rx/tx gain */
15073 + INIT_INI_ARRAY(&ah->iniModesRxGain,
15074 + ar9300Common_rx_gain_table_2p0,
15075 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
15076 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15077 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
15078 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
15079 + 5);
15080 +
15081 + /* Load PCIE SERDES settings from INI */
15082 +
15083 + /* Awake Setting */
15084 +
15085 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
15086 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
15087 + ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
15088 + 2);
15089 +
15090 + /* Sleep Setting */
15091 +
15092 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
15093 + ar9300PciePhy_clkreq_enable_L1_2p0,
15094 + ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
15095 + 2);
15096 +
15097 + /* Fast clock modal settings */
15098 + INIT_INI_ARRAY(&ah->iniModesAdditional,
15099 + ar9300Modes_fast_clock_2p0,
15100 + ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
15101 + 3);
15102 +}
15103 +
15104 +static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
15105 +{
15106 + switch (ar9003_hw_get_tx_gain_idx(ah)) {
15107 + case 0:
15108 + default:
15109 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15110 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
15111 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
15112 + 5);
15113 + break;
15114 + case 1:
15115 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15116 + ar9300Modes_high_ob_db_tx_gain_table_2p0,
15117 + ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
15118 + 5);
15119 + break;
15120 + case 2:
15121 + INIT_INI_ARRAY(&ah->iniModesTxGain,
15122 + ar9300Modes_low_ob_db_tx_gain_table_2p0,
15123 + ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
15124 + 5);
15125 + break;
15126 + }
15127 +}
15128 +
15129 +static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
15130 +{
15131 + switch (ar9003_hw_get_rx_gain_idx(ah)) {
15132 + case 0:
15133 + default:
15134 + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
15135 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
15136 + 2);
15137 + break;
15138 + case 1:
15139 + INIT_INI_ARRAY(&ah->iniModesRxGain,
15140 + ar9300Common_wo_xlna_rx_gain_table_2p0,
15141 + ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
15142 + 2);
15143 + break;
15144 + }
15145 +}
15146 +
15147 +/* set gain table pointers according to values read from the eeprom */
15148 +static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
15149 +{
15150 + ar9003_tx_gain_table_apply(ah);
15151 + ar9003_rx_gain_table_apply(ah);
15152 +}
15153 +
15154 +/*
15155 + * Helper for ASPM support.
15156 + *
15157 + * Disable PLL when in L0s as well as receiver clock when in L1.
15158 + * This power saving option must be enabled through the SerDes.
15159 + *
15160 + * Programming the SerDes must go through the same 288 bit serial shift
15161 + * register as the other analog registers. Hence the 9 writes.
15162 + */
15163 +static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
15164 + int restore,
15165 + int power_off)
15166 +{
15167 + if (ah->is_pciexpress != true)
15168 + return;
15169 +
15170 + /* Do not touch SerDes registers */
15171 + if (ah->config.pcie_powersave_enable == 2)
15172 + return;
15173 +
15174 + /* Nothing to do on restore for 11N */
15175 + if (!restore) {
15176 + /* set bit 19 to allow forcing of pcie core into L1 state */
15177 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
15178 +
15179 + /* Several PCIe massages to ensure proper behaviour */
15180 + if (ah->config.pcie_waen)
15181 + REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
15182 + }
15183 +}
15184 +
15185 +/* Sets up the AR9003 hardware familiy callbacks */
15186 +void ar9003_hw_attach_ops(struct ath_hw *ah)
15187 +{
15188 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
15189 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
15190 +
15191 + priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
15192 + priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
15193 + priv_ops->macversion_supported = ar9003_hw_macversion_supported;
15194 +
15195 + ops->config_pci_powersave = ar9003_hw_configpcipowersave;
15196 +
15197 + ar9003_hw_attach_phy_ops(ah);
15198 + ar9003_hw_attach_calib_ops(ah);
15199 + ar9003_hw_attach_mac_ops(ah);
15200 +}
15201 --- /dev/null
15202 +++ b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
15203 @@ -0,0 +1,1793 @@
15204 +/*
15205 + * Copyright (c) 2010 Atheros Communications Inc.
15206 + *
15207 + * Permission to use, copy, modify, and/or distribute this software for any
15208 + * purpose with or without fee is hereby granted, provided that the above
15209 + * copyright notice and this permission notice appear in all copies.
15210 + *
15211 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15212 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15213 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15214 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15215 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15216 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15217 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15218 + */
15219 +
15220 +#ifndef INITVALS_9003_H
15221 +#define INITVALS_9003_H
15222 +
15223 +/* AR9003 2.0 */
15224 +
15225 +static const u32 ar9300_2p0_radio_postamble[][5] = {
15226 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15227 + {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
15228 + {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
15229 + {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
15230 + {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15231 + {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15232 + {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
15233 +};
15234 +
15235 +static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
15236 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15237 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
15238 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15239 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
15240 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
15241 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
15242 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
15243 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
15244 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
15245 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
15246 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
15247 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
15248 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
15249 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
15250 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
15251 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
15252 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
15253 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
15254 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
15255 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
15256 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
15257 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
15258 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
15259 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
15260 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
15261 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
15262 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
15263 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15264 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15265 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15266 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15267 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15268 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15269 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
15270 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15271 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
15272 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
15273 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
15274 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
15275 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
15276 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
15277 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
15278 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
15279 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
15280 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
15281 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
15282 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
15283 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
15284 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
15285 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
15286 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
15287 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
15288 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
15289 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
15290 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
15291 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
15292 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
15293 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
15294 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
15295 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15296 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15297 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15298 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15299 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15300 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15301 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
15302 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15303 + {0x00016048, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15304 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15305 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15306 + {0x00016448, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15307 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15308 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
15309 + {0x00016848, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
15310 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
15311 +};
15312 +
15313 +static const u32 ar9300Modes_fast_clock_2p0[][3] = {
15314 + /* Addr 5G_HT20 5G_HT40 */
15315 + {0x00001030, 0x00000268, 0x000004d0},
15316 + {0x00001070, 0x0000018c, 0x00000318},
15317 + {0x000010b0, 0x00000fd0, 0x00001fa0},
15318 + {0x00008014, 0x044c044c, 0x08980898},
15319 + {0x0000801c, 0x148ec02b, 0x148ec057},
15320 + {0x00008318, 0x000044c0, 0x00008980},
15321 + {0x00009e00, 0x03721821, 0x03721821},
15322 + {0x0000a230, 0x0000000b, 0x00000016},
15323 + {0x0000a254, 0x00000898, 0x00001130},
15324 +};
15325 +
15326 +static const u32 ar9300_2p0_radio_core[][2] = {
15327 + /* Addr allmodes */
15328 + {0x00016000, 0x36db6db6},
15329 + {0x00016004, 0x6db6db40},
15330 + {0x00016008, 0x73f00000},
15331 + {0x0001600c, 0x00000000},
15332 + {0x00016040, 0x7f80fff8},
15333 + {0x0001604c, 0x76d005b5},
15334 + {0x00016050, 0x556cf031},
15335 + {0x00016054, 0x43449440},
15336 + {0x00016058, 0x0c51c92c},
15337 + {0x0001605c, 0x3db7fffc},
15338 + {0x00016060, 0xfffffffc},
15339 + {0x00016064, 0x000f0278},
15340 + {0x0001606c, 0x6db60000},
15341 + {0x00016080, 0x00000000},
15342 + {0x00016084, 0x0e48048c},
15343 + {0x00016088, 0x54214514},
15344 + {0x0001608c, 0x119f481e},
15345 + {0x00016090, 0x24926490},
15346 + {0x00016098, 0xd2888888},
15347 + {0x000160a0, 0x0a108ffe},
15348 + {0x000160a4, 0x812fc370},
15349 + {0x000160a8, 0x423c8000},
15350 + {0x000160b4, 0x92480080},
15351 + {0x000160c0, 0x00adb6d0},
15352 + {0x000160c4, 0x6db6db60},
15353 + {0x000160c8, 0x6db6db6c},
15354 + {0x000160cc, 0x01e6c000},
15355 + {0x00016100, 0x3fffbe01},
15356 + {0x00016104, 0xfff80000},
15357 + {0x00016108, 0x00080010},
15358 + {0x00016140, 0x10804008},
15359 + {0x00016144, 0x02084080},
15360 + {0x00016148, 0x00000000},
15361 + {0x00016280, 0x058a0001},
15362 + {0x00016284, 0x3d840208},
15363 + {0x00016288, 0x01a20408},
15364 + {0x0001628c, 0x00038c07},
15365 + {0x00016290, 0x40000004},
15366 + {0x00016294, 0x458aa14f},
15367 + {0x00016380, 0x00000000},
15368 + {0x00016384, 0x00000000},
15369 + {0x00016388, 0x00800700},
15370 + {0x0001638c, 0x00800700},
15371 + {0x00016390, 0x00800700},
15372 + {0x00016394, 0x00000000},
15373 + {0x00016398, 0x00000000},
15374 + {0x0001639c, 0x00000000},
15375 + {0x000163a0, 0x00000001},
15376 + {0x000163a4, 0x00000001},
15377 + {0x000163a8, 0x00000000},
15378 + {0x000163ac, 0x00000000},
15379 + {0x000163b0, 0x00000000},
15380 + {0x000163b4, 0x00000000},
15381 + {0x000163b8, 0x00000000},
15382 + {0x000163bc, 0x00000000},
15383 + {0x000163c0, 0x000000a0},
15384 + {0x000163c4, 0x000c0000},
15385 + {0x000163c8, 0x14021402},
15386 + {0x000163cc, 0x00001402},
15387 + {0x000163d0, 0x00000000},
15388 + {0x000163d4, 0x00000000},
15389 + {0x00016400, 0x36db6db6},
15390 + {0x00016404, 0x6db6db40},
15391 + {0x00016408, 0x73f00000},
15392 + {0x0001640c, 0x00000000},
15393 + {0x00016440, 0x7f80fff8},
15394 + {0x0001644c, 0x76d005b5},
15395 + {0x00016450, 0x556cf031},
15396 + {0x00016454, 0x43449440},
15397 + {0x00016458, 0x0c51c92c},
15398 + {0x0001645c, 0x3db7fffc},
15399 + {0x00016460, 0xfffffffc},
15400 + {0x00016464, 0x000f0278},
15401 + {0x0001646c, 0x6db60000},
15402 + {0x00016500, 0x3fffbe01},
15403 + {0x00016504, 0xfff80000},
15404 + {0x00016508, 0x00080010},
15405 + {0x00016540, 0x10804008},
15406 + {0x00016544, 0x02084080},
15407 + {0x00016548, 0x00000000},
15408 + {0x00016780, 0x00000000},
15409 + {0x00016784, 0x00000000},
15410 + {0x00016788, 0x00800700},
15411 + {0x0001678c, 0x00800700},
15412 + {0x00016790, 0x00800700},
15413 + {0x00016794, 0x00000000},
15414 + {0x00016798, 0x00000000},
15415 + {0x0001679c, 0x00000000},
15416 + {0x000167a0, 0x00000001},
15417 + {0x000167a4, 0x00000001},
15418 + {0x000167a8, 0x00000000},
15419 + {0x000167ac, 0x00000000},
15420 + {0x000167b0, 0x00000000},
15421 + {0x000167b4, 0x00000000},
15422 + {0x000167b8, 0x00000000},
15423 + {0x000167bc, 0x00000000},
15424 + {0x000167c0, 0x000000a0},
15425 + {0x000167c4, 0x000c0000},
15426 + {0x000167c8, 0x14021402},
15427 + {0x000167cc, 0x00001402},
15428 + {0x000167d0, 0x00000000},
15429 + {0x000167d4, 0x00000000},
15430 + {0x00016800, 0x36db6db6},
15431 + {0x00016804, 0x6db6db40},
15432 + {0x00016808, 0x73f00000},
15433 + {0x0001680c, 0x00000000},
15434 + {0x00016840, 0x7f80fff8},
15435 + {0x0001684c, 0x76d005b5},
15436 + {0x00016850, 0x556cf031},
15437 + {0x00016854, 0x43449440},
15438 + {0x00016858, 0x0c51c92c},
15439 + {0x0001685c, 0x3db7fffc},
15440 + {0x00016860, 0xfffffffc},
15441 + {0x00016864, 0x000f0278},
15442 + {0x0001686c, 0x6db60000},
15443 + {0x00016900, 0x3fffbe01},
15444 + {0x00016904, 0xfff80000},
15445 + {0x00016908, 0x00080010},
15446 + {0x00016940, 0x10804008},
15447 + {0x00016944, 0x02084080},
15448 + {0x00016948, 0x00000000},
15449 + {0x00016b80, 0x00000000},
15450 + {0x00016b84, 0x00000000},
15451 + {0x00016b88, 0x00800700},
15452 + {0x00016b8c, 0x00800700},
15453 + {0x00016b90, 0x00800700},
15454 + {0x00016b94, 0x00000000},
15455 + {0x00016b98, 0x00000000},
15456 + {0x00016b9c, 0x00000000},
15457 + {0x00016ba0, 0x00000001},
15458 + {0x00016ba4, 0x00000001},
15459 + {0x00016ba8, 0x00000000},
15460 + {0x00016bac, 0x00000000},
15461 + {0x00016bb0, 0x00000000},
15462 + {0x00016bb4, 0x00000000},
15463 + {0x00016bb8, 0x00000000},
15464 + {0x00016bbc, 0x00000000},
15465 + {0x00016bc0, 0x000000a0},
15466 + {0x00016bc4, 0x000c0000},
15467 + {0x00016bc8, 0x14021402},
15468 + {0x00016bcc, 0x00001402},
15469 + {0x00016bd0, 0x00000000},
15470 + {0x00016bd4, 0x00000000},
15471 +};
15472 +
15473 +static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
15474 + /* Addr allmodes */
15475 + {0x0000a000, 0x02000101},
15476 + {0x0000a004, 0x02000102},
15477 + {0x0000a008, 0x02000103},
15478 + {0x0000a00c, 0x02000104},
15479 + {0x0000a010, 0x02000200},
15480 + {0x0000a014, 0x02000201},
15481 + {0x0000a018, 0x02000202},
15482 + {0x0000a01c, 0x02000203},
15483 + {0x0000a020, 0x02000204},
15484 + {0x0000a024, 0x02000205},
15485 + {0x0000a028, 0x02000208},
15486 + {0x0000a02c, 0x02000302},
15487 + {0x0000a030, 0x02000303},
15488 + {0x0000a034, 0x02000304},
15489 + {0x0000a038, 0x02000400},
15490 + {0x0000a03c, 0x02010300},
15491 + {0x0000a040, 0x02010301},
15492 + {0x0000a044, 0x02010302},
15493 + {0x0000a048, 0x02000500},
15494 + {0x0000a04c, 0x02010400},
15495 + {0x0000a050, 0x02020300},
15496 + {0x0000a054, 0x02020301},
15497 + {0x0000a058, 0x02020302},
15498 + {0x0000a05c, 0x02020303},
15499 + {0x0000a060, 0x02020400},
15500 + {0x0000a064, 0x02030300},
15501 + {0x0000a068, 0x02030301},
15502 + {0x0000a06c, 0x02030302},
15503 + {0x0000a070, 0x02030303},
15504 + {0x0000a074, 0x02030400},
15505 + {0x0000a078, 0x02040300},
15506 + {0x0000a07c, 0x02040301},
15507 + {0x0000a080, 0x02040302},
15508 + {0x0000a084, 0x02040303},
15509 + {0x0000a088, 0x02030500},
15510 + {0x0000a08c, 0x02040400},
15511 + {0x0000a090, 0x02050203},
15512 + {0x0000a094, 0x02050204},
15513 + {0x0000a098, 0x02050205},
15514 + {0x0000a09c, 0x02040500},
15515 + {0x0000a0a0, 0x02050301},
15516 + {0x0000a0a4, 0x02050302},
15517 + {0x0000a0a8, 0x02050303},
15518 + {0x0000a0ac, 0x02050400},
15519 + {0x0000a0b0, 0x02050401},
15520 + {0x0000a0b4, 0x02050402},
15521 + {0x0000a0b8, 0x02050403},
15522 + {0x0000a0bc, 0x02050500},
15523 + {0x0000a0c0, 0x02050501},
15524 + {0x0000a0c4, 0x02050502},
15525 + {0x0000a0c8, 0x02050503},
15526 + {0x0000a0cc, 0x02050504},
15527 + {0x0000a0d0, 0x02050600},
15528 + {0x0000a0d4, 0x02050601},
15529 + {0x0000a0d8, 0x02050602},
15530 + {0x0000a0dc, 0x02050603},
15531 + {0x0000a0e0, 0x02050604},
15532 + {0x0000a0e4, 0x02050700},
15533 + {0x0000a0e8, 0x02050701},
15534 + {0x0000a0ec, 0x02050702},
15535 + {0x0000a0f0, 0x02050703},
15536 + {0x0000a0f4, 0x02050704},
15537 + {0x0000a0f8, 0x02050705},
15538 + {0x0000a0fc, 0x02050708},
15539 + {0x0000a100, 0x02050709},
15540 + {0x0000a104, 0x0205070a},
15541 + {0x0000a108, 0x0205070b},
15542 + {0x0000a10c, 0x0205070c},
15543 + {0x0000a110, 0x0205070d},
15544 + {0x0000a114, 0x02050710},
15545 + {0x0000a118, 0x02050711},
15546 + {0x0000a11c, 0x02050712},
15547 + {0x0000a120, 0x02050713},
15548 + {0x0000a124, 0x02050714},
15549 + {0x0000a128, 0x02050715},
15550 + {0x0000a12c, 0x02050730},
15551 + {0x0000a130, 0x02050731},
15552 + {0x0000a134, 0x02050732},
15553 + {0x0000a138, 0x02050733},
15554 + {0x0000a13c, 0x02050734},
15555 + {0x0000a140, 0x02050735},
15556 + {0x0000a144, 0x02050750},
15557 + {0x0000a148, 0x02050751},
15558 + {0x0000a14c, 0x02050752},
15559 + {0x0000a150, 0x02050753},
15560 + {0x0000a154, 0x02050754},
15561 + {0x0000a158, 0x02050755},
15562 + {0x0000a15c, 0x02050770},
15563 + {0x0000a160, 0x02050771},
15564 + {0x0000a164, 0x02050772},
15565 + {0x0000a168, 0x02050773},
15566 + {0x0000a16c, 0x02050774},
15567 + {0x0000a170, 0x02050775},
15568 + {0x0000a174, 0x00000776},
15569 + {0x0000a178, 0x00000776},
15570 + {0x0000a17c, 0x00000776},
15571 + {0x0000a180, 0x00000776},
15572 + {0x0000a184, 0x00000776},
15573 + {0x0000a188, 0x00000776},
15574 + {0x0000a18c, 0x00000776},
15575 + {0x0000a190, 0x00000776},
15576 + {0x0000a194, 0x00000776},
15577 + {0x0000a198, 0x00000776},
15578 + {0x0000a19c, 0x00000776},
15579 + {0x0000a1a0, 0x00000776},
15580 + {0x0000a1a4, 0x00000776},
15581 + {0x0000a1a8, 0x00000776},
15582 + {0x0000a1ac, 0x00000776},
15583 + {0x0000a1b0, 0x00000776},
15584 + {0x0000a1b4, 0x00000776},
15585 + {0x0000a1b8, 0x00000776},
15586 + {0x0000a1bc, 0x00000776},
15587 + {0x0000a1c0, 0x00000776},
15588 + {0x0000a1c4, 0x00000776},
15589 + {0x0000a1c8, 0x00000776},
15590 + {0x0000a1cc, 0x00000776},
15591 + {0x0000a1d0, 0x00000776},
15592 + {0x0000a1d4, 0x00000776},
15593 + {0x0000a1d8, 0x00000776},
15594 + {0x0000a1dc, 0x00000776},
15595 + {0x0000a1e0, 0x00000776},
15596 + {0x0000a1e4, 0x00000776},
15597 + {0x0000a1e8, 0x00000776},
15598 + {0x0000a1ec, 0x00000776},
15599 + {0x0000a1f0, 0x00000776},
15600 + {0x0000a1f4, 0x00000776},
15601 + {0x0000a1f8, 0x00000776},
15602 + {0x0000a1fc, 0x00000776},
15603 + {0x0000b000, 0x02000101},
15604 + {0x0000b004, 0x02000102},
15605 + {0x0000b008, 0x02000103},
15606 + {0x0000b00c, 0x02000104},
15607 + {0x0000b010, 0x02000200},
15608 + {0x0000b014, 0x02000201},
15609 + {0x0000b018, 0x02000202},
15610 + {0x0000b01c, 0x02000203},
15611 + {0x0000b020, 0x02000204},
15612 + {0x0000b024, 0x02000205},
15613 + {0x0000b028, 0x02000208},
15614 + {0x0000b02c, 0x02000302},
15615 + {0x0000b030, 0x02000303},
15616 + {0x0000b034, 0x02000304},
15617 + {0x0000b038, 0x02000400},
15618 + {0x0000b03c, 0x02010300},
15619 + {0x0000b040, 0x02010301},
15620 + {0x0000b044, 0x02010302},
15621 + {0x0000b048, 0x02000500},
15622 + {0x0000b04c, 0x02010400},
15623 + {0x0000b050, 0x02020300},
15624 + {0x0000b054, 0x02020301},
15625 + {0x0000b058, 0x02020302},
15626 + {0x0000b05c, 0x02020303},
15627 + {0x0000b060, 0x02020400},
15628 + {0x0000b064, 0x02030300},
15629 + {0x0000b068, 0x02030301},
15630 + {0x0000b06c, 0x02030302},
15631 + {0x0000b070, 0x02030303},
15632 + {0x0000b074, 0x02030400},
15633 + {0x0000b078, 0x02040300},
15634 + {0x0000b07c, 0x02040301},
15635 + {0x0000b080, 0x02040302},
15636 + {0x0000b084, 0x02040303},
15637 + {0x0000b088, 0x02030500},
15638 + {0x0000b08c, 0x02040400},
15639 + {0x0000b090, 0x02050203},
15640 + {0x0000b094, 0x02050204},
15641 + {0x0000b098, 0x02050205},
15642 + {0x0000b09c, 0x02040500},
15643 + {0x0000b0a0, 0x02050301},
15644 + {0x0000b0a4, 0x02050302},
15645 + {0x0000b0a8, 0x02050303},
15646 + {0x0000b0ac, 0x02050400},
15647 + {0x0000b0b0, 0x02050401},
15648 + {0x0000b0b4, 0x02050402},
15649 + {0x0000b0b8, 0x02050403},
15650 + {0x0000b0bc, 0x02050500},
15651 + {0x0000b0c0, 0x02050501},
15652 + {0x0000b0c4, 0x02050502},
15653 + {0x0000b0c8, 0x02050503},
15654 + {0x0000b0cc, 0x02050504},
15655 + {0x0000b0d0, 0x02050600},
15656 + {0x0000b0d4, 0x02050601},
15657 + {0x0000b0d8, 0x02050602},
15658 + {0x0000b0dc, 0x02050603},
15659 + {0x0000b0e0, 0x02050604},
15660 + {0x0000b0e4, 0x02050700},
15661 + {0x0000b0e8, 0x02050701},
15662 + {0x0000b0ec, 0x02050702},
15663 + {0x0000b0f0, 0x02050703},
15664 + {0x0000b0f4, 0x02050704},
15665 + {0x0000b0f8, 0x02050705},
15666 + {0x0000b0fc, 0x02050708},
15667 + {0x0000b100, 0x02050709},
15668 + {0x0000b104, 0x0205070a},
15669 + {0x0000b108, 0x0205070b},
15670 + {0x0000b10c, 0x0205070c},
15671 + {0x0000b110, 0x0205070d},
15672 + {0x0000b114, 0x02050710},
15673 + {0x0000b118, 0x02050711},
15674 + {0x0000b11c, 0x02050712},
15675 + {0x0000b120, 0x02050713},
15676 + {0x0000b124, 0x02050714},
15677 + {0x0000b128, 0x02050715},
15678 + {0x0000b12c, 0x02050730},
15679 + {0x0000b130, 0x02050731},
15680 + {0x0000b134, 0x02050732},
15681 + {0x0000b138, 0x02050733},
15682 + {0x0000b13c, 0x02050734},
15683 + {0x0000b140, 0x02050735},
15684 + {0x0000b144, 0x02050750},
15685 + {0x0000b148, 0x02050751},
15686 + {0x0000b14c, 0x02050752},
15687 + {0x0000b150, 0x02050753},
15688 + {0x0000b154, 0x02050754},
15689 + {0x0000b158, 0x02050755},
15690 + {0x0000b15c, 0x02050770},
15691 + {0x0000b160, 0x02050771},
15692 + {0x0000b164, 0x02050772},
15693 + {0x0000b168, 0x02050773},
15694 + {0x0000b16c, 0x02050774},
15695 + {0x0000b170, 0x02050775},
15696 + {0x0000b174, 0x00000776},
15697 + {0x0000b178, 0x00000776},
15698 + {0x0000b17c, 0x00000776},
15699 + {0x0000b180, 0x00000776},
15700 + {0x0000b184, 0x00000776},
15701 + {0x0000b188, 0x00000776},
15702 + {0x0000b18c, 0x00000776},
15703 + {0x0000b190, 0x00000776},
15704 + {0x0000b194, 0x00000776},
15705 + {0x0000b198, 0x00000776},
15706 + {0x0000b19c, 0x00000776},
15707 + {0x0000b1a0, 0x00000776},
15708 + {0x0000b1a4, 0x00000776},
15709 + {0x0000b1a8, 0x00000776},
15710 + {0x0000b1ac, 0x00000776},
15711 + {0x0000b1b0, 0x00000776},
15712 + {0x0000b1b4, 0x00000776},
15713 + {0x0000b1b8, 0x00000776},
15714 + {0x0000b1bc, 0x00000776},
15715 + {0x0000b1c0, 0x00000776},
15716 + {0x0000b1c4, 0x00000776},
15717 + {0x0000b1c8, 0x00000776},
15718 + {0x0000b1cc, 0x00000776},
15719 + {0x0000b1d0, 0x00000776},
15720 + {0x0000b1d4, 0x00000776},
15721 + {0x0000b1d8, 0x00000776},
15722 + {0x0000b1dc, 0x00000776},
15723 + {0x0000b1e0, 0x00000776},
15724 + {0x0000b1e4, 0x00000776},
15725 + {0x0000b1e8, 0x00000776},
15726 + {0x0000b1ec, 0x00000776},
15727 + {0x0000b1f0, 0x00000776},
15728 + {0x0000b1f4, 0x00000776},
15729 + {0x0000b1f8, 0x00000776},
15730 + {0x0000b1fc, 0x00000776},
15731 +};
15732 +
15733 +static const u32 ar9300_2p0_mac_postamble[][5] = {
15734 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15735 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
15736 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
15737 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
15738 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
15739 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
15740 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
15741 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
15742 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
15743 +};
15744 +
15745 +static const u32 ar9300_2p0_soc_postamble[][5] = {
15746 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15747 + {0x00007010, 0x00000023, 0x00000023, 0x00000022, 0x00000022},
15748 +};
15749 +
15750 +static const u32 ar9200_merlin_2p0_radio_core[][2] = {
15751 + /* Addr common */
15752 + {0x00007800, 0x00040000},
15753 + {0x00007804, 0xdb005012},
15754 + {0x00007808, 0x04924914},
15755 + {0x0000780c, 0x21084210},
15756 + {0x00007810, 0x6d801300},
15757 + {0x00007814, 0x0019beff},
15758 + {0x00007818, 0x07e41000},
15759 + {0x0000781c, 0x00392000},
15760 + {0x00007820, 0x92592480},
15761 + {0x00007824, 0x00040000},
15762 + {0x00007828, 0xdb005012},
15763 + {0x0000782c, 0x04924914},
15764 + {0x00007830, 0x21084210},
15765 + {0x00007834, 0x6d801300},
15766 + {0x00007838, 0x0019beff},
15767 + {0x0000783c, 0x07e40000},
15768 + {0x00007840, 0x00392000},
15769 + {0x00007844, 0x92592480},
15770 + {0x00007848, 0x00100000},
15771 + {0x0000784c, 0x773f0567},
15772 + {0x00007850, 0x54214514},
15773 + {0x00007854, 0x12035828},
15774 + {0x00007858, 0x92592692},
15775 + {0x0000785c, 0x00000000},
15776 + {0x00007860, 0x56400000},
15777 + {0x00007864, 0x0a8e370e},
15778 + {0x00007868, 0xc0102850},
15779 + {0x0000786c, 0x812d4000},
15780 + {0x00007870, 0x807ec400},
15781 + {0x00007874, 0x001b6db0},
15782 + {0x00007878, 0x00376b63},
15783 + {0x0000787c, 0x06db6db6},
15784 + {0x00007880, 0x006d8000},
15785 + {0x00007884, 0xffeffffe},
15786 + {0x00007888, 0xffeffffe},
15787 + {0x0000788c, 0x00010000},
15788 + {0x00007890, 0x02060aeb},
15789 + {0x00007894, 0x5a108000},
15790 +};
15791 +
15792 +static const u32 ar9300_2p0_baseband_postamble[][5] = {
15793 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
15794 + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
15795 + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
15796 + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
15797 + {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
15798 + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
15799 + {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
15800 + {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
15801 + {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
15802 + {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
15803 + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
15804 + {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
15805 + {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
15806 + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15807 + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
15808 + {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
15809 + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
15810 + {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
15811 + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
15812 + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
15813 + {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
15814 + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
15815 + {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
15816 + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
15817 + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
15818 + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
15819 + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
15820 + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
15821 + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
15822 + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
15823 + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
15824 + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15825 + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
15826 + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
15827 + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
15828 + {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
15829 + {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
15830 + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15831 + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15832 + {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15833 + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15834 + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15835 + {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
15836 + {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15837 + {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15838 + {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
15839 + {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
15840 + {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
15841 + {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
15842 + {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
15843 +};
15844 +
15845 +static const u32 ar9300_2p0_baseband_core[][2] = {
15846 + /* Addr allmodes */
15847 + {0x00009800, 0xafe68e30},
15848 + {0x00009804, 0xfd14e000},
15849 + {0x00009808, 0x9c0a9f6b},
15850 + {0x0000980c, 0x04900000},
15851 + {0x00009814, 0x9280c00a},
15852 + {0x00009818, 0x00000000},
15853 + {0x0000981c, 0x00020028},
15854 + {0x00009834, 0x5f3ca3de},
15855 + {0x00009838, 0x0108ecff},
15856 + {0x0000983c, 0x14750600},
15857 + {0x00009880, 0x201fff00},
15858 + {0x00009884, 0x00001042},
15859 + {0x000098a4, 0x00200400},
15860 + {0x000098b0, 0x52440bbe},
15861 + {0x000098d0, 0x004b6a8e},
15862 + {0x000098d4, 0x00000820},
15863 + {0x000098dc, 0x00000000},
15864 + {0x000098f0, 0x00000000},
15865 + {0x000098f4, 0x00000000},
15866 + {0x00009c04, 0xff55ff55},
15867 + {0x00009c08, 0x0320ff55},
15868 + {0x00009c0c, 0x00000000},
15869 + {0x00009c10, 0x00000000},
15870 + {0x00009c14, 0x00046384},
15871 + {0x00009c18, 0x05b6b440},
15872 + {0x00009c1c, 0x00b6b440},
15873 + {0x00009d00, 0xc080a333},
15874 + {0x00009d04, 0x40206c10},
15875 + {0x00009d08, 0x009c4060},
15876 + {0x00009d0c, 0x9883800a},
15877 + {0x00009d10, 0x01834061},
15878 + {0x00009d14, 0x00c0040b},
15879 + {0x00009d18, 0x00000000},
15880 + {0x00009e08, 0x0038233c},
15881 + {0x00009e24, 0x990bb515},
15882 + {0x00009e28, 0x0c6f0000},
15883 + {0x00009e30, 0x06336f77},
15884 + {0x00009e34, 0x6af6532f},
15885 + {0x00009e38, 0x0cc80c00},
15886 + {0x00009e3c, 0xcf946222},
15887 + {0x00009e40, 0x0d261820},
15888 + {0x00009e4c, 0x00001004},
15889 + {0x00009e50, 0x00ff03f1},
15890 + {0x00009e54, 0x00000000},
15891 + {0x00009fc0, 0x803e4788},
15892 + {0x00009fc4, 0x0001efb5},
15893 + {0x00009fcc, 0x40000014},
15894 + {0x00009fd0, 0x01193b93},
15895 + {0x0000a20c, 0x00000000},
15896 + {0x0000a220, 0x00000000},
15897 + {0x0000a224, 0x00000000},
15898 + {0x0000a228, 0x10002310},
15899 + {0x0000a22c, 0x01036a1e},
15900 + {0x0000a234, 0x10000fff},
15901 + {0x0000a23c, 0x00000000},
15902 + {0x0000a244, 0x0c000000},
15903 + {0x0000a2a0, 0x00000001},
15904 + {0x0000a2c0, 0x00000001},
15905 + {0x0000a2c8, 0x00000000},
15906 + {0x0000a2cc, 0x18c43433},
15907 + {0x0000a2d4, 0x00000000},
15908 + {0x0000a2dc, 0x00000000},
15909 + {0x0000a2e0, 0x00000000},
15910 + {0x0000a2e4, 0x00000000},
15911 + {0x0000a2e8, 0x00000000},
15912 + {0x0000a2ec, 0x00000000},
15913 + {0x0000a2f0, 0x00000000},
15914 + {0x0000a2f4, 0x00000000},
15915 + {0x0000a2f8, 0x00000000},
15916 + {0x0000a344, 0x00000000},
15917 + {0x0000a34c, 0x00000000},
15918 + {0x0000a350, 0x0000a000},
15919 + {0x0000a364, 0x00000000},
15920 + {0x0000a370, 0x00000000},
15921 + {0x0000a390, 0x00000001},
15922 + {0x0000a394, 0x00000444},
15923 + {0x0000a398, 0x001f0e0f},
15924 + {0x0000a39c, 0x0075393f},
15925 + {0x0000a3a0, 0xb79f6427},
15926 + {0x0000a3a4, 0x00000000},
15927 + {0x0000a3a8, 0xaaaaaaaa},
15928 + {0x0000a3ac, 0x3c466478},
15929 + {0x0000a3c0, 0x20202020},
15930 + {0x0000a3c4, 0x22222220},
15931 + {0x0000a3c8, 0x20200020},
15932 + {0x0000a3cc, 0x20202020},
15933 + {0x0000a3d0, 0x20202020},
15934 + {0x0000a3d4, 0x20202020},
15935 + {0x0000a3d8, 0x20202020},
15936 + {0x0000a3dc, 0x20202020},
15937 + {0x0000a3e0, 0x20202020},
15938 + {0x0000a3e4, 0x20202020},
15939 + {0x0000a3e8, 0x20202020},
15940 + {0x0000a3ec, 0x20202020},
15941 + {0x0000a3f0, 0x00000000},
15942 + {0x0000a3f4, 0x00000246},
15943 + {0x0000a3f8, 0x0cdbd380},
15944 + {0x0000a3fc, 0x000f0f01},
15945 + {0x0000a400, 0x8fa91f01},
15946 + {0x0000a404, 0x00000000},
15947 + {0x0000a408, 0x0e79e5c6},
15948 + {0x0000a40c, 0x00820820},
15949 + {0x0000a414, 0x1ce739ce},
15950 + {0x0000a418, 0x7d001dce},
15951 + {0x0000a41c, 0x1ce739ce},
15952 + {0x0000a420, 0x000001ce},
15953 + {0x0000a424, 0x1ce739ce},
15954 + {0x0000a428, 0x000001ce},
15955 + {0x0000a42c, 0x1ce739ce},
15956 + {0x0000a430, 0x1ce739ce},
15957 + {0x0000a434, 0x00000000},
15958 + {0x0000a438, 0x00001801},
15959 + {0x0000a43c, 0x00000000},
15960 + {0x0000a440, 0x00000000},
15961 + {0x0000a444, 0x00000000},
15962 + {0x0000a448, 0x07000080},
15963 + {0x0000a44c, 0x00000001},
15964 + {0x0000a450, 0x00010000},
15965 + {0x0000a458, 0x00000000},
15966 + {0x0000a600, 0x00000000},
15967 + {0x0000a604, 0x00000000},
15968 + {0x0000a608, 0x00000000},
15969 + {0x0000a60c, 0x00000000},
15970 + {0x0000a610, 0x00000000},
15971 + {0x0000a614, 0x00000000},
15972 + {0x0000a618, 0x00000000},
15973 + {0x0000a61c, 0x00000000},
15974 + {0x0000a620, 0x00000000},
15975 + {0x0000a624, 0x00000000},
15976 + {0x0000a628, 0x00000000},
15977 + {0x0000a62c, 0x00000000},
15978 + {0x0000a630, 0x00000000},
15979 + {0x0000a634, 0x00000000},
15980 + {0x0000a638, 0x00000000},
15981 + {0x0000a63c, 0x00000000},
15982 + {0x0000a640, 0x00000000},
15983 + {0x0000a644, 0x3ffd9d74},
15984 + {0x0000a648, 0x0048060a},
15985 + {0x0000a64c, 0x00000637},
15986 + {0x0000a670, 0x03020100},
15987 + {0x0000a674, 0x09080504},
15988 + {0x0000a678, 0x0d0c0b0a},
15989 + {0x0000a67c, 0x13121110},
15990 + {0x0000a680, 0x31301514},
15991 + {0x0000a684, 0x35343332},
15992 + {0x0000a688, 0x00000036},
15993 + {0x0000a690, 0x00000838},
15994 + {0x0000a7c0, 0x00000000},
15995 + {0x0000a7c4, 0xfffffffc},
15996 + {0x0000a7c8, 0x00000000},
15997 + {0x0000a7cc, 0x00000000},
15998 + {0x0000a7d0, 0x00000000},
15999 + {0x0000a7d4, 0x00000004},
16000 + {0x0000a7dc, 0x00000001},
16001 + {0x0000a8d0, 0x004b6a8e},
16002 + {0x0000a8d4, 0x00000820},
16003 + {0x0000a8dc, 0x00000000},
16004 + {0x0000a8f0, 0x00000000},
16005 + {0x0000a8f4, 0x00000000},
16006 + {0x0000b2d0, 0x00000080},
16007 + {0x0000b2d4, 0x00000000},
16008 + {0x0000b2dc, 0x00000000},
16009 + {0x0000b2e0, 0x00000000},
16010 + {0x0000b2e4, 0x00000000},
16011 + {0x0000b2e8, 0x00000000},
16012 + {0x0000b2ec, 0x00000000},
16013 + {0x0000b2f0, 0x00000000},
16014 + {0x0000b2f4, 0x00000000},
16015 + {0x0000b2f8, 0x00000000},
16016 + {0x0000b408, 0x0e79e5c0},
16017 + {0x0000b40c, 0x00820820},
16018 + {0x0000b420, 0x00000000},
16019 + {0x0000b8d0, 0x004b6a8e},
16020 + {0x0000b8d4, 0x00000820},
16021 + {0x0000b8dc, 0x00000000},
16022 + {0x0000b8f0, 0x00000000},
16023 + {0x0000b8f4, 0x00000000},
16024 + {0x0000c2d0, 0x00000080},
16025 + {0x0000c2d4, 0x00000000},
16026 + {0x0000c2dc, 0x00000000},
16027 + {0x0000c2e0, 0x00000000},
16028 + {0x0000c2e4, 0x00000000},
16029 + {0x0000c2e8, 0x00000000},
16030 + {0x0000c2ec, 0x00000000},
16031 + {0x0000c2f0, 0x00000000},
16032 + {0x0000c2f4, 0x00000000},
16033 + {0x0000c2f8, 0x00000000},
16034 + {0x0000c408, 0x0e79e5c0},
16035 + {0x0000c40c, 0x00820820},
16036 + {0x0000c420, 0x00000000},
16037 +};
16038 +
16039 +static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
16040 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
16041 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
16042 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
16043 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
16044 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
16045 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
16046 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
16047 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
16048 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
16049 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
16050 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
16051 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
16052 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
16053 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
16054 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
16055 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
16056 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
16057 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
16058 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
16059 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
16060 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
16061 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
16062 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
16063 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
16064 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
16065 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
16066 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
16067 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16068 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16069 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16070 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16071 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16072 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16073 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16074 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
16075 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
16076 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
16077 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
16078 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
16079 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
16080 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
16081 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
16082 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
16083 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
16084 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
16085 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
16086 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
16087 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
16088 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
16089 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
16090 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
16091 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
16092 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
16093 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
16094 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
16095 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
16096 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
16097 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
16098 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
16099 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16100 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16101 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16102 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16103 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16104 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16105 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16106 + {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16107 + {0x00016048, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16108 + {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16109 + {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16110 + {0x00016448, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16111 + {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16112 + {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
16113 + {0x00016848, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
16114 + {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
16115 +};
16116 +
16117 +static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
16118 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
16119 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
16120 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
16121 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
16122 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
16123 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
16124 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
16125 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
16126 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
16127 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
16128 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
16129 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
16130 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
16131 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
16132 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
16133 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
16134 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
16135 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
16136 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
16137 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
16138 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
16139 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
16140 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
16141 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
16142 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
16143 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
16144 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
16145 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16146 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16147 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16148 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16149 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16150 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16151 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
16152 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
16153 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
16154 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
16155 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
16156 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
16157 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
16158 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
16159 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
16160 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
16161 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
16162 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
16163 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
16164 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
16165 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
16166 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
16167 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
16168 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
16169 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
16170 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
16171 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
16172 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
16173 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
16174 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
16175 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
16176 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
16177 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16178 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16179 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16180 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16181 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16182 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16183 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
16184 + {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16185 + {0x00016048, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16186 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16187 + {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16188 + {0x00016448, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16189 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16190 + {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
16191 + {0x00016848, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
16192 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16193 +};
16194 +
16195 +static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
16196 + /* Addr allmodes */
16197 + {0x0000a000, 0x00010000},
16198 + {0x0000a004, 0x00030002},
16199 + {0x0000a008, 0x00050004},
16200 + {0x0000a00c, 0x00810080},
16201 + {0x0000a010, 0x01800082},
16202 + {0x0000a014, 0x01820181},
16203 + {0x0000a018, 0x01840183},
16204 + {0x0000a01c, 0x01880185},
16205 + {0x0000a020, 0x018a0189},
16206 + {0x0000a024, 0x02850284},
16207 + {0x0000a028, 0x02890288},
16208 + {0x0000a02c, 0x028b028a},
16209 + {0x0000a030, 0x028d028c},
16210 + {0x0000a034, 0x02910290},
16211 + {0x0000a038, 0x02930292},
16212 + {0x0000a03c, 0x03910390},
16213 + {0x0000a040, 0x03930392},
16214 + {0x0000a044, 0x03950394},
16215 + {0x0000a048, 0x00000396},
16216 + {0x0000a04c, 0x00000000},
16217 + {0x0000a050, 0x00000000},
16218 + {0x0000a054, 0x00000000},
16219 + {0x0000a058, 0x00000000},
16220 + {0x0000a05c, 0x00000000},
16221 + {0x0000a060, 0x00000000},
16222 + {0x0000a064, 0x00000000},
16223 + {0x0000a068, 0x00000000},
16224 + {0x0000a06c, 0x00000000},
16225 + {0x0000a070, 0x00000000},
16226 + {0x0000a074, 0x00000000},
16227 + {0x0000a078, 0x00000000},
16228 + {0x0000a07c, 0x00000000},
16229 + {0x0000a080, 0x28282828},
16230 + {0x0000a084, 0x21212128},
16231 + {0x0000a088, 0x21212121},
16232 + {0x0000a08c, 0x1c1c1c21},
16233 + {0x0000a090, 0x1c1c1c1c},
16234 + {0x0000a094, 0x17171c1c},
16235 + {0x0000a098, 0x02020212},
16236 + {0x0000a09c, 0x02020202},
16237 + {0x0000a0a0, 0x00000000},
16238 + {0x0000a0a4, 0x00000000},
16239 + {0x0000a0a8, 0x00000000},
16240 + {0x0000a0ac, 0x00000000},
16241 + {0x0000a0b0, 0x00000000},
16242 + {0x0000a0b4, 0x00000000},
16243 + {0x0000a0b8, 0x00000000},
16244 + {0x0000a0bc, 0x00000000},
16245 + {0x0000a0c0, 0x001f0000},
16246 + {0x0000a0c4, 0x011f0100},
16247 + {0x0000a0c8, 0x011d011e},
16248 + {0x0000a0cc, 0x011b011c},
16249 + {0x0000a0d0, 0x02030204},
16250 + {0x0000a0d4, 0x02010202},
16251 + {0x0000a0d8, 0x021f0200},
16252 + {0x0000a0dc, 0x021d021e},
16253 + {0x0000a0e0, 0x03010302},
16254 + {0x0000a0e4, 0x031f0300},
16255 + {0x0000a0e8, 0x0402031e},
16256 + {0x0000a0ec, 0x04000401},
16257 + {0x0000a0f0, 0x041e041f},
16258 + {0x0000a0f4, 0x05010502},
16259 + {0x0000a0f8, 0x051f0500},
16260 + {0x0000a0fc, 0x0602051e},
16261 + {0x0000a100, 0x06000601},
16262 + {0x0000a104, 0x061e061f},
16263 + {0x0000a108, 0x0703061d},
16264 + {0x0000a10c, 0x07010702},
16265 + {0x0000a110, 0x00000700},
16266 + {0x0000a114, 0x00000000},
16267 + {0x0000a118, 0x00000000},
16268 + {0x0000a11c, 0x00000000},
16269 + {0x0000a120, 0x00000000},
16270 + {0x0000a124, 0x00000000},
16271 + {0x0000a128, 0x00000000},
16272 + {0x0000a12c, 0x00000000},
16273 + {0x0000a130, 0x00000000},
16274 + {0x0000a134, 0x00000000},
16275 + {0x0000a138, 0x00000000},
16276 + {0x0000a13c, 0x00000000},
16277 + {0x0000a140, 0x001f0000},
16278 + {0x0000a144, 0x011f0100},
16279 + {0x0000a148, 0x011d011e},
16280 + {0x0000a14c, 0x011b011c},
16281 + {0x0000a150, 0x02030204},
16282 + {0x0000a154, 0x02010202},
16283 + {0x0000a158, 0x021f0200},
16284 + {0x0000a15c, 0x021d021e},
16285 + {0x0000a160, 0x03010302},
16286 + {0x0000a164, 0x031f0300},
16287 + {0x0000a168, 0x0402031e},
16288 + {0x0000a16c, 0x04000401},
16289 + {0x0000a170, 0x041e041f},
16290 + {0x0000a174, 0x05010502},
16291 + {0x0000a178, 0x051f0500},
16292 + {0x0000a17c, 0x0602051e},
16293 + {0x0000a180, 0x06000601},
16294 + {0x0000a184, 0x061e061f},
16295 + {0x0000a188, 0x0703061d},
16296 + {0x0000a18c, 0x07010702},
16297 + {0x0000a190, 0x00000700},
16298 + {0x0000a194, 0x00000000},
16299 + {0x0000a198, 0x00000000},
16300 + {0x0000a19c, 0x00000000},
16301 + {0x0000a1a0, 0x00000000},
16302 + {0x0000a1a4, 0x00000000},
16303 + {0x0000a1a8, 0x00000000},
16304 + {0x0000a1ac, 0x00000000},
16305 + {0x0000a1b0, 0x00000000},
16306 + {0x0000a1b4, 0x00000000},
16307 + {0x0000a1b8, 0x00000000},
16308 + {0x0000a1bc, 0x00000000},
16309 + {0x0000a1c0, 0x00000000},
16310 + {0x0000a1c4, 0x00000000},
16311 + {0x0000a1c8, 0x00000000},
16312 + {0x0000a1cc, 0x00000000},
16313 + {0x0000a1d0, 0x00000000},
16314 + {0x0000a1d4, 0x00000000},
16315 + {0x0000a1d8, 0x00000000},
16316 + {0x0000a1dc, 0x00000000},
16317 + {0x0000a1e0, 0x00000000},
16318 + {0x0000a1e4, 0x00000000},
16319 + {0x0000a1e8, 0x00000000},
16320 + {0x0000a1ec, 0x00000000},
16321 + {0x0000a1f0, 0x00000396},
16322 + {0x0000a1f4, 0x00000396},
16323 + {0x0000a1f8, 0x00000396},
16324 + {0x0000a1fc, 0x00000196},
16325 + {0x0000b000, 0x00010000},
16326 + {0x0000b004, 0x00030002},
16327 + {0x0000b008, 0x00050004},
16328 + {0x0000b00c, 0x00810080},
16329 + {0x0000b010, 0x00830082},
16330 + {0x0000b014, 0x01810180},
16331 + {0x0000b018, 0x01830182},
16332 + {0x0000b01c, 0x01850184},
16333 + {0x0000b020, 0x02810280},
16334 + {0x0000b024, 0x02830282},
16335 + {0x0000b028, 0x02850284},
16336 + {0x0000b02c, 0x02890288},
16337 + {0x0000b030, 0x028b028a},
16338 + {0x0000b034, 0x0388028c},
16339 + {0x0000b038, 0x038a0389},
16340 + {0x0000b03c, 0x038c038b},
16341 + {0x0000b040, 0x0390038d},
16342 + {0x0000b044, 0x03920391},
16343 + {0x0000b048, 0x03940393},
16344 + {0x0000b04c, 0x03960395},
16345 + {0x0000b050, 0x00000000},
16346 + {0x0000b054, 0x00000000},
16347 + {0x0000b058, 0x00000000},
16348 + {0x0000b05c, 0x00000000},
16349 + {0x0000b060, 0x00000000},
16350 + {0x0000b064, 0x00000000},
16351 + {0x0000b068, 0x00000000},
16352 + {0x0000b06c, 0x00000000},
16353 + {0x0000b070, 0x00000000},
16354 + {0x0000b074, 0x00000000},
16355 + {0x0000b078, 0x00000000},
16356 + {0x0000b07c, 0x00000000},
16357 + {0x0000b080, 0x32323232},
16358 + {0x0000b084, 0x2f2f3232},
16359 + {0x0000b088, 0x23282a2d},
16360 + {0x0000b08c, 0x1c1e2123},
16361 + {0x0000b090, 0x14171919},
16362 + {0x0000b094, 0x0e0e1214},
16363 + {0x0000b098, 0x03050707},
16364 + {0x0000b09c, 0x00030303},
16365 + {0x0000b0a0, 0x00000000},
16366 + {0x0000b0a4, 0x00000000},
16367 + {0x0000b0a8, 0x00000000},
16368 + {0x0000b0ac, 0x00000000},
16369 + {0x0000b0b0, 0x00000000},
16370 + {0x0000b0b4, 0x00000000},
16371 + {0x0000b0b8, 0x00000000},
16372 + {0x0000b0bc, 0x00000000},
16373 + {0x0000b0c0, 0x003f0020},
16374 + {0x0000b0c4, 0x00400041},
16375 + {0x0000b0c8, 0x0140005f},
16376 + {0x0000b0cc, 0x0160015f},
16377 + {0x0000b0d0, 0x017e017f},
16378 + {0x0000b0d4, 0x02410242},
16379 + {0x0000b0d8, 0x025f0240},
16380 + {0x0000b0dc, 0x027f0260},
16381 + {0x0000b0e0, 0x0341027e},
16382 + {0x0000b0e4, 0x035f0340},
16383 + {0x0000b0e8, 0x037f0360},
16384 + {0x0000b0ec, 0x04400441},
16385 + {0x0000b0f0, 0x0460045f},
16386 + {0x0000b0f4, 0x0541047f},
16387 + {0x0000b0f8, 0x055f0540},
16388 + {0x0000b0fc, 0x057f0560},
16389 + {0x0000b100, 0x06400641},
16390 + {0x0000b104, 0x0660065f},
16391 + {0x0000b108, 0x067e067f},
16392 + {0x0000b10c, 0x07410742},
16393 + {0x0000b110, 0x075f0740},
16394 + {0x0000b114, 0x077f0760},
16395 + {0x0000b118, 0x07800781},
16396 + {0x0000b11c, 0x07a0079f},
16397 + {0x0000b120, 0x07c107bf},
16398 + {0x0000b124, 0x000007c0},
16399 + {0x0000b128, 0x00000000},
16400 + {0x0000b12c, 0x00000000},
16401 + {0x0000b130, 0x00000000},
16402 + {0x0000b134, 0x00000000},
16403 + {0x0000b138, 0x00000000},
16404 + {0x0000b13c, 0x00000000},
16405 + {0x0000b140, 0x003f0020},
16406 + {0x0000b144, 0x00400041},
16407 + {0x0000b148, 0x0140005f},
16408 + {0x0000b14c, 0x0160015f},
16409 + {0x0000b150, 0x017e017f},
16410 + {0x0000b154, 0x02410242},
16411 + {0x0000b158, 0x025f0240},
16412 + {0x0000b15c, 0x027f0260},
16413 + {0x0000b160, 0x0341027e},
16414 + {0x0000b164, 0x035f0340},
16415 + {0x0000b168, 0x037f0360},
16416 + {0x0000b16c, 0x04400441},
16417 + {0x0000b170, 0x0460045f},
16418 + {0x0000b174, 0x0541047f},
16419 + {0x0000b178, 0x055f0540},
16420 + {0x0000b17c, 0x057f0560},
16421 + {0x0000b180, 0x06400641},
16422 + {0x0000b184, 0x0660065f},
16423 + {0x0000b188, 0x067e067f},
16424 + {0x0000b18c, 0x07410742},
16425 + {0x0000b190, 0x075f0740},
16426 + {0x0000b194, 0x077f0760},
16427 + {0x0000b198, 0x07800781},
16428 + {0x0000b19c, 0x07a0079f},
16429 + {0x0000b1a0, 0x07c107bf},
16430 + {0x0000b1a4, 0x000007c0},
16431 + {0x0000b1a8, 0x00000000},
16432 + {0x0000b1ac, 0x00000000},
16433 + {0x0000b1b0, 0x00000000},
16434 + {0x0000b1b4, 0x00000000},
16435 + {0x0000b1b8, 0x00000000},
16436 + {0x0000b1bc, 0x00000000},
16437 + {0x0000b1c0, 0x00000000},
16438 + {0x0000b1c4, 0x00000000},
16439 + {0x0000b1c8, 0x00000000},
16440 + {0x0000b1cc, 0x00000000},
16441 + {0x0000b1d0, 0x00000000},
16442 + {0x0000b1d4, 0x00000000},
16443 + {0x0000b1d8, 0x00000000},
16444 + {0x0000b1dc, 0x00000000},
16445 + {0x0000b1e0, 0x00000000},
16446 + {0x0000b1e4, 0x00000000},
16447 + {0x0000b1e8, 0x00000000},
16448 + {0x0000b1ec, 0x00000000},
16449 + {0x0000b1f0, 0x00000396},
16450 + {0x0000b1f4, 0x00000396},
16451 + {0x0000b1f8, 0x00000396},
16452 + {0x0000b1fc, 0x00000196},
16453 +};
16454 +
16455 +static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
16456 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
16457 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
16458 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
16459 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
16460 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
16461 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
16462 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
16463 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
16464 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
16465 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
16466 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
16467 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
16468 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
16469 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
16470 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
16471 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
16472 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
16473 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
16474 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
16475 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
16476 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
16477 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
16478 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
16479 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
16480 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
16481 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
16482 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
16483 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16484 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16485 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16486 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16487 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16488 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16489 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
16490 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
16491 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
16492 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
16493 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
16494 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
16495 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
16496 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
16497 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
16498 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
16499 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
16500 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
16501 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
16502 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
16503 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
16504 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
16505 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
16506 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
16507 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
16508 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
16509 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
16510 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
16511 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
16512 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
16513 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
16514 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
16515 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16516 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16517 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16518 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16519 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16520 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16521 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
16522 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16523 + {0x00016048, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16524 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16525 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16526 + {0x00016448, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16527 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16528 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
16529 + {0x00016848, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
16530 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
16531 +};
16532 +
16533 +static const u32 ar9300_2p0_mac_core[][2] = {
16534 + /* Addr allmodes */
16535 + {0x00000008, 0x00000000},
16536 + {0x00000030, 0x00020085},
16537 + {0x00000034, 0x00000005},
16538 + {0x00000040, 0x00000000},
16539 + {0x00000044, 0x00000000},
16540 + {0x00000048, 0x00000008},
16541 + {0x0000004c, 0x00000010},
16542 + {0x00000050, 0x00000000},
16543 + {0x00001040, 0x002ffc0f},
16544 + {0x00001044, 0x002ffc0f},
16545 + {0x00001048, 0x002ffc0f},
16546 + {0x0000104c, 0x002ffc0f},
16547 + {0x00001050, 0x002ffc0f},
16548 + {0x00001054, 0x002ffc0f},
16549 + {0x00001058, 0x002ffc0f},
16550 + {0x0000105c, 0x002ffc0f},
16551 + {0x00001060, 0x002ffc0f},
16552 + {0x00001064, 0x002ffc0f},
16553 + {0x000010f0, 0x00000100},
16554 + {0x00001270, 0x00000000},
16555 + {0x000012b0, 0x00000000},
16556 + {0x000012f0, 0x00000000},
16557 + {0x0000143c, 0x00000000},
16558 + {0x0000147c, 0x00000000},
16559 + {0x00008000, 0x00000000},
16560 + {0x00008004, 0x00000000},
16561 + {0x00008008, 0x00000000},
16562 + {0x0000800c, 0x00000000},
16563 + {0x00008018, 0x00000000},
16564 + {0x00008020, 0x00000000},
16565 + {0x00008038, 0x00000000},
16566 + {0x0000803c, 0x00000000},
16567 + {0x00008040, 0x00000000},
16568 + {0x00008044, 0x00000000},
16569 + {0x00008048, 0x00000000},
16570 + {0x0000804c, 0xffffffff},
16571 + {0x00008054, 0x00000000},
16572 + {0x00008058, 0x00000000},
16573 + {0x0000805c, 0x000fc78f},
16574 + {0x00008060, 0x0000000f},
16575 + {0x00008064, 0x00000000},
16576 + {0x00008070, 0x00000310},
16577 + {0x00008074, 0x00000020},
16578 + {0x00008078, 0x00000000},
16579 + {0x0000809c, 0x0000000f},
16580 + {0x000080a0, 0x00000000},
16581 + {0x000080a4, 0x02ff0000},
16582 + {0x000080a8, 0x0e070605},
16583 + {0x000080ac, 0x0000000d},
16584 + {0x000080b0, 0x00000000},
16585 + {0x000080b4, 0x00000000},
16586 + {0x000080b8, 0x00000000},
16587 + {0x000080bc, 0x00000000},
16588 + {0x000080c0, 0x2a800000},
16589 + {0x000080c4, 0x06900168},
16590 + {0x000080c8, 0x13881c20},
16591 + {0x000080cc, 0x01f40000},
16592 + {0x000080d0, 0x00252500},
16593 + {0x000080d4, 0x00a00000},
16594 + {0x000080d8, 0x00400000},
16595 + {0x000080dc, 0x00000000},
16596 + {0x000080e0, 0xffffffff},
16597 + {0x000080e4, 0x0000ffff},
16598 + {0x000080e8, 0x3f3f3f3f},
16599 + {0x000080ec, 0x00000000},
16600 + {0x000080f0, 0x00000000},
16601 + {0x000080f4, 0x00000000},
16602 + {0x000080fc, 0x00020000},
16603 + {0x00008100, 0x00000000},
16604 + {0x00008108, 0x00000052},
16605 + {0x0000810c, 0x00000000},
16606 + {0x00008110, 0x00000000},
16607 + {0x00008114, 0x000007ff},
16608 + {0x00008118, 0x000000aa},
16609 + {0x0000811c, 0x00003210},
16610 + {0x00008124, 0x00000000},
16611 + {0x00008128, 0x00000000},
16612 + {0x0000812c, 0x00000000},
16613 + {0x00008130, 0x00000000},
16614 + {0x00008134, 0x00000000},
16615 + {0x00008138, 0x00000000},
16616 + {0x0000813c, 0x0000ffff},
16617 + {0x00008144, 0xffffffff},
16618 + {0x00008168, 0x00000000},
16619 + {0x0000816c, 0x00000000},
16620 + {0x00008170, 0x18486200},
16621 + {0x00008174, 0x33332210},
16622 + {0x00008178, 0x00000000},
16623 + {0x0000817c, 0x00020000},
16624 + {0x000081c0, 0x00000000},
16625 + {0x000081c4, 0x33332210},
16626 + {0x000081c8, 0x00000000},
16627 + {0x000081cc, 0x00000000},
16628 + {0x000081d4, 0x00000000},
16629 + {0x000081ec, 0x00000000},
16630 + {0x000081f0, 0x00000000},
16631 + {0x000081f4, 0x00000000},
16632 + {0x000081f8, 0x00000000},
16633 + {0x000081fc, 0x00000000},
16634 + {0x00008240, 0x00100000},
16635 + {0x00008244, 0x0010f424},
16636 + {0x00008248, 0x00000800},
16637 + {0x0000824c, 0x0001e848},
16638 + {0x00008250, 0x00000000},
16639 + {0x00008254, 0x00000000},
16640 + {0x00008258, 0x00000000},
16641 + {0x0000825c, 0x40000000},
16642 + {0x00008260, 0x00080922},
16643 + {0x00008264, 0x98a00010},
16644 + {0x00008268, 0xffffffff},
16645 + {0x0000826c, 0x0000ffff},
16646 + {0x00008270, 0x00000000},
16647 + {0x00008274, 0x40000000},
16648 + {0x00008278, 0x003e4180},
16649 + {0x0000827c, 0x00000004},
16650 + {0x00008284, 0x0000002c},
16651 + {0x00008288, 0x0000002c},
16652 + {0x0000828c, 0x000000ff},
16653 + {0x00008294, 0x00000000},
16654 + {0x00008298, 0x00000000},
16655 + {0x0000829c, 0x00000000},
16656 + {0x00008300, 0x00000140},
16657 + {0x00008314, 0x00000000},
16658 + {0x0000831c, 0x0000010d},
16659 + {0x00008328, 0x00000000},
16660 + {0x0000832c, 0x00000007},
16661 + {0x00008330, 0x00000302},
16662 + {0x00008334, 0x00000700},
16663 + {0x00008338, 0x00ff0000},
16664 + {0x0000833c, 0x02400000},
16665 + {0x00008340, 0x000107ff},
16666 + {0x00008344, 0xaa48105b},
16667 + {0x00008348, 0x008f0000},
16668 + {0x0000835c, 0x00000000},
16669 + {0x00008360, 0xffffffff},
16670 + {0x00008364, 0xffffffff},
16671 + {0x00008368, 0x00000000},
16672 + {0x00008370, 0x00000000},
16673 + {0x00008374, 0x000000ff},
16674 + {0x00008378, 0x00000000},
16675 + {0x0000837c, 0x00000000},
16676 + {0x00008380, 0xffffffff},
16677 + {0x00008384, 0xffffffff},
16678 + {0x00008390, 0xffffffff},
16679 + {0x00008394, 0xffffffff},
16680 + {0x00008398, 0x00000000},
16681 + {0x0000839c, 0x00000000},
16682 + {0x000083a0, 0x00000000},
16683 + {0x000083a4, 0x0000fa14},
16684 + {0x000083a8, 0x000f0c00},
16685 + {0x000083ac, 0x33332210},
16686 + {0x000083b0, 0x33332210},
16687 + {0x000083b4, 0x33332210},
16688 + {0x000083b8, 0x33332210},
16689 + {0x000083bc, 0x00000000},
16690 + {0x000083c0, 0x00000000},
16691 + {0x000083c4, 0x00000000},
16692 + {0x000083c8, 0x00000000},
16693 + {0x000083cc, 0x00000200},
16694 + {0x000083d0, 0x000301ff},
16695 +};
16696 +
16697 +static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
16698 + /* Addr allmodes */
16699 + {0x0000a000, 0x00010000},
16700 + {0x0000a004, 0x00030002},
16701 + {0x0000a008, 0x00050004},
16702 + {0x0000a00c, 0x00810080},
16703 + {0x0000a010, 0x01800082},
16704 + {0x0000a014, 0x01820181},
16705 + {0x0000a018, 0x01840183},
16706 + {0x0000a01c, 0x01880185},
16707 + {0x0000a020, 0x018a0189},
16708 + {0x0000a024, 0x02850284},
16709 + {0x0000a028, 0x02890288},
16710 + {0x0000a02c, 0x03850384},
16711 + {0x0000a030, 0x03890388},
16712 + {0x0000a034, 0x038b038a},
16713 + {0x0000a038, 0x038d038c},
16714 + {0x0000a03c, 0x03910390},
16715 + {0x0000a040, 0x03930392},
16716 + {0x0000a044, 0x03950394},
16717 + {0x0000a048, 0x00000396},
16718 + {0x0000a04c, 0x00000000},
16719 + {0x0000a050, 0x00000000},
16720 + {0x0000a054, 0x00000000},
16721 + {0x0000a058, 0x00000000},
16722 + {0x0000a05c, 0x00000000},
16723 + {0x0000a060, 0x00000000},
16724 + {0x0000a064, 0x00000000},
16725 + {0x0000a068, 0x00000000},
16726 + {0x0000a06c, 0x00000000},
16727 + {0x0000a070, 0x00000000},
16728 + {0x0000a074, 0x00000000},
16729 + {0x0000a078, 0x00000000},
16730 + {0x0000a07c, 0x00000000},
16731 + {0x0000a080, 0x28282828},
16732 + {0x0000a084, 0x28282828},
16733 + {0x0000a088, 0x28282828},
16734 + {0x0000a08c, 0x28282828},
16735 + {0x0000a090, 0x28282828},
16736 + {0x0000a094, 0x21212128},
16737 + {0x0000a098, 0x171c1c1c},
16738 + {0x0000a09c, 0x02020212},
16739 + {0x0000a0a0, 0x00000202},
16740 + {0x0000a0a4, 0x00000000},
16741 + {0x0000a0a8, 0x00000000},
16742 + {0x0000a0ac, 0x00000000},
16743 + {0x0000a0b0, 0x00000000},
16744 + {0x0000a0b4, 0x00000000},
16745 + {0x0000a0b8, 0x00000000},
16746 + {0x0000a0bc, 0x00000000},
16747 + {0x0000a0c0, 0x001f0000},
16748 + {0x0000a0c4, 0x011f0100},
16749 + {0x0000a0c8, 0x011d011e},
16750 + {0x0000a0cc, 0x011b011c},
16751 + {0x0000a0d0, 0x02030204},
16752 + {0x0000a0d4, 0x02010202},
16753 + {0x0000a0d8, 0x021f0200},
16754 + {0x0000a0dc, 0x021d021e},
16755 + {0x0000a0e0, 0x03010302},
16756 + {0x0000a0e4, 0x031f0300},
16757 + {0x0000a0e8, 0x0402031e},
16758 + {0x0000a0ec, 0x04000401},
16759 + {0x0000a0f0, 0x041e041f},
16760 + {0x0000a0f4, 0x05010502},
16761 + {0x0000a0f8, 0x051f0500},
16762 + {0x0000a0fc, 0x0602051e},
16763 + {0x0000a100, 0x06000601},
16764 + {0x0000a104, 0x061e061f},
16765 + {0x0000a108, 0x0703061d},
16766 + {0x0000a10c, 0x07010702},
16767 + {0x0000a110, 0x00000700},
16768 + {0x0000a114, 0x00000000},
16769 + {0x0000a118, 0x00000000},
16770 + {0x0000a11c, 0x00000000},
16771 + {0x0000a120, 0x00000000},
16772 + {0x0000a124, 0x00000000},
16773 + {0x0000a128, 0x00000000},
16774 + {0x0000a12c, 0x00000000},
16775 + {0x0000a130, 0x00000000},
16776 + {0x0000a134, 0x00000000},
16777 + {0x0000a138, 0x00000000},
16778 + {0x0000a13c, 0x00000000},
16779 + {0x0000a140, 0x001f0000},
16780 + {0x0000a144, 0x011f0100},
16781 + {0x0000a148, 0x011d011e},
16782 + {0x0000a14c, 0x011b011c},
16783 + {0x0000a150, 0x02030204},
16784 + {0x0000a154, 0x02010202},
16785 + {0x0000a158, 0x021f0200},
16786 + {0x0000a15c, 0x021d021e},
16787 + {0x0000a160, 0x03010302},
16788 + {0x0000a164, 0x031f0300},
16789 + {0x0000a168, 0x0402031e},
16790 + {0x0000a16c, 0x04000401},
16791 + {0x0000a170, 0x041e041f},
16792 + {0x0000a174, 0x05010502},
16793 + {0x0000a178, 0x051f0500},
16794 + {0x0000a17c, 0x0602051e},
16795 + {0x0000a180, 0x06000601},
16796 + {0x0000a184, 0x061e061f},
16797 + {0x0000a188, 0x0703061d},
16798 + {0x0000a18c, 0x07010702},
16799 + {0x0000a190, 0x00000700},
16800 + {0x0000a194, 0x00000000},
16801 + {0x0000a198, 0x00000000},
16802 + {0x0000a19c, 0x00000000},
16803 + {0x0000a1a0, 0x00000000},
16804 + {0x0000a1a4, 0x00000000},
16805 + {0x0000a1a8, 0x00000000},
16806 + {0x0000a1ac, 0x00000000},
16807 + {0x0000a1b0, 0x00000000},
16808 + {0x0000a1b4, 0x00000000},
16809 + {0x0000a1b8, 0x00000000},
16810 + {0x0000a1bc, 0x00000000},
16811 + {0x0000a1c0, 0x00000000},
16812 + {0x0000a1c4, 0x00000000},
16813 + {0x0000a1c8, 0x00000000},
16814 + {0x0000a1cc, 0x00000000},
16815 + {0x0000a1d0, 0x00000000},
16816 + {0x0000a1d4, 0x00000000},
16817 + {0x0000a1d8, 0x00000000},
16818 + {0x0000a1dc, 0x00000000},
16819 + {0x0000a1e0, 0x00000000},
16820 + {0x0000a1e4, 0x00000000},
16821 + {0x0000a1e8, 0x00000000},
16822 + {0x0000a1ec, 0x00000000},
16823 + {0x0000a1f0, 0x00000396},
16824 + {0x0000a1f4, 0x00000396},
16825 + {0x0000a1f8, 0x00000396},
16826 + {0x0000a1fc, 0x00000296},
16827 + {0x0000b000, 0x00010000},
16828 + {0x0000b004, 0x00030002},
16829 + {0x0000b008, 0x00050004},
16830 + {0x0000b00c, 0x00810080},
16831 + {0x0000b010, 0x00830082},
16832 + {0x0000b014, 0x01810180},
16833 + {0x0000b018, 0x01830182},
16834 + {0x0000b01c, 0x01850184},
16835 + {0x0000b020, 0x02810280},
16836 + {0x0000b024, 0x02830282},
16837 + {0x0000b028, 0x02850284},
16838 + {0x0000b02c, 0x02890288},
16839 + {0x0000b030, 0x028b028a},
16840 + {0x0000b034, 0x0388028c},
16841 + {0x0000b038, 0x038a0389},
16842 + {0x0000b03c, 0x038c038b},
16843 + {0x0000b040, 0x0390038d},
16844 + {0x0000b044, 0x03920391},
16845 + {0x0000b048, 0x03940393},
16846 + {0x0000b04c, 0x03960395},
16847 + {0x0000b050, 0x00000000},
16848 + {0x0000b054, 0x00000000},
16849 + {0x0000b058, 0x00000000},
16850 + {0x0000b05c, 0x00000000},
16851 + {0x0000b060, 0x00000000},
16852 + {0x0000b064, 0x00000000},
16853 + {0x0000b068, 0x00000000},
16854 + {0x0000b06c, 0x00000000},
16855 + {0x0000b070, 0x00000000},
16856 + {0x0000b074, 0x00000000},
16857 + {0x0000b078, 0x00000000},
16858 + {0x0000b07c, 0x00000000},
16859 + {0x0000b080, 0x32323232},
16860 + {0x0000b084, 0x2f2f3232},
16861 + {0x0000b088, 0x23282a2d},
16862 + {0x0000b08c, 0x1c1e2123},
16863 + {0x0000b090, 0x14171919},
16864 + {0x0000b094, 0x0e0e1214},
16865 + {0x0000b098, 0x03050707},
16866 + {0x0000b09c, 0x00030303},
16867 + {0x0000b0a0, 0x00000000},
16868 + {0x0000b0a4, 0x00000000},
16869 + {0x0000b0a8, 0x00000000},
16870 + {0x0000b0ac, 0x00000000},
16871 + {0x0000b0b0, 0x00000000},
16872 + {0x0000b0b4, 0x00000000},
16873 + {0x0000b0b8, 0x00000000},
16874 + {0x0000b0bc, 0x00000000},
16875 + {0x0000b0c0, 0x003f0020},
16876 + {0x0000b0c4, 0x00400041},
16877 + {0x0000b0c8, 0x0140005f},
16878 + {0x0000b0cc, 0x0160015f},
16879 + {0x0000b0d0, 0x017e017f},
16880 + {0x0000b0d4, 0x02410242},
16881 + {0x0000b0d8, 0x025f0240},
16882 + {0x0000b0dc, 0x027f0260},
16883 + {0x0000b0e0, 0x0341027e},
16884 + {0x0000b0e4, 0x035f0340},
16885 + {0x0000b0e8, 0x037f0360},
16886 + {0x0000b0ec, 0x04400441},
16887 + {0x0000b0f0, 0x0460045f},
16888 + {0x0000b0f4, 0x0541047f},
16889 + {0x0000b0f8, 0x055f0540},
16890 + {0x0000b0fc, 0x057f0560},
16891 + {0x0000b100, 0x06400641},
16892 + {0x0000b104, 0x0660065f},
16893 + {0x0000b108, 0x067e067f},
16894 + {0x0000b10c, 0x07410742},
16895 + {0x0000b110, 0x075f0740},
16896 + {0x0000b114, 0x077f0760},
16897 + {0x0000b118, 0x07800781},
16898 + {0x0000b11c, 0x07a0079f},
16899 + {0x0000b120, 0x07c107bf},
16900 + {0x0000b124, 0x000007c0},
16901 + {0x0000b128, 0x00000000},
16902 + {0x0000b12c, 0x00000000},
16903 + {0x0000b130, 0x00000000},
16904 + {0x0000b134, 0x00000000},
16905 + {0x0000b138, 0x00000000},
16906 + {0x0000b13c, 0x00000000},
16907 + {0x0000b140, 0x003f0020},
16908 + {0x0000b144, 0x00400041},
16909 + {0x0000b148, 0x0140005f},
16910 + {0x0000b14c, 0x0160015f},
16911 + {0x0000b150, 0x017e017f},
16912 + {0x0000b154, 0x02410242},
16913 + {0x0000b158, 0x025f0240},
16914 + {0x0000b15c, 0x027f0260},
16915 + {0x0000b160, 0x0341027e},
16916 + {0x0000b164, 0x035f0340},
16917 + {0x0000b168, 0x037f0360},
16918 + {0x0000b16c, 0x04400441},
16919 + {0x0000b170, 0x0460045f},
16920 + {0x0000b174, 0x0541047f},
16921 + {0x0000b178, 0x055f0540},
16922 + {0x0000b17c, 0x057f0560},
16923 + {0x0000b180, 0x06400641},
16924 + {0x0000b184, 0x0660065f},
16925 + {0x0000b188, 0x067e067f},
16926 + {0x0000b18c, 0x07410742},
16927 + {0x0000b190, 0x075f0740},
16928 + {0x0000b194, 0x077f0760},
16929 + {0x0000b198, 0x07800781},
16930 + {0x0000b19c, 0x07a0079f},
16931 + {0x0000b1a0, 0x07c107bf},
16932 + {0x0000b1a4, 0x000007c0},
16933 + {0x0000b1a8, 0x00000000},
16934 + {0x0000b1ac, 0x00000000},
16935 + {0x0000b1b0, 0x00000000},
16936 + {0x0000b1b4, 0x00000000},
16937 + {0x0000b1b8, 0x00000000},
16938 + {0x0000b1bc, 0x00000000},
16939 + {0x0000b1c0, 0x00000000},
16940 + {0x0000b1c4, 0x00000000},
16941 + {0x0000b1c8, 0x00000000},
16942 + {0x0000b1cc, 0x00000000},
16943 + {0x0000b1d0, 0x00000000},
16944 + {0x0000b1d4, 0x00000000},
16945 + {0x0000b1d8, 0x00000000},
16946 + {0x0000b1dc, 0x00000000},
16947 + {0x0000b1e0, 0x00000000},
16948 + {0x0000b1e4, 0x00000000},
16949 + {0x0000b1e8, 0x00000000},
16950 + {0x0000b1ec, 0x00000000},
16951 + {0x0000b1f0, 0x00000396},
16952 + {0x0000b1f4, 0x00000396},
16953 + {0x0000b1f8, 0x00000396},
16954 + {0x0000b1fc, 0x00000196},
16955 +};
16956 +
16957 +static const u32 ar9300_2p0_soc_preamble[][2] = {
16958 + /* Addr allmodes */
16959 + {0x000040a4, 0x00a0c1c9},
16960 + {0x00007008, 0x00000000},
16961 + {0x00007020, 0x00000000},
16962 + {0x00007034, 0x00000002},
16963 + {0x00007038, 0x000004c2},
16964 +};
16965 +
16966 +/*
16967 + * PCIE-PHY programming array, to be used prior to entering
16968 + * full sleep (holding RTC in reset, PLL is ON in L1 mode)
16969 + */
16970 +static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
16971 + {0x00004040, 0x08212e5e},
16972 + {0x00004040, 0x0008003b},
16973 + {0x00004044, 0x00000000},
16974 +};
16975 +
16976 +/*
16977 + * PCIE-PHY programming array, to be used when not in
16978 + * full sleep (holding RTC in reset)
16979 + */
16980 +static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
16981 + {0x00004040, 0x08253e5e},
16982 + {0x00004040, 0x0008003b},
16983 + {0x00004044, 0x00000000},
16984 +};
16985 +
16986 +/*
16987 + * PCIE-PHY programming array, to be used prior to entering
16988 + * full sleep (holding RTC in reset)
16989 + */
16990 +static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
16991 + {0x00004040, 0x08213e5e},
16992 + {0x00004040, 0x0008003b},
16993 + {0x00004044, 0x00000000},
16994 +};
16995 +
16996 +#endif /* INITVALS_9003_H */
16997 --- /dev/null
16998 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
16999 @@ -0,0 +1,611 @@
17000 +/*
17001 + * Copyright (c) 2010 Atheros Communications Inc.
17002 + *
17003 + * Permission to use, copy, modify, and/or distribute this software for any
17004 + * purpose with or without fee is hereby granted, provided that the above
17005 + * copyright notice and this permission notice appear in all copies.
17006 + *
17007 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17008 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17009 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17010 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17011 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17012 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17013 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17014 + */
17015 +#include "hw.h"
17016 +#include "ar9003_mac.h"
17017 +
17018 +static void ar9003_hw_rx_enable(struct ath_hw *hw)
17019 +{
17020 + REG_WRITE(hw, AR_CR, 0);
17021 +}
17022 +
17023 +static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
17024 +{
17025 + int checksum;
17026 +
17027 + checksum = ads->info + ads->link
17028 + + ads->data0 + ads->ctl3
17029 + + ads->data1 + ads->ctl5
17030 + + ads->data2 + ads->ctl7
17031 + + ads->data3 + ads->ctl9;
17032 +
17033 + return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
17034 +}
17035 +
17036 +static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
17037 +{
17038 + struct ar9003_txc *ads = ds;
17039 +
17040 + ads->link = ds_link;
17041 + ads->ctl10 &= ~AR_TxPtrChkSum;
17042 + ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
17043 +}
17044 +
17045 +static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
17046 +{
17047 + struct ar9003_txc *ads = ds;
17048 +
17049 + *ds_link = &ads->link;
17050 +}
17051 +
17052 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
17053 +{
17054 + u32 isr = 0;
17055 + u32 mask2 = 0;
17056 + struct ath9k_hw_capabilities *pCap = &ah->caps;
17057 + u32 sync_cause = 0;
17058 + struct ath_common *common = ath9k_hw_common(ah);
17059 +
17060 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
17061 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
17062 + == AR_RTC_STATUS_ON)
17063 + isr = REG_READ(ah, AR_ISR);
17064 + }
17065 +
17066 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
17067 +
17068 + *masked = 0;
17069 +
17070 + if (!isr && !sync_cause)
17071 + return false;
17072 +
17073 + if (isr) {
17074 + if (isr & AR_ISR_BCNMISC) {
17075 + u32 isr2;
17076 + isr2 = REG_READ(ah, AR_ISR_S2);
17077 +
17078 + mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
17079 + MAP_ISR_S2_TIM);
17080 + mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
17081 + MAP_ISR_S2_DTIM);
17082 + mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
17083 + MAP_ISR_S2_DTIMSYNC);
17084 + mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
17085 + MAP_ISR_S2_CABEND);
17086 + mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
17087 + MAP_ISR_S2_GTT);
17088 + mask2 |= ((isr2 & AR_ISR_S2_CST) <<
17089 + MAP_ISR_S2_CST);
17090 + mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
17091 + MAP_ISR_S2_TSFOOR);
17092 +
17093 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17094 + REG_WRITE(ah, AR_ISR_S2, isr2);
17095 + isr &= ~AR_ISR_BCNMISC;
17096 + }
17097 + }
17098 +
17099 + if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
17100 + isr = REG_READ(ah, AR_ISR_RAC);
17101 +
17102 + if (isr == 0xffffffff) {
17103 + *masked = 0;
17104 + return false;
17105 + }
17106 +
17107 + *masked = isr & ATH9K_INT_COMMON;
17108 +
17109 + if (ah->config.rx_intr_mitigation)
17110 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
17111 + *masked |= ATH9K_INT_RXLP;
17112 +
17113 + if (ah->config.tx_intr_mitigation)
17114 + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
17115 + *masked |= ATH9K_INT_TX;
17116 +
17117 + if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
17118 + *masked |= ATH9K_INT_RXLP;
17119 +
17120 + if (isr & AR_ISR_HP_RXOK)
17121 + *masked |= ATH9K_INT_RXHP;
17122 +
17123 + if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
17124 + *masked |= ATH9K_INT_TX;
17125 +
17126 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17127 + u32 s0, s1;
17128 + s0 = REG_READ(ah, AR_ISR_S0);
17129 + REG_WRITE(ah, AR_ISR_S0, s0);
17130 + s1 = REG_READ(ah, AR_ISR_S1);
17131 + REG_WRITE(ah, AR_ISR_S1, s1);
17132 +
17133 + isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
17134 + AR_ISR_TXEOL);
17135 + }
17136 + }
17137 +
17138 + if (isr & AR_ISR_GENTMR) {
17139 + u32 s5;
17140 +
17141 + if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
17142 + s5 = REG_READ(ah, AR_ISR_S5_S);
17143 + else
17144 + s5 = REG_READ(ah, AR_ISR_S5);
17145 +
17146 + ah->intr_gen_timer_trigger =
17147 + MS(s5, AR_ISR_S5_GENTIMER_TRIG);
17148 +
17149 + ah->intr_gen_timer_thresh =
17150 + MS(s5, AR_ISR_S5_GENTIMER_THRESH);
17151 +
17152 + if (ah->intr_gen_timer_trigger)
17153 + *masked |= ATH9K_INT_GENTIMER;
17154 +
17155 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17156 + REG_WRITE(ah, AR_ISR_S5, s5);
17157 + isr &= ~AR_ISR_GENTMR;
17158 + }
17159 +
17160 + }
17161 +
17162 + *masked |= mask2;
17163 +
17164 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
17165 + REG_WRITE(ah, AR_ISR, isr);
17166 +
17167 + (void) REG_READ(ah, AR_ISR);
17168 + }
17169 + }
17170 +
17171 + if (sync_cause) {
17172 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
17173 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
17174 + REG_WRITE(ah, AR_RC, 0);
17175 + *masked |= ATH9K_INT_FATAL;
17176 + }
17177 +
17178 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
17179 + ath_print(common, ATH_DBG_INTERRUPT,
17180 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
17181 +
17182 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
17183 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
17184 +
17185 + }
17186 + return true;
17187 +}
17188 +
17189 +static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
17190 + bool is_firstseg, bool is_lastseg,
17191 + const void *ds0, dma_addr_t buf_addr,
17192 + unsigned int qcu)
17193 +{
17194 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17195 + unsigned int descid = 0;
17196 +
17197 + ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
17198 + (1 << AR_TxRxDesc_S) |
17199 + (1 << AR_CtrlStat_S) |
17200 + (qcu << AR_TxQcuNum_S) | 0x17;
17201 +
17202 + ads->data0 = buf_addr;
17203 + ads->data1 = 0;
17204 + ads->data2 = 0;
17205 + ads->data3 = 0;
17206 +
17207 + ads->ctl3 = (seglen << AR_BufLen_S);
17208 + ads->ctl3 &= AR_BufLen;
17209 +
17210 + /* Fill in pointer checksum and descriptor id */
17211 + ads->ctl10 = ar9003_calc_ptr_chksum(ads);
17212 + ads->ctl10 |= (descid << AR_TxDescId_S);
17213 +
17214 + if (is_firstseg) {
17215 + ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
17216 + } else if (is_lastseg) {
17217 + ads->ctl11 = 0;
17218 + ads->ctl12 = 0;
17219 + ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
17220 + ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
17221 + } else {
17222 + /* XXX Intermediate descriptor in a multi-descriptor frame.*/
17223 + ads->ctl11 = 0;
17224 + ads->ctl12 = AR_TxMore;
17225 + ads->ctl13 = 0;
17226 + ads->ctl14 = 0;
17227 + }
17228 +}
17229 +
17230 +static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
17231 + struct ath_tx_status *ts)
17232 +{
17233 + struct ar9003_txs *ads;
17234 +
17235 + ads = &ah->ts_ring[ah->ts_tail];
17236 +
17237 + if ((ads->status8 & AR_TxDone) == 0)
17238 + return -EINPROGRESS;
17239 +
17240 + ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
17241 +
17242 + if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
17243 + (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
17244 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
17245 + "Tx Descriptor error %x\n", ads->ds_info);
17246 + memset(ads, 0, sizeof(*ads));
17247 + return -EIO;
17248 + }
17249 +
17250 + ts->qid = MS(ads->ds_info, AR_TxQcuNum);
17251 + ts->desc_id = MS(ads->status1, AR_TxDescId);
17252 + ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
17253 + ts->ts_tstamp = ads->status4;
17254 + ts->ts_status = 0;
17255 + ts->ts_flags = 0;
17256 +
17257 + if (ads->status3 & AR_ExcessiveRetries)
17258 + ts->ts_status |= ATH9K_TXERR_XRETRY;
17259 + if (ads->status3 & AR_Filtered)
17260 + ts->ts_status |= ATH9K_TXERR_FILT;
17261 + if (ads->status3 & AR_FIFOUnderrun) {
17262 + ts->ts_status |= ATH9K_TXERR_FIFO;
17263 + ath9k_hw_updatetxtriglevel(ah, true);
17264 + }
17265 + if (ads->status8 & AR_TxOpExceeded)
17266 + ts->ts_status |= ATH9K_TXERR_XTXOP;
17267 + if (ads->status3 & AR_TxTimerExpired)
17268 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
17269 +
17270 + if (ads->status3 & AR_DescCfgErr)
17271 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
17272 + if (ads->status3 & AR_TxDataUnderrun) {
17273 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
17274 + ath9k_hw_updatetxtriglevel(ah, true);
17275 + }
17276 + if (ads->status3 & AR_TxDelimUnderrun) {
17277 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
17278 + ath9k_hw_updatetxtriglevel(ah, true);
17279 + }
17280 + if (ads->status2 & AR_TxBaStatus) {
17281 + ts->ts_flags |= ATH9K_TX_BA;
17282 + ts->ba_low = ads->status5;
17283 + ts->ba_high = ads->status6;
17284 + }
17285 +
17286 + ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
17287 +
17288 + ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
17289 + ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
17290 + ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
17291 + ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
17292 + ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
17293 + ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
17294 + ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
17295 + ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
17296 + ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
17297 + ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
17298 + ts->ts_antenna = 0;
17299 +
17300 + ts->tid = MS(ads->status8, AR_TxTid);
17301 +
17302 + memset(ads, 0, sizeof(*ads));
17303 +
17304 + return 0;
17305 +}
17306 +
17307 +static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
17308 + u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
17309 + u32 keyIx, enum ath9k_key_type keyType, u32 flags)
17310 +{
17311 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17312 +
17313 + txpower += ah->txpower_indexoffset;
17314 + if (txpower > 63)
17315 + txpower = 63;
17316 +
17317 + ads->ctl11 = (pktlen & AR_FrameLen)
17318 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
17319 + | SM(txpower, AR_XmitPower)
17320 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
17321 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
17322 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
17323 + | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
17324 +
17325 + ads->ctl12 =
17326 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
17327 + | SM(type, AR_FrameType)
17328 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
17329 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
17330 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
17331 +
17332 + ads->ctl17 = SM(keyType, AR_EncrType) |
17333 + (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
17334 + ads->ctl18 = 0;
17335 + ads->ctl19 = AR_Not_Sounding;
17336 +
17337 + ads->ctl20 = 0;
17338 + ads->ctl21 = 0;
17339 + ads->ctl22 = 0;
17340 +}
17341 +
17342 +static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
17343 + void *lastds,
17344 + u32 durUpdateEn, u32 rtsctsRate,
17345 + u32 rtsctsDuration,
17346 + struct ath9k_11n_rate_series series[],
17347 + u32 nseries, u32 flags)
17348 +{
17349 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17350 + struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
17351 + u_int32_t ctl11;
17352 +
17353 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
17354 + ctl11 = ads->ctl11;
17355 +
17356 + if (flags & ATH9K_TXDESC_RTSENA) {
17357 + ctl11 &= ~AR_CTSEnable;
17358 + ctl11 |= AR_RTSEnable;
17359 + } else {
17360 + ctl11 &= ~AR_RTSEnable;
17361 + ctl11 |= AR_CTSEnable;
17362 + }
17363 +
17364 + ads->ctl11 = ctl11;
17365 + } else {
17366 + ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
17367 + }
17368 +
17369 + ads->ctl13 = set11nTries(series, 0)
17370 + | set11nTries(series, 1)
17371 + | set11nTries(series, 2)
17372 + | set11nTries(series, 3)
17373 + | (durUpdateEn ? AR_DurUpdateEna : 0)
17374 + | SM(0, AR_BurstDur);
17375 +
17376 + ads->ctl14 = set11nRate(series, 0)
17377 + | set11nRate(series, 1)
17378 + | set11nRate(series, 2)
17379 + | set11nRate(series, 3);
17380 +
17381 + ads->ctl15 = set11nPktDurRTSCTS(series, 0)
17382 + | set11nPktDurRTSCTS(series, 1);
17383 +
17384 + ads->ctl16 = set11nPktDurRTSCTS(series, 2)
17385 + | set11nPktDurRTSCTS(series, 3);
17386 +
17387 + ads->ctl18 = set11nRateFlags(series, 0)
17388 + | set11nRateFlags(series, 1)
17389 + | set11nRateFlags(series, 2)
17390 + | set11nRateFlags(series, 3)
17391 + | SM(rtsctsRate, AR_RTSCTSRate);
17392 + ads->ctl19 = AR_Not_Sounding;
17393 +
17394 + last_ads->ctl13 = ads->ctl13;
17395 + last_ads->ctl14 = ads->ctl14;
17396 +}
17397 +
17398 +static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
17399 + u32 aggrLen)
17400 +{
17401 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17402 +
17403 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
17404 +
17405 + ads->ctl17 &= ~AR_AggrLen;
17406 + ads->ctl17 |= SM(aggrLen, AR_AggrLen);
17407 +}
17408 +
17409 +static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
17410 + u32 numDelims)
17411 +{
17412 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17413 + unsigned int ctl17;
17414 +
17415 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
17416 +
17417 + /*
17418 + * We use a stack variable to manipulate ctl6 to reduce uncached
17419 + * read modify, modfiy, write.
17420 + */
17421 + ctl17 = ads->ctl17;
17422 + ctl17 &= ~AR_PadDelim;
17423 + ctl17 |= SM(numDelims, AR_PadDelim);
17424 + ads->ctl17 = ctl17;
17425 +}
17426 +
17427 +static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
17428 +{
17429 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17430 +
17431 + ads->ctl12 |= AR_IsAggr;
17432 + ads->ctl12 &= ~AR_MoreAggr;
17433 + ads->ctl17 &= ~AR_PadDelim;
17434 +}
17435 +
17436 +static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
17437 +{
17438 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17439 +
17440 + ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
17441 +}
17442 +
17443 +static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
17444 + u32 burstDuration)
17445 +{
17446 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17447 +
17448 + ads->ctl13 &= ~AR_BurstDur;
17449 + ads->ctl13 |= SM(burstDuration, AR_BurstDur);
17450 +
17451 +}
17452 +
17453 +static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
17454 + u32 vmf)
17455 +{
17456 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
17457 +
17458 + if (vmf)
17459 + ads->ctl11 |= AR_VirtMoreFrag;
17460 + else
17461 + ads->ctl11 &= ~AR_VirtMoreFrag;
17462 +}
17463 +
17464 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
17465 +{
17466 + struct ath_hw_ops *ops = ath9k_hw_ops(hw);
17467 +
17468 + ops->rx_enable = ar9003_hw_rx_enable;
17469 + ops->set_desc_link = ar9003_hw_set_desc_link;
17470 + ops->get_desc_link = ar9003_hw_get_desc_link;
17471 + ops->get_isr = ar9003_hw_get_isr;
17472 + ops->fill_txdesc = ar9003_hw_fill_txdesc;
17473 + ops->proc_txdesc = ar9003_hw_proc_txdesc;
17474 + ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
17475 + ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
17476 + ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
17477 + ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
17478 + ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
17479 + ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
17480 + ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
17481 + ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
17482 +}
17483 +
17484 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
17485 +{
17486 + REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
17487 +}
17488 +EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
17489 +
17490 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
17491 + enum ath9k_rx_qtype qtype)
17492 +{
17493 + if (qtype == ATH9K_RX_QUEUE_HP)
17494 + REG_WRITE(ah, AR_HP_RXDP, rxdp);
17495 + else
17496 + REG_WRITE(ah, AR_LP_RXDP, rxdp);
17497 +}
17498 +EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
17499 +
17500 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
17501 + void *buf_addr)
17502 +{
17503 + struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
17504 + unsigned int phyerr;
17505 +
17506 + /* TODO: byte swap on big endian for ar9300_10 */
17507 +
17508 + if ((rxsp->status11 & AR_RxDone) == 0)
17509 + return -EINPROGRESS;
17510 +
17511 + if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
17512 + return -EINVAL;
17513 +
17514 + if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
17515 + return -EINPROGRESS;
17516 +
17517 + if (!rxs)
17518 + return 0;
17519 +
17520 + rxs->rs_status = 0;
17521 + rxs->rs_flags = 0;
17522 +
17523 + rxs->rs_datalen = rxsp->status2 & AR_DataLen;
17524 + rxs->rs_tstamp = rxsp->status3;
17525 +
17526 + /* XXX: Keycache */
17527 + rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
17528 + rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
17529 + rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
17530 + rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
17531 + rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
17532 + rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
17533 + rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
17534 +
17535 + if (rxsp->status11 & AR_RxKeyIdxValid)
17536 + rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
17537 + else
17538 + rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
17539 +
17540 + rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
17541 + rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
17542 +
17543 + rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
17544 + rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
17545 + rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
17546 + rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
17547 + rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
17548 +
17549 + rxs->evm0 = rxsp->status6;
17550 + rxs->evm1 = rxsp->status7;
17551 + rxs->evm2 = rxsp->status8;
17552 + rxs->evm3 = rxsp->status9;
17553 + rxs->evm4 = (rxsp->status10 & 0xffff);
17554 +
17555 + if (rxsp->status11 & AR_PreDelimCRCErr)
17556 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
17557 +
17558 + if (rxsp->status11 & AR_PostDelimCRCErr)
17559 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
17560 +
17561 + if (rxsp->status11 & AR_DecryptBusyErr)
17562 + rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
17563 +
17564 + if ((rxsp->status11 & AR_RxFrameOK) == 0) {
17565 + if (rxsp->status11 & AR_CRCErr) {
17566 + rxs->rs_status |= ATH9K_RXERR_CRC;
17567 + } else if (rxsp->status11 & AR_PHYErr) {
17568 + rxs->rs_status |= ATH9K_RXERR_PHY;
17569 + phyerr = MS(rxsp->status11, AR_PHYErrCode);
17570 + rxs->rs_phyerr = phyerr;
17571 + } else if (rxsp->status11 & AR_DecryptCRCErr) {
17572 + rxs->rs_status |= ATH9K_RXERR_DECRYPT;
17573 + } else if (rxsp->status11 & AR_MichaelErr) {
17574 + rxs->rs_status |= ATH9K_RXERR_MIC;
17575 + }
17576 + }
17577 +
17578 + return 0;
17579 +}
17580 +EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
17581 +
17582 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
17583 +{
17584 + ah->ts_tail = 0;
17585 +
17586 + memset((void *) ah->ts_ring, 0,
17587 + ah->ts_size * sizeof(struct ar9003_txs));
17588 +
17589 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
17590 + "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
17591 + ah->ts_paddr_start, ah->ts_paddr_end,
17592 + ah->ts_ring, ah->ts_size);
17593 +
17594 + REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
17595 + REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
17596 +}
17597 +
17598 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
17599 + u32 ts_paddr_start,
17600 + u8 size)
17601 +{
17602 +
17603 + ah->ts_paddr_start = ts_paddr_start;
17604 + ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
17605 + ah->ts_size = size;
17606 + ah->ts_ring = (struct ar9003_txs *) ts_start;
17607 +
17608 + ath9k_hw_reset_txstatus_ring(ah);
17609 +}
17610 +EXPORT_SYMBOL(ath9k_hw_setup_statusring);
17611 --- /dev/null
17612 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
17613 @@ -0,0 +1,120 @@
17614 +/*
17615 + * Copyright (c) 2010 Atheros Communications Inc.
17616 + *
17617 + * Permission to use, copy, modify, and/or distribute this software for any
17618 + * purpose with or without fee is hereby granted, provided that the above
17619 + * copyright notice and this permission notice appear in all copies.
17620 + *
17621 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17622 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17623 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17624 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17625 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17626 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17627 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17628 + */
17629 +
17630 +#ifndef AR9003_MAC_H
17631 +#define AR9003_MAC_H
17632 +
17633 +#define AR_DescId 0xffff0000
17634 +#define AR_DescId_S 16
17635 +#define AR_CtrlStat 0x00004000
17636 +#define AR_CtrlStat_S 14
17637 +#define AR_TxRxDesc 0x00008000
17638 +#define AR_TxRxDesc_S 15
17639 +#define AR_TxQcuNum 0x00000f00
17640 +#define AR_TxQcuNum_S 8
17641 +
17642 +#define AR_BufLen 0x0fff0000
17643 +#define AR_BufLen_S 16
17644 +
17645 +#define AR_TxDescId 0xffff0000
17646 +#define AR_TxDescId_S 16
17647 +#define AR_TxPtrChkSum 0x0000ffff
17648 +
17649 +#define AR_TxTid 0xf0000000
17650 +#define AR_TxTid_S 28
17651 +
17652 +#define AR_LowRxChain 0x00004000
17653 +
17654 +#define AR_Not_Sounding 0x20000000
17655 +
17656 +#define MAP_ISR_S2_CST 6
17657 +#define MAP_ISR_S2_GTT 6
17658 +#define MAP_ISR_S2_TIM 3
17659 +#define MAP_ISR_S2_CABEND 0
17660 +#define MAP_ISR_S2_DTIMSYNC 7
17661 +#define MAP_ISR_S2_DTIM 7
17662 +#define MAP_ISR_S2_TSFOOR 4
17663 +
17664 +#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
17665 +
17666 +struct ar9003_rxs {
17667 + u32 ds_info;
17668 + u32 status1;
17669 + u32 status2;
17670 + u32 status3;
17671 + u32 status4;
17672 + u32 status5;
17673 + u32 status6;
17674 + u32 status7;
17675 + u32 status8;
17676 + u32 status9;
17677 + u32 status10;
17678 + u32 status11;
17679 +} __packed;
17680 +
17681 +/* Transmit Control Descriptor */
17682 +struct ar9003_txc {
17683 + u32 info; /* descriptor information */
17684 + u32 link; /* link pointer */
17685 + u32 data0; /* data pointer to 1st buffer */
17686 + u32 ctl3; /* DMA control 3 */
17687 + u32 data1; /* data pointer to 2nd buffer */
17688 + u32 ctl5; /* DMA control 5 */
17689 + u32 data2; /* data pointer to 3rd buffer */
17690 + u32 ctl7; /* DMA control 7 */
17691 + u32 data3; /* data pointer to 4th buffer */
17692 + u32 ctl9; /* DMA control 9 */
17693 + u32 ctl10; /* DMA control 10 */
17694 + u32 ctl11; /* DMA control 11 */
17695 + u32 ctl12; /* DMA control 12 */
17696 + u32 ctl13; /* DMA control 13 */
17697 + u32 ctl14; /* DMA control 14 */
17698 + u32 ctl15; /* DMA control 15 */
17699 + u32 ctl16; /* DMA control 16 */
17700 + u32 ctl17; /* DMA control 17 */
17701 + u32 ctl18; /* DMA control 18 */
17702 + u32 ctl19; /* DMA control 19 */
17703 + u32 ctl20; /* DMA control 20 */
17704 + u32 ctl21; /* DMA control 21 */
17705 + u32 ctl22; /* DMA control 22 */
17706 + u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
17707 +} __packed;
17708 +
17709 +struct ar9003_txs {
17710 + u32 ds_info;
17711 + u32 status1;
17712 + u32 status2;
17713 + u32 status3;
17714 + u32 status4;
17715 + u32 status5;
17716 + u32 status6;
17717 + u32 status7;
17718 + u32 status8;
17719 +} __packed;
17720 +
17721 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
17722 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
17723 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
17724 + enum ath9k_rx_qtype qtype);
17725 +
17726 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
17727 + struct ath_rx_status *rxs,
17728 + void *buf_addr);
17729 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
17730 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
17731 + u32 ts_paddr_start,
17732 + u8 size);
17733 +#endif
17734 --- /dev/null
17735 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
17736 @@ -0,0 +1,1142 @@
17737 +/*
17738 + * Copyright (c) 2010 Atheros Communications Inc.
17739 + *
17740 + * Permission to use, copy, modify, and/or distribute this software for any
17741 + * purpose with or without fee is hereby granted, provided that the above
17742 + * copyright notice and this permission notice appear in all copies.
17743 + *
17744 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17745 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17746 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17747 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17748 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17749 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17750 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17751 + */
17752 +
17753 +#include "hw.h"
17754 +#include "ar9003_phy.h"
17755 +
17756 +/**
17757 + * ar9003_hw_set_channel - set channel on single-chip device
17758 + * @ah: atheros hardware structure
17759 + * @chan:
17760 + *
17761 + * This is the function to change channel on single-chip devices, that is
17762 + * all devices after ar9280.
17763 + *
17764 + * This function takes the channel value in MHz and sets
17765 + * hardware channel value. Assumes writes have been enabled to analog bus.
17766 + *
17767 + * Actual Expression,
17768 + *
17769 + * For 2GHz channel,
17770 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
17771 + * (freq_ref = 40MHz)
17772 + *
17773 + * For 5GHz channel,
17774 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
17775 + * (freq_ref = 40MHz/(24>>amodeRefSel))
17776 + *
17777 + * For 5GHz channels which are 5MHz spaced,
17778 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
17779 + * (freq_ref = 40MHz)
17780 + */
17781 +static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
17782 +{
17783 + u16 bMode, fracMode = 0, aModeRefSel = 0;
17784 + u32 freq, channelSel = 0, reg32 = 0;
17785 + struct chan_centers centers;
17786 + int loadSynthChannel;
17787 +
17788 + ath9k_hw_get_channel_centers(ah, chan, &centers);
17789 + freq = centers.synth_center;
17790 +
17791 + if (freq < 4800) { /* 2 GHz, fractional mode */
17792 + channelSel = CHANSEL_2G(freq);
17793 + /* Set to 2G mode */
17794 + bMode = 1;
17795 + } else {
17796 + channelSel = CHANSEL_5G(freq);
17797 + /* Doubler is ON, so, divide channelSel by 2. */
17798 + channelSel >>= 1;
17799 + /* Set to 5G mode */
17800 + bMode = 0;
17801 + }
17802 +
17803 + /* Enable fractional mode for all channels */
17804 + fracMode = 1;
17805 + aModeRefSel = 0;
17806 + loadSynthChannel = 0;
17807 +
17808 + reg32 = (bMode << 29);
17809 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
17810 +
17811 + /* Enable Long shift Select for Synthesizer */
17812 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
17813 + AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
17814 +
17815 + /* Program Synth. setting */
17816 + reg32 = (channelSel << 2) | (fracMode << 30) |
17817 + (aModeRefSel << 28) | (loadSynthChannel << 31);
17818 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
17819 +
17820 + /* Toggle Load Synth channel bit */
17821 + loadSynthChannel = 1;
17822 + reg32 = (channelSel << 2) | (fracMode << 30) |
17823 + (aModeRefSel << 28) | (loadSynthChannel << 31);
17824 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
17825 +
17826 + ah->curchan = chan;
17827 + ah->curchan_rad_index = -1;
17828 +
17829 + return 0;
17830 +}
17831 +
17832 +/**
17833 + * ar9003_hw_spur_mitigate - convert baseband spur frequency
17834 + * @ah: atheros hardware structure
17835 + * @chan:
17836 + *
17837 + * For single-chip solutions. Converts to baseband spur frequency given the
17838 + * input channel frequency and compute register settings below.
17839 + *
17840 + * Spur mitigation for MRC CCK
17841 + */
17842 +static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
17843 + struct ath9k_channel *chan)
17844 +{
17845 + u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
17846 + int cur_bb_spur, negative = 0, cck_spur_freq;
17847 + int i;
17848 +
17849 + /*
17850 + * Need to verify range +/- 10 MHz in control channel, otherwise spur
17851 + * is out-of-band and can be ignored.
17852 + */
17853 +
17854 + for (i = 0; i < 4; i++) {
17855 + negative = 0;
17856 + cur_bb_spur = spur_freq[i] - chan->channel;
17857 +
17858 + if (cur_bb_spur < 0) {
17859 + negative = 1;
17860 + cur_bb_spur = -cur_bb_spur;
17861 + }
17862 + if (cur_bb_spur < 10) {
17863 + cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
17864 +
17865 + if (negative == 1)
17866 + cck_spur_freq = -cck_spur_freq;
17867 +
17868 + cck_spur_freq = cck_spur_freq & 0xfffff;
17869 +
17870 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
17871 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
17872 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17873 + AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
17874 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17875 + AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
17876 + 0x2);
17877 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17878 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
17879 + 0x1);
17880 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17881 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
17882 + cck_spur_freq);
17883 +
17884 + return;
17885 + }
17886 + }
17887 +
17888 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
17889 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
17890 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17891 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
17892 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
17893 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
17894 +}
17895 +
17896 +/* Clean all spur register fields */
17897 +static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
17898 +{
17899 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17900 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
17901 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17902 + AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
17903 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17904 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
17905 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
17906 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
17907 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17908 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
17909 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17910 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
17911 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17912 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
17913 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17914 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
17915 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17916 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
17917 +
17918 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17919 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
17920 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17921 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
17922 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17923 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
17924 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17925 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
17926 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17927 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
17928 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17929 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
17930 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17931 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
17932 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17933 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
17934 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17935 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
17936 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17937 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
17938 +}
17939 +
17940 +static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
17941 + int freq_offset,
17942 + int spur_freq_sd,
17943 + int spur_delta_phase,
17944 + int spur_subchannel_sd)
17945 +{
17946 + int mask_index = 0;
17947 +
17948 + /* OFDM Spur mitigation */
17949 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17950 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
17951 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17952 + AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
17953 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17954 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
17955 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
17956 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
17957 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17958 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
17959 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
17960 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
17961 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17962 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
17963 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17964 + AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
17965 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17966 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
17967 +
17968 + if (REG_READ_FIELD(ah, AR_PHY_MODE,
17969 + AR_PHY_MODE_DYNAMIC) == 0x1)
17970 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17971 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
17972 +
17973 + mask_index = (freq_offset << 4) / 5;
17974 + if (mask_index < 0)
17975 + mask_index = mask_index - 1;
17976 +
17977 + mask_index = mask_index & 0x7f;
17978 +
17979 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17980 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
17981 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17982 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
17983 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
17984 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
17985 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17986 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
17987 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17988 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
17989 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17990 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
17991 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
17992 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
17993 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
17994 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
17995 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
17996 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
17997 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
17998 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
17999 +}
18000 +
18001 +static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
18002 + struct ath9k_channel *chan,
18003 + int freq_offset)
18004 +{
18005 + int spur_freq_sd = 0;
18006 + int spur_subchannel_sd = 0;
18007 + int spur_delta_phase = 0;
18008 +
18009 + if (IS_CHAN_HT40(chan)) {
18010 + if (freq_offset < 0) {
18011 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
18012 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
18013 + spur_subchannel_sd = 1;
18014 + else
18015 + spur_subchannel_sd = 0;
18016 +
18017 + spur_freq_sd = ((freq_offset + 10) << 9) / 11;
18018 +
18019 + } else {
18020 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
18021 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
18022 + spur_subchannel_sd = 0;
18023 + else
18024 + spur_subchannel_sd = 1;
18025 +
18026 + spur_freq_sd = ((freq_offset - 10) << 9) / 11;
18027 +
18028 + }
18029 +
18030 + spur_delta_phase = (freq_offset << 17) / 5;
18031 +
18032 + } else {
18033 + spur_subchannel_sd = 0;
18034 + spur_freq_sd = (freq_offset << 9) /11;
18035 + spur_delta_phase = (freq_offset << 18) / 5;
18036 + }
18037 +
18038 + spur_freq_sd = spur_freq_sd & 0x3ff;
18039 + spur_delta_phase = spur_delta_phase & 0xfffff;
18040 +
18041 + ar9003_hw_spur_ofdm(ah,
18042 + freq_offset,
18043 + spur_freq_sd,
18044 + spur_delta_phase,
18045 + spur_subchannel_sd);
18046 +}
18047 +
18048 +/* Spur mitigation for OFDM */
18049 +static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
18050 + struct ath9k_channel *chan)
18051 +{
18052 + int synth_freq;
18053 + int range = 10;
18054 + int freq_offset = 0;
18055 + int mode;
18056 + u8* spurChansPtr;
18057 + unsigned int i;
18058 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
18059 +
18060 + if (IS_CHAN_5GHZ(chan)) {
18061 + spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
18062 + mode = 0;
18063 + }
18064 + else {
18065 + spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
18066 + mode = 1;
18067 + }
18068 +
18069 + if (spurChansPtr[0] == 0)
18070 + return; /* No spur in the mode */
18071 +
18072 + if (IS_CHAN_HT40(chan)) {
18073 + range = 19;
18074 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
18075 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
18076 + synth_freq = chan->channel - 10;
18077 + else
18078 + synth_freq = chan->channel + 10;
18079 + } else {
18080 + range = 10;
18081 + synth_freq = chan->channel;
18082 + }
18083 +
18084 + ar9003_hw_spur_ofdm_clear(ah);
18085 +
18086 + for (i = 0; spurChansPtr[i] && i < 5; i++) {
18087 + freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
18088 + if (abs(freq_offset) < range) {
18089 + ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
18090 + break;
18091 + }
18092 + }
18093 +}
18094 +
18095 +static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
18096 + struct ath9k_channel *chan)
18097 +{
18098 + ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
18099 + ar9003_hw_spur_mitigate_ofdm(ah, chan);
18100 +}
18101 +
18102 +static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
18103 + struct ath9k_channel *chan)
18104 +{
18105 + u32 pll;
18106 +
18107 + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
18108 +
18109 + if (chan && IS_CHAN_HALF_RATE(chan))
18110 + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
18111 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
18112 + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
18113 +
18114 + if (chan && IS_CHAN_5GHZ(chan)) {
18115 + pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
18116 +
18117 + /*
18118 + * When doing fast clock, set PLL to 0x142c
18119 + */
18120 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18121 + pll = 0x142c;
18122 + } else
18123 + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
18124 +
18125 + return pll;
18126 +}
18127 +
18128 +static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
18129 + struct ath9k_channel *chan)
18130 +{
18131 + u32 phymode;
18132 + u32 enableDacFifo = 0;
18133 +
18134 + enableDacFifo =
18135 + (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
18136 +
18137 + /* Enable 11n HT, 20 MHz */
18138 + phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
18139 + AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
18140 +
18141 + /* Configure baseband for dynamic 20/40 operation */
18142 + if (IS_CHAN_HT40(chan)) {
18143 + phymode |= AR_PHY_GC_DYN2040_EN;
18144 + /* Configure control (primary) channel at +-10MHz */
18145 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
18146 + (chan->chanmode == CHANNEL_G_HT40PLUS))
18147 + phymode |= AR_PHY_GC_DYN2040_PRI_CH;
18148 +
18149 + }
18150 +
18151 + /* make sure we preserve INI settings */
18152 + phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
18153 + /* turn off Green Field detection for STA for now */
18154 + phymode &= ~AR_PHY_GC_GF_DETECT_EN;
18155 +
18156 + REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
18157 +
18158 + /* Configure MAC for 20/40 operation */
18159 + ath9k_hw_set11nmac2040(ah);
18160 +
18161 + /* global transmit timeout (25 TUs default)*/
18162 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
18163 + /* carrier sense timeout */
18164 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
18165 +}
18166 +
18167 +static void ar9003_hw_init_bb(struct ath_hw *ah,
18168 + struct ath9k_channel *chan)
18169 +{
18170 + u32 synthDelay;
18171 +
18172 + /*
18173 + * Wait for the frequency synth to settle (synth goes on
18174 + * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
18175 + * Value is in 100ns increments.
18176 + */
18177 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
18178 + if (IS_CHAN_B(chan))
18179 + synthDelay = (4 * synthDelay) / 22;
18180 + else
18181 + synthDelay /= 10;
18182 +
18183 + /* Activate the PHY (includes baseband activate + synthesizer on) */
18184 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
18185 +
18186 + /*
18187 + * There is an issue if the AP starts the calibration before
18188 + * the base band timeout completes. This could result in the
18189 + * rx_clear false triggering. As a workaround we add delay an
18190 + * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
18191 + * does not happen.
18192 + */
18193 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
18194 +}
18195 +
18196 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
18197 +{
18198 + switch (rx) {
18199 + case 0x5:
18200 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
18201 + AR_PHY_SWAP_ALT_CHAIN);
18202 + case 0x3:
18203 + case 0x1:
18204 + case 0x2:
18205 + case 0x7:
18206 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
18207 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
18208 + break;
18209 + default:
18210 + break;
18211 + }
18212 +
18213 + REG_WRITE(ah, AR_SELFGEN_MASK, tx);
18214 + if (tx == 0x5) {
18215 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
18216 + AR_PHY_SWAP_ALT_CHAIN);
18217 + }
18218 +}
18219 +
18220 +/*
18221 + * Override INI values with chip specific configuration.
18222 + */
18223 +static void ar9003_hw_override_ini(struct ath_hw *ah)
18224 +{
18225 + u32 val;
18226 +
18227 + /*
18228 + * Set the RX_ABORT and RX_DIS and clear it only after
18229 + * RXE is set for MAC. This prevents frames with
18230 + * corrupted descriptor status.
18231 + */
18232 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
18233 +
18234 + /*
18235 + * For AR9280 and above, there is a new feature that allows
18236 + * Multicast search based on both MAC Address and Key ID. By default,
18237 + * this feature is enabled. But since the driver is not using this
18238 + * feature, we switch it off; otherwise multicast search based on
18239 + * MAC addr only will fail.
18240 + */
18241 + val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
18242 + REG_WRITE(ah, AR_PCU_MISC_MODE2,
18243 + val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
18244 +}
18245 +
18246 +static void ar9003_hw_prog_ini(struct ath_hw *ah,
18247 + struct ar5416IniArray *iniArr,
18248 + int column)
18249 +{
18250 + unsigned int i, regWrites = 0;
18251 +
18252 + /* New INI format: Array may be undefined (pre, core, post arrays) */
18253 + if (!iniArr->ia_array)
18254 + return;
18255 +
18256 + /*
18257 + * New INI format: Pre, core, and post arrays for a given subsystem
18258 + * may be modal (> 2 columns) or non-modal (2 columns). Determine if
18259 + * the array is non-modal and force the column to 1.
18260 + */
18261 + if (column >= iniArr->ia_columns)
18262 + column = 1;
18263 +
18264 + for (i = 0; i < iniArr->ia_rows; i++) {
18265 + u32 reg = INI_RA(iniArr, i, 0);
18266 + u32 val = INI_RA(iniArr, i, column);
18267 +
18268 + REG_WRITE(ah, reg, val);
18269 +
18270 + /*
18271 + * Determine if this is a shift register value, and insert the
18272 + * configured delay if so.
18273 + */
18274 + if (reg >= 0x16000 && reg < 0x17000
18275 + && ah->config.analog_shiftreg)
18276 + udelay(100);
18277 +
18278 + DO_DELAY(regWrites);
18279 + }
18280 +}
18281 +
18282 +static int ar9003_hw_process_ini(struct ath_hw *ah,
18283 + struct ath9k_channel *chan)
18284 +{
18285 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
18286 + unsigned int regWrites = 0, i;
18287 + struct ieee80211_channel *channel = chan->chan;
18288 + u32 modesIndex, freqIndex;
18289 +
18290 + switch (chan->chanmode) {
18291 + case CHANNEL_A:
18292 + case CHANNEL_A_HT20:
18293 + modesIndex = 1;
18294 + freqIndex = 1;
18295 + break;
18296 + case CHANNEL_A_HT40PLUS:
18297 + case CHANNEL_A_HT40MINUS:
18298 + modesIndex = 2;
18299 + freqIndex = 1;
18300 + break;
18301 + case CHANNEL_G:
18302 + case CHANNEL_G_HT20:
18303 + case CHANNEL_B:
18304 + modesIndex = 4;
18305 + freqIndex = 2;
18306 + break;
18307 + case CHANNEL_G_HT40PLUS:
18308 + case CHANNEL_G_HT40MINUS:
18309 + modesIndex = 3;
18310 + freqIndex = 2;
18311 + break;
18312 +
18313 + default:
18314 + return -EINVAL;
18315 + }
18316 +
18317 + for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
18318 + ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
18319 + ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
18320 + ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
18321 + ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
18322 + }
18323 +
18324 + REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
18325 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
18326 +
18327 + /*
18328 + * For 5GHz channels requiring Fast Clock, apply
18329 + * different modal values.
18330 + */
18331 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18332 + REG_WRITE_ARRAY(&ah->iniModesAdditional,
18333 + modesIndex, regWrites);
18334 +
18335 + ar9003_hw_override_ini(ah);
18336 + ar9003_hw_set_channel_regs(ah, chan);
18337 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
18338 +
18339 + /* Set TX power */
18340 + ah->eep_ops->set_txpower(ah, chan,
18341 + ath9k_regd_get_ctl(regulatory, chan),
18342 + channel->max_antenna_gain * 2,
18343 + channel->max_power * 2,
18344 + min((u32) MAX_RATE_POWER,
18345 + (u32) regulatory->power_limit));
18346 +
18347 + return 0;
18348 +}
18349 +
18350 +static void ar9003_hw_set_rfmode(struct ath_hw *ah,
18351 + struct ath9k_channel *chan)
18352 +{
18353 + u32 rfMode = 0;
18354 +
18355 + if (chan == NULL)
18356 + return;
18357 +
18358 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
18359 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
18360 +
18361 + if (IS_CHAN_A_5MHZ_SPACED(chan))
18362 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
18363 +
18364 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
18365 +}
18366 +
18367 +static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
18368 +{
18369 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
18370 +}
18371 +
18372 +static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
18373 + struct ath9k_channel *chan)
18374 +{
18375 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
18376 + u32 clockMhzScaled = 0x64000000;
18377 + struct chan_centers centers;
18378 +
18379 + /*
18380 + * half and quarter rate can divide the scaled clock by 2 or 4
18381 + * scale for selected channel bandwidth
18382 + */
18383 + if (IS_CHAN_HALF_RATE(chan))
18384 + clockMhzScaled = clockMhzScaled >> 1;
18385 + else if (IS_CHAN_QUARTER_RATE(chan))
18386 + clockMhzScaled = clockMhzScaled >> 2;
18387 +
18388 + /*
18389 + * ALGO -> coef = 1e8/fcarrier*fclock/40;
18390 + * scaled coef to provide precision for this floating calculation
18391 + */
18392 + ath9k_hw_get_channel_centers(ah, chan, &centers);
18393 + coef_scaled = clockMhzScaled / centers.synth_center;
18394 +
18395 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
18396 + &ds_coef_exp);
18397 +
18398 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
18399 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
18400 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
18401 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
18402 +
18403 + /*
18404 + * For Short GI,
18405 + * scaled coeff is 9/10 that of normal coeff
18406 + */
18407 + coef_scaled = (9 * coef_scaled) / 10;
18408 +
18409 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
18410 + &ds_coef_exp);
18411 +
18412 + /* for short gi */
18413 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
18414 + AR_PHY_SGI_DSC_MAN, ds_coef_man);
18415 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
18416 + AR_PHY_SGI_DSC_EXP, ds_coef_exp);
18417 +}
18418 +
18419 +static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
18420 +{
18421 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
18422 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
18423 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
18424 +}
18425 +
18426 +/*
18427 + * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
18428 + * Read the phy active delay register. Value is in 100ns increments.
18429 + */
18430 +static void ar9003_hw_rfbus_done(struct ath_hw *ah)
18431 +{
18432 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
18433 + if (IS_CHAN_B(ah->curchan))
18434 + synthDelay = (4 * synthDelay) / 22;
18435 + else
18436 + synthDelay /= 10;
18437 +
18438 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
18439 +
18440 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
18441 +}
18442 +
18443 +/*
18444 + * Set the interrupt and GPIO values so the ISR can disable RF
18445 + * on a switch signal. Assumes GPIO port and interrupt polarity
18446 + * are set prior to call.
18447 + */
18448 +static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
18449 +{
18450 + /* Connect rfsilent_bb_l to baseband */
18451 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
18452 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
18453 + /* Set input mux for rfsilent_bb_l to GPIO #0 */
18454 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
18455 + AR_GPIO_INPUT_MUX2_RFSILENT);
18456 +
18457 + /*
18458 + * Configure the desired GPIO port for input and
18459 + * enable baseband rf silence.
18460 + */
18461 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
18462 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
18463 +}
18464 +
18465 +static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
18466 +{
18467 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
18468 + if (value)
18469 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
18470 + else
18471 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
18472 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
18473 +}
18474 +
18475 +static bool ar9003_hw_ani_control(struct ath_hw *ah,
18476 + enum ath9k_ani_cmd cmd, int param)
18477 +{
18478 + struct ar5416AniState *aniState = ah->curani;
18479 + struct ath_common *common = ath9k_hw_common(ah);
18480 +
18481 + switch (cmd & ah->ani_function) {
18482 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
18483 + u32 level = param;
18484 +
18485 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
18486 + ath_print(common, ATH_DBG_ANI,
18487 + "level out of range (%u > %u)\n",
18488 + level,
18489 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
18490 + return false;
18491 + }
18492 +
18493 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
18494 + AR_PHY_DESIRED_SZ_TOT_DES,
18495 + ah->totalSizeDesired[level]);
18496 + REG_RMW_FIELD(ah, AR_PHY_AGC,
18497 + AR_PHY_AGC_COARSE_LOW,
18498 + ah->coarse_low[level]);
18499 + REG_RMW_FIELD(ah, AR_PHY_AGC,
18500 + AR_PHY_AGC_COARSE_HIGH,
18501 + ah->coarse_high[level]);
18502 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
18503 + AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
18504 +
18505 + if (level > aniState->noiseImmunityLevel)
18506 + ah->stats.ast_ani_niup++;
18507 + else if (level < aniState->noiseImmunityLevel)
18508 + ah->stats.ast_ani_nidown++;
18509 + aniState->noiseImmunityLevel = level;
18510 + break;
18511 + }
18512 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
18513 + const int m1ThreshLow[] = { 127, 50 };
18514 + const int m2ThreshLow[] = { 127, 40 };
18515 + const int m1Thresh[] = { 127, 0x4d };
18516 + const int m2Thresh[] = { 127, 0x40 };
18517 + const int m2CountThr[] = { 31, 16 };
18518 + const int m2CountThrLow[] = { 63, 48 };
18519 + u32 on = param ? 1 : 0;
18520 +
18521 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18522 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
18523 + m1ThreshLow[on]);
18524 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18525 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
18526 + m2ThreshLow[on]);
18527 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18528 + AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
18529 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18530 + AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
18531 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
18532 + AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
18533 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
18534 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
18535 + m2CountThrLow[on]);
18536 +
18537 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18538 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
18539 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18540 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
18541 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18542 + AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
18543 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
18544 + AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
18545 +
18546 + if (on)
18547 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
18548 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
18549 + else
18550 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
18551 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
18552 +
18553 + if (!on != aniState->ofdmWeakSigDetectOff) {
18554 + if (on)
18555 + ah->stats.ast_ani_ofdmon++;
18556 + else
18557 + ah->stats.ast_ani_ofdmoff++;
18558 + aniState->ofdmWeakSigDetectOff = !on;
18559 + }
18560 + break;
18561 + }
18562 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
18563 + const int weakSigThrCck[] = { 8, 6 };
18564 + u32 high = param ? 1 : 0;
18565 +
18566 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
18567 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
18568 + weakSigThrCck[high]);
18569 + if (high != aniState->cckWeakSigThreshold) {
18570 + if (high)
18571 + ah->stats.ast_ani_cckhigh++;
18572 + else
18573 + ah->stats.ast_ani_ccklow++;
18574 + aniState->cckWeakSigThreshold = high;
18575 + }
18576 + break;
18577 + }
18578 + case ATH9K_ANI_FIRSTEP_LEVEL:{
18579 + const int firstep[] = { 0, 4, 8 };
18580 + u32 level = param;
18581 +
18582 + if (level >= ARRAY_SIZE(firstep)) {
18583 + ath_print(common, ATH_DBG_ANI,
18584 + "level out of range (%u > %u)\n",
18585 + level,
18586 + (unsigned) ARRAY_SIZE(firstep));
18587 + return false;
18588 + }
18589 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
18590 + AR_PHY_FIND_SIG_FIRSTEP,
18591 + firstep[level]);
18592 + if (level > aniState->firstepLevel)
18593 + ah->stats.ast_ani_stepup++;
18594 + else if (level < aniState->firstepLevel)
18595 + ah->stats.ast_ani_stepdown++;
18596 + aniState->firstepLevel = level;
18597 + break;
18598 + }
18599 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
18600 + const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
18601 + u32 level = param;
18602 +
18603 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
18604 + ath_print(common, ATH_DBG_ANI,
18605 + "level out of range (%u > %u)\n",
18606 + level,
18607 + (unsigned) ARRAY_SIZE(cycpwrThr1));
18608 + return false;
18609 + }
18610 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
18611 + AR_PHY_TIMING5_CYCPWR_THR1,
18612 + cycpwrThr1[level]);
18613 + if (level > aniState->spurImmunityLevel)
18614 + ah->stats.ast_ani_spurup++;
18615 + else if (level < aniState->spurImmunityLevel)
18616 + ah->stats.ast_ani_spurdown++;
18617 + aniState->spurImmunityLevel = level;
18618 + break;
18619 + }
18620 + case ATH9K_ANI_PRESENT:
18621 + break;
18622 + default:
18623 + ath_print(common, ATH_DBG_ANI,
18624 + "invalid cmd %u\n", cmd);
18625 + return false;
18626 + }
18627 +
18628 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
18629 + ath_print(common, ATH_DBG_ANI,
18630 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
18631 + "ofdmWeakSigDetectOff=%d\n",
18632 + aniState->noiseImmunityLevel,
18633 + aniState->spurImmunityLevel,
18634 + !aniState->ofdmWeakSigDetectOff);
18635 + ath_print(common, ATH_DBG_ANI,
18636 + "cckWeakSigThreshold=%d, "
18637 + "firstepLevel=%d, listenTime=%d\n",
18638 + aniState->cckWeakSigThreshold,
18639 + aniState->firstepLevel,
18640 + aniState->listenTime);
18641 + ath_print(common, ATH_DBG_ANI,
18642 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
18643 + aniState->cycleCount,
18644 + aniState->ofdmPhyErrCount,
18645 + aniState->cckPhyErrCount);
18646 +
18647 + return true;
18648 +}
18649 +
18650 +static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
18651 +{
18652 + struct ath_common *common = ath9k_hw_common(ah);
18653 +
18654 + if (*nf > ah->nf_2g_max) {
18655 + ath_print(common, ATH_DBG_CALIBRATE,
18656 + "2 GHz NF (%d) > MAX (%d), "
18657 + "correcting to MAX",
18658 + *nf, ah->nf_2g_max);
18659 + *nf = ah->nf_2g_max;
18660 + } else if (*nf < ah->nf_2g_min) {
18661 + ath_print(common, ATH_DBG_CALIBRATE,
18662 + "2 GHz NF (%d) < MIN (%d), "
18663 + "correcting to MIN",
18664 + *nf, ah->nf_2g_min);
18665 + *nf = ah->nf_2g_min;
18666 + }
18667 +}
18668 +
18669 +static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
18670 +{
18671 + struct ath_common *common = ath9k_hw_common(ah);
18672 +
18673 + if (*nf > ah->nf_5g_max) {
18674 + ath_print(common, ATH_DBG_CALIBRATE,
18675 + "5 GHz NF (%d) > MAX (%d), "
18676 + "correcting to MAX",
18677 + *nf, ah->nf_5g_max);
18678 + *nf = ah->nf_5g_max;
18679 + } else if (*nf < ah->nf_5g_min) {
18680 + ath_print(common, ATH_DBG_CALIBRATE,
18681 + "5 GHz NF (%d) < MIN (%d), "
18682 + "correcting to MIN",
18683 + *nf, ah->nf_5g_min);
18684 + *nf = ah->nf_5g_min;
18685 + }
18686 +}
18687 +
18688 +static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
18689 +{
18690 + if (IS_CHAN_2GHZ(ah->curchan))
18691 + ar9003_hw_nf_sanitize_2g(ah, nf);
18692 + else
18693 + ar9003_hw_nf_sanitize_5g(ah, nf);
18694 +}
18695 +
18696 +static void ar9003_hw_do_getnf(struct ath_hw *ah,
18697 + int16_t nfarray[NUM_NF_READINGS])
18698 +{
18699 + struct ath_common *common = ath9k_hw_common(ah);
18700 + int16_t nf;
18701 +
18702 + nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
18703 + if (nf & 0x100)
18704 + nf = 0 - ((nf ^ 0x1ff) + 1);
18705 + ar9003_hw_nf_sanitize(ah, &nf);
18706 + ath_print(common, ATH_DBG_CALIBRATE,
18707 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
18708 + nfarray[0] = nf;
18709 +
18710 + nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
18711 + if (nf & 0x100)
18712 + nf = 0 - ((nf ^ 0x1ff) + 1);
18713 + ar9003_hw_nf_sanitize(ah, &nf);
18714 + ath_print(common, ATH_DBG_CALIBRATE,
18715 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
18716 + nfarray[1] = nf;
18717 +
18718 + nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
18719 + if (nf & 0x100)
18720 + nf = 0 - ((nf ^ 0x1ff) + 1);
18721 + ar9003_hw_nf_sanitize(ah, &nf);
18722 + ath_print(common, ATH_DBG_CALIBRATE,
18723 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
18724 + nfarray[2] = nf;
18725 +
18726 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
18727 + if (nf & 0x100)
18728 + nf = 0 - ((nf ^ 0x1ff) + 1);
18729 + ar9003_hw_nf_sanitize(ah, &nf);
18730 + ath_print(common, ATH_DBG_CALIBRATE,
18731 + "NF calibrated [ext] [chain 0] is %d\n", nf);
18732 + nfarray[3] = nf;
18733 +
18734 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
18735 + if (nf & 0x100)
18736 + nf = 0 - ((nf ^ 0x1ff) + 1);
18737 + ar9003_hw_nf_sanitize(ah, &nf);
18738 + ath_print(common, ATH_DBG_CALIBRATE,
18739 + "NF calibrated [ext] [chain 1] is %d\n", nf);
18740 + nfarray[4] = nf;
18741 +
18742 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
18743 + if (nf & 0x100)
18744 + nf = 0 - ((nf ^ 0x1ff) + 1);
18745 + ar9003_hw_nf_sanitize(ah, &nf);
18746 + ath_print(common, ATH_DBG_CALIBRATE,
18747 + "NF calibrated [ext] [chain 2] is %d\n", nf);
18748 + nfarray[5] = nf;
18749 +}
18750 +
18751 +void ar9003_hw_set_nf_limits(struct ath_hw *ah)
18752 +{
18753 + ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
18754 + ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
18755 + ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
18756 + ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
18757 +}
18758 +
18759 +/*
18760 + * Find out which of the RX chains are enabled
18761 + */
18762 +static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
18763 +{
18764 + u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
18765 + /*
18766 + * The bits [2:0] indicate the rx chain mask and are to be
18767 + * interpreted as follows:
18768 + * 00x => Only chain 0 is enabled
18769 + * 01x => Chain 1 and 0 enabled
18770 + * 1xx => Chain 2,1 and 0 enabled
18771 + */
18772 + return chain & 0x7;
18773 +}
18774 +
18775 +static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
18776 +{
18777 + struct ath9k_nfcal_hist *h;
18778 + unsigned i, j;
18779 + int32_t val;
18780 + const u32 ar9300_cca_regs[6] = {
18781 + AR_PHY_CCA_0,
18782 + AR_PHY_CCA_1,
18783 + AR_PHY_CCA_2,
18784 + AR_PHY_EXT_CCA,
18785 + AR_PHY_EXT_CCA_1,
18786 + AR_PHY_EXT_CCA_2,
18787 + };
18788 + u8 chainmask, rx_chain_status;
18789 + struct ath_common *common = ath9k_hw_common(ah);
18790 +
18791 + rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
18792 +
18793 + chainmask = 0x3F;
18794 + h = ah->nfCalHist;
18795 +
18796 + for (i = 0; i < NUM_NF_READINGS; i++) {
18797 + if (chainmask & (1 << i)) {
18798 + val = REG_READ(ah, ar9300_cca_regs[i]);
18799 + val &= 0xFFFFFE00;
18800 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
18801 + REG_WRITE(ah, ar9300_cca_regs[i], val);
18802 + }
18803 + }
18804 +
18805 + /*
18806 + * Load software filtered NF value into baseband internal minCCApwr
18807 + * variable.
18808 + */
18809 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
18810 + AR_PHY_AGC_CONTROL_ENABLE_NF);
18811 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
18812 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
18813 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
18814 +
18815 + /*
18816 + * Wait for load to complete, should be fast, a few 10s of us.
18817 + * The max delay was changed from an original 250us to 10000us
18818 + * since 250us often results in NF load timeout and causes deaf
18819 + * condition during stress testing 12/12/2009
18820 + */
18821 + for (j = 0; j < 1000; j++) {
18822 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
18823 + AR_PHY_AGC_CONTROL_NF) == 0)
18824 + break;
18825 + udelay(10);
18826 + }
18827 +
18828 + /*
18829 + * We timed out waiting for the noisefloor to load, probably due to an
18830 + * in-progress rx. Simply return here and allow the load plenty of time
18831 + * to complete before the next calibration interval. We need to avoid
18832 + * trying to load -50 (which happens below) while the previous load is
18833 + * still in progress as this can cause rx deafness. Instead by returning
18834 + * here, the baseband nf cal will just be capped by our present
18835 + * noisefloor until the next calibration timer.
18836 + */
18837 + if (j == 1000) {
18838 + ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
18839 + "to load: AR_PHY_AGC_CONTROL=0x%x\n",
18840 + REG_READ(ah, AR_PHY_AGC_CONTROL));
18841 + }
18842 +
18843 + /*
18844 + * Restore maxCCAPower register parameter again so that we're not capped
18845 + * by the median we just loaded. This will be initial (and max) value
18846 + * of next noise floor calibration the baseband does.
18847 + */
18848 + for (i = 0; i < NUM_NF_READINGS; i++) {
18849 + if (chainmask & (1 << i)) {
18850 + val = REG_READ(ah, ar9300_cca_regs[i]);
18851 + val &= 0xFFFFFE00;
18852 + val |= (((u32) (-50) << 1) & 0x1ff);
18853 + REG_WRITE(ah, ar9300_cca_regs[i], val);
18854 + }
18855 + }
18856 +}
18857 +
18858 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
18859 +{
18860 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
18861 +
18862 + priv_ops->rf_set_freq = ar9003_hw_set_channel;
18863 + priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
18864 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
18865 + priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
18866 + priv_ops->init_bb = ar9003_hw_init_bb;
18867 + priv_ops->process_ini = ar9003_hw_process_ini;
18868 + priv_ops->set_rfmode = ar9003_hw_set_rfmode;
18869 + priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
18870 + priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
18871 + priv_ops->rfbus_req = ar9003_hw_rfbus_req;
18872 + priv_ops->rfbus_done = ar9003_hw_rfbus_done;
18873 + priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
18874 + priv_ops->set_diversity = ar9003_hw_set_diversity;
18875 + priv_ops->ani_control = ar9003_hw_ani_control;
18876 + priv_ops->do_getnf = ar9003_hw_do_getnf;
18877 + priv_ops->loadnf = ar9003_hw_loadnf;
18878 +}
18879 --- /dev/null
18880 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
18881 @@ -0,0 +1,847 @@
18882 +/*
18883 + * Copyright (c) 2002-2010 Atheros Communications, Inc.
18884 + *
18885 + * Permission to use, copy, modify, and/or distribute this software for any
18886 + * purpose with or without fee is hereby granted, provided that the above
18887 + * copyright notice and this permission notice appear in all copies.
18888 + *
18889 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
18890 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18891 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18892 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18893 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18894 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18895 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18896 + */
18897 +
18898 +#ifndef AR9003_PHY_H
18899 +#define AR9003_PHY_H
18900 +
18901 +/*
18902 + * Channel Register Map
18903 + */
18904 +#define AR_CHAN_BASE 0x9800
18905 +
18906 +#define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
18907 +#define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
18908 +#define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
18909 +#define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
18910 +#define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
18911 +#define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
18912 +#define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
18913 +#define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
18914 +#define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
18915 +#define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
18916 +
18917 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
18918 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
18919 +
18920 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
18921 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
18922 +
18923 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
18924 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
18925 +
18926 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
18927 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
18928 +
18929 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
18930 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
18931 +
18932 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
18933 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
18934 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
18935 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
18936 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
18937 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
18938 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
18939 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
18940 +
18941 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
18942 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
18943 +
18944 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
18945 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
18946 +
18947 +#define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
18948 +
18949 +#define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
18950 +#define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
18951 +#define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
18952 +
18953 +#define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
18954 +#define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
18955 +#define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
18956 +#define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
18957 +#define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
18958 +#define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
18959 +
18960 +#define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
18961 +#define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
18962 +#define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
18963 +#define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
18964 +#define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
18965 +#define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
18966 +
18967 +/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
18968 +#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
18969 +#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
18970 +#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
18971 +#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
18972 +#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
18973 +#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
18974 +
18975 +#define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
18976 +#define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
18977 +#define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
18978 +#define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
18979 +
18980 +/*
18981 + * Channel Field Definitions
18982 + */
18983 +#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
18984 +#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
18985 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
18986 +#define AR_PHY_TIMING3_DSC_MAN_S 17
18987 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
18988 +#define AR_PHY_TIMING3_DSC_EXP_S 13
18989 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
18990 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
18991 +#define AR_PHY_TIMING4_DO_CAL 0x10000
18992 +
18993 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
18994 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
18995 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
18996 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
18997 +
18998 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
18999 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
19000 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
19001 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
19002 +
19003 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
19004 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
19005 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
19006 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
19007 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
19008 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
19009 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
19010 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
19011 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
19012 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
19013 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
19014 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
19015 +#define AR_PHY_SFCORR_M1_THRESH_S 17
19016 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
19017 +#define AR_PHY_SFCORR_M2_THRESH_S 24
19018 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
19019 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
19020 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
19021 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
19022 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
19023 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
19024 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
19025 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
19026 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
19027 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
19028 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
19029 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
19030 +#define AR_PHY_EXT_CCA_THRESH62_S 16
19031 +#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
19032 +#define AR_PHY_EXT_MINCCA_PWR_S 16
19033 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
19034 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
19035 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
19036 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
19037 +#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
19038 +#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
19039 +#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
19040 +#define AR_PHY_TIMING5_RSSI_THR1A_S 16
19041 +#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
19042 +#define AR_PHY_RADAR_0_ENA 0x00000001
19043 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
19044 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
19045 +#define AR_PHY_RADAR_0_INBAND_S 1
19046 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
19047 +#define AR_PHY_RADAR_0_PRSSI_S 6
19048 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
19049 +#define AR_PHY_RADAR_0_HEIGHT_S 12
19050 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
19051 +#define AR_PHY_RADAR_0_RRSSI_S 18
19052 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
19053 +#define AR_PHY_RADAR_0_FIRPWR_S 24
19054 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
19055 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
19056 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
19057 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
19058 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
19059 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
19060 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
19061 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
19062 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
19063 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
19064 +#define AR_PHY_RADAR_1_MAXLEN_S 0
19065 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
19066 +#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
19067 +#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
19068 +#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
19069 +#define AR_PHY_RADAR_LB_DC_CAP_S 23
19070 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
19071 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
19072 +#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
19073 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
19074 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
19075 +#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
19076 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
19077 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
19078 +#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
19079 +#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
19080 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
19081 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
19082 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
19083 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
19084 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
19085 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
19086 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
19087 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
19088 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
19089 +
19090 +/*
19091 + * MRC Register Map
19092 + */
19093 +#define AR_MRC_BASE 0x9c00
19094 +
19095 +#define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
19096 +#define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
19097 +#define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
19098 +#define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
19099 +#define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
19100 +#define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
19101 +#define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
19102 +#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
19103 +#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
19104 +
19105 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
19106 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
19107 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
19108 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
19109 +
19110 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
19111 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
19112 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
19113 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
19114 +
19115 +/*
19116 + * MRC Feild Definitions
19117 + */
19118 +#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
19119 +#define AR_PHY_SGI_DSC_MAN_S 4
19120 +#define AR_PHY_SGI_DSC_EXP 0x0000000F
19121 +#define AR_PHY_SGI_DSC_EXP_S 0
19122 +/*
19123 + * BBB Register Map
19124 + */
19125 +#define AR_BBB_BASE 0x9d00
19126 +
19127 +/*
19128 + * AGC Register Map
19129 + */
19130 +#define AR_AGC_BASE 0x9e00
19131 +
19132 +#define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
19133 +#define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
19134 +#define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
19135 +#define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
19136 +#define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
19137 +#define AR_PHY_AGC (AR_AGC_BASE + 0x14)
19138 +#define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
19139 +#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
19140 +#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
19141 +#define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
19142 +#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
19143 +#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
19144 +#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
19145 +#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
19146 +#define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
19147 +#define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
19148 +#define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
19149 +#define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
19150 +#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
19151 +#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
19152 +#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
19153 +#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
19154 +#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
19155 +#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
19156 +
19157 +#define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
19158 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
19159 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
19160 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
19161 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
19162 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
19163 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
19164 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
19165 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
19166 +
19167 +#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
19168 +
19169 +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
19170 +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
19171 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
19172 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
19173 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
19174 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
19175 +
19176 +/*
19177 + * AGC Field Definitions
19178 + */
19179 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
19180 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
19181 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
19182 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
19183 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
19184 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
19185 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
19186 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
19187 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
19188 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
19189 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
19190 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
19191 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
19192 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
19193 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
19194 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
19195 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
19196 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
19197 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
19198 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
19199 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
19200 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
19201 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
19202 +#define AR_PHY_SETTLING_SWITCH_S 7
19203 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
19204 +#define AR_PHY_DESIRED_SZ_ADC_S 0
19205 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
19206 +#define AR_PHY_DESIRED_SZ_PGA_S 8
19207 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
19208 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
19209 +#define AR_PHY_MINCCA_PWR 0x1FF00000
19210 +#define AR_PHY_MINCCA_PWR_S 20
19211 +#define AR_PHY_CCA_THRESH62 0x0007F000
19212 +#define AR_PHY_CCA_THRESH62_S 12
19213 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
19214 +#define AR9280_PHY_MINCCA_PWR_S 20
19215 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
19216 +#define AR9280_PHY_CCA_THRESH62_S 12
19217 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
19218 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
19219 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
19220 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
19221 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
19222 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
19223 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
19224 +
19225 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
19226 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
19227 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
19228 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
19229 +
19230 +#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
19231 +#define AR_PHY_AGC_COARSE_LOW 0x00007F80
19232 +#define AR_PHY_AGC_COARSE_LOW_S 7
19233 +#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
19234 +#define AR_PHY_AGC_COARSE_HIGH_S 15
19235 +#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
19236 +#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
19237 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
19238 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
19239 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
19240 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
19241 +#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
19242 +#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
19243 +#define AR_PHY_FIND_SIG_RELPWR_S 6
19244 +#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
19245 +#define AR_PHY_FIND_SIG_RELSTEP 0x1f
19246 +#define AR_PHY_FIND_SIG_RELSTEP_S 0
19247 +#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
19248 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
19249 +#define AR_PHY_RESTART_DIV_GC_S 18
19250 +#define AR_PHY_RESTART_ENA 0x01
19251 +#define AR_PHY_DC_RESTART_DIS 0x40000000
19252 +
19253 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
19254 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
19255 +#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
19256 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
19257 +
19258 +#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
19259 +#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
19260 +
19261 +/*
19262 + * SM Register Map
19263 + */
19264 +#define AR_SM_BASE 0xa200
19265 +
19266 +#define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
19267 +#define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
19268 +#define AR_PHY_MODE (AR_SM_BASE + 0x8)
19269 +#define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
19270 +#define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20)
19271 +#define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24)
19272 +#define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
19273 +#define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
19274 +#define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
19275 +#define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
19276 +#define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
19277 +#define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
19278 +#define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
19279 +#define AR_PHY_RIFS (AR_SM_BASE + 0x44)
19280 +#define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
19281 +#define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
19282 +
19283 +#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
19284 +#define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
19285 +#define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
19286 +#define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
19287 +#define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
19288 +#define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
19289 +#define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
19290 +#define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
19291 +#define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
19292 +#define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
19293 +#define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
19294 +#define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
19295 +#define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
19296 +#define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
19297 +#define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
19298 +#define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
19299 +#define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
19300 +#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
19301 +#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
19302 +
19303 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
19304 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
19305 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
19306 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
19307 +
19308 +#define AR_PHY_TEST (AR_SM_BASE + 0x160)
19309 +
19310 +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
19311 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19
19312 +
19313 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
19314 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
19315 +
19316 +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
19317 +#define AR_PHY_TEST_CHAIN_SEL_S 30
19318 +
19319 +#define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164)
19320 +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
19321 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
19322 +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
19323 +#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
19324 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
19325 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
19326 +#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
19327 +#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
19328 +#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
19329 +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
19330 +
19331 +
19332 +#define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
19333 +
19334 +#define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
19335 +#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
19336 +#define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
19337 +#define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
19338 +#define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
19339 +#define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180)
19340 +#define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190)
19341 +#define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194)
19342 +
19343 +#define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4)
19344 +#define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
19345 +#define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
19346 +#define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
19347 +
19348 +#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
19349 +#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
19350 +
19351 +#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
19352 +#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
19353 +#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
19354 +#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
19355 +#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
19356 +#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
19357 +
19358 +#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
19359 +
19360 +#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
19361 +
19362 +#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
19363 +#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
19364 +#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
19365 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450)
19366 +
19367 +#define AR_PHY_PANIC_WD_STATUS (AR_SM_BASE + 0x5c0)
19368 +#define AR_PHY_PANIC_WD_CTL_1 (AR_SM_BASE + 0x5c4)
19369 +#define AR_PHY_PANIC_WD_CTL_2 (AR_SM_BASE + 0x5c8)
19370 +#define AR_PHY_BT_CTL (AR_SM_BASE + 0x5cc)
19371 +#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
19372 +#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
19373 +#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
19374 +#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
19375 +
19376 +#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
19377 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
19378 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
19379 +#define AR_PHY_65NM_CH0_SYNTH7 0x16098
19380 +#define AR_PHY_65NM_CH0_BIAS1 0x160c0
19381 +#define AR_PHY_65NM_CH0_BIAS2 0x160c4
19382 +#define AR_PHY_65NM_CH0_BIAS4 0x160cc
19383 +#define AR_PHY_65NM_CH0_RXTX4 0x1610c
19384 +#define AR_PHY_65NM_CH0_THERM 0x16290
19385 +
19386 +#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
19387 +#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
19388 +#define AR_PHY_65NM_CH0_THERM_START 0x20000000
19389 +#define AR_PHY_65NM_CH0_THERM_START_S 29
19390 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
19391 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
19392 +
19393 +#define AR_PHY_65NM_CH0_RXTX1 0x16100
19394 +#define AR_PHY_65NM_CH0_RXTX2 0x16104
19395 +#define AR_PHY_65NM_CH1_RXTX1 0x16500
19396 +#define AR_PHY_65NM_CH1_RXTX2 0x16504
19397 +#define AR_PHY_65NM_CH2_RXTX1 0x16900
19398 +#define AR_PHY_65NM_CH2_RXTX2 0x16904
19399 +
19400 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
19401 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
19402 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
19403 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
19404 +#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
19405 +#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
19406 +#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
19407 +#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
19408 +#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
19409 +#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
19410 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
19411 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
19412 +#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
19413 +#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
19414 +
19415 +/*
19416 + * SM Field Definitions
19417 + */
19418 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
19419 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
19420 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
19421 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
19422 +
19423 +#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
19424 +
19425 +#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
19426 +#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
19427 +
19428 +#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
19429 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
19430 +#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
19431 +#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
19432 +#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
19433 +#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
19434 +#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
19435 +#define AR_PHY_GC_DYN2040_PRI_CH_S 4
19436 +#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
19437 +#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
19438 +#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
19439 +#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
19440 +#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
19441 +#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
19442 +#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
19443 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
19444 +
19445 +#define AR_PHY_CALMODE_IQ 0x00000000
19446 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
19447 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
19448 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
19449 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
19450 +#define AR_PHY_MODE_OFDM 0x00000000
19451 +#define AR_PHY_MODE_CCK 0x00000001
19452 +#define AR_PHY_MODE_DYNAMIC 0x00000004
19453 +#define AR_PHY_MODE_DYNAMIC_S 2
19454 +#define AR_PHY_MODE_HALF 0x00000020
19455 +#define AR_PHY_MODE_QUARTER 0x00000040
19456 +#define AR_PHY_MAC_CLK_MODE 0x00000080
19457 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
19458 +#define AR_PHY_MODE_SVD_HALF 0x00000200
19459 +#define AR_PHY_ACTIVE_EN 0x00000001
19460 +#define AR_PHY_ACTIVE_DIS 0x00000000
19461 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
19462 +#define AR_PHY_FORCE_XPA_CFG_S 0
19463 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
19464 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
19465 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
19466 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
19467 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
19468 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
19469 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
19470 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
19471 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
19472 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
19473 +#define AR_PHY_TX_END_DATA_START 0x000000FF
19474 +#define AR_PHY_TX_END_DATA_START_S 0
19475 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
19476 +#define AR_PHY_TX_END_PA_ON_S 8
19477 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
19478 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
19479 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
19480 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
19481 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
19482 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
19483 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
19484 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
19485 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
19486 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
19487 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
19488 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
19489 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
19490 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
19491 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
19492 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
19493 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
19494 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
19495 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
19496 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
19497 +#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
19498 +#define AR_PHY_TXGAIN_FORCE 0x00000001
19499 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
19500 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
19501 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
19502 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
19503 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
19504 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
19505 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
19506 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
19507 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
19508 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
19509 +
19510 +#define AR_PHY_POWER_TX_RATE1 0x9934
19511 +#define AR_PHY_POWER_TX_RATE2 0x9938
19512 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
19513 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
19514 +#define PHY_AGC_CLR 0x10000000
19515 +#define RFSILENT_BB 0x00002000
19516 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
19517 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
19518 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
19519 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
19520 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
19521 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
19522 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
19523 +#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
19524 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
19525 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
19526 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
19527 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
19528 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
19529 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
19530 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
19531 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
19532 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
19533 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
19534 +#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
19535 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
19536 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
19537 +#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
19538 +#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
19539 +
19540 +#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
19541 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
19542 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
19543 +
19544 +#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
19545 +#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
19546 +#define AR_PHY_TPC_19_ALPHA_THERM 0xff
19547 +#define AR_PHY_TPC_19_ALPHA_THERM_S 0
19548 +
19549 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
19550 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
19551 +
19552 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
19553 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
19554 +
19555 +/*
19556 + * Channel 1 Register Map
19557 + */
19558 +#define AR_CHAN1_BASE 0xa800
19559 +
19560 +#define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
19561 +#define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
19562 +#define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
19563 +
19564 +#define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
19565 +#define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
19566 +#define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
19567 +
19568 +/*
19569 + * Channel 1 Field Definitions
19570 + */
19571 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
19572 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
19573 +
19574 +/*
19575 + * AGC 1 Register Map
19576 + */
19577 +#define AR_AGC1_BASE 0xae00
19578 +
19579 +#define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
19580 +#define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
19581 +#define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
19582 +#define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
19583 +#define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
19584 +#define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
19585 +#define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
19586 +
19587 +/*
19588 + * AGC 1 Field Definitions
19589 + */
19590 +#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
19591 +#define AR_PHY_CH1_MINCCA_PWR_S 20
19592 +
19593 +/*
19594 + * SM 1 Register Map
19595 + */
19596 +#define AR_SM1_BASE 0xb200
19597 +
19598 +#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
19599 +#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
19600 +#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
19601 +#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
19602 +#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
19603 +#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
19604 +#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
19605 +#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
19606 +#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
19607 +#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
19608 +#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
19609 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450)
19610 +
19611 +/*
19612 + * Channel 2 Register Map
19613 + */
19614 +#define AR_CHAN2_BASE 0xb800
19615 +
19616 +#define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
19617 +#define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
19618 +#define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
19619 +
19620 +#define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
19621 +#define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
19622 +#define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
19623 +
19624 +/*
19625 + * Channel 2 Field Definitions
19626 + */
19627 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
19628 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
19629 +/*
19630 + * AGC 2 Register Map
19631 + */
19632 +#define AR_AGC2_BASE 0xbe00
19633 +
19634 +#define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
19635 +#define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
19636 +#define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
19637 +#define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
19638 +#define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
19639 +
19640 +/*
19641 + * AGC 2 Field Definitions
19642 + */
19643 +#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
19644 +#define AR_PHY_CH2_MINCCA_PWR_S 20
19645 +
19646 +/*
19647 + * SM 2 Register Map
19648 + */
19649 +#define AR_SM2_BASE 0xc200
19650 +
19651 +#define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
19652 +#define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
19653 +#define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
19654 +#define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
19655 +#define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
19656 +#define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
19657 +#define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
19658 +#define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
19659 +#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
19660 +#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
19661 +#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
19662 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450)
19663 +
19664 +#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
19665 +
19666 +/*
19667 + * AGC 3 Register Map
19668 + */
19669 +#define AR_AGC3_BASE 0xce00
19670 +
19671 +#define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
19672 +
19673 +/*
19674 + * Misc helper defines
19675 + */
19676 +#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
19677 +
19678 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19679 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19680 +#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19681 +#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19682 +
19683 +#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19684 +#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19685 +#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19686 +
19687 +#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19688 +#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19689 +#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19690 +#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
19691 +#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19692 +#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19693 +#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19694 +#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
19695 +
19696 +#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
19697 +#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
19698 +#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
19699 +#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
19700 +
19701 +#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
19702 +#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
19703 +#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
19704 +
19705 +#define AR_PHY_BB_WD_STATUS 0x00000007
19706 +#define AR_PHY_BB_WD_STATUS_S 0
19707 +#define AR_PHY_BB_WD_DET_HANG 0x00000008
19708 +#define AR_PHY_BB_WD_DET_HANG_S 3
19709 +#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
19710 +#define AR_PHY_BB_WD_RADAR_SM_S 4
19711 +#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
19712 +#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
19713 +#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
19714 +#define AR_PHY_BB_WD_RX_CCK_SM_S 12
19715 +#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
19716 +#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
19717 +#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
19718 +#define AR_PHY_BB_WD_TX_CCK_SM_S 20
19719 +#define AR_PHY_BB_WD_AGC_SM 0x0F000000
19720 +#define AR_PHY_BB_WD_AGC_SM_S 24
19721 +#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
19722 +#define AR_PHY_BB_WD_SRCH_SM_S 28
19723 +
19724 +#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
19725 +
19726 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
19727 +
19728 +#endif /* AR9003_PHY_H */
19729 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
19730 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
19731 @@ -114,8 +114,10 @@ enum buffer_type {
19732 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
19733 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
19734
19735 +#define ATH_TXSTATUS_RING_SIZE 64
19736 +
19737 struct ath_descdma {
19738 - struct ath_desc *dd_desc;
19739 + void *dd_desc;
19740 dma_addr_t dd_desc_paddr;
19741 u32 dd_desc_len;
19742 struct ath_buf *dd_bufptr;
19743 @@ -123,7 +125,7 @@ struct ath_descdma {
19744
19745 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
19746 struct list_head *head, const char *name,
19747 - int nbuf, int ndesc);
19748 + int nbuf, int ndesc, bool is_tx);
19749 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
19750 struct list_head *head);
19751
19752 @@ -188,6 +190,7 @@ enum ATH_AGGR_STATUS {
19753 ATH_AGGR_LIMITED,
19754 };
19755
19756 +#define ATH_TXFIFO_DEPTH 8
19757 struct ath_txq {
19758 u32 axq_qnum;
19759 u32 *axq_link;
19760 @@ -197,6 +200,10 @@ struct ath_txq {
19761 bool stopped;
19762 bool axq_tx_inprogress;
19763 struct list_head axq_acq;
19764 + struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
19765 + struct list_head txq_fifo_pending;
19766 + u8 txq_headidx;
19767 + u8 txq_tailidx;
19768 };
19769
19770 #define AGGR_CLEANUP BIT(1)
19771 @@ -223,6 +230,12 @@ struct ath_tx {
19772 struct ath_descdma txdma;
19773 };
19774
19775 +struct ath_rx_edma {
19776 + struct sk_buff_head rx_fifo;
19777 + struct sk_buff_head rx_buffers;
19778 + u32 rx_fifo_hwsize;
19779 +};
19780 +
19781 struct ath_rx {
19782 u8 defant;
19783 u8 rxotherant;
19784 @@ -232,6 +245,8 @@ struct ath_rx {
19785 spinlock_t rxbuflock;
19786 struct list_head rxbuf;
19787 struct ath_descdma rxdma;
19788 + struct ath_buf *rx_bufptr;
19789 + struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
19790 };
19791
19792 int ath_startrecv(struct ath_softc *sc);
19793 @@ -240,7 +255,7 @@ void ath_flushrecv(struct ath_softc *sc)
19794 u32 ath_calcrxfilter(struct ath_softc *sc);
19795 int ath_rx_init(struct ath_softc *sc, int nbufs);
19796 void ath_rx_cleanup(struct ath_softc *sc);
19797 -int ath_rx_tasklet(struct ath_softc *sc, int flush);
19798 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
19799 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
19800 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
19801 int ath_tx_setup(struct ath_softc *sc, int haltype);
19802 @@ -258,6 +273,7 @@ int ath_txq_update(struct ath_softc *sc,
19803 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
19804 struct ath_tx_control *txctl);
19805 void ath_tx_tasklet(struct ath_softc *sc);
19806 +void ath_tx_edma_tasklet(struct ath_softc *sc);
19807 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
19808 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
19809 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
19810 @@ -507,6 +523,8 @@ struct ath_softc {
19811 struct ath_beacon_config cur_beacon_conf;
19812 struct delayed_work tx_complete_work;
19813 struct ath_btcoex btcoex;
19814 +
19815 + struct ath_descdma txsdma;
19816 };
19817
19818 struct ath_wiphy {
19819 --- a/drivers/net/wireless/ath/ath9k/beacon.c
19820 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
19821 @@ -93,8 +93,6 @@ static void ath_beacon_setup(struct ath_
19822 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
19823 }
19824
19825 - ds->ds_data = bf->bf_buf_addr;
19826 -
19827 sband = &sc->sbands[common->hw->conf.channel->band];
19828 rate = sband->bitrates[rateidx].hw_value;
19829 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
19830 @@ -109,7 +107,8 @@ static void ath_beacon_setup(struct ath_
19831
19832 /* NB: beacon's BufLen must be a multiple of 4 bytes */
19833 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
19834 - true, true, ds);
19835 + true, true, ds, bf->bf_buf_addr,
19836 + sc->beacon.beaconq);
19837
19838 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
19839 series[0].Tries = 1;
19840 --- a/drivers/net/wireless/ath/ath9k/calib.c
19841 +++ b/drivers/net/wireless/ath/ath9k/calib.c
19842 @@ -15,10 +15,12 @@
19843 */
19844
19845 #include "hw.h"
19846 +#include "hw-ops.h"
19847 +
19848 +/* Common calibration code */
19849
19850 /* We can tune this as we go by monitoring really low values */
19851 #define ATH9K_NF_TOO_LOW -60
19852 -#define AR9285_CLCAL_REDO_THRESH 1
19853
19854 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
19855 * is incorrect and we should use the static NF value. Later we can try to
19856 @@ -87,98 +89,9 @@ static void ath9k_hw_update_nfcal_hist_b
19857 return;
19858 }
19859
19860 -static void ath9k_hw_do_getnf(struct ath_hw *ah,
19861 - int16_t nfarray[NUM_NF_READINGS])
19862 -{
19863 - struct ath_common *common = ath9k_hw_common(ah);
19864 - int16_t nf;
19865 -
19866 - if (AR_SREV_9280_10_OR_LATER(ah))
19867 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
19868 - else
19869 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
19870 -
19871 - if (nf & 0x100)
19872 - nf = 0 - ((nf ^ 0x1ff) + 1);
19873 - ath_print(common, ATH_DBG_CALIBRATE,
19874 - "NF calibrated [ctl] [chain 0] is %d\n", nf);
19875 -
19876 - if (AR_SREV_9271(ah) && (nf >= -114))
19877 - nf = -116;
19878 -
19879 - nfarray[0] = nf;
19880 -
19881 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
19882 - if (AR_SREV_9280_10_OR_LATER(ah))
19883 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
19884 - AR9280_PHY_CH1_MINCCA_PWR);
19885 - else
19886 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
19887 - AR_PHY_CH1_MINCCA_PWR);
19888 -
19889 - if (nf & 0x100)
19890 - nf = 0 - ((nf ^ 0x1ff) + 1);
19891 - ath_print(common, ATH_DBG_CALIBRATE,
19892 - "NF calibrated [ctl] [chain 1] is %d\n", nf);
19893 - nfarray[1] = nf;
19894 -
19895 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
19896 - nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
19897 - AR_PHY_CH2_MINCCA_PWR);
19898 - if (nf & 0x100)
19899 - nf = 0 - ((nf ^ 0x1ff) + 1);
19900 - ath_print(common, ATH_DBG_CALIBRATE,
19901 - "NF calibrated [ctl] [chain 2] is %d\n", nf);
19902 - nfarray[2] = nf;
19903 - }
19904 - }
19905 -
19906 - if (AR_SREV_9280_10_OR_LATER(ah))
19907 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
19908 - AR9280_PHY_EXT_MINCCA_PWR);
19909 - else
19910 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
19911 - AR_PHY_EXT_MINCCA_PWR);
19912 -
19913 - if (nf & 0x100)
19914 - nf = 0 - ((nf ^ 0x1ff) + 1);
19915 - ath_print(common, ATH_DBG_CALIBRATE,
19916 - "NF calibrated [ext] [chain 0] is %d\n", nf);
19917 -
19918 - if (AR_SREV_9271(ah) && (nf >= -114))
19919 - nf = -116;
19920 -
19921 - nfarray[3] = nf;
19922 -
19923 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
19924 - if (AR_SREV_9280_10_OR_LATER(ah))
19925 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
19926 - AR9280_PHY_CH1_EXT_MINCCA_PWR);
19927 - else
19928 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
19929 - AR_PHY_CH1_EXT_MINCCA_PWR);
19930 -
19931 - if (nf & 0x100)
19932 - nf = 0 - ((nf ^ 0x1ff) + 1);
19933 - ath_print(common, ATH_DBG_CALIBRATE,
19934 - "NF calibrated [ext] [chain 1] is %d\n", nf);
19935 - nfarray[4] = nf;
19936 -
19937 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
19938 - nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
19939 - AR_PHY_CH2_EXT_MINCCA_PWR);
19940 - if (nf & 0x100)
19941 - nf = 0 - ((nf ^ 0x1ff) + 1);
19942 - ath_print(common, ATH_DBG_CALIBRATE,
19943 - "NF calibrated [ext] [chain 2] is %d\n", nf);
19944 - nfarray[5] = nf;
19945 - }
19946 - }
19947 -}
19948 -
19949 -static bool getNoiseFloorThresh(struct ath_hw *ah,
19950 - enum ieee80211_band band,
19951 - int16_t *nft)
19952 +static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
19953 + enum ieee80211_band band,
19954 + int16_t *nft)
19955 {
19956 switch (band) {
19957 case IEEE80211_BAND_5GHZ:
19958 @@ -195,44 +108,8 @@ static bool getNoiseFloorThresh(struct a
19959 return true;
19960 }
19961
19962 -static void ath9k_hw_setup_calibration(struct ath_hw *ah,
19963 - struct ath9k_cal_list *currCal)
19964 -{
19965 - struct ath_common *common = ath9k_hw_common(ah);
19966 -
19967 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
19968 - AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
19969 - currCal->calData->calCountMax);
19970 -
19971 - switch (currCal->calData->calType) {
19972 - case IQ_MISMATCH_CAL:
19973 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
19974 - ath_print(common, ATH_DBG_CALIBRATE,
19975 - "starting IQ Mismatch Calibration\n");
19976 - break;
19977 - case ADC_GAIN_CAL:
19978 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
19979 - ath_print(common, ATH_DBG_CALIBRATE,
19980 - "starting ADC Gain Calibration\n");
19981 - break;
19982 - case ADC_DC_CAL:
19983 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
19984 - ath_print(common, ATH_DBG_CALIBRATE,
19985 - "starting ADC DC Calibration\n");
19986 - break;
19987 - case ADC_DC_INIT_CAL:
19988 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
19989 - ath_print(common, ATH_DBG_CALIBRATE,
19990 - "starting Init ADC DC Calibration\n");
19991 - break;
19992 - }
19993 -
19994 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
19995 - AR_PHY_TIMING_CTRL4_DO_CAL);
19996 -}
19997 -
19998 -static void ath9k_hw_reset_calibration(struct ath_hw *ah,
19999 - struct ath9k_cal_list *currCal)
20000 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
20001 + struct ath9k_cal_list *currCal)
20002 {
20003 int i;
20004
20005 @@ -250,324 +127,6 @@ static void ath9k_hw_reset_calibration(s
20006 ah->cal_samples = 0;
20007 }
20008
20009 -static bool ath9k_hw_per_calibration(struct ath_hw *ah,
20010 - struct ath9k_channel *ichan,
20011 - u8 rxchainmask,
20012 - struct ath9k_cal_list *currCal)
20013 -{
20014 - bool iscaldone = false;
20015 -
20016 - if (currCal->calState == CAL_RUNNING) {
20017 - if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
20018 - AR_PHY_TIMING_CTRL4_DO_CAL)) {
20019 -
20020 - currCal->calData->calCollect(ah);
20021 - ah->cal_samples++;
20022 -
20023 - if (ah->cal_samples >= currCal->calData->calNumSamples) {
20024 - int i, numChains = 0;
20025 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20026 - if (rxchainmask & (1 << i))
20027 - numChains++;
20028 - }
20029 -
20030 - currCal->calData->calPostProc(ah, numChains);
20031 - ichan->CalValid |= currCal->calData->calType;
20032 - currCal->calState = CAL_DONE;
20033 - iscaldone = true;
20034 - } else {
20035 - ath9k_hw_setup_calibration(ah, currCal);
20036 - }
20037 - }
20038 - } else if (!(ichan->CalValid & currCal->calData->calType)) {
20039 - ath9k_hw_reset_calibration(ah, currCal);
20040 - }
20041 -
20042 - return iscaldone;
20043 -}
20044 -
20045 -/* Assumes you are talking about the currently configured channel */
20046 -static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
20047 - enum ath9k_cal_types calType)
20048 -{
20049 - struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
20050 -
20051 - switch (calType & ah->supp_cals) {
20052 - case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
20053 - return true;
20054 - case ADC_GAIN_CAL:
20055 - case ADC_DC_CAL:
20056 - if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
20057 - conf_is_ht20(conf)))
20058 - return true;
20059 - break;
20060 - }
20061 - return false;
20062 -}
20063 -
20064 -static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
20065 -{
20066 - int i;
20067 -
20068 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20069 - ah->totalPowerMeasI[i] +=
20070 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20071 - ah->totalPowerMeasQ[i] +=
20072 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20073 - ah->totalIqCorrMeas[i] +=
20074 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20075 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20076 - "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
20077 - ah->cal_samples, i, ah->totalPowerMeasI[i],
20078 - ah->totalPowerMeasQ[i],
20079 - ah->totalIqCorrMeas[i]);
20080 - }
20081 -}
20082 -
20083 -static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
20084 -{
20085 - int i;
20086 -
20087 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20088 - ah->totalAdcIOddPhase[i] +=
20089 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20090 - ah->totalAdcIEvenPhase[i] +=
20091 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20092 - ah->totalAdcQOddPhase[i] +=
20093 - REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20094 - ah->totalAdcQEvenPhase[i] +=
20095 - REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
20096 -
20097 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20098 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
20099 - "oddq=0x%08x; evenq=0x%08x;\n",
20100 - ah->cal_samples, i,
20101 - ah->totalAdcIOddPhase[i],
20102 - ah->totalAdcIEvenPhase[i],
20103 - ah->totalAdcQOddPhase[i],
20104 - ah->totalAdcQEvenPhase[i]);
20105 - }
20106 -}
20107 -
20108 -static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
20109 -{
20110 - int i;
20111 -
20112 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
20113 - ah->totalAdcDcOffsetIOddPhase[i] +=
20114 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
20115 - ah->totalAdcDcOffsetIEvenPhase[i] +=
20116 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
20117 - ah->totalAdcDcOffsetQOddPhase[i] +=
20118 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
20119 - ah->totalAdcDcOffsetQEvenPhase[i] +=
20120 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
20121 -
20122 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
20123 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
20124 - "oddq=0x%08x; evenq=0x%08x;\n",
20125 - ah->cal_samples, i,
20126 - ah->totalAdcDcOffsetIOddPhase[i],
20127 - ah->totalAdcDcOffsetIEvenPhase[i],
20128 - ah->totalAdcDcOffsetQOddPhase[i],
20129 - ah->totalAdcDcOffsetQEvenPhase[i]);
20130 - }
20131 -}
20132 -
20133 -static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
20134 -{
20135 - struct ath_common *common = ath9k_hw_common(ah);
20136 - u32 powerMeasQ, powerMeasI, iqCorrMeas;
20137 - u32 qCoffDenom, iCoffDenom;
20138 - int32_t qCoff, iCoff;
20139 - int iqCorrNeg, i;
20140 -
20141 - for (i = 0; i < numChains; i++) {
20142 - powerMeasI = ah->totalPowerMeasI[i];
20143 - powerMeasQ = ah->totalPowerMeasQ[i];
20144 - iqCorrMeas = ah->totalIqCorrMeas[i];
20145 -
20146 - ath_print(common, ATH_DBG_CALIBRATE,
20147 - "Starting IQ Cal and Correction for Chain %d\n",
20148 - i);
20149 -
20150 - ath_print(common, ATH_DBG_CALIBRATE,
20151 - "Orignal: Chn %diq_corr_meas = 0x%08x\n",
20152 - i, ah->totalIqCorrMeas[i]);
20153 -
20154 - iqCorrNeg = 0;
20155 -
20156 - if (iqCorrMeas > 0x80000000) {
20157 - iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
20158 - iqCorrNeg = 1;
20159 - }
20160 -
20161 - ath_print(common, ATH_DBG_CALIBRATE,
20162 - "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
20163 - ath_print(common, ATH_DBG_CALIBRATE,
20164 - "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
20165 - ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
20166 - iqCorrNeg);
20167 -
20168 - iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
20169 - qCoffDenom = powerMeasQ / 64;
20170 -
20171 - if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
20172 - (qCoffDenom != 0)) {
20173 - iCoff = iqCorrMeas / iCoffDenom;
20174 - qCoff = powerMeasI / qCoffDenom - 64;
20175 - ath_print(common, ATH_DBG_CALIBRATE,
20176 - "Chn %d iCoff = 0x%08x\n", i, iCoff);
20177 - ath_print(common, ATH_DBG_CALIBRATE,
20178 - "Chn %d qCoff = 0x%08x\n", i, qCoff);
20179 -
20180 - iCoff = iCoff & 0x3f;
20181 - ath_print(common, ATH_DBG_CALIBRATE,
20182 - "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
20183 - if (iqCorrNeg == 0x0)
20184 - iCoff = 0x40 - iCoff;
20185 -
20186 - if (qCoff > 15)
20187 - qCoff = 15;
20188 - else if (qCoff <= -16)
20189 - qCoff = 16;
20190 -
20191 - ath_print(common, ATH_DBG_CALIBRATE,
20192 - "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
20193 - i, iCoff, qCoff);
20194 -
20195 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
20196 - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
20197 - iCoff);
20198 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
20199 - AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
20200 - qCoff);
20201 - ath_print(common, ATH_DBG_CALIBRATE,
20202 - "IQ Cal and Correction done for Chain %d\n",
20203 - i);
20204 - }
20205 - }
20206 -
20207 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
20208 - AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
20209 -}
20210 -
20211 -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
20212 -{
20213 - struct ath_common *common = ath9k_hw_common(ah);
20214 - u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
20215 - u32 qGainMismatch, iGainMismatch, val, i;
20216 -
20217 - for (i = 0; i < numChains; i++) {
20218 - iOddMeasOffset = ah->totalAdcIOddPhase[i];
20219 - iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
20220 - qOddMeasOffset = ah->totalAdcQOddPhase[i];
20221 - qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
20222 -
20223 - ath_print(common, ATH_DBG_CALIBRATE,
20224 - "Starting ADC Gain Cal for Chain %d\n", i);
20225 -
20226 - ath_print(common, ATH_DBG_CALIBRATE,
20227 - "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
20228 - iOddMeasOffset);
20229 - ath_print(common, ATH_DBG_CALIBRATE,
20230 - "Chn %d pwr_meas_even_i = 0x%08x\n", i,
20231 - iEvenMeasOffset);
20232 - ath_print(common, ATH_DBG_CALIBRATE,
20233 - "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
20234 - qOddMeasOffset);
20235 - ath_print(common, ATH_DBG_CALIBRATE,
20236 - "Chn %d pwr_meas_even_q = 0x%08x\n", i,
20237 - qEvenMeasOffset);
20238 -
20239 - if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
20240 - iGainMismatch =
20241 - ((iEvenMeasOffset * 32) /
20242 - iOddMeasOffset) & 0x3f;
20243 - qGainMismatch =
20244 - ((qOddMeasOffset * 32) /
20245 - qEvenMeasOffset) & 0x3f;
20246 -
20247 - ath_print(common, ATH_DBG_CALIBRATE,
20248 - "Chn %d gain_mismatch_i = 0x%08x\n", i,
20249 - iGainMismatch);
20250 - ath_print(common, ATH_DBG_CALIBRATE,
20251 - "Chn %d gain_mismatch_q = 0x%08x\n", i,
20252 - qGainMismatch);
20253 -
20254 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
20255 - val &= 0xfffff000;
20256 - val |= (qGainMismatch) | (iGainMismatch << 6);
20257 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
20258 -
20259 - ath_print(common, ATH_DBG_CALIBRATE,
20260 - "ADC Gain Cal done for Chain %d\n", i);
20261 - }
20262 - }
20263 -
20264 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
20265 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
20266 - AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
20267 -}
20268 -
20269 -static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
20270 -{
20271 - struct ath_common *common = ath9k_hw_common(ah);
20272 - u32 iOddMeasOffset, iEvenMeasOffset, val, i;
20273 - int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
20274 - const struct ath9k_percal_data *calData =
20275 - ah->cal_list_curr->calData;
20276 - u32 numSamples =
20277 - (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
20278 -
20279 - for (i = 0; i < numChains; i++) {
20280 - iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
20281 - iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
20282 - qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
20283 - qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
20284 -
20285 - ath_print(common, ATH_DBG_CALIBRATE,
20286 - "Starting ADC DC Offset Cal for Chain %d\n", i);
20287 -
20288 - ath_print(common, ATH_DBG_CALIBRATE,
20289 - "Chn %d pwr_meas_odd_i = %d\n", i,
20290 - iOddMeasOffset);
20291 - ath_print(common, ATH_DBG_CALIBRATE,
20292 - "Chn %d pwr_meas_even_i = %d\n", i,
20293 - iEvenMeasOffset);
20294 - ath_print(common, ATH_DBG_CALIBRATE,
20295 - "Chn %d pwr_meas_odd_q = %d\n", i,
20296 - qOddMeasOffset);
20297 - ath_print(common, ATH_DBG_CALIBRATE,
20298 - "Chn %d pwr_meas_even_q = %d\n", i,
20299 - qEvenMeasOffset);
20300 -
20301 - iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
20302 - numSamples) & 0x1ff;
20303 - qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
20304 - numSamples) & 0x1ff;
20305 -
20306 - ath_print(common, ATH_DBG_CALIBRATE,
20307 - "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
20308 - iDcMismatch);
20309 - ath_print(common, ATH_DBG_CALIBRATE,
20310 - "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
20311 - qDcMismatch);
20312 -
20313 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
20314 - val &= 0xc0000fff;
20315 - val |= (qDcMismatch << 12) | (iDcMismatch << 21);
20316 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
20317 -
20318 - ath_print(common, ATH_DBG_CALIBRATE,
20319 - "ADC DC Offset Cal done for Chain %d\n", i);
20320 - }
20321 -
20322 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
20323 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
20324 - AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
20325 -}
20326 -
20327 /* This is done for the currently configured channel */
20328 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
20329 {
20330 @@ -614,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw
20331 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
20332 }
20333
20334 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
20335 -{
20336 - struct ath9k_nfcal_hist *h;
20337 - int i, j;
20338 - int32_t val;
20339 - const u32 ar5416_cca_regs[6] = {
20340 - AR_PHY_CCA,
20341 - AR_PHY_CH1_CCA,
20342 - AR_PHY_CH2_CCA,
20343 - AR_PHY_EXT_CCA,
20344 - AR_PHY_CH1_EXT_CCA,
20345 - AR_PHY_CH2_EXT_CCA
20346 - };
20347 - u8 chainmask, rx_chain_status;
20348 -
20349 - rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
20350 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
20351 - chainmask = 0x9;
20352 - else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
20353 - if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
20354 - chainmask = 0x1B;
20355 - else
20356 - chainmask = 0x09;
20357 - } else {
20358 - if (rx_chain_status & 0x4)
20359 - chainmask = 0x3F;
20360 - else if (rx_chain_status & 0x2)
20361 - chainmask = 0x1B;
20362 - else
20363 - chainmask = 0x09;
20364 - }
20365 -
20366 - h = ah->nfCalHist;
20367 -
20368 - for (i = 0; i < NUM_NF_READINGS; i++) {
20369 - if (chainmask & (1 << i)) {
20370 - val = REG_READ(ah, ar5416_cca_regs[i]);
20371 - val &= 0xFFFFFE00;
20372 - val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
20373 - REG_WRITE(ah, ar5416_cca_regs[i], val);
20374 - }
20375 - }
20376 -
20377 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20378 - AR_PHY_AGC_CONTROL_ENABLE_NF);
20379 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20380 - AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
20381 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
20382 -
20383 - for (j = 0; j < 5; j++) {
20384 - if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
20385 - AR_PHY_AGC_CONTROL_NF) == 0)
20386 - break;
20387 - udelay(50);
20388 - }
20389 -
20390 - for (i = 0; i < NUM_NF_READINGS; i++) {
20391 - if (chainmask & (1 << i)) {
20392 - val = REG_READ(ah, ar5416_cca_regs[i]);
20393 - val &= 0xFFFFFE00;
20394 - val |= (((u32) (-50) << 1) & 0x1ff);
20395 - REG_WRITE(ah, ar5416_cca_regs[i], val);
20396 - }
20397 - }
20398 -}
20399 -
20400 int16_t ath9k_hw_getnf(struct ath_hw *ah,
20401 struct ath9k_channel *chan)
20402 {
20403 @@ -699,7 +192,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah
20404 } else {
20405 ath9k_hw_do_getnf(ah, nfarray);
20406 nf = nfarray[0];
20407 - if (getNoiseFloorThresh(ah, c->band, &nfThresh)
20408 + if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
20409 && nf > nfThresh) {
20410 ath_print(common, ATH_DBG_CALIBRATE,
20411 "noise floor failed detected; "
20412 @@ -757,567 +250,3 @@ s16 ath9k_hw_getchan_noise(struct ath_hw
20413 return nf;
20414 }
20415 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
20416 -
20417 -static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
20418 -{
20419 - u32 rddata;
20420 - int32_t delta, currPDADC, slope;
20421 -
20422 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
20423 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
20424 -
20425 - if (ah->initPDADC == 0 || currPDADC == 0) {
20426 - /*
20427 - * Zero value indicates that no frames have been transmitted yet,
20428 - * can't do temperature compensation until frames are transmitted.
20429 - */
20430 - return;
20431 - } else {
20432 - slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
20433 -
20434 - if (slope == 0) { /* to avoid divide by zero case */
20435 - delta = 0;
20436 - } else {
20437 - delta = ((currPDADC - ah->initPDADC)*4) / slope;
20438 - }
20439 - REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
20440 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
20441 - REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
20442 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
20443 - }
20444 -}
20445 -
20446 -static void ath9k_olc_temp_compensation(struct ath_hw *ah)
20447 -{
20448 - u32 rddata, i;
20449 - int delta, currPDADC, regval;
20450 -
20451 - if (OLC_FOR_AR9287_10_LATER) {
20452 - ath9k_olc_temp_compensation_9287(ah);
20453 - } else {
20454 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
20455 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
20456 -
20457 - if (ah->initPDADC == 0 || currPDADC == 0) {
20458 - return;
20459 - } else {
20460 - if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
20461 - delta = (currPDADC - ah->initPDADC + 4) / 8;
20462 - else
20463 - delta = (currPDADC - ah->initPDADC + 5) / 10;
20464 -
20465 - if (delta != ah->PDADCdelta) {
20466 - ah->PDADCdelta = delta;
20467 - for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
20468 - regval = ah->originalGain[i] - delta;
20469 - if (regval < 0)
20470 - regval = 0;
20471 -
20472 - REG_RMW_FIELD(ah,
20473 - AR_PHY_TX_GAIN_TBL1 + i * 4,
20474 - AR_PHY_TX_GAIN, regval);
20475 - }
20476 - }
20477 - }
20478 - }
20479 -}
20480 -
20481 -static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
20482 -{
20483 - u32 regVal;
20484 - unsigned int i;
20485 - u32 regList [][2] = {
20486 - { 0x786c, 0 },
20487 - { 0x7854, 0 },
20488 - { 0x7820, 0 },
20489 - { 0x7824, 0 },
20490 - { 0x7868, 0 },
20491 - { 0x783c, 0 },
20492 - { 0x7838, 0 } ,
20493 - { 0x7828, 0 } ,
20494 - };
20495 -
20496 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20497 - regList[i][1] = REG_READ(ah, regList[i][0]);
20498 -
20499 - regVal = REG_READ(ah, 0x7834);
20500 - regVal &= (~(0x1));
20501 - REG_WRITE(ah, 0x7834, regVal);
20502 - regVal = REG_READ(ah, 0x9808);
20503 - regVal |= (0x1 << 27);
20504 - REG_WRITE(ah, 0x9808, regVal);
20505 -
20506 - /* 786c,b23,1, pwddac=1 */
20507 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
20508 - /* 7854, b5,1, pdrxtxbb=1 */
20509 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
20510 - /* 7854, b7,1, pdv2i=1 */
20511 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
20512 - /* 7854, b8,1, pddacinterface=1 */
20513 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
20514 - /* 7824,b12,0, offcal=0 */
20515 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
20516 - /* 7838, b1,0, pwddb=0 */
20517 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
20518 - /* 7820,b11,0, enpacal=0 */
20519 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
20520 - /* 7820,b25,1, pdpadrv1=0 */
20521 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
20522 - /* 7820,b24,0, pdpadrv2=0 */
20523 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
20524 - /* 7820,b23,0, pdpaout=0 */
20525 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
20526 - /* 783c,b14-16,7, padrvgn2tab_0=7 */
20527 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
20528 - /*
20529 - * 7838,b29-31,0, padrvgn1tab_0=0
20530 - * does not matter since we turn it off
20531 - */
20532 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
20533 -
20534 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
20535 -
20536 - /* Set:
20537 - * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
20538 - * txon=1,paon=1,oscon=1,synthon_force=1
20539 - */
20540 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
20541 - udelay(30);
20542 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
20543 -
20544 - /* find off_6_1; */
20545 - for (i = 6; i > 0; i--) {
20546 - regVal = REG_READ(ah, 0x7834);
20547 - regVal |= (1 << (20 + i));
20548 - REG_WRITE(ah, 0x7834, regVal);
20549 - udelay(1);
20550 - //regVal = REG_READ(ah, 0x7834);
20551 - regVal &= (~(0x1 << (20 + i)));
20552 - regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
20553 - << (20 + i));
20554 - REG_WRITE(ah, 0x7834, regVal);
20555 - }
20556 -
20557 - regVal = (regVal >>20) & 0x7f;
20558 -
20559 - /* Update PA cal info */
20560 - if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
20561 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
20562 - ah->pacal_info.max_skipcount =
20563 - 2 * ah->pacal_info.max_skipcount;
20564 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
20565 - } else {
20566 - ah->pacal_info.max_skipcount = 1;
20567 - ah->pacal_info.skipcount = 0;
20568 - ah->pacal_info.prev_offset = regVal;
20569 - }
20570 -
20571 - regVal = REG_READ(ah, 0x7834);
20572 - regVal |= 0x1;
20573 - REG_WRITE(ah, 0x7834, regVal);
20574 - regVal = REG_READ(ah, 0x9808);
20575 - regVal &= (~(0x1 << 27));
20576 - REG_WRITE(ah, 0x9808, regVal);
20577 -
20578 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20579 - REG_WRITE(ah, regList[i][0], regList[i][1]);
20580 -}
20581 -
20582 -static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
20583 -{
20584 - struct ath_common *common = ath9k_hw_common(ah);
20585 - u32 regVal;
20586 - int i, offset, offs_6_1, offs_0;
20587 - u32 ccomp_org, reg_field;
20588 - u32 regList[][2] = {
20589 - { 0x786c, 0 },
20590 - { 0x7854, 0 },
20591 - { 0x7820, 0 },
20592 - { 0x7824, 0 },
20593 - { 0x7868, 0 },
20594 - { 0x783c, 0 },
20595 - { 0x7838, 0 },
20596 - };
20597 -
20598 - ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
20599 -
20600 - /* PA CAL is not needed for high power solution */
20601 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
20602 - AR5416_EEP_TXGAIN_HIGH_POWER)
20603 - return;
20604 -
20605 - if (AR_SREV_9285_11(ah)) {
20606 - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
20607 - udelay(10);
20608 - }
20609 -
20610 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20611 - regList[i][1] = REG_READ(ah, regList[i][0]);
20612 -
20613 - regVal = REG_READ(ah, 0x7834);
20614 - regVal &= (~(0x1));
20615 - REG_WRITE(ah, 0x7834, regVal);
20616 - regVal = REG_READ(ah, 0x9808);
20617 - regVal |= (0x1 << 27);
20618 - REG_WRITE(ah, 0x9808, regVal);
20619 -
20620 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
20621 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
20622 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
20623 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
20624 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
20625 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
20626 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
20627 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
20628 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
20629 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
20630 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
20631 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
20632 - ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
20633 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
20634 -
20635 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
20636 - udelay(30);
20637 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
20638 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
20639 -
20640 - for (i = 6; i > 0; i--) {
20641 - regVal = REG_READ(ah, 0x7834);
20642 - regVal |= (1 << (19 + i));
20643 - REG_WRITE(ah, 0x7834, regVal);
20644 - udelay(1);
20645 - regVal = REG_READ(ah, 0x7834);
20646 - regVal &= (~(0x1 << (19 + i)));
20647 - reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
20648 - regVal |= (reg_field << (19 + i));
20649 - REG_WRITE(ah, 0x7834, regVal);
20650 - }
20651 -
20652 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
20653 - udelay(1);
20654 - reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
20655 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
20656 - offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
20657 - offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
20658 -
20659 - offset = (offs_6_1<<1) | offs_0;
20660 - offset = offset - 0;
20661 - offs_6_1 = offset>>1;
20662 - offs_0 = offset & 1;
20663 -
20664 - if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
20665 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
20666 - ah->pacal_info.max_skipcount =
20667 - 2 * ah->pacal_info.max_skipcount;
20668 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
20669 - } else {
20670 - ah->pacal_info.max_skipcount = 1;
20671 - ah->pacal_info.skipcount = 0;
20672 - ah->pacal_info.prev_offset = offset;
20673 - }
20674 -
20675 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
20676 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
20677 -
20678 - regVal = REG_READ(ah, 0x7834);
20679 - regVal |= 0x1;
20680 - REG_WRITE(ah, 0x7834, regVal);
20681 - regVal = REG_READ(ah, 0x9808);
20682 - regVal &= (~(0x1 << 27));
20683 - REG_WRITE(ah, 0x9808, regVal);
20684 -
20685 - for (i = 0; i < ARRAY_SIZE(regList); i++)
20686 - REG_WRITE(ah, regList[i][0], regList[i][1]);
20687 -
20688 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
20689 -
20690 - if (AR_SREV_9285_11(ah))
20691 - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
20692 -
20693 -}
20694 -
20695 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
20696 - u8 rxchainmask, bool longcal)
20697 -{
20698 - bool iscaldone = true;
20699 - struct ath9k_cal_list *currCal = ah->cal_list_curr;
20700 -
20701 - if (currCal &&
20702 - (currCal->calState == CAL_RUNNING ||
20703 - currCal->calState == CAL_WAITING)) {
20704 - iscaldone = ath9k_hw_per_calibration(ah, chan,
20705 - rxchainmask, currCal);
20706 - if (iscaldone) {
20707 - ah->cal_list_curr = currCal = currCal->calNext;
20708 -
20709 - if (currCal->calState == CAL_WAITING) {
20710 - iscaldone = false;
20711 - ath9k_hw_reset_calibration(ah, currCal);
20712 - }
20713 - }
20714 - }
20715 -
20716 - /* Do NF cal only at longer intervals */
20717 - if (longcal) {
20718 - /* Do periodic PAOffset Cal */
20719 - if (AR_SREV_9271(ah)) {
20720 - if (!ah->pacal_info.skipcount)
20721 - ath9k_hw_9271_pa_cal(ah, false);
20722 - else
20723 - ah->pacal_info.skipcount--;
20724 - } else if (AR_SREV_9285_11_OR_LATER(ah)) {
20725 - if (!ah->pacal_info.skipcount)
20726 - ath9k_hw_9285_pa_cal(ah, false);
20727 - else
20728 - ah->pacal_info.skipcount--;
20729 - }
20730 -
20731 - if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
20732 - ath9k_olc_temp_compensation(ah);
20733 -
20734 - /* Get the value from the previous NF cal and update history buffer */
20735 - ath9k_hw_getnf(ah, chan);
20736 -
20737 - /*
20738 - * Load the NF from history buffer of the current channel.
20739 - * NF is slow time-variant, so it is OK to use a historical value.
20740 - */
20741 - ath9k_hw_loadnf(ah, ah->curchan);
20742 -
20743 - ath9k_hw_start_nfcal(ah);
20744 - }
20745 -
20746 - return iscaldone;
20747 -}
20748 -EXPORT_SYMBOL(ath9k_hw_calibrate);
20749 -
20750 -/* Carrier leakage Calibration fix */
20751 -static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
20752 -{
20753 - struct ath_common *common = ath9k_hw_common(ah);
20754 -
20755 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20756 - if (IS_CHAN_HT20(chan)) {
20757 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
20758 - REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
20759 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20760 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20761 - REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
20762 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
20763 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
20764 - AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
20765 - ath_print(common, ATH_DBG_CALIBRATE, "offset "
20766 - "calibration failed to complete in "
20767 - "1ms; noisy ??\n");
20768 - return false;
20769 - }
20770 - REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
20771 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
20772 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20773 - }
20774 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
20775 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
20776 - REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
20777 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
20778 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
20779 - 0, AH_WAIT_TIMEOUT)) {
20780 - ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
20781 - "failed to complete in 1ms; noisy ??\n");
20782 - return false;
20783 - }
20784 -
20785 - REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
20786 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
20787 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
20788 -
20789 - return true;
20790 -}
20791 -
20792 -static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
20793 -{
20794 - int i;
20795 - u_int32_t txgain_max;
20796 - u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
20797 - u_int32_t reg_clc_I0, reg_clc_Q0;
20798 - u_int32_t i0_num = 0;
20799 - u_int32_t q0_num = 0;
20800 - u_int32_t total_num = 0;
20801 - u_int32_t reg_rf2g5_org;
20802 - bool retv = true;
20803 -
20804 - if (!(ar9285_cl_cal(ah, chan)))
20805 - return false;
20806 -
20807 - txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
20808 - AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
20809 -
20810 - for (i = 0; i < (txgain_max+1); i++) {
20811 - clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
20812 - AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
20813 - if (!(gain_mask & (1 << clc_gain))) {
20814 - gain_mask |= (1 << clc_gain);
20815 - clc_num++;
20816 - }
20817 - }
20818 -
20819 - for (i = 0; i < clc_num; i++) {
20820 - reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
20821 - & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
20822 - reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
20823 - & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
20824 - if (reg_clc_I0 == 0)
20825 - i0_num++;
20826 -
20827 - if (reg_clc_Q0 == 0)
20828 - q0_num++;
20829 - }
20830 - total_num = i0_num + q0_num;
20831 - if (total_num > AR9285_CLCAL_REDO_THRESH) {
20832 - reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
20833 - if (AR_SREV_9285E_20(ah)) {
20834 - REG_WRITE(ah, AR9285_RF2G5,
20835 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
20836 - AR9285_RF2G5_IC50TX_XE_SET);
20837 - } else {
20838 - REG_WRITE(ah, AR9285_RF2G5,
20839 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
20840 - AR9285_RF2G5_IC50TX_SET);
20841 - }
20842 - retv = ar9285_cl_cal(ah, chan);
20843 - REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
20844 - }
20845 - return retv;
20846 -}
20847 -
20848 -bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
20849 -{
20850 - struct ath_common *common = ath9k_hw_common(ah);
20851 -
20852 - if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
20853 - if (!ar9285_clc(ah, chan))
20854 - return false;
20855 - } else {
20856 - if (AR_SREV_9280_10_OR_LATER(ah)) {
20857 - if (!AR_SREV_9287_10_OR_LATER(ah))
20858 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
20859 - AR_PHY_ADC_CTL_OFF_PWDADC);
20860 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
20861 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20862 - }
20863 -
20864 - /* Calibrate the AGC */
20865 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
20866 - REG_READ(ah, AR_PHY_AGC_CONTROL) |
20867 - AR_PHY_AGC_CONTROL_CAL);
20868 -
20869 - /* Poll for offset calibration complete */
20870 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
20871 - 0, AH_WAIT_TIMEOUT)) {
20872 - ath_print(common, ATH_DBG_CALIBRATE,
20873 - "offset calibration failed to "
20874 - "complete in 1ms; noisy environment?\n");
20875 - return false;
20876 - }
20877 -
20878 - if (AR_SREV_9280_10_OR_LATER(ah)) {
20879 - if (!AR_SREV_9287_10_OR_LATER(ah))
20880 - REG_SET_BIT(ah, AR_PHY_ADC_CTL,
20881 - AR_PHY_ADC_CTL_OFF_PWDADC);
20882 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
20883 - AR_PHY_AGC_CONTROL_FLTR_CAL);
20884 - }
20885 - }
20886 -
20887 - /* Do PA Calibration */
20888 - if (AR_SREV_9271(ah))
20889 - ath9k_hw_9271_pa_cal(ah, true);
20890 - else if (AR_SREV_9285_11_OR_LATER(ah))
20891 - ath9k_hw_9285_pa_cal(ah, true);
20892 -
20893 - /* Do NF Calibration after DC offset and other calibrations */
20894 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
20895 - REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
20896 -
20897 - ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
20898 -
20899 - /* Enable IQ, ADC Gain and ADC DC offset CALs */
20900 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
20901 - if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
20902 - INIT_CAL(&ah->adcgain_caldata);
20903 - INSERT_CAL(ah, &ah->adcgain_caldata);
20904 - ath_print(common, ATH_DBG_CALIBRATE,
20905 - "enabling ADC Gain Calibration.\n");
20906 - }
20907 - if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
20908 - INIT_CAL(&ah->adcdc_caldata);
20909 - INSERT_CAL(ah, &ah->adcdc_caldata);
20910 - ath_print(common, ATH_DBG_CALIBRATE,
20911 - "enabling ADC DC Calibration.\n");
20912 - }
20913 - if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
20914 - INIT_CAL(&ah->iq_caldata);
20915 - INSERT_CAL(ah, &ah->iq_caldata);
20916 - ath_print(common, ATH_DBG_CALIBRATE,
20917 - "enabling IQ Calibration.\n");
20918 - }
20919 -
20920 - ah->cal_list_curr = ah->cal_list;
20921 -
20922 - if (ah->cal_list_curr)
20923 - ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
20924 - }
20925 -
20926 - chan->CalValid = 0;
20927 -
20928 - return true;
20929 -}
20930 -
20931 -const struct ath9k_percal_data iq_cal_multi_sample = {
20932 - IQ_MISMATCH_CAL,
20933 - MAX_CAL_SAMPLES,
20934 - PER_MIN_LOG_COUNT,
20935 - ath9k_hw_iqcal_collect,
20936 - ath9k_hw_iqcalibrate
20937 -};
20938 -const struct ath9k_percal_data iq_cal_single_sample = {
20939 - IQ_MISMATCH_CAL,
20940 - MIN_CAL_SAMPLES,
20941 - PER_MAX_LOG_COUNT,
20942 - ath9k_hw_iqcal_collect,
20943 - ath9k_hw_iqcalibrate
20944 -};
20945 -const struct ath9k_percal_data adc_gain_cal_multi_sample = {
20946 - ADC_GAIN_CAL,
20947 - MAX_CAL_SAMPLES,
20948 - PER_MIN_LOG_COUNT,
20949 - ath9k_hw_adc_gaincal_collect,
20950 - ath9k_hw_adc_gaincal_calibrate
20951 -};
20952 -const struct ath9k_percal_data adc_gain_cal_single_sample = {
20953 - ADC_GAIN_CAL,
20954 - MIN_CAL_SAMPLES,
20955 - PER_MAX_LOG_COUNT,
20956 - ath9k_hw_adc_gaincal_collect,
20957 - ath9k_hw_adc_gaincal_calibrate
20958 -};
20959 -const struct ath9k_percal_data adc_dc_cal_multi_sample = {
20960 - ADC_DC_CAL,
20961 - MAX_CAL_SAMPLES,
20962 - PER_MIN_LOG_COUNT,
20963 - ath9k_hw_adc_dccal_collect,
20964 - ath9k_hw_adc_dccal_calibrate
20965 -};
20966 -const struct ath9k_percal_data adc_dc_cal_single_sample = {
20967 - ADC_DC_CAL,
20968 - MIN_CAL_SAMPLES,
20969 - PER_MAX_LOG_COUNT,
20970 - ath9k_hw_adc_dccal_collect,
20971 - ath9k_hw_adc_dccal_calibrate
20972 -};
20973 -const struct ath9k_percal_data adc_init_dc_cal = {
20974 - ADC_DC_INIT_CAL,
20975 - MIN_CAL_SAMPLES,
20976 - INIT_LOG_COUNT,
20977 - ath9k_hw_adc_dccal_collect,
20978 - ath9k_hw_adc_dccal_calibrate
20979 -};
20980 --- a/drivers/net/wireless/ath/ath9k/calib.h
20981 +++ b/drivers/net/wireless/ath/ath9k/calib.h
20982 @@ -19,14 +19,6 @@
20983
20984 #include "hw.h"
20985
20986 -extern const struct ath9k_percal_data iq_cal_multi_sample;
20987 -extern const struct ath9k_percal_data iq_cal_single_sample;
20988 -extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
20989 -extern const struct ath9k_percal_data adc_gain_cal_single_sample;
20990 -extern const struct ath9k_percal_data adc_dc_cal_multi_sample;
20991 -extern const struct ath9k_percal_data adc_dc_cal_single_sample;
20992 -extern const struct ath9k_percal_data adc_init_dc_cal;
20993 -
20994 #define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85
20995 #define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112
20996 #define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118
20997 @@ -76,7 +68,8 @@ enum ath9k_cal_types {
20998 ADC_DC_INIT_CAL = 0x1,
20999 ADC_GAIN_CAL = 0x2,
21000 ADC_DC_CAL = 0x4,
21001 - IQ_MISMATCH_CAL = 0x8
21002 + IQ_MISMATCH_CAL = 0x8,
21003 + TEMP_COMP_CAL = 0x10,
21004 };
21005
21006 enum ath9k_cal_state {
21007 @@ -122,14 +115,12 @@ struct ath9k_pacal_info{
21008
21009 bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
21010 void ath9k_hw_start_nfcal(struct ath_hw *ah);
21011 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
21012 int16_t ath9k_hw_getnf(struct ath_hw *ah,
21013 struct ath9k_channel *chan);
21014 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
21015 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
21016 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
21017 - u8 rxchainmask, bool longcal);
21018 -bool ath9k_hw_init_cal(struct ath_hw *ah,
21019 - struct ath9k_channel *chan);
21020 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
21021 + struct ath9k_cal_list *currCal);
21022 +
21023
21024 #endif /* CALIB_H */
21025 --- a/drivers/net/wireless/ath/ath9k/common.h
21026 +++ b/drivers/net/wireless/ath/ath9k/common.h
21027 @@ -20,6 +20,7 @@
21028 #include "../debug.h"
21029
21030 #include "hw.h"
21031 +#include "hw-ops.h"
21032
21033 /* Common header for Atheros 802.11n base driver cores */
21034
21035 @@ -76,11 +77,12 @@ struct ath_buf {
21036 an aggregate) */
21037 struct ath_buf *bf_next; /* next subframe in the aggregate */
21038 struct sk_buff *bf_mpdu; /* enclosing frame structure */
21039 - struct ath_desc *bf_desc; /* virtual addr of desc */
21040 + void *bf_desc; /* virtual addr of desc */
21041 dma_addr_t bf_daddr; /* physical addr of desc */
21042 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
21043 bool bf_stale;
21044 bool bf_isnullfunc;
21045 + bool bf_tx_aborted;
21046 u16 bf_flags;
21047 struct ath_buf_state bf_state;
21048 dma_addr_t bf_dmacontext;
21049 --- a/drivers/net/wireless/ath/ath9k/debug.c
21050 +++ b/drivers/net/wireless/ath/ath9k/debug.c
21051 @@ -180,8 +180,15 @@ void ath_debug_stat_interrupt(struct ath
21052 {
21053 if (status)
21054 sc->debug.stats.istats.total++;
21055 - if (status & ATH9K_INT_RX)
21056 - sc->debug.stats.istats.rxok++;
21057 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
21058 + if (status & ATH9K_INT_RXLP)
21059 + sc->debug.stats.istats.rxlp++;
21060 + if (status & ATH9K_INT_RXHP)
21061 + sc->debug.stats.istats.rxhp++;
21062 + } else {
21063 + if (status & ATH9K_INT_RX)
21064 + sc->debug.stats.istats.rxok++;
21065 + }
21066 if (status & ATH9K_INT_RXEOL)
21067 sc->debug.stats.istats.rxeol++;
21068 if (status & ATH9K_INT_RXORN)
21069 @@ -223,8 +230,15 @@ static ssize_t read_file_interrupt(struc
21070 char buf[512];
21071 unsigned int len = 0;
21072
21073 - len += snprintf(buf + len, sizeof(buf) - len,
21074 - "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
21075 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
21076 + len += snprintf(buf + len, sizeof(buf) - len,
21077 + "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
21078 + len += snprintf(buf + len, sizeof(buf) - len,
21079 + "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
21080 + } else {
21081 + len += snprintf(buf + len, sizeof(buf) - len,
21082 + "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
21083 + }
21084 len += snprintf(buf + len, sizeof(buf) - len,
21085 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
21086 len += snprintf(buf + len, sizeof(buf) - len,
21087 --- a/drivers/net/wireless/ath/ath9k/debug.h
21088 +++ b/drivers/net/wireless/ath/ath9k/debug.h
21089 @@ -35,6 +35,8 @@ struct ath_buf;
21090 * struct ath_interrupt_stats - Contains statistics about interrupts
21091 * @total: Total no. of interrupts generated so far
21092 * @rxok: RX with no errors
21093 + * @rxlp: RX with low priority RX
21094 + * @rxhp: RX with high priority, uapsd only
21095 * @rxeol: RX with no more RXDESC available
21096 * @rxorn: RX FIFO overrun
21097 * @txok: TX completed at the requested rate
21098 @@ -55,6 +57,8 @@ struct ath_buf;
21099 struct ath_interrupt_stats {
21100 u32 total;
21101 u32 rxok;
21102 + u32 rxlp;
21103 + u32 rxhp;
21104 u32 rxeol;
21105 u32 rxorn;
21106 u32 txok;
21107 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
21108 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
21109 @@ -256,14 +256,13 @@ int ath9k_hw_eeprom_init(struct ath_hw *
21110 {
21111 int status;
21112
21113 - if (AR_SREV_9287(ah)) {
21114 - ah->eep_map = EEP_MAP_AR9287;
21115 - ah->eep_ops = &eep_AR9287_ops;
21116 + if (AR_SREV_9300_20_OR_LATER(ah))
21117 + ah->eep_ops = &eep_ar9300_ops;
21118 + else if (AR_SREV_9287(ah)) {
21119 + ah->eep_ops = &eep_ar9287_ops;
21120 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
21121 - ah->eep_map = EEP_MAP_4KBITS;
21122 ah->eep_ops = &eep_4k_ops;
21123 } else {
21124 - ah->eep_map = EEP_MAP_DEFAULT;
21125 ah->eep_ops = &eep_def_ops;
21126 }
21127
21128 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
21129 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
21130 @@ -19,6 +19,7 @@
21131
21132 #include "../ath.h"
21133 #include <net/cfg80211.h>
21134 +#include "ar9003_eeprom.h"
21135
21136 #define AH_USE_EEPROM 0x1
21137
21138 @@ -93,7 +94,6 @@
21139 */
21140 #define AR9285_RDEXT_DEFAULT 0x1F
21141
21142 -#define AR_EEPROM_MAC(i) (0x1d+(i))
21143 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
21144 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
21145 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
21146 @@ -155,6 +155,7 @@
21147 #define AR5416_BCHAN_UNUSED 0xFF
21148 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
21149 #define AR5416_MAX_CHAINS 3
21150 +#define AR9300_MAX_CHAINS 3
21151 #define AR5416_PWR_TABLE_OFFSET_DB -5
21152
21153 /* Rx gain type values */
21154 @@ -249,16 +250,20 @@ enum eeprom_param {
21155 EEP_MINOR_REV,
21156 EEP_TX_MASK,
21157 EEP_RX_MASK,
21158 + EEP_FSTCLK_5G,
21159 EEP_RXGAIN_TYPE,
21160 - EEP_TXGAIN_TYPE,
21161 EEP_OL_PWRCTRL,
21162 + EEP_TXGAIN_TYPE,
21163 EEP_RC_CHAIN_MASK,
21164 EEP_DAC_HPWR_5G,
21165 EEP_FRAC_N_5G,
21166 EEP_DEV_TYPE,
21167 EEP_TEMPSENSE_SLOPE,
21168 EEP_TEMPSENSE_SLOPE_PAL_ON,
21169 - EEP_PWR_TABLE_OFFSET
21170 + EEP_PWR_TABLE_OFFSET,
21171 + EEP_DRIVE_STRENGTH,
21172 + EEP_INTERNAL_REGULATOR,
21173 + EEP_SWREG
21174 };
21175
21176 enum ar5416_rates {
21177 @@ -656,13 +661,6 @@ struct ath9k_country_entry {
21178 u8 iso[3];
21179 };
21180
21181 -enum ath9k_eep_map {
21182 - EEP_MAP_DEFAULT = 0x0,
21183 - EEP_MAP_4KBITS,
21184 - EEP_MAP_AR9287,
21185 - EEP_MAP_MAX
21186 -};
21187 -
21188 struct eeprom_ops {
21189 int (*check_eeprom)(struct ath_hw *hw);
21190 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
21191 @@ -713,6 +711,8 @@ int ath9k_hw_eeprom_init(struct ath_hw *
21192
21193 extern const struct eeprom_ops eep_def_ops;
21194 extern const struct eeprom_ops eep_4k_ops;
21195 -extern const struct eeprom_ops eep_AR9287_ops;
21196 +extern const struct eeprom_ops eep_ar9287_ops;
21197 +extern const struct eeprom_ops eep_ar9287_ops;
21198 +extern const struct eeprom_ops eep_ar9300_ops;
21199
21200 #endif /* EEPROM_H */
21201 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
21202 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
21203 @@ -15,6 +15,7 @@
21204 */
21205
21206 #include "hw.h"
21207 +#include "ar9002_phy.h"
21208
21209 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
21210 {
21211 @@ -182,11 +183,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct
21212 switch (param) {
21213 case EEP_NFTHRESH_2:
21214 return pModal->noiseFloorThreshCh[0];
21215 - case AR_EEPROM_MAC(0):
21216 + case EEP_MAC_LSW:
21217 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21218 - case AR_EEPROM_MAC(1):
21219 + case EEP_MAC_MID:
21220 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21221 - case AR_EEPROM_MAC(2):
21222 + case EEP_MAC_MSW:
21223 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21224 case EEP_REG_0:
21225 return pBase->regDmn[0];
21226 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
21227 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
21228 @@ -15,6 +15,7 @@
21229 */
21230
21231 #include "hw.h"
21232 +#include "ar9002_phy.h"
21233
21234 static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
21235 {
21236 @@ -172,11 +173,11 @@ static u32 ath9k_hw_AR9287_get_eeprom(st
21237 switch (param) {
21238 case EEP_NFTHRESH_2:
21239 return pModal->noiseFloorThreshCh[0];
21240 - case AR_EEPROM_MAC(0):
21241 + case EEP_MAC_LSW:
21242 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21243 - case AR_EEPROM_MAC(1):
21244 + case EEP_MAC_MID:
21245 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21246 - case AR_EEPROM_MAC(2):
21247 + case EEP_MAC_MSW:
21248 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21249 case EEP_REG_0:
21250 return pBase->regDmn[0];
21251 @@ -1169,7 +1170,7 @@ static u16 ath9k_hw_AR9287_get_spur_chan
21252 #undef EEP_MAP9287_SPURCHAN
21253 }
21254
21255 -const struct eeprom_ops eep_AR9287_ops = {
21256 +const struct eeprom_ops eep_ar9287_ops = {
21257 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
21258 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
21259 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
21260 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
21261 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
21262 @@ -15,6 +15,7 @@
21263 */
21264
21265 #include "hw.h"
21266 +#include "ar9002_phy.h"
21267
21268 static void ath9k_get_txgain_index(struct ath_hw *ah,
21269 struct ath9k_channel *chan,
21270 @@ -222,6 +223,12 @@ static int ath9k_hw_def_check_eeprom(str
21271 return -EINVAL;
21272 }
21273
21274 + /* Enable fixup for AR_AN_TOP2 if necessary */
21275 + if (AR_SREV_9280_10_OR_LATER(ah) &&
21276 + (eep->baseEepHeader.version & 0xff) > 0x0a &&
21277 + eep->baseEepHeader.pwdclkind == 0)
21278 + ah->need_an_top2_fixup = 1;
21279 +
21280 return 0;
21281 }
21282
21283 @@ -237,11 +244,11 @@ static u32 ath9k_hw_def_get_eeprom(struc
21284 return pModal[0].noiseFloorThreshCh[0];
21285 case EEP_NFTHRESH_2:
21286 return pModal[1].noiseFloorThreshCh[0];
21287 - case AR_EEPROM_MAC(0):
21288 + case EEP_MAC_LSW:
21289 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
21290 - case AR_EEPROM_MAC(1):
21291 + case EEP_MAC_MID:
21292 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
21293 - case AR_EEPROM_MAC(2):
21294 + case EEP_MAC_MSW:
21295 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
21296 case EEP_REG_0:
21297 return pBase->regDmn[0];
21298 --- /dev/null
21299 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
21300 @@ -0,0 +1,280 @@
21301 +/*
21302 + * Copyright (c) 2010 Atheros Communications Inc.
21303 + *
21304 + * Permission to use, copy, modify, and/or distribute this software for any
21305 + * purpose with or without fee is hereby granted, provided that the above
21306 + * copyright notice and this permission notice appear in all copies.
21307 + *
21308 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21309 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
21310 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
21311 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
21312 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
21313 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21314 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21315 + */
21316 +
21317 +#ifndef ATH9K_HW_OPS_H
21318 +#define ATH9K_HW_OPS_H
21319 +
21320 +#include "hw.h"
21321 +
21322 +/* Hardware core and driver accessible callbacks */
21323 +
21324 +static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
21325 + int restore,
21326 + int power_off)
21327 +{
21328 + ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
21329 +}
21330 +
21331 +static inline void ath9k_hw_rxena(struct ath_hw *ah)
21332 +{
21333 + ath9k_hw_ops(ah)->rx_enable(ah);
21334 +}
21335 +
21336 +static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
21337 + u32 link)
21338 +{
21339 + ath9k_hw_ops(ah)->set_desc_link(ds, link);
21340 +}
21341 +
21342 +static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
21343 + u32 **link)
21344 +{
21345 + ath9k_hw_ops(ah)->get_desc_link(ds, link);
21346 +}
21347 +static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
21348 + struct ath9k_channel *chan,
21349 + u8 rxchainmask,
21350 + bool longcal)
21351 +{
21352 + return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
21353 +}
21354 +
21355 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
21356 +{
21357 + return ath9k_hw_ops(ah)->get_isr(ah, masked);
21358 +}
21359 +
21360 +static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
21361 + bool is_firstseg, bool is_lastseg,
21362 + const void *ds0, dma_addr_t buf_addr,
21363 + unsigned int qcu)
21364 +{
21365 + ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
21366 + ds0, buf_addr, qcu);
21367 +}
21368 +
21369 +static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
21370 + struct ath_tx_status *ts)
21371 +{
21372 + return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
21373 +}
21374 +
21375 +static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
21376 + u32 pktLen, enum ath9k_pkt_type type,
21377 + u32 txPower, u32 keyIx,
21378 + enum ath9k_key_type keyType,
21379 + u32 flags)
21380 +{
21381 + ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
21382 + keyType, flags);
21383 +}
21384 +
21385 +static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
21386 + void *lastds,
21387 + u32 durUpdateEn, u32 rtsctsRate,
21388 + u32 rtsctsDuration,
21389 + struct ath9k_11n_rate_series series[],
21390 + u32 nseries, u32 flags)
21391 +{
21392 + ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
21393 + rtsctsRate, rtsctsDuration, series,
21394 + nseries, flags);
21395 +}
21396 +
21397 +static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
21398 + u32 aggrLen)
21399 +{
21400 + ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
21401 +}
21402 +
21403 +static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
21404 + u32 numDelims)
21405 +{
21406 + ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
21407 +}
21408 +
21409 +static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
21410 +{
21411 + ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
21412 +}
21413 +
21414 +static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
21415 +{
21416 + ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
21417 +}
21418 +
21419 +static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
21420 + u32 burstDuration)
21421 +{
21422 + ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
21423 +}
21424 +
21425 +static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
21426 + u32 vmf)
21427 +{
21428 + ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
21429 +}
21430 +
21431 +/* Private hardware call ops */
21432 +
21433 +/* PHY ops */
21434 +
21435 +static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
21436 + struct ath9k_channel *chan)
21437 +{
21438 + return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
21439 +}
21440 +
21441 +static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
21442 + struct ath9k_channel *chan)
21443 +{
21444 + ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
21445 +}
21446 +
21447 +static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
21448 +{
21449 + if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
21450 + return 0;
21451 +
21452 + return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
21453 +}
21454 +
21455 +static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
21456 +{
21457 + if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
21458 + return;
21459 +
21460 + ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
21461 +}
21462 +
21463 +static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
21464 + struct ath9k_channel *chan,
21465 + u16 modesIndex)
21466 +{
21467 + if (!ath9k_hw_private_ops(ah)->set_rf_regs)
21468 + return true;
21469 +
21470 + return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
21471 +}
21472 +
21473 +static inline void ath9k_hw_init_bb(struct ath_hw *ah,
21474 + struct ath9k_channel *chan)
21475 +{
21476 + return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
21477 +}
21478 +
21479 +static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
21480 + struct ath9k_channel *chan)
21481 +{
21482 + return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
21483 +}
21484 +
21485 +static inline int ath9k_hw_process_ini(struct ath_hw *ah,
21486 + struct ath9k_channel *chan)
21487 +{
21488 + return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
21489 +}
21490 +
21491 +static inline void ath9k_olc_init(struct ath_hw *ah)
21492 +{
21493 + if (!ath9k_hw_private_ops(ah)->olc_init)
21494 + return;
21495 +
21496 + return ath9k_hw_private_ops(ah)->olc_init(ah);
21497 +}
21498 +
21499 +static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
21500 + struct ath9k_channel *chan)
21501 +{
21502 + return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
21503 +}
21504 +
21505 +static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
21506 +{
21507 + return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
21508 +}
21509 +
21510 +static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
21511 + struct ath9k_channel *chan)
21512 +{
21513 + return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
21514 +}
21515 +
21516 +static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
21517 +{
21518 + return ath9k_hw_private_ops(ah)->rfbus_req(ah);
21519 +}
21520 +
21521 +static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
21522 +{
21523 + return ath9k_hw_private_ops(ah)->rfbus_done(ah);
21524 +}
21525 +
21526 +static inline void ath9k_enable_rfkill(struct ath_hw *ah)
21527 +{
21528 + return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
21529 +}
21530 +
21531 +static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
21532 +{
21533 + if (!ath9k_hw_private_ops(ah)->restore_chainmask)
21534 + return;
21535 +
21536 + return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
21537 +}
21538 +
21539 +static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
21540 +{
21541 + return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
21542 +}
21543 +
21544 +static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
21545 + enum ath9k_ani_cmd cmd, int param)
21546 +{
21547 + return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
21548 +}
21549 +
21550 +static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
21551 + int16_t nfarray[NUM_NF_READINGS])
21552 +{
21553 + ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
21554 +}
21555 +
21556 +static inline void ath9k_hw_loadnf(struct ath_hw *ah,
21557 + struct ath9k_channel *chan)
21558 +{
21559 + ath9k_hw_private_ops(ah)->loadnf(ah, chan);
21560 +}
21561 +
21562 +static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
21563 + struct ath9k_channel *chan)
21564 +{
21565 + return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
21566 +}
21567 +
21568 +static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
21569 + struct ath9k_cal_list *currCal)
21570 +{
21571 + ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
21572 +}
21573 +
21574 +static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
21575 + enum ath9k_cal_types calType)
21576 +{
21577 + return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
21578 +}
21579 +
21580 +#endif /* ATH9K_HW_OPS_H */
21581 --- a/drivers/net/wireless/ath/ath9k/hw.c
21582 +++ b/drivers/net/wireless/ath/ath9k/hw.c
21583 @@ -1,5 +1,5 @@
21584 /*
21585 - * Copyright (c) 2008-2009 Atheros Communications Inc.
21586 + * Copyright (c) 2008-2010 Atheros Communications Inc.
21587 *
21588 * Permission to use, copy, modify, and/or distribute this software for any
21589 * purpose with or without fee is hereby granted, provided that the above
21590 @@ -19,15 +19,15 @@
21591 #include <asm/unaligned.h>
21592
21593 #include "hw.h"
21594 +#include "hw-ops.h"
21595 #include "rc.h"
21596 -#include "initvals.h"
21597 +#include "ar9003_mac.h"
21598
21599 #define ATH9K_CLOCK_RATE_CCK 22
21600 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
21601 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
21602
21603 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
21604 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
21605
21606 MODULE_AUTHOR("Atheros Communications");
21607 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
21608 @@ -46,6 +46,39 @@ static void __exit ath9k_exit(void)
21609 }
21610 module_exit(ath9k_exit);
21611
21612 +/* Private hardware callbacks */
21613 +
21614 +static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
21615 +{
21616 + ath9k_hw_private_ops(ah)->init_cal_settings(ah);
21617 +}
21618 +
21619 +static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
21620 +{
21621 + ath9k_hw_private_ops(ah)->init_mode_regs(ah);
21622 +}
21623 +
21624 +static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
21625 +{
21626 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
21627 +
21628 + return priv_ops->macversion_supported(ah->hw_version.macVersion);
21629 +}
21630 +
21631 +static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
21632 + struct ath9k_channel *chan)
21633 +{
21634 + return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
21635 +}
21636 +
21637 +static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
21638 +{
21639 + if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
21640 + return;
21641 +
21642 + ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
21643 +}
21644 +
21645 /********************/
21646 /* Helper Functions */
21647 /********************/
21648 @@ -233,21 +266,6 @@ static void ath9k_hw_read_revisions(stru
21649 }
21650 }
21651
21652 -static int ath9k_hw_get_radiorev(struct ath_hw *ah)
21653 -{
21654 - u32 val;
21655 - int i;
21656 -
21657 - REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
21658 -
21659 - for (i = 0; i < 8; i++)
21660 - REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
21661 - val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
21662 - val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
21663 -
21664 - return ath9k_hw_reverse_bits(val, 8);
21665 -}
21666 -
21667 /************************************/
21668 /* HW Attach, Detach, Init Routines */
21669 /************************************/
21670 @@ -270,18 +288,25 @@ static void ath9k_hw_disablepcie(struct
21671 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
21672 }
21673
21674 +/* This should work for all families including legacy */
21675 static bool ath9k_hw_chip_test(struct ath_hw *ah)
21676 {
21677 struct ath_common *common = ath9k_hw_common(ah);
21678 - u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
21679 + u32 regAddr[2] = { AR_STA_ID0 };
21680 u32 regHold[2];
21681 u32 patternData[4] = { 0x55555555,
21682 0xaaaaaaaa,
21683 0x66666666,
21684 0x99999999 };
21685 - int i, j;
21686 + int i, j, loop_max;
21687
21688 - for (i = 0; i < 2; i++) {
21689 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
21690 + loop_max = 2;
21691 + regAddr[1] = AR_PHY_BASE + (8 << 2);
21692 + } else
21693 + loop_max = 1;
21694 +
21695 + for (i = 0; i < loop_max; i++) {
21696 u32 addr = regAddr[i];
21697 u32 wrData, rdData;
21698
21699 @@ -336,7 +361,13 @@ static void ath9k_hw_init_config(struct
21700 ah->config.ofdm_trig_high = 500;
21701 ah->config.cck_trig_high = 200;
21702 ah->config.cck_trig_low = 100;
21703 - ah->config.enable_ani = 1;
21704 +
21705 + /*
21706 + * For now ANI is disabled for AR9003, it is still
21707 + * being tested.
21708 + */
21709 + if (!AR_SREV_9300_20_OR_LATER(ah))
21710 + ah->config.enable_ani = 1;
21711
21712 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
21713 ah->config.spurchans[i][0] = AR_NO_SPUR;
21714 @@ -369,7 +400,6 @@ static void ath9k_hw_init_config(struct
21715 if (num_possible_cpus() > 1)
21716 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
21717 }
21718 -EXPORT_SYMBOL(ath9k_hw_init);
21719
21720 static void ath9k_hw_init_defaults(struct ath_hw *ah)
21721 {
21722 @@ -383,8 +413,6 @@ static void ath9k_hw_init_defaults(struc
21723 ah->hw_version.subvendorid = 0;
21724
21725 ah->ah_flags = 0;
21726 - if (ah->hw_version.devid == AR5416_AR9100_DEVID)
21727 - ah->hw_version.macVersion = AR_SREV_VERSION_9100;
21728 if (!AR_SREV_9100(ah))
21729 ah->ah_flags = AH_USE_EEPROM;
21730
21731 @@ -397,44 +425,17 @@ static void ath9k_hw_init_defaults(struc
21732 ah->power_mode = ATH9K_PM_UNDEFINED;
21733 }
21734
21735 -static int ath9k_hw_rf_claim(struct ath_hw *ah)
21736 -{
21737 - u32 val;
21738 -
21739 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
21740 -
21741 - val = ath9k_hw_get_radiorev(ah);
21742 - switch (val & AR_RADIO_SREV_MAJOR) {
21743 - case 0:
21744 - val = AR_RAD5133_SREV_MAJOR;
21745 - break;
21746 - case AR_RAD5133_SREV_MAJOR:
21747 - case AR_RAD5122_SREV_MAJOR:
21748 - case AR_RAD2133_SREV_MAJOR:
21749 - case AR_RAD2122_SREV_MAJOR:
21750 - break;
21751 - default:
21752 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21753 - "Radio Chip Rev 0x%02X not supported\n",
21754 - val & AR_RADIO_SREV_MAJOR);
21755 - return -EOPNOTSUPP;
21756 - }
21757 -
21758 - ah->hw_version.analog5GhzRev = val;
21759 -
21760 - return 0;
21761 -}
21762 -
21763 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
21764 {
21765 struct ath_common *common = ath9k_hw_common(ah);
21766 u32 sum;
21767 int i;
21768 u16 eeval;
21769 + u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
21770
21771 sum = 0;
21772 for (i = 0; i < 3; i++) {
21773 - eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
21774 + eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
21775 sum += eeval;
21776 common->macaddr[2 * i] = eeval >> 8;
21777 common->macaddr[2 * i + 1] = eeval & 0xff;
21778 @@ -445,54 +446,6 @@ static int ath9k_hw_init_macaddr(struct
21779 return 0;
21780 }
21781
21782 -static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
21783 -{
21784 - u32 rxgain_type;
21785 -
21786 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
21787 - rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
21788 -
21789 - if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
21790 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21791 - ar9280Modes_backoff_13db_rxgain_9280_2,
21792 - ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
21793 - else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
21794 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21795 - ar9280Modes_backoff_23db_rxgain_9280_2,
21796 - ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
21797 - else
21798 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21799 - ar9280Modes_original_rxgain_9280_2,
21800 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
21801 - } else {
21802 - INIT_INI_ARRAY(&ah->iniModesRxGain,
21803 - ar9280Modes_original_rxgain_9280_2,
21804 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
21805 - }
21806 -}
21807 -
21808 -static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
21809 -{
21810 - u32 txgain_type;
21811 -
21812 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
21813 - txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
21814 -
21815 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
21816 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21817 - ar9280Modes_high_power_tx_gain_9280_2,
21818 - ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
21819 - else
21820 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21821 - ar9280Modes_original_tx_gain_9280_2,
21822 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
21823 - } else {
21824 - INIT_INI_ARRAY(&ah->iniModesTxGain,
21825 - ar9280Modes_original_tx_gain_9280_2,
21826 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
21827 - }
21828 -}
21829 -
21830 static int ath9k_hw_post_init(struct ath_hw *ah)
21831 {
21832 int ecode;
21833 @@ -502,9 +455,11 @@ static int ath9k_hw_post_init(struct ath
21834 return -ENODEV;
21835 }
21836
21837 - ecode = ath9k_hw_rf_claim(ah);
21838 - if (ecode != 0)
21839 - return ecode;
21840 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
21841 + ecode = ar9002_hw_rf_claim(ah);
21842 + if (ecode != 0)
21843 + return ecode;
21844 + }
21845
21846 ecode = ath9k_hw_eeprom_init(ah);
21847 if (ecode != 0)
21848 @@ -515,14 +470,12 @@ static int ath9k_hw_post_init(struct ath
21849 ah->eep_ops->get_eeprom_ver(ah),
21850 ah->eep_ops->get_eeprom_rev(ah));
21851
21852 - if (!AR_SREV_9280_10_OR_LATER(ah)) {
21853 - ecode = ath9k_hw_rf_alloc_ext_banks(ah);
21854 - if (ecode) {
21855 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21856 - "Failed allocating banks for "
21857 - "external radio\n");
21858 - return ecode;
21859 - }
21860 + ecode = ath9k_hw_rf_alloc_ext_banks(ah);
21861 + if (ecode) {
21862 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
21863 + "Failed allocating banks for "
21864 + "external radio\n");
21865 + return ecode;
21866 }
21867
21868 if (!AR_SREV_9100(ah)) {
21869 @@ -533,344 +486,22 @@ static int ath9k_hw_post_init(struct ath
21870 return 0;
21871 }
21872
21873 -static bool ath9k_hw_devid_supported(u16 devid)
21874 -{
21875 - switch (devid) {
21876 - case AR5416_DEVID_PCI:
21877 - case AR5416_DEVID_PCIE:
21878 - case AR5416_AR9100_DEVID:
21879 - case AR9160_DEVID_PCI:
21880 - case AR9280_DEVID_PCI:
21881 - case AR9280_DEVID_PCIE:
21882 - case AR9285_DEVID_PCIE:
21883 - case AR5416_DEVID_AR9287_PCI:
21884 - case AR5416_DEVID_AR9287_PCIE:
21885 - case AR2427_DEVID_PCIE:
21886 - return true;
21887 - default:
21888 - break;
21889 - }
21890 - return false;
21891 -}
21892 -
21893 -static bool ath9k_hw_macversion_supported(u32 macversion)
21894 -{
21895 - switch (macversion) {
21896 - case AR_SREV_VERSION_5416_PCI:
21897 - case AR_SREV_VERSION_5416_PCIE:
21898 - case AR_SREV_VERSION_9160:
21899 - case AR_SREV_VERSION_9100:
21900 - case AR_SREV_VERSION_9280:
21901 - case AR_SREV_VERSION_9285:
21902 - case AR_SREV_VERSION_9287:
21903 - case AR_SREV_VERSION_9271:
21904 - return true;
21905 - default:
21906 - break;
21907 - }
21908 - return false;
21909 -}
21910 -
21911 -static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
21912 -{
21913 - if (AR_SREV_9160_10_OR_LATER(ah)) {
21914 - if (AR_SREV_9280_10_OR_LATER(ah)) {
21915 - ah->iq_caldata.calData = &iq_cal_single_sample;
21916 - ah->adcgain_caldata.calData =
21917 - &adc_gain_cal_single_sample;
21918 - ah->adcdc_caldata.calData =
21919 - &adc_dc_cal_single_sample;
21920 - ah->adcdc_calinitdata.calData =
21921 - &adc_init_dc_cal;
21922 - } else {
21923 - ah->iq_caldata.calData = &iq_cal_multi_sample;
21924 - ah->adcgain_caldata.calData =
21925 - &adc_gain_cal_multi_sample;
21926 - ah->adcdc_caldata.calData =
21927 - &adc_dc_cal_multi_sample;
21928 - ah->adcdc_calinitdata.calData =
21929 - &adc_init_dc_cal;
21930 - }
21931 - ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
21932 - }
21933 -}
21934 -
21935 -static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
21936 -{
21937 - if (AR_SREV_9271(ah)) {
21938 - INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
21939 - ARRAY_SIZE(ar9271Modes_9271), 6);
21940 - INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
21941 - ARRAY_SIZE(ar9271Common_9271), 2);
21942 - INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
21943 - ar9271Common_normal_cck_fir_coeff_9271,
21944 - ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
21945 - INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
21946 - ar9271Common_japan_2484_cck_fir_coeff_9271,
21947 - ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
21948 - INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
21949 - ar9271Modes_9271_1_0_only,
21950 - ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
21951 - INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
21952 - ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
21953 - INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
21954 - ar9271Modes_high_power_tx_gain_9271,
21955 - ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
21956 - INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
21957 - ar9271Modes_normal_power_tx_gain_9271,
21958 - ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
21959 - return;
21960 - }
21961 -
21962 - if (AR_SREV_9287_11_OR_LATER(ah)) {
21963 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
21964 - ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
21965 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
21966 - ARRAY_SIZE(ar9287Common_9287_1_1), 2);
21967 - if (ah->config.pcie_clock_req)
21968 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21969 - ar9287PciePhy_clkreq_off_L1_9287_1_1,
21970 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
21971 - else
21972 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21973 - ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
21974 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
21975 - 2);
21976 - } else if (AR_SREV_9287_10_OR_LATER(ah)) {
21977 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
21978 - ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
21979 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
21980 - ARRAY_SIZE(ar9287Common_9287_1_0), 2);
21981 -
21982 - if (ah->config.pcie_clock_req)
21983 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21984 - ar9287PciePhy_clkreq_off_L1_9287_1_0,
21985 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
21986 - else
21987 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
21988 - ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
21989 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
21990 - 2);
21991 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
21992 -
21993 -
21994 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
21995 - ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
21996 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
21997 - ARRAY_SIZE(ar9285Common_9285_1_2), 2);
21998 -
21999 - if (ah->config.pcie_clock_req) {
22000 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22001 - ar9285PciePhy_clkreq_off_L1_9285_1_2,
22002 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
22003 - } else {
22004 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22005 - ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
22006 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
22007 - 2);
22008 - }
22009 - } else if (AR_SREV_9285_10_OR_LATER(ah)) {
22010 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
22011 - ARRAY_SIZE(ar9285Modes_9285), 6);
22012 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
22013 - ARRAY_SIZE(ar9285Common_9285), 2);
22014 -
22015 - if (ah->config.pcie_clock_req) {
22016 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22017 - ar9285PciePhy_clkreq_off_L1_9285,
22018 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
22019 - } else {
22020 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22021 - ar9285PciePhy_clkreq_always_on_L1_9285,
22022 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
22023 - }
22024 - } else if (AR_SREV_9280_20_OR_LATER(ah)) {
22025 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
22026 - ARRAY_SIZE(ar9280Modes_9280_2), 6);
22027 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
22028 - ARRAY_SIZE(ar9280Common_9280_2), 2);
22029 -
22030 - if (ah->config.pcie_clock_req) {
22031 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22032 - ar9280PciePhy_clkreq_off_L1_9280,
22033 - ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
22034 - } else {
22035 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
22036 - ar9280PciePhy_clkreq_always_on_L1_9280,
22037 - ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
22038 - }
22039 - INIT_INI_ARRAY(&ah->iniModesAdditional,
22040 - ar9280Modes_fast_clock_9280_2,
22041 - ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
22042 - } else if (AR_SREV_9280_10_OR_LATER(ah)) {
22043 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
22044 - ARRAY_SIZE(ar9280Modes_9280), 6);
22045 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
22046 - ARRAY_SIZE(ar9280Common_9280), 2);
22047 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
22048 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
22049 - ARRAY_SIZE(ar5416Modes_9160), 6);
22050 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
22051 - ARRAY_SIZE(ar5416Common_9160), 2);
22052 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
22053 - ARRAY_SIZE(ar5416Bank0_9160), 2);
22054 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
22055 - ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
22056 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
22057 - ARRAY_SIZE(ar5416Bank1_9160), 2);
22058 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
22059 - ARRAY_SIZE(ar5416Bank2_9160), 2);
22060 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
22061 - ARRAY_SIZE(ar5416Bank3_9160), 3);
22062 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
22063 - ARRAY_SIZE(ar5416Bank6_9160), 3);
22064 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
22065 - ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
22066 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
22067 - ARRAY_SIZE(ar5416Bank7_9160), 2);
22068 - if (AR_SREV_9160_11(ah)) {
22069 - INIT_INI_ARRAY(&ah->iniAddac,
22070 - ar5416Addac_91601_1,
22071 - ARRAY_SIZE(ar5416Addac_91601_1), 2);
22072 - } else {
22073 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
22074 - ARRAY_SIZE(ar5416Addac_9160), 2);
22075 - }
22076 - } else if (AR_SREV_9100_OR_LATER(ah)) {
22077 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
22078 - ARRAY_SIZE(ar5416Modes_9100), 6);
22079 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
22080 - ARRAY_SIZE(ar5416Common_9100), 2);
22081 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
22082 - ARRAY_SIZE(ar5416Bank0_9100), 2);
22083 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
22084 - ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
22085 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
22086 - ARRAY_SIZE(ar5416Bank1_9100), 2);
22087 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
22088 - ARRAY_SIZE(ar5416Bank2_9100), 2);
22089 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
22090 - ARRAY_SIZE(ar5416Bank3_9100), 3);
22091 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
22092 - ARRAY_SIZE(ar5416Bank6_9100), 3);
22093 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
22094 - ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
22095 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
22096 - ARRAY_SIZE(ar5416Bank7_9100), 2);
22097 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
22098 - ARRAY_SIZE(ar5416Addac_9100), 2);
22099 - } else {
22100 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
22101 - ARRAY_SIZE(ar5416Modes), 6);
22102 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
22103 - ARRAY_SIZE(ar5416Common), 2);
22104 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
22105 - ARRAY_SIZE(ar5416Bank0), 2);
22106 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
22107 - ARRAY_SIZE(ar5416BB_RfGain), 3);
22108 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
22109 - ARRAY_SIZE(ar5416Bank1), 2);
22110 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
22111 - ARRAY_SIZE(ar5416Bank2), 2);
22112 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
22113 - ARRAY_SIZE(ar5416Bank3), 3);
22114 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
22115 - ARRAY_SIZE(ar5416Bank6), 3);
22116 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
22117 - ARRAY_SIZE(ar5416Bank6TPC), 3);
22118 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
22119 - ARRAY_SIZE(ar5416Bank7), 2);
22120 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
22121 - ARRAY_SIZE(ar5416Addac), 2);
22122 - }
22123 -}
22124 -
22125 -static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
22126 -{
22127 - if (AR_SREV_9287_11_OR_LATER(ah))
22128 - INIT_INI_ARRAY(&ah->iniModesRxGain,
22129 - ar9287Modes_rx_gain_9287_1_1,
22130 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
22131 - else if (AR_SREV_9287_10(ah))
22132 - INIT_INI_ARRAY(&ah->iniModesRxGain,
22133 - ar9287Modes_rx_gain_9287_1_0,
22134 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
22135 - else if (AR_SREV_9280_20(ah))
22136 - ath9k_hw_init_rxgain_ini(ah);
22137 -
22138 - if (AR_SREV_9287_11_OR_LATER(ah)) {
22139 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22140 - ar9287Modes_tx_gain_9287_1_1,
22141 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
22142 - } else if (AR_SREV_9287_10(ah)) {
22143 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22144 - ar9287Modes_tx_gain_9287_1_0,
22145 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
22146 - } else if (AR_SREV_9280_20(ah)) {
22147 - ath9k_hw_init_txgain_ini(ah);
22148 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
22149 - u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
22150 -
22151 - /* txgain table */
22152 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
22153 - if (AR_SREV_9285E_20(ah)) {
22154 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22155 - ar9285Modes_XE2_0_high_power,
22156 - ARRAY_SIZE(
22157 - ar9285Modes_XE2_0_high_power), 6);
22158 - } else {
22159 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22160 - ar9285Modes_high_power_tx_gain_9285_1_2,
22161 - ARRAY_SIZE(
22162 - ar9285Modes_high_power_tx_gain_9285_1_2), 6);
22163 - }
22164 - } else {
22165 - if (AR_SREV_9285E_20(ah)) {
22166 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22167 - ar9285Modes_XE2_0_normal_power,
22168 - ARRAY_SIZE(
22169 - ar9285Modes_XE2_0_normal_power), 6);
22170 - } else {
22171 - INIT_INI_ARRAY(&ah->iniModesTxGain,
22172 - ar9285Modes_original_tx_gain_9285_1_2,
22173 - ARRAY_SIZE(
22174 - ar9285Modes_original_tx_gain_9285_1_2), 6);
22175 - }
22176 - }
22177 - }
22178 -}
22179 -
22180 -static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
22181 +static void ath9k_hw_attach_ops(struct ath_hw *ah)
22182 {
22183 - struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
22184 - struct ath_common *common = ath9k_hw_common(ah);
22185 -
22186 - ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
22187 - (ah->eep_map != EEP_MAP_4KBITS) &&
22188 - ((pBase->version & 0xff) > 0x0a) &&
22189 - (pBase->pwdclkind == 0);
22190 -
22191 - if (ah->need_an_top2_fixup)
22192 - ath_print(common, ATH_DBG_EEPROM,
22193 - "needs fixup for AR_AN_TOP2 register\n");
22194 + if (AR_SREV_9300_20_OR_LATER(ah))
22195 + ar9003_hw_attach_ops(ah);
22196 + else
22197 + ar9002_hw_attach_ops(ah);
22198 }
22199
22200 -int ath9k_hw_init(struct ath_hw *ah)
22201 +/* Called for all hardware families */
22202 +static int __ath9k_hw_init(struct ath_hw *ah)
22203 {
22204 struct ath_common *common = ath9k_hw_common(ah);
22205 int r = 0;
22206
22207 - if (common->bus_ops->ath_bus_type != ATH_USB) {
22208 - if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
22209 - ath_print(common, ATH_DBG_FATAL,
22210 - "Unsupported device ID: 0x%0x\n",
22211 - ah->hw_version.devid);
22212 - return -EOPNOTSUPP;
22213 - }
22214 - }
22215 -
22216 - ath9k_hw_init_defaults(ah);
22217 - ath9k_hw_init_config(ah);
22218 + if (ah->hw_version.devid == AR5416_AR9100_DEVID)
22219 + ah->hw_version.macVersion = AR_SREV_VERSION_9100;
22220
22221 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
22222 ath_print(common, ATH_DBG_FATAL,
22223 @@ -878,6 +509,11 @@ int ath9k_hw_init(struct ath_hw *ah)
22224 return -EIO;
22225 }
22226
22227 + ath9k_hw_init_defaults(ah);
22228 + ath9k_hw_init_config(ah);
22229 +
22230 + ath9k_hw_attach_ops(ah);
22231 +
22232 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
22233 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
22234 return -EIO;
22235 @@ -902,7 +538,7 @@ int ath9k_hw_init(struct ath_hw *ah)
22236 else
22237 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
22238
22239 - if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
22240 + if (!ath9k_hw_macversion_supported(ah)) {
22241 ath_print(common, ATH_DBG_FATAL,
22242 "Mac Chip Rev 0x%02x.%x is not supported by "
22243 "this driver\n", ah->hw_version.macVersion,
22244 @@ -910,28 +546,15 @@ int ath9k_hw_init(struct ath_hw *ah)
22245 return -EOPNOTSUPP;
22246 }
22247
22248 - if (AR_SREV_9100(ah)) {
22249 - ah->iq_caldata.calData = &iq_cal_multi_sample;
22250 - ah->supp_cals = IQ_MISMATCH_CAL;
22251 - ah->is_pciexpress = false;
22252 - }
22253 -
22254 - if (AR_SREV_9271(ah))
22255 + if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
22256 ah->is_pciexpress = false;
22257
22258 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
22259 -
22260 ath9k_hw_init_cal_settings(ah);
22261
22262 ah->ani_function = ATH9K_ANI_ALL;
22263 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22264 + if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
22265 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
22266 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
22267 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
22268 - } else {
22269 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
22270 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
22271 - }
22272
22273 ath9k_hw_init_mode_regs(ah);
22274
22275 @@ -940,15 +563,8 @@ int ath9k_hw_init(struct ath_hw *ah)
22276 else
22277 ath9k_hw_disablepcie(ah);
22278
22279 - /* Support for Japan ch.14 (2484) spread */
22280 - if (AR_SREV_9287_11_OR_LATER(ah)) {
22281 - INIT_INI_ARRAY(&ah->iniCckfirNormal,
22282 - ar9287Common_normal_cck_fir_coeff_92871_1,
22283 - ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
22284 - INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
22285 - ar9287Common_japan_2484_cck_fir_coeff_92871_1,
22286 - ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
22287 - }
22288 + if (!AR_SREV_9300_20_OR_LATER(ah))
22289 + ar9002_hw_cck_chan14_spread(ah);
22290
22291 r = ath9k_hw_post_init(ah);
22292 if (r)
22293 @@ -959,8 +575,6 @@ int ath9k_hw_init(struct ath_hw *ah)
22294 if (r)
22295 return r;
22296
22297 - ath9k_hw_init_eeprom_fix(ah);
22298 -
22299 r = ath9k_hw_init_macaddr(ah);
22300 if (r) {
22301 ath_print(common, ATH_DBG_FATAL,
22302 @@ -973,6 +587,9 @@ int ath9k_hw_init(struct ath_hw *ah)
22303 else
22304 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
22305
22306 + if (AR_SREV_9300_20_OR_LATER(ah))
22307 + ar9003_hw_set_nf_limits(ah);
22308 +
22309 ath9k_init_nfcal_hist_buffer(ah);
22310
22311 common->state = ATH_HW_INITIALIZED;
22312 @@ -980,21 +597,45 @@ int ath9k_hw_init(struct ath_hw *ah)
22313 return 0;
22314 }
22315
22316 -static void ath9k_hw_init_bb(struct ath_hw *ah,
22317 - struct ath9k_channel *chan)
22318 +int ath9k_hw_init(struct ath_hw *ah)
22319 {
22320 - u32 synthDelay;
22321 + int ret;
22322 + struct ath_common *common = ath9k_hw_common(ah);
22323
22324 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
22325 - if (IS_CHAN_B(chan))
22326 - synthDelay = (4 * synthDelay) / 22;
22327 - else
22328 - synthDelay /= 10;
22329 + /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
22330 + switch (ah->hw_version.devid) {
22331 + case AR5416_DEVID_PCI:
22332 + case AR5416_DEVID_PCIE:
22333 + case AR5416_AR9100_DEVID:
22334 + case AR9160_DEVID_PCI:
22335 + case AR9280_DEVID_PCI:
22336 + case AR9280_DEVID_PCIE:
22337 + case AR9285_DEVID_PCIE:
22338 + case AR9287_DEVID_PCI:
22339 + case AR9287_DEVID_PCIE:
22340 + case AR2427_DEVID_PCIE:
22341 + case AR9300_DEVID_PCIE:
22342 + break;
22343 + default:
22344 + if (common->bus_ops->ath_bus_type == ATH_USB)
22345 + break;
22346 + ath_print(common, ATH_DBG_FATAL,
22347 + "Hardware device ID 0x%04x not supported\n",
22348 + ah->hw_version.devid);
22349 + return -EOPNOTSUPP;
22350 + }
22351
22352 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
22353 + ret = __ath9k_hw_init(ah);
22354 + if (ret) {
22355 + ath_print(common, ATH_DBG_FATAL,
22356 + "Unable to initialize hardware; "
22357 + "initialization status: %d\n", ret);
22358 + return ret;
22359 + }
22360
22361 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
22362 + return 0;
22363 }
22364 +EXPORT_SYMBOL(ath9k_hw_init);
22365
22366 static void ath9k_hw_init_qos(struct ath_hw *ah)
22367 {
22368 @@ -1016,64 +657,8 @@ static void ath9k_hw_init_qos(struct ath
22369 static void ath9k_hw_init_pll(struct ath_hw *ah,
22370 struct ath9k_channel *chan)
22371 {
22372 - u32 pll;
22373 -
22374 - if (AR_SREV_9100(ah)) {
22375 - if (chan && IS_CHAN_5GHZ(chan))
22376 - pll = 0x1450;
22377 - else
22378 - pll = 0x1458;
22379 - } else {
22380 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22381 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
22382 -
22383 - if (chan && IS_CHAN_HALF_RATE(chan))
22384 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
22385 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22386 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
22387 -
22388 - if (chan && IS_CHAN_5GHZ(chan)) {
22389 - pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
22390 -
22391 -
22392 - if (AR_SREV_9280_20(ah)) {
22393 - if (((chan->channel % 20) == 0)
22394 - || ((chan->channel % 10) == 0))
22395 - pll = 0x2850;
22396 - else
22397 - pll = 0x142c;
22398 - }
22399 - } else {
22400 - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
22401 - }
22402 + u32 pll = ath9k_hw_compute_pll_control(ah, chan);
22403
22404 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
22405 -
22406 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
22407 -
22408 - if (chan && IS_CHAN_HALF_RATE(chan))
22409 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
22410 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22411 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
22412 -
22413 - if (chan && IS_CHAN_5GHZ(chan))
22414 - pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
22415 - else
22416 - pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
22417 - } else {
22418 - pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
22419 -
22420 - if (chan && IS_CHAN_HALF_RATE(chan))
22421 - pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
22422 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
22423 - pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
22424 -
22425 - if (chan && IS_CHAN_5GHZ(chan))
22426 - pll |= SM(0xa, AR_RTC_PLL_DIV);
22427 - else
22428 - pll |= SM(0xb, AR_RTC_PLL_DIV);
22429 - }
22430 - }
22431 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
22432
22433 /* Switch the core clock for ar9271 to 117Mhz */
22434 @@ -1087,43 +672,6 @@ static void ath9k_hw_init_pll(struct ath
22435 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
22436 }
22437
22438 -static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
22439 -{
22440 - int rx_chainmask, tx_chainmask;
22441 -
22442 - rx_chainmask = ah->rxchainmask;
22443 - tx_chainmask = ah->txchainmask;
22444 -
22445 - switch (rx_chainmask) {
22446 - case 0x5:
22447 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
22448 - AR_PHY_SWAP_ALT_CHAIN);
22449 - case 0x3:
22450 - if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
22451 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
22452 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
22453 - break;
22454 - }
22455 - case 0x1:
22456 - case 0x2:
22457 - case 0x7:
22458 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
22459 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
22460 - break;
22461 - default:
22462 - break;
22463 - }
22464 -
22465 - REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
22466 - if (tx_chainmask == 0x5) {
22467 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
22468 - AR_PHY_SWAP_ALT_CHAIN);
22469 - }
22470 - if (AR_SREV_9100(ah))
22471 - REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
22472 - REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
22473 -}
22474 -
22475 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
22476 enum nl80211_iftype opmode)
22477 {
22478 @@ -1133,12 +681,24 @@ static void ath9k_hw_init_interrupt_mask
22479 AR_IMR_RXORN |
22480 AR_IMR_BCNMISC;
22481
22482 - if (ah->config.rx_intr_mitigation)
22483 - imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22484 - else
22485 - imr_reg |= AR_IMR_RXOK;
22486 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22487 + imr_reg |= AR_IMR_RXOK_HP;
22488 + if (ah->config.rx_intr_mitigation)
22489 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22490 + else
22491 + imr_reg |= AR_IMR_RXOK_LP;
22492
22493 - imr_reg |= AR_IMR_TXOK;
22494 + } else {
22495 + if (ah->config.rx_intr_mitigation)
22496 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
22497 + else
22498 + imr_reg |= AR_IMR_RXOK;
22499 + }
22500 +
22501 + if (ah->config.tx_intr_mitigation)
22502 + imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
22503 + else
22504 + imr_reg |= AR_IMR_TXOK;
22505
22506 if (opmode == NL80211_IFTYPE_AP)
22507 imr_reg |= AR_IMR_MIB;
22508 @@ -1152,6 +712,13 @@ static void ath9k_hw_init_interrupt_mask
22509 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
22510 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
22511 }
22512 +
22513 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22514 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
22515 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
22516 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
22517 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
22518 + }
22519 }
22520
22521 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
22522 @@ -1215,310 +782,72 @@ void ath9k_hw_init_global_settings(struc
22523 /*
22524 * Workaround for early ACK timeouts, add an offset to match the
22525 * initval's 64us ack timeout value.
22526 - * This was initially only meant to work around an issue with delayed
22527 - * BA frames in some implementations, but it has been found to fix ACK
22528 - * timeout issues in other cases as well.
22529 - */
22530 - if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
22531 - acktimeout += 64 - sifstime - ah->slottime;
22532 -
22533 - ath9k_hw_setslottime(ah, slottime);
22534 - ath9k_hw_set_ack_timeout(ah, acktimeout);
22535 - ath9k_hw_set_cts_timeout(ah, acktimeout);
22536 - if (ah->globaltxtimeout != (u32) -1)
22537 - ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
22538 -}
22539 -EXPORT_SYMBOL(ath9k_hw_init_global_settings);
22540 -
22541 -void ath9k_hw_deinit(struct ath_hw *ah)
22542 -{
22543 - struct ath_common *common = ath9k_hw_common(ah);
22544 -
22545 - if (common->state < ATH_HW_INITIALIZED)
22546 - goto free_hw;
22547 -
22548 - if (!AR_SREV_9100(ah))
22549 - ath9k_hw_ani_disable(ah);
22550 -
22551 - ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
22552 -
22553 -free_hw:
22554 - if (!AR_SREV_9280_10_OR_LATER(ah))
22555 - ath9k_hw_rf_free_ext_banks(ah);
22556 -}
22557 -EXPORT_SYMBOL(ath9k_hw_deinit);
22558 -
22559 -/*******/
22560 -/* INI */
22561 -/*******/
22562 -
22563 -static void ath9k_hw_override_ini(struct ath_hw *ah,
22564 - struct ath9k_channel *chan)
22565 -{
22566 - u32 val;
22567 -
22568 - /*
22569 - * Set the RX_ABORT and RX_DIS and clear if off only after
22570 - * RXE is set for MAC. This prevents frames with corrupted
22571 - * descriptor status.
22572 - */
22573 - REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
22574 -
22575 - if (AR_SREV_9280_10_OR_LATER(ah)) {
22576 - val = REG_READ(ah, AR_PCU_MISC_MODE2);
22577 -
22578 - if (!AR_SREV_9271(ah))
22579 - val &= ~AR_PCU_MISC_MODE2_HWWAR1;
22580 -
22581 - if (AR_SREV_9287_10_OR_LATER(ah))
22582 - val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
22583 -
22584 - REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
22585 - }
22586 -
22587 - if (!AR_SREV_5416_20_OR_LATER(ah) ||
22588 - AR_SREV_9280_10_OR_LATER(ah))
22589 - return;
22590 - /*
22591 - * Disable BB clock gating
22592 - * Necessary to avoid issues on AR5416 2.0
22593 - */
22594 - REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
22595 -
22596 - /*
22597 - * Disable RIFS search on some chips to avoid baseband
22598 - * hang issues.
22599 - */
22600 - if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
22601 - val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
22602 - val &= ~AR_PHY_RIFS_INIT_DELAY;
22603 - REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
22604 - }
22605 -}
22606 -
22607 -static void ath9k_olc_init(struct ath_hw *ah)
22608 -{
22609 - u32 i;
22610 -
22611 - if (OLC_FOR_AR9287_10_LATER) {
22612 - REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
22613 - AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
22614 - ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
22615 - AR9287_AN_TXPC0_TXPCMODE,
22616 - AR9287_AN_TXPC0_TXPCMODE_S,
22617 - AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
22618 - udelay(100);
22619 - } else {
22620 - for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
22621 - ah->originalGain[i] =
22622 - MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
22623 - AR_PHY_TX_GAIN);
22624 - ah->PDADCdelta = 0;
22625 - }
22626 -}
22627 -
22628 -static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
22629 - struct ath9k_channel *chan)
22630 -{
22631 - u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
22632 -
22633 - if (IS_CHAN_B(chan))
22634 - ctl |= CTL_11B;
22635 - else if (IS_CHAN_G(chan))
22636 - ctl |= CTL_11G;
22637 - else
22638 - ctl |= CTL_11A;
22639 -
22640 - return ctl;
22641 -}
22642 -
22643 -static int ath9k_hw_process_ini(struct ath_hw *ah,
22644 - struct ath9k_channel *chan)
22645 -{
22646 - struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
22647 - int i, regWrites = 0;
22648 - struct ieee80211_channel *channel = chan->chan;
22649 - u32 modesIndex, freqIndex;
22650 -
22651 - switch (chan->chanmode) {
22652 - case CHANNEL_A:
22653 - case CHANNEL_A_HT20:
22654 - modesIndex = 1;
22655 - freqIndex = 1;
22656 - break;
22657 - case CHANNEL_A_HT40PLUS:
22658 - case CHANNEL_A_HT40MINUS:
22659 - modesIndex = 2;
22660 - freqIndex = 1;
22661 - break;
22662 - case CHANNEL_G:
22663 - case CHANNEL_G_HT20:
22664 - case CHANNEL_B:
22665 - modesIndex = 4;
22666 - freqIndex = 2;
22667 - break;
22668 - case CHANNEL_G_HT40PLUS:
22669 - case CHANNEL_G_HT40MINUS:
22670 - modesIndex = 3;
22671 - freqIndex = 2;
22672 - break;
22673 -
22674 - default:
22675 - return -EINVAL;
22676 - }
22677 -
22678 - /* Set correct baseband to analog shift setting to access analog chips */
22679 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
22680 -
22681 - /* Write ADDAC shifts */
22682 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
22683 - ah->eep_ops->set_addac(ah, chan);
22684 -
22685 - if (AR_SREV_5416_22_OR_LATER(ah)) {
22686 - REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
22687 - } else {
22688 - struct ar5416IniArray temp;
22689 - u32 addacSize =
22690 - sizeof(u32) * ah->iniAddac.ia_rows *
22691 - ah->iniAddac.ia_columns;
22692 -
22693 - /* For AR5416 2.0/2.1 */
22694 - memcpy(ah->addac5416_21,
22695 - ah->iniAddac.ia_array, addacSize);
22696 -
22697 - /* override CLKDRV value at [row, column] = [31, 1] */
22698 - (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
22699 -
22700 - temp.ia_array = ah->addac5416_21;
22701 - temp.ia_columns = ah->iniAddac.ia_columns;
22702 - temp.ia_rows = ah->iniAddac.ia_rows;
22703 - REG_WRITE_ARRAY(&temp, 1, regWrites);
22704 - }
22705 -
22706 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
22707 -
22708 - for (i = 0; i < ah->iniModes.ia_rows; i++) {
22709 - u32 reg = INI_RA(&ah->iniModes, i, 0);
22710 - u32 val = INI_RA(&ah->iniModes, i, modesIndex);
22711 -
22712 - if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
22713 - val &= ~AR_AN_TOP2_PWDCLKIND;
22714 -
22715 - REG_WRITE(ah, reg, val);
22716 -
22717 - if (reg >= 0x7800 && reg < 0x78a0
22718 - && ah->config.analog_shiftreg) {
22719 - udelay(100);
22720 - }
22721 -
22722 - DO_DELAY(regWrites);
22723 - }
22724 -
22725 - if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
22726 - REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
22727 -
22728 - if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
22729 - AR_SREV_9287_10_OR_LATER(ah))
22730 - REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
22731 -
22732 - if (AR_SREV_9271_10(ah))
22733 - REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
22734 - modesIndex, regWrites);
22735 -
22736 - /* Write common array parameters */
22737 - for (i = 0; i < ah->iniCommon.ia_rows; i++) {
22738 - u32 reg = INI_RA(&ah->iniCommon, i, 0);
22739 - u32 val = INI_RA(&ah->iniCommon, i, 1);
22740 -
22741 - REG_WRITE(ah, reg, val);
22742 -
22743 - if (reg >= 0x7800 && reg < 0x78a0
22744 - && ah->config.analog_shiftreg) {
22745 - udelay(100);
22746 - }
22747 -
22748 - DO_DELAY(regWrites);
22749 - }
22750 -
22751 - if (AR_SREV_9271(ah)) {
22752 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
22753 - REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
22754 - modesIndex, regWrites);
22755 - else
22756 - REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
22757 - modesIndex, regWrites);
22758 - }
22759 -
22760 - ath9k_hw_write_regs(ah, freqIndex, regWrites);
22761 + * This was initially only meant to work around an issue with delayed
22762 + * BA frames in some implementations, but it has been found to fix ACK
22763 + * timeout issues in other cases as well.
22764 + */
22765 + if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
22766 + acktimeout += 64 - sifstime - ah->slottime;
22767
22768 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
22769 - REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
22770 - regWrites);
22771 - }
22772 + ath9k_hw_setslottime(ah, slottime);
22773 + ath9k_hw_set_ack_timeout(ah, acktimeout);
22774 + ath9k_hw_set_cts_timeout(ah, acktimeout);
22775 + if (ah->globaltxtimeout != (u32) -1)
22776 + ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
22777 +}
22778 +EXPORT_SYMBOL(ath9k_hw_init_global_settings);
22779
22780 - ath9k_hw_override_ini(ah, chan);
22781 - ath9k_hw_set_regs(ah, chan);
22782 - ath9k_hw_init_chain_masks(ah);
22783 +void ath9k_hw_deinit(struct ath_hw *ah)
22784 +{
22785 + struct ath_common *common = ath9k_hw_common(ah);
22786
22787 - if (OLC_FOR_AR9280_20_LATER)
22788 - ath9k_olc_init(ah);
22789 + if (common->state < ATH_HW_INITIALIZED)
22790 + goto free_hw;
22791
22792 - /* Set TX power */
22793 - ah->eep_ops->set_txpower(ah, chan,
22794 - ath9k_regd_get_ctl(regulatory, chan),
22795 - channel->max_antenna_gain * 2,
22796 - channel->max_power * 2,
22797 - min((u32) MAX_RATE_POWER,
22798 - (u32) regulatory->power_limit));
22799 + if (!AR_SREV_9100(ah))
22800 + ath9k_hw_ani_disable(ah);
22801
22802 - /* Write analog registers */
22803 - if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
22804 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
22805 - "ar5416SetRfRegs failed\n");
22806 - return -EIO;
22807 - }
22808 + ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
22809
22810 - return 0;
22811 +free_hw:
22812 + ath9k_hw_rf_free_ext_banks(ah);
22813 }
22814 +EXPORT_SYMBOL(ath9k_hw_deinit);
22815
22816 -/****************************************/
22817 -/* Reset and Channel Switching Routines */
22818 -/****************************************/
22819 +/*******/
22820 +/* INI */
22821 +/*******/
22822
22823 -static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
22824 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
22825 {
22826 - u32 rfMode = 0;
22827 -
22828 - if (chan == NULL)
22829 - return;
22830 -
22831 - rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
22832 - ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
22833 -
22834 - if (!AR_SREV_9280_10_OR_LATER(ah))
22835 - rfMode |= (IS_CHAN_5GHZ(chan)) ?
22836 - AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
22837 + u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
22838
22839 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
22840 - rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
22841 + if (IS_CHAN_B(chan))
22842 + ctl |= CTL_11B;
22843 + else if (IS_CHAN_G(chan))
22844 + ctl |= CTL_11G;
22845 + else
22846 + ctl |= CTL_11A;
22847
22848 - REG_WRITE(ah, AR_PHY_MODE, rfMode);
22849 + return ctl;
22850 }
22851
22852 -static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
22853 -{
22854 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
22855 -}
22856 +/****************************************/
22857 +/* Reset and Channel Switching Routines */
22858 +/****************************************/
22859
22860 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
22861 {
22862 + struct ath_common *common = ath9k_hw_common(ah);
22863 u32 regval;
22864
22865 /*
22866 * set AHB_MODE not to do cacheline prefetches
22867 */
22868 - regval = REG_READ(ah, AR_AHB_MODE);
22869 - REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
22870 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
22871 + regval = REG_READ(ah, AR_AHB_MODE);
22872 + REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
22873 + }
22874
22875 /*
22876 * let mac dma reads be in 128 byte chunks
22877 @@ -1531,7 +860,8 @@ static inline void ath9k_hw_set_dma(stru
22878 * The initial value depends on whether aggregation is enabled, and is
22879 * adjusted whenever underruns are detected.
22880 */
22881 - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
22882 + if (!AR_SREV_9300_20_OR_LATER(ah))
22883 + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
22884
22885 /*
22886 * let mac dma writes be in 128 byte chunks
22887 @@ -1544,6 +874,14 @@ static inline void ath9k_hw_set_dma(stru
22888 */
22889 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
22890
22891 + if (AR_SREV_9300_20_OR_LATER(ah)) {
22892 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
22893 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
22894 +
22895 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
22896 + ah->caps.rx_status_len);
22897 + }
22898 +
22899 /*
22900 * reduce the number of usable entries in PCU TXBUF to avoid
22901 * wrap around issues.
22902 @@ -1559,6 +897,9 @@ static inline void ath9k_hw_set_dma(stru
22903 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
22904 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
22905 }
22906 +
22907 + if (AR_SREV_9300_20_OR_LATER(ah))
22908 + ath9k_hw_reset_txstatus_ring(ah);
22909 }
22910
22911 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
22912 @@ -1586,10 +927,8 @@ static void ath9k_hw_set_operating_mode(
22913 }
22914 }
22915
22916 -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
22917 - u32 coef_scaled,
22918 - u32 *coef_mantissa,
22919 - u32 *coef_exponent)
22920 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
22921 + u32 *coef_mantissa, u32 *coef_exponent)
22922 {
22923 u32 coef_exp, coef_man;
22924
22925 @@ -1605,40 +944,6 @@ static inline void ath9k_hw_get_delta_sl
22926 *coef_exponent = coef_exp - 16;
22927 }
22928
22929 -static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
22930 - struct ath9k_channel *chan)
22931 -{
22932 - u32 coef_scaled, ds_coef_exp, ds_coef_man;
22933 - u32 clockMhzScaled = 0x64000000;
22934 - struct chan_centers centers;
22935 -
22936 - if (IS_CHAN_HALF_RATE(chan))
22937 - clockMhzScaled = clockMhzScaled >> 1;
22938 - else if (IS_CHAN_QUARTER_RATE(chan))
22939 - clockMhzScaled = clockMhzScaled >> 2;
22940 -
22941 - ath9k_hw_get_channel_centers(ah, chan, &centers);
22942 - coef_scaled = clockMhzScaled / centers.synth_center;
22943 -
22944 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
22945 - &ds_coef_exp);
22946 -
22947 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
22948 - AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
22949 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
22950 - AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
22951 -
22952 - coef_scaled = (9 * coef_scaled) / 10;
22953 -
22954 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
22955 - &ds_coef_exp);
22956 -
22957 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
22958 - AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
22959 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
22960 - AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
22961 -}
22962 -
22963 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
22964 {
22965 u32 rst_flags;
22966 @@ -1663,11 +968,16 @@ static bool ath9k_hw_set_reset(struct at
22967 if (tmpReg &
22968 (AR_INTR_SYNC_LOCAL_TIMEOUT |
22969 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
22970 + u32 val;
22971 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
22972 - REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
22973 - } else {
22974 +
22975 + val = AR_RC_HOSTIF;
22976 + if (!AR_SREV_9300_20_OR_LATER(ah))
22977 + val |= AR_RC_AHB;
22978 + REG_WRITE(ah, AR_RC, val);
22979 +
22980 + } else if (!AR_SREV_9300_20_OR_LATER(ah))
22981 REG_WRITE(ah, AR_RC, AR_RC_AHB);
22982 - }
22983
22984 rst_flags = AR_RTC_RC_MAC_WARM;
22985 if (type == ATH9K_RESET_COLD)
22986 @@ -1698,13 +1008,15 @@ static bool ath9k_hw_set_reset_power_on(
22987 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
22988 AR_RTC_FORCE_WAKE_ON_INT);
22989
22990 - if (!AR_SREV_9100(ah))
22991 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
22992 REG_WRITE(ah, AR_RC, AR_RC_AHB);
22993
22994 REG_WRITE(ah, AR_RTC_RESET, 0);
22995 - udelay(2);
22996
22997 - if (!AR_SREV_9100(ah))
22998 + if (!AR_SREV_9300_20_OR_LATER(ah))
22999 + udelay(2);
23000 +
23001 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
23002 REG_WRITE(ah, AR_RC, 0);
23003
23004 REG_WRITE(ah, AR_RTC_RESET, 1);
23005 @@ -1740,34 +1052,6 @@ static bool ath9k_hw_set_reset_reg(struc
23006 }
23007 }
23008
23009 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
23010 -{
23011 - u32 phymode;
23012 - u32 enableDacFifo = 0;
23013 -
23014 - if (AR_SREV_9285_10_OR_LATER(ah))
23015 - enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
23016 - AR_PHY_FC_ENABLE_DAC_FIFO);
23017 -
23018 - phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
23019 - | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
23020 -
23021 - if (IS_CHAN_HT40(chan)) {
23022 - phymode |= AR_PHY_FC_DYN2040_EN;
23023 -
23024 - if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
23025 - (chan->chanmode == CHANNEL_G_HT40PLUS))
23026 - phymode |= AR_PHY_FC_DYN2040_PRI_CH;
23027 -
23028 - }
23029 - REG_WRITE(ah, AR_PHY_TURBO, phymode);
23030 -
23031 - ath9k_hw_set11nmac2040(ah);
23032 -
23033 - REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
23034 - REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
23035 -}
23036 -
23037 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
23038 struct ath9k_channel *chan)
23039 {
23040 @@ -1793,7 +1077,7 @@ static bool ath9k_hw_channel_change(stru
23041 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
23042 struct ath_common *common = ath9k_hw_common(ah);
23043 struct ieee80211_channel *channel = chan->chan;
23044 - u32 synthDelay, qnum;
23045 + u32 qnum;
23046 int r;
23047
23048 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
23049 @@ -1805,17 +1089,15 @@ static bool ath9k_hw_channel_change(stru
23050 }
23051 }
23052
23053 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
23054 - if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
23055 - AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
23056 + if (!ath9k_hw_rfbus_req(ah)) {
23057 ath_print(common, ATH_DBG_FATAL,
23058 "Could not kill baseband RX\n");
23059 return false;
23060 }
23061
23062 - ath9k_hw_set_regs(ah, chan);
23063 + ath9k_hw_set_channel_regs(ah, chan);
23064
23065 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
23066 + r = ath9k_hw_rf_set_freq(ah, chan);
23067 if (r) {
23068 ath_print(common, ATH_DBG_FATAL,
23069 "Failed to set channel\n");
23070 @@ -1829,20 +1111,12 @@ static bool ath9k_hw_channel_change(stru
23071 min((u32) MAX_RATE_POWER,
23072 (u32) regulatory->power_limit));
23073
23074 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
23075 - if (IS_CHAN_B(chan))
23076 - synthDelay = (4 * synthDelay) / 22;
23077 - else
23078 - synthDelay /= 10;
23079 -
23080 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
23081 -
23082 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
23083 + ath9k_hw_rfbus_done(ah);
23084
23085 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
23086 ath9k_hw_set_delta_slope(ah, chan);
23087
23088 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
23089 + ath9k_hw_spur_mitigate_freq(ah, chan);
23090
23091 if (!chan->oneTimeCalsDone)
23092 chan->oneTimeCalsDone = true;
23093 @@ -1850,18 +1124,6 @@ static bool ath9k_hw_channel_change(stru
23094 return true;
23095 }
23096
23097 -static void ath9k_enable_rfkill(struct ath_hw *ah)
23098 -{
23099 - REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
23100 - AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
23101 -
23102 - REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
23103 - AR_GPIO_INPUT_MUX2_RFSILENT);
23104 -
23105 - ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
23106 - REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
23107 -}
23108 -
23109 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
23110 bool bChannelChange)
23111 {
23112 @@ -1871,11 +1133,18 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23113 u32 saveDefAntenna;
23114 u32 macStaId1;
23115 u64 tsf = 0;
23116 - int i, rx_chainmask, r;
23117 + int i, r;
23118
23119 ah->txchainmask = common->tx_chainmask;
23120 ah->rxchainmask = common->rx_chainmask;
23121
23122 + if (!ah->chip_fullsleep) {
23123 + ath9k_hw_abortpcurecv(ah);
23124 + if (!ath9k_hw_stopdmarecv(ah))
23125 + ath_print(common, ATH_DBG_XMIT,
23126 + "Failed to stop receive dma\n");
23127 + }
23128 +
23129 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
23130 return -EIO;
23131
23132 @@ -1943,16 +1212,6 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23133 if (AR_SREV_9280_10_OR_LATER(ah))
23134 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
23135
23136 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23137 - /* Enable ASYNC FIFO */
23138 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23139 - AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
23140 - REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
23141 - REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23142 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
23143 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
23144 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
23145 - }
23146 r = ath9k_hw_process_ini(ah, chan);
23147 if (r)
23148 return r;
23149 @@ -1977,7 +1236,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23150 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
23151 ath9k_hw_set_delta_slope(ah, chan);
23152
23153 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
23154 + ath9k_hw_spur_mitigate_freq(ah, chan);
23155 ah->eep_ops->set_board_values(ah, chan);
23156
23157 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
23158 @@ -1999,7 +1258,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23159
23160 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
23161
23162 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
23163 + r = ath9k_hw_rf_set_freq(ah, chan);
23164 if (r)
23165 return r;
23166
23167 @@ -2018,25 +1277,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23168
23169 ath9k_hw_init_global_settings(ah);
23170
23171 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23172 - REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
23173 - AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
23174 - REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
23175 - AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
23176 - REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
23177 - AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
23178 -
23179 - REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
23180 - REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
23181 -
23182 - REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
23183 - AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
23184 - REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
23185 - AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
23186 - }
23187 - if (AR_SREV_9287_12_OR_LATER(ah)) {
23188 - REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
23189 - AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
23190 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
23191 + ar9002_hw_enable_async_fifo(ah);
23192 + ar9002_hw_enable_wep_aggregation(ah);
23193 }
23194
23195 REG_WRITE(ah, AR_STA_ID1,
23196 @@ -2051,17 +1294,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23197 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
23198 }
23199
23200 + if (ah->config.tx_intr_mitigation) {
23201 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
23202 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
23203 + }
23204 +
23205 ath9k_hw_init_bb(ah, chan);
23206
23207 if (!ath9k_hw_init_cal(ah, chan))
23208 return -EIO;
23209
23210 - rx_chainmask = ah->rxchainmask;
23211 - if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
23212 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
23213 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
23214 - }
23215 -
23216 + ath9k_hw_restore_chainmask(ah);
23217 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
23218
23219 /*
23220 @@ -2093,6 +1336,11 @@ int ath9k_hw_reset(struct ath_hw *ah, st
23221 if (ah->btcoex_hw.enabled)
23222 ath9k_hw_btcoex_enable(ah);
23223
23224 + if (AR_SREV_9300_20_OR_LATER(ah)) {
23225 + ath9k_hw_loadnf(ah, curchan);
23226 + ath9k_hw_start_nfcal(ah);
23227 + }
23228 +
23229 return 0;
23230 }
23231 EXPORT_SYMBOL(ath9k_hw_reset);
23232 @@ -2379,21 +1627,35 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
23233 /* Power Management (Chipset) */
23234 /******************************/
23235
23236 +/*
23237 + * Notify Power Mgt is disabled in self-generated frames.
23238 + * If requested, force chip to sleep.
23239 + */
23240 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
23241 {
23242 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
23243 if (setChip) {
23244 + /*
23245 + * Clear the RTC force wake bit to allow the
23246 + * mac to go to sleep.
23247 + */
23248 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
23249 AR_RTC_FORCE_WAKE_EN);
23250 - if (!AR_SREV_9100(ah))
23251 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
23252 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
23253
23254 + /* Shutdown chip. Active low */
23255 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
23256 REG_CLR_BIT(ah, (AR_RTC_RESET),
23257 AR_RTC_RESET_EN);
23258 }
23259 }
23260
23261 +/*
23262 + * Notify Power Management is enabled in self-generating
23263 + * frames. If request, set power mode of chip to
23264 + * auto/normal. Duration in units of 128us (1/8 TU).
23265 + */
23266 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
23267 {
23268 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
23269 @@ -2401,9 +1663,14 @@ static void ath9k_set_power_network_slee
23270 struct ath9k_hw_capabilities *pCap = &ah->caps;
23271
23272 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23273 + /* Set WakeOnInterrupt bit; clear ForceWake bit */
23274 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
23275 AR_RTC_FORCE_WAKE_ON_INT);
23276 } else {
23277 + /*
23278 + * Clear the RTC force wake bit to allow the
23279 + * mac to go to sleep.
23280 + */
23281 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
23282 AR_RTC_FORCE_WAKE_EN);
23283 }
23284 @@ -2422,7 +1689,8 @@ static bool ath9k_hw_set_power_awake(str
23285 ATH9K_RESET_POWER_ON) != true) {
23286 return false;
23287 }
23288 - ath9k_hw_init_pll(ah, NULL);
23289 + if (!AR_SREV_9300_20_OR_LATER(ah))
23290 + ath9k_hw_init_pll(ah, NULL);
23291 }
23292 if (AR_SREV_9100(ah))
23293 REG_SET_BIT(ah, AR_RTC_RESET,
23294 @@ -2492,420 +1760,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah
23295 }
23296 EXPORT_SYMBOL(ath9k_hw_setpower);
23297
23298 -/*
23299 - * Helper for ASPM support.
23300 - *
23301 - * Disable PLL when in L0s as well as receiver clock when in L1.
23302 - * This power saving option must be enabled through the SerDes.
23303 - *
23304 - * Programming the SerDes must go through the same 288 bit serial shift
23305 - * register as the other analog registers. Hence the 9 writes.
23306 - */
23307 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
23308 -{
23309 - u8 i;
23310 - u32 val;
23311 -
23312 - if (ah->is_pciexpress != true)
23313 - return;
23314 -
23315 - /* Do not touch SerDes registers */
23316 - if (ah->config.pcie_powersave_enable == 2)
23317 - return;
23318 -
23319 - /* Nothing to do on restore for 11N */
23320 - if (!restore) {
23321 - if (AR_SREV_9280_20_OR_LATER(ah)) {
23322 - /*
23323 - * AR9280 2.0 or later chips use SerDes values from the
23324 - * initvals.h initialized depending on chipset during
23325 - * ath9k_hw_init()
23326 - */
23327 - for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
23328 - REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
23329 - INI_RA(&ah->iniPcieSerdes, i, 1));
23330 - }
23331 - } else if (AR_SREV_9280(ah) &&
23332 - (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
23333 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
23334 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
23335 -
23336 - /* RX shut off when elecidle is asserted */
23337 - REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
23338 - REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
23339 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
23340 -
23341 - /* Shut off CLKREQ active in L1 */
23342 - if (ah->config.pcie_clock_req)
23343 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
23344 - else
23345 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
23346 -
23347 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
23348 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
23349 - REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
23350 -
23351 - /* Load the new settings */
23352 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
23353 -
23354 - } else {
23355 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
23356 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
23357 -
23358 - /* RX shut off when elecidle is asserted */
23359 - REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
23360 - REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
23361 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
23362 -
23363 - /*
23364 - * Ignore ah->ah_config.pcie_clock_req setting for
23365 - * pre-AR9280 11n
23366 - */
23367 - REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
23368 -
23369 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
23370 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
23371 - REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
23372 -
23373 - /* Load the new settings */
23374 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
23375 - }
23376 -
23377 - udelay(1000);
23378 -
23379 - /* set bit 19 to allow forcing of pcie core into L1 state */
23380 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
23381 -
23382 - /* Several PCIe massages to ensure proper behaviour */
23383 - if (ah->config.pcie_waen) {
23384 - val = ah->config.pcie_waen;
23385 - if (!power_off)
23386 - val &= (~AR_WA_D3_L1_DISABLE);
23387 - } else {
23388 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
23389 - AR_SREV_9287(ah)) {
23390 - val = AR9285_WA_DEFAULT;
23391 - if (!power_off)
23392 - val &= (~AR_WA_D3_L1_DISABLE);
23393 - } else if (AR_SREV_9280(ah)) {
23394 - /*
23395 - * On AR9280 chips bit 22 of 0x4004 needs to be
23396 - * set otherwise card may disappear.
23397 - */
23398 - val = AR9280_WA_DEFAULT;
23399 - if (!power_off)
23400 - val &= (~AR_WA_D3_L1_DISABLE);
23401 - } else
23402 - val = AR_WA_DEFAULT;
23403 - }
23404 -
23405 - REG_WRITE(ah, AR_WA, val);
23406 - }
23407 -
23408 - if (power_off) {
23409 - /*
23410 - * Set PCIe workaround bits
23411 - * bit 14 in WA register (disable L1) should only
23412 - * be set when device enters D3 and be cleared
23413 - * when device comes back to D0.
23414 - */
23415 - if (ah->config.pcie_waen) {
23416 - if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
23417 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
23418 - } else {
23419 - if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
23420 - AR_SREV_9287(ah)) &&
23421 - (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
23422 - (AR_SREV_9280(ah) &&
23423 - (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
23424 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
23425 - }
23426 - }
23427 - }
23428 -}
23429 -EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
23430 -
23431 -/**********************/
23432 -/* Interrupt Handling */
23433 -/**********************/
23434 -
23435 -bool ath9k_hw_intrpend(struct ath_hw *ah)
23436 -{
23437 - u32 host_isr;
23438 -
23439 - if (AR_SREV_9100(ah))
23440 - return true;
23441 -
23442 - host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
23443 - if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
23444 - return true;
23445 -
23446 - host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
23447 - if ((host_isr & AR_INTR_SYNC_DEFAULT)
23448 - && (host_isr != AR_INTR_SPURIOUS))
23449 - return true;
23450 -
23451 - return false;
23452 -}
23453 -EXPORT_SYMBOL(ath9k_hw_intrpend);
23454 -
23455 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
23456 -{
23457 - u32 isr = 0;
23458 - u32 mask2 = 0;
23459 - struct ath9k_hw_capabilities *pCap = &ah->caps;
23460 - u32 sync_cause = 0;
23461 - bool fatal_int = false;
23462 - struct ath_common *common = ath9k_hw_common(ah);
23463 -
23464 - if (!AR_SREV_9100(ah)) {
23465 - if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
23466 - if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
23467 - == AR_RTC_STATUS_ON) {
23468 - isr = REG_READ(ah, AR_ISR);
23469 - }
23470 - }
23471 -
23472 - sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
23473 - AR_INTR_SYNC_DEFAULT;
23474 -
23475 - *masked = 0;
23476 -
23477 - if (!isr && !sync_cause)
23478 - return false;
23479 - } else {
23480 - *masked = 0;
23481 - isr = REG_READ(ah, AR_ISR);
23482 - }
23483 -
23484 - if (isr) {
23485 - if (isr & AR_ISR_BCNMISC) {
23486 - u32 isr2;
23487 - isr2 = REG_READ(ah, AR_ISR_S2);
23488 - if (isr2 & AR_ISR_S2_TIM)
23489 - mask2 |= ATH9K_INT_TIM;
23490 - if (isr2 & AR_ISR_S2_DTIM)
23491 - mask2 |= ATH9K_INT_DTIM;
23492 - if (isr2 & AR_ISR_S2_DTIMSYNC)
23493 - mask2 |= ATH9K_INT_DTIMSYNC;
23494 - if (isr2 & (AR_ISR_S2_CABEND))
23495 - mask2 |= ATH9K_INT_CABEND;
23496 - if (isr2 & AR_ISR_S2_GTT)
23497 - mask2 |= ATH9K_INT_GTT;
23498 - if (isr2 & AR_ISR_S2_CST)
23499 - mask2 |= ATH9K_INT_CST;
23500 - if (isr2 & AR_ISR_S2_TSFOOR)
23501 - mask2 |= ATH9K_INT_TSFOOR;
23502 - }
23503 -
23504 - isr = REG_READ(ah, AR_ISR_RAC);
23505 - if (isr == 0xffffffff) {
23506 - *masked = 0;
23507 - return false;
23508 - }
23509 -
23510 - *masked = isr & ATH9K_INT_COMMON;
23511 -
23512 - if (ah->config.rx_intr_mitigation) {
23513 - if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
23514 - *masked |= ATH9K_INT_RX;
23515 - }
23516 -
23517 - if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
23518 - *masked |= ATH9K_INT_RX;
23519 - if (isr &
23520 - (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
23521 - AR_ISR_TXEOL)) {
23522 - u32 s0_s, s1_s;
23523 -
23524 - *masked |= ATH9K_INT_TX;
23525 -
23526 - s0_s = REG_READ(ah, AR_ISR_S0_S);
23527 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
23528 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
23529 -
23530 - s1_s = REG_READ(ah, AR_ISR_S1_S);
23531 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
23532 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
23533 - }
23534 -
23535 - if (isr & AR_ISR_RXORN) {
23536 - ath_print(common, ATH_DBG_INTERRUPT,
23537 - "receive FIFO overrun interrupt\n");
23538 - }
23539 -
23540 - if (!AR_SREV_9100(ah)) {
23541 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23542 - u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
23543 - if (isr5 & AR_ISR_S5_TIM_TIMER)
23544 - *masked |= ATH9K_INT_TIM_TIMER;
23545 - }
23546 - }
23547 -
23548 - *masked |= mask2;
23549 - }
23550 -
23551 - if (AR_SREV_9100(ah))
23552 - return true;
23553 -
23554 - if (isr & AR_ISR_GENTMR) {
23555 - u32 s5_s;
23556 -
23557 - s5_s = REG_READ(ah, AR_ISR_S5_S);
23558 - if (isr & AR_ISR_GENTMR) {
23559 - ah->intr_gen_timer_trigger =
23560 - MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
23561 -
23562 - ah->intr_gen_timer_thresh =
23563 - MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
23564 -
23565 - if (ah->intr_gen_timer_trigger)
23566 - *masked |= ATH9K_INT_GENTIMER;
23567 -
23568 - }
23569 - }
23570 -
23571 - if (sync_cause) {
23572 - fatal_int =
23573 - (sync_cause &
23574 - (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
23575 - ? true : false;
23576 -
23577 - if (fatal_int) {
23578 - if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
23579 - ath_print(common, ATH_DBG_ANY,
23580 - "received PCI FATAL interrupt\n");
23581 - }
23582 - if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
23583 - ath_print(common, ATH_DBG_ANY,
23584 - "received PCI PERR interrupt\n");
23585 - }
23586 - *masked |= ATH9K_INT_FATAL;
23587 - }
23588 - if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
23589 - ath_print(common, ATH_DBG_INTERRUPT,
23590 - "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
23591 - REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
23592 - REG_WRITE(ah, AR_RC, 0);
23593 - *masked |= ATH9K_INT_FATAL;
23594 - }
23595 - if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
23596 - ath_print(common, ATH_DBG_INTERRUPT,
23597 - "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
23598 - }
23599 -
23600 - REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
23601 - (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
23602 - }
23603 -
23604 - return true;
23605 -}
23606 -EXPORT_SYMBOL(ath9k_hw_getisr);
23607 -
23608 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
23609 -{
23610 - enum ath9k_int omask = ah->imask;
23611 - u32 mask, mask2;
23612 - struct ath9k_hw_capabilities *pCap = &ah->caps;
23613 - struct ath_common *common = ath9k_hw_common(ah);
23614 -
23615 - ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
23616 -
23617 - if (omask & ATH9K_INT_GLOBAL) {
23618 - ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
23619 - REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
23620 - (void) REG_READ(ah, AR_IER);
23621 - if (!AR_SREV_9100(ah)) {
23622 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
23623 - (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
23624 -
23625 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
23626 - (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
23627 - }
23628 - }
23629 -
23630 - mask = ints & ATH9K_INT_COMMON;
23631 - mask2 = 0;
23632 -
23633 - if (ints & ATH9K_INT_TX) {
23634 - if (ah->txok_interrupt_mask)
23635 - mask |= AR_IMR_TXOK;
23636 - if (ah->txdesc_interrupt_mask)
23637 - mask |= AR_IMR_TXDESC;
23638 - if (ah->txerr_interrupt_mask)
23639 - mask |= AR_IMR_TXERR;
23640 - if (ah->txeol_interrupt_mask)
23641 - mask |= AR_IMR_TXEOL;
23642 - }
23643 - if (ints & ATH9K_INT_RX) {
23644 - mask |= AR_IMR_RXERR;
23645 - if (ah->config.rx_intr_mitigation)
23646 - mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
23647 - else
23648 - mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
23649 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
23650 - mask |= AR_IMR_GENTMR;
23651 - }
23652 -
23653 - if (ints & (ATH9K_INT_BMISC)) {
23654 - mask |= AR_IMR_BCNMISC;
23655 - if (ints & ATH9K_INT_TIM)
23656 - mask2 |= AR_IMR_S2_TIM;
23657 - if (ints & ATH9K_INT_DTIM)
23658 - mask2 |= AR_IMR_S2_DTIM;
23659 - if (ints & ATH9K_INT_DTIMSYNC)
23660 - mask2 |= AR_IMR_S2_DTIMSYNC;
23661 - if (ints & ATH9K_INT_CABEND)
23662 - mask2 |= AR_IMR_S2_CABEND;
23663 - if (ints & ATH9K_INT_TSFOOR)
23664 - mask2 |= AR_IMR_S2_TSFOOR;
23665 - }
23666 -
23667 - if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
23668 - mask |= AR_IMR_BCNMISC;
23669 - if (ints & ATH9K_INT_GTT)
23670 - mask2 |= AR_IMR_S2_GTT;
23671 - if (ints & ATH9K_INT_CST)
23672 - mask2 |= AR_IMR_S2_CST;
23673 - }
23674 -
23675 - ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
23676 - REG_WRITE(ah, AR_IMR, mask);
23677 - ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
23678 - AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
23679 - AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
23680 - ah->imrs2_reg |= mask2;
23681 - REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
23682 -
23683 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
23684 - if (ints & ATH9K_INT_TIM_TIMER)
23685 - REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
23686 - else
23687 - REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
23688 - }
23689 -
23690 - if (ints & ATH9K_INT_GLOBAL) {
23691 - ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
23692 - REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
23693 - if (!AR_SREV_9100(ah)) {
23694 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
23695 - AR_INTR_MAC_IRQ);
23696 - REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
23697 -
23698 -
23699 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
23700 - AR_INTR_SYNC_DEFAULT);
23701 - REG_WRITE(ah, AR_INTR_SYNC_MASK,
23702 - AR_INTR_SYNC_DEFAULT);
23703 - }
23704 - ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
23705 - REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
23706 - }
23707 -
23708 - return omask;
23709 -}
23710 -EXPORT_SYMBOL(ath9k_hw_set_interrupts);
23711 -
23712 /*******************/
23713 /* Beacon Handling */
23714 /*******************/
23715 @@ -3241,6 +2095,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw
23716 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
23717 }
23718
23719 + if (AR_SREV_9300_20_OR_LATER(ah)) {
23720 + pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
23721 + pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
23722 + pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
23723 + pCap->rx_status_len = sizeof(struct ar9003_rxs);
23724 + pCap->tx_desc_len = sizeof(struct ar9003_txc);
23725 + pCap->txs_len = sizeof(struct ar9003_txs);
23726 + } else {
23727 + pCap->tx_desc_len = sizeof(struct ath_desc);
23728 + }
23729 +
23730 + if (AR_SREV_9300_20_OR_LATER(ah))
23731 + pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
23732 +
23733 return 0;
23734 }
23735
23736 @@ -3273,10 +2141,6 @@ bool ath9k_hw_getcapability(struct ath_h
23737 case ATH9K_CAP_TKIP_SPLIT:
23738 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
23739 false : true;
23740 - case ATH9K_CAP_DIVERSITY:
23741 - return (REG_READ(ah, AR_PHY_CCK_DETECT) &
23742 - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
23743 - true : false;
23744 case ATH9K_CAP_MCAST_KEYSRCH:
23745 switch (capability) {
23746 case 0:
23747 @@ -3319,8 +2183,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
23748 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
23749 u32 capability, u32 setting, int *status)
23750 {
23751 - u32 v;
23752 -
23753 switch (type) {
23754 case ATH9K_CAP_TKIP_MIC:
23755 if (setting)
23756 @@ -3330,14 +2192,6 @@ bool ath9k_hw_setcapability(struct ath_h
23757 ah->sta_id1_defaults &=
23758 ~AR_STA_ID1_CRPT_MIC_ENABLE;
23759 return true;
23760 - case ATH9K_CAP_DIVERSITY:
23761 - v = REG_READ(ah, AR_PHY_CCK_DETECT);
23762 - if (setting)
23763 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
23764 - else
23765 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
23766 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
23767 - return true;
23768 case ATH9K_CAP_MCAST_KEYSRCH:
23769 if (setting)
23770 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
23771 @@ -3405,7 +2259,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah,
23772 if (gpio >= ah->caps.num_gpio_pins)
23773 return 0xffffffff;
23774
23775 - if (AR_SREV_9271(ah))
23776 + if (AR_SREV_9300_20_OR_LATER(ah))
23777 + return MS_REG_READ(AR9300, gpio) != 0;
23778 + else if (AR_SREV_9271(ah))
23779 return MS_REG_READ(AR9271, gpio) != 0;
23780 else if (AR_SREV_9287_10_OR_LATER(ah))
23781 return MS_REG_READ(AR9287, gpio) != 0;
23782 @@ -3847,6 +2703,7 @@ static struct {
23783 { AR_SREV_VERSION_9285, "9285" },
23784 { AR_SREV_VERSION_9287, "9287" },
23785 { AR_SREV_VERSION_9271, "9271" },
23786 + { AR_SREV_VERSION_9300, "9300" },
23787 };
23788
23789 /* For devices with external radios */
23790 --- a/drivers/net/wireless/ath/ath9k/hw.h
23791 +++ b/drivers/net/wireless/ath/ath9k/hw.h
23792 @@ -1,5 +1,5 @@
23793 /*
23794 - * Copyright (c) 2008-2009 Atheros Communications Inc.
23795 + * Copyright (c) 2008-2010 Atheros Communications Inc.
23796 *
23797 * Permission to use, copy, modify, and/or distribute this software for any
23798 * purpose with or without fee is hereby granted, provided that the above
23799 @@ -41,6 +41,9 @@
23800 #define AR9280_DEVID_PCIE 0x002a
23801 #define AR9285_DEVID_PCIE 0x002b
23802 #define AR2427_DEVID_PCIE 0x002c
23803 +#define AR9287_DEVID_PCI 0x002d
23804 +#define AR9287_DEVID_PCIE 0x002e
23805 +#define AR9300_DEVID_PCIE 0x0030
23806
23807 #define AR5416_AR9100_DEVID 0x000b
23808
23809 @@ -48,9 +51,6 @@
23810 #define AR_SUBVENDOR_ID_NEW_A 0x7065
23811 #define AR5416_MAGIC 0x19641014
23812
23813 -#define AR5416_DEVID_AR9287_PCI 0x002D
23814 -#define AR5416_DEVID_AR9287_PCIE 0x002E
23815 -
23816 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
23817 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
23818 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
23819 @@ -75,6 +75,8 @@
23820 #define REG_RMW_FIELD(_a, _r, _f, _v) \
23821 REG_WRITE(_a, _r, \
23822 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
23823 +#define REG_READ_FIELD(_a, _r, _f) \
23824 + (((REG_READ(_a, _r) & _f) >> _f##_S))
23825 #define REG_SET_BIT(_a, _r, _f) \
23826 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
23827 #define REG_CLR_BIT(_a, _r, _f) \
23828 @@ -135,6 +137,16 @@
23829
23830 #define TU_TO_USEC(_tu) ((_tu) << 10)
23831
23832 +#define ATH9K_HW_RX_HP_QDEPTH 16
23833 +#define ATH9K_HW_RX_LP_QDEPTH 128
23834 +
23835 +enum ath_ini_subsys {
23836 + ATH_INI_PRE = 0,
23837 + ATH_INI_CORE,
23838 + ATH_INI_POST,
23839 + ATH_INI_NUM_SPLIT,
23840 +};
23841 +
23842 enum wireless_mode {
23843 ATH9K_MODE_11A = 0,
23844 ATH9K_MODE_11G,
23845 @@ -165,13 +177,15 @@ enum ath9k_hw_caps {
23846 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
23847 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
23848 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
23849 + ATH9K_HW_CAP_EDMA = BIT(17),
23850 + ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
23851 + ATH9K_HW_CAP_LDPC = BIT(19),
23852 };
23853
23854 enum ath9k_capability_type {
23855 ATH9K_CAP_CIPHER = 0,
23856 ATH9K_CAP_TKIP_MIC,
23857 ATH9K_CAP_TKIP_SPLIT,
23858 - ATH9K_CAP_DIVERSITY,
23859 ATH9K_CAP_TXPOW,
23860 ATH9K_CAP_MCAST_KEYSRCH,
23861 ATH9K_CAP_DS
23862 @@ -192,6 +206,11 @@ struct ath9k_hw_capabilities {
23863 u8 num_gpio_pins;
23864 u8 num_antcfg_2ghz;
23865 u8 num_antcfg_5ghz;
23866 + u8 rx_hp_qdepth;
23867 + u8 rx_lp_qdepth;
23868 + u8 rx_status_len;
23869 + u8 tx_desc_len;
23870 + u8 txs_len;
23871 };
23872
23873 struct ath9k_ops_config {
23874 @@ -212,6 +231,7 @@ struct ath9k_ops_config {
23875 u32 enable_ani;
23876 int serialize_regmode;
23877 bool rx_intr_mitigation;
23878 + bool tx_intr_mitigation;
23879 #define SPUR_DISABLE 0
23880 #define SPUR_ENABLE_IOCTL 1
23881 #define SPUR_ENABLE_EEPROM 2
23882 @@ -231,6 +251,8 @@ struct ath9k_ops_config {
23883 enum ath9k_int {
23884 ATH9K_INT_RX = 0x00000001,
23885 ATH9K_INT_RXDESC = 0x00000002,
23886 + ATH9K_INT_RXHP = 0x00000001,
23887 + ATH9K_INT_RXLP = 0x00000002,
23888 ATH9K_INT_RXNOFRM = 0x00000008,
23889 ATH9K_INT_RXEOL = 0x00000010,
23890 ATH9K_INT_RXORN = 0x00000020,
23891 @@ -363,6 +385,12 @@ enum ser_reg_mode {
23892 SER_REG_MODE_AUTO = 2,
23893 };
23894
23895 +enum ath9k_rx_qtype {
23896 + ATH9K_RX_QUEUE_HP,
23897 + ATH9K_RX_QUEUE_LP,
23898 + ATH9K_RX_QUEUE_MAX,
23899 +};
23900 +
23901 struct ath9k_beacon_state {
23902 u32 bs_nexttbtt;
23903 u32 bs_nextdtim;
23904 @@ -440,6 +468,124 @@ struct ath_gen_timer_table {
23905 } timer_mask;
23906 };
23907
23908 +/**
23909 + * struct ath_hw_private_ops - callbacks used internally by hardware code
23910 + *
23911 + * This structure contains private callbacks designed to only be used internally
23912 + * by the hardware core.
23913 + *
23914 + * @init_cal_settings: setup types of calibrations supported
23915 + * @init_cal: starts actual calibration
23916 + *
23917 + * @init_mode_regs: Initializes mode registers
23918 + * @init_mode_gain_regs: Initialize TX/RX gain registers
23919 + * @macversion_supported: If this specific mac revision is supported
23920 + *
23921 + * @rf_set_freq: change frequency
23922 + * @spur_mitigate_freq: spur mitigation
23923 + * @rf_alloc_ext_banks:
23924 + * @rf_free_ext_banks:
23925 + * @set_rf_regs:
23926 + * @compute_pll_control: compute the PLL control value to use for
23927 + * AR_RTC_PLL_CONTROL for a given channel
23928 + * @setup_calibration: set up calibration
23929 + * @iscal_supported: used to query if a type of calibration is supported
23930 + * @loadnf: load noise floor read from each chain on the CCA registers
23931 + */
23932 +struct ath_hw_private_ops {
23933 + /* Calibration ops */
23934 + void (*init_cal_settings)(struct ath_hw *ah);
23935 + bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
23936 +
23937 + void (*init_mode_regs)(struct ath_hw *ah);
23938 + void (*init_mode_gain_regs)(struct ath_hw *ah);
23939 + bool (*macversion_supported)(u32 macversion);
23940 + void (*setup_calibration)(struct ath_hw *ah,
23941 + struct ath9k_cal_list *currCal);
23942 + bool (*iscal_supported)(struct ath_hw *ah,
23943 + enum ath9k_cal_types calType);
23944 +
23945 + /* PHY ops */
23946 + int (*rf_set_freq)(struct ath_hw *ah,
23947 + struct ath9k_channel *chan);
23948 + void (*spur_mitigate_freq)(struct ath_hw *ah,
23949 + struct ath9k_channel *chan);
23950 + int (*rf_alloc_ext_banks)(struct ath_hw *ah);
23951 + void (*rf_free_ext_banks)(struct ath_hw *ah);
23952 + bool (*set_rf_regs)(struct ath_hw *ah,
23953 + struct ath9k_channel *chan,
23954 + u16 modesIndex);
23955 + void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
23956 + void (*init_bb)(struct ath_hw *ah,
23957 + struct ath9k_channel *chan);
23958 + int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
23959 + void (*olc_init)(struct ath_hw *ah);
23960 + void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
23961 + void (*mark_phy_inactive)(struct ath_hw *ah);
23962 + void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
23963 + bool (*rfbus_req)(struct ath_hw *ah);
23964 + void (*rfbus_done)(struct ath_hw *ah);
23965 + void (*enable_rfkill)(struct ath_hw *ah);
23966 + void (*restore_chainmask)(struct ath_hw *ah);
23967 + void (*set_diversity)(struct ath_hw *ah, bool value);
23968 + u32 (*compute_pll_control)(struct ath_hw *ah,
23969 + struct ath9k_channel *chan);
23970 + bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
23971 + int param);
23972 + void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
23973 + void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
23974 +};
23975 +
23976 +/**
23977 + * struct ath_hw_ops - callbacks used by hardware code and driver code
23978 + *
23979 + * This structure contains callbacks designed to to be used internally by
23980 + * hardware code and also by the lower level driver.
23981 + *
23982 + * @config_pci_powersave:
23983 + * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
23984 + */
23985 +struct ath_hw_ops {
23986 + void (*config_pci_powersave)(struct ath_hw *ah,
23987 + int restore,
23988 + int power_off);
23989 + void (*rx_enable)(struct ath_hw *ah);
23990 + void (*set_desc_link)(void *ds, u32 link);
23991 + void (*get_desc_link)(void *ds, u32 **link);
23992 + bool (*calibrate)(struct ath_hw *ah,
23993 + struct ath9k_channel *chan,
23994 + u8 rxchainmask,
23995 + bool longcal);
23996 + bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
23997 + void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
23998 + bool is_firstseg, bool is_is_lastseg,
23999 + const void *ds0, dma_addr_t buf_addr,
24000 + unsigned int qcu);
24001 + int (*proc_txdesc)(struct ath_hw *ah, void *ds,
24002 + struct ath_tx_status *ts);
24003 + void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
24004 + u32 pktLen, enum ath9k_pkt_type type,
24005 + u32 txPower, u32 keyIx,
24006 + enum ath9k_key_type keyType,
24007 + u32 flags);
24008 + void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
24009 + void *lastds,
24010 + u32 durUpdateEn, u32 rtsctsRate,
24011 + u32 rtsctsDuration,
24012 + struct ath9k_11n_rate_series series[],
24013 + u32 nseries, u32 flags);
24014 + void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
24015 + u32 aggrLen);
24016 + void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
24017 + u32 numDelims);
24018 + void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
24019 + void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
24020 + void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
24021 + u32 burstDuration);
24022 + void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
24023 + u32 vmf);
24024 +};
24025 +
24026 struct ath_hw {
24027 struct ieee80211_hw *hw;
24028 struct ath_common common;
24029 @@ -453,14 +599,18 @@ struct ath_hw {
24030 struct ar5416_eeprom_def def;
24031 struct ar5416_eeprom_4k map4k;
24032 struct ar9287_eeprom map9287;
24033 + struct ar9300_eeprom ar9300_eep;
24034 } eeprom;
24035 const struct eeprom_ops *eep_ops;
24036 - enum ath9k_eep_map eep_map;
24037
24038 bool sw_mgmt_crypto;
24039 bool is_pciexpress;
24040 bool need_an_top2_fixup;
24041 u16 tx_trig_level;
24042 + s16 nf_2g_max;
24043 + s16 nf_2g_min;
24044 + s16 nf_5g_max;
24045 + s16 nf_5g_min;
24046 u16 rfsilent;
24047 u32 rfkill_gpio;
24048 u32 rfkill_polarity;
24049 @@ -493,6 +643,7 @@ struct ath_hw {
24050 struct ath9k_cal_list adcgain_caldata;
24051 struct ath9k_cal_list adcdc_calinitdata;
24052 struct ath9k_cal_list adcdc_caldata;
24053 + struct ath9k_cal_list tempCompCalData;
24054 struct ath9k_cal_list *cal_list;
24055 struct ath9k_cal_list *cal_list_last;
24056 struct ath9k_cal_list *cal_list_curr;
24057 @@ -533,12 +684,10 @@ struct ath_hw {
24058 DONT_USE_32KHZ,
24059 } enable_32kHz_clock;
24060
24061 - /* Callback for radio frequency change */
24062 - int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
24063 -
24064 - /* Callback for baseband spur frequency */
24065 - void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
24066 - struct ath9k_channel *chan);
24067 + /* Private to hardware code */
24068 + struct ath_hw_private_ops private_ops;
24069 + /* Accessed by the lower level driver */
24070 + struct ath_hw_ops ops;
24071
24072 /* Used to program the radio on non single-chip devices */
24073 u32 *analogBank0Data;
24074 @@ -592,6 +741,7 @@ struct ath_hw {
24075 struct ar5416IniArray iniBank7;
24076 struct ar5416IniArray iniAddac;
24077 struct ar5416IniArray iniPcieSerdes;
24078 + struct ar5416IniArray iniPcieSerdesLowPower;
24079 struct ar5416IniArray iniModesAdditional;
24080 struct ar5416IniArray iniModesRxGain;
24081 struct ar5416IniArray iniModesTxGain;
24082 @@ -604,9 +754,21 @@ struct ath_hw {
24083 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
24084 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
24085
24086 + struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
24087 + struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
24088 + struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
24089 + struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
24090 +
24091 u32 intr_gen_timer_trigger;
24092 u32 intr_gen_timer_thresh;
24093 struct ath_gen_timer_table hw_gen_timers;
24094 +
24095 + struct ar9003_txs *ts_ring;
24096 + void *ts_start;
24097 + u32 ts_paddr_start;
24098 + u32 ts_paddr_end;
24099 + u16 ts_tail;
24100 + u8 ts_size;
24101 };
24102
24103 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
24104 @@ -619,6 +781,16 @@ static inline struct ath_regulatory *ath
24105 return &(ath9k_hw_common(ah)->regulatory);
24106 }
24107
24108 +static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
24109 +{
24110 + return &ah->private_ops;
24111 +}
24112 +
24113 +static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
24114 +{
24115 + return &ah->ops;
24116 +}
24117 +
24118 /* Initialization, Detach, Reset */
24119 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
24120 void ath9k_hw_deinit(struct ath_hw *ah);
24121 @@ -630,6 +802,7 @@ bool ath9k_hw_getcapability(struct ath_h
24122 u32 capability, u32 *result);
24123 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
24124 u32 capability, u32 setting, int *status);
24125 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
24126
24127 /* Key Cache Management */
24128 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
24129 @@ -681,13 +854,6 @@ void ath9k_hw_set_sta_beacon_timers(stru
24130
24131 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
24132
24133 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
24134 -
24135 -/* Interrupt Handling */
24136 -bool ath9k_hw_intrpend(struct ath_hw *ah);
24137 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
24138 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
24139 -
24140 /* Generic hw timer primitives */
24141 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
24142 void (*trigger)(void *),
24143 @@ -709,6 +875,36 @@ void ath9k_hw_name(struct ath_hw *ah, ch
24144 /* HTC */
24145 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
24146
24147 +/* PHY */
24148 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
24149 + u32 *coef_mantissa, u32 *coef_exponent);
24150 +
24151 +/*
24152 + * Code Specific to AR5008, AR9001 or AR9002,
24153 + * we stuff these here to avoid callbacks for AR9003.
24154 + */
24155 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
24156 +int ar9002_hw_rf_claim(struct ath_hw *ah);
24157 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
24158 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
24159 +
24160 +/*
24161 + * Code specifric to AR9003, we stuff these here to avoid callbacks
24162 + * for older families
24163 + */
24164 +void ar9003_hw_set_nf_limits(struct ath_hw *ah);
24165 +
24166 +/* Hardware family op attach helpers */
24167 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
24168 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
24169 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
24170 +
24171 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
24172 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
24173 +
24174 +void ar9002_hw_attach_ops(struct ath_hw *ah);
24175 +void ar9003_hw_attach_ops(struct ath_hw *ah);
24176 +
24177 #define ATH_PCIE_CAP_LINK_CTRL 0x70
24178 #define ATH_PCIE_CAP_LINK_L0S 1
24179 #define ATH_PCIE_CAP_LINK_L1 2
24180 --- a/drivers/net/wireless/ath/ath9k/init.c
24181 +++ b/drivers/net/wireless/ath/ath9k/init.c
24182 @@ -191,6 +191,9 @@ static void setup_ht_cap(struct ath_soft
24183 IEEE80211_HT_CAP_SGI_40 |
24184 IEEE80211_HT_CAP_DSSSCCK40;
24185
24186 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
24187 + ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
24188 +
24189 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
24190 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
24191
24192 @@ -235,31 +238,37 @@ static int ath9k_reg_notifier(struct wip
24193 */
24194 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
24195 struct list_head *head, const char *name,
24196 - int nbuf, int ndesc)
24197 + int nbuf, int ndesc, bool is_tx)
24198 {
24199 #define DS2PHYS(_dd, _ds) \
24200 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
24201 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
24202 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
24203 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
24204 - struct ath_desc *ds;
24205 + u8 *ds;
24206 struct ath_buf *bf;
24207 - int i, bsize, error;
24208 + int i, bsize, error, desc_len;
24209
24210 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
24211 name, nbuf, ndesc);
24212
24213 INIT_LIST_HEAD(head);
24214 +
24215 + if (is_tx)
24216 + desc_len = sc->sc_ah->caps.tx_desc_len;
24217 + else
24218 + desc_len = sizeof(struct ath_desc);
24219 +
24220 /* ath_desc must be a multiple of DWORDs */
24221 - if ((sizeof(struct ath_desc) % 4) != 0) {
24222 + if ((desc_len % 4) != 0) {
24223 ath_print(common, ATH_DBG_FATAL,
24224 "ath_desc not DWORD aligned\n");
24225 - BUG_ON((sizeof(struct ath_desc) % 4) != 0);
24226 + BUG_ON((desc_len % 4) != 0);
24227 error = -ENOMEM;
24228 goto fail;
24229 }
24230
24231 - dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
24232 + dd->dd_desc_len = desc_len * nbuf * ndesc;
24233
24234 /*
24235 * Need additional DMA memory because we can't use
24236 @@ -272,7 +281,7 @@ int ath_descdma_setup(struct ath_softc *
24237 u32 dma_len;
24238
24239 while (ndesc_skipped) {
24240 - dma_len = ndesc_skipped * sizeof(struct ath_desc);
24241 + dma_len = ndesc_skipped * desc_len;
24242 dd->dd_desc_len += dma_len;
24243
24244 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
24245 @@ -286,7 +295,7 @@ int ath_descdma_setup(struct ath_softc *
24246 error = -ENOMEM;
24247 goto fail;
24248 }
24249 - ds = dd->dd_desc;
24250 + ds = (u8 *) dd->dd_desc;
24251 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
24252 name, ds, (u32) dd->dd_desc_len,
24253 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
24254 @@ -300,7 +309,7 @@ int ath_descdma_setup(struct ath_softc *
24255 }
24256 dd->dd_bufptr = bf;
24257
24258 - for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
24259 + for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
24260 bf->bf_desc = ds;
24261 bf->bf_daddr = DS2PHYS(dd, ds);
24262
24263 @@ -316,7 +325,7 @@ int ath_descdma_setup(struct ath_softc *
24264 ((caddr_t) dd->dd_desc +
24265 dd->dd_desc_len));
24266
24267 - ds += ndesc;
24268 + ds += (desc_len * ndesc);
24269 bf->bf_desc = ds;
24270 bf->bf_daddr = DS2PHYS(dd, ds);
24271 }
24272 @@ -514,7 +523,7 @@ static void ath9k_init_misc(struct ath_s
24273 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
24274 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
24275
24276 - ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
24277 + ath9k_hw_set_diversity(sc->sc_ah, true);
24278 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
24279
24280 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
24281 @@ -568,13 +577,10 @@ static int ath9k_init_softc(u16 devid, s
24282 ath_read_cachesize(common, &csz);
24283 common->cachelsz = csz << 2; /* convert to bytes */
24284
24285 + /* Initializes the hardware for all supported chipsets */
24286 ret = ath9k_hw_init(ah);
24287 - if (ret) {
24288 - ath_print(common, ATH_DBG_FATAL,
24289 - "Unable to initialize hardware; "
24290 - "initialization status: %d\n", ret);
24291 + if (ret)
24292 goto err_hw;
24293 - }
24294
24295 ret = ath9k_init_debug(ah);
24296 if (ret) {
24297 --- a/drivers/net/wireless/ath/ath9k/initvals.h
24298 +++ /dev/null
24299 @@ -1,7200 +0,0 @@
24300 -/*
24301 - * Copyright (c) 2008-2009 Atheros Communications Inc.
24302 - *
24303 - * Permission to use, copy, modify, and/or distribute this software for any
24304 - * purpose with or without fee is hereby granted, provided that the above
24305 - * copyright notice and this permission notice appear in all copies.
24306 - *
24307 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
24308 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
24309 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
24310 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24311 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
24312 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
24313 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24314 - */
24315 -
24316 -static const u32 ar5416Modes[][6] = {
24317 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
24318 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
24319 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24320 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
24321 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
24322 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24323 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
24324 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
24325 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
24326 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
24327 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24328 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
24329 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24330 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
24331 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
24332 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24333 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24334 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24335 - { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
24336 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
24337 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
24338 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
24339 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
24340 - { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
24341 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
24342 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
24343 - { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
24344 - { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
24345 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
24346 - { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24347 - { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24348 - { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
24349 - { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
24350 - { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
24351 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
24352 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
24353 - { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
24354 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
24355 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
24356 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24357 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24358 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
24359 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
24360 - { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24361 - { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24362 - { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
24363 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
24364 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
24365 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
24366 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
24367 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
24368 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
24369 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
24370 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
24371 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
24372 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
24373 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
24374 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
24375 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
24376 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
24377 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24378 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24379 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
24380 -};
24381 -
24382 -static const u32 ar5416Common[][2] = {
24383 - { 0x0000000c, 0x00000000 },
24384 - { 0x00000030, 0x00020015 },
24385 - { 0x00000034, 0x00000005 },
24386 - { 0x00000040, 0x00000000 },
24387 - { 0x00000044, 0x00000008 },
24388 - { 0x00000048, 0x00000008 },
24389 - { 0x0000004c, 0x00000010 },
24390 - { 0x00000050, 0x00000000 },
24391 - { 0x00000054, 0x0000001f },
24392 - { 0x00000800, 0x00000000 },
24393 - { 0x00000804, 0x00000000 },
24394 - { 0x00000808, 0x00000000 },
24395 - { 0x0000080c, 0x00000000 },
24396 - { 0x00000810, 0x00000000 },
24397 - { 0x00000814, 0x00000000 },
24398 - { 0x00000818, 0x00000000 },
24399 - { 0x0000081c, 0x00000000 },
24400 - { 0x00000820, 0x00000000 },
24401 - { 0x00000824, 0x00000000 },
24402 - { 0x00001040, 0x002ffc0f },
24403 - { 0x00001044, 0x002ffc0f },
24404 - { 0x00001048, 0x002ffc0f },
24405 - { 0x0000104c, 0x002ffc0f },
24406 - { 0x00001050, 0x002ffc0f },
24407 - { 0x00001054, 0x002ffc0f },
24408 - { 0x00001058, 0x002ffc0f },
24409 - { 0x0000105c, 0x002ffc0f },
24410 - { 0x00001060, 0x002ffc0f },
24411 - { 0x00001064, 0x002ffc0f },
24412 - { 0x00001230, 0x00000000 },
24413 - { 0x00001270, 0x00000000 },
24414 - { 0x00001038, 0x00000000 },
24415 - { 0x00001078, 0x00000000 },
24416 - { 0x000010b8, 0x00000000 },
24417 - { 0x000010f8, 0x00000000 },
24418 - { 0x00001138, 0x00000000 },
24419 - { 0x00001178, 0x00000000 },
24420 - { 0x000011b8, 0x00000000 },
24421 - { 0x000011f8, 0x00000000 },
24422 - { 0x00001238, 0x00000000 },
24423 - { 0x00001278, 0x00000000 },
24424 - { 0x000012b8, 0x00000000 },
24425 - { 0x000012f8, 0x00000000 },
24426 - { 0x00001338, 0x00000000 },
24427 - { 0x00001378, 0x00000000 },
24428 - { 0x000013b8, 0x00000000 },
24429 - { 0x000013f8, 0x00000000 },
24430 - { 0x00001438, 0x00000000 },
24431 - { 0x00001478, 0x00000000 },
24432 - { 0x000014b8, 0x00000000 },
24433 - { 0x000014f8, 0x00000000 },
24434 - { 0x00001538, 0x00000000 },
24435 - { 0x00001578, 0x00000000 },
24436 - { 0x000015b8, 0x00000000 },
24437 - { 0x000015f8, 0x00000000 },
24438 - { 0x00001638, 0x00000000 },
24439 - { 0x00001678, 0x00000000 },
24440 - { 0x000016b8, 0x00000000 },
24441 - { 0x000016f8, 0x00000000 },
24442 - { 0x00001738, 0x00000000 },
24443 - { 0x00001778, 0x00000000 },
24444 - { 0x000017b8, 0x00000000 },
24445 - { 0x000017f8, 0x00000000 },
24446 - { 0x0000103c, 0x00000000 },
24447 - { 0x0000107c, 0x00000000 },
24448 - { 0x000010bc, 0x00000000 },
24449 - { 0x000010fc, 0x00000000 },
24450 - { 0x0000113c, 0x00000000 },
24451 - { 0x0000117c, 0x00000000 },
24452 - { 0x000011bc, 0x00000000 },
24453 - { 0x000011fc, 0x00000000 },
24454 - { 0x0000123c, 0x00000000 },
24455 - { 0x0000127c, 0x00000000 },
24456 - { 0x000012bc, 0x00000000 },
24457 - { 0x000012fc, 0x00000000 },
24458 - { 0x0000133c, 0x00000000 },
24459 - { 0x0000137c, 0x00000000 },
24460 - { 0x000013bc, 0x00000000 },
24461 - { 0x000013fc, 0x00000000 },
24462 - { 0x0000143c, 0x00000000 },
24463 - { 0x0000147c, 0x00000000 },
24464 - { 0x00004030, 0x00000002 },
24465 - { 0x0000403c, 0x00000002 },
24466 - { 0x00007010, 0x00000000 },
24467 - { 0x00007038, 0x000004c2 },
24468 - { 0x00008004, 0x00000000 },
24469 - { 0x00008008, 0x00000000 },
24470 - { 0x0000800c, 0x00000000 },
24471 - { 0x00008018, 0x00000700 },
24472 - { 0x00008020, 0x00000000 },
24473 - { 0x00008038, 0x00000000 },
24474 - { 0x0000803c, 0x00000000 },
24475 - { 0x00008048, 0x40000000 },
24476 - { 0x00008054, 0x00000000 },
24477 - { 0x00008058, 0x00000000 },
24478 - { 0x0000805c, 0x000fc78f },
24479 - { 0x00008060, 0x0000000f },
24480 - { 0x00008064, 0x00000000 },
24481 - { 0x000080c0, 0x2a82301a },
24482 - { 0x000080c4, 0x05dc01e0 },
24483 - { 0x000080c8, 0x1f402710 },
24484 - { 0x000080cc, 0x01f40000 },
24485 - { 0x000080d0, 0x00001e00 },
24486 - { 0x000080d4, 0x00000000 },
24487 - { 0x000080d8, 0x00400000 },
24488 - { 0x000080e0, 0xffffffff },
24489 - { 0x000080e4, 0x0000ffff },
24490 - { 0x000080e8, 0x003f3f3f },
24491 - { 0x000080ec, 0x00000000 },
24492 - { 0x000080f0, 0x00000000 },
24493 - { 0x000080f4, 0x00000000 },
24494 - { 0x000080f8, 0x00000000 },
24495 - { 0x000080fc, 0x00020000 },
24496 - { 0x00008100, 0x00020000 },
24497 - { 0x00008104, 0x00000001 },
24498 - { 0x00008108, 0x00000052 },
24499 - { 0x0000810c, 0x00000000 },
24500 - { 0x00008110, 0x00000168 },
24501 - { 0x00008118, 0x000100aa },
24502 - { 0x0000811c, 0x00003210 },
24503 - { 0x00008124, 0x00000000 },
24504 - { 0x00008128, 0x00000000 },
24505 - { 0x0000812c, 0x00000000 },
24506 - { 0x00008130, 0x00000000 },
24507 - { 0x00008134, 0x00000000 },
24508 - { 0x00008138, 0x00000000 },
24509 - { 0x0000813c, 0x00000000 },
24510 - { 0x00008144, 0xffffffff },
24511 - { 0x00008168, 0x00000000 },
24512 - { 0x0000816c, 0x00000000 },
24513 - { 0x00008170, 0x32143320 },
24514 - { 0x00008174, 0xfaa4fa50 },
24515 - { 0x00008178, 0x00000100 },
24516 - { 0x0000817c, 0x00000000 },
24517 - { 0x000081c4, 0x00000000 },
24518 - { 0x000081ec, 0x00000000 },
24519 - { 0x000081f0, 0x00000000 },
24520 - { 0x000081f4, 0x00000000 },
24521 - { 0x000081f8, 0x00000000 },
24522 - { 0x000081fc, 0x00000000 },
24523 - { 0x00008200, 0x00000000 },
24524 - { 0x00008204, 0x00000000 },
24525 - { 0x00008208, 0x00000000 },
24526 - { 0x0000820c, 0x00000000 },
24527 - { 0x00008210, 0x00000000 },
24528 - { 0x00008214, 0x00000000 },
24529 - { 0x00008218, 0x00000000 },
24530 - { 0x0000821c, 0x00000000 },
24531 - { 0x00008220, 0x00000000 },
24532 - { 0x00008224, 0x00000000 },
24533 - { 0x00008228, 0x00000000 },
24534 - { 0x0000822c, 0x00000000 },
24535 - { 0x00008230, 0x00000000 },
24536 - { 0x00008234, 0x00000000 },
24537 - { 0x00008238, 0x00000000 },
24538 - { 0x0000823c, 0x00000000 },
24539 - { 0x00008240, 0x00100000 },
24540 - { 0x00008244, 0x0010f400 },
24541 - { 0x00008248, 0x00000100 },
24542 - { 0x0000824c, 0x0001e800 },
24543 - { 0x00008250, 0x00000000 },
24544 - { 0x00008254, 0x00000000 },
24545 - { 0x00008258, 0x00000000 },
24546 - { 0x0000825c, 0x400000ff },
24547 - { 0x00008260, 0x00080922 },
24548 - { 0x00008264, 0xa8000010 },
24549 - { 0x00008270, 0x00000000 },
24550 - { 0x00008274, 0x40000000 },
24551 - { 0x00008278, 0x003e4180 },
24552 - { 0x0000827c, 0x00000000 },
24553 - { 0x00008284, 0x0000002c },
24554 - { 0x00008288, 0x0000002c },
24555 - { 0x0000828c, 0x00000000 },
24556 - { 0x00008294, 0x00000000 },
24557 - { 0x00008298, 0x00000000 },
24558 - { 0x00008300, 0x00000000 },
24559 - { 0x00008304, 0x00000000 },
24560 - { 0x00008308, 0x00000000 },
24561 - { 0x0000830c, 0x00000000 },
24562 - { 0x00008310, 0x00000000 },
24563 - { 0x00008314, 0x00000000 },
24564 - { 0x00008318, 0x00000000 },
24565 - { 0x00008328, 0x00000000 },
24566 - { 0x0000832c, 0x00000007 },
24567 - { 0x00008330, 0x00000302 },
24568 - { 0x00008334, 0x00000e00 },
24569 - { 0x00008338, 0x00070000 },
24570 - { 0x0000833c, 0x00000000 },
24571 - { 0x00008340, 0x000107ff },
24572 - { 0x00009808, 0x00000000 },
24573 - { 0x0000980c, 0xad848e19 },
24574 - { 0x00009810, 0x7d14e000 },
24575 - { 0x00009814, 0x9c0a9f6b },
24576 - { 0x0000981c, 0x00000000 },
24577 - { 0x0000982c, 0x0000a000 },
24578 - { 0x00009830, 0x00000000 },
24579 - { 0x0000983c, 0x00200400 },
24580 - { 0x00009840, 0x206a002e },
24581 - { 0x0000984c, 0x1284233c },
24582 - { 0x00009854, 0x00000859 },
24583 - { 0x00009900, 0x00000000 },
24584 - { 0x00009904, 0x00000000 },
24585 - { 0x00009908, 0x00000000 },
24586 - { 0x0000990c, 0x00000000 },
24587 - { 0x0000991c, 0x10000fff },
24588 - { 0x00009920, 0x05100000 },
24589 - { 0x0000a920, 0x05100000 },
24590 - { 0x0000b920, 0x05100000 },
24591 - { 0x00009928, 0x00000001 },
24592 - { 0x0000992c, 0x00000004 },
24593 - { 0x00009934, 0x1e1f2022 },
24594 - { 0x00009938, 0x0a0b0c0d },
24595 - { 0x0000993c, 0x00000000 },
24596 - { 0x00009948, 0x9280b212 },
24597 - { 0x0000994c, 0x00020028 },
24598 - { 0x00009954, 0x5d50e188 },
24599 - { 0x00009958, 0x00081fff },
24600 - { 0x0000c95c, 0x004b6a8e },
24601 - { 0x0000c968, 0x000003ce },
24602 - { 0x00009970, 0x190fb515 },
24603 - { 0x00009974, 0x00000000 },
24604 - { 0x00009978, 0x00000001 },
24605 - { 0x0000997c, 0x00000000 },
24606 - { 0x00009980, 0x00000000 },
24607 - { 0x00009984, 0x00000000 },
24608 - { 0x00009988, 0x00000000 },
24609 - { 0x0000998c, 0x00000000 },
24610 - { 0x00009990, 0x00000000 },
24611 - { 0x00009994, 0x00000000 },
24612 - { 0x00009998, 0x00000000 },
24613 - { 0x0000999c, 0x00000000 },
24614 - { 0x000099a0, 0x00000000 },
24615 - { 0x000099a4, 0x00000001 },
24616 - { 0x000099a8, 0x001fff00 },
24617 - { 0x000099ac, 0x00000000 },
24618 - { 0x000099b0, 0x03051000 },
24619 - { 0x000099dc, 0x00000000 },
24620 - { 0x000099e0, 0x00000200 },
24621 - { 0x000099e4, 0xaaaaaaaa },
24622 - { 0x000099e8, 0x3c466478 },
24623 - { 0x000099ec, 0x000000aa },
24624 - { 0x000099fc, 0x00001042 },
24625 - { 0x00009b00, 0x00000000 },
24626 - { 0x00009b04, 0x00000001 },
24627 - { 0x00009b08, 0x00000002 },
24628 - { 0x00009b0c, 0x00000003 },
24629 - { 0x00009b10, 0x00000004 },
24630 - { 0x00009b14, 0x00000005 },
24631 - { 0x00009b18, 0x00000008 },
24632 - { 0x00009b1c, 0x00000009 },
24633 - { 0x00009b20, 0x0000000a },
24634 - { 0x00009b24, 0x0000000b },
24635 - { 0x00009b28, 0x0000000c },
24636 - { 0x00009b2c, 0x0000000d },
24637 - { 0x00009b30, 0x00000010 },
24638 - { 0x00009b34, 0x00000011 },
24639 - { 0x00009b38, 0x00000012 },
24640 - { 0x00009b3c, 0x00000013 },
24641 - { 0x00009b40, 0x00000014 },
24642 - { 0x00009b44, 0x00000015 },
24643 - { 0x00009b48, 0x00000018 },
24644 - { 0x00009b4c, 0x00000019 },
24645 - { 0x00009b50, 0x0000001a },
24646 - { 0x00009b54, 0x0000001b },
24647 - { 0x00009b58, 0x0000001c },
24648 - { 0x00009b5c, 0x0000001d },
24649 - { 0x00009b60, 0x00000020 },
24650 - { 0x00009b64, 0x00000021 },
24651 - { 0x00009b68, 0x00000022 },
24652 - { 0x00009b6c, 0x00000023 },
24653 - { 0x00009b70, 0x00000024 },
24654 - { 0x00009b74, 0x00000025 },
24655 - { 0x00009b78, 0x00000028 },
24656 - { 0x00009b7c, 0x00000029 },
24657 - { 0x00009b80, 0x0000002a },
24658 - { 0x00009b84, 0x0000002b },
24659 - { 0x00009b88, 0x0000002c },
24660 - { 0x00009b8c, 0x0000002d },
24661 - { 0x00009b90, 0x00000030 },
24662 - { 0x00009b94, 0x00000031 },
24663 - { 0x00009b98, 0x00000032 },
24664 - { 0x00009b9c, 0x00000033 },
24665 - { 0x00009ba0, 0x00000034 },
24666 - { 0x00009ba4, 0x00000035 },
24667 - { 0x00009ba8, 0x00000035 },
24668 - { 0x00009bac, 0x00000035 },
24669 - { 0x00009bb0, 0x00000035 },
24670 - { 0x00009bb4, 0x00000035 },
24671 - { 0x00009bb8, 0x00000035 },
24672 - { 0x00009bbc, 0x00000035 },
24673 - { 0x00009bc0, 0x00000035 },
24674 - { 0x00009bc4, 0x00000035 },
24675 - { 0x00009bc8, 0x00000035 },
24676 - { 0x00009bcc, 0x00000035 },
24677 - { 0x00009bd0, 0x00000035 },
24678 - { 0x00009bd4, 0x00000035 },
24679 - { 0x00009bd8, 0x00000035 },
24680 - { 0x00009bdc, 0x00000035 },
24681 - { 0x00009be0, 0x00000035 },
24682 - { 0x00009be4, 0x00000035 },
24683 - { 0x00009be8, 0x00000035 },
24684 - { 0x00009bec, 0x00000035 },
24685 - { 0x00009bf0, 0x00000035 },
24686 - { 0x00009bf4, 0x00000035 },
24687 - { 0x00009bf8, 0x00000010 },
24688 - { 0x00009bfc, 0x0000001a },
24689 - { 0x0000a210, 0x40806333 },
24690 - { 0x0000a214, 0x00106c10 },
24691 - { 0x0000a218, 0x009c4060 },
24692 - { 0x0000a220, 0x018830c6 },
24693 - { 0x0000a224, 0x00000400 },
24694 - { 0x0000a228, 0x00000bb5 },
24695 - { 0x0000a22c, 0x00000011 },
24696 - { 0x0000a234, 0x20202020 },
24697 - { 0x0000a238, 0x20202020 },
24698 - { 0x0000a23c, 0x13c889af },
24699 - { 0x0000a240, 0x38490a20 },
24700 - { 0x0000a244, 0x00007bb6 },
24701 - { 0x0000a248, 0x0fff3ffc },
24702 - { 0x0000a24c, 0x00000001 },
24703 - { 0x0000a250, 0x0000a000 },
24704 - { 0x0000a254, 0x00000000 },
24705 - { 0x0000a258, 0x0cc75380 },
24706 - { 0x0000a25c, 0x0f0f0f01 },
24707 - { 0x0000a260, 0xdfa91f01 },
24708 - { 0x0000a268, 0x00000000 },
24709 - { 0x0000a26c, 0x0e79e5c6 },
24710 - { 0x0000b26c, 0x0e79e5c6 },
24711 - { 0x0000c26c, 0x0e79e5c6 },
24712 - { 0x0000d270, 0x00820820 },
24713 - { 0x0000a278, 0x1ce739ce },
24714 - { 0x0000a27c, 0x051701ce },
24715 - { 0x0000a338, 0x00000000 },
24716 - { 0x0000a33c, 0x00000000 },
24717 - { 0x0000a340, 0x00000000 },
24718 - { 0x0000a344, 0x00000000 },
24719 - { 0x0000a348, 0x3fffffff },
24720 - { 0x0000a34c, 0x3fffffff },
24721 - { 0x0000a350, 0x3fffffff },
24722 - { 0x0000a354, 0x0003ffff },
24723 - { 0x0000a358, 0x79a8aa1f },
24724 - { 0x0000d35c, 0x07ffffef },
24725 - { 0x0000d360, 0x0fffffe7 },
24726 - { 0x0000d364, 0x17ffffe5 },
24727 - { 0x0000d368, 0x1fffffe4 },
24728 - { 0x0000d36c, 0x37ffffe3 },
24729 - { 0x0000d370, 0x3fffffe3 },
24730 - { 0x0000d374, 0x57ffffe3 },
24731 - { 0x0000d378, 0x5fffffe2 },
24732 - { 0x0000d37c, 0x7fffffe2 },
24733 - { 0x0000d380, 0x7f3c7bba },
24734 - { 0x0000d384, 0xf3307ff0 },
24735 - { 0x0000a388, 0x08000000 },
24736 - { 0x0000a38c, 0x20202020 },
24737 - { 0x0000a390, 0x20202020 },
24738 - { 0x0000a394, 0x1ce739ce },
24739 - { 0x0000a398, 0x000001ce },
24740 - { 0x0000a39c, 0x00000001 },
24741 - { 0x0000a3a0, 0x00000000 },
24742 - { 0x0000a3a4, 0x00000000 },
24743 - { 0x0000a3a8, 0x00000000 },
24744 - { 0x0000a3ac, 0x00000000 },
24745 - { 0x0000a3b0, 0x00000000 },
24746 - { 0x0000a3b4, 0x00000000 },
24747 - { 0x0000a3b8, 0x00000000 },
24748 - { 0x0000a3bc, 0x00000000 },
24749 - { 0x0000a3c0, 0x00000000 },
24750 - { 0x0000a3c4, 0x00000000 },
24751 - { 0x0000a3c8, 0x00000246 },
24752 - { 0x0000a3cc, 0x20202020 },
24753 - { 0x0000a3d0, 0x20202020 },
24754 - { 0x0000a3d4, 0x20202020 },
24755 - { 0x0000a3dc, 0x1ce739ce },
24756 - { 0x0000a3e0, 0x000001ce },
24757 -};
24758 -
24759 -static const u32 ar5416Bank0[][2] = {
24760 - { 0x000098b0, 0x1e5795e5 },
24761 - { 0x000098e0, 0x02008020 },
24762 -};
24763 -
24764 -static const u32 ar5416BB_RfGain[][3] = {
24765 - { 0x00009a00, 0x00000000, 0x00000000 },
24766 - { 0x00009a04, 0x00000040, 0x00000040 },
24767 - { 0x00009a08, 0x00000080, 0x00000080 },
24768 - { 0x00009a0c, 0x000001a1, 0x00000141 },
24769 - { 0x00009a10, 0x000001e1, 0x00000181 },
24770 - { 0x00009a14, 0x00000021, 0x000001c1 },
24771 - { 0x00009a18, 0x00000061, 0x00000001 },
24772 - { 0x00009a1c, 0x00000168, 0x00000041 },
24773 - { 0x00009a20, 0x000001a8, 0x000001a8 },
24774 - { 0x00009a24, 0x000001e8, 0x000001e8 },
24775 - { 0x00009a28, 0x00000028, 0x00000028 },
24776 - { 0x00009a2c, 0x00000068, 0x00000068 },
24777 - { 0x00009a30, 0x00000189, 0x000000a8 },
24778 - { 0x00009a34, 0x000001c9, 0x00000169 },
24779 - { 0x00009a38, 0x00000009, 0x000001a9 },
24780 - { 0x00009a3c, 0x00000049, 0x000001e9 },
24781 - { 0x00009a40, 0x00000089, 0x00000029 },
24782 - { 0x00009a44, 0x00000170, 0x00000069 },
24783 - { 0x00009a48, 0x000001b0, 0x00000190 },
24784 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
24785 - { 0x00009a50, 0x00000030, 0x00000010 },
24786 - { 0x00009a54, 0x00000070, 0x00000050 },
24787 - { 0x00009a58, 0x00000191, 0x00000090 },
24788 - { 0x00009a5c, 0x000001d1, 0x00000151 },
24789 - { 0x00009a60, 0x00000011, 0x00000191 },
24790 - { 0x00009a64, 0x00000051, 0x000001d1 },
24791 - { 0x00009a68, 0x00000091, 0x00000011 },
24792 - { 0x00009a6c, 0x000001b8, 0x00000051 },
24793 - { 0x00009a70, 0x000001f8, 0x00000198 },
24794 - { 0x00009a74, 0x00000038, 0x000001d8 },
24795 - { 0x00009a78, 0x00000078, 0x00000018 },
24796 - { 0x00009a7c, 0x00000199, 0x00000058 },
24797 - { 0x00009a80, 0x000001d9, 0x00000098 },
24798 - { 0x00009a84, 0x00000019, 0x00000159 },
24799 - { 0x00009a88, 0x00000059, 0x00000199 },
24800 - { 0x00009a8c, 0x00000099, 0x000001d9 },
24801 - { 0x00009a90, 0x000000d9, 0x00000019 },
24802 - { 0x00009a94, 0x000000f9, 0x00000059 },
24803 - { 0x00009a98, 0x000000f9, 0x00000099 },
24804 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
24805 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
24806 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
24807 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
24808 - { 0x00009aac, 0x000000f9, 0x000000f9 },
24809 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
24810 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
24811 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
24812 - { 0x00009abc, 0x000000f9, 0x000000f9 },
24813 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
24814 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
24815 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
24816 - { 0x00009acc, 0x000000f9, 0x000000f9 },
24817 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
24818 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
24819 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
24820 - { 0x00009adc, 0x000000f9, 0x000000f9 },
24821 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
24822 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
24823 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
24824 - { 0x00009aec, 0x000000f9, 0x000000f9 },
24825 - { 0x00009af0, 0x000000f9, 0x000000f9 },
24826 - { 0x00009af4, 0x000000f9, 0x000000f9 },
24827 - { 0x00009af8, 0x000000f9, 0x000000f9 },
24828 - { 0x00009afc, 0x000000f9, 0x000000f9 },
24829 -};
24830 -
24831 -static const u32 ar5416Bank1[][2] = {
24832 - { 0x000098b0, 0x02108421 },
24833 - { 0x000098ec, 0x00000008 },
24834 -};
24835 -
24836 -static const u32 ar5416Bank2[][2] = {
24837 - { 0x000098b0, 0x0e73ff17 },
24838 - { 0x000098e0, 0x00000420 },
24839 -};
24840 -
24841 -static const u32 ar5416Bank3[][3] = {
24842 - { 0x000098f0, 0x01400018, 0x01c00018 },
24843 -};
24844 -
24845 -static const u32 ar5416Bank6[][3] = {
24846 -
24847 - { 0x0000989c, 0x00000000, 0x00000000 },
24848 - { 0x0000989c, 0x00000000, 0x00000000 },
24849 - { 0x0000989c, 0x00000000, 0x00000000 },
24850 - { 0x0000989c, 0x00e00000, 0x00e00000 },
24851 - { 0x0000989c, 0x005e0000, 0x005e0000 },
24852 - { 0x0000989c, 0x00120000, 0x00120000 },
24853 - { 0x0000989c, 0x00620000, 0x00620000 },
24854 - { 0x0000989c, 0x00020000, 0x00020000 },
24855 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24856 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24857 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24858 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
24859 - { 0x0000989c, 0x005f0000, 0x005f0000 },
24860 - { 0x0000989c, 0x00870000, 0x00870000 },
24861 - { 0x0000989c, 0x00f90000, 0x00f90000 },
24862 - { 0x0000989c, 0x007b0000, 0x007b0000 },
24863 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24864 - { 0x0000989c, 0x00f50000, 0x00f50000 },
24865 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
24866 - { 0x0000989c, 0x00110000, 0x00110000 },
24867 - { 0x0000989c, 0x006100a8, 0x006100a8 },
24868 - { 0x0000989c, 0x004210a2, 0x004210a2 },
24869 - { 0x0000989c, 0x0014008f, 0x0014008f },
24870 - { 0x0000989c, 0x00c40003, 0x00c40003 },
24871 - { 0x0000989c, 0x003000f2, 0x003000f2 },
24872 - { 0x0000989c, 0x00440016, 0x00440016 },
24873 - { 0x0000989c, 0x00410040, 0x00410040 },
24874 - { 0x0000989c, 0x0001805e, 0x0001805e },
24875 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
24876 - { 0x0000989c, 0x000000f1, 0x000000f1 },
24877 - { 0x0000989c, 0x00002081, 0x00002081 },
24878 - { 0x0000989c, 0x000000d4, 0x000000d4 },
24879 - { 0x000098d0, 0x0000000f, 0x0010000f },
24880 -};
24881 -
24882 -static const u32 ar5416Bank6TPC[][3] = {
24883 - { 0x0000989c, 0x00000000, 0x00000000 },
24884 - { 0x0000989c, 0x00000000, 0x00000000 },
24885 - { 0x0000989c, 0x00000000, 0x00000000 },
24886 - { 0x0000989c, 0x00e00000, 0x00e00000 },
24887 - { 0x0000989c, 0x005e0000, 0x005e0000 },
24888 - { 0x0000989c, 0x00120000, 0x00120000 },
24889 - { 0x0000989c, 0x00620000, 0x00620000 },
24890 - { 0x0000989c, 0x00020000, 0x00020000 },
24891 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24892 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24893 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24894 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
24895 - { 0x0000989c, 0x005f0000, 0x005f0000 },
24896 - { 0x0000989c, 0x00870000, 0x00870000 },
24897 - { 0x0000989c, 0x00f90000, 0x00f90000 },
24898 - { 0x0000989c, 0x007b0000, 0x007b0000 },
24899 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
24900 - { 0x0000989c, 0x00f50000, 0x00f50000 },
24901 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
24902 - { 0x0000989c, 0x00110000, 0x00110000 },
24903 - { 0x0000989c, 0x006100a8, 0x006100a8 },
24904 - { 0x0000989c, 0x00423022, 0x00423022 },
24905 - { 0x0000989c, 0x201400df, 0x201400df },
24906 - { 0x0000989c, 0x00c40002, 0x00c40002 },
24907 - { 0x0000989c, 0x003000f2, 0x003000f2 },
24908 - { 0x0000989c, 0x00440016, 0x00440016 },
24909 - { 0x0000989c, 0x00410040, 0x00410040 },
24910 - { 0x0000989c, 0x0001805e, 0x0001805e },
24911 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
24912 - { 0x0000989c, 0x000000e1, 0x000000e1 },
24913 - { 0x0000989c, 0x00007081, 0x00007081 },
24914 - { 0x0000989c, 0x000000d4, 0x000000d4 },
24915 - { 0x000098d0, 0x0000000f, 0x0010000f },
24916 -};
24917 -
24918 -static const u32 ar5416Bank7[][2] = {
24919 - { 0x0000989c, 0x00000500 },
24920 - { 0x0000989c, 0x00000800 },
24921 - { 0x000098cc, 0x0000000e },
24922 -};
24923 -
24924 -static const u32 ar5416Addac[][2] = {
24925 - {0x0000989c, 0x00000000 },
24926 - {0x0000989c, 0x00000003 },
24927 - {0x0000989c, 0x00000000 },
24928 - {0x0000989c, 0x0000000c },
24929 - {0x0000989c, 0x00000000 },
24930 - {0x0000989c, 0x00000030 },
24931 - {0x0000989c, 0x00000000 },
24932 - {0x0000989c, 0x00000000 },
24933 - {0x0000989c, 0x00000000 },
24934 - {0x0000989c, 0x00000000 },
24935 - {0x0000989c, 0x00000000 },
24936 - {0x0000989c, 0x00000000 },
24937 - {0x0000989c, 0x00000000 },
24938 - {0x0000989c, 0x00000000 },
24939 - {0x0000989c, 0x00000000 },
24940 - {0x0000989c, 0x00000000 },
24941 - {0x0000989c, 0x00000000 },
24942 - {0x0000989c, 0x00000000 },
24943 - {0x0000989c, 0x00000060 },
24944 - {0x0000989c, 0x00000000 },
24945 - {0x0000989c, 0x00000000 },
24946 - {0x0000989c, 0x00000000 },
24947 - {0x0000989c, 0x00000000 },
24948 - {0x0000989c, 0x00000000 },
24949 - {0x0000989c, 0x00000000 },
24950 - {0x0000989c, 0x00000000 },
24951 - {0x0000989c, 0x00000000 },
24952 - {0x0000989c, 0x00000000 },
24953 - {0x0000989c, 0x00000000 },
24954 - {0x0000989c, 0x00000000 },
24955 - {0x0000989c, 0x00000000 },
24956 - {0x0000989c, 0x00000058 },
24957 - {0x0000989c, 0x00000000 },
24958 - {0x0000989c, 0x00000000 },
24959 - {0x0000989c, 0x00000000 },
24960 - {0x0000989c, 0x00000000 },
24961 - {0x000098cc, 0x00000000 },
24962 -};
24963 -
24964 -static const u32 ar5416Modes_9100[][6] = {
24965 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
24966 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
24967 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24968 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
24969 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
24970 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24971 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
24972 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
24973 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24974 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
24975 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
24976 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
24977 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
24978 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24979 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24980 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
24981 - { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
24982 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
24983 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
24984 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
24985 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
24986 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
24987 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
24988 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
24989 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
24990 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
24991 - { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
24992 - { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
24993 - { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
24994 - { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
24995 -#ifdef TB243
24996 - { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24997 - { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24998 - { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
24999 - { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
25000 -#else
25001 - { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
25002 - { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
25003 - { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
25004 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
25005 -#endif
25006 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
25007 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
25008 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
25009 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
25010 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
25011 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
25012 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25013 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25014 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
25015 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
25016 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25017 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25018 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25019 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
25020 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
25021 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
25022 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
25023 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
25024 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
25025 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
25026 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
25027 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
25028 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
25029 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
25030 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
25031 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
25032 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
25033 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25034 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25035 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25036 -};
25037 -
25038 -static const u32 ar5416Common_9100[][2] = {
25039 - { 0x0000000c, 0x00000000 },
25040 - { 0x00000030, 0x00020015 },
25041 - { 0x00000034, 0x00000005 },
25042 - { 0x00000040, 0x00000000 },
25043 - { 0x00000044, 0x00000008 },
25044 - { 0x00000048, 0x00000008 },
25045 - { 0x0000004c, 0x00000010 },
25046 - { 0x00000050, 0x00000000 },
25047 - { 0x00000054, 0x0000001f },
25048 - { 0x00000800, 0x00000000 },
25049 - { 0x00000804, 0x00000000 },
25050 - { 0x00000808, 0x00000000 },
25051 - { 0x0000080c, 0x00000000 },
25052 - { 0x00000810, 0x00000000 },
25053 - { 0x00000814, 0x00000000 },
25054 - { 0x00000818, 0x00000000 },
25055 - { 0x0000081c, 0x00000000 },
25056 - { 0x00000820, 0x00000000 },
25057 - { 0x00000824, 0x00000000 },
25058 - { 0x00001040, 0x002ffc0f },
25059 - { 0x00001044, 0x002ffc0f },
25060 - { 0x00001048, 0x002ffc0f },
25061 - { 0x0000104c, 0x002ffc0f },
25062 - { 0x00001050, 0x002ffc0f },
25063 - { 0x00001054, 0x002ffc0f },
25064 - { 0x00001058, 0x002ffc0f },
25065 - { 0x0000105c, 0x002ffc0f },
25066 - { 0x00001060, 0x002ffc0f },
25067 - { 0x00001064, 0x002ffc0f },
25068 - { 0x00001230, 0x00000000 },
25069 - { 0x00001270, 0x00000000 },
25070 - { 0x00001038, 0x00000000 },
25071 - { 0x00001078, 0x00000000 },
25072 - { 0x000010b8, 0x00000000 },
25073 - { 0x000010f8, 0x00000000 },
25074 - { 0x00001138, 0x00000000 },
25075 - { 0x00001178, 0x00000000 },
25076 - { 0x000011b8, 0x00000000 },
25077 - { 0x000011f8, 0x00000000 },
25078 - { 0x00001238, 0x00000000 },
25079 - { 0x00001278, 0x00000000 },
25080 - { 0x000012b8, 0x00000000 },
25081 - { 0x000012f8, 0x00000000 },
25082 - { 0x00001338, 0x00000000 },
25083 - { 0x00001378, 0x00000000 },
25084 - { 0x000013b8, 0x00000000 },
25085 - { 0x000013f8, 0x00000000 },
25086 - { 0x00001438, 0x00000000 },
25087 - { 0x00001478, 0x00000000 },
25088 - { 0x000014b8, 0x00000000 },
25089 - { 0x000014f8, 0x00000000 },
25090 - { 0x00001538, 0x00000000 },
25091 - { 0x00001578, 0x00000000 },
25092 - { 0x000015b8, 0x00000000 },
25093 - { 0x000015f8, 0x00000000 },
25094 - { 0x00001638, 0x00000000 },
25095 - { 0x00001678, 0x00000000 },
25096 - { 0x000016b8, 0x00000000 },
25097 - { 0x000016f8, 0x00000000 },
25098 - { 0x00001738, 0x00000000 },
25099 - { 0x00001778, 0x00000000 },
25100 - { 0x000017b8, 0x00000000 },
25101 - { 0x000017f8, 0x00000000 },
25102 - { 0x0000103c, 0x00000000 },
25103 - { 0x0000107c, 0x00000000 },
25104 - { 0x000010bc, 0x00000000 },
25105 - { 0x000010fc, 0x00000000 },
25106 - { 0x0000113c, 0x00000000 },
25107 - { 0x0000117c, 0x00000000 },
25108 - { 0x000011bc, 0x00000000 },
25109 - { 0x000011fc, 0x00000000 },
25110 - { 0x0000123c, 0x00000000 },
25111 - { 0x0000127c, 0x00000000 },
25112 - { 0x000012bc, 0x00000000 },
25113 - { 0x000012fc, 0x00000000 },
25114 - { 0x0000133c, 0x00000000 },
25115 - { 0x0000137c, 0x00000000 },
25116 - { 0x000013bc, 0x00000000 },
25117 - { 0x000013fc, 0x00000000 },
25118 - { 0x0000143c, 0x00000000 },
25119 - { 0x0000147c, 0x00000000 },
25120 - { 0x00020010, 0x00000003 },
25121 - { 0x00020038, 0x000004c2 },
25122 - { 0x00008004, 0x00000000 },
25123 - { 0x00008008, 0x00000000 },
25124 - { 0x0000800c, 0x00000000 },
25125 - { 0x00008018, 0x00000700 },
25126 - { 0x00008020, 0x00000000 },
25127 - { 0x00008038, 0x00000000 },
25128 - { 0x0000803c, 0x00000000 },
25129 - { 0x00008048, 0x40000000 },
25130 - { 0x00008054, 0x00004000 },
25131 - { 0x00008058, 0x00000000 },
25132 - { 0x0000805c, 0x000fc78f },
25133 - { 0x00008060, 0x0000000f },
25134 - { 0x00008064, 0x00000000 },
25135 - { 0x000080c0, 0x2a82301a },
25136 - { 0x000080c4, 0x05dc01e0 },
25137 - { 0x000080c8, 0x1f402710 },
25138 - { 0x000080cc, 0x01f40000 },
25139 - { 0x000080d0, 0x00001e00 },
25140 - { 0x000080d4, 0x00000000 },
25141 - { 0x000080d8, 0x00400000 },
25142 - { 0x000080e0, 0xffffffff },
25143 - { 0x000080e4, 0x0000ffff },
25144 - { 0x000080e8, 0x003f3f3f },
25145 - { 0x000080ec, 0x00000000 },
25146 - { 0x000080f0, 0x00000000 },
25147 - { 0x000080f4, 0x00000000 },
25148 - { 0x000080f8, 0x00000000 },
25149 - { 0x000080fc, 0x00020000 },
25150 - { 0x00008100, 0x00020000 },
25151 - { 0x00008104, 0x00000001 },
25152 - { 0x00008108, 0x00000052 },
25153 - { 0x0000810c, 0x00000000 },
25154 - { 0x00008110, 0x00000168 },
25155 - { 0x00008118, 0x000100aa },
25156 - { 0x0000811c, 0x00003210 },
25157 - { 0x00008120, 0x08f04800 },
25158 - { 0x00008124, 0x00000000 },
25159 - { 0x00008128, 0x00000000 },
25160 - { 0x0000812c, 0x00000000 },
25161 - { 0x00008130, 0x00000000 },
25162 - { 0x00008134, 0x00000000 },
25163 - { 0x00008138, 0x00000000 },
25164 - { 0x0000813c, 0x00000000 },
25165 - { 0x00008144, 0x00000000 },
25166 - { 0x00008168, 0x00000000 },
25167 - { 0x0000816c, 0x00000000 },
25168 - { 0x00008170, 0x32143320 },
25169 - { 0x00008174, 0xfaa4fa50 },
25170 - { 0x00008178, 0x00000100 },
25171 - { 0x0000817c, 0x00000000 },
25172 - { 0x000081c4, 0x00000000 },
25173 - { 0x000081d0, 0x00003210 },
25174 - { 0x000081ec, 0x00000000 },
25175 - { 0x000081f0, 0x00000000 },
25176 - { 0x000081f4, 0x00000000 },
25177 - { 0x000081f8, 0x00000000 },
25178 - { 0x000081fc, 0x00000000 },
25179 - { 0x00008200, 0x00000000 },
25180 - { 0x00008204, 0x00000000 },
25181 - { 0x00008208, 0x00000000 },
25182 - { 0x0000820c, 0x00000000 },
25183 - { 0x00008210, 0x00000000 },
25184 - { 0x00008214, 0x00000000 },
25185 - { 0x00008218, 0x00000000 },
25186 - { 0x0000821c, 0x00000000 },
25187 - { 0x00008220, 0x00000000 },
25188 - { 0x00008224, 0x00000000 },
25189 - { 0x00008228, 0x00000000 },
25190 - { 0x0000822c, 0x00000000 },
25191 - { 0x00008230, 0x00000000 },
25192 - { 0x00008234, 0x00000000 },
25193 - { 0x00008238, 0x00000000 },
25194 - { 0x0000823c, 0x00000000 },
25195 - { 0x00008240, 0x00100000 },
25196 - { 0x00008244, 0x0010f400 },
25197 - { 0x00008248, 0x00000100 },
25198 - { 0x0000824c, 0x0001e800 },
25199 - { 0x00008250, 0x00000000 },
25200 - { 0x00008254, 0x00000000 },
25201 - { 0x00008258, 0x00000000 },
25202 - { 0x0000825c, 0x400000ff },
25203 - { 0x00008260, 0x00080922 },
25204 - { 0x00008270, 0x00000000 },
25205 - { 0x00008274, 0x40000000 },
25206 - { 0x00008278, 0x003e4180 },
25207 - { 0x0000827c, 0x00000000 },
25208 - { 0x00008284, 0x0000002c },
25209 - { 0x00008288, 0x0000002c },
25210 - { 0x0000828c, 0x00000000 },
25211 - { 0x00008294, 0x00000000 },
25212 - { 0x00008298, 0x00000000 },
25213 - { 0x00008300, 0x00000000 },
25214 - { 0x00008304, 0x00000000 },
25215 - { 0x00008308, 0x00000000 },
25216 - { 0x0000830c, 0x00000000 },
25217 - { 0x00008310, 0x00000000 },
25218 - { 0x00008314, 0x00000000 },
25219 - { 0x00008318, 0x00000000 },
25220 - { 0x00008328, 0x00000000 },
25221 - { 0x0000832c, 0x00000007 },
25222 - { 0x00008330, 0x00000302 },
25223 - { 0x00008334, 0x00000e00 },
25224 - { 0x00008338, 0x00000000 },
25225 - { 0x0000833c, 0x00000000 },
25226 - { 0x00008340, 0x000107ff },
25227 - { 0x00009808, 0x00000000 },
25228 - { 0x0000980c, 0xad848e19 },
25229 - { 0x00009810, 0x7d14e000 },
25230 - { 0x00009814, 0x9c0a9f6b },
25231 - { 0x0000981c, 0x00000000 },
25232 - { 0x0000982c, 0x0000a000 },
25233 - { 0x00009830, 0x00000000 },
25234 - { 0x0000983c, 0x00200400 },
25235 - { 0x00009840, 0x206a01ae },
25236 - { 0x0000984c, 0x1284233c },
25237 - { 0x00009854, 0x00000859 },
25238 - { 0x00009900, 0x00000000 },
25239 - { 0x00009904, 0x00000000 },
25240 - { 0x00009908, 0x00000000 },
25241 - { 0x0000990c, 0x00000000 },
25242 - { 0x0000991c, 0x10000fff },
25243 - { 0x00009920, 0x05100000 },
25244 - { 0x0000a920, 0x05100000 },
25245 - { 0x0000b920, 0x05100000 },
25246 - { 0x00009928, 0x00000001 },
25247 - { 0x0000992c, 0x00000004 },
25248 - { 0x00009934, 0x1e1f2022 },
25249 - { 0x00009938, 0x0a0b0c0d },
25250 - { 0x0000993c, 0x00000000 },
25251 - { 0x00009948, 0x9280b212 },
25252 - { 0x0000994c, 0x00020028 },
25253 - { 0x0000c95c, 0x004b6a8e },
25254 - { 0x0000c968, 0x000003ce },
25255 - { 0x00009970, 0x190fb515 },
25256 - { 0x00009974, 0x00000000 },
25257 - { 0x00009978, 0x00000001 },
25258 - { 0x0000997c, 0x00000000 },
25259 - { 0x00009980, 0x00000000 },
25260 - { 0x00009984, 0x00000000 },
25261 - { 0x00009988, 0x00000000 },
25262 - { 0x0000998c, 0x00000000 },
25263 - { 0x00009990, 0x00000000 },
25264 - { 0x00009994, 0x00000000 },
25265 - { 0x00009998, 0x00000000 },
25266 - { 0x0000999c, 0x00000000 },
25267 - { 0x000099a0, 0x00000000 },
25268 - { 0x000099a4, 0x00000001 },
25269 - { 0x000099a8, 0x201fff00 },
25270 - { 0x000099ac, 0x006f0000 },
25271 - { 0x000099b0, 0x03051000 },
25272 - { 0x000099dc, 0x00000000 },
25273 - { 0x000099e0, 0x00000200 },
25274 - { 0x000099e4, 0xaaaaaaaa },
25275 - { 0x000099e8, 0x3c466478 },
25276 - { 0x000099ec, 0x0cc80caa },
25277 - { 0x000099fc, 0x00001042 },
25278 - { 0x00009b00, 0x00000000 },
25279 - { 0x00009b04, 0x00000001 },
25280 - { 0x00009b08, 0x00000002 },
25281 - { 0x00009b0c, 0x00000003 },
25282 - { 0x00009b10, 0x00000004 },
25283 - { 0x00009b14, 0x00000005 },
25284 - { 0x00009b18, 0x00000008 },
25285 - { 0x00009b1c, 0x00000009 },
25286 - { 0x00009b20, 0x0000000a },
25287 - { 0x00009b24, 0x0000000b },
25288 - { 0x00009b28, 0x0000000c },
25289 - { 0x00009b2c, 0x0000000d },
25290 - { 0x00009b30, 0x00000010 },
25291 - { 0x00009b34, 0x00000011 },
25292 - { 0x00009b38, 0x00000012 },
25293 - { 0x00009b3c, 0x00000013 },
25294 - { 0x00009b40, 0x00000014 },
25295 - { 0x00009b44, 0x00000015 },
25296 - { 0x00009b48, 0x00000018 },
25297 - { 0x00009b4c, 0x00000019 },
25298 - { 0x00009b50, 0x0000001a },
25299 - { 0x00009b54, 0x0000001b },
25300 - { 0x00009b58, 0x0000001c },
25301 - { 0x00009b5c, 0x0000001d },
25302 - { 0x00009b60, 0x00000020 },
25303 - { 0x00009b64, 0x00000021 },
25304 - { 0x00009b68, 0x00000022 },
25305 - { 0x00009b6c, 0x00000023 },
25306 - { 0x00009b70, 0x00000024 },
25307 - { 0x00009b74, 0x00000025 },
25308 - { 0x00009b78, 0x00000028 },
25309 - { 0x00009b7c, 0x00000029 },
25310 - { 0x00009b80, 0x0000002a },
25311 - { 0x00009b84, 0x0000002b },
25312 - { 0x00009b88, 0x0000002c },
25313 - { 0x00009b8c, 0x0000002d },
25314 - { 0x00009b90, 0x00000030 },
25315 - { 0x00009b94, 0x00000031 },
25316 - { 0x00009b98, 0x00000032 },
25317 - { 0x00009b9c, 0x00000033 },
25318 - { 0x00009ba0, 0x00000034 },
25319 - { 0x00009ba4, 0x00000035 },
25320 - { 0x00009ba8, 0x00000035 },
25321 - { 0x00009bac, 0x00000035 },
25322 - { 0x00009bb0, 0x00000035 },
25323 - { 0x00009bb4, 0x00000035 },
25324 - { 0x00009bb8, 0x00000035 },
25325 - { 0x00009bbc, 0x00000035 },
25326 - { 0x00009bc0, 0x00000035 },
25327 - { 0x00009bc4, 0x00000035 },
25328 - { 0x00009bc8, 0x00000035 },
25329 - { 0x00009bcc, 0x00000035 },
25330 - { 0x00009bd0, 0x00000035 },
25331 - { 0x00009bd4, 0x00000035 },
25332 - { 0x00009bd8, 0x00000035 },
25333 - { 0x00009bdc, 0x00000035 },
25334 - { 0x00009be0, 0x00000035 },
25335 - { 0x00009be4, 0x00000035 },
25336 - { 0x00009be8, 0x00000035 },
25337 - { 0x00009bec, 0x00000035 },
25338 - { 0x00009bf0, 0x00000035 },
25339 - { 0x00009bf4, 0x00000035 },
25340 - { 0x00009bf8, 0x00000010 },
25341 - { 0x00009bfc, 0x0000001a },
25342 - { 0x0000a210, 0x40806333 },
25343 - { 0x0000a214, 0x00106c10 },
25344 - { 0x0000a218, 0x009c4060 },
25345 - { 0x0000a220, 0x018830c6 },
25346 - { 0x0000a224, 0x00000400 },
25347 - { 0x0000a228, 0x001a0bb5 },
25348 - { 0x0000a22c, 0x00000000 },
25349 - { 0x0000a234, 0x20202020 },
25350 - { 0x0000a238, 0x20202020 },
25351 - { 0x0000a23c, 0x13c889ae },
25352 - { 0x0000a240, 0x38490a20 },
25353 - { 0x0000a244, 0x00007bb6 },
25354 - { 0x0000a248, 0x0fff3ffc },
25355 - { 0x0000a24c, 0x00000001 },
25356 - { 0x0000a250, 0x0000a000 },
25357 - { 0x0000a254, 0x00000000 },
25358 - { 0x0000a258, 0x0cc75380 },
25359 - { 0x0000a25c, 0x0f0f0f01 },
25360 - { 0x0000a260, 0xdfa91f01 },
25361 - { 0x0000a268, 0x00000001 },
25362 - { 0x0000a26c, 0x0ebae9c6 },
25363 - { 0x0000b26c, 0x0ebae9c6 },
25364 - { 0x0000c26c, 0x0ebae9c6 },
25365 - { 0x0000d270, 0x00820820 },
25366 - { 0x0000a278, 0x1ce739ce },
25367 - { 0x0000a27c, 0x050701ce },
25368 - { 0x0000a338, 0x00000000 },
25369 - { 0x0000a33c, 0x00000000 },
25370 - { 0x0000a340, 0x00000000 },
25371 - { 0x0000a344, 0x00000000 },
25372 - { 0x0000a348, 0x3fffffff },
25373 - { 0x0000a34c, 0x3fffffff },
25374 - { 0x0000a350, 0x3fffffff },
25375 - { 0x0000a354, 0x0003ffff },
25376 - { 0x0000a358, 0x79a8aa33 },
25377 - { 0x0000d35c, 0x07ffffef },
25378 - { 0x0000d360, 0x0fffffe7 },
25379 - { 0x0000d364, 0x17ffffe5 },
25380 - { 0x0000d368, 0x1fffffe4 },
25381 - { 0x0000d36c, 0x37ffffe3 },
25382 - { 0x0000d370, 0x3fffffe3 },
25383 - { 0x0000d374, 0x57ffffe3 },
25384 - { 0x0000d378, 0x5fffffe2 },
25385 - { 0x0000d37c, 0x7fffffe2 },
25386 - { 0x0000d380, 0x7f3c7bba },
25387 - { 0x0000d384, 0xf3307ff0 },
25388 - { 0x0000a388, 0x0c000000 },
25389 - { 0x0000a38c, 0x20202020 },
25390 - { 0x0000a390, 0x20202020 },
25391 - { 0x0000a394, 0x1ce739ce },
25392 - { 0x0000a398, 0x000001ce },
25393 - { 0x0000a39c, 0x00000001 },
25394 - { 0x0000a3a0, 0x00000000 },
25395 - { 0x0000a3a4, 0x00000000 },
25396 - { 0x0000a3a8, 0x00000000 },
25397 - { 0x0000a3ac, 0x00000000 },
25398 - { 0x0000a3b0, 0x00000000 },
25399 - { 0x0000a3b4, 0x00000000 },
25400 - { 0x0000a3b8, 0x00000000 },
25401 - { 0x0000a3bc, 0x00000000 },
25402 - { 0x0000a3c0, 0x00000000 },
25403 - { 0x0000a3c4, 0x00000000 },
25404 - { 0x0000a3c8, 0x00000246 },
25405 - { 0x0000a3cc, 0x20202020 },
25406 - { 0x0000a3d0, 0x20202020 },
25407 - { 0x0000a3d4, 0x20202020 },
25408 - { 0x0000a3dc, 0x1ce739ce },
25409 - { 0x0000a3e0, 0x000001ce },
25410 -};
25411 -
25412 -static const u32 ar5416Bank0_9100[][2] = {
25413 - { 0x000098b0, 0x1e5795e5 },
25414 - { 0x000098e0, 0x02008020 },
25415 -};
25416 -
25417 -static const u32 ar5416BB_RfGain_9100[][3] = {
25418 - { 0x00009a00, 0x00000000, 0x00000000 },
25419 - { 0x00009a04, 0x00000040, 0x00000040 },
25420 - { 0x00009a08, 0x00000080, 0x00000080 },
25421 - { 0x00009a0c, 0x000001a1, 0x00000141 },
25422 - { 0x00009a10, 0x000001e1, 0x00000181 },
25423 - { 0x00009a14, 0x00000021, 0x000001c1 },
25424 - { 0x00009a18, 0x00000061, 0x00000001 },
25425 - { 0x00009a1c, 0x00000168, 0x00000041 },
25426 - { 0x00009a20, 0x000001a8, 0x000001a8 },
25427 - { 0x00009a24, 0x000001e8, 0x000001e8 },
25428 - { 0x00009a28, 0x00000028, 0x00000028 },
25429 - { 0x00009a2c, 0x00000068, 0x00000068 },
25430 - { 0x00009a30, 0x00000189, 0x000000a8 },
25431 - { 0x00009a34, 0x000001c9, 0x00000169 },
25432 - { 0x00009a38, 0x00000009, 0x000001a9 },
25433 - { 0x00009a3c, 0x00000049, 0x000001e9 },
25434 - { 0x00009a40, 0x00000089, 0x00000029 },
25435 - { 0x00009a44, 0x00000170, 0x00000069 },
25436 - { 0x00009a48, 0x000001b0, 0x00000190 },
25437 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
25438 - { 0x00009a50, 0x00000030, 0x00000010 },
25439 - { 0x00009a54, 0x00000070, 0x00000050 },
25440 - { 0x00009a58, 0x00000191, 0x00000090 },
25441 - { 0x00009a5c, 0x000001d1, 0x00000151 },
25442 - { 0x00009a60, 0x00000011, 0x00000191 },
25443 - { 0x00009a64, 0x00000051, 0x000001d1 },
25444 - { 0x00009a68, 0x00000091, 0x00000011 },
25445 - { 0x00009a6c, 0x000001b8, 0x00000051 },
25446 - { 0x00009a70, 0x000001f8, 0x00000198 },
25447 - { 0x00009a74, 0x00000038, 0x000001d8 },
25448 - { 0x00009a78, 0x00000078, 0x00000018 },
25449 - { 0x00009a7c, 0x00000199, 0x00000058 },
25450 - { 0x00009a80, 0x000001d9, 0x00000098 },
25451 - { 0x00009a84, 0x00000019, 0x00000159 },
25452 - { 0x00009a88, 0x00000059, 0x00000199 },
25453 - { 0x00009a8c, 0x00000099, 0x000001d9 },
25454 - { 0x00009a90, 0x000000d9, 0x00000019 },
25455 - { 0x00009a94, 0x000000f9, 0x00000059 },
25456 - { 0x00009a98, 0x000000f9, 0x00000099 },
25457 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
25458 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
25459 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
25460 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
25461 - { 0x00009aac, 0x000000f9, 0x000000f9 },
25462 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
25463 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
25464 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
25465 - { 0x00009abc, 0x000000f9, 0x000000f9 },
25466 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
25467 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
25468 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
25469 - { 0x00009acc, 0x000000f9, 0x000000f9 },
25470 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
25471 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
25472 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
25473 - { 0x00009adc, 0x000000f9, 0x000000f9 },
25474 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
25475 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
25476 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
25477 - { 0x00009aec, 0x000000f9, 0x000000f9 },
25478 - { 0x00009af0, 0x000000f9, 0x000000f9 },
25479 - { 0x00009af4, 0x000000f9, 0x000000f9 },
25480 - { 0x00009af8, 0x000000f9, 0x000000f9 },
25481 - { 0x00009afc, 0x000000f9, 0x000000f9 },
25482 -};
25483 -
25484 -static const u32 ar5416Bank1_9100[][2] = {
25485 - { 0x000098b0, 0x02108421},
25486 - { 0x000098ec, 0x00000008},
25487 -};
25488 -
25489 -static const u32 ar5416Bank2_9100[][2] = {
25490 - { 0x000098b0, 0x0e73ff17},
25491 - { 0x000098e0, 0x00000420},
25492 -};
25493 -
25494 -static const u32 ar5416Bank3_9100[][3] = {
25495 - { 0x000098f0, 0x01400018, 0x01c00018 },
25496 -};
25497 -
25498 -static const u32 ar5416Bank6_9100[][3] = {
25499 -
25500 - { 0x0000989c, 0x00000000, 0x00000000 },
25501 - { 0x0000989c, 0x00000000, 0x00000000 },
25502 - { 0x0000989c, 0x00000000, 0x00000000 },
25503 - { 0x0000989c, 0x00e00000, 0x00e00000 },
25504 - { 0x0000989c, 0x005e0000, 0x005e0000 },
25505 - { 0x0000989c, 0x00120000, 0x00120000 },
25506 - { 0x0000989c, 0x00620000, 0x00620000 },
25507 - { 0x0000989c, 0x00020000, 0x00020000 },
25508 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25509 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25510 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25511 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25512 - { 0x0000989c, 0x005f0000, 0x005f0000 },
25513 - { 0x0000989c, 0x00870000, 0x00870000 },
25514 - { 0x0000989c, 0x00f90000, 0x00f90000 },
25515 - { 0x0000989c, 0x007b0000, 0x007b0000 },
25516 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25517 - { 0x0000989c, 0x00f50000, 0x00f50000 },
25518 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
25519 - { 0x0000989c, 0x00110000, 0x00110000 },
25520 - { 0x0000989c, 0x006100a8, 0x006100a8 },
25521 - { 0x0000989c, 0x004210a2, 0x004210a2 },
25522 - { 0x0000989c, 0x0014000f, 0x0014000f },
25523 - { 0x0000989c, 0x00c40002, 0x00c40002 },
25524 - { 0x0000989c, 0x003000f2, 0x003000f2 },
25525 - { 0x0000989c, 0x00440016, 0x00440016 },
25526 - { 0x0000989c, 0x00410040, 0x00410040 },
25527 - { 0x0000989c, 0x000180d6, 0x000180d6 },
25528 - { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
25529 - { 0x0000989c, 0x000000b1, 0x000000b1 },
25530 - { 0x0000989c, 0x00002000, 0x00002000 },
25531 - { 0x0000989c, 0x000000d4, 0x000000d4 },
25532 - { 0x000098d0, 0x0000000f, 0x0010000f },
25533 -};
25534 -
25535 -
25536 -static const u32 ar5416Bank6TPC_9100[][3] = {
25537 -
25538 - { 0x0000989c, 0x00000000, 0x00000000 },
25539 - { 0x0000989c, 0x00000000, 0x00000000 },
25540 - { 0x0000989c, 0x00000000, 0x00000000 },
25541 - { 0x0000989c, 0x00e00000, 0x00e00000 },
25542 - { 0x0000989c, 0x005e0000, 0x005e0000 },
25543 - { 0x0000989c, 0x00120000, 0x00120000 },
25544 - { 0x0000989c, 0x00620000, 0x00620000 },
25545 - { 0x0000989c, 0x00020000, 0x00020000 },
25546 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25547 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25548 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25549 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
25550 - { 0x0000989c, 0x005f0000, 0x005f0000 },
25551 - { 0x0000989c, 0x00870000, 0x00870000 },
25552 - { 0x0000989c, 0x00f90000, 0x00f90000 },
25553 - { 0x0000989c, 0x007b0000, 0x007b0000 },
25554 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
25555 - { 0x0000989c, 0x00f50000, 0x00f50000 },
25556 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
25557 - { 0x0000989c, 0x00110000, 0x00110000 },
25558 - { 0x0000989c, 0x006100a8, 0x006100a8 },
25559 - { 0x0000989c, 0x00423022, 0x00423022 },
25560 - { 0x0000989c, 0x2014008f, 0x2014008f },
25561 - { 0x0000989c, 0x00c40002, 0x00c40002 },
25562 - { 0x0000989c, 0x003000f2, 0x003000f2 },
25563 - { 0x0000989c, 0x00440016, 0x00440016 },
25564 - { 0x0000989c, 0x00410040, 0x00410040 },
25565 - { 0x0000989c, 0x0001805e, 0x0001805e },
25566 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
25567 - { 0x0000989c, 0x000000e1, 0x000000e1 },
25568 - { 0x0000989c, 0x00007080, 0x00007080 },
25569 - { 0x0000989c, 0x000000d4, 0x000000d4 },
25570 - { 0x000098d0, 0x0000000f, 0x0010000f },
25571 -};
25572 -
25573 -static const u32 ar5416Bank7_9100[][2] = {
25574 - { 0x0000989c, 0x00000500 },
25575 - { 0x0000989c, 0x00000800 },
25576 - { 0x000098cc, 0x0000000e },
25577 -};
25578 -
25579 -static const u32 ar5416Addac_9100[][2] = {
25580 - {0x0000989c, 0x00000000 },
25581 - {0x0000989c, 0x00000000 },
25582 - {0x0000989c, 0x00000000 },
25583 - {0x0000989c, 0x00000000 },
25584 - {0x0000989c, 0x00000000 },
25585 - {0x0000989c, 0x00000000 },
25586 - {0x0000989c, 0x00000000 },
25587 - {0x0000989c, 0x00000010 },
25588 - {0x0000989c, 0x00000000 },
25589 - {0x0000989c, 0x00000000 },
25590 - {0x0000989c, 0x00000000 },
25591 - {0x0000989c, 0x00000000 },
25592 - {0x0000989c, 0x00000000 },
25593 - {0x0000989c, 0x00000000 },
25594 - {0x0000989c, 0x00000000 },
25595 - {0x0000989c, 0x00000000 },
25596 - {0x0000989c, 0x00000000 },
25597 - {0x0000989c, 0x00000000 },
25598 - {0x0000989c, 0x00000000 },
25599 - {0x0000989c, 0x00000000 },
25600 - {0x0000989c, 0x00000000 },
25601 - {0x0000989c, 0x000000c0 },
25602 - {0x0000989c, 0x00000015 },
25603 - {0x0000989c, 0x00000000 },
25604 - {0x0000989c, 0x00000000 },
25605 - {0x0000989c, 0x00000000 },
25606 - {0x0000989c, 0x00000000 },
25607 - {0x0000989c, 0x00000000 },
25608 - {0x0000989c, 0x00000000 },
25609 - {0x0000989c, 0x00000000 },
25610 - {0x0000989c, 0x00000000 },
25611 - {0x000098cc, 0x00000000 },
25612 -};
25613 -
25614 -static const u32 ar5416Modes_9160[][6] = {
25615 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
25616 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
25617 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
25618 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25619 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
25620 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
25621 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
25622 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
25623 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
25624 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
25625 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
25626 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
25627 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
25628 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25629 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25630 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
25631 - { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
25632 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
25633 - { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
25634 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
25635 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
25636 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
25637 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
25638 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
25639 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
25640 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
25641 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
25642 - { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25643 - { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25644 - { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
25645 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
25646 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
25647 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
25648 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
25649 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
25650 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
25651 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
25652 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
25653 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25654 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25655 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
25656 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
25657 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25658 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25659 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
25660 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
25661 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
25662 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
25663 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
25664 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
25665 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
25666 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
25667 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
25668 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
25669 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
25670 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
25671 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
25672 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
25673 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
25674 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25675 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25676 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
25677 -};
25678 -
25679 -static const u32 ar5416Common_9160[][2] = {
25680 - { 0x0000000c, 0x00000000 },
25681 - { 0x00000030, 0x00020015 },
25682 - { 0x00000034, 0x00000005 },
25683 - { 0x00000040, 0x00000000 },
25684 - { 0x00000044, 0x00000008 },
25685 - { 0x00000048, 0x00000008 },
25686 - { 0x0000004c, 0x00000010 },
25687 - { 0x00000050, 0x00000000 },
25688 - { 0x00000054, 0x0000001f },
25689 - { 0x00000800, 0x00000000 },
25690 - { 0x00000804, 0x00000000 },
25691 - { 0x00000808, 0x00000000 },
25692 - { 0x0000080c, 0x00000000 },
25693 - { 0x00000810, 0x00000000 },
25694 - { 0x00000814, 0x00000000 },
25695 - { 0x00000818, 0x00000000 },
25696 - { 0x0000081c, 0x00000000 },
25697 - { 0x00000820, 0x00000000 },
25698 - { 0x00000824, 0x00000000 },
25699 - { 0x00001040, 0x002ffc0f },
25700 - { 0x00001044, 0x002ffc0f },
25701 - { 0x00001048, 0x002ffc0f },
25702 - { 0x0000104c, 0x002ffc0f },
25703 - { 0x00001050, 0x002ffc0f },
25704 - { 0x00001054, 0x002ffc0f },
25705 - { 0x00001058, 0x002ffc0f },
25706 - { 0x0000105c, 0x002ffc0f },
25707 - { 0x00001060, 0x002ffc0f },
25708 - { 0x00001064, 0x002ffc0f },
25709 - { 0x00001230, 0x00000000 },
25710 - { 0x00001270, 0x00000000 },
25711 - { 0x00001038, 0x00000000 },
25712 - { 0x00001078, 0x00000000 },
25713 - { 0x000010b8, 0x00000000 },
25714 - { 0x000010f8, 0x00000000 },
25715 - { 0x00001138, 0x00000000 },
25716 - { 0x00001178, 0x00000000 },
25717 - { 0x000011b8, 0x00000000 },
25718 - { 0x000011f8, 0x00000000 },
25719 - { 0x00001238, 0x00000000 },
25720 - { 0x00001278, 0x00000000 },
25721 - { 0x000012b8, 0x00000000 },
25722 - { 0x000012f8, 0x00000000 },
25723 - { 0x00001338, 0x00000000 },
25724 - { 0x00001378, 0x00000000 },
25725 - { 0x000013b8, 0x00000000 },
25726 - { 0x000013f8, 0x00000000 },
25727 - { 0x00001438, 0x00000000 },
25728 - { 0x00001478, 0x00000000 },
25729 - { 0x000014b8, 0x00000000 },
25730 - { 0x000014f8, 0x00000000 },
25731 - { 0x00001538, 0x00000000 },
25732 - { 0x00001578, 0x00000000 },
25733 - { 0x000015b8, 0x00000000 },
25734 - { 0x000015f8, 0x00000000 },
25735 - { 0x00001638, 0x00000000 },
25736 - { 0x00001678, 0x00000000 },
25737 - { 0x000016b8, 0x00000000 },
25738 - { 0x000016f8, 0x00000000 },
25739 - { 0x00001738, 0x00000000 },
25740 - { 0x00001778, 0x00000000 },
25741 - { 0x000017b8, 0x00000000 },
25742 - { 0x000017f8, 0x00000000 },
25743 - { 0x0000103c, 0x00000000 },
25744 - { 0x0000107c, 0x00000000 },
25745 - { 0x000010bc, 0x00000000 },
25746 - { 0x000010fc, 0x00000000 },
25747 - { 0x0000113c, 0x00000000 },
25748 - { 0x0000117c, 0x00000000 },
25749 - { 0x000011bc, 0x00000000 },
25750 - { 0x000011fc, 0x00000000 },
25751 - { 0x0000123c, 0x00000000 },
25752 - { 0x0000127c, 0x00000000 },
25753 - { 0x000012bc, 0x00000000 },
25754 - { 0x000012fc, 0x00000000 },
25755 - { 0x0000133c, 0x00000000 },
25756 - { 0x0000137c, 0x00000000 },
25757 - { 0x000013bc, 0x00000000 },
25758 - { 0x000013fc, 0x00000000 },
25759 - { 0x0000143c, 0x00000000 },
25760 - { 0x0000147c, 0x00000000 },
25761 - { 0x00004030, 0x00000002 },
25762 - { 0x0000403c, 0x00000002 },
25763 - { 0x00007010, 0x00000020 },
25764 - { 0x00007038, 0x000004c2 },
25765 - { 0x00008004, 0x00000000 },
25766 - { 0x00008008, 0x00000000 },
25767 - { 0x0000800c, 0x00000000 },
25768 - { 0x00008018, 0x00000700 },
25769 - { 0x00008020, 0x00000000 },
25770 - { 0x00008038, 0x00000000 },
25771 - { 0x0000803c, 0x00000000 },
25772 - { 0x00008048, 0x40000000 },
25773 - { 0x00008054, 0x00000000 },
25774 - { 0x00008058, 0x00000000 },
25775 - { 0x0000805c, 0x000fc78f },
25776 - { 0x00008060, 0x0000000f },
25777 - { 0x00008064, 0x00000000 },
25778 - { 0x000080c0, 0x2a82301a },
25779 - { 0x000080c4, 0x05dc01e0 },
25780 - { 0x000080c8, 0x1f402710 },
25781 - { 0x000080cc, 0x01f40000 },
25782 - { 0x000080d0, 0x00001e00 },
25783 - { 0x000080d4, 0x00000000 },
25784 - { 0x000080d8, 0x00400000 },
25785 - { 0x000080e0, 0xffffffff },
25786 - { 0x000080e4, 0x0000ffff },
25787 - { 0x000080e8, 0x003f3f3f },
25788 - { 0x000080ec, 0x00000000 },
25789 - { 0x000080f0, 0x00000000 },
25790 - { 0x000080f4, 0x00000000 },
25791 - { 0x000080f8, 0x00000000 },
25792 - { 0x000080fc, 0x00020000 },
25793 - { 0x00008100, 0x00020000 },
25794 - { 0x00008104, 0x00000001 },
25795 - { 0x00008108, 0x00000052 },
25796 - { 0x0000810c, 0x00000000 },
25797 - { 0x00008110, 0x00000168 },
25798 - { 0x00008118, 0x000100aa },
25799 - { 0x0000811c, 0x00003210 },
25800 - { 0x00008120, 0x08f04800 },
25801 - { 0x00008124, 0x00000000 },
25802 - { 0x00008128, 0x00000000 },
25803 - { 0x0000812c, 0x00000000 },
25804 - { 0x00008130, 0x00000000 },
25805 - { 0x00008134, 0x00000000 },
25806 - { 0x00008138, 0x00000000 },
25807 - { 0x0000813c, 0x00000000 },
25808 - { 0x00008144, 0xffffffff },
25809 - { 0x00008168, 0x00000000 },
25810 - { 0x0000816c, 0x00000000 },
25811 - { 0x00008170, 0x32143320 },
25812 - { 0x00008174, 0xfaa4fa50 },
25813 - { 0x00008178, 0x00000100 },
25814 - { 0x0000817c, 0x00000000 },
25815 - { 0x000081c4, 0x00000000 },
25816 - { 0x000081d0, 0x00003210 },
25817 - { 0x000081ec, 0x00000000 },
25818 - { 0x000081f0, 0x00000000 },
25819 - { 0x000081f4, 0x00000000 },
25820 - { 0x000081f8, 0x00000000 },
25821 - { 0x000081fc, 0x00000000 },
25822 - { 0x00008200, 0x00000000 },
25823 - { 0x00008204, 0x00000000 },
25824 - { 0x00008208, 0x00000000 },
25825 - { 0x0000820c, 0x00000000 },
25826 - { 0x00008210, 0x00000000 },
25827 - { 0x00008214, 0x00000000 },
25828 - { 0x00008218, 0x00000000 },
25829 - { 0x0000821c, 0x00000000 },
25830 - { 0x00008220, 0x00000000 },
25831 - { 0x00008224, 0x00000000 },
25832 - { 0x00008228, 0x00000000 },
25833 - { 0x0000822c, 0x00000000 },
25834 - { 0x00008230, 0x00000000 },
25835 - { 0x00008234, 0x00000000 },
25836 - { 0x00008238, 0x00000000 },
25837 - { 0x0000823c, 0x00000000 },
25838 - { 0x00008240, 0x00100000 },
25839 - { 0x00008244, 0x0010f400 },
25840 - { 0x00008248, 0x00000100 },
25841 - { 0x0000824c, 0x0001e800 },
25842 - { 0x00008250, 0x00000000 },
25843 - { 0x00008254, 0x00000000 },
25844 - { 0x00008258, 0x00000000 },
25845 - { 0x0000825c, 0x400000ff },
25846 - { 0x00008260, 0x00080922 },
25847 - { 0x00008270, 0x00000000 },
25848 - { 0x00008274, 0x40000000 },
25849 - { 0x00008278, 0x003e4180 },
25850 - { 0x0000827c, 0x00000000 },
25851 - { 0x00008284, 0x0000002c },
25852 - { 0x00008288, 0x0000002c },
25853 - { 0x0000828c, 0x00000000 },
25854 - { 0x00008294, 0x00000000 },
25855 - { 0x00008298, 0x00000000 },
25856 - { 0x00008300, 0x00000000 },
25857 - { 0x00008304, 0x00000000 },
25858 - { 0x00008308, 0x00000000 },
25859 - { 0x0000830c, 0x00000000 },
25860 - { 0x00008310, 0x00000000 },
25861 - { 0x00008314, 0x00000000 },
25862 - { 0x00008318, 0x00000000 },
25863 - { 0x00008328, 0x00000000 },
25864 - { 0x0000832c, 0x00000007 },
25865 - { 0x00008330, 0x00000302 },
25866 - { 0x00008334, 0x00000e00 },
25867 - { 0x00008338, 0x00ff0000 },
25868 - { 0x0000833c, 0x00000000 },
25869 - { 0x00008340, 0x000107ff },
25870 - { 0x00009808, 0x00000000 },
25871 - { 0x0000980c, 0xad848e19 },
25872 - { 0x00009810, 0x7d14e000 },
25873 - { 0x00009814, 0x9c0a9f6b },
25874 - { 0x0000981c, 0x00000000 },
25875 - { 0x0000982c, 0x0000a000 },
25876 - { 0x00009830, 0x00000000 },
25877 - { 0x0000983c, 0x00200400 },
25878 - { 0x00009840, 0x206a01ae },
25879 - { 0x0000984c, 0x1284233c },
25880 - { 0x00009854, 0x00000859 },
25881 - { 0x00009900, 0x00000000 },
25882 - { 0x00009904, 0x00000000 },
25883 - { 0x00009908, 0x00000000 },
25884 - { 0x0000990c, 0x00000000 },
25885 - { 0x0000991c, 0x10000fff },
25886 - { 0x00009920, 0x05100000 },
25887 - { 0x0000a920, 0x05100000 },
25888 - { 0x0000b920, 0x05100000 },
25889 - { 0x00009928, 0x00000001 },
25890 - { 0x0000992c, 0x00000004 },
25891 - { 0x00009934, 0x1e1f2022 },
25892 - { 0x00009938, 0x0a0b0c0d },
25893 - { 0x0000993c, 0x00000000 },
25894 - { 0x00009948, 0x9280b212 },
25895 - { 0x0000994c, 0x00020028 },
25896 - { 0x00009954, 0x5f3ca3de },
25897 - { 0x00009958, 0x2108ecff },
25898 - { 0x00009940, 0x00750604 },
25899 - { 0x0000c95c, 0x004b6a8e },
25900 - { 0x00009970, 0x190fb515 },
25901 - { 0x00009974, 0x00000000 },
25902 - { 0x00009978, 0x00000001 },
25903 - { 0x0000997c, 0x00000000 },
25904 - { 0x00009980, 0x00000000 },
25905 - { 0x00009984, 0x00000000 },
25906 - { 0x00009988, 0x00000000 },
25907 - { 0x0000998c, 0x00000000 },
25908 - { 0x00009990, 0x00000000 },
25909 - { 0x00009994, 0x00000000 },
25910 - { 0x00009998, 0x00000000 },
25911 - { 0x0000999c, 0x00000000 },
25912 - { 0x000099a0, 0x00000000 },
25913 - { 0x000099a4, 0x00000001 },
25914 - { 0x000099a8, 0x201fff00 },
25915 - { 0x000099ac, 0x006f0000 },
25916 - { 0x000099b0, 0x03051000 },
25917 - { 0x000099dc, 0x00000000 },
25918 - { 0x000099e0, 0x00000200 },
25919 - { 0x000099e4, 0xaaaaaaaa },
25920 - { 0x000099e8, 0x3c466478 },
25921 - { 0x000099ec, 0x0cc80caa },
25922 - { 0x000099fc, 0x00001042 },
25923 - { 0x00009b00, 0x00000000 },
25924 - { 0x00009b04, 0x00000001 },
25925 - { 0x00009b08, 0x00000002 },
25926 - { 0x00009b0c, 0x00000003 },
25927 - { 0x00009b10, 0x00000004 },
25928 - { 0x00009b14, 0x00000005 },
25929 - { 0x00009b18, 0x00000008 },
25930 - { 0x00009b1c, 0x00000009 },
25931 - { 0x00009b20, 0x0000000a },
25932 - { 0x00009b24, 0x0000000b },
25933 - { 0x00009b28, 0x0000000c },
25934 - { 0x00009b2c, 0x0000000d },
25935 - { 0x00009b30, 0x00000010 },
25936 - { 0x00009b34, 0x00000011 },
25937 - { 0x00009b38, 0x00000012 },
25938 - { 0x00009b3c, 0x00000013 },
25939 - { 0x00009b40, 0x00000014 },
25940 - { 0x00009b44, 0x00000015 },
25941 - { 0x00009b48, 0x00000018 },
25942 - { 0x00009b4c, 0x00000019 },
25943 - { 0x00009b50, 0x0000001a },
25944 - { 0x00009b54, 0x0000001b },
25945 - { 0x00009b58, 0x0000001c },
25946 - { 0x00009b5c, 0x0000001d },
25947 - { 0x00009b60, 0x00000020 },
25948 - { 0x00009b64, 0x00000021 },
25949 - { 0x00009b68, 0x00000022 },
25950 - { 0x00009b6c, 0x00000023 },
25951 - { 0x00009b70, 0x00000024 },
25952 - { 0x00009b74, 0x00000025 },
25953 - { 0x00009b78, 0x00000028 },
25954 - { 0x00009b7c, 0x00000029 },
25955 - { 0x00009b80, 0x0000002a },
25956 - { 0x00009b84, 0x0000002b },
25957 - { 0x00009b88, 0x0000002c },
25958 - { 0x00009b8c, 0x0000002d },
25959 - { 0x00009b90, 0x00000030 },
25960 - { 0x00009b94, 0x00000031 },
25961 - { 0x00009b98, 0x00000032 },
25962 - { 0x00009b9c, 0x00000033 },
25963 - { 0x00009ba0, 0x00000034 },
25964 - { 0x00009ba4, 0x00000035 },
25965 - { 0x00009ba8, 0x00000035 },
25966 - { 0x00009bac, 0x00000035 },
25967 - { 0x00009bb0, 0x00000035 },
25968 - { 0x00009bb4, 0x00000035 },
25969 - { 0x00009bb8, 0x00000035 },
25970 - { 0x00009bbc, 0x00000035 },
25971 - { 0x00009bc0, 0x00000035 },
25972 - { 0x00009bc4, 0x00000035 },
25973 - { 0x00009bc8, 0x00000035 },
25974 - { 0x00009bcc, 0x00000035 },
25975 - { 0x00009bd0, 0x00000035 },
25976 - { 0x00009bd4, 0x00000035 },
25977 - { 0x00009bd8, 0x00000035 },
25978 - { 0x00009bdc, 0x00000035 },
25979 - { 0x00009be0, 0x00000035 },
25980 - { 0x00009be4, 0x00000035 },
25981 - { 0x00009be8, 0x00000035 },
25982 - { 0x00009bec, 0x00000035 },
25983 - { 0x00009bf0, 0x00000035 },
25984 - { 0x00009bf4, 0x00000035 },
25985 - { 0x00009bf8, 0x00000010 },
25986 - { 0x00009bfc, 0x0000001a },
25987 - { 0x0000a210, 0x40806333 },
25988 - { 0x0000a214, 0x00106c10 },
25989 - { 0x0000a218, 0x009c4060 },
25990 - { 0x0000a220, 0x018830c6 },
25991 - { 0x0000a224, 0x00000400 },
25992 - { 0x0000a228, 0x001a0bb5 },
25993 - { 0x0000a22c, 0x00000000 },
25994 - { 0x0000a234, 0x20202020 },
25995 - { 0x0000a238, 0x20202020 },
25996 - { 0x0000a23c, 0x13c889af },
25997 - { 0x0000a240, 0x38490a20 },
25998 - { 0x0000a244, 0x00007bb6 },
25999 - { 0x0000a248, 0x0fff3ffc },
26000 - { 0x0000a24c, 0x00000001 },
26001 - { 0x0000a250, 0x0000e000 },
26002 - { 0x0000a254, 0x00000000 },
26003 - { 0x0000a258, 0x0cc75380 },
26004 - { 0x0000a25c, 0x0f0f0f01 },
26005 - { 0x0000a260, 0xdfa91f01 },
26006 - { 0x0000a268, 0x00000001 },
26007 - { 0x0000a26c, 0x0ebae9c6 },
26008 - { 0x0000b26c, 0x0ebae9c6 },
26009 - { 0x0000c26c, 0x0ebae9c6 },
26010 - { 0x0000d270, 0x00820820 },
26011 - { 0x0000a278, 0x1ce739ce },
26012 - { 0x0000a27c, 0x050701ce },
26013 - { 0x0000a338, 0x00000000 },
26014 - { 0x0000a33c, 0x00000000 },
26015 - { 0x0000a340, 0x00000000 },
26016 - { 0x0000a344, 0x00000000 },
26017 - { 0x0000a348, 0x3fffffff },
26018 - { 0x0000a34c, 0x3fffffff },
26019 - { 0x0000a350, 0x3fffffff },
26020 - { 0x0000a354, 0x0003ffff },
26021 - { 0x0000a358, 0x79bfaa03 },
26022 - { 0x0000d35c, 0x07ffffef },
26023 - { 0x0000d360, 0x0fffffe7 },
26024 - { 0x0000d364, 0x17ffffe5 },
26025 - { 0x0000d368, 0x1fffffe4 },
26026 - { 0x0000d36c, 0x37ffffe3 },
26027 - { 0x0000d370, 0x3fffffe3 },
26028 - { 0x0000d374, 0x57ffffe3 },
26029 - { 0x0000d378, 0x5fffffe2 },
26030 - { 0x0000d37c, 0x7fffffe2 },
26031 - { 0x0000d380, 0x7f3c7bba },
26032 - { 0x0000d384, 0xf3307ff0 },
26033 - { 0x0000a388, 0x0c000000 },
26034 - { 0x0000a38c, 0x20202020 },
26035 - { 0x0000a390, 0x20202020 },
26036 - { 0x0000a394, 0x1ce739ce },
26037 - { 0x0000a398, 0x000001ce },
26038 - { 0x0000a39c, 0x00000001 },
26039 - { 0x0000a3a0, 0x00000000 },
26040 - { 0x0000a3a4, 0x00000000 },
26041 - { 0x0000a3a8, 0x00000000 },
26042 - { 0x0000a3ac, 0x00000000 },
26043 - { 0x0000a3b0, 0x00000000 },
26044 - { 0x0000a3b4, 0x00000000 },
26045 - { 0x0000a3b8, 0x00000000 },
26046 - { 0x0000a3bc, 0x00000000 },
26047 - { 0x0000a3c0, 0x00000000 },
26048 - { 0x0000a3c4, 0x00000000 },
26049 - { 0x0000a3c8, 0x00000246 },
26050 - { 0x0000a3cc, 0x20202020 },
26051 - { 0x0000a3d0, 0x20202020 },
26052 - { 0x0000a3d4, 0x20202020 },
26053 - { 0x0000a3dc, 0x1ce739ce },
26054 - { 0x0000a3e0, 0x000001ce },
26055 -};
26056 -
26057 -static const u32 ar5416Bank0_9160[][2] = {
26058 - { 0x000098b0, 0x1e5795e5 },
26059 - { 0x000098e0, 0x02008020 },
26060 -};
26061 -
26062 -static const u32 ar5416BB_RfGain_9160[][3] = {
26063 - { 0x00009a00, 0x00000000, 0x00000000 },
26064 - { 0x00009a04, 0x00000040, 0x00000040 },
26065 - { 0x00009a08, 0x00000080, 0x00000080 },
26066 - { 0x00009a0c, 0x000001a1, 0x00000141 },
26067 - { 0x00009a10, 0x000001e1, 0x00000181 },
26068 - { 0x00009a14, 0x00000021, 0x000001c1 },
26069 - { 0x00009a18, 0x00000061, 0x00000001 },
26070 - { 0x00009a1c, 0x00000168, 0x00000041 },
26071 - { 0x00009a20, 0x000001a8, 0x000001a8 },
26072 - { 0x00009a24, 0x000001e8, 0x000001e8 },
26073 - { 0x00009a28, 0x00000028, 0x00000028 },
26074 - { 0x00009a2c, 0x00000068, 0x00000068 },
26075 - { 0x00009a30, 0x00000189, 0x000000a8 },
26076 - { 0x00009a34, 0x000001c9, 0x00000169 },
26077 - { 0x00009a38, 0x00000009, 0x000001a9 },
26078 - { 0x00009a3c, 0x00000049, 0x000001e9 },
26079 - { 0x00009a40, 0x00000089, 0x00000029 },
26080 - { 0x00009a44, 0x00000170, 0x00000069 },
26081 - { 0x00009a48, 0x000001b0, 0x00000190 },
26082 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
26083 - { 0x00009a50, 0x00000030, 0x00000010 },
26084 - { 0x00009a54, 0x00000070, 0x00000050 },
26085 - { 0x00009a58, 0x00000191, 0x00000090 },
26086 - { 0x00009a5c, 0x000001d1, 0x00000151 },
26087 - { 0x00009a60, 0x00000011, 0x00000191 },
26088 - { 0x00009a64, 0x00000051, 0x000001d1 },
26089 - { 0x00009a68, 0x00000091, 0x00000011 },
26090 - { 0x00009a6c, 0x000001b8, 0x00000051 },
26091 - { 0x00009a70, 0x000001f8, 0x00000198 },
26092 - { 0x00009a74, 0x00000038, 0x000001d8 },
26093 - { 0x00009a78, 0x00000078, 0x00000018 },
26094 - { 0x00009a7c, 0x00000199, 0x00000058 },
26095 - { 0x00009a80, 0x000001d9, 0x00000098 },
26096 - { 0x00009a84, 0x00000019, 0x00000159 },
26097 - { 0x00009a88, 0x00000059, 0x00000199 },
26098 - { 0x00009a8c, 0x00000099, 0x000001d9 },
26099 - { 0x00009a90, 0x000000d9, 0x00000019 },
26100 - { 0x00009a94, 0x000000f9, 0x00000059 },
26101 - { 0x00009a98, 0x000000f9, 0x00000099 },
26102 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
26103 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
26104 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
26105 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
26106 - { 0x00009aac, 0x000000f9, 0x000000f9 },
26107 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
26108 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
26109 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
26110 - { 0x00009abc, 0x000000f9, 0x000000f9 },
26111 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
26112 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
26113 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
26114 - { 0x00009acc, 0x000000f9, 0x000000f9 },
26115 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
26116 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
26117 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
26118 - { 0x00009adc, 0x000000f9, 0x000000f9 },
26119 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
26120 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
26121 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
26122 - { 0x00009aec, 0x000000f9, 0x000000f9 },
26123 - { 0x00009af0, 0x000000f9, 0x000000f9 },
26124 - { 0x00009af4, 0x000000f9, 0x000000f9 },
26125 - { 0x00009af8, 0x000000f9, 0x000000f9 },
26126 - { 0x00009afc, 0x000000f9, 0x000000f9 },
26127 -};
26128 -
26129 -static const u32 ar5416Bank1_9160[][2] = {
26130 - { 0x000098b0, 0x02108421 },
26131 - { 0x000098ec, 0x00000008 },
26132 -};
26133 -
26134 -static const u32 ar5416Bank2_9160[][2] = {
26135 - { 0x000098b0, 0x0e73ff17 },
26136 - { 0x000098e0, 0x00000420 },
26137 -};
26138 -
26139 -static const u32 ar5416Bank3_9160[][3] = {
26140 - { 0x000098f0, 0x01400018, 0x01c00018 },
26141 -};
26142 -
26143 -static const u32 ar5416Bank6_9160[][3] = {
26144 - { 0x0000989c, 0x00000000, 0x00000000 },
26145 - { 0x0000989c, 0x00000000, 0x00000000 },
26146 - { 0x0000989c, 0x00000000, 0x00000000 },
26147 - { 0x0000989c, 0x00e00000, 0x00e00000 },
26148 - { 0x0000989c, 0x005e0000, 0x005e0000 },
26149 - { 0x0000989c, 0x00120000, 0x00120000 },
26150 - { 0x0000989c, 0x00620000, 0x00620000 },
26151 - { 0x0000989c, 0x00020000, 0x00020000 },
26152 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26153 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26154 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26155 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
26156 - { 0x0000989c, 0x005f0000, 0x005f0000 },
26157 - { 0x0000989c, 0x00870000, 0x00870000 },
26158 - { 0x0000989c, 0x00f90000, 0x00f90000 },
26159 - { 0x0000989c, 0x007b0000, 0x007b0000 },
26160 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26161 - { 0x0000989c, 0x00f50000, 0x00f50000 },
26162 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
26163 - { 0x0000989c, 0x00110000, 0x00110000 },
26164 - { 0x0000989c, 0x006100a8, 0x006100a8 },
26165 - { 0x0000989c, 0x004210a2, 0x004210a2 },
26166 - { 0x0000989c, 0x0014008f, 0x0014008f },
26167 - { 0x0000989c, 0x00c40003, 0x00c40003 },
26168 - { 0x0000989c, 0x003000f2, 0x003000f2 },
26169 - { 0x0000989c, 0x00440016, 0x00440016 },
26170 - { 0x0000989c, 0x00410040, 0x00410040 },
26171 - { 0x0000989c, 0x0001805e, 0x0001805e },
26172 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
26173 - { 0x0000989c, 0x000000f1, 0x000000f1 },
26174 - { 0x0000989c, 0x00002081, 0x00002081 },
26175 - { 0x0000989c, 0x000000d4, 0x000000d4 },
26176 - { 0x000098d0, 0x0000000f, 0x0010000f },
26177 -};
26178 -
26179 -static const u32 ar5416Bank6TPC_9160[][3] = {
26180 - { 0x0000989c, 0x00000000, 0x00000000 },
26181 - { 0x0000989c, 0x00000000, 0x00000000 },
26182 - { 0x0000989c, 0x00000000, 0x00000000 },
26183 - { 0x0000989c, 0x00e00000, 0x00e00000 },
26184 - { 0x0000989c, 0x005e0000, 0x005e0000 },
26185 - { 0x0000989c, 0x00120000, 0x00120000 },
26186 - { 0x0000989c, 0x00620000, 0x00620000 },
26187 - { 0x0000989c, 0x00020000, 0x00020000 },
26188 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26189 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26190 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26191 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
26192 - { 0x0000989c, 0x005f0000, 0x005f0000 },
26193 - { 0x0000989c, 0x00870000, 0x00870000 },
26194 - { 0x0000989c, 0x00f90000, 0x00f90000 },
26195 - { 0x0000989c, 0x007b0000, 0x007b0000 },
26196 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
26197 - { 0x0000989c, 0x00f50000, 0x00f50000 },
26198 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
26199 - { 0x0000989c, 0x00110000, 0x00110000 },
26200 - { 0x0000989c, 0x006100a8, 0x006100a8 },
26201 - { 0x0000989c, 0x00423022, 0x00423022 },
26202 - { 0x0000989c, 0x2014008f, 0x2014008f },
26203 - { 0x0000989c, 0x00c40002, 0x00c40002 },
26204 - { 0x0000989c, 0x003000f2, 0x003000f2 },
26205 - { 0x0000989c, 0x00440016, 0x00440016 },
26206 - { 0x0000989c, 0x00410040, 0x00410040 },
26207 - { 0x0000989c, 0x0001805e, 0x0001805e },
26208 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
26209 - { 0x0000989c, 0x000000e1, 0x000000e1 },
26210 - { 0x0000989c, 0x00007080, 0x00007080 },
26211 - { 0x0000989c, 0x000000d4, 0x000000d4 },
26212 - { 0x000098d0, 0x0000000f, 0x0010000f },
26213 -};
26214 -
26215 -static const u32 ar5416Bank7_9160[][2] = {
26216 - { 0x0000989c, 0x00000500 },
26217 - { 0x0000989c, 0x00000800 },
26218 - { 0x000098cc, 0x0000000e },
26219 -};
26220 -
26221 -static u32 ar5416Addac_9160[][2] = {
26222 - {0x0000989c, 0x00000000 },
26223 - {0x0000989c, 0x00000000 },
26224 - {0x0000989c, 0x00000000 },
26225 - {0x0000989c, 0x00000000 },
26226 - {0x0000989c, 0x00000000 },
26227 - {0x0000989c, 0x00000000 },
26228 - {0x0000989c, 0x000000c0 },
26229 - {0x0000989c, 0x00000018 },
26230 - {0x0000989c, 0x00000004 },
26231 - {0x0000989c, 0x00000000 },
26232 - {0x0000989c, 0x00000000 },
26233 - {0x0000989c, 0x00000000 },
26234 - {0x0000989c, 0x00000000 },
26235 - {0x0000989c, 0x00000000 },
26236 - {0x0000989c, 0x00000000 },
26237 - {0x0000989c, 0x00000000 },
26238 - {0x0000989c, 0x00000000 },
26239 - {0x0000989c, 0x00000000 },
26240 - {0x0000989c, 0x00000000 },
26241 - {0x0000989c, 0x00000000 },
26242 - {0x0000989c, 0x00000000 },
26243 - {0x0000989c, 0x000000c0 },
26244 - {0x0000989c, 0x00000019 },
26245 - {0x0000989c, 0x00000004 },
26246 - {0x0000989c, 0x00000000 },
26247 - {0x0000989c, 0x00000000 },
26248 - {0x0000989c, 0x00000000 },
26249 - {0x0000989c, 0x00000004 },
26250 - {0x0000989c, 0x00000003 },
26251 - {0x0000989c, 0x00000008 },
26252 - {0x0000989c, 0x00000000 },
26253 - {0x000098cc, 0x00000000 },
26254 -};
26255 -
26256 -static u32 ar5416Addac_91601_1[][2] = {
26257 - {0x0000989c, 0x00000000 },
26258 - {0x0000989c, 0x00000000 },
26259 - {0x0000989c, 0x00000000 },
26260 - {0x0000989c, 0x00000000 },
26261 - {0x0000989c, 0x00000000 },
26262 - {0x0000989c, 0x00000000 },
26263 - {0x0000989c, 0x000000c0 },
26264 - {0x0000989c, 0x00000018 },
26265 - {0x0000989c, 0x00000004 },
26266 - {0x0000989c, 0x00000000 },
26267 - {0x0000989c, 0x00000000 },
26268 - {0x0000989c, 0x00000000 },
26269 - {0x0000989c, 0x00000000 },
26270 - {0x0000989c, 0x00000000 },
26271 - {0x0000989c, 0x00000000 },
26272 - {0x0000989c, 0x00000000 },
26273 - {0x0000989c, 0x00000000 },
26274 - {0x0000989c, 0x00000000 },
26275 - {0x0000989c, 0x00000000 },
26276 - {0x0000989c, 0x00000000 },
26277 - {0x0000989c, 0x00000000 },
26278 - {0x0000989c, 0x000000c0 },
26279 - {0x0000989c, 0x00000019 },
26280 - {0x0000989c, 0x00000004 },
26281 - {0x0000989c, 0x00000000 },
26282 - {0x0000989c, 0x00000000 },
26283 - {0x0000989c, 0x00000000 },
26284 - {0x0000989c, 0x00000000 },
26285 - {0x0000989c, 0x00000000 },
26286 - {0x0000989c, 0x00000000 },
26287 - {0x0000989c, 0x00000000 },
26288 - {0x000098cc, 0x00000000 },
26289 -};
26290 -
26291 -/* XXX 9280 1 */
26292 -static const u32 ar9280Modes_9280[][6] = {
26293 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
26294 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
26295 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
26296 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
26297 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
26298 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
26299 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
26300 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26301 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26302 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
26303 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26304 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
26305 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
26306 - { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
26307 - { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
26308 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
26309 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
26310 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
26311 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
26312 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
26313 - { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
26314 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
26315 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
26316 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
26317 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
26318 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
26319 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26320 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26321 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
26322 - { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
26323 - { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
26324 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
26325 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
26326 - { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
26327 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
26328 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
26329 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26330 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26331 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
26332 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
26333 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
26334 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
26335 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
26336 - { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
26337 - { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
26338 - { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
26339 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
26340 - { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
26341 - { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
26342 - { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
26343 - { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
26344 - { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
26345 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
26346 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
26347 - { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
26348 - { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
26349 - { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
26350 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
26351 - { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
26352 - { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
26353 - { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
26354 - { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
26355 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
26356 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
26357 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
26358 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
26359 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
26360 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
26361 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
26362 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
26363 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
26364 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
26365 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
26366 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
26367 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
26368 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
26369 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
26370 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
26371 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
26372 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
26373 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
26374 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
26375 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
26376 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
26377 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
26378 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
26379 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
26380 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
26381 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
26382 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
26383 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
26384 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
26385 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
26386 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
26387 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
26388 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
26389 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
26390 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
26391 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
26392 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
26393 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
26394 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
26395 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
26396 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
26397 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
26398 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
26399 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
26400 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
26401 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
26402 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
26403 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
26404 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
26405 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
26406 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
26407 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
26408 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
26409 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
26410 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
26411 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
26412 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
26413 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
26414 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
26415 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
26416 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
26417 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
26418 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
26419 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
26420 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
26421 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
26422 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
26423 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
26424 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
26425 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
26426 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
26427 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
26428 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
26429 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
26430 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
26431 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
26432 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
26433 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26434 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26435 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26436 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26437 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26438 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26439 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26440 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26441 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26442 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26443 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26444 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26445 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26446 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26447 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26448 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26449 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26450 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26451 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26452 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26453 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26454 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26455 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26456 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26457 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26458 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
26459 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
26460 - { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
26461 - { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
26462 - { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
26463 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
26464 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
26465 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
26466 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26467 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
26468 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
26469 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
26470 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
26471 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
26472 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
26473 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
26474 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
26475 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
26476 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
26477 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
26478 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
26479 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
26480 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
26481 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
26482 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
26483 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
26484 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
26485 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
26486 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
26487 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
26488 - { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
26489 - { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
26490 - { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
26491 - { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
26492 -};
26493 -
26494 -static const u32 ar9280Common_9280[][2] = {
26495 - { 0x0000000c, 0x00000000 },
26496 - { 0x00000030, 0x00020015 },
26497 - { 0x00000034, 0x00000005 },
26498 - { 0x00000040, 0x00000000 },
26499 - { 0x00000044, 0x00000008 },
26500 - { 0x00000048, 0x00000008 },
26501 - { 0x0000004c, 0x00000010 },
26502 - { 0x00000050, 0x00000000 },
26503 - { 0x00000054, 0x0000001f },
26504 - { 0x00000800, 0x00000000 },
26505 - { 0x00000804, 0x00000000 },
26506 - { 0x00000808, 0x00000000 },
26507 - { 0x0000080c, 0x00000000 },
26508 - { 0x00000810, 0x00000000 },
26509 - { 0x00000814, 0x00000000 },
26510 - { 0x00000818, 0x00000000 },
26511 - { 0x0000081c, 0x00000000 },
26512 - { 0x00000820, 0x00000000 },
26513 - { 0x00000824, 0x00000000 },
26514 - { 0x00001040, 0x002ffc0f },
26515 - { 0x00001044, 0x002ffc0f },
26516 - { 0x00001048, 0x002ffc0f },
26517 - { 0x0000104c, 0x002ffc0f },
26518 - { 0x00001050, 0x002ffc0f },
26519 - { 0x00001054, 0x002ffc0f },
26520 - { 0x00001058, 0x002ffc0f },
26521 - { 0x0000105c, 0x002ffc0f },
26522 - { 0x00001060, 0x002ffc0f },
26523 - { 0x00001064, 0x002ffc0f },
26524 - { 0x00001230, 0x00000000 },
26525 - { 0x00001270, 0x00000000 },
26526 - { 0x00001038, 0x00000000 },
26527 - { 0x00001078, 0x00000000 },
26528 - { 0x000010b8, 0x00000000 },
26529 - { 0x000010f8, 0x00000000 },
26530 - { 0x00001138, 0x00000000 },
26531 - { 0x00001178, 0x00000000 },
26532 - { 0x000011b8, 0x00000000 },
26533 - { 0x000011f8, 0x00000000 },
26534 - { 0x00001238, 0x00000000 },
26535 - { 0x00001278, 0x00000000 },
26536 - { 0x000012b8, 0x00000000 },
26537 - { 0x000012f8, 0x00000000 },
26538 - { 0x00001338, 0x00000000 },
26539 - { 0x00001378, 0x00000000 },
26540 - { 0x000013b8, 0x00000000 },
26541 - { 0x000013f8, 0x00000000 },
26542 - { 0x00001438, 0x00000000 },
26543 - { 0x00001478, 0x00000000 },
26544 - { 0x000014b8, 0x00000000 },
26545 - { 0x000014f8, 0x00000000 },
26546 - { 0x00001538, 0x00000000 },
26547 - { 0x00001578, 0x00000000 },
26548 - { 0x000015b8, 0x00000000 },
26549 - { 0x000015f8, 0x00000000 },
26550 - { 0x00001638, 0x00000000 },
26551 - { 0x00001678, 0x00000000 },
26552 - { 0x000016b8, 0x00000000 },
26553 - { 0x000016f8, 0x00000000 },
26554 - { 0x00001738, 0x00000000 },
26555 - { 0x00001778, 0x00000000 },
26556 - { 0x000017b8, 0x00000000 },
26557 - { 0x000017f8, 0x00000000 },
26558 - { 0x0000103c, 0x00000000 },
26559 - { 0x0000107c, 0x00000000 },
26560 - { 0x000010bc, 0x00000000 },
26561 - { 0x000010fc, 0x00000000 },
26562 - { 0x0000113c, 0x00000000 },
26563 - { 0x0000117c, 0x00000000 },
26564 - { 0x000011bc, 0x00000000 },
26565 - { 0x000011fc, 0x00000000 },
26566 - { 0x0000123c, 0x00000000 },
26567 - { 0x0000127c, 0x00000000 },
26568 - { 0x000012bc, 0x00000000 },
26569 - { 0x000012fc, 0x00000000 },
26570 - { 0x0000133c, 0x00000000 },
26571 - { 0x0000137c, 0x00000000 },
26572 - { 0x000013bc, 0x00000000 },
26573 - { 0x000013fc, 0x00000000 },
26574 - { 0x0000143c, 0x00000000 },
26575 - { 0x0000147c, 0x00000000 },
26576 - { 0x00004030, 0x00000002 },
26577 - { 0x0000403c, 0x00000002 },
26578 - { 0x00004024, 0x0000001f },
26579 - { 0x00007010, 0x00000033 },
26580 - { 0x00007038, 0x000004c2 },
26581 - { 0x00008004, 0x00000000 },
26582 - { 0x00008008, 0x00000000 },
26583 - { 0x0000800c, 0x00000000 },
26584 - { 0x00008018, 0x00000700 },
26585 - { 0x00008020, 0x00000000 },
26586 - { 0x00008038, 0x00000000 },
26587 - { 0x0000803c, 0x00000000 },
26588 - { 0x00008048, 0x40000000 },
26589 - { 0x00008054, 0x00000000 },
26590 - { 0x00008058, 0x00000000 },
26591 - { 0x0000805c, 0x000fc78f },
26592 - { 0x00008060, 0x0000000f },
26593 - { 0x00008064, 0x00000000 },
26594 - { 0x00008070, 0x00000000 },
26595 - { 0x000080c0, 0x2a82301a },
26596 - { 0x000080c4, 0x05dc01e0 },
26597 - { 0x000080c8, 0x1f402710 },
26598 - { 0x000080cc, 0x01f40000 },
26599 - { 0x000080d0, 0x00001e00 },
26600 - { 0x000080d4, 0x00000000 },
26601 - { 0x000080d8, 0x00400000 },
26602 - { 0x000080e0, 0xffffffff },
26603 - { 0x000080e4, 0x0000ffff },
26604 - { 0x000080e8, 0x003f3f3f },
26605 - { 0x000080ec, 0x00000000 },
26606 - { 0x000080f0, 0x00000000 },
26607 - { 0x000080f4, 0x00000000 },
26608 - { 0x000080f8, 0x00000000 },
26609 - { 0x000080fc, 0x00020000 },
26610 - { 0x00008100, 0x00020000 },
26611 - { 0x00008104, 0x00000001 },
26612 - { 0x00008108, 0x00000052 },
26613 - { 0x0000810c, 0x00000000 },
26614 - { 0x00008110, 0x00000168 },
26615 - { 0x00008118, 0x000100aa },
26616 - { 0x0000811c, 0x00003210 },
26617 - { 0x00008120, 0x08f04800 },
26618 - { 0x00008124, 0x00000000 },
26619 - { 0x00008128, 0x00000000 },
26620 - { 0x0000812c, 0x00000000 },
26621 - { 0x00008130, 0x00000000 },
26622 - { 0x00008134, 0x00000000 },
26623 - { 0x00008138, 0x00000000 },
26624 - { 0x0000813c, 0x00000000 },
26625 - { 0x00008144, 0x00000000 },
26626 - { 0x00008168, 0x00000000 },
26627 - { 0x0000816c, 0x00000000 },
26628 - { 0x00008170, 0x32143320 },
26629 - { 0x00008174, 0xfaa4fa50 },
26630 - { 0x00008178, 0x00000100 },
26631 - { 0x0000817c, 0x00000000 },
26632 - { 0x000081c4, 0x00000000 },
26633 - { 0x000081d0, 0x00003210 },
26634 - { 0x000081ec, 0x00000000 },
26635 - { 0x000081f0, 0x00000000 },
26636 - { 0x000081f4, 0x00000000 },
26637 - { 0x000081f8, 0x00000000 },
26638 - { 0x000081fc, 0x00000000 },
26639 - { 0x00008200, 0x00000000 },
26640 - { 0x00008204, 0x00000000 },
26641 - { 0x00008208, 0x00000000 },
26642 - { 0x0000820c, 0x00000000 },
26643 - { 0x00008210, 0x00000000 },
26644 - { 0x00008214, 0x00000000 },
26645 - { 0x00008218, 0x00000000 },
26646 - { 0x0000821c, 0x00000000 },
26647 - { 0x00008220, 0x00000000 },
26648 - { 0x00008224, 0x00000000 },
26649 - { 0x00008228, 0x00000000 },
26650 - { 0x0000822c, 0x00000000 },
26651 - { 0x00008230, 0x00000000 },
26652 - { 0x00008234, 0x00000000 },
26653 - { 0x00008238, 0x00000000 },
26654 - { 0x0000823c, 0x00000000 },
26655 - { 0x00008240, 0x00100000 },
26656 - { 0x00008244, 0x0010f400 },
26657 - { 0x00008248, 0x00000100 },
26658 - { 0x0000824c, 0x0001e800 },
26659 - { 0x00008250, 0x00000000 },
26660 - { 0x00008254, 0x00000000 },
26661 - { 0x00008258, 0x00000000 },
26662 - { 0x0000825c, 0x400000ff },
26663 - { 0x00008260, 0x00080922 },
26664 - { 0x00008270, 0x00000000 },
26665 - { 0x00008274, 0x40000000 },
26666 - { 0x00008278, 0x003e4180 },
26667 - { 0x0000827c, 0x00000000 },
26668 - { 0x00008284, 0x0000002c },
26669 - { 0x00008288, 0x0000002c },
26670 - { 0x0000828c, 0x00000000 },
26671 - { 0x00008294, 0x00000000 },
26672 - { 0x00008298, 0x00000000 },
26673 - { 0x00008300, 0x00000000 },
26674 - { 0x00008304, 0x00000000 },
26675 - { 0x00008308, 0x00000000 },
26676 - { 0x0000830c, 0x00000000 },
26677 - { 0x00008310, 0x00000000 },
26678 - { 0x00008314, 0x00000000 },
26679 - { 0x00008318, 0x00000000 },
26680 - { 0x00008328, 0x00000000 },
26681 - { 0x0000832c, 0x00000007 },
26682 - { 0x00008330, 0x00000302 },
26683 - { 0x00008334, 0x00000e00 },
26684 - { 0x00008338, 0x00000000 },
26685 - { 0x0000833c, 0x00000000 },
26686 - { 0x00008340, 0x000107ff },
26687 - { 0x00008344, 0x00000000 },
26688 - { 0x00009808, 0x00000000 },
26689 - { 0x0000980c, 0xaf268e30 },
26690 - { 0x00009810, 0xfd14e000 },
26691 - { 0x00009814, 0x9c0a9f6b },
26692 - { 0x0000981c, 0x00000000 },
26693 - { 0x0000982c, 0x0000a000 },
26694 - { 0x00009830, 0x00000000 },
26695 - { 0x0000983c, 0x00200400 },
26696 - { 0x00009840, 0x206a01ae },
26697 - { 0x0000984c, 0x0040233c },
26698 - { 0x0000a84c, 0x0040233c },
26699 - { 0x00009854, 0x00000044 },
26700 - { 0x00009900, 0x00000000 },
26701 - { 0x00009904, 0x00000000 },
26702 - { 0x00009908, 0x00000000 },
26703 - { 0x0000990c, 0x00000000 },
26704 - { 0x0000991c, 0x10000fff },
26705 - { 0x00009920, 0x04900000 },
26706 - { 0x0000a920, 0x04900000 },
26707 - { 0x00009928, 0x00000001 },
26708 - { 0x0000992c, 0x00000004 },
26709 - { 0x00009934, 0x1e1f2022 },
26710 - { 0x00009938, 0x0a0b0c0d },
26711 - { 0x0000993c, 0x00000000 },
26712 - { 0x00009948, 0x9280c00a },
26713 - { 0x0000994c, 0x00020028 },
26714 - { 0x00009954, 0xe250a51e },
26715 - { 0x00009958, 0x3388ffff },
26716 - { 0x00009940, 0x00781204 },
26717 - { 0x0000c95c, 0x004b6a8e },
26718 - { 0x0000c968, 0x000003ce },
26719 - { 0x00009970, 0x190fb514 },
26720 - { 0x00009974, 0x00000000 },
26721 - { 0x00009978, 0x00000001 },
26722 - { 0x0000997c, 0x00000000 },
26723 - { 0x00009980, 0x00000000 },
26724 - { 0x00009984, 0x00000000 },
26725 - { 0x00009988, 0x00000000 },
26726 - { 0x0000998c, 0x00000000 },
26727 - { 0x00009990, 0x00000000 },
26728 - { 0x00009994, 0x00000000 },
26729 - { 0x00009998, 0x00000000 },
26730 - { 0x0000999c, 0x00000000 },
26731 - { 0x000099a0, 0x00000000 },
26732 - { 0x000099a4, 0x00000001 },
26733 - { 0x000099a8, 0x201fff00 },
26734 - { 0x000099ac, 0x006f00c4 },
26735 - { 0x000099b0, 0x03051000 },
26736 - { 0x000099b4, 0x00000820 },
26737 - { 0x000099dc, 0x00000000 },
26738 - { 0x000099e0, 0x00000000 },
26739 - { 0x000099e4, 0xaaaaaaaa },
26740 - { 0x000099e8, 0x3c466478 },
26741 - { 0x000099ec, 0x0cc80caa },
26742 - { 0x000099fc, 0x00001042 },
26743 - { 0x0000a210, 0x4080a333 },
26744 - { 0x0000a214, 0x40206c10 },
26745 - { 0x0000a218, 0x009c4060 },
26746 - { 0x0000a220, 0x01834061 },
26747 - { 0x0000a224, 0x00000400 },
26748 - { 0x0000a228, 0x000003b5 },
26749 - { 0x0000a22c, 0x23277200 },
26750 - { 0x0000a234, 0x20202020 },
26751 - { 0x0000a238, 0x20202020 },
26752 - { 0x0000a23c, 0x13c889af },
26753 - { 0x0000a240, 0x38490a20 },
26754 - { 0x0000a244, 0x00007bb6 },
26755 - { 0x0000a248, 0x0fff3ffc },
26756 - { 0x0000a24c, 0x00000001 },
26757 - { 0x0000a250, 0x001da000 },
26758 - { 0x0000a254, 0x00000000 },
26759 - { 0x0000a258, 0x0cdbd380 },
26760 - { 0x0000a25c, 0x0f0f0f01 },
26761 - { 0x0000a260, 0xdfa91f01 },
26762 - { 0x0000a268, 0x00000000 },
26763 - { 0x0000a26c, 0x0ebae9c6 },
26764 - { 0x0000b26c, 0x0ebae9c6 },
26765 - { 0x0000d270, 0x00820820 },
26766 - { 0x0000a278, 0x1ce739ce },
26767 - { 0x0000a27c, 0x050701ce },
26768 - { 0x0000a358, 0x7999aa0f },
26769 - { 0x0000d35c, 0x07ffffef },
26770 - { 0x0000d360, 0x0fffffe7 },
26771 - { 0x0000d364, 0x17ffffe5 },
26772 - { 0x0000d368, 0x1fffffe4 },
26773 - { 0x0000d36c, 0x37ffffe3 },
26774 - { 0x0000d370, 0x3fffffe3 },
26775 - { 0x0000d374, 0x57ffffe3 },
26776 - { 0x0000d378, 0x5fffffe2 },
26777 - { 0x0000d37c, 0x7fffffe2 },
26778 - { 0x0000d380, 0x7f3c7bba },
26779 - { 0x0000d384, 0xf3307ff0 },
26780 - { 0x0000a388, 0x0c000000 },
26781 - { 0x0000a38c, 0x20202020 },
26782 - { 0x0000a390, 0x20202020 },
26783 - { 0x0000a394, 0x1ce739ce },
26784 - { 0x0000a398, 0x000001ce },
26785 - { 0x0000a39c, 0x00000001 },
26786 - { 0x0000a3a0, 0x00000000 },
26787 - { 0x0000a3a4, 0x00000000 },
26788 - { 0x0000a3a8, 0x00000000 },
26789 - { 0x0000a3ac, 0x00000000 },
26790 - { 0x0000a3b0, 0x00000000 },
26791 - { 0x0000a3b4, 0x00000000 },
26792 - { 0x0000a3b8, 0x00000000 },
26793 - { 0x0000a3bc, 0x00000000 },
26794 - { 0x0000a3c0, 0x00000000 },
26795 - { 0x0000a3c4, 0x00000000 },
26796 - { 0x0000a3c8, 0x00000246 },
26797 - { 0x0000a3cc, 0x20202020 },
26798 - { 0x0000a3d0, 0x20202020 },
26799 - { 0x0000a3d4, 0x20202020 },
26800 - { 0x0000a3dc, 0x1ce739ce },
26801 - { 0x0000a3e0, 0x000001ce },
26802 - { 0x0000a3e4, 0x00000000 },
26803 - { 0x0000a3e8, 0x18c43433 },
26804 - { 0x0000a3ec, 0x00f38081 },
26805 - { 0x00007800, 0x00040000 },
26806 - { 0x00007804, 0xdb005012 },
26807 - { 0x00007808, 0x04924914 },
26808 - { 0x0000780c, 0x21084210 },
26809 - { 0x00007810, 0x6d801300 },
26810 - { 0x00007814, 0x0019beff },
26811 - { 0x00007818, 0x07e40000 },
26812 - { 0x0000781c, 0x00492000 },
26813 - { 0x00007820, 0x92492480 },
26814 - { 0x00007824, 0x00040000 },
26815 - { 0x00007828, 0xdb005012 },
26816 - { 0x0000782c, 0x04924914 },
26817 - { 0x00007830, 0x21084210 },
26818 - { 0x00007834, 0x6d801300 },
26819 - { 0x00007838, 0x0019beff },
26820 - { 0x0000783c, 0x07e40000 },
26821 - { 0x00007840, 0x00492000 },
26822 - { 0x00007844, 0x92492480 },
26823 - { 0x00007848, 0x00120000 },
26824 - { 0x00007850, 0x54214514 },
26825 - { 0x00007858, 0x92592692 },
26826 - { 0x00007860, 0x52802000 },
26827 - { 0x00007864, 0x0a8e370e },
26828 - { 0x00007868, 0xc0102850 },
26829 - { 0x0000786c, 0x812d4000 },
26830 - { 0x00007874, 0x001b6db0 },
26831 - { 0x00007878, 0x00376b63 },
26832 - { 0x0000787c, 0x06db6db6 },
26833 - { 0x00007880, 0x006d8000 },
26834 - { 0x00007884, 0xffeffffe },
26835 - { 0x00007888, 0xffeffffe },
26836 - { 0x00007890, 0x00060aeb },
26837 - { 0x00007894, 0x5a108000 },
26838 - { 0x00007898, 0x2a850160 },
26839 -};
26840 -
26841 -/* XXX 9280 2 */
26842 -static const u32 ar9280Modes_9280_2[][6] = {
26843 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
26844 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
26845 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
26846 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
26847 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26848 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
26849 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
26850 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
26851 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
26852 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
26853 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26854 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
26855 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
26856 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
26857 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
26858 - { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
26859 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
26860 - { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
26861 - { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
26862 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
26863 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
26864 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
26865 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
26866 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
26867 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
26868 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
26869 - { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
26870 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
26871 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26872 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
26873 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
26874 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
26875 - { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
26876 - { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
26877 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
26878 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
26879 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
26880 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
26881 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
26882 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26883 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26884 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
26885 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
26886 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
26887 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
26888 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
26889 - { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
26890 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
26891 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
26892 - { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
26893 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
26894 - { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
26895 -};
26896 -
26897 -static const u32 ar9280Common_9280_2[][2] = {
26898 - { 0x0000000c, 0x00000000 },
26899 - { 0x00000030, 0x00020015 },
26900 - { 0x00000034, 0x00000005 },
26901 - { 0x00000040, 0x00000000 },
26902 - { 0x00000044, 0x00000008 },
26903 - { 0x00000048, 0x00000008 },
26904 - { 0x0000004c, 0x00000010 },
26905 - { 0x00000050, 0x00000000 },
26906 - { 0x00000054, 0x0000001f },
26907 - { 0x00000800, 0x00000000 },
26908 - { 0x00000804, 0x00000000 },
26909 - { 0x00000808, 0x00000000 },
26910 - { 0x0000080c, 0x00000000 },
26911 - { 0x00000810, 0x00000000 },
26912 - { 0x00000814, 0x00000000 },
26913 - { 0x00000818, 0x00000000 },
26914 - { 0x0000081c, 0x00000000 },
26915 - { 0x00000820, 0x00000000 },
26916 - { 0x00000824, 0x00000000 },
26917 - { 0x00001040, 0x002ffc0f },
26918 - { 0x00001044, 0x002ffc0f },
26919 - { 0x00001048, 0x002ffc0f },
26920 - { 0x0000104c, 0x002ffc0f },
26921 - { 0x00001050, 0x002ffc0f },
26922 - { 0x00001054, 0x002ffc0f },
26923 - { 0x00001058, 0x002ffc0f },
26924 - { 0x0000105c, 0x002ffc0f },
26925 - { 0x00001060, 0x002ffc0f },
26926 - { 0x00001064, 0x002ffc0f },
26927 - { 0x00001230, 0x00000000 },
26928 - { 0x00001270, 0x00000000 },
26929 - { 0x00001038, 0x00000000 },
26930 - { 0x00001078, 0x00000000 },
26931 - { 0x000010b8, 0x00000000 },
26932 - { 0x000010f8, 0x00000000 },
26933 - { 0x00001138, 0x00000000 },
26934 - { 0x00001178, 0x00000000 },
26935 - { 0x000011b8, 0x00000000 },
26936 - { 0x000011f8, 0x00000000 },
26937 - { 0x00001238, 0x00000000 },
26938 - { 0x00001278, 0x00000000 },
26939 - { 0x000012b8, 0x00000000 },
26940 - { 0x000012f8, 0x00000000 },
26941 - { 0x00001338, 0x00000000 },
26942 - { 0x00001378, 0x00000000 },
26943 - { 0x000013b8, 0x00000000 },
26944 - { 0x000013f8, 0x00000000 },
26945 - { 0x00001438, 0x00000000 },
26946 - { 0x00001478, 0x00000000 },
26947 - { 0x000014b8, 0x00000000 },
26948 - { 0x000014f8, 0x00000000 },
26949 - { 0x00001538, 0x00000000 },
26950 - { 0x00001578, 0x00000000 },
26951 - { 0x000015b8, 0x00000000 },
26952 - { 0x000015f8, 0x00000000 },
26953 - { 0x00001638, 0x00000000 },
26954 - { 0x00001678, 0x00000000 },
26955 - { 0x000016b8, 0x00000000 },
26956 - { 0x000016f8, 0x00000000 },
26957 - { 0x00001738, 0x00000000 },
26958 - { 0x00001778, 0x00000000 },
26959 - { 0x000017b8, 0x00000000 },
26960 - { 0x000017f8, 0x00000000 },
26961 - { 0x0000103c, 0x00000000 },
26962 - { 0x0000107c, 0x00000000 },
26963 - { 0x000010bc, 0x00000000 },
26964 - { 0x000010fc, 0x00000000 },
26965 - { 0x0000113c, 0x00000000 },
26966 - { 0x0000117c, 0x00000000 },
26967 - { 0x000011bc, 0x00000000 },
26968 - { 0x000011fc, 0x00000000 },
26969 - { 0x0000123c, 0x00000000 },
26970 - { 0x0000127c, 0x00000000 },
26971 - { 0x000012bc, 0x00000000 },
26972 - { 0x000012fc, 0x00000000 },
26973 - { 0x0000133c, 0x00000000 },
26974 - { 0x0000137c, 0x00000000 },
26975 - { 0x000013bc, 0x00000000 },
26976 - { 0x000013fc, 0x00000000 },
26977 - { 0x0000143c, 0x00000000 },
26978 - { 0x0000147c, 0x00000000 },
26979 - { 0x00004030, 0x00000002 },
26980 - { 0x0000403c, 0x00000002 },
26981 - { 0x00004024, 0x0000001f },
26982 - { 0x00004060, 0x00000000 },
26983 - { 0x00004064, 0x00000000 },
26984 - { 0x00007010, 0x00000033 },
26985 - { 0x00007034, 0x00000002 },
26986 - { 0x00007038, 0x000004c2 },
26987 - { 0x00008004, 0x00000000 },
26988 - { 0x00008008, 0x00000000 },
26989 - { 0x0000800c, 0x00000000 },
26990 - { 0x00008018, 0x00000700 },
26991 - { 0x00008020, 0x00000000 },
26992 - { 0x00008038, 0x00000000 },
26993 - { 0x0000803c, 0x00000000 },
26994 - { 0x00008048, 0x40000000 },
26995 - { 0x00008054, 0x00000000 },
26996 - { 0x00008058, 0x00000000 },
26997 - { 0x0000805c, 0x000fc78f },
26998 - { 0x00008060, 0x0000000f },
26999 - { 0x00008064, 0x00000000 },
27000 - { 0x00008070, 0x00000000 },
27001 - { 0x000080c0, 0x2a80001a },
27002 - { 0x000080c4, 0x05dc01e0 },
27003 - { 0x000080c8, 0x1f402710 },
27004 - { 0x000080cc, 0x01f40000 },
27005 - { 0x000080d0, 0x00001e00 },
27006 - { 0x000080d4, 0x00000000 },
27007 - { 0x000080d8, 0x00400000 },
27008 - { 0x000080e0, 0xffffffff },
27009 - { 0x000080e4, 0x0000ffff },
27010 - { 0x000080e8, 0x003f3f3f },
27011 - { 0x000080ec, 0x00000000 },
27012 - { 0x000080f0, 0x00000000 },
27013 - { 0x000080f4, 0x00000000 },
27014 - { 0x000080f8, 0x00000000 },
27015 - { 0x000080fc, 0x00020000 },
27016 - { 0x00008100, 0x00020000 },
27017 - { 0x00008104, 0x00000001 },
27018 - { 0x00008108, 0x00000052 },
27019 - { 0x0000810c, 0x00000000 },
27020 - { 0x00008110, 0x00000168 },
27021 - { 0x00008118, 0x000100aa },
27022 - { 0x0000811c, 0x00003210 },
27023 - { 0x00008124, 0x00000000 },
27024 - { 0x00008128, 0x00000000 },
27025 - { 0x0000812c, 0x00000000 },
27026 - { 0x00008130, 0x00000000 },
27027 - { 0x00008134, 0x00000000 },
27028 - { 0x00008138, 0x00000000 },
27029 - { 0x0000813c, 0x00000000 },
27030 - { 0x00008144, 0xffffffff },
27031 - { 0x00008168, 0x00000000 },
27032 - { 0x0000816c, 0x00000000 },
27033 - { 0x00008170, 0x32143320 },
27034 - { 0x00008174, 0xfaa4fa50 },
27035 - { 0x00008178, 0x00000100 },
27036 - { 0x0000817c, 0x00000000 },
27037 - { 0x000081c0, 0x00000000 },
27038 - { 0x000081ec, 0x00000000 },
27039 - { 0x000081f0, 0x00000000 },
27040 - { 0x000081f4, 0x00000000 },
27041 - { 0x000081f8, 0x00000000 },
27042 - { 0x000081fc, 0x00000000 },
27043 - { 0x00008200, 0x00000000 },
27044 - { 0x00008204, 0x00000000 },
27045 - { 0x00008208, 0x00000000 },
27046 - { 0x0000820c, 0x00000000 },
27047 - { 0x00008210, 0x00000000 },
27048 - { 0x00008214, 0x00000000 },
27049 - { 0x00008218, 0x00000000 },
27050 - { 0x0000821c, 0x00000000 },
27051 - { 0x00008220, 0x00000000 },
27052 - { 0x00008224, 0x00000000 },
27053 - { 0x00008228, 0x00000000 },
27054 - { 0x0000822c, 0x00000000 },
27055 - { 0x00008230, 0x00000000 },
27056 - { 0x00008234, 0x00000000 },
27057 - { 0x00008238, 0x00000000 },
27058 - { 0x0000823c, 0x00000000 },
27059 - { 0x00008240, 0x00100000 },
27060 - { 0x00008244, 0x0010f400 },
27061 - { 0x00008248, 0x00000100 },
27062 - { 0x0000824c, 0x0001e800 },
27063 - { 0x00008250, 0x00000000 },
27064 - { 0x00008254, 0x00000000 },
27065 - { 0x00008258, 0x00000000 },
27066 - { 0x0000825c, 0x400000ff },
27067 - { 0x00008260, 0x00080922 },
27068 - { 0x00008264, 0xa8a00010 },
27069 - { 0x00008270, 0x00000000 },
27070 - { 0x00008274, 0x40000000 },
27071 - { 0x00008278, 0x003e4180 },
27072 - { 0x0000827c, 0x00000000 },
27073 - { 0x00008284, 0x0000002c },
27074 - { 0x00008288, 0x0000002c },
27075 - { 0x0000828c, 0x00000000 },
27076 - { 0x00008294, 0x00000000 },
27077 - { 0x00008298, 0x00000000 },
27078 - { 0x0000829c, 0x00000000 },
27079 - { 0x00008300, 0x00000040 },
27080 - { 0x00008314, 0x00000000 },
27081 - { 0x00008328, 0x00000000 },
27082 - { 0x0000832c, 0x00000007 },
27083 - { 0x00008330, 0x00000302 },
27084 - { 0x00008334, 0x00000e00 },
27085 - { 0x00008338, 0x00ff0000 },
27086 - { 0x0000833c, 0x00000000 },
27087 - { 0x00008340, 0x000107ff },
27088 - { 0x00008344, 0x00481043 },
27089 - { 0x00009808, 0x00000000 },
27090 - { 0x0000980c, 0xafa68e30 },
27091 - { 0x00009810, 0xfd14e000 },
27092 - { 0x00009814, 0x9c0a9f6b },
27093 - { 0x0000981c, 0x00000000 },
27094 - { 0x0000982c, 0x0000a000 },
27095 - { 0x00009830, 0x00000000 },
27096 - { 0x0000983c, 0x00200400 },
27097 - { 0x0000984c, 0x0040233c },
27098 - { 0x0000a84c, 0x0040233c },
27099 - { 0x00009854, 0x00000044 },
27100 - { 0x00009900, 0x00000000 },
27101 - { 0x00009904, 0x00000000 },
27102 - { 0x00009908, 0x00000000 },
27103 - { 0x0000990c, 0x00000000 },
27104 - { 0x00009910, 0x01002310 },
27105 - { 0x0000991c, 0x10000fff },
27106 - { 0x00009920, 0x04900000 },
27107 - { 0x0000a920, 0x04900000 },
27108 - { 0x00009928, 0x00000001 },
27109 - { 0x0000992c, 0x00000004 },
27110 - { 0x00009934, 0x1e1f2022 },
27111 - { 0x00009938, 0x0a0b0c0d },
27112 - { 0x0000993c, 0x00000000 },
27113 - { 0x00009948, 0x9280c00a },
27114 - { 0x0000994c, 0x00020028 },
27115 - { 0x00009954, 0x5f3ca3de },
27116 - { 0x00009958, 0x2108ecff },
27117 - { 0x00009940, 0x14750604 },
27118 - { 0x0000c95c, 0x004b6a8e },
27119 - { 0x00009970, 0x190fb515 },
27120 - { 0x00009974, 0x00000000 },
27121 - { 0x00009978, 0x00000001 },
27122 - { 0x0000997c, 0x00000000 },
27123 - { 0x00009980, 0x00000000 },
27124 - { 0x00009984, 0x00000000 },
27125 - { 0x00009988, 0x00000000 },
27126 - { 0x0000998c, 0x00000000 },
27127 - { 0x00009990, 0x00000000 },
27128 - { 0x00009994, 0x00000000 },
27129 - { 0x00009998, 0x00000000 },
27130 - { 0x0000999c, 0x00000000 },
27131 - { 0x000099a0, 0x00000000 },
27132 - { 0x000099a4, 0x00000001 },
27133 - { 0x000099a8, 0x201fff00 },
27134 - { 0x000099ac, 0x006f0000 },
27135 - { 0x000099b0, 0x03051000 },
27136 - { 0x000099b4, 0x00000820 },
27137 - { 0x000099dc, 0x00000000 },
27138 - { 0x000099e0, 0x00000000 },
27139 - { 0x000099e4, 0xaaaaaaaa },
27140 - { 0x000099e8, 0x3c466478 },
27141 - { 0x000099ec, 0x0cc80caa },
27142 - { 0x000099f0, 0x00000000 },
27143 - { 0x000099fc, 0x00001042 },
27144 - { 0x0000a208, 0x803e4788 },
27145 - { 0x0000a210, 0x4080a333 },
27146 - { 0x0000a214, 0x40206c10 },
27147 - { 0x0000a218, 0x009c4060 },
27148 - { 0x0000a220, 0x01834061 },
27149 - { 0x0000a224, 0x00000400 },
27150 - { 0x0000a228, 0x000003b5 },
27151 - { 0x0000a22c, 0x233f7180 },
27152 - { 0x0000a234, 0x20202020 },
27153 - { 0x0000a238, 0x20202020 },
27154 - { 0x0000a240, 0x38490a20 },
27155 - { 0x0000a244, 0x00007bb6 },
27156 - { 0x0000a248, 0x0fff3ffc },
27157 - { 0x0000a24c, 0x00000000 },
27158 - { 0x0000a254, 0x00000000 },
27159 - { 0x0000a258, 0x0cdbd380 },
27160 - { 0x0000a25c, 0x0f0f0f01 },
27161 - { 0x0000a260, 0xdfa91f01 },
27162 - { 0x0000a268, 0x00000000 },
27163 - { 0x0000a26c, 0x0e79e5c6 },
27164 - { 0x0000b26c, 0x0e79e5c6 },
27165 - { 0x0000d270, 0x00820820 },
27166 - { 0x0000a278, 0x1ce739ce },
27167 - { 0x0000d35c, 0x07ffffef },
27168 - { 0x0000d360, 0x0fffffe7 },
27169 - { 0x0000d364, 0x17ffffe5 },
27170 - { 0x0000d368, 0x1fffffe4 },
27171 - { 0x0000d36c, 0x37ffffe3 },
27172 - { 0x0000d370, 0x3fffffe3 },
27173 - { 0x0000d374, 0x57ffffe3 },
27174 - { 0x0000d378, 0x5fffffe2 },
27175 - { 0x0000d37c, 0x7fffffe2 },
27176 - { 0x0000d380, 0x7f3c7bba },
27177 - { 0x0000d384, 0xf3307ff0 },
27178 - { 0x0000a38c, 0x20202020 },
27179 - { 0x0000a390, 0x20202020 },
27180 - { 0x0000a394, 0x1ce739ce },
27181 - { 0x0000a398, 0x000001ce },
27182 - { 0x0000a39c, 0x00000001 },
27183 - { 0x0000a3a0, 0x00000000 },
27184 - { 0x0000a3a4, 0x00000000 },
27185 - { 0x0000a3a8, 0x00000000 },
27186 - { 0x0000a3ac, 0x00000000 },
27187 - { 0x0000a3b0, 0x00000000 },
27188 - { 0x0000a3b4, 0x00000000 },
27189 - { 0x0000a3b8, 0x00000000 },
27190 - { 0x0000a3bc, 0x00000000 },
27191 - { 0x0000a3c0, 0x00000000 },
27192 - { 0x0000a3c4, 0x00000000 },
27193 - { 0x0000a3c8, 0x00000246 },
27194 - { 0x0000a3cc, 0x20202020 },
27195 - { 0x0000a3d0, 0x20202020 },
27196 - { 0x0000a3d4, 0x20202020 },
27197 - { 0x0000a3dc, 0x1ce739ce },
27198 - { 0x0000a3e0, 0x000001ce },
27199 - { 0x0000a3e4, 0x00000000 },
27200 - { 0x0000a3e8, 0x18c43433 },
27201 - { 0x0000a3ec, 0x00f70081 },
27202 - { 0x00007800, 0x00040000 },
27203 - { 0x00007804, 0xdb005012 },
27204 - { 0x00007808, 0x04924914 },
27205 - { 0x0000780c, 0x21084210 },
27206 - { 0x00007810, 0x6d801300 },
27207 - { 0x00007818, 0x07e41000 },
27208 - { 0x00007824, 0x00040000 },
27209 - { 0x00007828, 0xdb005012 },
27210 - { 0x0000782c, 0x04924914 },
27211 - { 0x00007830, 0x21084210 },
27212 - { 0x00007834, 0x6d801300 },
27213 - { 0x0000783c, 0x07e40000 },
27214 - { 0x00007848, 0x00100000 },
27215 - { 0x0000784c, 0x773f0567 },
27216 - { 0x00007850, 0x54214514 },
27217 - { 0x00007854, 0x12035828 },
27218 - { 0x00007858, 0x9259269a },
27219 - { 0x00007860, 0x52802000 },
27220 - { 0x00007864, 0x0a8e370e },
27221 - { 0x00007868, 0xc0102850 },
27222 - { 0x0000786c, 0x812d4000 },
27223 - { 0x00007870, 0x807ec400 },
27224 - { 0x00007874, 0x001b6db0 },
27225 - { 0x00007878, 0x00376b63 },
27226 - { 0x0000787c, 0x06db6db6 },
27227 - { 0x00007880, 0x006d8000 },
27228 - { 0x00007884, 0xffeffffe },
27229 - { 0x00007888, 0xffeffffe },
27230 - { 0x0000788c, 0x00010000 },
27231 - { 0x00007890, 0x02060aeb },
27232 - { 0x00007898, 0x2a850160 },
27233 -};
27234 -
27235 -static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
27236 - { 0x00001030, 0x00000268, 0x000004d0 },
27237 - { 0x00001070, 0x0000018c, 0x00000318 },
27238 - { 0x000010b0, 0x00000fd0, 0x00001fa0 },
27239 - { 0x00008014, 0x044c044c, 0x08980898 },
27240 - { 0x0000801c, 0x148ec02b, 0x148ec057 },
27241 - { 0x00008318, 0x000044c0, 0x00008980 },
27242 - { 0x00009820, 0x02020200, 0x02020200 },
27243 - { 0x00009824, 0x01000f0f, 0x01000f0f },
27244 - { 0x00009828, 0x0b020001, 0x0b020001 },
27245 - { 0x00009834, 0x00000f0f, 0x00000f0f },
27246 - { 0x00009844, 0x03721821, 0x03721821 },
27247 - { 0x00009914, 0x00000898, 0x00001130 },
27248 - { 0x00009918, 0x0000000b, 0x00000016 },
27249 -};
27250 -
27251 -static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
27252 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27253 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27254 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27255 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27256 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27257 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27258 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27259 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27260 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27261 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27262 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27263 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27264 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27265 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27266 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27267 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27268 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27269 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27270 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27271 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27272 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27273 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27274 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27275 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27276 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27277 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27278 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27279 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27280 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27281 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27282 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27283 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27284 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27285 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27286 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27287 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27288 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27289 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27290 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27291 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27292 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27293 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27294 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27295 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27296 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27297 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27298 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27299 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27300 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
27301 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
27302 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
27303 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
27304 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
27305 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
27306 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
27307 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
27308 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
27309 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
27310 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
27311 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
27312 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
27313 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
27314 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
27315 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
27316 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
27317 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
27318 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
27319 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
27320 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
27321 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
27322 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
27323 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
27324 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
27325 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
27326 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
27327 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
27328 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
27329 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
27330 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
27331 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
27332 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27333 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27334 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27335 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27336 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27337 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27338 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27339 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27340 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27341 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27342 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27343 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27344 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27345 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27346 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27347 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27348 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27349 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27350 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27351 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27352 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27353 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27354 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27355 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27356 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27357 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27358 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27359 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27360 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27361 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27362 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27363 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27364 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27365 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27366 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27367 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27368 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27369 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27370 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27371 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27372 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27373 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27374 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27375 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27376 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27377 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27378 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27379 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
27380 - { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
27381 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
27382 -};
27383 -
27384 -static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
27385 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27386 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27387 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27388 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27389 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27390 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27391 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27392 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27393 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27394 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27395 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27396 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27397 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27398 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27399 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27400 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27401 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27402 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27403 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27404 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27405 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27406 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27407 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27408 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27409 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27410 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27411 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27412 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27413 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27414 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27415 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27416 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27417 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27418 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27419 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27420 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27421 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27422 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27423 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27424 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27425 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27426 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27427 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27428 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27429 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27430 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27431 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27432 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27433 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
27434 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
27435 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
27436 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
27437 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
27438 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
27439 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
27440 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
27441 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
27442 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
27443 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
27444 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
27445 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
27446 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
27447 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
27448 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
27449 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
27450 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
27451 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
27452 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
27453 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
27454 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
27455 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
27456 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
27457 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
27458 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
27459 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
27460 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
27461 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
27462 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
27463 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
27464 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
27465 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
27466 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
27467 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
27468 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
27469 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
27470 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
27471 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
27472 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
27473 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
27474 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
27475 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
27476 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
27477 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
27478 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
27479 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
27480 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
27481 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
27482 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
27483 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
27484 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
27485 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
27486 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
27487 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27488 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27489 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27490 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27491 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27492 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27493 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27494 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27495 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27496 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27497 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27498 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27499 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27500 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27501 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27502 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27503 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27504 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27505 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27506 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27507 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27508 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27509 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27510 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27511 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27512 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
27513 - { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
27514 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
27515 -};
27516 -
27517 -static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
27518 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
27519 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
27520 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
27521 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
27522 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
27523 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
27524 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
27525 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
27526 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
27527 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
27528 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
27529 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
27530 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
27531 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
27532 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
27533 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
27534 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
27535 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
27536 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
27537 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
27538 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
27539 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
27540 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
27541 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
27542 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
27543 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
27544 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
27545 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
27546 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
27547 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
27548 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
27549 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
27550 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
27551 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
27552 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
27553 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
27554 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
27555 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
27556 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
27557 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
27558 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
27559 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
27560 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
27561 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
27562 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
27563 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
27564 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
27565 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
27566 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
27567 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
27568 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
27569 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
27570 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
27571 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
27572 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
27573 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
27574 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
27575 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
27576 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
27577 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
27578 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
27579 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
27580 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
27581 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
27582 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
27583 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
27584 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
27585 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
27586 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
27587 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
27588 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
27589 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
27590 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
27591 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
27592 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
27593 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
27594 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
27595 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
27596 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
27597 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
27598 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
27599 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
27600 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
27601 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
27602 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
27603 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
27604 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
27605 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
27606 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
27607 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
27608 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
27609 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
27610 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
27611 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
27612 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
27613 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
27614 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
27615 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
27616 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
27617 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
27618 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
27619 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
27620 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27621 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27622 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27623 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27624 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27625 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27626 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27627 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27628 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27629 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27630 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27631 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27632 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27633 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27634 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27635 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27636 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27637 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27638 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27639 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27640 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27641 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27642 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27643 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27644 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27645 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
27646 - { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
27647 - { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
27648 -};
27649 -
27650 -static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
27651 - { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
27652 - { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
27653 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27654 - { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
27655 - { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
27656 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
27657 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
27658 - { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
27659 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
27660 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
27661 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
27662 - { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
27663 - { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
27664 - { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
27665 - { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
27666 - { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
27667 - { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
27668 - { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
27669 - { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
27670 - { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
27671 - { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
27672 - { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
27673 - { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
27674 - { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
27675 - { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
27676 - { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
27677 - { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
27678 - { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
27679 - { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
27680 - { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
27681 -};
27682 -
27683 -static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
27684 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
27685 - { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
27686 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27687 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
27688 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
27689 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
27690 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
27691 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
27692 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
27693 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
27694 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
27695 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
27696 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
27697 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
27698 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
27699 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
27700 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
27701 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
27702 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
27703 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
27704 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
27705 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
27706 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
27707 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
27708 - { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
27709 - { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
27710 - { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
27711 - { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
27712 - { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
27713 - { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
27714 -};
27715 -
27716 -static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
27717 - {0x00004040, 0x9248fd00 },
27718 - {0x00004040, 0x24924924 },
27719 - {0x00004040, 0xa8000019 },
27720 - {0x00004040, 0x13160820 },
27721 - {0x00004040, 0xe5980560 },
27722 - {0x00004040, 0xc01dcffc },
27723 - {0x00004040, 0x1aaabe41 },
27724 - {0x00004040, 0xbe105554 },
27725 - {0x00004040, 0x00043007 },
27726 - {0x00004044, 0x00000000 },
27727 -};
27728 -
27729 -static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
27730 - {0x00004040, 0x9248fd00 },
27731 - {0x00004040, 0x24924924 },
27732 - {0x00004040, 0xa8000019 },
27733 - {0x00004040, 0x13160820 },
27734 - {0x00004040, 0xe5980560 },
27735 - {0x00004040, 0xc01dcffd },
27736 - {0x00004040, 0x1aaabe41 },
27737 - {0x00004040, 0xbe105554 },
27738 - {0x00004040, 0x00043007 },
27739 - {0x00004044, 0x00000000 },
27740 -};
27741 -
27742 -/* AR9285 Revsion 10*/
27743 -static const u_int32_t ar9285Modes_9285[][6] = {
27744 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
27745 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
27746 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27747 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
27748 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27749 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
27750 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
27751 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27752 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27753 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27754 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27755 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27756 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27757 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
27758 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
27759 - { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
27760 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
27761 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
27762 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
27763 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
27764 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27765 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
27766 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
27767 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
27768 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
27769 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
27770 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
27771 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27772 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27773 - { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
27774 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
27775 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
27776 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27777 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
27778 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27779 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27780 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27781 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27782 - { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
27783 - { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
27784 - { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
27785 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
27786 - { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
27787 - { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
27788 - { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
27789 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27790 - { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
27791 - { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
27792 - { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
27793 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
27794 - { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
27795 - { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
27796 - { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
27797 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
27798 - { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
27799 - { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
27800 - { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
27801 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
27802 - { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
27803 - { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
27804 - { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
27805 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
27806 - { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
27807 - { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
27808 - { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
27809 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
27810 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
27811 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
27812 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
27813 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
27814 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
27815 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
27816 - { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
27817 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
27818 - { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
27819 - { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
27820 - { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
27821 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
27822 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
27823 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
27824 - { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
27825 - { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
27826 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27827 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
27828 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
27829 - { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
27830 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
27831 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
27832 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
27833 - { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
27834 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
27835 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
27836 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
27837 - { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
27838 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
27839 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
27840 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
27841 - { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
27842 - { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
27843 - { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
27844 - { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
27845 - { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
27846 - { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
27847 - { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
27848 - { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
27849 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
27850 - { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
27851 - { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
27852 - { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
27853 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
27854 - { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
27855 - { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
27856 - { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
27857 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
27858 - { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
27859 - { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
27860 - { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
27861 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
27862 - { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
27863 - { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
27864 - { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
27865 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
27866 - { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
27867 - { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
27868 - { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
27869 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
27870 - { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
27871 - { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27872 - { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27873 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27874 - { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27875 - { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27876 - { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27877 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27878 - { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27879 - { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27880 - { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27881 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27882 - { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27883 - { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27884 - { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27885 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27886 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27887 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27888 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27889 - { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27890 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27891 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27892 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27893 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27894 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27895 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27896 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27897 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27898 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27899 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27900 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27901 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27902 - { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27903 - { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27904 - { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27905 - { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27906 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27907 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27908 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27909 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
27910 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
27911 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
27912 - { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
27913 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
27914 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
27915 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
27916 - { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
27917 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
27918 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
27919 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27920 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
27921 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
27922 - { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
27923 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
27924 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
27925 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
27926 - { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
27927 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
27928 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
27929 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
27930 - { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
27931 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
27932 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
27933 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
27934 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
27935 - { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
27936 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
27937 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
27938 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
27939 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
27940 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
27941 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
27942 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
27943 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
27944 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
27945 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
27946 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
27947 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
27948 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
27949 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
27950 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
27951 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
27952 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
27953 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
27954 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
27955 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27956 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
27957 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
27958 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
27959 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
27960 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
27961 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
27962 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
27963 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
27964 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
27965 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
27966 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
27967 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
27968 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
27969 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
27970 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
27971 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
27972 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
27973 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
27974 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
27975 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
27976 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
27977 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
27978 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
27979 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
27980 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
27981 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
27982 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
27983 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
27984 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
27985 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
27986 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
27987 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
27988 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
27989 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
27990 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
27991 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
27992 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
27993 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
27994 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
27995 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
27996 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
27997 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
27998 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
27999 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28000 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28001 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28002 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28003 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28004 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28005 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28006 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28007 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28008 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28009 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28010 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28011 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28012 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28013 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28014 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28015 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28016 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28017 - { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28018 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28019 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28020 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28021 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28022 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28023 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28024 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28025 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28026 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28027 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28028 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28029 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28030 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28031 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28032 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28033 - { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28034 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28035 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28036 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28037 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
28038 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
28039 - { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
28040 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
28041 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
28042 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
28043 - { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
28044 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28045 - { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
28046 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
28047 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
28048 - { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
28049 - { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
28050 - { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
28051 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
28052 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
28053 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
28054 - { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
28055 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
28056 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
28057 - { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
28058 - { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
28059 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
28060 - { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
28061 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
28062 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
28063 -};
28064 -
28065 -static const u_int32_t ar9285Common_9285[][2] = {
28066 - { 0x0000000c, 0x00000000 },
28067 - { 0x00000030, 0x00020045 },
28068 - { 0x00000034, 0x00000005 },
28069 - { 0x00000040, 0x00000000 },
28070 - { 0x00000044, 0x00000008 },
28071 - { 0x00000048, 0x00000008 },
28072 - { 0x0000004c, 0x00000010 },
28073 - { 0x00000050, 0x00000000 },
28074 - { 0x00000054, 0x0000001f },
28075 - { 0x00000800, 0x00000000 },
28076 - { 0x00000804, 0x00000000 },
28077 - { 0x00000808, 0x00000000 },
28078 - { 0x0000080c, 0x00000000 },
28079 - { 0x00000810, 0x00000000 },
28080 - { 0x00000814, 0x00000000 },
28081 - { 0x00000818, 0x00000000 },
28082 - { 0x0000081c, 0x00000000 },
28083 - { 0x00000820, 0x00000000 },
28084 - { 0x00000824, 0x00000000 },
28085 - { 0x00001040, 0x002ffc0f },
28086 - { 0x00001044, 0x002ffc0f },
28087 - { 0x00001048, 0x002ffc0f },
28088 - { 0x0000104c, 0x002ffc0f },
28089 - { 0x00001050, 0x002ffc0f },
28090 - { 0x00001054, 0x002ffc0f },
28091 - { 0x00001058, 0x002ffc0f },
28092 - { 0x0000105c, 0x002ffc0f },
28093 - { 0x00001060, 0x002ffc0f },
28094 - { 0x00001064, 0x002ffc0f },
28095 - { 0x00001230, 0x00000000 },
28096 - { 0x00001270, 0x00000000 },
28097 - { 0x00001038, 0x00000000 },
28098 - { 0x00001078, 0x00000000 },
28099 - { 0x000010b8, 0x00000000 },
28100 - { 0x000010f8, 0x00000000 },
28101 - { 0x00001138, 0x00000000 },
28102 - { 0x00001178, 0x00000000 },
28103 - { 0x000011b8, 0x00000000 },
28104 - { 0x000011f8, 0x00000000 },
28105 - { 0x00001238, 0x00000000 },
28106 - { 0x00001278, 0x00000000 },
28107 - { 0x000012b8, 0x00000000 },
28108 - { 0x000012f8, 0x00000000 },
28109 - { 0x00001338, 0x00000000 },
28110 - { 0x00001378, 0x00000000 },
28111 - { 0x000013b8, 0x00000000 },
28112 - { 0x000013f8, 0x00000000 },
28113 - { 0x00001438, 0x00000000 },
28114 - { 0x00001478, 0x00000000 },
28115 - { 0x000014b8, 0x00000000 },
28116 - { 0x000014f8, 0x00000000 },
28117 - { 0x00001538, 0x00000000 },
28118 - { 0x00001578, 0x00000000 },
28119 - { 0x000015b8, 0x00000000 },
28120 - { 0x000015f8, 0x00000000 },
28121 - { 0x00001638, 0x00000000 },
28122 - { 0x00001678, 0x00000000 },
28123 - { 0x000016b8, 0x00000000 },
28124 - { 0x000016f8, 0x00000000 },
28125 - { 0x00001738, 0x00000000 },
28126 - { 0x00001778, 0x00000000 },
28127 - { 0x000017b8, 0x00000000 },
28128 - { 0x000017f8, 0x00000000 },
28129 - { 0x0000103c, 0x00000000 },
28130 - { 0x0000107c, 0x00000000 },
28131 - { 0x000010bc, 0x00000000 },
28132 - { 0x000010fc, 0x00000000 },
28133 - { 0x0000113c, 0x00000000 },
28134 - { 0x0000117c, 0x00000000 },
28135 - { 0x000011bc, 0x00000000 },
28136 - { 0x000011fc, 0x00000000 },
28137 - { 0x0000123c, 0x00000000 },
28138 - { 0x0000127c, 0x00000000 },
28139 - { 0x000012bc, 0x00000000 },
28140 - { 0x000012fc, 0x00000000 },
28141 - { 0x0000133c, 0x00000000 },
28142 - { 0x0000137c, 0x00000000 },
28143 - { 0x000013bc, 0x00000000 },
28144 - { 0x000013fc, 0x00000000 },
28145 - { 0x0000143c, 0x00000000 },
28146 - { 0x0000147c, 0x00000000 },
28147 - { 0x00004030, 0x00000002 },
28148 - { 0x0000403c, 0x00000002 },
28149 - { 0x00004024, 0x0000001f },
28150 - { 0x00004060, 0x00000000 },
28151 - { 0x00004064, 0x00000000 },
28152 - { 0x00007010, 0x00000031 },
28153 - { 0x00007034, 0x00000002 },
28154 - { 0x00007038, 0x000004c2 },
28155 - { 0x00008004, 0x00000000 },
28156 - { 0x00008008, 0x00000000 },
28157 - { 0x0000800c, 0x00000000 },
28158 - { 0x00008018, 0x00000700 },
28159 - { 0x00008020, 0x00000000 },
28160 - { 0x00008038, 0x00000000 },
28161 - { 0x0000803c, 0x00000000 },
28162 - { 0x00008048, 0x00000000 },
28163 - { 0x00008054, 0x00000000 },
28164 - { 0x00008058, 0x00000000 },
28165 - { 0x0000805c, 0x000fc78f },
28166 - { 0x00008060, 0x0000000f },
28167 - { 0x00008064, 0x00000000 },
28168 - { 0x00008070, 0x00000000 },
28169 - { 0x000080c0, 0x2a80001a },
28170 - { 0x000080c4, 0x05dc01e0 },
28171 - { 0x000080c8, 0x1f402710 },
28172 - { 0x000080cc, 0x01f40000 },
28173 - { 0x000080d0, 0x00001e00 },
28174 - { 0x000080d4, 0x00000000 },
28175 - { 0x000080d8, 0x00400000 },
28176 - { 0x000080e0, 0xffffffff },
28177 - { 0x000080e4, 0x0000ffff },
28178 - { 0x000080e8, 0x003f3f3f },
28179 - { 0x000080ec, 0x00000000 },
28180 - { 0x000080f0, 0x00000000 },
28181 - { 0x000080f4, 0x00000000 },
28182 - { 0x000080f8, 0x00000000 },
28183 - { 0x000080fc, 0x00020000 },
28184 - { 0x00008100, 0x00020000 },
28185 - { 0x00008104, 0x00000001 },
28186 - { 0x00008108, 0x00000052 },
28187 - { 0x0000810c, 0x00000000 },
28188 - { 0x00008110, 0x00000168 },
28189 - { 0x00008118, 0x000100aa },
28190 - { 0x0000811c, 0x00003210 },
28191 - { 0x00008120, 0x08f04800 },
28192 - { 0x00008124, 0x00000000 },
28193 - { 0x00008128, 0x00000000 },
28194 - { 0x0000812c, 0x00000000 },
28195 - { 0x00008130, 0x00000000 },
28196 - { 0x00008134, 0x00000000 },
28197 - { 0x00008138, 0x00000000 },
28198 - { 0x0000813c, 0x00000000 },
28199 - { 0x00008144, 0x00000000 },
28200 - { 0x00008168, 0x00000000 },
28201 - { 0x0000816c, 0x00000000 },
28202 - { 0x00008170, 0x32143320 },
28203 - { 0x00008174, 0xfaa4fa50 },
28204 - { 0x00008178, 0x00000100 },
28205 - { 0x0000817c, 0x00000000 },
28206 - { 0x000081c0, 0x00000000 },
28207 - { 0x000081d0, 0x00003210 },
28208 - { 0x000081ec, 0x00000000 },
28209 - { 0x000081f0, 0x00000000 },
28210 - { 0x000081f4, 0x00000000 },
28211 - { 0x000081f8, 0x00000000 },
28212 - { 0x000081fc, 0x00000000 },
28213 - { 0x00008200, 0x00000000 },
28214 - { 0x00008204, 0x00000000 },
28215 - { 0x00008208, 0x00000000 },
28216 - { 0x0000820c, 0x00000000 },
28217 - { 0x00008210, 0x00000000 },
28218 - { 0x00008214, 0x00000000 },
28219 - { 0x00008218, 0x00000000 },
28220 - { 0x0000821c, 0x00000000 },
28221 - { 0x00008220, 0x00000000 },
28222 - { 0x00008224, 0x00000000 },
28223 - { 0x00008228, 0x00000000 },
28224 - { 0x0000822c, 0x00000000 },
28225 - { 0x00008230, 0x00000000 },
28226 - { 0x00008234, 0x00000000 },
28227 - { 0x00008238, 0x00000000 },
28228 - { 0x0000823c, 0x00000000 },
28229 - { 0x00008240, 0x00100000 },
28230 - { 0x00008244, 0x0010f400 },
28231 - { 0x00008248, 0x00000100 },
28232 - { 0x0000824c, 0x0001e800 },
28233 - { 0x00008250, 0x00000000 },
28234 - { 0x00008254, 0x00000000 },
28235 - { 0x00008258, 0x00000000 },
28236 - { 0x0000825c, 0x400000ff },
28237 - { 0x00008260, 0x00080922 },
28238 - { 0x00008264, 0xa8a00010 },
28239 - { 0x00008270, 0x00000000 },
28240 - { 0x00008274, 0x40000000 },
28241 - { 0x00008278, 0x003e4180 },
28242 - { 0x0000827c, 0x00000000 },
28243 - { 0x00008284, 0x0000002c },
28244 - { 0x00008288, 0x0000002c },
28245 - { 0x0000828c, 0x00000000 },
28246 - { 0x00008294, 0x00000000 },
28247 - { 0x00008298, 0x00000000 },
28248 - { 0x0000829c, 0x00000000 },
28249 - { 0x00008300, 0x00000040 },
28250 - { 0x00008314, 0x00000000 },
28251 - { 0x00008328, 0x00000000 },
28252 - { 0x0000832c, 0x00000001 },
28253 - { 0x00008330, 0x00000302 },
28254 - { 0x00008334, 0x00000e00 },
28255 - { 0x00008338, 0x00000000 },
28256 - { 0x0000833c, 0x00000000 },
28257 - { 0x00008340, 0x00010380 },
28258 - { 0x00008344, 0x00481043 },
28259 - { 0x00009808, 0x00000000 },
28260 - { 0x0000980c, 0xafe68e30 },
28261 - { 0x00009810, 0xfd14e000 },
28262 - { 0x00009814, 0x9c0a9f6b },
28263 - { 0x0000981c, 0x00000000 },
28264 - { 0x0000982c, 0x0000a000 },
28265 - { 0x00009830, 0x00000000 },
28266 - { 0x0000983c, 0x00200400 },
28267 - { 0x0000984c, 0x0040233c },
28268 - { 0x00009854, 0x00000044 },
28269 - { 0x00009900, 0x00000000 },
28270 - { 0x00009904, 0x00000000 },
28271 - { 0x00009908, 0x00000000 },
28272 - { 0x0000990c, 0x00000000 },
28273 - { 0x00009910, 0x01002310 },
28274 - { 0x0000991c, 0x10000fff },
28275 - { 0x00009920, 0x04900000 },
28276 - { 0x00009928, 0x00000001 },
28277 - { 0x0000992c, 0x00000004 },
28278 - { 0x00009934, 0x1e1f2022 },
28279 - { 0x00009938, 0x0a0b0c0d },
28280 - { 0x0000993c, 0x00000000 },
28281 - { 0x00009940, 0x14750604 },
28282 - { 0x00009948, 0x9280c00a },
28283 - { 0x0000994c, 0x00020028 },
28284 - { 0x00009954, 0x5f3ca3de },
28285 - { 0x00009958, 0x2108ecff },
28286 - { 0x00009968, 0x000003ce },
28287 - { 0x00009970, 0x1927b515 },
28288 - { 0x00009974, 0x00000000 },
28289 - { 0x00009978, 0x00000001 },
28290 - { 0x0000997c, 0x00000000 },
28291 - { 0x00009980, 0x00000000 },
28292 - { 0x00009984, 0x00000000 },
28293 - { 0x00009988, 0x00000000 },
28294 - { 0x0000998c, 0x00000000 },
28295 - { 0x00009990, 0x00000000 },
28296 - { 0x00009994, 0x00000000 },
28297 - { 0x00009998, 0x00000000 },
28298 - { 0x0000999c, 0x00000000 },
28299 - { 0x000099a0, 0x00000000 },
28300 - { 0x000099a4, 0x00000001 },
28301 - { 0x000099a8, 0x201fff00 },
28302 - { 0x000099ac, 0x2def0a00 },
28303 - { 0x000099b0, 0x03051000 },
28304 - { 0x000099b4, 0x00000820 },
28305 - { 0x000099dc, 0x00000000 },
28306 - { 0x000099e0, 0x00000000 },
28307 - { 0x000099e4, 0xaaaaaaaa },
28308 - { 0x000099e8, 0x3c466478 },
28309 - { 0x000099ec, 0x0cc80caa },
28310 - { 0x000099f0, 0x00000000 },
28311 - { 0x0000a208, 0x803e6788 },
28312 - { 0x0000a210, 0x4080a333 },
28313 - { 0x0000a214, 0x00206c10 },
28314 - { 0x0000a218, 0x009c4060 },
28315 - { 0x0000a220, 0x01834061 },
28316 - { 0x0000a224, 0x00000400 },
28317 - { 0x0000a228, 0x000003b5 },
28318 - { 0x0000a22c, 0x00000000 },
28319 - { 0x0000a234, 0x20202020 },
28320 - { 0x0000a238, 0x20202020 },
28321 - { 0x0000a244, 0x00000000 },
28322 - { 0x0000a248, 0xfffffffc },
28323 - { 0x0000a24c, 0x00000000 },
28324 - { 0x0000a254, 0x00000000 },
28325 - { 0x0000a258, 0x0ccb5380 },
28326 - { 0x0000a25c, 0x15151501 },
28327 - { 0x0000a260, 0xdfa90f01 },
28328 - { 0x0000a268, 0x00000000 },
28329 - { 0x0000a26c, 0x0ebae9e6 },
28330 - { 0x0000d270, 0x0d820820 },
28331 - { 0x0000a278, 0x39ce739c },
28332 - { 0x0000a27c, 0x050e039c },
28333 - { 0x0000d35c, 0x07ffffef },
28334 - { 0x0000d360, 0x0fffffe7 },
28335 - { 0x0000d364, 0x17ffffe5 },
28336 - { 0x0000d368, 0x1fffffe4 },
28337 - { 0x0000d36c, 0x37ffffe3 },
28338 - { 0x0000d370, 0x3fffffe3 },
28339 - { 0x0000d374, 0x57ffffe3 },
28340 - { 0x0000d378, 0x5fffffe2 },
28341 - { 0x0000d37c, 0x7fffffe2 },
28342 - { 0x0000d380, 0x7f3c7bba },
28343 - { 0x0000d384, 0xf3307ff0 },
28344 - { 0x0000a388, 0x0c000000 },
28345 - { 0x0000a38c, 0x20202020 },
28346 - { 0x0000a390, 0x20202020 },
28347 - { 0x0000a394, 0x39ce739c },
28348 - { 0x0000a398, 0x0000039c },
28349 - { 0x0000a39c, 0x00000001 },
28350 - { 0x0000a3a0, 0x00000000 },
28351 - { 0x0000a3a4, 0x00000000 },
28352 - { 0x0000a3a8, 0x00000000 },
28353 - { 0x0000a3ac, 0x00000000 },
28354 - { 0x0000a3b0, 0x00000000 },
28355 - { 0x0000a3b4, 0x00000000 },
28356 - { 0x0000a3b8, 0x00000000 },
28357 - { 0x0000a3bc, 0x00000000 },
28358 - { 0x0000a3c0, 0x00000000 },
28359 - { 0x0000a3c4, 0x00000000 },
28360 - { 0x0000a3cc, 0x20202020 },
28361 - { 0x0000a3d0, 0x20202020 },
28362 - { 0x0000a3d4, 0x20202020 },
28363 - { 0x0000a3dc, 0x39ce739c },
28364 - { 0x0000a3e0, 0x0000039c },
28365 - { 0x0000a3e4, 0x00000000 },
28366 - { 0x0000a3e8, 0x18c43433 },
28367 - { 0x0000a3ec, 0x00f70081 },
28368 - { 0x00007800, 0x00140000 },
28369 - { 0x00007804, 0x0e4548d8 },
28370 - { 0x00007808, 0x54214514 },
28371 - { 0x0000780c, 0x02025820 },
28372 - { 0x00007810, 0x71c0d388 },
28373 - { 0x00007814, 0x924934a8 },
28374 - { 0x0000781c, 0x00000000 },
28375 - { 0x00007820, 0x00000c04 },
28376 - { 0x00007824, 0x00d86fff },
28377 - { 0x00007828, 0x26d2491b },
28378 - { 0x0000782c, 0x6e36d97b },
28379 - { 0x00007830, 0xedb6d96c },
28380 - { 0x00007834, 0x71400086 },
28381 - { 0x00007838, 0xfac68800 },
28382 - { 0x0000783c, 0x0001fffe },
28383 - { 0x00007840, 0xffeb1a20 },
28384 - { 0x00007844, 0x000c0db6 },
28385 - { 0x00007848, 0x6db61b6f },
28386 - { 0x0000784c, 0x6d9b66db },
28387 - { 0x00007850, 0x6d8c6dba },
28388 - { 0x00007854, 0x00040000 },
28389 - { 0x00007858, 0xdb003012 },
28390 - { 0x0000785c, 0x04924914 },
28391 - { 0x00007860, 0x21084210 },
28392 - { 0x00007864, 0xf7d7ffde },
28393 - { 0x00007868, 0xc2034080 },
28394 - { 0x0000786c, 0x48609eb4 },
28395 - { 0x00007870, 0x10142c00 },
28396 -};
28397 -
28398 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
28399 - {0x00004040, 0x9248fd00 },
28400 - {0x00004040, 0x24924924 },
28401 - {0x00004040, 0xa8000019 },
28402 - {0x00004040, 0x13160820 },
28403 - {0x00004040, 0xe5980560 },
28404 - {0x00004040, 0xc01dcffd },
28405 - {0x00004040, 0x1aaabe41 },
28406 - {0x00004040, 0xbe105554 },
28407 - {0x00004040, 0x00043007 },
28408 - {0x00004044, 0x00000000 },
28409 -};
28410 -
28411 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
28412 - {0x00004040, 0x9248fd00 },
28413 - {0x00004040, 0x24924924 },
28414 - {0x00004040, 0xa8000019 },
28415 - {0x00004040, 0x13160820 },
28416 - {0x00004040, 0xe5980560 },
28417 - {0x00004040, 0xc01dcffc },
28418 - {0x00004040, 0x1aaabe41 },
28419 - {0x00004040, 0xbe105554 },
28420 - {0x00004040, 0x00043007 },
28421 - {0x00004044, 0x00000000 },
28422 -};
28423 -
28424 -/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
28425 -static const u_int32_t ar9285Modes_9285_1_2[][6] = {
28426 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
28427 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
28428 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
28429 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
28430 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
28431 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
28432 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
28433 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
28434 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28435 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28436 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
28437 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
28438 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28439 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
28440 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
28441 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
28442 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
28443 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
28444 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
28445 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
28446 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
28447 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
28448 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
28449 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
28450 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
28451 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
28452 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
28453 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
28454 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
28455 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28456 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28457 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
28458 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
28459 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
28460 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
28461 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
28462 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
28463 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
28464 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28465 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28466 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
28467 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
28468 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
28469 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
28470 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
28471 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
28472 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
28473 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
28474 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
28475 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
28476 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
28477 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
28478 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
28479 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
28480 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
28481 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
28482 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
28483 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
28484 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
28485 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
28486 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
28487 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
28488 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
28489 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
28490 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
28491 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
28492 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
28493 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
28494 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
28495 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
28496 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
28497 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
28498 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
28499 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
28500 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
28501 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
28502 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
28503 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
28504 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
28505 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
28506 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
28507 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
28508 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
28509 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
28510 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
28511 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
28512 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
28513 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
28514 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
28515 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
28516 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
28517 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
28518 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
28519 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
28520 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
28521 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
28522 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
28523 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
28524 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
28525 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
28526 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
28527 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
28528 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
28529 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
28530 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
28531 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
28532 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
28533 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
28534 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
28535 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
28536 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
28537 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
28538 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
28539 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
28540 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
28541 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
28542 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
28543 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
28544 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
28545 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
28546 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
28547 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
28548 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
28549 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
28550 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
28551 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
28552 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
28553 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
28554 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
28555 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28556 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28557 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28558 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28559 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28560 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28561 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28562 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28563 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28564 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28565 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28566 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28567 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28568 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28569 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28570 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28571 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28572 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28573 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28574 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28575 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28576 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28577 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28578 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28579 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28580 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28581 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28582 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28583 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28584 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28585 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28586 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28587 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28588 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28589 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28590 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28591 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28592 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28593 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28594 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
28595 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
28596 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
28597 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
28598 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
28599 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
28600 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
28601 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
28602 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
28603 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
28604 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
28605 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
28606 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
28607 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
28608 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
28609 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
28610 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
28611 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
28612 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
28613 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
28614 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
28615 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
28616 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
28617 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
28618 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
28619 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
28620 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
28621 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
28622 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
28623 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
28624 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
28625 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
28626 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
28627 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
28628 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
28629 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
28630 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
28631 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
28632 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
28633 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
28634 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
28635 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
28636 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
28637 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
28638 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
28639 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
28640 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
28641 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
28642 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
28643 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
28644 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
28645 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
28646 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
28647 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
28648 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
28649 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
28650 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
28651 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
28652 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
28653 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
28654 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
28655 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
28656 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
28657 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
28658 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
28659 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
28660 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
28661 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
28662 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
28663 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
28664 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
28665 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
28666 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
28667 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
28668 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
28669 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
28670 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
28671 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
28672 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
28673 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
28674 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
28675 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
28676 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
28677 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
28678 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
28679 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
28680 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
28681 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
28682 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
28683 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28684 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28685 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28686 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28687 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28688 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28689 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28690 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28691 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28692 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28693 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28694 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28695 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28696 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28697 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28698 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28699 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28700 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28701 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28702 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28703 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28704 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28705 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28706 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28707 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28708 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28709 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28710 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28711 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28712 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28713 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28714 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28715 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28716 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28717 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28718 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28719 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28720 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28721 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
28722 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
28723 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
28724 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
28725 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
28726 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
28727 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
28728 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
28729 -};
28730 -
28731 -static const u_int32_t ar9285Common_9285_1_2[][2] = {
28732 - { 0x0000000c, 0x00000000 },
28733 - { 0x00000030, 0x00020045 },
28734 - { 0x00000034, 0x00000005 },
28735 - { 0x00000040, 0x00000000 },
28736 - { 0x00000044, 0x00000008 },
28737 - { 0x00000048, 0x00000008 },
28738 - { 0x0000004c, 0x00000010 },
28739 - { 0x00000050, 0x00000000 },
28740 - { 0x00000054, 0x0000001f },
28741 - { 0x00000800, 0x00000000 },
28742 - { 0x00000804, 0x00000000 },
28743 - { 0x00000808, 0x00000000 },
28744 - { 0x0000080c, 0x00000000 },
28745 - { 0x00000810, 0x00000000 },
28746 - { 0x00000814, 0x00000000 },
28747 - { 0x00000818, 0x00000000 },
28748 - { 0x0000081c, 0x00000000 },
28749 - { 0x00000820, 0x00000000 },
28750 - { 0x00000824, 0x00000000 },
28751 - { 0x00001040, 0x002ffc0f },
28752 - { 0x00001044, 0x002ffc0f },
28753 - { 0x00001048, 0x002ffc0f },
28754 - { 0x0000104c, 0x002ffc0f },
28755 - { 0x00001050, 0x002ffc0f },
28756 - { 0x00001054, 0x002ffc0f },
28757 - { 0x00001058, 0x002ffc0f },
28758 - { 0x0000105c, 0x002ffc0f },
28759 - { 0x00001060, 0x002ffc0f },
28760 - { 0x00001064, 0x002ffc0f },
28761 - { 0x00001230, 0x00000000 },
28762 - { 0x00001270, 0x00000000 },
28763 - { 0x00001038, 0x00000000 },
28764 - { 0x00001078, 0x00000000 },
28765 - { 0x000010b8, 0x00000000 },
28766 - { 0x000010f8, 0x00000000 },
28767 - { 0x00001138, 0x00000000 },
28768 - { 0x00001178, 0x00000000 },
28769 - { 0x000011b8, 0x00000000 },
28770 - { 0x000011f8, 0x00000000 },
28771 - { 0x00001238, 0x00000000 },
28772 - { 0x00001278, 0x00000000 },
28773 - { 0x000012b8, 0x00000000 },
28774 - { 0x000012f8, 0x00000000 },
28775 - { 0x00001338, 0x00000000 },
28776 - { 0x00001378, 0x00000000 },
28777 - { 0x000013b8, 0x00000000 },
28778 - { 0x000013f8, 0x00000000 },
28779 - { 0x00001438, 0x00000000 },
28780 - { 0x00001478, 0x00000000 },
28781 - { 0x000014b8, 0x00000000 },
28782 - { 0x000014f8, 0x00000000 },
28783 - { 0x00001538, 0x00000000 },
28784 - { 0x00001578, 0x00000000 },
28785 - { 0x000015b8, 0x00000000 },
28786 - { 0x000015f8, 0x00000000 },
28787 - { 0x00001638, 0x00000000 },
28788 - { 0x00001678, 0x00000000 },
28789 - { 0x000016b8, 0x00000000 },
28790 - { 0x000016f8, 0x00000000 },
28791 - { 0x00001738, 0x00000000 },
28792 - { 0x00001778, 0x00000000 },
28793 - { 0x000017b8, 0x00000000 },
28794 - { 0x000017f8, 0x00000000 },
28795 - { 0x0000103c, 0x00000000 },
28796 - { 0x0000107c, 0x00000000 },
28797 - { 0x000010bc, 0x00000000 },
28798 - { 0x000010fc, 0x00000000 },
28799 - { 0x0000113c, 0x00000000 },
28800 - { 0x0000117c, 0x00000000 },
28801 - { 0x000011bc, 0x00000000 },
28802 - { 0x000011fc, 0x00000000 },
28803 - { 0x0000123c, 0x00000000 },
28804 - { 0x0000127c, 0x00000000 },
28805 - { 0x000012bc, 0x00000000 },
28806 - { 0x000012fc, 0x00000000 },
28807 - { 0x0000133c, 0x00000000 },
28808 - { 0x0000137c, 0x00000000 },
28809 - { 0x000013bc, 0x00000000 },
28810 - { 0x000013fc, 0x00000000 },
28811 - { 0x0000143c, 0x00000000 },
28812 - { 0x0000147c, 0x00000000 },
28813 - { 0x00004030, 0x00000002 },
28814 - { 0x0000403c, 0x00000002 },
28815 - { 0x00004024, 0x0000001f },
28816 - { 0x00004060, 0x00000000 },
28817 - { 0x00004064, 0x00000000 },
28818 - { 0x00007010, 0x00000031 },
28819 - { 0x00007034, 0x00000002 },
28820 - { 0x00007038, 0x000004c2 },
28821 - { 0x00008004, 0x00000000 },
28822 - { 0x00008008, 0x00000000 },
28823 - { 0x0000800c, 0x00000000 },
28824 - { 0x00008018, 0x00000700 },
28825 - { 0x00008020, 0x00000000 },
28826 - { 0x00008038, 0x00000000 },
28827 - { 0x0000803c, 0x00000000 },
28828 - { 0x00008048, 0x00000000 },
28829 - { 0x00008054, 0x00000000 },
28830 - { 0x00008058, 0x00000000 },
28831 - { 0x0000805c, 0x000fc78f },
28832 - { 0x00008060, 0x0000000f },
28833 - { 0x00008064, 0x00000000 },
28834 - { 0x00008070, 0x00000000 },
28835 - { 0x000080c0, 0x2a80001a },
28836 - { 0x000080c4, 0x05dc01e0 },
28837 - { 0x000080c8, 0x1f402710 },
28838 - { 0x000080cc, 0x01f40000 },
28839 - { 0x000080d0, 0x00001e00 },
28840 - { 0x000080d4, 0x00000000 },
28841 - { 0x000080d8, 0x00400000 },
28842 - { 0x000080e0, 0xffffffff },
28843 - { 0x000080e4, 0x0000ffff },
28844 - { 0x000080e8, 0x003f3f3f },
28845 - { 0x000080ec, 0x00000000 },
28846 - { 0x000080f0, 0x00000000 },
28847 - { 0x000080f4, 0x00000000 },
28848 - { 0x000080f8, 0x00000000 },
28849 - { 0x000080fc, 0x00020000 },
28850 - { 0x00008100, 0x00020000 },
28851 - { 0x00008104, 0x00000001 },
28852 - { 0x00008108, 0x00000052 },
28853 - { 0x0000810c, 0x00000000 },
28854 - { 0x00008110, 0x00000168 },
28855 - { 0x00008118, 0x000100aa },
28856 - { 0x0000811c, 0x00003210 },
28857 - { 0x00008120, 0x08f04810 },
28858 - { 0x00008124, 0x00000000 },
28859 - { 0x00008128, 0x00000000 },
28860 - { 0x0000812c, 0x00000000 },
28861 - { 0x00008130, 0x00000000 },
28862 - { 0x00008134, 0x00000000 },
28863 - { 0x00008138, 0x00000000 },
28864 - { 0x0000813c, 0x00000000 },
28865 - { 0x00008144, 0xffffffff },
28866 - { 0x00008168, 0x00000000 },
28867 - { 0x0000816c, 0x00000000 },
28868 - { 0x00008170, 0x32143320 },
28869 - { 0x00008174, 0xfaa4fa50 },
28870 - { 0x00008178, 0x00000100 },
28871 - { 0x0000817c, 0x00000000 },
28872 - { 0x000081c0, 0x00000000 },
28873 - { 0x000081d0, 0x0000320a },
28874 - { 0x000081ec, 0x00000000 },
28875 - { 0x000081f0, 0x00000000 },
28876 - { 0x000081f4, 0x00000000 },
28877 - { 0x000081f8, 0x00000000 },
28878 - { 0x000081fc, 0x00000000 },
28879 - { 0x00008200, 0x00000000 },
28880 - { 0x00008204, 0x00000000 },
28881 - { 0x00008208, 0x00000000 },
28882 - { 0x0000820c, 0x00000000 },
28883 - { 0x00008210, 0x00000000 },
28884 - { 0x00008214, 0x00000000 },
28885 - { 0x00008218, 0x00000000 },
28886 - { 0x0000821c, 0x00000000 },
28887 - { 0x00008220, 0x00000000 },
28888 - { 0x00008224, 0x00000000 },
28889 - { 0x00008228, 0x00000000 },
28890 - { 0x0000822c, 0x00000000 },
28891 - { 0x00008230, 0x00000000 },
28892 - { 0x00008234, 0x00000000 },
28893 - { 0x00008238, 0x00000000 },
28894 - { 0x0000823c, 0x00000000 },
28895 - { 0x00008240, 0x00100000 },
28896 - { 0x00008244, 0x0010f400 },
28897 - { 0x00008248, 0x00000100 },
28898 - { 0x0000824c, 0x0001e800 },
28899 - { 0x00008250, 0x00000000 },
28900 - { 0x00008254, 0x00000000 },
28901 - { 0x00008258, 0x00000000 },
28902 - { 0x0000825c, 0x400000ff },
28903 - { 0x00008260, 0x00080922 },
28904 - { 0x00008264, 0x88a00010 },
28905 - { 0x00008270, 0x00000000 },
28906 - { 0x00008274, 0x40000000 },
28907 - { 0x00008278, 0x003e4180 },
28908 - { 0x0000827c, 0x00000000 },
28909 - { 0x00008284, 0x0000002c },
28910 - { 0x00008288, 0x0000002c },
28911 - { 0x0000828c, 0x00000000 },
28912 - { 0x00008294, 0x00000000 },
28913 - { 0x00008298, 0x00000000 },
28914 - { 0x0000829c, 0x00000000 },
28915 - { 0x00008300, 0x00000040 },
28916 - { 0x00008314, 0x00000000 },
28917 - { 0x00008328, 0x00000000 },
28918 - { 0x0000832c, 0x00000001 },
28919 - { 0x00008330, 0x00000302 },
28920 - { 0x00008334, 0x00000e00 },
28921 - { 0x00008338, 0x00ff0000 },
28922 - { 0x0000833c, 0x00000000 },
28923 - { 0x00008340, 0x00010380 },
28924 - { 0x00008344, 0x00481043 },
28925 - { 0x00009808, 0x00000000 },
28926 - { 0x0000980c, 0xafe68e30 },
28927 - { 0x00009810, 0xfd14e000 },
28928 - { 0x00009814, 0x9c0a9f6b },
28929 - { 0x0000981c, 0x00000000 },
28930 - { 0x0000982c, 0x0000a000 },
28931 - { 0x00009830, 0x00000000 },
28932 - { 0x0000983c, 0x00200400 },
28933 - { 0x0000984c, 0x0040233c },
28934 - { 0x00009854, 0x00000044 },
28935 - { 0x00009900, 0x00000000 },
28936 - { 0x00009904, 0x00000000 },
28937 - { 0x00009908, 0x00000000 },
28938 - { 0x0000990c, 0x00000000 },
28939 - { 0x00009910, 0x01002310 },
28940 - { 0x0000991c, 0x10000fff },
28941 - { 0x00009920, 0x04900000 },
28942 - { 0x00009928, 0x00000001 },
28943 - { 0x0000992c, 0x00000004 },
28944 - { 0x00009934, 0x1e1f2022 },
28945 - { 0x00009938, 0x0a0b0c0d },
28946 - { 0x0000993c, 0x00000000 },
28947 - { 0x00009940, 0x14750604 },
28948 - { 0x00009948, 0x9280c00a },
28949 - { 0x0000994c, 0x00020028 },
28950 - { 0x00009954, 0x5f3ca3de },
28951 - { 0x00009958, 0x2108ecff },
28952 - { 0x00009968, 0x000003ce },
28953 - { 0x00009970, 0x192bb514 },
28954 - { 0x00009974, 0x00000000 },
28955 - { 0x00009978, 0x00000001 },
28956 - { 0x0000997c, 0x00000000 },
28957 - { 0x00009980, 0x00000000 },
28958 - { 0x00009984, 0x00000000 },
28959 - { 0x00009988, 0x00000000 },
28960 - { 0x0000998c, 0x00000000 },
28961 - { 0x00009990, 0x00000000 },
28962 - { 0x00009994, 0x00000000 },
28963 - { 0x00009998, 0x00000000 },
28964 - { 0x0000999c, 0x00000000 },
28965 - { 0x000099a0, 0x00000000 },
28966 - { 0x000099a4, 0x00000001 },
28967 - { 0x000099a8, 0x201fff00 },
28968 - { 0x000099ac, 0x2def0400 },
28969 - { 0x000099b0, 0x03051000 },
28970 - { 0x000099b4, 0x00000820 },
28971 - { 0x000099dc, 0x00000000 },
28972 - { 0x000099e0, 0x00000000 },
28973 - { 0x000099e4, 0xaaaaaaaa },
28974 - { 0x000099e8, 0x3c466478 },
28975 - { 0x000099ec, 0x0cc80caa },
28976 - { 0x000099f0, 0x00000000 },
28977 - { 0x0000a208, 0x803e68c8 },
28978 - { 0x0000a210, 0x4080a333 },
28979 - { 0x0000a214, 0x00206c10 },
28980 - { 0x0000a218, 0x009c4060 },
28981 - { 0x0000a220, 0x01834061 },
28982 - { 0x0000a224, 0x00000400 },
28983 - { 0x0000a228, 0x000003b5 },
28984 - { 0x0000a22c, 0x00000000 },
28985 - { 0x0000a234, 0x20202020 },
28986 - { 0x0000a238, 0x20202020 },
28987 - { 0x0000a244, 0x00000000 },
28988 - { 0x0000a248, 0xfffffffc },
28989 - { 0x0000a24c, 0x00000000 },
28990 - { 0x0000a254, 0x00000000 },
28991 - { 0x0000a258, 0x0ccb5380 },
28992 - { 0x0000a25c, 0x15151501 },
28993 - { 0x0000a260, 0xdfa90f01 },
28994 - { 0x0000a268, 0x00000000 },
28995 - { 0x0000a26c, 0x0ebae9e6 },
28996 - { 0x0000d270, 0x0d820820 },
28997 - { 0x0000d35c, 0x07ffffef },
28998 - { 0x0000d360, 0x0fffffe7 },
28999 - { 0x0000d364, 0x17ffffe5 },
29000 - { 0x0000d368, 0x1fffffe4 },
29001 - { 0x0000d36c, 0x37ffffe3 },
29002 - { 0x0000d370, 0x3fffffe3 },
29003 - { 0x0000d374, 0x57ffffe3 },
29004 - { 0x0000d378, 0x5fffffe2 },
29005 - { 0x0000d37c, 0x7fffffe2 },
29006 - { 0x0000d380, 0x7f3c7bba },
29007 - { 0x0000d384, 0xf3307ff0 },
29008 - { 0x0000a388, 0x0c000000 },
29009 - { 0x0000a38c, 0x20202020 },
29010 - { 0x0000a390, 0x20202020 },
29011 - { 0x0000a39c, 0x00000001 },
29012 - { 0x0000a3a0, 0x00000000 },
29013 - { 0x0000a3a4, 0x00000000 },
29014 - { 0x0000a3a8, 0x00000000 },
29015 - { 0x0000a3ac, 0x00000000 },
29016 - { 0x0000a3b0, 0x00000000 },
29017 - { 0x0000a3b4, 0x00000000 },
29018 - { 0x0000a3b8, 0x00000000 },
29019 - { 0x0000a3bc, 0x00000000 },
29020 - { 0x0000a3c0, 0x00000000 },
29021 - { 0x0000a3c4, 0x00000000 },
29022 - { 0x0000a3cc, 0x20202020 },
29023 - { 0x0000a3d0, 0x20202020 },
29024 - { 0x0000a3d4, 0x20202020 },
29025 - { 0x0000a3e4, 0x00000000 },
29026 - { 0x0000a3e8, 0x18c43433 },
29027 - { 0x0000a3ec, 0x00f70081 },
29028 - { 0x00007800, 0x00140000 },
29029 - { 0x00007804, 0x0e4548d8 },
29030 - { 0x00007808, 0x54214514 },
29031 - { 0x0000780c, 0x02025830 },
29032 - { 0x00007810, 0x71c0d388 },
29033 - { 0x0000781c, 0x00000000 },
29034 - { 0x00007824, 0x00d86fff },
29035 - { 0x0000782c, 0x6e36d97b },
29036 - { 0x00007834, 0x71400087 },
29037 - { 0x00007844, 0x000c0db6 },
29038 - { 0x00007848, 0x6db6246f },
29039 - { 0x0000784c, 0x6d9b66db },
29040 - { 0x00007850, 0x6d8c6dba },
29041 - { 0x00007854, 0x00040000 },
29042 - { 0x00007858, 0xdb003012 },
29043 - { 0x0000785c, 0x04924914 },
29044 - { 0x00007860, 0x21084210 },
29045 - { 0x00007864, 0xf7d7ffde },
29046 - { 0x00007868, 0xc2034080 },
29047 - { 0x00007870, 0x10142c00 },
29048 -};
29049 -
29050 -static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
29051 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29052 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29053 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
29054 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
29055 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
29056 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
29057 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
29058 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
29059 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
29060 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
29061 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
29062 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
29063 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
29064 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
29065 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
29066 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29067 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29068 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29069 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29070 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29071 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29072 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29073 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29074 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
29075 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
29076 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
29077 - { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
29078 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
29079 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
29080 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
29081 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
29082 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
29083 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29084 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
29085 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29086 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29087 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29088 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29089 -};
29090 -
29091 -static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
29092 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29093 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29094 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
29095 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
29096 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
29097 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
29098 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
29099 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
29100 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
29101 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
29102 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
29103 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
29104 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
29105 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
29106 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
29107 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29108 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29109 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29110 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29111 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29112 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29113 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29114 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29115 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
29116 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
29117 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
29118 - { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
29119 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
29120 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
29121 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
29122 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
29123 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
29124 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29125 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
29126 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29127 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29128 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29129 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29130 -};
29131 -
29132 -static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
29133 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29134 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
29135 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
29136 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
29137 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
29138 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
29139 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
29140 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
29141 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
29142 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
29143 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
29144 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
29145 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
29146 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
29147 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29148 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29149 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29150 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29151 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29152 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29153 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29154 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29155 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
29156 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
29157 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
29158 - { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
29159 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
29160 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
29161 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
29162 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
29163 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
29164 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29165 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
29166 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29167 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29168 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
29169 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
29170 -};
29171 -
29172 -static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
29173 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29174 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
29175 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
29176 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
29177 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
29178 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
29179 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
29180 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
29181 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
29182 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
29183 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
29184 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
29185 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
29186 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
29187 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
29188 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
29189 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29190 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29191 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29192 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29193 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29194 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
29195 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
29196 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
29197 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
29198 - { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
29199 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
29200 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
29201 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
29202 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
29203 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
29204 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29205 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
29206 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29207 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29208 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
29209 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
29210 -};
29211 -
29212 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
29213 - {0x00004040, 0x9248fd00 },
29214 - {0x00004040, 0x24924924 },
29215 - {0x00004040, 0xa8000019 },
29216 - {0x00004040, 0x13160820 },
29217 - {0x00004040, 0xe5980560 },
29218 - {0x00004040, 0xc01dcffd },
29219 - {0x00004040, 0x1aaabe41 },
29220 - {0x00004040, 0xbe105554 },
29221 - {0x00004040, 0x00043007 },
29222 - {0x00004044, 0x00000000 },
29223 -};
29224 -
29225 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
29226 - {0x00004040, 0x9248fd00 },
29227 - {0x00004040, 0x24924924 },
29228 - {0x00004040, 0xa8000019 },
29229 - {0x00004040, 0x13160820 },
29230 - {0x00004040, 0xe5980560 },
29231 - {0x00004040, 0xc01dcffc },
29232 - {0x00004040, 0x1aaabe41 },
29233 - {0x00004040, 0xbe105554 },
29234 - {0x00004040, 0x00043007 },
29235 - {0x00004044, 0x00000000 },
29236 -};
29237 -
29238 -/* AR9287 Revision 10 */
29239 -static const u_int32_t ar9287Modes_9287_1_0[][6] = {
29240 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29241 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
29242 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
29243 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
29244 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
29245 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
29246 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
29247 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
29248 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
29249 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
29250 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
29251 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
29252 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
29253 - { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
29254 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29255 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
29256 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
29257 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
29258 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
29259 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
29260 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
29261 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
29262 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29263 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
29264 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
29265 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
29266 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
29267 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29268 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
29269 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29270 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
29271 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
29272 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
29273 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
29274 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
29275 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29276 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
29277 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29278 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29279 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
29280 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29281 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
29282 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
29283 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29284 -};
29285 -
29286 -static const u_int32_t ar9287Common_9287_1_0[][2] = {
29287 - { 0x0000000c, 0x00000000 },
29288 - { 0x00000030, 0x00020015 },
29289 - { 0x00000034, 0x00000005 },
29290 - { 0x00000040, 0x00000000 },
29291 - { 0x00000044, 0x00000008 },
29292 - { 0x00000048, 0x00000008 },
29293 - { 0x0000004c, 0x00000010 },
29294 - { 0x00000050, 0x00000000 },
29295 - { 0x00000054, 0x0000001f },
29296 - { 0x00000800, 0x00000000 },
29297 - { 0x00000804, 0x00000000 },
29298 - { 0x00000808, 0x00000000 },
29299 - { 0x0000080c, 0x00000000 },
29300 - { 0x00000810, 0x00000000 },
29301 - { 0x00000814, 0x00000000 },
29302 - { 0x00000818, 0x00000000 },
29303 - { 0x0000081c, 0x00000000 },
29304 - { 0x00000820, 0x00000000 },
29305 - { 0x00000824, 0x00000000 },
29306 - { 0x00001040, 0x002ffc0f },
29307 - { 0x00001044, 0x002ffc0f },
29308 - { 0x00001048, 0x002ffc0f },
29309 - { 0x0000104c, 0x002ffc0f },
29310 - { 0x00001050, 0x002ffc0f },
29311 - { 0x00001054, 0x002ffc0f },
29312 - { 0x00001058, 0x002ffc0f },
29313 - { 0x0000105c, 0x002ffc0f },
29314 - { 0x00001060, 0x002ffc0f },
29315 - { 0x00001064, 0x002ffc0f },
29316 - { 0x00001230, 0x00000000 },
29317 - { 0x00001270, 0x00000000 },
29318 - { 0x00001038, 0x00000000 },
29319 - { 0x00001078, 0x00000000 },
29320 - { 0x000010b8, 0x00000000 },
29321 - { 0x000010f8, 0x00000000 },
29322 - { 0x00001138, 0x00000000 },
29323 - { 0x00001178, 0x00000000 },
29324 - { 0x000011b8, 0x00000000 },
29325 - { 0x000011f8, 0x00000000 },
29326 - { 0x00001238, 0x00000000 },
29327 - { 0x00001278, 0x00000000 },
29328 - { 0x000012b8, 0x00000000 },
29329 - { 0x000012f8, 0x00000000 },
29330 - { 0x00001338, 0x00000000 },
29331 - { 0x00001378, 0x00000000 },
29332 - { 0x000013b8, 0x00000000 },
29333 - { 0x000013f8, 0x00000000 },
29334 - { 0x00001438, 0x00000000 },
29335 - { 0x00001478, 0x00000000 },
29336 - { 0x000014b8, 0x00000000 },
29337 - { 0x000014f8, 0x00000000 },
29338 - { 0x00001538, 0x00000000 },
29339 - { 0x00001578, 0x00000000 },
29340 - { 0x000015b8, 0x00000000 },
29341 - { 0x000015f8, 0x00000000 },
29342 - { 0x00001638, 0x00000000 },
29343 - { 0x00001678, 0x00000000 },
29344 - { 0x000016b8, 0x00000000 },
29345 - { 0x000016f8, 0x00000000 },
29346 - { 0x00001738, 0x00000000 },
29347 - { 0x00001778, 0x00000000 },
29348 - { 0x000017b8, 0x00000000 },
29349 - { 0x000017f8, 0x00000000 },
29350 - { 0x0000103c, 0x00000000 },
29351 - { 0x0000107c, 0x00000000 },
29352 - { 0x000010bc, 0x00000000 },
29353 - { 0x000010fc, 0x00000000 },
29354 - { 0x0000113c, 0x00000000 },
29355 - { 0x0000117c, 0x00000000 },
29356 - { 0x000011bc, 0x00000000 },
29357 - { 0x000011fc, 0x00000000 },
29358 - { 0x0000123c, 0x00000000 },
29359 - { 0x0000127c, 0x00000000 },
29360 - { 0x000012bc, 0x00000000 },
29361 - { 0x000012fc, 0x00000000 },
29362 - { 0x0000133c, 0x00000000 },
29363 - { 0x0000137c, 0x00000000 },
29364 - { 0x000013bc, 0x00000000 },
29365 - { 0x000013fc, 0x00000000 },
29366 - { 0x0000143c, 0x00000000 },
29367 - { 0x0000147c, 0x00000000 },
29368 - { 0x00004030, 0x00000002 },
29369 - { 0x0000403c, 0x00000002 },
29370 - { 0x00004024, 0x0000001f },
29371 - { 0x00004060, 0x00000000 },
29372 - { 0x00004064, 0x00000000 },
29373 - { 0x00007010, 0x00000033 },
29374 - { 0x00007020, 0x00000000 },
29375 - { 0x00007034, 0x00000002 },
29376 - { 0x00007038, 0x000004c2 },
29377 - { 0x00008004, 0x00000000 },
29378 - { 0x00008008, 0x00000000 },
29379 - { 0x0000800c, 0x00000000 },
29380 - { 0x00008018, 0x00000700 },
29381 - { 0x00008020, 0x00000000 },
29382 - { 0x00008038, 0x00000000 },
29383 - { 0x0000803c, 0x00000000 },
29384 - { 0x00008048, 0x40000000 },
29385 - { 0x00008054, 0x00000000 },
29386 - { 0x00008058, 0x00000000 },
29387 - { 0x0000805c, 0x000fc78f },
29388 - { 0x00008060, 0x0000000f },
29389 - { 0x00008064, 0x00000000 },
29390 - { 0x00008070, 0x00000000 },
29391 - { 0x000080c0, 0x2a80001a },
29392 - { 0x000080c4, 0x05dc01e0 },
29393 - { 0x000080c8, 0x1f402710 },
29394 - { 0x000080cc, 0x01f40000 },
29395 - { 0x000080d0, 0x00001e00 },
29396 - { 0x000080d4, 0x00000000 },
29397 - { 0x000080d8, 0x00400000 },
29398 - { 0x000080e0, 0xffffffff },
29399 - { 0x000080e4, 0x0000ffff },
29400 - { 0x000080e8, 0x003f3f3f },
29401 - { 0x000080ec, 0x00000000 },
29402 - { 0x000080f0, 0x00000000 },
29403 - { 0x000080f4, 0x00000000 },
29404 - { 0x000080f8, 0x00000000 },
29405 - { 0x000080fc, 0x00020000 },
29406 - { 0x00008100, 0x00020000 },
29407 - { 0x00008104, 0x00000001 },
29408 - { 0x00008108, 0x00000052 },
29409 - { 0x0000810c, 0x00000000 },
29410 - { 0x00008110, 0x00000168 },
29411 - { 0x00008118, 0x000100aa },
29412 - { 0x0000811c, 0x00003210 },
29413 - { 0x00008124, 0x00000000 },
29414 - { 0x00008128, 0x00000000 },
29415 - { 0x0000812c, 0x00000000 },
29416 - { 0x00008130, 0x00000000 },
29417 - { 0x00008134, 0x00000000 },
29418 - { 0x00008138, 0x00000000 },
29419 - { 0x0000813c, 0x00000000 },
29420 - { 0x00008144, 0xffffffff },
29421 - { 0x00008168, 0x00000000 },
29422 - { 0x0000816c, 0x00000000 },
29423 - { 0x00008170, 0x18487320 },
29424 - { 0x00008174, 0xfaa4fa50 },
29425 - { 0x00008178, 0x00000100 },
29426 - { 0x0000817c, 0x00000000 },
29427 - { 0x000081c0, 0x00000000 },
29428 - { 0x000081c4, 0x00000000 },
29429 - { 0x000081d4, 0x00000000 },
29430 - { 0x000081ec, 0x00000000 },
29431 - { 0x000081f0, 0x00000000 },
29432 - { 0x000081f4, 0x00000000 },
29433 - { 0x000081f8, 0x00000000 },
29434 - { 0x000081fc, 0x00000000 },
29435 - { 0x00008200, 0x00000000 },
29436 - { 0x00008204, 0x00000000 },
29437 - { 0x00008208, 0x00000000 },
29438 - { 0x0000820c, 0x00000000 },
29439 - { 0x00008210, 0x00000000 },
29440 - { 0x00008214, 0x00000000 },
29441 - { 0x00008218, 0x00000000 },
29442 - { 0x0000821c, 0x00000000 },
29443 - { 0x00008220, 0x00000000 },
29444 - { 0x00008224, 0x00000000 },
29445 - { 0x00008228, 0x00000000 },
29446 - { 0x0000822c, 0x00000000 },
29447 - { 0x00008230, 0x00000000 },
29448 - { 0x00008234, 0x00000000 },
29449 - { 0x00008238, 0x00000000 },
29450 - { 0x0000823c, 0x00000000 },
29451 - { 0x00008240, 0x00100000 },
29452 - { 0x00008244, 0x0010f400 },
29453 - { 0x00008248, 0x00000100 },
29454 - { 0x0000824c, 0x0001e800 },
29455 - { 0x00008250, 0x00000000 },
29456 - { 0x00008254, 0x00000000 },
29457 - { 0x00008258, 0x00000000 },
29458 - { 0x0000825c, 0x400000ff },
29459 - { 0x00008260, 0x00080922 },
29460 - { 0x00008264, 0xa8a00010 },
29461 - { 0x00008270, 0x00000000 },
29462 - { 0x00008274, 0x40000000 },
29463 - { 0x00008278, 0x003e4180 },
29464 - { 0x0000827c, 0x00000000 },
29465 - { 0x00008284, 0x0000002c },
29466 - { 0x00008288, 0x0000002c },
29467 - { 0x0000828c, 0x000000ff },
29468 - { 0x00008294, 0x00000000 },
29469 - { 0x00008298, 0x00000000 },
29470 - { 0x0000829c, 0x00000000 },
29471 - { 0x00008300, 0x00000040 },
29472 - { 0x00008314, 0x00000000 },
29473 - { 0x00008328, 0x00000000 },
29474 - { 0x0000832c, 0x00000007 },
29475 - { 0x00008330, 0x00000302 },
29476 - { 0x00008334, 0x00000e00 },
29477 - { 0x00008338, 0x00ff0000 },
29478 - { 0x0000833c, 0x00000000 },
29479 - { 0x00008340, 0x000107ff },
29480 - { 0x00008344, 0x01c81043 },
29481 - { 0x00008360, 0xffffffff },
29482 - { 0x00008364, 0xffffffff },
29483 - { 0x00008368, 0x00000000 },
29484 - { 0x00008370, 0x00000000 },
29485 - { 0x00008374, 0x000000ff },
29486 - { 0x00008378, 0x00000000 },
29487 - { 0x0000837c, 0x00000000 },
29488 - { 0x00008380, 0xffffffff },
29489 - { 0x00008384, 0xffffffff },
29490 - { 0x00008390, 0x0fffffff },
29491 - { 0x00008394, 0x0fffffff },
29492 - { 0x00008398, 0x00000000 },
29493 - { 0x0000839c, 0x00000000 },
29494 - { 0x000083a0, 0x00000000 },
29495 - { 0x00009808, 0x00000000 },
29496 - { 0x0000980c, 0xafe68e30 },
29497 - { 0x00009810, 0xfd14e000 },
29498 - { 0x00009814, 0x9c0a9f6b },
29499 - { 0x0000981c, 0x00000000 },
29500 - { 0x0000982c, 0x0000a000 },
29501 - { 0x00009830, 0x00000000 },
29502 - { 0x0000983c, 0x00200400 },
29503 - { 0x0000984c, 0x0040233c },
29504 - { 0x0000a84c, 0x0040233c },
29505 - { 0x00009854, 0x00000044 },
29506 - { 0x00009900, 0x00000000 },
29507 - { 0x00009904, 0x00000000 },
29508 - { 0x00009908, 0x00000000 },
29509 - { 0x0000990c, 0x00000000 },
29510 - { 0x00009910, 0x10002310 },
29511 - { 0x0000991c, 0x10000fff },
29512 - { 0x00009920, 0x04900000 },
29513 - { 0x0000a920, 0x04900000 },
29514 - { 0x00009928, 0x00000001 },
29515 - { 0x0000992c, 0x00000004 },
29516 - { 0x00009930, 0x00000000 },
29517 - { 0x0000a930, 0x00000000 },
29518 - { 0x00009934, 0x1e1f2022 },
29519 - { 0x00009938, 0x0a0b0c0d },
29520 - { 0x0000993c, 0x00000000 },
29521 - { 0x00009948, 0x9280c00a },
29522 - { 0x0000994c, 0x00020028 },
29523 - { 0x00009954, 0x5f3ca3de },
29524 - { 0x00009958, 0x0108ecff },
29525 - { 0x00009940, 0x14750604 },
29526 - { 0x0000c95c, 0x004b6a8e },
29527 - { 0x00009970, 0x990bb515 },
29528 - { 0x00009974, 0x00000000 },
29529 - { 0x00009978, 0x00000001 },
29530 - { 0x0000997c, 0x00000000 },
29531 - { 0x000099a0, 0x00000000 },
29532 - { 0x000099a4, 0x00000001 },
29533 - { 0x000099a8, 0x201fff00 },
29534 - { 0x000099ac, 0x0c6f0000 },
29535 - { 0x000099b0, 0x03051000 },
29536 - { 0x000099b4, 0x00000820 },
29537 - { 0x000099c4, 0x06336f77 },
29538 - { 0x000099c8, 0x6af65329 },
29539 - { 0x000099cc, 0x08f186c8 },
29540 - { 0x000099d0, 0x00046384 },
29541 - { 0x000099dc, 0x00000000 },
29542 - { 0x000099e0, 0x00000000 },
29543 - { 0x000099e4, 0xaaaaaaaa },
29544 - { 0x000099e8, 0x3c466478 },
29545 - { 0x000099ec, 0x0cc80caa },
29546 - { 0x000099f0, 0x00000000 },
29547 - { 0x000099fc, 0x00001042 },
29548 - { 0x0000a1f4, 0x00fffeff },
29549 - { 0x0000a1f8, 0x00f5f9ff },
29550 - { 0x0000a1fc, 0xb79f6427 },
29551 - { 0x0000a208, 0x803e4788 },
29552 - { 0x0000a210, 0x4080a333 },
29553 - { 0x0000a214, 0x40206c10 },
29554 - { 0x0000a218, 0x009c4060 },
29555 - { 0x0000a220, 0x01834061 },
29556 - { 0x0000a224, 0x00000400 },
29557 - { 0x0000a228, 0x000003b5 },
29558 - { 0x0000a22c, 0x233f7180 },
29559 - { 0x0000a234, 0x20202020 },
29560 - { 0x0000a238, 0x20202020 },
29561 - { 0x0000a23c, 0x13c889af },
29562 - { 0x0000a240, 0x38490a20 },
29563 - { 0x0000a244, 0x00000000 },
29564 - { 0x0000a248, 0xfffffffc },
29565 - { 0x0000a24c, 0x00000000 },
29566 - { 0x0000a254, 0x00000000 },
29567 - { 0x0000a258, 0x0cdbd380 },
29568 - { 0x0000a25c, 0x0f0f0f01 },
29569 - { 0x0000a260, 0xdfa91f01 },
29570 - { 0x0000a264, 0x00418a11 },
29571 - { 0x0000b264, 0x00418a11 },
29572 - { 0x0000a268, 0x00000000 },
29573 - { 0x0000a26c, 0x0e79e5c6 },
29574 - { 0x0000b26c, 0x0e79e5c6 },
29575 - { 0x0000d270, 0x00820820 },
29576 - { 0x0000a278, 0x1ce739ce },
29577 - { 0x0000a27c, 0x050701ce },
29578 - { 0x0000d35c, 0x07ffffef },
29579 - { 0x0000d360, 0x0fffffe7 },
29580 - { 0x0000d364, 0x17ffffe5 },
29581 - { 0x0000d368, 0x1fffffe4 },
29582 - { 0x0000d36c, 0x37ffffe3 },
29583 - { 0x0000d370, 0x3fffffe3 },
29584 - { 0x0000d374, 0x57ffffe3 },
29585 - { 0x0000d378, 0x5fffffe2 },
29586 - { 0x0000d37c, 0x7fffffe2 },
29587 - { 0x0000d380, 0x7f3c7bba },
29588 - { 0x0000d384, 0xf3307ff0 },
29589 - { 0x0000a388, 0x0c000000 },
29590 - { 0x0000a38c, 0x20202020 },
29591 - { 0x0000a390, 0x20202020 },
29592 - { 0x0000a394, 0x1ce739ce },
29593 - { 0x0000a398, 0x000001ce },
29594 - { 0x0000b398, 0x000001ce },
29595 - { 0x0000a39c, 0x00000001 },
29596 - { 0x0000a3c8, 0x00000246 },
29597 - { 0x0000a3cc, 0x20202020 },
29598 - { 0x0000a3d0, 0x20202020 },
29599 - { 0x0000a3d4, 0x20202020 },
29600 - { 0x0000a3dc, 0x1ce739ce },
29601 - { 0x0000a3e0, 0x000001ce },
29602 - { 0x0000a3e4, 0x00000000 },
29603 - { 0x0000a3e8, 0x18c43433 },
29604 - { 0x0000a3ec, 0x00f70081 },
29605 - { 0x0000a3f0, 0x01036a1e },
29606 - { 0x0000a3f4, 0x00000000 },
29607 - { 0x0000b3f4, 0x00000000 },
29608 - { 0x0000a7d8, 0x00000001 },
29609 - { 0x00007800, 0x00000800 },
29610 - { 0x00007804, 0x6c35ffb0 },
29611 - { 0x00007808, 0x6db6c000 },
29612 - { 0x0000780c, 0x6db6cb30 },
29613 - { 0x00007810, 0x6db6cb6c },
29614 - { 0x00007814, 0x0501e200 },
29615 - { 0x00007818, 0x0094128d },
29616 - { 0x0000781c, 0x976ee392 },
29617 - { 0x00007820, 0xf75ff6fc },
29618 - { 0x00007824, 0x00040000 },
29619 - { 0x00007828, 0xdb003012 },
29620 - { 0x0000782c, 0x04924914 },
29621 - { 0x00007830, 0x21084210 },
29622 - { 0x00007834, 0x00140000 },
29623 - { 0x00007838, 0x0e4548d8 },
29624 - { 0x0000783c, 0x54214514 },
29625 - { 0x00007840, 0x02025820 },
29626 - { 0x00007844, 0x71c0d388 },
29627 - { 0x00007848, 0x934934a8 },
29628 - { 0x00007850, 0x00000000 },
29629 - { 0x00007854, 0x00000800 },
29630 - { 0x00007858, 0x6c35ffb0 },
29631 - { 0x0000785c, 0x6db6c000 },
29632 - { 0x00007860, 0x6db6cb2c },
29633 - { 0x00007864, 0x6db6cb6c },
29634 - { 0x00007868, 0x0501e200 },
29635 - { 0x0000786c, 0x0094128d },
29636 - { 0x00007870, 0x976ee392 },
29637 - { 0x00007874, 0xf75ff6fc },
29638 - { 0x00007878, 0x00040000 },
29639 - { 0x0000787c, 0xdb003012 },
29640 - { 0x00007880, 0x04924914 },
29641 - { 0x00007884, 0x21084210 },
29642 - { 0x00007888, 0x001b6db0 },
29643 - { 0x0000788c, 0x00376b63 },
29644 - { 0x00007890, 0x06db6db6 },
29645 - { 0x00007894, 0x006d8000 },
29646 - { 0x00007898, 0x48100000 },
29647 - { 0x0000789c, 0x00000000 },
29648 - { 0x000078a0, 0x08000000 },
29649 - { 0x000078a4, 0x0007ffd8 },
29650 - { 0x000078a8, 0x0007ffd8 },
29651 - { 0x000078ac, 0x001c0020 },
29652 - { 0x000078b0, 0x000611eb },
29653 - { 0x000078b4, 0x40008080 },
29654 - { 0x000078b8, 0x2a850160 },
29655 -};
29656 -
29657 -static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
29658 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29659 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29660 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
29661 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
29662 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
29663 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
29664 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
29665 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
29666 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
29667 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
29668 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
29669 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
29670 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
29671 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
29672 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
29673 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
29674 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
29675 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
29676 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
29677 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
29678 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
29679 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
29680 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
29681 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
29682 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
29683 - { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
29684 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
29685 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
29686 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
29687 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
29688 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
29689 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
29690 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
29691 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
29692 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
29693 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
29694 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29695 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29696 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29697 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29698 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29699 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29700 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29701 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29702 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
29703 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
29704 -};
29705 -
29706 -
29707 -static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
29708 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29709 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
29710 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
29711 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
29712 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
29713 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
29714 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
29715 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
29716 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
29717 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
29718 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
29719 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
29720 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
29721 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
29722 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
29723 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
29724 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
29725 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
29726 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
29727 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
29728 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
29729 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
29730 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
29731 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
29732 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
29733 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
29734 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
29735 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
29736 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
29737 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
29738 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
29739 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
29740 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
29741 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
29742 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
29743 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
29744 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
29745 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
29746 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
29747 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
29748 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
29749 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
29750 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
29751 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
29752 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
29753 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
29754 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
29755 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
29756 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
29757 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
29758 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
29759 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
29760 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
29761 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
29762 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
29763 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
29764 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
29765 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
29766 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
29767 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
29768 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
29769 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
29770 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
29771 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
29772 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
29773 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
29774 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
29775 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
29776 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
29777 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
29778 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
29779 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
29780 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
29781 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
29782 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
29783 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
29784 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
29785 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
29786 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
29787 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
29788 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
29789 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
29790 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
29791 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
29792 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
29793 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
29794 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
29795 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
29796 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
29797 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
29798 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
29799 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
29800 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
29801 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
29802 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
29803 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
29804 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
29805 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
29806 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
29807 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
29808 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
29809 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
29810 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
29811 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
29812 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29813 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29814 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29815 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29816 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29817 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29818 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29819 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29820 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29821 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29822 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29823 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29824 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29825 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29826 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29827 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29828 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29829 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29830 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29831 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29832 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29833 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29834 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29835 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29836 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29837 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
29838 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
29839 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
29840 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
29841 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
29842 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
29843 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
29844 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
29845 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
29846 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
29847 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
29848 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
29849 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
29850 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
29851 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
29852 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
29853 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
29854 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
29855 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
29856 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
29857 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
29858 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
29859 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
29860 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
29861 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
29862 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
29863 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
29864 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
29865 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
29866 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
29867 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
29868 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
29869 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
29870 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
29871 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
29872 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
29873 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
29874 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
29875 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
29876 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
29877 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
29878 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
29879 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
29880 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
29881 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
29882 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
29883 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
29884 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
29885 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
29886 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
29887 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
29888 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
29889 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
29890 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
29891 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
29892 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
29893 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
29894 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
29895 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
29896 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
29897 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
29898 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
29899 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
29900 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
29901 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
29902 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
29903 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
29904 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
29905 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
29906 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
29907 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
29908 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
29909 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
29910 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
29911 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
29912 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
29913 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
29914 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
29915 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
29916 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
29917 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
29918 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
29919 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
29920 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
29921 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
29922 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
29923 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
29924 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
29925 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
29926 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
29927 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
29928 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
29929 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
29930 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
29931 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
29932 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
29933 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
29934 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
29935 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
29936 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
29937 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
29938 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
29939 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
29940 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29941 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29942 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29943 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29944 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29945 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29946 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29947 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29948 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29949 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29950 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29951 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29952 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29953 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29954 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29955 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29956 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29957 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29958 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29959 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29960 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29961 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29962 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29963 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29964 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
29965 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
29966 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
29967 -};
29968 -
29969 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
29970 - {0x00004040, 0x9248fd00 },
29971 - {0x00004040, 0x24924924 },
29972 - {0x00004040, 0xa8000019 },
29973 - {0x00004040, 0x13160820 },
29974 - {0x00004040, 0xe5980560 },
29975 - {0x00004040, 0xc01dcffd },
29976 - {0x00004040, 0x1aaabe41 },
29977 - {0x00004040, 0xbe105554 },
29978 - {0x00004040, 0x00043007 },
29979 - {0x00004044, 0x00000000 },
29980 -};
29981 -
29982 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
29983 - {0x00004040, 0x9248fd00 },
29984 - {0x00004040, 0x24924924 },
29985 - {0x00004040, 0xa8000019 },
29986 - {0x00004040, 0x13160820 },
29987 - {0x00004040, 0xe5980560 },
29988 - {0x00004040, 0xc01dcffc },
29989 - {0x00004040, 0x1aaabe41 },
29990 - {0x00004040, 0xbe105554 },
29991 - {0x00004040, 0x00043007 },
29992 - {0x00004044, 0x00000000 },
29993 -};
29994 -
29995 -/* AR9287 Revision 11 */
29996 -
29997 -static const u_int32_t ar9287Modes_9287_1_1[][6] = {
29998 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
29999 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
30000 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
30001 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
30002 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
30003 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
30004 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
30005 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
30006 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
30007 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
30008 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
30009 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
30010 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
30011 - { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
30012 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30013 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
30014 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
30015 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
30016 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
30017 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
30018 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
30019 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
30020 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
30021 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
30022 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
30023 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
30024 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
30025 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
30026 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
30027 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
30028 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
30029 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
30030 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
30031 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
30032 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
30033 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
30034 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
30035 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30036 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30037 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
30038 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
30039 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
30040 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
30041 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30042 -};
30043 -
30044 -static const u_int32_t ar9287Common_9287_1_1[][2] = {
30045 - { 0x0000000c, 0x00000000 },
30046 - { 0x00000030, 0x00020015 },
30047 - { 0x00000034, 0x00000005 },
30048 - { 0x00000040, 0x00000000 },
30049 - { 0x00000044, 0x00000008 },
30050 - { 0x00000048, 0x00000008 },
30051 - { 0x0000004c, 0x00000010 },
30052 - { 0x00000050, 0x00000000 },
30053 - { 0x00000054, 0x0000001f },
30054 - { 0x00000800, 0x00000000 },
30055 - { 0x00000804, 0x00000000 },
30056 - { 0x00000808, 0x00000000 },
30057 - { 0x0000080c, 0x00000000 },
30058 - { 0x00000810, 0x00000000 },
30059 - { 0x00000814, 0x00000000 },
30060 - { 0x00000818, 0x00000000 },
30061 - { 0x0000081c, 0x00000000 },
30062 - { 0x00000820, 0x00000000 },
30063 - { 0x00000824, 0x00000000 },
30064 - { 0x00001040, 0x002ffc0f },
30065 - { 0x00001044, 0x002ffc0f },
30066 - { 0x00001048, 0x002ffc0f },
30067 - { 0x0000104c, 0x002ffc0f },
30068 - { 0x00001050, 0x002ffc0f },
30069 - { 0x00001054, 0x002ffc0f },
30070 - { 0x00001058, 0x002ffc0f },
30071 - { 0x0000105c, 0x002ffc0f },
30072 - { 0x00001060, 0x002ffc0f },
30073 - { 0x00001064, 0x002ffc0f },
30074 - { 0x00001230, 0x00000000 },
30075 - { 0x00001270, 0x00000000 },
30076 - { 0x00001038, 0x00000000 },
30077 - { 0x00001078, 0x00000000 },
30078 - { 0x000010b8, 0x00000000 },
30079 - { 0x000010f8, 0x00000000 },
30080 - { 0x00001138, 0x00000000 },
30081 - { 0x00001178, 0x00000000 },
30082 - { 0x000011b8, 0x00000000 },
30083 - { 0x000011f8, 0x00000000 },
30084 - { 0x00001238, 0x00000000 },
30085 - { 0x00001278, 0x00000000 },
30086 - { 0x000012b8, 0x00000000 },
30087 - { 0x000012f8, 0x00000000 },
30088 - { 0x00001338, 0x00000000 },
30089 - { 0x00001378, 0x00000000 },
30090 - { 0x000013b8, 0x00000000 },
30091 - { 0x000013f8, 0x00000000 },
30092 - { 0x00001438, 0x00000000 },
30093 - { 0x00001478, 0x00000000 },
30094 - { 0x000014b8, 0x00000000 },
30095 - { 0x000014f8, 0x00000000 },
30096 - { 0x00001538, 0x00000000 },
30097 - { 0x00001578, 0x00000000 },
30098 - { 0x000015b8, 0x00000000 },
30099 - { 0x000015f8, 0x00000000 },
30100 - { 0x00001638, 0x00000000 },
30101 - { 0x00001678, 0x00000000 },
30102 - { 0x000016b8, 0x00000000 },
30103 - { 0x000016f8, 0x00000000 },
30104 - { 0x00001738, 0x00000000 },
30105 - { 0x00001778, 0x00000000 },
30106 - { 0x000017b8, 0x00000000 },
30107 - { 0x000017f8, 0x00000000 },
30108 - { 0x0000103c, 0x00000000 },
30109 - { 0x0000107c, 0x00000000 },
30110 - { 0x000010bc, 0x00000000 },
30111 - { 0x000010fc, 0x00000000 },
30112 - { 0x0000113c, 0x00000000 },
30113 - { 0x0000117c, 0x00000000 },
30114 - { 0x000011bc, 0x00000000 },
30115 - { 0x000011fc, 0x00000000 },
30116 - { 0x0000123c, 0x00000000 },
30117 - { 0x0000127c, 0x00000000 },
30118 - { 0x000012bc, 0x00000000 },
30119 - { 0x000012fc, 0x00000000 },
30120 - { 0x0000133c, 0x00000000 },
30121 - { 0x0000137c, 0x00000000 },
30122 - { 0x000013bc, 0x00000000 },
30123 - { 0x000013fc, 0x00000000 },
30124 - { 0x0000143c, 0x00000000 },
30125 - { 0x0000147c, 0x00000000 },
30126 - { 0x00004030, 0x00000002 },
30127 - { 0x0000403c, 0x00000002 },
30128 - { 0x00004024, 0x0000001f },
30129 - { 0x00004060, 0x00000000 },
30130 - { 0x00004064, 0x00000000 },
30131 - { 0x00007010, 0x00000033 },
30132 - { 0x00007020, 0x00000000 },
30133 - { 0x00007034, 0x00000002 },
30134 - { 0x00007038, 0x000004c2 },
30135 - { 0x00008004, 0x00000000 },
30136 - { 0x00008008, 0x00000000 },
30137 - { 0x0000800c, 0x00000000 },
30138 - { 0x00008018, 0x00000700 },
30139 - { 0x00008020, 0x00000000 },
30140 - { 0x00008038, 0x00000000 },
30141 - { 0x0000803c, 0x00000000 },
30142 - { 0x00008048, 0x40000000 },
30143 - { 0x00008054, 0x00000000 },
30144 - { 0x00008058, 0x00000000 },
30145 - { 0x0000805c, 0x000fc78f },
30146 - { 0x00008060, 0x0000000f },
30147 - { 0x00008064, 0x00000000 },
30148 - { 0x00008070, 0x00000000 },
30149 - { 0x000080c0, 0x2a80001a },
30150 - { 0x000080c4, 0x05dc01e0 },
30151 - { 0x000080c8, 0x1f402710 },
30152 - { 0x000080cc, 0x01f40000 },
30153 - { 0x000080d0, 0x00001e00 },
30154 - { 0x000080d4, 0x00000000 },
30155 - { 0x000080d8, 0x00400000 },
30156 - { 0x000080e0, 0xffffffff },
30157 - { 0x000080e4, 0x0000ffff },
30158 - { 0x000080e8, 0x003f3f3f },
30159 - { 0x000080ec, 0x00000000 },
30160 - { 0x000080f0, 0x00000000 },
30161 - { 0x000080f4, 0x00000000 },
30162 - { 0x000080f8, 0x00000000 },
30163 - { 0x000080fc, 0x00020000 },
30164 - { 0x00008100, 0x00020000 },
30165 - { 0x00008104, 0x00000001 },
30166 - { 0x00008108, 0x00000052 },
30167 - { 0x0000810c, 0x00000000 },
30168 - { 0x00008110, 0x00000168 },
30169 - { 0x00008118, 0x000100aa },
30170 - { 0x0000811c, 0x00003210 },
30171 - { 0x00008124, 0x00000000 },
30172 - { 0x00008128, 0x00000000 },
30173 - { 0x0000812c, 0x00000000 },
30174 - { 0x00008130, 0x00000000 },
30175 - { 0x00008134, 0x00000000 },
30176 - { 0x00008138, 0x00000000 },
30177 - { 0x0000813c, 0x00000000 },
30178 - { 0x00008144, 0xffffffff },
30179 - { 0x00008168, 0x00000000 },
30180 - { 0x0000816c, 0x00000000 },
30181 - { 0x00008170, 0x18487320 },
30182 - { 0x00008174, 0xfaa4fa50 },
30183 - { 0x00008178, 0x00000100 },
30184 - { 0x0000817c, 0x00000000 },
30185 - { 0x000081c0, 0x00000000 },
30186 - { 0x000081c4, 0x00000000 },
30187 - { 0x000081d4, 0x00000000 },
30188 - { 0x000081ec, 0x00000000 },
30189 - { 0x000081f0, 0x00000000 },
30190 - { 0x000081f4, 0x00000000 },
30191 - { 0x000081f8, 0x00000000 },
30192 - { 0x000081fc, 0x00000000 },
30193 - { 0x00008200, 0x00000000 },
30194 - { 0x00008204, 0x00000000 },
30195 - { 0x00008208, 0x00000000 },
30196 - { 0x0000820c, 0x00000000 },
30197 - { 0x00008210, 0x00000000 },
30198 - { 0x00008214, 0x00000000 },
30199 - { 0x00008218, 0x00000000 },
30200 - { 0x0000821c, 0x00000000 },
30201 - { 0x00008220, 0x00000000 },
30202 - { 0x00008224, 0x00000000 },
30203 - { 0x00008228, 0x00000000 },
30204 - { 0x0000822c, 0x00000000 },
30205 - { 0x00008230, 0x00000000 },
30206 - { 0x00008234, 0x00000000 },
30207 - { 0x00008238, 0x00000000 },
30208 - { 0x0000823c, 0x00000000 },
30209 - { 0x00008240, 0x00100000 },
30210 - { 0x00008244, 0x0010f400 },
30211 - { 0x00008248, 0x00000100 },
30212 - { 0x0000824c, 0x0001e800 },
30213 - { 0x00008250, 0x00000000 },
30214 - { 0x00008254, 0x00000000 },
30215 - { 0x00008258, 0x00000000 },
30216 - { 0x0000825c, 0x400000ff },
30217 - { 0x00008260, 0x00080922 },
30218 - { 0x00008264, 0x88a00010 },
30219 - { 0x00008270, 0x00000000 },
30220 - { 0x00008274, 0x40000000 },
30221 - { 0x00008278, 0x003e4180 },
30222 - { 0x0000827c, 0x00000000 },
30223 - { 0x00008284, 0x0000002c },
30224 - { 0x00008288, 0x0000002c },
30225 - { 0x0000828c, 0x000000ff },
30226 - { 0x00008294, 0x00000000 },
30227 - { 0x00008298, 0x00000000 },
30228 - { 0x0000829c, 0x00000000 },
30229 - { 0x00008300, 0x00000040 },
30230 - { 0x00008314, 0x00000000 },
30231 - { 0x00008328, 0x00000000 },
30232 - { 0x0000832c, 0x00000007 },
30233 - { 0x00008330, 0x00000302 },
30234 - { 0x00008334, 0x00000e00 },
30235 - { 0x00008338, 0x00ff0000 },
30236 - { 0x0000833c, 0x00000000 },
30237 - { 0x00008340, 0x000107ff },
30238 - { 0x00008344, 0x01c81043 },
30239 - { 0x00008360, 0xffffffff },
30240 - { 0x00008364, 0xffffffff },
30241 - { 0x00008368, 0x00000000 },
30242 - { 0x00008370, 0x00000000 },
30243 - { 0x00008374, 0x000000ff },
30244 - { 0x00008378, 0x00000000 },
30245 - { 0x0000837c, 0x00000000 },
30246 - { 0x00008380, 0xffffffff },
30247 - { 0x00008384, 0xffffffff },
30248 - { 0x00008390, 0x0fffffff },
30249 - { 0x00008394, 0x0fffffff },
30250 - { 0x00008398, 0x00000000 },
30251 - { 0x0000839c, 0x00000000 },
30252 - { 0x000083a0, 0x00000000 },
30253 - { 0x00009808, 0x00000000 },
30254 - { 0x0000980c, 0xafe68e30 },
30255 - { 0x00009810, 0xfd14e000 },
30256 - { 0x00009814, 0x9c0a9f6b },
30257 - { 0x0000981c, 0x00000000 },
30258 - { 0x0000982c, 0x0000a000 },
30259 - { 0x00009830, 0x00000000 },
30260 - { 0x0000983c, 0x00200400 },
30261 - { 0x0000984c, 0x0040233c },
30262 - { 0x0000a84c, 0x0040233c },
30263 - { 0x00009854, 0x00000044 },
30264 - { 0x00009900, 0x00000000 },
30265 - { 0x00009904, 0x00000000 },
30266 - { 0x00009908, 0x00000000 },
30267 - { 0x0000990c, 0x00000000 },
30268 - { 0x00009910, 0x10002310 },
30269 - { 0x0000991c, 0x10000fff },
30270 - { 0x00009920, 0x04900000 },
30271 - { 0x0000a920, 0x04900000 },
30272 - { 0x00009928, 0x00000001 },
30273 - { 0x0000992c, 0x00000004 },
30274 - { 0x00009930, 0x00000000 },
30275 - { 0x0000a930, 0x00000000 },
30276 - { 0x00009934, 0x1e1f2022 },
30277 - { 0x00009938, 0x0a0b0c0d },
30278 - { 0x0000993c, 0x00000000 },
30279 - { 0x00009948, 0x9280c00a },
30280 - { 0x0000994c, 0x00020028 },
30281 - { 0x00009954, 0x5f3ca3de },
30282 - { 0x00009958, 0x0108ecff },
30283 - { 0x00009940, 0x14750604 },
30284 - { 0x0000c95c, 0x004b6a8e },
30285 - { 0x00009970, 0x990bb514 },
30286 - { 0x00009974, 0x00000000 },
30287 - { 0x00009978, 0x00000001 },
30288 - { 0x0000997c, 0x00000000 },
30289 - { 0x000099a0, 0x00000000 },
30290 - { 0x000099a4, 0x00000001 },
30291 - { 0x000099a8, 0x201fff00 },
30292 - { 0x000099ac, 0x0c6f0000 },
30293 - { 0x000099b0, 0x03051000 },
30294 - { 0x000099b4, 0x00000820 },
30295 - { 0x000099c4, 0x06336f77 },
30296 - { 0x000099c8, 0x6af6532f },
30297 - { 0x000099cc, 0x08f186c8 },
30298 - { 0x000099d0, 0x00046384 },
30299 - { 0x000099dc, 0x00000000 },
30300 - { 0x000099e0, 0x00000000 },
30301 - { 0x000099e4, 0xaaaaaaaa },
30302 - { 0x000099e8, 0x3c466478 },
30303 - { 0x000099ec, 0x0cc80caa },
30304 - { 0x000099f0, 0x00000000 },
30305 - { 0x000099fc, 0x00001042 },
30306 - { 0x0000a208, 0x803e4788 },
30307 - { 0x0000a210, 0x4080a333 },
30308 - { 0x0000a214, 0x40206c10 },
30309 - { 0x0000a218, 0x009c4060 },
30310 - { 0x0000a220, 0x01834061 },
30311 - { 0x0000a224, 0x00000400 },
30312 - { 0x0000a228, 0x000003b5 },
30313 - { 0x0000a22c, 0x233f7180 },
30314 - { 0x0000a234, 0x20202020 },
30315 - { 0x0000a238, 0x20202020 },
30316 - { 0x0000a23c, 0x13c889af },
30317 - { 0x0000a240, 0x38490a20 },
30318 - { 0x0000a244, 0x00000000 },
30319 - { 0x0000a248, 0xfffffffc },
30320 - { 0x0000a24c, 0x00000000 },
30321 - { 0x0000a254, 0x00000000 },
30322 - { 0x0000a258, 0x0cdbd380 },
30323 - { 0x0000a25c, 0x0f0f0f01 },
30324 - { 0x0000a260, 0xdfa91f01 },
30325 - { 0x0000a264, 0x00418a11 },
30326 - { 0x0000b264, 0x00418a11 },
30327 - { 0x0000a268, 0x00000000 },
30328 - { 0x0000a26c, 0x0e79e5c6 },
30329 - { 0x0000b26c, 0x0e79e5c6 },
30330 - { 0x0000d270, 0x00820820 },
30331 - { 0x0000a278, 0x1ce739ce },
30332 - { 0x0000a27c, 0x050701ce },
30333 - { 0x0000d35c, 0x07ffffef },
30334 - { 0x0000d360, 0x0fffffe7 },
30335 - { 0x0000d364, 0x17ffffe5 },
30336 - { 0x0000d368, 0x1fffffe4 },
30337 - { 0x0000d36c, 0x37ffffe3 },
30338 - { 0x0000d370, 0x3fffffe3 },
30339 - { 0x0000d374, 0x57ffffe3 },
30340 - { 0x0000d378, 0x5fffffe2 },
30341 - { 0x0000d37c, 0x7fffffe2 },
30342 - { 0x0000d380, 0x7f3c7bba },
30343 - { 0x0000d384, 0xf3307ff0 },
30344 - { 0x0000a388, 0x0c000000 },
30345 - { 0x0000a38c, 0x20202020 },
30346 - { 0x0000a390, 0x20202020 },
30347 - { 0x0000a394, 0x1ce739ce },
30348 - { 0x0000a398, 0x000001ce },
30349 - { 0x0000b398, 0x000001ce },
30350 - { 0x0000a39c, 0x00000001 },
30351 - { 0x0000a3c8, 0x00000246 },
30352 - { 0x0000a3cc, 0x20202020 },
30353 - { 0x0000a3d0, 0x20202020 },
30354 - { 0x0000a3d4, 0x20202020 },
30355 - { 0x0000a3dc, 0x1ce739ce },
30356 - { 0x0000a3e0, 0x000001ce },
30357 - { 0x0000a3e4, 0x00000000 },
30358 - { 0x0000a3e8, 0x18c43433 },
30359 - { 0x0000a3ec, 0x00f70081 },
30360 - { 0x0000a3f0, 0x01036a1e },
30361 - { 0x0000a3f4, 0x00000000 },
30362 - { 0x0000b3f4, 0x00000000 },
30363 - { 0x0000a7d8, 0x000003f1 },
30364 - { 0x00007800, 0x00000800 },
30365 - { 0x00007804, 0x6c35ffd2 },
30366 - { 0x00007808, 0x6db6c000 },
30367 - { 0x0000780c, 0x6db6cb30 },
30368 - { 0x00007810, 0x6db6cb6c },
30369 - { 0x00007814, 0x0501e200 },
30370 - { 0x00007818, 0x0094128d },
30371 - { 0x0000781c, 0x976ee392 },
30372 - { 0x00007820, 0xf75ff6fc },
30373 - { 0x00007824, 0x00040000 },
30374 - { 0x00007828, 0xdb003012 },
30375 - { 0x0000782c, 0x04924914 },
30376 - { 0x00007830, 0x21084210 },
30377 - { 0x00007834, 0x00140000 },
30378 - { 0x00007838, 0x0e4548d8 },
30379 - { 0x0000783c, 0x54214514 },
30380 - { 0x00007840, 0x02025830 },
30381 - { 0x00007844, 0x71c0d388 },
30382 - { 0x00007848, 0x934934a8 },
30383 - { 0x00007850, 0x00000000 },
30384 - { 0x00007854, 0x00000800 },
30385 - { 0x00007858, 0x6c35ffd2 },
30386 - { 0x0000785c, 0x6db6c000 },
30387 - { 0x00007860, 0x6db6cb30 },
30388 - { 0x00007864, 0x6db6cb6c },
30389 - { 0x00007868, 0x0501e200 },
30390 - { 0x0000786c, 0x0094128d },
30391 - { 0x00007870, 0x976ee392 },
30392 - { 0x00007874, 0xf75ff6fc },
30393 - { 0x00007878, 0x00040000 },
30394 - { 0x0000787c, 0xdb003012 },
30395 - { 0x00007880, 0x04924914 },
30396 - { 0x00007884, 0x21084210 },
30397 - { 0x00007888, 0x001b6db0 },
30398 - { 0x0000788c, 0x00376b63 },
30399 - { 0x00007890, 0x06db6db6 },
30400 - { 0x00007894, 0x006d8000 },
30401 - { 0x00007898, 0x48100000 },
30402 - { 0x0000789c, 0x00000000 },
30403 - { 0x000078a0, 0x08000000 },
30404 - { 0x000078a4, 0x0007ffd8 },
30405 - { 0x000078a8, 0x0007ffd8 },
30406 - { 0x000078ac, 0x001c0020 },
30407 - { 0x000078b0, 0x00060aeb },
30408 - { 0x000078b4, 0x40008080 },
30409 - { 0x000078b8, 0x2a850160 },
30410 -};
30411 -
30412 -/*
30413 - * For Japanese regulatory requirements, 2484 MHz requires the following three
30414 - * registers be programmed differently from the channel between 2412 and 2472 MHz.
30415 - */
30416 -static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
30417 - { 0x0000a1f4, 0x00fffeff },
30418 - { 0x0000a1f8, 0x00f5f9ff },
30419 - { 0x0000a1fc, 0xb79f6427 },
30420 -};
30421 -
30422 -static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
30423 - { 0x0000a1f4, 0x00000000 },
30424 - { 0x0000a1f8, 0xefff0301 },
30425 - { 0x0000a1fc, 0xca9228ee },
30426 -};
30427 -
30428 -static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
30429 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
30430 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30431 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
30432 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
30433 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
30434 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
30435 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
30436 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
30437 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
30438 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
30439 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
30440 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
30441 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
30442 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
30443 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
30444 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
30445 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
30446 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
30447 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
30448 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
30449 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
30450 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
30451 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
30452 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
30453 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
30454 - { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
30455 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
30456 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
30457 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
30458 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
30459 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
30460 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
30461 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
30462 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
30463 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
30464 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30465 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30466 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30467 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30468 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30469 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30470 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30471 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30472 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30473 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
30474 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
30475 -};
30476 -
30477 -static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
30478 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
30479 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
30480 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
30481 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
30482 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
30483 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
30484 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
30485 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
30486 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
30487 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
30488 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
30489 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
30490 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
30491 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
30492 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
30493 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
30494 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
30495 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
30496 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
30497 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
30498 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
30499 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
30500 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
30501 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
30502 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
30503 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
30504 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
30505 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
30506 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
30507 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
30508 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
30509 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
30510 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
30511 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
30512 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
30513 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
30514 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
30515 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
30516 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
30517 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
30518 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
30519 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
30520 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
30521 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
30522 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
30523 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
30524 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
30525 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
30526 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
30527 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
30528 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
30529 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
30530 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
30531 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
30532 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
30533 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
30534 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
30535 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
30536 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
30537 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
30538 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
30539 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
30540 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
30541 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
30542 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
30543 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
30544 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
30545 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
30546 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
30547 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
30548 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
30549 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
30550 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
30551 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
30552 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
30553 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
30554 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
30555 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
30556 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
30557 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
30558 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
30559 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
30560 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
30561 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
30562 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
30563 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
30564 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
30565 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
30566 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
30567 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
30568 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
30569 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
30570 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
30571 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
30572 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
30573 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
30574 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
30575 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
30576 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
30577 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
30578 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
30579 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
30580 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
30581 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
30582 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30583 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30584 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30585 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30586 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30587 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30588 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30589 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30590 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30591 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30592 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30593 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30594 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30595 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30596 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30597 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30598 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30599 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30600 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30601 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30602 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30603 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30604 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30605 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30606 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30607 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
30608 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
30609 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
30610 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
30611 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
30612 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
30613 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
30614 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
30615 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
30616 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
30617 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
30618 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
30619 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
30620 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
30621 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
30622 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
30623 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
30624 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
30625 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
30626 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
30627 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
30628 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
30629 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
30630 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
30631 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
30632 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
30633 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
30634 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
30635 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
30636 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
30637 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
30638 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
30639 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
30640 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
30641 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
30642 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
30643 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
30644 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
30645 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
30646 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
30647 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
30648 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
30649 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
30650 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
30651 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
30652 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
30653 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
30654 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
30655 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
30656 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
30657 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
30658 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
30659 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
30660 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
30661 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
30662 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
30663 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
30664 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
30665 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
30666 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
30667 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
30668 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
30669 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
30670 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
30671 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
30672 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
30673 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
30674 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
30675 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
30676 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
30677 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
30678 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
30679 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
30680 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
30681 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
30682 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
30683 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
30684 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
30685 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
30686 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
30687 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
30688 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
30689 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
30690 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
30691 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
30692 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
30693 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
30694 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
30695 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
30696 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
30697 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
30698 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
30699 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
30700 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
30701 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
30702 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
30703 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
30704 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
30705 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
30706 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
30707 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
30708 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
30709 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
30710 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30711 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30712 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30713 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30714 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30715 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30716 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30717 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30718 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30719 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30720 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30721 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30722 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30723 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30724 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30725 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30726 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30727 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30728 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30729 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30730 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30731 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30732 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30733 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30734 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
30735 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
30736 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
30737 -};
30738 -
30739 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
30740 - {0x00004040, 0x9248fd00 },
30741 - {0x00004040, 0x24924924 },
30742 - {0x00004040, 0xa8000019 },
30743 - {0x00004040, 0x13160820 },
30744 - {0x00004040, 0xe5980560 },
30745 - {0x00004040, 0xc01dcffd },
30746 - {0x00004040, 0x1aaabe41 },
30747 - {0x00004040, 0xbe105554 },
30748 - {0x00004040, 0x00043007 },
30749 - {0x00004044, 0x00000000 },
30750 -};
30751 -
30752 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
30753 - {0x00004040, 0x9248fd00 },
30754 - {0x00004040, 0x24924924 },
30755 - {0x00004040, 0xa8000019 },
30756 - {0x00004040, 0x13160820 },
30757 - {0x00004040, 0xe5980560 },
30758 - {0x00004040, 0xc01dcffc },
30759 - {0x00004040, 0x1aaabe41 },
30760 - {0x00004040, 0xbe105554 },
30761 - {0x00004040, 0x00043007 },
30762 - {0x00004044, 0x00000000 },
30763 -};
30764 -
30765 -
30766 -/* AR9271 initialization values automaticaly created: 06/04/09 */
30767 -static const u_int32_t ar9271Modes_9271[][6] = {
30768 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
30769 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
30770 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
30771 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
30772 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
30773 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
30774 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
30775 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30776 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
30777 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
30778 - { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
30779 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30780 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
30781 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
30782 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
30783 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
30784 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
30785 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
30786 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
30787 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
30788 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
30789 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
30790 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
30791 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
30792 - { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
30793 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
30794 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
30795 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
30796 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
30797 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30798 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30799 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
30800 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
30801 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
30802 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
30803 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
30804 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
30805 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
30806 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30807 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30808 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
30809 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
30810 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
30811 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
30812 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
30813 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
30814 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
30815 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
30816 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
30817 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
30818 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
30819 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
30820 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
30821 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
30822 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
30823 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
30824 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
30825 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
30826 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
30827 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
30828 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
30829 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
30830 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
30831 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
30832 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
30833 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
30834 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
30835 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
30836 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30837 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30838 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30839 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30840 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30841 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30842 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
30843 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
30844 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
30845 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
30846 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
30847 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
30848 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
30849 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
30850 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
30851 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
30852 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
30853 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
30854 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
30855 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
30856 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
30857 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
30858 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
30859 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
30860 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
30861 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
30862 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
30863 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
30864 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
30865 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
30866 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
30867 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
30868 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
30869 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
30870 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
30871 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
30872 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
30873 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
30874 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
30875 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
30876 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
30877 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
30878 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
30879 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
30880 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
30881 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
30882 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
30883 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
30884 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
30885 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
30886 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
30887 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
30888 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
30889 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
30890 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
30891 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
30892 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
30893 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
30894 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
30895 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
30896 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
30897 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30898 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30899 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30900 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30901 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30902 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30903 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30904 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30905 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30906 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30907 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30908 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30909 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30910 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30911 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30912 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30913 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30914 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30915 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30916 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30917 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30918 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30919 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30920 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30921 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30922 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30923 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30924 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30925 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30926 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30927 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30928 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30929 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30930 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30931 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30932 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30933 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30934 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30935 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
30936 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
30937 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
30938 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
30939 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
30940 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
30941 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
30942 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
30943 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
30944 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
30945 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
30946 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
30947 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
30948 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
30949 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
30950 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
30951 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
30952 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
30953 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
30954 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
30955 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
30956 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
30957 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
30958 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
30959 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
30960 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
30961 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
30962 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
30963 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
30964 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30965 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30966 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30967 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30968 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30969 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30970 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
30971 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
30972 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
30973 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
30974 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
30975 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
30976 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
30977 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
30978 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
30979 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
30980 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
30981 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
30982 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
30983 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
30984 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
30985 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
30986 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
30987 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
30988 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
30989 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
30990 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
30991 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
30992 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
30993 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
30994 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
30995 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
30996 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
30997 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
30998 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
30999 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
31000 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
31001 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
31002 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
31003 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
31004 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
31005 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
31006 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
31007 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
31008 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
31009 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
31010 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
31011 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
31012 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
31013 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
31014 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
31015 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
31016 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
31017 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
31018 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
31019 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
31020 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
31021 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
31022 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
31023 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
31024 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
31025 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31026 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31027 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31028 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31029 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31030 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31031 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31032 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31033 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31034 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31035 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31036 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31037 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31038 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31039 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31040 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31041 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31042 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31043 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31044 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31045 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31046 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31047 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31048 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31049 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31050 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31051 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31052 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31053 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31054 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31055 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31056 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31057 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31058 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31059 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31060 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31061 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31062 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31063 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31064 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
31065 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31066 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31067 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
31068 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
31069 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
31070 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
31071 -};
31072 -
31073 -static const u_int32_t ar9271Common_9271[][2] = {
31074 - { 0x0000000c, 0x00000000 },
31075 - { 0x00000030, 0x00020045 },
31076 - { 0x00000034, 0x00000005 },
31077 - { 0x00000040, 0x00000000 },
31078 - { 0x00000044, 0x00000008 },
31079 - { 0x00000048, 0x00000008 },
31080 - { 0x0000004c, 0x00000010 },
31081 - { 0x00000050, 0x00000000 },
31082 - { 0x00000054, 0x0000001f },
31083 - { 0x00000800, 0x00000000 },
31084 - { 0x00000804, 0x00000000 },
31085 - { 0x00000808, 0x00000000 },
31086 - { 0x0000080c, 0x00000000 },
31087 - { 0x00000810, 0x00000000 },
31088 - { 0x00000814, 0x00000000 },
31089 - { 0x00000818, 0x00000000 },
31090 - { 0x0000081c, 0x00000000 },
31091 - { 0x00000820, 0x00000000 },
31092 - { 0x00000824, 0x00000000 },
31093 - { 0x00001040, 0x002ffc0f },
31094 - { 0x00001044, 0x002ffc0f },
31095 - { 0x00001048, 0x002ffc0f },
31096 - { 0x0000104c, 0x002ffc0f },
31097 - { 0x00001050, 0x002ffc0f },
31098 - { 0x00001054, 0x002ffc0f },
31099 - { 0x00001058, 0x002ffc0f },
31100 - { 0x0000105c, 0x002ffc0f },
31101 - { 0x00001060, 0x002ffc0f },
31102 - { 0x00001064, 0x002ffc0f },
31103 - { 0x00001230, 0x00000000 },
31104 - { 0x00001270, 0x00000000 },
31105 - { 0x00001038, 0x00000000 },
31106 - { 0x00001078, 0x00000000 },
31107 - { 0x000010b8, 0x00000000 },
31108 - { 0x000010f8, 0x00000000 },
31109 - { 0x00001138, 0x00000000 },
31110 - { 0x00001178, 0x00000000 },
31111 - { 0x000011b8, 0x00000000 },
31112 - { 0x000011f8, 0x00000000 },
31113 - { 0x00001238, 0x00000000 },
31114 - { 0x00001278, 0x00000000 },
31115 - { 0x000012b8, 0x00000000 },
31116 - { 0x000012f8, 0x00000000 },
31117 - { 0x00001338, 0x00000000 },
31118 - { 0x00001378, 0x00000000 },
31119 - { 0x000013b8, 0x00000000 },
31120 - { 0x000013f8, 0x00000000 },
31121 - { 0x00001438, 0x00000000 },
31122 - { 0x00001478, 0x00000000 },
31123 - { 0x000014b8, 0x00000000 },
31124 - { 0x000014f8, 0x00000000 },
31125 - { 0x00001538, 0x00000000 },
31126 - { 0x00001578, 0x00000000 },
31127 - { 0x000015b8, 0x00000000 },
31128 - { 0x000015f8, 0x00000000 },
31129 - { 0x00001638, 0x00000000 },
31130 - { 0x00001678, 0x00000000 },
31131 - { 0x000016b8, 0x00000000 },
31132 - { 0x000016f8, 0x00000000 },
31133 - { 0x00001738, 0x00000000 },
31134 - { 0x00001778, 0x00000000 },
31135 - { 0x000017b8, 0x00000000 },
31136 - { 0x000017f8, 0x00000000 },
31137 - { 0x0000103c, 0x00000000 },
31138 - { 0x0000107c, 0x00000000 },
31139 - { 0x000010bc, 0x00000000 },
31140 - { 0x000010fc, 0x00000000 },
31141 - { 0x0000113c, 0x00000000 },
31142 - { 0x0000117c, 0x00000000 },
31143 - { 0x000011bc, 0x00000000 },
31144 - { 0x000011fc, 0x00000000 },
31145 - { 0x0000123c, 0x00000000 },
31146 - { 0x0000127c, 0x00000000 },
31147 - { 0x000012bc, 0x00000000 },
31148 - { 0x000012fc, 0x00000000 },
31149 - { 0x0000133c, 0x00000000 },
31150 - { 0x0000137c, 0x00000000 },
31151 - { 0x000013bc, 0x00000000 },
31152 - { 0x000013fc, 0x00000000 },
31153 - { 0x0000143c, 0x00000000 },
31154 - { 0x0000147c, 0x00000000 },
31155 - { 0x00004030, 0x00000002 },
31156 - { 0x0000403c, 0x00000002 },
31157 - { 0x00004024, 0x0000001f },
31158 - { 0x00004060, 0x00000000 },
31159 - { 0x00004064, 0x00000000 },
31160 - { 0x00008004, 0x00000000 },
31161 - { 0x00008008, 0x00000000 },
31162 - { 0x0000800c, 0x00000000 },
31163 - { 0x00008018, 0x00000700 },
31164 - { 0x00008020, 0x00000000 },
31165 - { 0x00008038, 0x00000000 },
31166 - { 0x0000803c, 0x00000000 },
31167 - { 0x00008048, 0x00000000 },
31168 - { 0x00008054, 0x00000000 },
31169 - { 0x00008058, 0x00000000 },
31170 - { 0x0000805c, 0x000fc78f },
31171 - { 0x00008060, 0x0000000f },
31172 - { 0x00008064, 0x00000000 },
31173 - { 0x00008070, 0x00000000 },
31174 - { 0x000080b0, 0x00000000 },
31175 - { 0x000080b4, 0x00000000 },
31176 - { 0x000080b8, 0x00000000 },
31177 - { 0x000080bc, 0x00000000 },
31178 - { 0x000080c0, 0x2a80001a },
31179 - { 0x000080c4, 0x05dc01e0 },
31180 - { 0x000080c8, 0x1f402710 },
31181 - { 0x000080cc, 0x01f40000 },
31182 - { 0x000080d0, 0x00001e00 },
31183 - { 0x000080d4, 0x00000000 },
31184 - { 0x000080d8, 0x00400000 },
31185 - { 0x000080e0, 0xffffffff },
31186 - { 0x000080e4, 0x0000ffff },
31187 - { 0x000080e8, 0x003f3f3f },
31188 - { 0x000080ec, 0x00000000 },
31189 - { 0x000080f0, 0x00000000 },
31190 - { 0x000080f4, 0x00000000 },
31191 - { 0x000080f8, 0x00000000 },
31192 - { 0x000080fc, 0x00020000 },
31193 - { 0x00008100, 0x00020000 },
31194 - { 0x00008104, 0x00000001 },
31195 - { 0x00008108, 0x00000052 },
31196 - { 0x0000810c, 0x00000000 },
31197 - { 0x00008110, 0x00000168 },
31198 - { 0x00008118, 0x000100aa },
31199 - { 0x0000811c, 0x00003210 },
31200 - { 0x00008120, 0x08f04810 },
31201 - { 0x00008124, 0x00000000 },
31202 - { 0x00008128, 0x00000000 },
31203 - { 0x0000812c, 0x00000000 },
31204 - { 0x00008130, 0x00000000 },
31205 - { 0x00008134, 0x00000000 },
31206 - { 0x00008138, 0x00000000 },
31207 - { 0x0000813c, 0x00000000 },
31208 - { 0x00008144, 0xffffffff },
31209 - { 0x00008168, 0x00000000 },
31210 - { 0x0000816c, 0x00000000 },
31211 - { 0x00008170, 0x32143320 },
31212 - { 0x00008174, 0xfaa4fa50 },
31213 - { 0x00008178, 0x00000100 },
31214 - { 0x0000817c, 0x00000000 },
31215 - { 0x000081c0, 0x00000000 },
31216 - { 0x000081d0, 0x0000320a },
31217 - { 0x000081ec, 0x00000000 },
31218 - { 0x000081f0, 0x00000000 },
31219 - { 0x000081f4, 0x00000000 },
31220 - { 0x000081f8, 0x00000000 },
31221 - { 0x000081fc, 0x00000000 },
31222 - { 0x00008200, 0x00000000 },
31223 - { 0x00008204, 0x00000000 },
31224 - { 0x00008208, 0x00000000 },
31225 - { 0x0000820c, 0x00000000 },
31226 - { 0x00008210, 0x00000000 },
31227 - { 0x00008214, 0x00000000 },
31228 - { 0x00008218, 0x00000000 },
31229 - { 0x0000821c, 0x00000000 },
31230 - { 0x00008220, 0x00000000 },
31231 - { 0x00008224, 0x00000000 },
31232 - { 0x00008228, 0x00000000 },
31233 - { 0x0000822c, 0x00000000 },
31234 - { 0x00008230, 0x00000000 },
31235 - { 0x00008234, 0x00000000 },
31236 - { 0x00008238, 0x00000000 },
31237 - { 0x0000823c, 0x00000000 },
31238 - { 0x00008240, 0x00100000 },
31239 - { 0x00008244, 0x0010f400 },
31240 - { 0x00008248, 0x00000100 },
31241 - { 0x0000824c, 0x0001e800 },
31242 - { 0x00008250, 0x00000000 },
31243 - { 0x00008254, 0x00000000 },
31244 - { 0x00008258, 0x00000000 },
31245 - { 0x0000825c, 0x400000ff },
31246 - { 0x00008260, 0x00080922 },
31247 - { 0x00008264, 0xa8a00010 },
31248 - { 0x00008270, 0x00000000 },
31249 - { 0x00008274, 0x40000000 },
31250 - { 0x00008278, 0x003e4180 },
31251 - { 0x0000827c, 0x00000000 },
31252 - { 0x00008284, 0x0000002c },
31253 - { 0x00008288, 0x0000002c },
31254 - { 0x0000828c, 0x00000000 },
31255 - { 0x00008294, 0x00000000 },
31256 - { 0x00008298, 0x00000000 },
31257 - { 0x0000829c, 0x00000000 },
31258 - { 0x00008300, 0x00000040 },
31259 - { 0x00008314, 0x00000000 },
31260 - { 0x00008328, 0x00000000 },
31261 - { 0x0000832c, 0x00000001 },
31262 - { 0x00008330, 0x00000302 },
31263 - { 0x00008334, 0x00000e00 },
31264 - { 0x00008338, 0x00ff0000 },
31265 - { 0x0000833c, 0x00000000 },
31266 - { 0x00008340, 0x00010380 },
31267 - { 0x00008344, 0x00581043 },
31268 - { 0x00007010, 0x00000030 },
31269 - { 0x00007034, 0x00000002 },
31270 - { 0x00007038, 0x000004c2 },
31271 - { 0x00007800, 0x00140000 },
31272 - { 0x00007804, 0x0e4548d8 },
31273 - { 0x00007808, 0x54214514 },
31274 - { 0x0000780c, 0x02025820 },
31275 - { 0x00007810, 0x71c0d388 },
31276 - { 0x00007814, 0x924934a8 },
31277 - { 0x0000781c, 0x00000000 },
31278 - { 0x00007828, 0x66964300 },
31279 - { 0x0000782c, 0x8db6d961 },
31280 - { 0x00007830, 0x8db6d96c },
31281 - { 0x00007834, 0x6140008b },
31282 - { 0x0000783c, 0x72ee0a72 },
31283 - { 0x00007840, 0xbbfffffc },
31284 - { 0x00007844, 0x000c0db6 },
31285 - { 0x00007848, 0x6db61b6f },
31286 - { 0x0000784c, 0x6d9b66db },
31287 - { 0x00007850, 0x6d8c6dba },
31288 - { 0x00007854, 0x00040000 },
31289 - { 0x00007858, 0xdb003012 },
31290 - { 0x0000785c, 0x04924914 },
31291 - { 0x00007860, 0x21084210 },
31292 - { 0x00007864, 0xf7d7ffde },
31293 - { 0x00007868, 0xc2034080 },
31294 - { 0x00007870, 0x10142c00 },
31295 - { 0x00009808, 0x00000000 },
31296 - { 0x0000980c, 0xafe68e30 },
31297 - { 0x00009810, 0xfd14e000 },
31298 - { 0x00009814, 0x9c0a9f6b },
31299 - { 0x0000981c, 0x00000000 },
31300 - { 0x0000982c, 0x0000a000 },
31301 - { 0x00009830, 0x00000000 },
31302 - { 0x0000983c, 0x00200400 },
31303 - { 0x0000984c, 0x0040233c },
31304 - { 0x00009854, 0x00000044 },
31305 - { 0x00009900, 0x00000000 },
31306 - { 0x00009904, 0x00000000 },
31307 - { 0x00009908, 0x00000000 },
31308 - { 0x0000990c, 0x00000000 },
31309 - { 0x0000991c, 0x10000fff },
31310 - { 0x00009920, 0x04900000 },
31311 - { 0x00009928, 0x00000001 },
31312 - { 0x0000992c, 0x00000004 },
31313 - { 0x00009934, 0x1e1f2022 },
31314 - { 0x00009938, 0x0a0b0c0d },
31315 - { 0x0000993c, 0x00000000 },
31316 - { 0x00009940, 0x14750604 },
31317 - { 0x00009948, 0x9280c00a },
31318 - { 0x0000994c, 0x00020028 },
31319 - { 0x00009954, 0x5f3ca3de },
31320 - { 0x00009958, 0x0108ecff },
31321 - { 0x00009968, 0x000003ce },
31322 - { 0x00009970, 0x192bb514 },
31323 - { 0x00009974, 0x00000000 },
31324 - { 0x00009978, 0x00000001 },
31325 - { 0x0000997c, 0x00000000 },
31326 - { 0x00009980, 0x00000000 },
31327 - { 0x00009984, 0x00000000 },
31328 - { 0x00009988, 0x00000000 },
31329 - { 0x0000998c, 0x00000000 },
31330 - { 0x00009990, 0x00000000 },
31331 - { 0x00009994, 0x00000000 },
31332 - { 0x00009998, 0x00000000 },
31333 - { 0x0000999c, 0x00000000 },
31334 - { 0x000099a0, 0x00000000 },
31335 - { 0x000099a4, 0x00000001 },
31336 - { 0x000099a8, 0x201fff00 },
31337 - { 0x000099ac, 0x2def0400 },
31338 - { 0x000099b0, 0x03051000 },
31339 - { 0x000099b4, 0x00000820 },
31340 - { 0x000099dc, 0x00000000 },
31341 - { 0x000099e0, 0x00000000 },
31342 - { 0x000099e4, 0xaaaaaaaa },
31343 - { 0x000099e8, 0x3c466478 },
31344 - { 0x000099ec, 0x0cc80caa },
31345 - { 0x000099f0, 0x00000000 },
31346 - { 0x0000a208, 0x803e68c8 },
31347 - { 0x0000a210, 0x4080a333 },
31348 - { 0x0000a214, 0x00206c10 },
31349 - { 0x0000a218, 0x009c4060 },
31350 - { 0x0000a220, 0x01834061 },
31351 - { 0x0000a224, 0x00000400 },
31352 - { 0x0000a228, 0x000003b5 },
31353 - { 0x0000a22c, 0x00000000 },
31354 - { 0x0000a234, 0x20202020 },
31355 - { 0x0000a238, 0x20202020 },
31356 - { 0x0000a244, 0x00000000 },
31357 - { 0x0000a248, 0xfffffffc },
31358 - { 0x0000a24c, 0x00000000 },
31359 - { 0x0000a254, 0x00000000 },
31360 - { 0x0000a258, 0x0ccb5380 },
31361 - { 0x0000a25c, 0x15151501 },
31362 - { 0x0000a260, 0xdfa90f01 },
31363 - { 0x0000a268, 0x00000000 },
31364 - { 0x0000a26c, 0x0ebae9e6 },
31365 - { 0x0000a388, 0x0c000000 },
31366 - { 0x0000a38c, 0x20202020 },
31367 - { 0x0000a390, 0x20202020 },
31368 - { 0x0000a39c, 0x00000001 },
31369 - { 0x0000a3a0, 0x00000000 },
31370 - { 0x0000a3a4, 0x00000000 },
31371 - { 0x0000a3a8, 0x00000000 },
31372 - { 0x0000a3ac, 0x00000000 },
31373 - { 0x0000a3b0, 0x00000000 },
31374 - { 0x0000a3b4, 0x00000000 },
31375 - { 0x0000a3b8, 0x00000000 },
31376 - { 0x0000a3bc, 0x00000000 },
31377 - { 0x0000a3c0, 0x00000000 },
31378 - { 0x0000a3c4, 0x00000000 },
31379 - { 0x0000a3cc, 0x20202020 },
31380 - { 0x0000a3d0, 0x20202020 },
31381 - { 0x0000a3d4, 0x20202020 },
31382 - { 0x0000a3e4, 0x00000000 },
31383 - { 0x0000a3e8, 0x18c43433 },
31384 - { 0x0000a3ec, 0x00f70081 },
31385 - { 0x0000a3f0, 0x01036a2f },
31386 - { 0x0000a3f4, 0x00000000 },
31387 - { 0x0000d270, 0x0d820820 },
31388 - { 0x0000d35c, 0x07ffffef },
31389 - { 0x0000d360, 0x0fffffe7 },
31390 - { 0x0000d364, 0x17ffffe5 },
31391 - { 0x0000d368, 0x1fffffe4 },
31392 - { 0x0000d36c, 0x37ffffe3 },
31393 - { 0x0000d370, 0x3fffffe3 },
31394 - { 0x0000d374, 0x57ffffe3 },
31395 - { 0x0000d378, 0x5fffffe2 },
31396 - { 0x0000d37c, 0x7fffffe2 },
31397 - { 0x0000d380, 0x7f3c7bba },
31398 - { 0x0000d384, 0xf3307ff0 },
31399 -};
31400 -
31401 -static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
31402 - { 0x0000a1f4, 0x00fffeff },
31403 - { 0x0000a1f8, 0x00f5f9ff },
31404 - { 0x0000a1fc, 0xb79f6427 },
31405 -};
31406 -
31407 -static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
31408 - { 0x0000a1f4, 0x00000000 },
31409 - { 0x0000a1f8, 0xefff0301 },
31410 - { 0x0000a1fc, 0xca9228ee },
31411 -};
31412 -
31413 -static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
31414 - { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
31415 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
31416 -};
31417 -
31418 -static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
31419 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
31420 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
31421 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31422 - { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
31423 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31424 - { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
31425 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
31426 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31427 -};
31428 -
31429 -static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
31430 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31431 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31432 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31433 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31434 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
31435 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
31436 - { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
31437 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
31438 - { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
31439 - { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
31440 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
31441 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
31442 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
31443 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
31444 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31445 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31446 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31447 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31448 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31449 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31450 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31451 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31452 - { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
31453 - { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
31454 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31455 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31456 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
31457 - { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31458 - { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
31459 - { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31460 - { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
31461 - { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
31462 - { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
31463 -};
31464 -
31465 -static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
31466 - { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
31467 - { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
31468 - { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
31469 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
31470 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
31471 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
31472 - { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
31473 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
31474 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
31475 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
31476 - { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
31477 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
31478 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
31479 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
31480 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31481 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31482 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31483 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31484 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31485 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31486 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31487 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31488 - { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
31489 - { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
31490 - { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
31491 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31492 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
31493 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31494 - { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
31495 - { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
31496 - { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
31497 - { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
31498 - { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
31499 -};
31500 --- a/drivers/net/wireless/ath/ath9k/mac.c
31501 +++ b/drivers/net/wireless/ath/ath9k/mac.c
31502 @@ -57,6 +57,18 @@ void ath9k_hw_txstart(struct ath_hw *ah,
31503 }
31504 EXPORT_SYMBOL(ath9k_hw_txstart);
31505
31506 +void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
31507 +{
31508 + struct ar5416_desc *ads = AR5416DESC(ds);
31509 +
31510 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31511 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31512 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31513 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31514 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31515 +}
31516 +EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
31517 +
31518 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
31519 {
31520 u32 npend;
31521 @@ -207,281 +219,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *a
31522 }
31523 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
31524
31525 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
31526 - u32 segLen, bool firstSeg,
31527 - bool lastSeg, const struct ath_desc *ds0)
31528 -{
31529 - struct ar5416_desc *ads = AR5416DESC(ds);
31530 -
31531 - if (firstSeg) {
31532 - ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
31533 - } else if (lastSeg) {
31534 - ads->ds_ctl0 = 0;
31535 - ads->ds_ctl1 = segLen;
31536 - ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
31537 - ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
31538 - } else {
31539 - ads->ds_ctl0 = 0;
31540 - ads->ds_ctl1 = segLen | AR_TxMore;
31541 - ads->ds_ctl2 = 0;
31542 - ads->ds_ctl3 = 0;
31543 - }
31544 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31545 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31546 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31547 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31548 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31549 -}
31550 -EXPORT_SYMBOL(ath9k_hw_filltxdesc);
31551 -
31552 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
31553 -{
31554 - struct ar5416_desc *ads = AR5416DESC(ds);
31555 -
31556 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
31557 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
31558 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
31559 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
31560 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
31561 -}
31562 -EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
31563 -
31564 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
31565 - struct ath_tx_status *ts)
31566 -{
31567 - struct ar5416_desc *ads = AR5416DESC(ds);
31568 -
31569 - if ((ads->ds_txstatus9 & AR_TxDone) == 0)
31570 - return -EINPROGRESS;
31571 -
31572 - ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
31573 - ts->ts_tstamp = ads->AR_SendTimestamp;
31574 - ts->ts_status = 0;
31575 - ts->ts_flags = 0;
31576 -
31577 - if (ads->ds_txstatus1 & AR_FrmXmitOK)
31578 - ts->ts_status |= ATH9K_TX_ACKED;
31579 - if (ads->ds_txstatus1 & AR_ExcessiveRetries)
31580 - ts->ts_status |= ATH9K_TXERR_XRETRY;
31581 - if (ads->ds_txstatus1 & AR_Filtered)
31582 - ts->ts_status |= ATH9K_TXERR_FILT;
31583 - if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
31584 - ts->ts_status |= ATH9K_TXERR_FIFO;
31585 - ath9k_hw_updatetxtriglevel(ah, true);
31586 - }
31587 - if (ads->ds_txstatus9 & AR_TxOpExceeded)
31588 - ts->ts_status |= ATH9K_TXERR_XTXOP;
31589 - if (ads->ds_txstatus1 & AR_TxTimerExpired)
31590 - ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
31591 -
31592 - if (ads->ds_txstatus1 & AR_DescCfgErr)
31593 - ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
31594 - if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
31595 - ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
31596 - ath9k_hw_updatetxtriglevel(ah, true);
31597 - }
31598 - if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
31599 - ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
31600 - ath9k_hw_updatetxtriglevel(ah, true);
31601 - }
31602 - if (ads->ds_txstatus0 & AR_TxBaStatus) {
31603 - ts->ts_flags |= ATH9K_TX_BA;
31604 - ts->ba_low = ads->AR_BaBitmapLow;
31605 - ts->ba_high = ads->AR_BaBitmapHigh;
31606 - }
31607 -
31608 - ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
31609 - switch (ts->ts_rateindex) {
31610 - case 0:
31611 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
31612 - break;
31613 - case 1:
31614 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
31615 - break;
31616 - case 2:
31617 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
31618 - break;
31619 - case 3:
31620 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
31621 - break;
31622 - }
31623 -
31624 - ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
31625 - ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
31626 - ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
31627 - ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
31628 - ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
31629 - ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
31630 - ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
31631 - ts->evm0 = ads->AR_TxEVM0;
31632 - ts->evm1 = ads->AR_TxEVM1;
31633 - ts->evm2 = ads->AR_TxEVM2;
31634 - ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
31635 - ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
31636 - ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
31637 - ts->ts_antenna = 0;
31638 -
31639 - return 0;
31640 -}
31641 -EXPORT_SYMBOL(ath9k_hw_txprocdesc);
31642 -
31643 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
31644 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
31645 - u32 keyIx, enum ath9k_key_type keyType, u32 flags)
31646 -{
31647 - struct ar5416_desc *ads = AR5416DESC(ds);
31648 -
31649 - txPower += ah->txpower_indexoffset;
31650 - if (txPower > 63)
31651 - txPower = 63;
31652 -
31653 - ads->ds_ctl0 = (pktLen & AR_FrameLen)
31654 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
31655 - | SM(txPower, AR_XmitPower)
31656 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
31657 - | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
31658 - | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
31659 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
31660 -
31661 - ads->ds_ctl1 =
31662 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
31663 - | SM(type, AR_FrameType)
31664 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
31665 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
31666 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
31667 -
31668 - ads->ds_ctl6 = SM(keyType, AR_EncrType);
31669 -
31670 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
31671 - ads->ds_ctl8 = 0;
31672 - ads->ds_ctl9 = 0;
31673 - ads->ds_ctl10 = 0;
31674 - ads->ds_ctl11 = 0;
31675 - }
31676 -}
31677 -EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
31678 -
31679 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
31680 - struct ath_desc *lastds,
31681 - u32 durUpdateEn, u32 rtsctsRate,
31682 - u32 rtsctsDuration,
31683 - struct ath9k_11n_rate_series series[],
31684 - u32 nseries, u32 flags)
31685 -{
31686 - struct ar5416_desc *ads = AR5416DESC(ds);
31687 - struct ar5416_desc *last_ads = AR5416DESC(lastds);
31688 - u32 ds_ctl0;
31689 -
31690 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
31691 - ds_ctl0 = ads->ds_ctl0;
31692 -
31693 - if (flags & ATH9K_TXDESC_RTSENA) {
31694 - ds_ctl0 &= ~AR_CTSEnable;
31695 - ds_ctl0 |= AR_RTSEnable;
31696 - } else {
31697 - ds_ctl0 &= ~AR_RTSEnable;
31698 - ds_ctl0 |= AR_CTSEnable;
31699 - }
31700 -
31701 - ads->ds_ctl0 = ds_ctl0;
31702 - } else {
31703 - ads->ds_ctl0 =
31704 - (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
31705 - }
31706 -
31707 - ads->ds_ctl2 = set11nTries(series, 0)
31708 - | set11nTries(series, 1)
31709 - | set11nTries(series, 2)
31710 - | set11nTries(series, 3)
31711 - | (durUpdateEn ? AR_DurUpdateEna : 0)
31712 - | SM(0, AR_BurstDur);
31713 -
31714 - ads->ds_ctl3 = set11nRate(series, 0)
31715 - | set11nRate(series, 1)
31716 - | set11nRate(series, 2)
31717 - | set11nRate(series, 3);
31718 -
31719 - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
31720 - | set11nPktDurRTSCTS(series, 1);
31721 -
31722 - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
31723 - | set11nPktDurRTSCTS(series, 3);
31724 -
31725 - ads->ds_ctl7 = set11nRateFlags(series, 0)
31726 - | set11nRateFlags(series, 1)
31727 - | set11nRateFlags(series, 2)
31728 - | set11nRateFlags(series, 3)
31729 - | SM(rtsctsRate, AR_RTSCTSRate);
31730 - last_ads->ds_ctl2 = ads->ds_ctl2;
31731 - last_ads->ds_ctl3 = ads->ds_ctl3;
31732 -}
31733 -EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
31734 -
31735 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
31736 - u32 aggrLen)
31737 -{
31738 - struct ar5416_desc *ads = AR5416DESC(ds);
31739 -
31740 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
31741 - ads->ds_ctl6 &= ~AR_AggrLen;
31742 - ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
31743 -}
31744 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
31745 -
31746 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
31747 - u32 numDelims)
31748 -{
31749 - struct ar5416_desc *ads = AR5416DESC(ds);
31750 - unsigned int ctl6;
31751 -
31752 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
31753 -
31754 - ctl6 = ads->ds_ctl6;
31755 - ctl6 &= ~AR_PadDelim;
31756 - ctl6 |= SM(numDelims, AR_PadDelim);
31757 - ads->ds_ctl6 = ctl6;
31758 -}
31759 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
31760 -
31761 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
31762 -{
31763 - struct ar5416_desc *ads = AR5416DESC(ds);
31764 -
31765 - ads->ds_ctl1 |= AR_IsAggr;
31766 - ads->ds_ctl1 &= ~AR_MoreAggr;
31767 - ads->ds_ctl6 &= ~AR_PadDelim;
31768 -}
31769 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
31770 -
31771 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
31772 -{
31773 - struct ar5416_desc *ads = AR5416DESC(ds);
31774 -
31775 - ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
31776 -}
31777 -EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
31778 -
31779 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
31780 - u32 burstDuration)
31781 -{
31782 - struct ar5416_desc *ads = AR5416DESC(ds);
31783 -
31784 - ads->ds_ctl2 &= ~AR_BurstDur;
31785 - ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
31786 -}
31787 -EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
31788 -
31789 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
31790 - u32 vmf)
31791 -{
31792 - struct ar5416_desc *ads = AR5416DESC(ds);
31793 -
31794 - if (vmf)
31795 - ads->ds_ctl0 |= AR_VirtMoreFrag;
31796 - else
31797 - ads->ds_ctl0 &= ~AR_VirtMoreFrag;
31798 -}
31799 -
31800 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
31801 {
31802 *txqs &= ah->intr_txqs;
31803 @@ -796,6 +533,12 @@ bool ath9k_hw_resettxqueue(struct ath_hw
31804 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
31805 | AR_D_MISC_BEACON_USE
31806 | AR_D_MISC_POST_FR_BKOFF_DIS);
31807 + /* cwmin and cwmax should be 0 for beacon queue */
31808 + if (AR_SREV_9300_20_OR_LATER(ah)) {
31809 + REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
31810 + | SM(0, AR_D_LCL_IFS_CWMAX)
31811 + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
31812 + }
31813 break;
31814 case ATH9K_TX_QUEUE_CAB:
31815 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
31816 @@ -832,6 +575,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw
31817 AR_D_MISC_POST_FR_BKOFF_DIS);
31818 }
31819
31820 + if (AR_SREV_9300_20_OR_LATER(ah))
31821 + REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
31822 +
31823 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
31824 ah->txok_interrupt_mask |= 1 << q;
31825 else
31826 @@ -940,22 +686,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *a
31827 }
31828 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
31829
31830 -void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
31831 - u32 size, u32 flags)
31832 -{
31833 - struct ar5416_desc *ads = AR5416DESC(ds);
31834 - struct ath9k_hw_capabilities *pCap = &ah->caps;
31835 -
31836 - ads->ds_ctl1 = size & AR_BufLen;
31837 - if (flags & ATH9K_RXDESC_INTREQ)
31838 - ads->ds_ctl1 |= AR_RxIntrReq;
31839 -
31840 - ads->ds_rxstatus8 &= ~AR_RxDone;
31841 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
31842 - memset(&(ads->u), 0, sizeof(ads->u));
31843 -}
31844 -EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
31845 -
31846 /*
31847 * This can stop or re-enables RX.
31848 *
31849 @@ -999,12 +729,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah
31850 }
31851 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
31852
31853 -void ath9k_hw_rxena(struct ath_hw *ah)
31854 -{
31855 - REG_WRITE(ah, AR_CR, AR_CR_RXE);
31856 -}
31857 -EXPORT_SYMBOL(ath9k_hw_rxena);
31858 -
31859 void ath9k_hw_startpcureceive(struct ath_hw *ah)
31860 {
31861 ath9k_enable_mib_counters(ah);
31862 @@ -1023,6 +747,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw
31863 }
31864 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
31865
31866 +void ath9k_hw_abortpcurecv(struct ath_hw *ah)
31867 +{
31868 + REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
31869 +
31870 + ath9k_hw_disable_mib_counters(ah);
31871 +}
31872 +EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
31873 +
31874 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
31875 {
31876 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
31877 @@ -1068,3 +800,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw
31878 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
31879 }
31880 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
31881 +
31882 +bool ath9k_hw_intrpend(struct ath_hw *ah)
31883 +{
31884 + u32 host_isr;
31885 +
31886 + if (AR_SREV_9100(ah))
31887 + return true;
31888 +
31889 + host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
31890 + if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
31891 + return true;
31892 +
31893 + host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
31894 + if ((host_isr & AR_INTR_SYNC_DEFAULT)
31895 + && (host_isr != AR_INTR_SPURIOUS))
31896 + return true;
31897 +
31898 + return false;
31899 +}
31900 +EXPORT_SYMBOL(ath9k_hw_intrpend);
31901 +
31902 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
31903 + enum ath9k_int ints)
31904 +{
31905 + enum ath9k_int omask = ah->imask;
31906 + u32 mask, mask2;
31907 + struct ath9k_hw_capabilities *pCap = &ah->caps;
31908 + struct ath_common *common = ath9k_hw_common(ah);
31909 +
31910 + ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
31911 +
31912 + if (omask & ATH9K_INT_GLOBAL) {
31913 + ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
31914 + REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
31915 + (void) REG_READ(ah, AR_IER);
31916 + if (!AR_SREV_9100(ah)) {
31917 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
31918 + (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
31919 +
31920 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
31921 + (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
31922 + }
31923 + }
31924 +
31925 + /* TODO: global int Ref count */
31926 + mask = ints & ATH9K_INT_COMMON;
31927 + mask2 = 0;
31928 +
31929 + if (ints & ATH9K_INT_TX) {
31930 + if (ah->config.tx_intr_mitigation)
31931 + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
31932 + if (ah->txok_interrupt_mask)
31933 + mask |= AR_IMR_TXOK;
31934 + if (ah->txdesc_interrupt_mask)
31935 + mask |= AR_IMR_TXDESC;
31936 + if (ah->txerr_interrupt_mask)
31937 + mask |= AR_IMR_TXERR;
31938 + if (ah->txeol_interrupt_mask)
31939 + mask |= AR_IMR_TXEOL;
31940 + }
31941 + if (ints & ATH9K_INT_RX) {
31942 + if (AR_SREV_9300_20_OR_LATER(ah)) {
31943 + mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
31944 + if (ah->config.rx_intr_mitigation) {
31945 + mask &= ~AR_IMR_RXOK_LP;
31946 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
31947 + } else {
31948 + mask |= AR_IMR_RXOK_LP;
31949 + }
31950 + } else {
31951 + if (ah->config.rx_intr_mitigation)
31952 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
31953 + else
31954 + mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
31955 + }
31956 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
31957 + mask |= AR_IMR_GENTMR;
31958 + }
31959 +
31960 + if (ints & (ATH9K_INT_BMISC)) {
31961 + mask |= AR_IMR_BCNMISC;
31962 + if (ints & ATH9K_INT_TIM)
31963 + mask2 |= AR_IMR_S2_TIM;
31964 + if (ints & ATH9K_INT_DTIM)
31965 + mask2 |= AR_IMR_S2_DTIM;
31966 + if (ints & ATH9K_INT_DTIMSYNC)
31967 + mask2 |= AR_IMR_S2_DTIMSYNC;
31968 + if (ints & ATH9K_INT_CABEND)
31969 + mask2 |= AR_IMR_S2_CABEND;
31970 + if (ints & ATH9K_INT_TSFOOR)
31971 + mask2 |= AR_IMR_S2_TSFOOR;
31972 + }
31973 +
31974 + if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
31975 + mask |= AR_IMR_BCNMISC;
31976 + if (ints & ATH9K_INT_GTT)
31977 + mask2 |= AR_IMR_S2_GTT;
31978 + if (ints & ATH9K_INT_CST)
31979 + mask2 |= AR_IMR_S2_CST;
31980 + }
31981 +
31982 + ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
31983 + REG_WRITE(ah, AR_IMR, mask);
31984 + ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
31985 + AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
31986 + AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
31987 + ah->imrs2_reg |= mask2;
31988 + REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
31989 +
31990 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
31991 + if (ints & ATH9K_INT_TIM_TIMER)
31992 + REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
31993 + else
31994 + REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
31995 + }
31996 +
31997 + if (ints & ATH9K_INT_GLOBAL) {
31998 + ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
31999 + REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
32000 + if (!AR_SREV_9100(ah)) {
32001 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
32002 + AR_INTR_MAC_IRQ);
32003 + REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
32004 +
32005 +
32006 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
32007 + AR_INTR_SYNC_DEFAULT);
32008 + REG_WRITE(ah, AR_INTR_SYNC_MASK,
32009 + AR_INTR_SYNC_DEFAULT);
32010 + }
32011 + ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
32012 + REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
32013 + }
32014 +
32015 + return omask;
32016 +}
32017 +EXPORT_SYMBOL(ath9k_hw_set_interrupts);
32018 --- a/drivers/net/wireless/ath/ath9k/mac.h
32019 +++ b/drivers/net/wireless/ath/ath9k/mac.h
32020 @@ -86,7 +86,6 @@
32021 #define ATH9K_TX_DESC_CFG_ERR 0x04
32022 #define ATH9K_TX_DATA_UNDERRUN 0x08
32023 #define ATH9K_TX_DELIM_UNDERRUN 0x10
32024 -#define ATH9K_TX_SW_ABORTED 0x40
32025 #define ATH9K_TX_SW_FILTERED 0x80
32026
32027 /* 64 bytes */
32028 @@ -117,7 +116,10 @@ struct ath_tx_status {
32029 int8_t ts_rssi_ext0;
32030 int8_t ts_rssi_ext1;
32031 int8_t ts_rssi_ext2;
32032 - u8 pad[3];
32033 + u8 qid;
32034 + u16 desc_id;
32035 + u8 tid;
32036 + u8 pad[2];
32037 u32 ba_low;
32038 u32 ba_high;
32039 u32 evm0;
32040 @@ -148,6 +150,8 @@ struct ath_rx_status {
32041 u32 evm0;
32042 u32 evm1;
32043 u32 evm2;
32044 + u32 evm3;
32045 + u32 evm4;
32046 };
32047
32048 struct ath_htc_rx_status {
32049 @@ -259,7 +263,8 @@ struct ath_desc {
32050 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
32051 #define ATH9K_TXDESC_VMF 0x0100
32052 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
32053 -#define ATH9K_TXDESC_CAB 0x0400
32054 +#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
32055 +#define ATH9K_TXDESC_LDPC 0x00010000
32056
32057 #define ATH9K_RXDESC_INTREQ 0x0020
32058
32059 @@ -353,7 +358,6 @@ struct ar5416_desc {
32060 #define AR_DestIdxValid 0x40000000
32061 #define AR_CTSEnable 0x80000000
32062
32063 -#define AR_BufLen 0x00000fff
32064 #define AR_TxMore 0x00001000
32065 #define AR_DestIdx 0x000fe000
32066 #define AR_DestIdx_S 13
32067 @@ -410,6 +414,7 @@ struct ar5416_desc {
32068 #define AR_EncrType 0x0c000000
32069 #define AR_EncrType_S 26
32070 #define AR_TxCtlRsvd61 0xf0000000
32071 +#define AR_LDPC 0x80000000
32072
32073 #define AR_2040_0 0x00000001
32074 #define AR_GI0 0x00000002
32075 @@ -493,7 +498,6 @@ struct ar5416_desc {
32076
32077 #define AR_RxCTLRsvd00 0xffffffff
32078
32079 -#define AR_BufLen 0x00000fff
32080 #define AR_RxCtlRsvd00 0x00001000
32081 #define AR_RxIntrReq 0x00002000
32082 #define AR_RxCtlRsvd01 0xffffc000
32083 @@ -686,34 +690,10 @@ struct ath9k_channel;
32084 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
32085 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
32086 void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
32087 +void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
32088 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
32089 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
32090 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
32091 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
32092 - u32 segLen, bool firstSeg,
32093 - bool lastSeg, const struct ath_desc *ds0);
32094 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
32095 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
32096 - struct ath_tx_status *ts);
32097 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
32098 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
32099 - u32 keyIx, enum ath9k_key_type keyType, u32 flags);
32100 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
32101 - struct ath_desc *lastds,
32102 - u32 durUpdateEn, u32 rtsctsRate,
32103 - u32 rtsctsDuration,
32104 - struct ath9k_11n_rate_series series[],
32105 - u32 nseries, u32 flags);
32106 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
32107 - u32 aggrLen);
32108 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
32109 - u32 numDelims);
32110 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
32111 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
32112 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
32113 - u32 burstDuration);
32114 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
32115 - u32 vmf);
32116 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
32117 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
32118 const struct ath9k_tx_queue_info *qinfo);
32119 @@ -729,10 +709,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw
32120 u32 size, u32 flags);
32121 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
32122 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
32123 -void ath9k_hw_rxena(struct ath_hw *ah);
32124 void ath9k_hw_startpcureceive(struct ath_hw *ah);
32125 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
32126 +void ath9k_hw_abortpcurecv(struct ath_hw *ah);
32127 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
32128 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
32129
32130 +/* Interrupt Handling */
32131 +bool ath9k_hw_intrpend(struct ath_hw *ah);
32132 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
32133 + enum ath9k_int ints);
32134 +
32135 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
32136 +
32137 #endif /* MAC_H */
32138 --- a/drivers/net/wireless/ath/ath9k/main.c
32139 +++ b/drivers/net/wireless/ath/ath9k/main.c
32140 @@ -401,6 +401,7 @@ void ath9k_tasklet(unsigned long data)
32141 struct ath_common *common = ath9k_hw_common(ah);
32142
32143 u32 status = sc->intrstatus;
32144 + u32 rxmask;
32145
32146 ath9k_ps_wakeup(sc);
32147
32148 @@ -410,14 +411,30 @@ void ath9k_tasklet(unsigned long data)
32149 return;
32150 }
32151
32152 - if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
32153 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32154 + rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
32155 + ATH9K_INT_RXORN);
32156 + else
32157 + rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
32158 +
32159 + if (status & rxmask) {
32160 spin_lock_bh(&sc->rx.rxflushlock);
32161 - ath_rx_tasklet(sc, 0);
32162 +
32163 + /* Check for high priority Rx first */
32164 + if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
32165 + (status & ATH9K_INT_RXHP))
32166 + ath_rx_tasklet(sc, 0, true);
32167 +
32168 + ath_rx_tasklet(sc, 0, false);
32169 spin_unlock_bh(&sc->rx.rxflushlock);
32170 }
32171
32172 - if (status & ATH9K_INT_TX)
32173 - ath_tx_tasklet(sc);
32174 + if (status & ATH9K_INT_TX) {
32175 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32176 + ath_tx_edma_tasklet(sc);
32177 + else
32178 + ath_tx_tasklet(sc);
32179 + }
32180
32181 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
32182 /*
32183 @@ -445,6 +462,8 @@ irqreturn_t ath_isr(int irq, void *dev)
32184 ATH9K_INT_RXORN | \
32185 ATH9K_INT_RXEOL | \
32186 ATH9K_INT_RX | \
32187 + ATH9K_INT_RXLP | \
32188 + ATH9K_INT_RXHP | \
32189 ATH9K_INT_TX | \
32190 ATH9K_INT_BMISS | \
32191 ATH9K_INT_CST | \
32192 @@ -496,7 +515,8 @@ irqreturn_t ath_isr(int irq, void *dev)
32193 * If a FATAL or RXORN interrupt is received, we have to reset the
32194 * chip immediately.
32195 */
32196 - if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
32197 + if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
32198 + !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
32199 goto chip_reset;
32200
32201 if (status & ATH9K_INT_SWBA)
32202 @@ -505,6 +525,13 @@ irqreturn_t ath_isr(int irq, void *dev)
32203 if (status & ATH9K_INT_TXURN)
32204 ath9k_hw_updatetxtriglevel(ah, true);
32205
32206 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
32207 + if (status & ATH9K_INT_RXEOL) {
32208 + ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
32209 + ath9k_hw_set_interrupts(ah, ah->imask);
32210 + }
32211 + }
32212 +
32213 if (status & ATH9K_INT_MIB) {
32214 /*
32215 * Disable interrupts until we service the MIB
32216 @@ -1162,9 +1189,14 @@ static int ath9k_start(struct ieee80211_
32217 }
32218
32219 /* Setup our intr mask. */
32220 - ah->imask = ATH9K_INT_RX | ATH9K_INT_TX
32221 - | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
32222 - | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
32223 + ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
32224 + ATH9K_INT_RXORN | ATH9K_INT_FATAL |
32225 + ATH9K_INT_GLOBAL;
32226 +
32227 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
32228 + ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
32229 + else
32230 + ah->imask |= ATH9K_INT_RX;
32231
32232 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
32233 ah->imask |= ATH9K_INT_GTT;
32234 @@ -1436,7 +1468,8 @@ static int ath9k_add_interface(struct ie
32235 if ((vif->type == NL80211_IFTYPE_STATION) ||
32236 (vif->type == NL80211_IFTYPE_ADHOC) ||
32237 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
32238 - ah->imask |= ATH9K_INT_MIB;
32239 + if (ah->config.enable_ani)
32240 + ah->imask |= ATH9K_INT_MIB;
32241 ah->imask |= ATH9K_INT_TSFOOR;
32242 }
32243
32244 --- a/drivers/net/wireless/ath/ath9k/pci.c
32245 +++ b/drivers/net/wireless/ath/ath9k/pci.c
32246 @@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
32247 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
32248 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
32249 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
32250 + { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
32251 { 0 }
32252 };
32253
32254 --- a/drivers/net/wireless/ath/ath9k/phy.c
32255 +++ /dev/null
32256 @@ -1,978 +0,0 @@
32257 -/*
32258 - * Copyright (c) 2008-2009 Atheros Communications Inc.
32259 - *
32260 - * Permission to use, copy, modify, and/or distribute this software for any
32261 - * purpose with or without fee is hereby granted, provided that the above
32262 - * copyright notice and this permission notice appear in all copies.
32263 - *
32264 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
32265 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32266 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
32267 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
32268 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
32269 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32270 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
32271 - */
32272 -
32273 -/**
32274 - * DOC: Programming Atheros 802.11n analog front end radios
32275 - *
32276 - * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
32277 - * devices have either an external AR2133 analog front end radio for single
32278 - * band 2.4 GHz communication or an AR5133 analog front end radio for dual
32279 - * band 2.4 GHz / 5 GHz communication.
32280 - *
32281 - * All devices after the AR5416 and AR5418 family starting with the AR9280
32282 - * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
32283 - * into a single-chip and require less programming.
32284 - *
32285 - * The following single-chips exist with a respective embedded radio:
32286 - *
32287 - * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32288 - * AR9281 - 11n single-band 1x2 MIMO for PCIe
32289 - * AR9285 - 11n single-band 1x1 for PCIe
32290 - * AR9287 - 11n single-band 2x2 MIMO for PCIe
32291 - *
32292 - * AR9220 - 11n dual-band 2x2 MIMO for PCI
32293 - * AR9223 - 11n single-band 2x2 MIMO for PCI
32294 - *
32295 - * AR9287 - 11n single-band 1x1 MIMO for USB
32296 - */
32297 -
32298 -#include <linux/slab.h>
32299 -
32300 -#include "hw.h"
32301 -
32302 -/**
32303 - * ath9k_hw_write_regs - ??
32304 - *
32305 - * @ah: atheros hardware structure
32306 - * @freqIndex:
32307 - * @regWrites:
32308 - *
32309 - * Used for both the chipsets with an external AR2133/AR5133 radios and
32310 - * single-chip devices.
32311 - */
32312 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
32313 -{
32314 - REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
32315 -}
32316 -
32317 -/**
32318 - * ath9k_hw_ar9280_set_channel - set channel on single-chip device
32319 - * @ah: atheros hardware structure
32320 - * @chan:
32321 - *
32322 - * This is the function to change channel on single-chip devices, that is
32323 - * all devices after ar9280.
32324 - *
32325 - * This function takes the channel value in MHz and sets
32326 - * hardware channel value. Assumes writes have been enabled to analog bus.
32327 - *
32328 - * Actual Expression,
32329 - *
32330 - * For 2GHz channel,
32331 - * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
32332 - * (freq_ref = 40MHz)
32333 - *
32334 - * For 5GHz channel,
32335 - * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
32336 - * (freq_ref = 40MHz/(24>>amodeRefSel))
32337 - */
32338 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
32339 -{
32340 - u16 bMode, fracMode, aModeRefSel = 0;
32341 - u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
32342 - struct chan_centers centers;
32343 - u32 refDivA = 24;
32344 -
32345 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32346 - freq = centers.synth_center;
32347 -
32348 - reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
32349 - reg32 &= 0xc0000000;
32350 -
32351 - if (freq < 4800) { /* 2 GHz, fractional mode */
32352 - u32 txctl;
32353 - int regWrites = 0;
32354 -
32355 - bMode = 1;
32356 - fracMode = 1;
32357 - aModeRefSel = 0;
32358 - channelSel = (freq * 0x10000) / 15;
32359 -
32360 - if (AR_SREV_9287_11_OR_LATER(ah)) {
32361 - if (freq == 2484) {
32362 - /* Enable channel spreading for channel 14 */
32363 - REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
32364 - 1, regWrites);
32365 - } else {
32366 - REG_WRITE_ARRAY(&ah->iniCckfirNormal,
32367 - 1, regWrites);
32368 - }
32369 - } else {
32370 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
32371 - if (freq == 2484) {
32372 - /* Enable channel spreading for channel 14 */
32373 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32374 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
32375 - } else {
32376 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32377 - txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
32378 - }
32379 - }
32380 - } else {
32381 - bMode = 0;
32382 - fracMode = 0;
32383 -
32384 - switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
32385 - case 0:
32386 - if ((freq % 20) == 0) {
32387 - aModeRefSel = 3;
32388 - } else if ((freq % 10) == 0) {
32389 - aModeRefSel = 2;
32390 - }
32391 - if (aModeRefSel)
32392 - break;
32393 - case 1:
32394 - default:
32395 - aModeRefSel = 0;
32396 - /*
32397 - * Enable 2G (fractional) mode for channels
32398 - * which are 5MHz spaced.
32399 - */
32400 - fracMode = 1;
32401 - refDivA = 1;
32402 - channelSel = (freq * 0x8000) / 15;
32403 -
32404 - /* RefDivA setting */
32405 - REG_RMW_FIELD(ah, AR_AN_SYNTH9,
32406 - AR_AN_SYNTH9_REFDIVA, refDivA);
32407 -
32408 - }
32409 -
32410 - if (!fracMode) {
32411 - ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
32412 - channelSel = ndiv & 0x1ff;
32413 - channelFrac = (ndiv & 0xfffffe00) * 2;
32414 - channelSel = (channelSel << 17) | channelFrac;
32415 - }
32416 - }
32417 -
32418 - reg32 = reg32 |
32419 - (bMode << 29) |
32420 - (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
32421 -
32422 - REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
32423 -
32424 - ah->curchan = chan;
32425 - ah->curchan_rad_index = -1;
32426 -
32427 - return 0;
32428 -}
32429 -
32430 -/**
32431 - * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
32432 - * @ah: atheros hardware structure
32433 - * @chan:
32434 - *
32435 - * For single-chip solutions. Converts to baseband spur frequency given the
32436 - * input channel frequency and compute register settings below.
32437 - */
32438 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
32439 -{
32440 - int bb_spur = AR_NO_SPUR;
32441 - int freq;
32442 - int bin, cur_bin;
32443 - int bb_spur_off, spur_subchannel_sd;
32444 - int spur_freq_sd;
32445 - int spur_delta_phase;
32446 - int denominator;
32447 - int upper, lower, cur_vit_mask;
32448 - int tmp, newVal;
32449 - int i;
32450 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
32451 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
32452 - };
32453 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
32454 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
32455 - };
32456 - int inc[4] = { 0, 100, 0, 0 };
32457 - struct chan_centers centers;
32458 -
32459 - int8_t mask_m[123];
32460 - int8_t mask_p[123];
32461 - int8_t mask_amt;
32462 - int tmp_mask;
32463 - int cur_bb_spur;
32464 - bool is2GHz = IS_CHAN_2GHZ(chan);
32465 -
32466 - memset(&mask_m, 0, sizeof(int8_t) * 123);
32467 - memset(&mask_p, 0, sizeof(int8_t) * 123);
32468 -
32469 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32470 - freq = centers.synth_center;
32471 -
32472 - ah->config.spurmode = SPUR_ENABLE_EEPROM;
32473 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
32474 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
32475 -
32476 - if (is2GHz)
32477 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
32478 - else
32479 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
32480 -
32481 - if (AR_NO_SPUR == cur_bb_spur)
32482 - break;
32483 - cur_bb_spur = cur_bb_spur - freq;
32484 -
32485 - if (IS_CHAN_HT40(chan)) {
32486 - if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
32487 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
32488 - bb_spur = cur_bb_spur;
32489 - break;
32490 - }
32491 - } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
32492 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
32493 - bb_spur = cur_bb_spur;
32494 - break;
32495 - }
32496 - }
32497 -
32498 - if (AR_NO_SPUR == bb_spur) {
32499 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
32500 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
32501 - return;
32502 - } else {
32503 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
32504 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
32505 - }
32506 -
32507 - bin = bb_spur * 320;
32508 -
32509 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
32510 -
32511 - newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
32512 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
32513 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
32514 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
32515 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
32516 -
32517 - newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
32518 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
32519 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
32520 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
32521 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
32522 - REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
32523 -
32524 - if (IS_CHAN_HT40(chan)) {
32525 - if (bb_spur < 0) {
32526 - spur_subchannel_sd = 1;
32527 - bb_spur_off = bb_spur + 10;
32528 - } else {
32529 - spur_subchannel_sd = 0;
32530 - bb_spur_off = bb_spur - 10;
32531 - }
32532 - } else {
32533 - spur_subchannel_sd = 0;
32534 - bb_spur_off = bb_spur;
32535 - }
32536 -
32537 - if (IS_CHAN_HT40(chan))
32538 - spur_delta_phase =
32539 - ((bb_spur * 262144) /
32540 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32541 - else
32542 - spur_delta_phase =
32543 - ((bb_spur * 524288) /
32544 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32545 -
32546 - denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
32547 - spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
32548 -
32549 - newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
32550 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
32551 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
32552 - REG_WRITE(ah, AR_PHY_TIMING11, newVal);
32553 -
32554 - newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
32555 - REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
32556 -
32557 - cur_bin = -6000;
32558 - upper = bin + 100;
32559 - lower = bin - 100;
32560 -
32561 - for (i = 0; i < 4; i++) {
32562 - int pilot_mask = 0;
32563 - int chan_mask = 0;
32564 - int bp = 0;
32565 - for (bp = 0; bp < 30; bp++) {
32566 - if ((cur_bin > lower) && (cur_bin < upper)) {
32567 - pilot_mask = pilot_mask | 0x1 << bp;
32568 - chan_mask = chan_mask | 0x1 << bp;
32569 - }
32570 - cur_bin += 100;
32571 - }
32572 - cur_bin += inc[i];
32573 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
32574 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
32575 - }
32576 -
32577 - cur_vit_mask = 6100;
32578 - upper = bin + 120;
32579 - lower = bin - 120;
32580 -
32581 - for (i = 0; i < 123; i++) {
32582 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
32583 -
32584 - /* workaround for gcc bug #37014 */
32585 - volatile int tmp_v = abs(cur_vit_mask - bin);
32586 -
32587 - if (tmp_v < 75)
32588 - mask_amt = 1;
32589 - else
32590 - mask_amt = 0;
32591 - if (cur_vit_mask < 0)
32592 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
32593 - else
32594 - mask_p[cur_vit_mask / 100] = mask_amt;
32595 - }
32596 - cur_vit_mask -= 100;
32597 - }
32598 -
32599 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
32600 - | (mask_m[48] << 26) | (mask_m[49] << 24)
32601 - | (mask_m[50] << 22) | (mask_m[51] << 20)
32602 - | (mask_m[52] << 18) | (mask_m[53] << 16)
32603 - | (mask_m[54] << 14) | (mask_m[55] << 12)
32604 - | (mask_m[56] << 10) | (mask_m[57] << 8)
32605 - | (mask_m[58] << 6) | (mask_m[59] << 4)
32606 - | (mask_m[60] << 2) | (mask_m[61] << 0);
32607 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
32608 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
32609 -
32610 - tmp_mask = (mask_m[31] << 28)
32611 - | (mask_m[32] << 26) | (mask_m[33] << 24)
32612 - | (mask_m[34] << 22) | (mask_m[35] << 20)
32613 - | (mask_m[36] << 18) | (mask_m[37] << 16)
32614 - | (mask_m[48] << 14) | (mask_m[39] << 12)
32615 - | (mask_m[40] << 10) | (mask_m[41] << 8)
32616 - | (mask_m[42] << 6) | (mask_m[43] << 4)
32617 - | (mask_m[44] << 2) | (mask_m[45] << 0);
32618 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
32619 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
32620 -
32621 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
32622 - | (mask_m[18] << 26) | (mask_m[18] << 24)
32623 - | (mask_m[20] << 22) | (mask_m[20] << 20)
32624 - | (mask_m[22] << 18) | (mask_m[22] << 16)
32625 - | (mask_m[24] << 14) | (mask_m[24] << 12)
32626 - | (mask_m[25] << 10) | (mask_m[26] << 8)
32627 - | (mask_m[27] << 6) | (mask_m[28] << 4)
32628 - | (mask_m[29] << 2) | (mask_m[30] << 0);
32629 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
32630 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
32631 -
32632 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
32633 - | (mask_m[2] << 26) | (mask_m[3] << 24)
32634 - | (mask_m[4] << 22) | (mask_m[5] << 20)
32635 - | (mask_m[6] << 18) | (mask_m[7] << 16)
32636 - | (mask_m[8] << 14) | (mask_m[9] << 12)
32637 - | (mask_m[10] << 10) | (mask_m[11] << 8)
32638 - | (mask_m[12] << 6) | (mask_m[13] << 4)
32639 - | (mask_m[14] << 2) | (mask_m[15] << 0);
32640 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
32641 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
32642 -
32643 - tmp_mask = (mask_p[15] << 28)
32644 - | (mask_p[14] << 26) | (mask_p[13] << 24)
32645 - | (mask_p[12] << 22) | (mask_p[11] << 20)
32646 - | (mask_p[10] << 18) | (mask_p[9] << 16)
32647 - | (mask_p[8] << 14) | (mask_p[7] << 12)
32648 - | (mask_p[6] << 10) | (mask_p[5] << 8)
32649 - | (mask_p[4] << 6) | (mask_p[3] << 4)
32650 - | (mask_p[2] << 2) | (mask_p[1] << 0);
32651 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
32652 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
32653 -
32654 - tmp_mask = (mask_p[30] << 28)
32655 - | (mask_p[29] << 26) | (mask_p[28] << 24)
32656 - | (mask_p[27] << 22) | (mask_p[26] << 20)
32657 - | (mask_p[25] << 18) | (mask_p[24] << 16)
32658 - | (mask_p[23] << 14) | (mask_p[22] << 12)
32659 - | (mask_p[21] << 10) | (mask_p[20] << 8)
32660 - | (mask_p[19] << 6) | (mask_p[18] << 4)
32661 - | (mask_p[17] << 2) | (mask_p[16] << 0);
32662 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
32663 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
32664 -
32665 - tmp_mask = (mask_p[45] << 28)
32666 - | (mask_p[44] << 26) | (mask_p[43] << 24)
32667 - | (mask_p[42] << 22) | (mask_p[41] << 20)
32668 - | (mask_p[40] << 18) | (mask_p[39] << 16)
32669 - | (mask_p[38] << 14) | (mask_p[37] << 12)
32670 - | (mask_p[36] << 10) | (mask_p[35] << 8)
32671 - | (mask_p[34] << 6) | (mask_p[33] << 4)
32672 - | (mask_p[32] << 2) | (mask_p[31] << 0);
32673 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
32674 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
32675 -
32676 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
32677 - | (mask_p[59] << 26) | (mask_p[58] << 24)
32678 - | (mask_p[57] << 22) | (mask_p[56] << 20)
32679 - | (mask_p[55] << 18) | (mask_p[54] << 16)
32680 - | (mask_p[53] << 14) | (mask_p[52] << 12)
32681 - | (mask_p[51] << 10) | (mask_p[50] << 8)
32682 - | (mask_p[49] << 6) | (mask_p[48] << 4)
32683 - | (mask_p[47] << 2) | (mask_p[46] << 0);
32684 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
32685 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
32686 -}
32687 -
32688 -/* All code below is for non single-chip solutions */
32689 -
32690 -/**
32691 - * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
32692 - * @rfbuf:
32693 - * @reg32:
32694 - * @numBits:
32695 - * @firstBit:
32696 - * @column:
32697 - *
32698 - * Performs analog "swizzling" of parameters into their location.
32699 - * Used on external AR2133/AR5133 radios.
32700 - */
32701 -static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
32702 - u32 numBits, u32 firstBit,
32703 - u32 column)
32704 -{
32705 - u32 tmp32, mask, arrayEntry, lastBit;
32706 - int32_t bitPosition, bitsLeft;
32707 -
32708 - tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
32709 - arrayEntry = (firstBit - 1) / 8;
32710 - bitPosition = (firstBit - 1) % 8;
32711 - bitsLeft = numBits;
32712 - while (bitsLeft > 0) {
32713 - lastBit = (bitPosition + bitsLeft > 8) ?
32714 - 8 : bitPosition + bitsLeft;
32715 - mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
32716 - (column * 8);
32717 - rfBuf[arrayEntry] &= ~mask;
32718 - rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
32719 - (column * 8)) & mask;
32720 - bitsLeft -= 8 - bitPosition;
32721 - tmp32 = tmp32 >> (8 - bitPosition);
32722 - bitPosition = 0;
32723 - arrayEntry++;
32724 - }
32725 -}
32726 -
32727 -/*
32728 - * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
32729 - * rf_pwd_icsyndiv.
32730 - *
32731 - * Theoretical Rules:
32732 - * if 2 GHz band
32733 - * if forceBiasAuto
32734 - * if synth_freq < 2412
32735 - * bias = 0
32736 - * else if 2412 <= synth_freq <= 2422
32737 - * bias = 1
32738 - * else // synth_freq > 2422
32739 - * bias = 2
32740 - * else if forceBias > 0
32741 - * bias = forceBias & 7
32742 - * else
32743 - * no change, use value from ini file
32744 - * else
32745 - * no change, invalid band
32746 - *
32747 - * 1st Mod:
32748 - * 2422 also uses value of 2
32749 - * <approved>
32750 - *
32751 - * 2nd Mod:
32752 - * Less than 2412 uses value of 0, 2412 and above uses value of 2
32753 - */
32754 -static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
32755 -{
32756 - struct ath_common *common = ath9k_hw_common(ah);
32757 - u32 tmp_reg;
32758 - int reg_writes = 0;
32759 - u32 new_bias = 0;
32760 -
32761 - if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
32762 - return;
32763 - }
32764 -
32765 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
32766 -
32767 - if (synth_freq < 2412)
32768 - new_bias = 0;
32769 - else if (synth_freq < 2422)
32770 - new_bias = 1;
32771 - else
32772 - new_bias = 2;
32773 -
32774 - /* pre-reverse this field */
32775 - tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
32776 -
32777 - ath_print(common, ATH_DBG_CONFIG,
32778 - "Force rf_pwd_icsyndiv to %1d on %4d\n",
32779 - new_bias, synth_freq);
32780 -
32781 - /* swizzle rf_pwd_icsyndiv */
32782 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
32783 -
32784 - /* write Bank 6 with new params */
32785 - REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
32786 -}
32787 -
32788 -/**
32789 - * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
32790 - * @ah: atheros hardware stucture
32791 - * @chan:
32792 - *
32793 - * For the external AR2133/AR5133 radios, takes the MHz channel value and set
32794 - * the channel value. Assumes writes enabled to analog bus and bank6 register
32795 - * cache in ah->analogBank6Data.
32796 - */
32797 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
32798 -{
32799 - struct ath_common *common = ath9k_hw_common(ah);
32800 - u32 channelSel = 0;
32801 - u32 bModeSynth = 0;
32802 - u32 aModeRefSel = 0;
32803 - u32 reg32 = 0;
32804 - u16 freq;
32805 - struct chan_centers centers;
32806 -
32807 - ath9k_hw_get_channel_centers(ah, chan, &centers);
32808 - freq = centers.synth_center;
32809 -
32810 - if (freq < 4800) {
32811 - u32 txctl;
32812 -
32813 - if (((freq - 2192) % 5) == 0) {
32814 - channelSel = ((freq - 672) * 2 - 3040) / 10;
32815 - bModeSynth = 0;
32816 - } else if (((freq - 2224) % 5) == 0) {
32817 - channelSel = ((freq - 704) * 2 - 3040) / 10;
32818 - bModeSynth = 1;
32819 - } else {
32820 - ath_print(common, ATH_DBG_FATAL,
32821 - "Invalid channel %u MHz\n", freq);
32822 - return -EINVAL;
32823 - }
32824 -
32825 - channelSel = (channelSel << 2) & 0xff;
32826 - channelSel = ath9k_hw_reverse_bits(channelSel, 8);
32827 -
32828 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
32829 - if (freq == 2484) {
32830 -
32831 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32832 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
32833 - } else {
32834 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
32835 - txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
32836 - }
32837 -
32838 - } else if ((freq % 20) == 0 && freq >= 5120) {
32839 - channelSel =
32840 - ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
32841 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32842 - } else if ((freq % 10) == 0) {
32843 - channelSel =
32844 - ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
32845 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
32846 - aModeRefSel = ath9k_hw_reverse_bits(2, 2);
32847 - else
32848 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32849 - } else if ((freq % 5) == 0) {
32850 - channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
32851 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
32852 - } else {
32853 - ath_print(common, ATH_DBG_FATAL,
32854 - "Invalid channel %u MHz\n", freq);
32855 - return -EINVAL;
32856 - }
32857 -
32858 - ath9k_hw_force_bias(ah, freq);
32859 -
32860 - reg32 =
32861 - (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
32862 - (1 << 5) | 0x1;
32863 -
32864 - REG_WRITE(ah, AR_PHY(0x37), reg32);
32865 -
32866 - ah->curchan = chan;
32867 - ah->curchan_rad_index = -1;
32868 -
32869 - return 0;
32870 -}
32871 -
32872 -/**
32873 - * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
32874 - * @ah: atheros hardware structure
32875 - * @chan:
32876 - *
32877 - * For non single-chip solutions. Converts to baseband spur frequency given the
32878 - * input channel frequency and compute register settings below.
32879 - */
32880 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
32881 -{
32882 - int bb_spur = AR_NO_SPUR;
32883 - int bin, cur_bin;
32884 - int spur_freq_sd;
32885 - int spur_delta_phase;
32886 - int denominator;
32887 - int upper, lower, cur_vit_mask;
32888 - int tmp, new;
32889 - int i;
32890 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
32891 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
32892 - };
32893 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
32894 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
32895 - };
32896 - int inc[4] = { 0, 100, 0, 0 };
32897 -
32898 - int8_t mask_m[123];
32899 - int8_t mask_p[123];
32900 - int8_t mask_amt;
32901 - int tmp_mask;
32902 - int cur_bb_spur;
32903 - bool is2GHz = IS_CHAN_2GHZ(chan);
32904 -
32905 - memset(&mask_m, 0, sizeof(int8_t) * 123);
32906 - memset(&mask_p, 0, sizeof(int8_t) * 123);
32907 -
32908 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
32909 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
32910 - if (AR_NO_SPUR == cur_bb_spur)
32911 - break;
32912 - cur_bb_spur = cur_bb_spur - (chan->channel * 10);
32913 - if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
32914 - bb_spur = cur_bb_spur;
32915 - break;
32916 - }
32917 - }
32918 -
32919 - if (AR_NO_SPUR == bb_spur)
32920 - return;
32921 -
32922 - bin = bb_spur * 32;
32923 -
32924 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
32925 - new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
32926 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
32927 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
32928 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
32929 -
32930 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
32931 -
32932 - new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
32933 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
32934 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
32935 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
32936 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
32937 - REG_WRITE(ah, AR_PHY_SPUR_REG, new);
32938 -
32939 - spur_delta_phase = ((bb_spur * 524288) / 100) &
32940 - AR_PHY_TIMING11_SPUR_DELTA_PHASE;
32941 -
32942 - denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
32943 - spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
32944 -
32945 - new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
32946 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
32947 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
32948 - REG_WRITE(ah, AR_PHY_TIMING11, new);
32949 -
32950 - cur_bin = -6000;
32951 - upper = bin + 100;
32952 - lower = bin - 100;
32953 -
32954 - for (i = 0; i < 4; i++) {
32955 - int pilot_mask = 0;
32956 - int chan_mask = 0;
32957 - int bp = 0;
32958 - for (bp = 0; bp < 30; bp++) {
32959 - if ((cur_bin > lower) && (cur_bin < upper)) {
32960 - pilot_mask = pilot_mask | 0x1 << bp;
32961 - chan_mask = chan_mask | 0x1 << bp;
32962 - }
32963 - cur_bin += 100;
32964 - }
32965 - cur_bin += inc[i];
32966 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
32967 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
32968 - }
32969 -
32970 - cur_vit_mask = 6100;
32971 - upper = bin + 120;
32972 - lower = bin - 120;
32973 -
32974 - for (i = 0; i < 123; i++) {
32975 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
32976 -
32977 - /* workaround for gcc bug #37014 */
32978 - volatile int tmp_v = abs(cur_vit_mask - bin);
32979 -
32980 - if (tmp_v < 75)
32981 - mask_amt = 1;
32982 - else
32983 - mask_amt = 0;
32984 - if (cur_vit_mask < 0)
32985 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
32986 - else
32987 - mask_p[cur_vit_mask / 100] = mask_amt;
32988 - }
32989 - cur_vit_mask -= 100;
32990 - }
32991 -
32992 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
32993 - | (mask_m[48] << 26) | (mask_m[49] << 24)
32994 - | (mask_m[50] << 22) | (mask_m[51] << 20)
32995 - | (mask_m[52] << 18) | (mask_m[53] << 16)
32996 - | (mask_m[54] << 14) | (mask_m[55] << 12)
32997 - | (mask_m[56] << 10) | (mask_m[57] << 8)
32998 - | (mask_m[58] << 6) | (mask_m[59] << 4)
32999 - | (mask_m[60] << 2) | (mask_m[61] << 0);
33000 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
33001 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
33002 -
33003 - tmp_mask = (mask_m[31] << 28)
33004 - | (mask_m[32] << 26) | (mask_m[33] << 24)
33005 - | (mask_m[34] << 22) | (mask_m[35] << 20)
33006 - | (mask_m[36] << 18) | (mask_m[37] << 16)
33007 - | (mask_m[48] << 14) | (mask_m[39] << 12)
33008 - | (mask_m[40] << 10) | (mask_m[41] << 8)
33009 - | (mask_m[42] << 6) | (mask_m[43] << 4)
33010 - | (mask_m[44] << 2) | (mask_m[45] << 0);
33011 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
33012 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
33013 -
33014 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
33015 - | (mask_m[18] << 26) | (mask_m[18] << 24)
33016 - | (mask_m[20] << 22) | (mask_m[20] << 20)
33017 - | (mask_m[22] << 18) | (mask_m[22] << 16)
33018 - | (mask_m[24] << 14) | (mask_m[24] << 12)
33019 - | (mask_m[25] << 10) | (mask_m[26] << 8)
33020 - | (mask_m[27] << 6) | (mask_m[28] << 4)
33021 - | (mask_m[29] << 2) | (mask_m[30] << 0);
33022 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
33023 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
33024 -
33025 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
33026 - | (mask_m[2] << 26) | (mask_m[3] << 24)
33027 - | (mask_m[4] << 22) | (mask_m[5] << 20)
33028 - | (mask_m[6] << 18) | (mask_m[7] << 16)
33029 - | (mask_m[8] << 14) | (mask_m[9] << 12)
33030 - | (mask_m[10] << 10) | (mask_m[11] << 8)
33031 - | (mask_m[12] << 6) | (mask_m[13] << 4)
33032 - | (mask_m[14] << 2) | (mask_m[15] << 0);
33033 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
33034 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
33035 -
33036 - tmp_mask = (mask_p[15] << 28)
33037 - | (mask_p[14] << 26) | (mask_p[13] << 24)
33038 - | (mask_p[12] << 22) | (mask_p[11] << 20)
33039 - | (mask_p[10] << 18) | (mask_p[9] << 16)
33040 - | (mask_p[8] << 14) | (mask_p[7] << 12)
33041 - | (mask_p[6] << 10) | (mask_p[5] << 8)
33042 - | (mask_p[4] << 6) | (mask_p[3] << 4)
33043 - | (mask_p[2] << 2) | (mask_p[1] << 0);
33044 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
33045 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
33046 -
33047 - tmp_mask = (mask_p[30] << 28)
33048 - | (mask_p[29] << 26) | (mask_p[28] << 24)
33049 - | (mask_p[27] << 22) | (mask_p[26] << 20)
33050 - | (mask_p[25] << 18) | (mask_p[24] << 16)
33051 - | (mask_p[23] << 14) | (mask_p[22] << 12)
33052 - | (mask_p[21] << 10) | (mask_p[20] << 8)
33053 - | (mask_p[19] << 6) | (mask_p[18] << 4)
33054 - | (mask_p[17] << 2) | (mask_p[16] << 0);
33055 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
33056 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
33057 -
33058 - tmp_mask = (mask_p[45] << 28)
33059 - | (mask_p[44] << 26) | (mask_p[43] << 24)
33060 - | (mask_p[42] << 22) | (mask_p[41] << 20)
33061 - | (mask_p[40] << 18) | (mask_p[39] << 16)
33062 - | (mask_p[38] << 14) | (mask_p[37] << 12)
33063 - | (mask_p[36] << 10) | (mask_p[35] << 8)
33064 - | (mask_p[34] << 6) | (mask_p[33] << 4)
33065 - | (mask_p[32] << 2) | (mask_p[31] << 0);
33066 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
33067 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
33068 -
33069 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
33070 - | (mask_p[59] << 26) | (mask_p[58] << 24)
33071 - | (mask_p[57] << 22) | (mask_p[56] << 20)
33072 - | (mask_p[55] << 18) | (mask_p[54] << 16)
33073 - | (mask_p[53] << 14) | (mask_p[52] << 12)
33074 - | (mask_p[51] << 10) | (mask_p[50] << 8)
33075 - | (mask_p[49] << 6) | (mask_p[48] << 4)
33076 - | (mask_p[47] << 2) | (mask_p[46] << 0);
33077 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
33078 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
33079 -}
33080 -
33081 -/**
33082 - * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
33083 - * @ah: atheros hardware structure
33084 - *
33085 - * Only required for older devices with external AR2133/AR5133 radios.
33086 - */
33087 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
33088 -{
33089 -#define ATH_ALLOC_BANK(bank, size) do { \
33090 - bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
33091 - if (!bank) { \
33092 - ath_print(common, ATH_DBG_FATAL, \
33093 - "Cannot allocate RF banks\n"); \
33094 - return -ENOMEM; \
33095 - } \
33096 - } while (0);
33097 -
33098 - struct ath_common *common = ath9k_hw_common(ah);
33099 -
33100 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
33101 -
33102 - ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
33103 - ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
33104 - ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
33105 - ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
33106 - ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
33107 - ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
33108 - ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
33109 - ATH_ALLOC_BANK(ah->addac5416_21,
33110 - ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
33111 - ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
33112 -
33113 - return 0;
33114 -#undef ATH_ALLOC_BANK
33115 -}
33116 -
33117 -
33118 -/**
33119 - * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
33120 - * @ah: atheros hardware struture
33121 - * For the external AR2133/AR5133 radios banks.
33122 - */
33123 -void
33124 -ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
33125 -{
33126 -#define ATH_FREE_BANK(bank) do { \
33127 - kfree(bank); \
33128 - bank = NULL; \
33129 - } while (0);
33130 -
33131 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
33132 -
33133 - ATH_FREE_BANK(ah->analogBank0Data);
33134 - ATH_FREE_BANK(ah->analogBank1Data);
33135 - ATH_FREE_BANK(ah->analogBank2Data);
33136 - ATH_FREE_BANK(ah->analogBank3Data);
33137 - ATH_FREE_BANK(ah->analogBank6Data);
33138 - ATH_FREE_BANK(ah->analogBank6TPCData);
33139 - ATH_FREE_BANK(ah->analogBank7Data);
33140 - ATH_FREE_BANK(ah->addac5416_21);
33141 - ATH_FREE_BANK(ah->bank6Temp);
33142 -
33143 -#undef ATH_FREE_BANK
33144 -}
33145 -
33146 -/* *
33147 - * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
33148 - * @ah: atheros hardware structure
33149 - * @chan:
33150 - * @modesIndex:
33151 - *
33152 - * Used for the external AR2133/AR5133 radios.
33153 - *
33154 - * Reads the EEPROM header info from the device structure and programs
33155 - * all rf registers. This routine requires access to the analog
33156 - * rf device. This is not required for single-chip devices.
33157 - */
33158 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33159 - u16 modesIndex)
33160 -{
33161 - u32 eepMinorRev;
33162 - u32 ob5GHz = 0, db5GHz = 0;
33163 - u32 ob2GHz = 0, db2GHz = 0;
33164 - int regWrites = 0;
33165 -
33166 - /*
33167 - * Software does not need to program bank data
33168 - * for single chip devices, that is AR9280 or anything
33169 - * after that.
33170 - */
33171 - if (AR_SREV_9280_10_OR_LATER(ah))
33172 - return true;
33173 -
33174 - /* Setup rf parameters */
33175 - eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
33176 -
33177 - /* Setup Bank 0 Write */
33178 - RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
33179 -
33180 - /* Setup Bank 1 Write */
33181 - RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
33182 -
33183 - /* Setup Bank 2 Write */
33184 - RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
33185 -
33186 - /* Setup Bank 6 Write */
33187 - RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
33188 - modesIndex);
33189 - {
33190 - int i;
33191 - for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
33192 - ah->analogBank6Data[i] =
33193 - INI_RA(&ah->iniBank6TPC, i, modesIndex);
33194 - }
33195 - }
33196 -
33197 - /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
33198 - if (eepMinorRev >= 2) {
33199 - if (IS_CHAN_2GHZ(chan)) {
33200 - ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
33201 - db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
33202 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33203 - ob2GHz, 3, 197, 0);
33204 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33205 - db2GHz, 3, 194, 0);
33206 - } else {
33207 - ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
33208 - db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
33209 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33210 - ob5GHz, 3, 203, 0);
33211 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
33212 - db5GHz, 3, 200, 0);
33213 - }
33214 - }
33215 -
33216 - /* Setup Bank 7 Setup */
33217 - RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
33218 -
33219 - /* Write Analog registers */
33220 - REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
33221 - regWrites);
33222 - REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
33223 - regWrites);
33224 - REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
33225 - regWrites);
33226 - REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
33227 - regWrites);
33228 - REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
33229 - regWrites);
33230 - REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
33231 - regWrites);
33232 -
33233 - return true;
33234 -}
33235 --- a/drivers/net/wireless/ath/ath9k/phy.h
33236 +++ b/drivers/net/wireless/ath/ath9k/phy.h
33237 @@ -17,504 +17,15 @@
33238 #ifndef PHY_H
33239 #define PHY_H
33240
33241 -/* Common between single chip and non single-chip solutions */
33242 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
33243 -
33244 -/* Single chip radio settings */
33245 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
33246 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
33247 -
33248 -/* Routines below are for non single-chip solutions */
33249 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
33250 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
33251 -
33252 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
33253 -void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33254 -
33255 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
33256 - struct ath9k_channel *chan,
33257 - u16 modesIndex);
33258 +#define CHANSEL_DIV 15
33259 +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
33260 +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
33261
33262 #define AR_PHY_BASE 0x9800
33263 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
33264
33265 -#define AR_PHY_TEST 0x9800
33266 -#define PHY_AGC_CLR 0x10000000
33267 -#define RFSILENT_BB 0x00002000
33268 -
33269 -#define AR_PHY_TURBO 0x9804
33270 -#define AR_PHY_FC_TURBO_MODE 0x00000001
33271 -#define AR_PHY_FC_TURBO_SHORT 0x00000002
33272 -#define AR_PHY_FC_DYN2040_EN 0x00000004
33273 -#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
33274 -#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
33275 -/* For 25 MHz channel spacing -- not used but supported by hw */
33276 -#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
33277 -#define AR_PHY_FC_HT_EN 0x00000040
33278 -#define AR_PHY_FC_SHORT_GI_40 0x00000080
33279 -#define AR_PHY_FC_WALSH 0x00000100
33280 -#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
33281 -#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
33282 -
33283 -#define AR_PHY_TEST2 0x9808
33284 -
33285 -#define AR_PHY_TIMING2 0x9810
33286 -#define AR_PHY_TIMING3 0x9814
33287 -#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
33288 -#define AR_PHY_TIMING3_DSC_MAN_S 17
33289 -#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
33290 -#define AR_PHY_TIMING3_DSC_EXP_S 13
33291 -
33292 -#define AR_PHY_CHIP_ID 0x9818
33293 -#define AR_PHY_CHIP_ID_REV_0 0x80
33294 -#define AR_PHY_CHIP_ID_REV_1 0x81
33295 -#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
33296 -
33297 -#define AR_PHY_ACTIVE 0x981C
33298 -#define AR_PHY_ACTIVE_EN 0x00000001
33299 -#define AR_PHY_ACTIVE_DIS 0x00000000
33300 -
33301 -#define AR_PHY_RF_CTL2 0x9824
33302 -#define AR_PHY_TX_END_DATA_START 0x000000FF
33303 -#define AR_PHY_TX_END_DATA_START_S 0
33304 -#define AR_PHY_TX_END_PA_ON 0x0000FF00
33305 -#define AR_PHY_TX_END_PA_ON_S 8
33306 -
33307 -#define AR_PHY_RF_CTL3 0x9828
33308 -#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
33309 -#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
33310 -
33311 -#define AR_PHY_ADC_CTL 0x982C
33312 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
33313 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
33314 -#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
33315 -#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
33316 -#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
33317 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
33318 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
33319 -
33320 -#define AR_PHY_ADC_SERIAL_CTL 0x9830
33321 -#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
33322 -#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
33323 -
33324 -#define AR_PHY_RF_CTL4 0x9834
33325 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
33326 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
33327 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
33328 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
33329 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
33330 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
33331 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
33332 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
33333 -
33334 -#define AR_PHY_TSTDAC_CONST 0x983c
33335 -
33336 -#define AR_PHY_SETTLING 0x9844
33337 -#define AR_PHY_SETTLING_SWITCH 0x00003F80
33338 -#define AR_PHY_SETTLING_SWITCH_S 7
33339 -
33340 -#define AR_PHY_RXGAIN 0x9848
33341 -#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
33342 -#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
33343 -#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
33344 -#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
33345 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
33346 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
33347 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
33348 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
33349 -
33350 -#define AR_PHY_DESIRED_SZ 0x9850
33351 -#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
33352 -#define AR_PHY_DESIRED_SZ_ADC_S 0
33353 -#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
33354 -#define AR_PHY_DESIRED_SZ_PGA_S 8
33355 -#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
33356 -#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
33357 -
33358 -#define AR_PHY_FIND_SIG 0x9858
33359 -#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
33360 -#define AR_PHY_FIND_SIG_FIRSTEP_S 12
33361 -#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
33362 -#define AR_PHY_FIND_SIG_FIRPWR_S 18
33363 -
33364 -#define AR_PHY_AGC_CTL1 0x985C
33365 -#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
33366 -#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
33367 -#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
33368 -#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
33369 -
33370 -#define AR_PHY_AGC_CONTROL 0x9860
33371 -#define AR_PHY_AGC_CONTROL_CAL 0x00000001
33372 -#define AR_PHY_AGC_CONTROL_NF 0x00000002
33373 -#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
33374 -#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
33375 -#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
33376 -
33377 -#define AR_PHY_CCA 0x9864
33378 -#define AR_PHY_MINCCA_PWR 0x0FF80000
33379 -#define AR_PHY_MINCCA_PWR_S 19
33380 -#define AR_PHY_CCA_THRESH62 0x0007F000
33381 -#define AR_PHY_CCA_THRESH62_S 12
33382 -#define AR9280_PHY_MINCCA_PWR 0x1FF00000
33383 -#define AR9280_PHY_MINCCA_PWR_S 20
33384 -#define AR9280_PHY_CCA_THRESH62 0x000FF000
33385 -#define AR9280_PHY_CCA_THRESH62_S 12
33386 -
33387 -#define AR_PHY_SFCORR_LOW 0x986C
33388 -#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
33389 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
33390 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
33391 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
33392 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
33393 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
33394 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
33395 -
33396 -#define AR_PHY_SFCORR 0x9868
33397 -#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
33398 -#define AR_PHY_SFCORR_M2COUNT_THR_S 0
33399 -#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
33400 -#define AR_PHY_SFCORR_M1_THRESH_S 17
33401 -#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
33402 -#define AR_PHY_SFCORR_M2_THRESH_S 24
33403 -
33404 -#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
33405 -#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
33406 -#define AR_PHY_SYNTH_CONTROL 0x9874
33407 -#define AR_PHY_SLEEP_SCAL 0x9878
33408 -
33409 -#define AR_PHY_PLL_CTL 0x987c
33410 -#define AR_PHY_PLL_CTL_40 0xaa
33411 -#define AR_PHY_PLL_CTL_40_5413 0x04
33412 -#define AR_PHY_PLL_CTL_44 0xab
33413 -#define AR_PHY_PLL_CTL_44_2133 0xeb
33414 -#define AR_PHY_PLL_CTL_40_2133 0xea
33415 -
33416 -#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
33417 -#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
33418 -#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
33419 -#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
33420 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
33421 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
33422 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
33423 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
33424 -#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
33425 -#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
33426 -#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
33427 -#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
33428 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
33429 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
33430 -
33431 -#define AR_PHY_RX_DELAY 0x9914
33432 -#define AR_PHY_SEARCH_START_DELAY 0x9918
33433 -#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
33434 -
33435 -#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
33436 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
33437 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
33438 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
33439 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
33440 -#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
33441 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
33442 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
33443 -#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
33444 -
33445 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
33446 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
33447 -#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
33448 -#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
33449 -
33450 -#define AR_PHY_TIMING5 0x9924
33451 -#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
33452 -#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
33453 -
33454 -#define AR_PHY_POWER_TX_RATE1 0x9934
33455 -#define AR_PHY_POWER_TX_RATE2 0x9938
33456 -#define AR_PHY_POWER_TX_RATE_MAX 0x993c
33457 -#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
33458 -
33459 -#define AR_PHY_FRAME_CTL 0x9944
33460 -#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
33461 -#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
33462 -
33463 -#define AR_PHY_TXPWRADJ 0x994C
33464 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
33465 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
33466 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
33467 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
33468 -
33469 -#define AR_PHY_RADAR_EXT 0x9940
33470 -#define AR_PHY_RADAR_EXT_ENA 0x00004000
33471 -
33472 -#define AR_PHY_RADAR_0 0x9954
33473 -#define AR_PHY_RADAR_0_ENA 0x00000001
33474 -#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
33475 -#define AR_PHY_RADAR_0_INBAND 0x0000003e
33476 -#define AR_PHY_RADAR_0_INBAND_S 1
33477 -#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
33478 -#define AR_PHY_RADAR_0_PRSSI_S 6
33479 -#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
33480 -#define AR_PHY_RADAR_0_HEIGHT_S 12
33481 -#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
33482 -#define AR_PHY_RADAR_0_RRSSI_S 18
33483 -#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
33484 -#define AR_PHY_RADAR_0_FIRPWR_S 24
33485 -
33486 -#define AR_PHY_RADAR_1 0x9958
33487 -#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
33488 -#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
33489 -#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
33490 -#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
33491 -#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
33492 -#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
33493 -#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
33494 -#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
33495 -#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
33496 -#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
33497 -#define AR_PHY_RADAR_1_MAXLEN_S 0
33498 -
33499 -#define AR_PHY_SWITCH_CHAIN_0 0x9960
33500 -#define AR_PHY_SWITCH_COM 0x9964
33501 -
33502 -#define AR_PHY_SIGMA_DELTA 0x996C
33503 -#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
33504 -#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
33505 -#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
33506 -#define AR_PHY_SIGMA_DELTA_FILT2_S 3
33507 -#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
33508 -#define AR_PHY_SIGMA_DELTA_FILT1_S 8
33509 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
33510 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
33511 -
33512 -#define AR_PHY_RESTART 0x9970
33513 -#define AR_PHY_RESTART_DIV_GC 0x001C0000
33514 -#define AR_PHY_RESTART_DIV_GC_S 18
33515 -
33516 -#define AR_PHY_RFBUS_REQ 0x997C
33517 -#define AR_PHY_RFBUS_REQ_EN 0x00000001
33518 -
33519 -#define AR_PHY_TIMING7 0x9980
33520 -#define AR_PHY_TIMING8 0x9984
33521 -#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
33522 -#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
33523 -
33524 -#define AR_PHY_BIN_MASK2_1 0x9988
33525 -#define AR_PHY_BIN_MASK2_2 0x998c
33526 -#define AR_PHY_BIN_MASK2_3 0x9990
33527 -#define AR_PHY_BIN_MASK2_4 0x9994
33528 -
33529 -#define AR_PHY_BIN_MASK_1 0x9900
33530 -#define AR_PHY_BIN_MASK_2 0x9904
33531 -#define AR_PHY_BIN_MASK_3 0x9908
33532 -
33533 -#define AR_PHY_MASK_CTL 0x990c
33534 -
33535 -#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
33536 -#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
33537 -
33538 -#define AR_PHY_TIMING9 0x9998
33539 -#define AR_PHY_TIMING10 0x999c
33540 -#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
33541 -#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
33542 -
33543 -#define AR_PHY_TIMING11 0x99a0
33544 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
33545 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
33546 -#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
33547 -#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
33548 -#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
33549 -#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
33550 -
33551 -#define AR_PHY_RX_CHAINMASK 0x99a4
33552 -#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
33553 -#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
33554 -#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
33555 -
33556 -#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
33557 -#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
33558 -#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
33559 -#define AR_PHY_9285_ANT_DIV_CTL_S 24
33560 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
33561 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
33562 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
33563 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
33564 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
33565 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
33566 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
33567 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
33568 -#define AR_PHY_9285_ANT_DIV_LNA1 2
33569 -#define AR_PHY_9285_ANT_DIV_LNA2 1
33570 -#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
33571 -#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
33572 -#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
33573 -#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
33574 -
33575 -#define AR_PHY_EXT_CCA0 0x99b8
33576 -#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
33577 -#define AR_PHY_EXT_CCA0_THRESH62_S 0
33578 -
33579 -#define AR_PHY_EXT_CCA 0x99bc
33580 -#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
33581 -#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
33582 -#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
33583 -#define AR_PHY_EXT_CCA_THRESH62_S 16
33584 -#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
33585 -#define AR_PHY_EXT_MINCCA_PWR_S 23
33586 -#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
33587 -#define AR9280_PHY_EXT_MINCCA_PWR_S 16
33588 -
33589 -#define AR_PHY_SFCORR_EXT 0x99c0
33590 -#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
33591 -#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
33592 -#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
33593 -#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
33594 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
33595 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
33596 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
33597 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
33598 -#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
33599 -
33600 -#define AR_PHY_HALFGI 0x99D0
33601 -#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
33602 -#define AR_PHY_HALFGI_DSC_MAN_S 4
33603 -#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
33604 -#define AR_PHY_HALFGI_DSC_EXP_S 0
33605 -
33606 -#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
33607 -#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
33608 -
33609 -#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
33610 -
33611 -#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
33612 -#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
33613 -
33614 -#define AR_PHY_M_SLEEP 0x99f0
33615 -#define AR_PHY_REFCLKDLY 0x99f4
33616 -#define AR_PHY_REFCLKPD 0x99f8
33617 -
33618 -#define AR_PHY_CALMODE 0x99f0
33619 -
33620 -#define AR_PHY_CALMODE_IQ 0x00000000
33621 -#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
33622 -#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
33623 -#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
33624 -
33625 -#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
33626 -#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
33627 -#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
33628 -#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
33629 -
33630 -#define AR_PHY_CURRENT_RSSI 0x9c1c
33631 -#define AR9280_PHY_CURRENT_RSSI 0x9c3c
33632 -
33633 -#define AR_PHY_RFBUS_GRANT 0x9C20
33634 -#define AR_PHY_RFBUS_GRANT_EN 0x00000001
33635 -
33636 -#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
33637 -#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
33638 -
33639 -#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
33640 -
33641 -#define AR_PHY_MODE 0xA200
33642 -#define AR_PHY_MODE_ASYNCFIFO 0x80
33643 -#define AR_PHY_MODE_AR2133 0x08
33644 -#define AR_PHY_MODE_AR5111 0x00
33645 -#define AR_PHY_MODE_AR5112 0x08
33646 -#define AR_PHY_MODE_DYNAMIC 0x04
33647 -#define AR_PHY_MODE_RF2GHZ 0x02
33648 -#define AR_PHY_MODE_RF5GHZ 0x00
33649 -#define AR_PHY_MODE_CCK 0x01
33650 -#define AR_PHY_MODE_OFDM 0x00
33651 -#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
33652 -
33653 -#define AR_PHY_CCK_TX_CTRL 0xA204
33654 -#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
33655 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
33656 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
33657 -
33658 -#define AR_PHY_CCK_DETECT 0xA208
33659 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
33660 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
33661 -/* [12:6] settling time for antenna switch */
33662 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
33663 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
33664 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
33665 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
33666 -
33667 -#define AR_PHY_GAIN_2GHZ 0xA20C
33668 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
33669 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
33670 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
33671 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
33672 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
33673 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
33674 -
33675 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
33676 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
33677 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
33678 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
33679 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
33680 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
33681 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
33682 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
33683 -
33684 -#define AR_PHY_CCK_RXCTRL4 0xA21C
33685 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
33686 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
33687 -
33688 -#define AR_PHY_DAG_CTRLCCK 0xA228
33689 -#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
33690 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
33691 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
33692 -
33693 -#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
33694 -#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
33695 -
33696 -#define AR_PHY_POWER_TX_RATE3 0xA234
33697 -#define AR_PHY_POWER_TX_RATE4 0xA238
33698 -
33699 -#define AR_PHY_SCRM_SEQ_XR 0xA23C
33700 -#define AR_PHY_HEADER_DETECT_XR 0xA240
33701 -#define AR_PHY_CHIRP_DETECTED_XR 0xA244
33702 -#define AR_PHY_BLUETOOTH 0xA254
33703 -
33704 -#define AR_PHY_TPCRG1 0xA258
33705 -#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
33706 -#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
33707 -
33708 -#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
33709 -#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
33710 -#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
33711 -#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
33712 -#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
33713 -#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
33714 -
33715 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
33716 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
33717 -
33718 -#define AR_PHY_TX_PWRCTRL4 0xa264
33719 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
33720 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
33721 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
33722 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
33723 -
33724 -#define AR_PHY_TX_PWRCTRL6_0 0xa270
33725 -#define AR_PHY_TX_PWRCTRL6_1 0xb270
33726 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
33727 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
33728 -
33729 -#define AR_PHY_TX_PWRCTRL7 0xa274
33730 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
33731 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
33732 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
33733 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
33734 -
33735 -#define AR_PHY_TX_PWRCTRL9 0xa27C
33736 -#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
33737 -#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
33738 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
33739 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
33740 -
33741 -#define AR_PHY_TX_GAIN_TBL1 0xa300
33742 #define AR_PHY_TX_GAIN_CLC 0x0000001E
33743 #define AR_PHY_TX_GAIN_CLC_S 1
33744 #define AR_PHY_TX_GAIN 0x0007F000
33745 @@ -526,91 +37,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33746 #define AR_PHY_CLC_Q0 0x0000ffd0
33747 #define AR_PHY_CLC_Q0_S 5
33748
33749 -#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
33750 -#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
33751 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
33752 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
33753 -
33754 -#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
33755 -#define AR_PHY_MASK2_M_31_45 0xa3a4
33756 -#define AR_PHY_MASK2_M_16_30 0xa3a8
33757 -#define AR_PHY_MASK2_M_00_15 0xa3ac
33758 -#define AR_PHY_MASK2_P_15_01 0xa3b8
33759 -#define AR_PHY_MASK2_P_30_16 0xa3bc
33760 -#define AR_PHY_MASK2_P_45_31 0xa3c0
33761 -#define AR_PHY_MASK2_P_61_45 0xa3c4
33762 -#define AR_PHY_SPUR_REG 0x994c
33763 -
33764 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
33765 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
33766 -
33767 -#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
33768 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
33769 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
33770 -#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
33771 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
33772 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
33773 -
33774 -#define AR_PHY_PILOT_MASK_01_30 0xa3b0
33775 -#define AR_PHY_PILOT_MASK_31_60 0xa3b4
33776 -
33777 -#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
33778 -#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
33779 -
33780 -#define AR_PHY_ANALOG_SWAP 0xa268
33781 -#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
33782 -
33783 -#define AR_PHY_TPCRG5 0xA26C
33784 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
33785 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
33786 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
33787 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
33788 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
33789 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
33790 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
33791 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
33792 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
33793 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
33794 -
33795 -/* Carrier leak calibration control, do it after AGC calibration */
33796 -#define AR_PHY_CL_CAL_CTL 0xA358
33797 -#define AR_PHY_CL_CAL_ENABLE 0x00000002
33798 -#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
33799 -
33800 -#define AR_PHY_POWER_TX_RATE5 0xA38C
33801 -#define AR_PHY_POWER_TX_RATE6 0xA390
33802 -
33803 -#define AR_PHY_CAL_CHAINMASK 0xA39C
33804 -
33805 -#define AR_PHY_POWER_TX_SUB 0xA3C8
33806 -#define AR_PHY_POWER_TX_RATE7 0xA3CC
33807 -#define AR_PHY_POWER_TX_RATE8 0xA3D0
33808 -#define AR_PHY_POWER_TX_RATE9 0xA3D4
33809 -
33810 -#define AR_PHY_XPA_CFG 0xA3D8
33811 -#define AR_PHY_FORCE_XPA_CFG 0x000000001
33812 -#define AR_PHY_FORCE_XPA_CFG_S 0
33813 -
33814 -#define AR_PHY_CH1_CCA 0xa864
33815 -#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
33816 -#define AR_PHY_CH1_MINCCA_PWR_S 19
33817 -#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
33818 -#define AR9280_PHY_CH1_MINCCA_PWR_S 20
33819 -
33820 -#define AR_PHY_CH2_CCA 0xb864
33821 -#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
33822 -#define AR_PHY_CH2_MINCCA_PWR_S 19
33823 -
33824 -#define AR_PHY_CH1_EXT_CCA 0xa9bc
33825 -#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
33826 -#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
33827 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
33828 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
33829 -
33830 -#define AR_PHY_CH2_EXT_CCA 0xb9bc
33831 -#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
33832 -#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
33833 -
33834 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
33835 int r; \
33836 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
33837 @@ -625,6 +51,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33838 #define ANTSWAP_AB 0x0001
33839 #define REDUCE_CHAIN_0 0x00000050
33840 #define REDUCE_CHAIN_1 0x00000051
33841 +#define AR_PHY_CHIP_ID 0x9818
33842
33843 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
33844 int i; \
33845 @@ -632,4 +59,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
33846 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
33847 } while (0)
33848
33849 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
33850 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
33851 +
33852 #endif
33853 --- a/drivers/net/wireless/ath/ath9k/rc.c
33854 +++ b/drivers/net/wireless/ath/ath9k/rc.c
33855 @@ -691,6 +691,15 @@ static void ath_get_rate(void *priv, str
33856 rate_table = sc->cur_rate_table;
33857 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
33858
33859 + /*
33860 + * If we're in HT mode and both us and our peer supports LDPC.
33861 + * We don't need to check our own device's capabilities as our own
33862 + * ht capabilities would have already been intersected with our peer's.
33863 + */
33864 + if (conf_is_ht(&sc->hw->conf) &&
33865 + (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
33866 + tx_info->flags |= IEEE80211_TX_CTL_LDPC;
33867 +
33868 if (is_probe) {
33869 /* set one try for probe rates. For the
33870 * probes don't enable rts */
33871 --- a/drivers/net/wireless/ath/ath9k/recv.c
33872 +++ b/drivers/net/wireless/ath/ath9k/recv.c
33873 @@ -15,6 +15,9 @@
33874 */
33875
33876 #include "ath9k.h"
33877 +#include "ar9003_mac.h"
33878 +
33879 +#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
33880
33881 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
33882 struct ieee80211_hdr *hdr)
33883 @@ -115,56 +118,246 @@ static void ath_opmode_init(struct ath_s
33884 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
33885 }
33886
33887 -int ath_rx_init(struct ath_softc *sc, int nbufs)
33888 +static bool ath_rx_edma_buf_link(struct ath_softc *sc,
33889 + enum ath9k_rx_qtype qtype)
33890 {
33891 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33892 + struct ath_hw *ah = sc->sc_ah;
33893 + struct ath_rx_edma *rx_edma;
33894 struct sk_buff *skb;
33895 struct ath_buf *bf;
33896 - int error = 0;
33897
33898 - spin_lock_init(&sc->rx.rxflushlock);
33899 - sc->sc_flags &= ~SC_OP_RXFLUSH;
33900 - spin_lock_init(&sc->rx.rxbuflock);
33901 + rx_edma = &sc->rx.rx_edma[qtype];
33902 + if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
33903 + return false;
33904
33905 - common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
33906 - min(common->cachelsz, (u16)64));
33907 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
33908 + list_del_init(&bf->list);
33909 +
33910 + skb = bf->bf_mpdu;
33911
33912 - ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
33913 - common->cachelsz, common->rx_bufsize);
33914 + ATH_RXBUF_RESET(bf);
33915 + memset(skb->data, 0, ah->caps.rx_status_len);
33916 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
33917 + ah->caps.rx_status_len, DMA_TO_DEVICE);
33918 +
33919 + SKB_CB_ATHBUF(skb) = bf;
33920 + ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
33921 + skb_queue_tail(&rx_edma->rx_fifo, skb);
33922 +
33923 + return true;
33924 +}
33925
33926 - /* Initialize rx descriptors */
33927 +static void ath_rx_addbuffer_edma(struct ath_softc *sc,
33928 + enum ath9k_rx_qtype qtype, int size)
33929 +{
33930 + struct ath_rx_edma *rx_edma;
33931 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
33932 + u32 nbuf = 0;
33933
33934 - error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
33935 - "rx", nbufs, 1);
33936 - if (error != 0) {
33937 - ath_print(common, ATH_DBG_FATAL,
33938 - "failed to allocate rx descriptors: %d\n", error);
33939 - goto err;
33940 + rx_edma = &sc->rx.rx_edma[qtype];
33941 + if (list_empty(&sc->rx.rxbuf)) {
33942 + ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
33943 + return;
33944 }
33945
33946 + while (!list_empty(&sc->rx.rxbuf)) {
33947 + nbuf++;
33948 +
33949 + if (!ath_rx_edma_buf_link(sc, qtype))
33950 + break;
33951 +
33952 + if (nbuf >= size)
33953 + break;
33954 + }
33955 +}
33956 +
33957 +static void ath_rx_remove_buffer(struct ath_softc *sc,
33958 + enum ath9k_rx_qtype qtype)
33959 +{
33960 + struct ath_buf *bf;
33961 + struct ath_rx_edma *rx_edma;
33962 + struct sk_buff *skb;
33963 +
33964 + rx_edma = &sc->rx.rx_edma[qtype];
33965 +
33966 + while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
33967 + bf = SKB_CB_ATHBUF(skb);
33968 + BUG_ON(!bf);
33969 + list_add_tail(&bf->list, &sc->rx.rxbuf);
33970 + }
33971 +}
33972 +
33973 +static void ath_rx_edma_cleanup(struct ath_softc *sc)
33974 +{
33975 + struct ath_buf *bf;
33976 +
33977 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
33978 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
33979 +
33980 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
33981 + if (bf->bf_mpdu)
33982 + dev_kfree_skb_any(bf->bf_mpdu);
33983 + }
33984 +
33985 + INIT_LIST_HEAD(&sc->rx.rxbuf);
33986 +
33987 + kfree(sc->rx.rx_bufptr);
33988 + sc->rx.rx_bufptr = NULL;
33989 +}
33990 +
33991 +static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
33992 +{
33993 + skb_queue_head_init(&rx_edma->rx_fifo);
33994 + skb_queue_head_init(&rx_edma->rx_buffers);
33995 + rx_edma->rx_fifo_hwsize = size;
33996 +}
33997 +
33998 +static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
33999 +{
34000 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
34001 + struct ath_hw *ah = sc->sc_ah;
34002 + struct sk_buff *skb;
34003 + struct ath_buf *bf;
34004 + int error = 0, i;
34005 + u32 size;
34006 +
34007 +
34008 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
34009 + ah->caps.rx_status_len,
34010 + min(common->cachelsz, (u16)64));
34011 +
34012 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
34013 + ah->caps.rx_status_len);
34014 +
34015 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
34016 + ah->caps.rx_lp_qdepth);
34017 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
34018 + ah->caps.rx_hp_qdepth);
34019 +
34020 + size = sizeof(struct ath_buf) * nbufs;
34021 + bf = kzalloc(size, GFP_KERNEL);
34022 + if (!bf)
34023 + return -ENOMEM;
34024 +
34025 + INIT_LIST_HEAD(&sc->rx.rxbuf);
34026 + sc->rx.rx_bufptr = bf;
34027 +
34028 + for (i = 0; i < nbufs; i++, bf++) {
34029 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
34030 - if (skb == NULL) {
34031 + if (!skb) {
34032 error = -ENOMEM;
34033 - goto err;
34034 + goto rx_init_fail;
34035 }
34036
34037 + memset(skb->data, 0, common->rx_bufsize);
34038 bf->bf_mpdu = skb;
34039 +
34040 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
34041 common->rx_bufsize,
34042 - DMA_FROM_DEVICE);
34043 + DMA_BIDIRECTIONAL);
34044 if (unlikely(dma_mapping_error(sc->dev,
34045 - bf->bf_buf_addr))) {
34046 - dev_kfree_skb_any(skb);
34047 - bf->bf_mpdu = NULL;
34048 + bf->bf_buf_addr))) {
34049 + dev_kfree_skb_any(skb);
34050 + bf->bf_mpdu = NULL;
34051 + ath_print(common, ATH_DBG_FATAL,
34052 + "dma_mapping_error() on RX init\n");
34053 + error = -ENOMEM;
34054 + goto rx_init_fail;
34055 + }
34056 +
34057 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34058 + }
34059 +
34060 + return 0;
34061 +
34062 +rx_init_fail:
34063 + ath_rx_edma_cleanup(sc);
34064 + return error;
34065 +}
34066 +
34067 +static void ath_edma_start_recv(struct ath_softc *sc)
34068 +{
34069 + spin_lock_bh(&sc->rx.rxbuflock);
34070 +
34071 + ath9k_hw_rxena(sc->sc_ah);
34072 +
34073 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
34074 + sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
34075 +
34076 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
34077 + sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
34078 +
34079 + spin_unlock_bh(&sc->rx.rxbuflock);
34080 +
34081 + ath_opmode_init(sc);
34082 +
34083 + ath9k_hw_startpcureceive(sc->sc_ah);
34084 +}
34085 +
34086 +static void ath_edma_stop_recv(struct ath_softc *sc)
34087 +{
34088 + spin_lock_bh(&sc->rx.rxbuflock);
34089 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
34090 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
34091 + spin_unlock_bh(&sc->rx.rxbuflock);
34092 +}
34093 +
34094 +int ath_rx_init(struct ath_softc *sc, int nbufs)
34095 +{
34096 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
34097 + struct sk_buff *skb;
34098 + struct ath_buf *bf;
34099 + int error = 0;
34100 +
34101 + spin_lock_init(&sc->rx.rxflushlock);
34102 + sc->sc_flags &= ~SC_OP_RXFLUSH;
34103 + spin_lock_init(&sc->rx.rxbuflock);
34104 +
34105 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34106 + return ath_rx_edma_init(sc, nbufs);
34107 + } else {
34108 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
34109 + min(common->cachelsz, (u16)64));
34110 +
34111 + ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
34112 + common->cachelsz, common->rx_bufsize);
34113 +
34114 + /* Initialize rx descriptors */
34115 +
34116 + error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
34117 + "rx", nbufs, 1, 0);
34118 + if (error != 0) {
34119 ath_print(common, ATH_DBG_FATAL,
34120 - "dma_mapping_error() on RX init\n");
34121 - error = -ENOMEM;
34122 + "failed to allocate rx descriptors: %d\n",
34123 + error);
34124 goto err;
34125 }
34126 - bf->bf_dmacontext = bf->bf_buf_addr;
34127 +
34128 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34129 + skb = ath_rxbuf_alloc(common, common->rx_bufsize,
34130 + GFP_KERNEL);
34131 + if (skb == NULL) {
34132 + error = -ENOMEM;
34133 + goto err;
34134 + }
34135 +
34136 + bf->bf_mpdu = skb;
34137 + bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
34138 + common->rx_bufsize,
34139 + DMA_FROM_DEVICE);
34140 + if (unlikely(dma_mapping_error(sc->dev,
34141 + bf->bf_buf_addr))) {
34142 + dev_kfree_skb_any(skb);
34143 + bf->bf_mpdu = NULL;
34144 + ath_print(common, ATH_DBG_FATAL,
34145 + "dma_mapping_error() on RX init\n");
34146 + error = -ENOMEM;
34147 + goto err;
34148 + }
34149 + bf->bf_dmacontext = bf->bf_buf_addr;
34150 + }
34151 + sc->rx.rxlink = NULL;
34152 }
34153 - sc->rx.rxlink = NULL;
34154
34155 err:
34156 if (error)
34157 @@ -180,17 +373,23 @@ void ath_rx_cleanup(struct ath_softc *sc
34158 struct sk_buff *skb;
34159 struct ath_buf *bf;
34160
34161 - list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34162 - skb = bf->bf_mpdu;
34163 - if (skb) {
34164 - dma_unmap_single(sc->dev, bf->bf_buf_addr,
34165 - common->rx_bufsize, DMA_FROM_DEVICE);
34166 - dev_kfree_skb(skb);
34167 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34168 + ath_rx_edma_cleanup(sc);
34169 + return;
34170 + } else {
34171 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
34172 + skb = bf->bf_mpdu;
34173 + if (skb) {
34174 + dma_unmap_single(sc->dev, bf->bf_buf_addr,
34175 + common->rx_bufsize,
34176 + DMA_FROM_DEVICE);
34177 + dev_kfree_skb(skb);
34178 + }
34179 }
34180 - }
34181
34182 - if (sc->rx.rxdma.dd_desc_len != 0)
34183 - ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
34184 + if (sc->rx.rxdma.dd_desc_len != 0)
34185 + ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
34186 + }
34187 }
34188
34189 /*
34190 @@ -273,6 +472,11 @@ int ath_startrecv(struct ath_softc *sc)
34191 struct ath_hw *ah = sc->sc_ah;
34192 struct ath_buf *bf, *tbf;
34193
34194 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34195 + ath_edma_start_recv(sc);
34196 + return 0;
34197 + }
34198 +
34199 spin_lock_bh(&sc->rx.rxbuflock);
34200 if (list_empty(&sc->rx.rxbuf))
34201 goto start_recv;
34202 @@ -306,7 +510,11 @@ bool ath_stoprecv(struct ath_softc *sc)
34203 ath9k_hw_stoppcurecv(ah);
34204 ath9k_hw_setrxfilter(ah, 0);
34205 stopped = ath9k_hw_stopdmarecv(ah);
34206 - sc->rx.rxlink = NULL;
34207 +
34208 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34209 + ath_edma_stop_recv(sc);
34210 + else
34211 + sc->rx.rxlink = NULL;
34212
34213 return stopped;
34214 }
34215 @@ -315,7 +523,9 @@ void ath_flushrecv(struct ath_softc *sc)
34216 {
34217 spin_lock_bh(&sc->rx.rxflushlock);
34218 sc->sc_flags |= SC_OP_RXFLUSH;
34219 - ath_rx_tasklet(sc, 1);
34220 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34221 + ath_rx_tasklet(sc, 1, true);
34222 + ath_rx_tasklet(sc, 1, false);
34223 sc->sc_flags &= ~SC_OP_RXFLUSH;
34224 spin_unlock_bh(&sc->rx.rxflushlock);
34225 }
34226 @@ -469,14 +679,147 @@ static void ath_rx_send_to_mac80211(stru
34227 ieee80211_rx(hw, skb);
34228 }
34229
34230 -int ath_rx_tasklet(struct ath_softc *sc, int flush)
34231 +static bool ath_edma_get_buffers(struct ath_softc *sc,
34232 + enum ath9k_rx_qtype qtype)
34233 {
34234 -#define PA2DESC(_sc, _pa) \
34235 - ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
34236 - ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
34237 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
34238 + struct ath_hw *ah = sc->sc_ah;
34239 + struct ath_common *common = ath9k_hw_common(ah);
34240 + struct sk_buff *skb;
34241 + struct ath_buf *bf;
34242 + int ret;
34243 +
34244 + skb = skb_peek(&rx_edma->rx_fifo);
34245 + if (!skb)
34246 + return false;
34247 +
34248 + bf = SKB_CB_ATHBUF(skb);
34249 + BUG_ON(!bf);
34250 +
34251 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
34252 + common->rx_bufsize, DMA_FROM_DEVICE);
34253 +
34254 + ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
34255 + if (ret == -EINPROGRESS)
34256 + return false;
34257 +
34258 + __skb_unlink(skb, &rx_edma->rx_fifo);
34259 + if (ret == -EINVAL) {
34260 + /* corrupt descriptor, skip this one and the following one */
34261 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34262 + ath_rx_edma_buf_link(sc, qtype);
34263 + skb = skb_peek(&rx_edma->rx_fifo);
34264 + if (!skb)
34265 + return true;
34266
34267 + bf = SKB_CB_ATHBUF(skb);
34268 + BUG_ON(!bf);
34269 +
34270 + __skb_unlink(skb, &rx_edma->rx_fifo);
34271 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34272 + ath_rx_edma_buf_link(sc, qtype);
34273 + }
34274 + skb_queue_tail(&rx_edma->rx_buffers, skb);
34275 +
34276 + return true;
34277 +}
34278 +
34279 +static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
34280 + struct ath_rx_status *rs,
34281 + enum ath9k_rx_qtype qtype)
34282 +{
34283 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
34284 + struct sk_buff *skb;
34285 struct ath_buf *bf;
34286 +
34287 + while (ath_edma_get_buffers(sc, qtype));
34288 + skb = __skb_dequeue(&rx_edma->rx_buffers);
34289 + if (!skb)
34290 + return NULL;
34291 +
34292 + bf = SKB_CB_ATHBUF(skb);
34293 + ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
34294 + return bf;
34295 +}
34296 +
34297 +static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
34298 + struct ath_rx_status *rs)
34299 +{
34300 + struct ath_hw *ah = sc->sc_ah;
34301 + struct ath_common *common = ath9k_hw_common(ah);
34302 struct ath_desc *ds;
34303 + struct ath_buf *bf;
34304 + int ret;
34305 +
34306 + if (list_empty(&sc->rx.rxbuf)) {
34307 + sc->rx.rxlink = NULL;
34308 + return NULL;
34309 + }
34310 +
34311 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
34312 + ds = bf->bf_desc;
34313 +
34314 + /*
34315 + * Must provide the virtual address of the current
34316 + * descriptor, the physical address, and the virtual
34317 + * address of the next descriptor in the h/w chain.
34318 + * This allows the HAL to look ahead to see if the
34319 + * hardware is done with a descriptor by checking the
34320 + * done bit in the following descriptor and the address
34321 + * of the current descriptor the DMA engine is working
34322 + * on. All this is necessary because of our use of
34323 + * a self-linked list to avoid rx overruns.
34324 + */
34325 + ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
34326 + if (ret == -EINPROGRESS) {
34327 + struct ath_rx_status trs;
34328 + struct ath_buf *tbf;
34329 + struct ath_desc *tds;
34330 +
34331 + memset(&trs, 0, sizeof(trs));
34332 + if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
34333 + sc->rx.rxlink = NULL;
34334 + return NULL;
34335 + }
34336 +
34337 + tbf = list_entry(bf->list.next, struct ath_buf, list);
34338 +
34339 + /*
34340 + * On some hardware the descriptor status words could
34341 + * get corrupted, including the done bit. Because of
34342 + * this, check if the next descriptor's done bit is
34343 + * set or not.
34344 + *
34345 + * If the next descriptor's done bit is set, the current
34346 + * descriptor has been corrupted. Force s/w to discard
34347 + * this descriptor and continue...
34348 + */
34349 +
34350 + tds = tbf->bf_desc;
34351 + ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
34352 + if (ret == -EINPROGRESS)
34353 + return NULL;
34354 + }
34355 +
34356 + if (!bf->bf_mpdu)
34357 + return bf;
34358 +
34359 + /*
34360 + * Synchronize the DMA transfer with CPU before
34361 + * 1. accessing the frame
34362 + * 2. requeueing the same buffer to h/w
34363 + */
34364 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
34365 + common->rx_bufsize,
34366 + DMA_FROM_DEVICE);
34367 +
34368 + return bf;
34369 +}
34370 +
34371 +
34372 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
34373 +{
34374 + struct ath_buf *bf;
34375 struct sk_buff *skb = NULL, *requeue_skb;
34376 struct ieee80211_rx_status *rxs;
34377 struct ath_hw *ah = sc->sc_ah;
34378 @@ -491,7 +834,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
34379 int retval;
34380 bool decrypt_error = false;
34381 struct ath_rx_status rs;
34382 + enum ath9k_rx_qtype qtype;
34383 + bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
34384 + int dma_type;
34385 +
34386 + if (edma)
34387 + dma_type = DMA_FROM_DEVICE;
34388 + else
34389 + dma_type = DMA_BIDIRECTIONAL;
34390
34391 + qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
34392 spin_lock_bh(&sc->rx.rxbuflock);
34393
34394 do {
34395 @@ -499,71 +851,19 @@ int ath_rx_tasklet(struct ath_softc *sc,
34396 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
34397 break;
34398
34399 - if (list_empty(&sc->rx.rxbuf)) {
34400 - sc->rx.rxlink = NULL;
34401 - break;
34402 - }
34403 -
34404 - bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
34405 - ds = bf->bf_desc;
34406 -
34407 - /*
34408 - * Must provide the virtual address of the current
34409 - * descriptor, the physical address, and the virtual
34410 - * address of the next descriptor in the h/w chain.
34411 - * This allows the HAL to look ahead to see if the
34412 - * hardware is done with a descriptor by checking the
34413 - * done bit in the following descriptor and the address
34414 - * of the current descriptor the DMA engine is working
34415 - * on. All this is necessary because of our use of
34416 - * a self-linked list to avoid rx overruns.
34417 - */
34418 memset(&rs, 0, sizeof(rs));
34419 - retval = ath9k_hw_rxprocdesc(ah, ds, &rs, 0);
34420 - if (retval == -EINPROGRESS) {
34421 - struct ath_rx_status trs;
34422 - struct ath_buf *tbf;
34423 - struct ath_desc *tds;
34424 -
34425 - memset(&trs, 0, sizeof(trs));
34426 - if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
34427 - sc->rx.rxlink = NULL;
34428 - break;
34429 - }
34430 + if (edma)
34431 + bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
34432 + else
34433 + bf = ath_get_next_rx_buf(sc, &rs);
34434
34435 - tbf = list_entry(bf->list.next, struct ath_buf, list);
34436 -
34437 - /*
34438 - * On some hardware the descriptor status words could
34439 - * get corrupted, including the done bit. Because of
34440 - * this, check if the next descriptor's done bit is
34441 - * set or not.
34442 - *
34443 - * If the next descriptor's done bit is set, the current
34444 - * descriptor has been corrupted. Force s/w to discard
34445 - * this descriptor and continue...
34446 - */
34447 -
34448 - tds = tbf->bf_desc;
34449 - retval = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
34450 - if (retval == -EINPROGRESS) {
34451 - break;
34452 - }
34453 - }
34454 + if (!bf)
34455 + break;
34456
34457 skb = bf->bf_mpdu;
34458 if (!skb)
34459 continue;
34460
34461 - /*
34462 - * Synchronize the DMA transfer with CPU before
34463 - * 1. accessing the frame
34464 - * 2. requeueing the same buffer to h/w
34465 - */
34466 - dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
34467 - common->rx_bufsize,
34468 - DMA_FROM_DEVICE);
34469 -
34470 hdr = (struct ieee80211_hdr *) skb->data;
34471 rxs = IEEE80211_SKB_RXCB(skb);
34472
34473 @@ -597,9 +897,11 @@ int ath_rx_tasklet(struct ath_softc *sc,
34474 /* Unmap the frame */
34475 dma_unmap_single(sc->dev, bf->bf_buf_addr,
34476 common->rx_bufsize,
34477 - DMA_FROM_DEVICE);
34478 + dma_type);
34479
34480 - skb_put(skb, rs.rs_datalen);
34481 + skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
34482 + if (ah->caps.rx_status_len)
34483 + skb_pull(skb, ah->caps.rx_status_len);
34484
34485 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
34486 rxs, decrypt_error);
34487 @@ -608,7 +910,7 @@ int ath_rx_tasklet(struct ath_softc *sc,
34488 bf->bf_mpdu = requeue_skb;
34489 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
34490 common->rx_bufsize,
34491 - DMA_FROM_DEVICE);
34492 + dma_type);
34493 if (unlikely(dma_mapping_error(sc->dev,
34494 bf->bf_buf_addr))) {
34495 dev_kfree_skb_any(requeue_skb);
34496 @@ -639,12 +941,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
34497 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
34498
34499 requeue:
34500 - list_move_tail(&bf->list, &sc->rx.rxbuf);
34501 - ath_rx_buf_link(sc, bf);
34502 + if (edma) {
34503 + list_add_tail(&bf->list, &sc->rx.rxbuf);
34504 + ath_rx_edma_buf_link(sc, qtype);
34505 + } else {
34506 + list_move_tail(&bf->list, &sc->rx.rxbuf);
34507 + ath_rx_buf_link(sc, bf);
34508 + }
34509 } while (1);
34510
34511 spin_unlock_bh(&sc->rx.rxbuflock);
34512
34513 return 0;
34514 -#undef PA2DESC
34515 }
34516 --- a/drivers/net/wireless/ath/ath9k/reg.h
34517 +++ b/drivers/net/wireless/ath/ath9k/reg.h
34518 @@ -20,7 +20,7 @@
34519 #include "../reg.h"
34520
34521 #define AR_CR 0x0008
34522 -#define AR_CR_RXE 0x00000004
34523 +#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
34524 #define AR_CR_RXD 0x00000020
34525 #define AR_CR_SWI 0x00000040
34526
34527 @@ -39,6 +39,12 @@
34528 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
34529 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
34530
34531 +#define AR_RXBP_THRESH 0x0018
34532 +#define AR_RXBP_THRESH_HP 0x0000000f
34533 +#define AR_RXBP_THRESH_HP_S 0
34534 +#define AR_RXBP_THRESH_LP 0x00003f00
34535 +#define AR_RXBP_THRESH_LP_S 8
34536 +
34537 #define AR_MIRT 0x0020
34538 #define AR_MIRT_VAL 0x0000ffff
34539 #define AR_MIRT_VAL_S 16
34540 @@ -144,6 +150,9 @@
34541 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
34542 #define AR_MACMISC_MISC_OBS_BUS_1 1
34543
34544 +#define AR_DATABUF_SIZE 0x0060
34545 +#define AR_DATABUF_SIZE_MASK 0x00000FFF
34546 +
34547 #define AR_GTXTO 0x0064
34548 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
34549 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
34550 @@ -160,9 +169,14 @@
34551 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
34552 #define AR_CST_TIMEOUT_LIMIT_S 16
34553
34554 +#define AR_HP_RXDP 0x0074
34555 +#define AR_LP_RXDP 0x0078
34556 +
34557 #define AR_ISR 0x0080
34558 #define AR_ISR_RXOK 0x00000001
34559 #define AR_ISR_RXDESC 0x00000002
34560 +#define AR_ISR_HP_RXOK 0x00000001
34561 +#define AR_ISR_LP_RXOK 0x00000002
34562 #define AR_ISR_RXERR 0x00000004
34563 #define AR_ISR_RXNOPKT 0x00000008
34564 #define AR_ISR_RXEOL 0x00000010
34565 @@ -232,7 +246,6 @@
34566 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
34567 #define AR_ISR_S5_TIM_TIMER 0x00000010
34568 #define AR_ISR_S5_DTIM_TIMER 0x00000020
34569 -#define AR_ISR_S5_S 0x00d8
34570 #define AR_IMR_S5 0x00b8
34571 #define AR_IMR_S5_TIM_TIMER 0x00000010
34572 #define AR_IMR_S5_DTIM_TIMER 0x00000020
34573 @@ -240,7 +253,6 @@
34574 #define AR_ISR_S5_GENTIMER_TRIG_S 0
34575 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
34576 #define AR_ISR_S5_GENTIMER_THRESH_S 16
34577 -#define AR_ISR_S5_S 0x00d8
34578 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
34579 #define AR_IMR_S5_GENTIMER_TRIG_S 0
34580 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
34581 @@ -249,6 +261,8 @@
34582 #define AR_IMR 0x00a0
34583 #define AR_IMR_RXOK 0x00000001
34584 #define AR_IMR_RXDESC 0x00000002
34585 +#define AR_IMR_RXOK_HP 0x00000001
34586 +#define AR_IMR_RXOK_LP 0x00000002
34587 #define AR_IMR_RXERR 0x00000004
34588 #define AR_IMR_RXNOPKT 0x00000008
34589 #define AR_IMR_RXEOL 0x00000010
34590 @@ -332,10 +346,10 @@
34591 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
34592 #define AR_ISR_S1_QCU_TXEOL_S 16
34593
34594 -#define AR_ISR_S2_S 0x00cc
34595 -#define AR_ISR_S3_S 0x00d0
34596 -#define AR_ISR_S4_S 0x00d4
34597 -#define AR_ISR_S5_S 0x00d8
34598 +#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
34599 +#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
34600 +#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
34601 +#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
34602 #define AR_DMADBG_0 0x00e0
34603 #define AR_DMADBG_1 0x00e4
34604 #define AR_DMADBG_2 0x00e8
34605 @@ -369,6 +383,9 @@
34606 #define AR_Q9_TXDP 0x0824
34607 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
34608
34609 +#define AR_Q_STATUS_RING_START 0x830
34610 +#define AR_Q_STATUS_RING_END 0x834
34611 +
34612 #define AR_Q_TXE 0x0840
34613 #define AR_Q_TXE_M 0x000003FF
34614
34615 @@ -461,6 +478,10 @@
34616 #define AR_Q_RDYTIMESHDN 0x0a40
34617 #define AR_Q_RDYTIMESHDN_M 0x000003FF
34618
34619 +/* MAC Descriptor CRC check */
34620 +#define AR_Q_DESC_CRCCHK 0xa44
34621 +/* Enable CRC check on the descriptor fetched from host */
34622 +#define AR_Q_DESC_CRCCHK_EN 1
34623
34624 #define AR_NUM_DCU 10
34625 #define AR_DCU_0 0x0001
34626 @@ -759,6 +780,8 @@
34627 #define AR_SREV_VERSION_9271 0x140
34628 #define AR_SREV_REVISION_9271_10 0
34629 #define AR_SREV_REVISION_9271_11 1
34630 +#define AR_SREV_VERSION_9300 0x1c0
34631 +#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
34632
34633 #define AR_SREV_5416(_ah) \
34634 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
34635 @@ -844,6 +867,15 @@
34636 #define AR_SREV_9271_11(_ah) \
34637 (AR_SREV_9271(_ah) && \
34638 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
34639 +#define AR_SREV_9300(_ah) \
34640 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
34641 +#define AR_SREV_9300_20(_ah) \
34642 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
34643 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
34644 +#define AR_SREV_9300_20_OR_LATER(_ah) \
34645 + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
34646 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
34647 + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
34648
34649 #define AR_SREV_9285E_20(_ah) \
34650 (AR_SREV_9285_12_OR_LATER(_ah) && \
34651 @@ -945,6 +977,7 @@ enum {
34652 #define AR9285_NUM_GPIO 12
34653 #define AR9287_NUM_GPIO 11
34654 #define AR9271_NUM_GPIO 16
34655 +#define AR9300_NUM_GPIO 17
34656
34657 #define AR_GPIO_IN_OUT 0x4048
34658 #define AR_GPIO_IN_VAL 0x0FFFC000
34659 @@ -957,19 +990,21 @@ enum {
34660 #define AR9287_GPIO_IN_VAL_S 11
34661 #define AR9271_GPIO_IN_VAL 0xFFFF0000
34662 #define AR9271_GPIO_IN_VAL_S 16
34663 +#define AR9300_GPIO_IN_VAL 0x0001FFFF
34664 +#define AR9300_GPIO_IN_VAL_S 0
34665
34666 -#define AR_GPIO_OE_OUT 0x404c
34667 +#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
34668 #define AR_GPIO_OE_OUT_DRV 0x3
34669 #define AR_GPIO_OE_OUT_DRV_NO 0x0
34670 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
34671 #define AR_GPIO_OE_OUT_DRV_HI 0x2
34672 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
34673
34674 -#define AR_GPIO_INTR_POL 0x4050
34675 -#define AR_GPIO_INTR_POL_VAL 0x00001FFF
34676 +#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
34677 +#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
34678 #define AR_GPIO_INTR_POL_VAL_S 0
34679
34680 -#define AR_GPIO_INPUT_EN_VAL 0x4054
34681 +#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
34682 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
34683 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
34684 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
34685 @@ -987,13 +1022,13 @@ enum {
34686 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
34687 #define AR_GPIO_JTAG_DISABLE 0x00020000
34688
34689 -#define AR_GPIO_INPUT_MUX1 0x4058
34690 +#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
34691 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
34692 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
34693 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
34694 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
34695
34696 -#define AR_GPIO_INPUT_MUX2 0x405c
34697 +#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
34698 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
34699 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
34700 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
34701 @@ -1001,13 +1036,13 @@ enum {
34702 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
34703 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
34704
34705 -#define AR_GPIO_OUTPUT_MUX1 0x4060
34706 -#define AR_GPIO_OUTPUT_MUX2 0x4064
34707 -#define AR_GPIO_OUTPUT_MUX3 0x4068
34708 +#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
34709 +#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
34710 +#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
34711
34712 -#define AR_INPUT_STATE 0x406c
34713 +#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
34714
34715 -#define AR_EEPROM_STATUS_DATA 0x407c
34716 +#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
34717 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
34718 #define AR_EEPROM_STATUS_DATA_VAL_S 0
34719 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
34720 @@ -1015,13 +1050,24 @@ enum {
34721 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
34722 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
34723
34724 -#define AR_OBS 0x4080
34725 +#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
34726
34727 -#define AR_GPIO_PDPU 0x4088
34728 +#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
34729
34730 -#define AR_PCIE_MSI 0x4094
34731 +#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
34732 #define AR_PCIE_MSI_ENABLE 0x00000001
34733
34734 +#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
34735 +#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
34736 +#define AR_INTR_PRIO_SYNC_MASK 0x40cc
34737 +#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
34738 +
34739 +#define AR_RTC_9300_PLL_DIV 0x000003ff
34740 +#define AR_RTC_9300_PLL_DIV_S 0
34741 +#define AR_RTC_9300_PLL_REFDIV 0x00003C00
34742 +#define AR_RTC_9300_PLL_REFDIV_S 10
34743 +#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
34744 +#define AR_RTC_9300_PLL_CLKSEL_S 14
34745
34746 #define AR_RTC_9160_PLL_DIV 0x000003ff
34747 #define AR_RTC_9160_PLL_DIV_S 0
34748 @@ -1039,6 +1085,16 @@ enum {
34749 #define AR_RTC_RC_COLD_RESET 0x00000004
34750 #define AR_RTC_RC_WARM_RESET 0x00000008
34751
34752 +/* Crystal Control */
34753 +#define AR_RTC_XTAL_CONTROL 0x7004
34754 +
34755 +/* Reg Control 0 */
34756 +#define AR_RTC_REG_CONTROL0 0x7008
34757 +
34758 +/* Reg Control 1 */
34759 +#define AR_RTC_REG_CONTROL1 0x700c
34760 +#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
34761 +
34762 #define AR_RTC_PLL_CONTROL \
34763 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
34764
34765 @@ -1069,6 +1125,7 @@ enum {
34766 #define AR_RTC_SLEEP_CLK \
34767 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
34768 #define AR_RTC_FORCE_DERIVED_CLK 0x2
34769 +#define AR_RTC_FORCE_SWREG_PRD 0x00000004
34770
34771 #define AR_RTC_FORCE_WAKE \
34772 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
34773 @@ -1533,7 +1590,7 @@ enum {
34774 #define AR_TSFOOR_THRESHOLD 0x813c
34775 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
34776
34777 -#define AR_PHY_ERR_EIFS_MASK 8144
34778 +#define AR_PHY_ERR_EIFS_MASK 0x8144
34779
34780 #define AR_PHY_ERR_3 0x8168
34781 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
34782 @@ -1599,24 +1656,26 @@ enum {
34783 #define AR_FIRST_NDP_TIMER 7
34784 #define AR_NDP2_PERIOD 0x81a0
34785 #define AR_NDP2_TIMER_MODE 0x81c0
34786 -#define AR_NEXT_TBTT_TIMER 0x8200
34787 -#define AR_NEXT_DMA_BEACON_ALERT 0x8204
34788 -#define AR_NEXT_SWBA 0x8208
34789 -#define AR_NEXT_CFP 0x8208
34790 -#define AR_NEXT_HCF 0x820C
34791 -#define AR_NEXT_TIM 0x8210
34792 -#define AR_NEXT_DTIM 0x8214
34793 -#define AR_NEXT_QUIET_TIMER 0x8218
34794 -#define AR_NEXT_NDP_TIMER 0x821C
34795 -
34796 -#define AR_BEACON_PERIOD 0x8220
34797 -#define AR_DMA_BEACON_PERIOD 0x8224
34798 -#define AR_SWBA_PERIOD 0x8228
34799 -#define AR_HCF_PERIOD 0x822C
34800 -#define AR_TIM_PERIOD 0x8230
34801 -#define AR_DTIM_PERIOD 0x8234
34802 -#define AR_QUIET_PERIOD 0x8238
34803 -#define AR_NDP_PERIOD 0x823C
34804 +
34805 +#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
34806 +#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
34807 +#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
34808 +#define AR_NEXT_SWBA AR_GEN_TIMERS(2)
34809 +#define AR_NEXT_CFP AR_GEN_TIMERS(2)
34810 +#define AR_NEXT_HCF AR_GEN_TIMERS(3)
34811 +#define AR_NEXT_TIM AR_GEN_TIMERS(4)
34812 +#define AR_NEXT_DTIM AR_GEN_TIMERS(5)
34813 +#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
34814 +#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
34815 +
34816 +#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
34817 +#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
34818 +#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
34819 +#define AR_HCF_PERIOD AR_GEN_TIMERS(11)
34820 +#define AR_TIM_PERIOD AR_GEN_TIMERS(12)
34821 +#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
34822 +#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
34823 +#define AR_NDP_PERIOD AR_GEN_TIMERS(15)
34824
34825 #define AR_TIMER_MODE 0x8240
34826 #define AR_TBTT_TIMER_EN 0x00000001
34827 @@ -1730,4 +1789,32 @@ enum {
34828 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
34829 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
34830
34831 +#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
34832 +#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
34833 + * based on both MAC Address and Key ID.
34834 + * If bit is 0, then Multicast search is
34835 + * based on MAC address only.
34836 + * For Merlin and above only.
34837 + */
34838 +#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
34839 + * when it is enable, AGG_WEP would takes
34840 + * charge of the encryption interface of
34841 + * pcu_txsm.
34842 + */
34843 +
34844 +#define AR9300_SM_BASE 0xa200
34845 +#define AR9002_PHY_AGC_CONTROL 0x9860
34846 +#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
34847 +#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
34848 +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
34849 +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
34850 +#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
34851 +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
34852 +#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
34853 +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
34854 +#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
34855 +#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
34856 +#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
34857 +#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
34858 +
34859 #endif
34860 --- a/drivers/net/wireless/ath/ath9k/xmit.c
34861 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
34862 @@ -15,6 +15,7 @@
34863 */
34864
34865 #include "ath9k.h"
34866 +#include "ar9003_mac.h"
34867
34868 #define BITS_PER_BYTE 8
34869 #define OFDM_PLCP_BITS 22
34870 @@ -91,7 +92,6 @@ static int ath_max_4ms_framelen[3][16] =
34871 }
34872 };
34873
34874 -
34875 /*********************/
34876 /* Aggregation logic */
34877 /*********************/
34878 @@ -279,7 +279,7 @@ static struct ath_buf* ath_clone_txbuf(s
34879 tbf->aphy = bf->aphy;
34880 tbf->bf_mpdu = bf->bf_mpdu;
34881 tbf->bf_buf_addr = bf->bf_buf_addr;
34882 - *(tbf->bf_desc) = *(bf->bf_desc);
34883 + memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
34884 tbf->bf_state = bf->bf_state;
34885 tbf->bf_dmacontext = bf->bf_dmacontext;
34886
34887 @@ -359,7 +359,7 @@ static void ath_tx_complete_aggr(struct
34888 acked_cnt++;
34889 } else {
34890 if (!(tid->state & AGGR_CLEANUP) &&
34891 - ts->ts_flags != ATH9K_TX_SW_ABORTED) {
34892 + !bf_last->bf_tx_aborted) {
34893 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
34894 ath_tx_set_retry(sc, txq, bf);
34895 txpending = 1;
34896 @@ -378,7 +378,8 @@ static void ath_tx_complete_aggr(struct
34897 }
34898 }
34899
34900 - if (bf_next == NULL) {
34901 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
34902 + bf_next == NULL) {
34903 /*
34904 * Make sure the last desc is reclaimed if it
34905 * not a holding desc.
34906 @@ -412,36 +413,43 @@ static void ath_tx_complete_aggr(struct
34907 !txfail, sendbar);
34908 } else {
34909 /* retry the un-acked ones */
34910 - if (bf->bf_next == NULL && bf_last->bf_stale) {
34911 - struct ath_buf *tbf;
34912 -
34913 - tbf = ath_clone_txbuf(sc, bf_last);
34914 - /*
34915 - * Update tx baw and complete the frame with
34916 - * failed status if we run out of tx buf
34917 - */
34918 - if (!tbf) {
34919 - spin_lock_bh(&txq->axq_lock);
34920 - ath_tx_update_baw(sc, tid,
34921 - bf->bf_seqno);
34922 - spin_unlock_bh(&txq->axq_lock);
34923 -
34924 - bf->bf_state.bf_type |= BUF_XRETRY;
34925 - ath_tx_rc_status(bf, ts, nbad,
34926 - 0, false);
34927 - ath_tx_complete_buf(sc, bf, txq,
34928 - &bf_head, ts, 0, 0);
34929 - break;
34930 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
34931 + if (bf->bf_next == NULL && bf_last->bf_stale) {
34932 + struct ath_buf *tbf;
34933 +
34934 + tbf = ath_clone_txbuf(sc, bf_last);
34935 + /*
34936 + * Update tx baw and complete the
34937 + * frame with failed status if we
34938 + * run out of tx buf.
34939 + */
34940 + if (!tbf) {
34941 + spin_lock_bh(&txq->axq_lock);
34942 + ath_tx_update_baw(sc, tid,
34943 + bf->bf_seqno);
34944 + spin_unlock_bh(&txq->axq_lock);
34945 +
34946 + bf->bf_state.bf_type |=
34947 + BUF_XRETRY;
34948 + ath_tx_rc_status(bf, ts, nbad,
34949 + 0, false);
34950 + ath_tx_complete_buf(sc, bf, txq,
34951 + &bf_head,
34952 + ts, 0, 0);
34953 + break;
34954 + }
34955 +
34956 + ath9k_hw_cleartxdesc(sc->sc_ah,
34957 + tbf->bf_desc);
34958 + list_add_tail(&tbf->list, &bf_head);
34959 + } else {
34960 + /*
34961 + * Clear descriptor status words for
34962 + * software retry
34963 + */
34964 + ath9k_hw_cleartxdesc(sc->sc_ah,
34965 + bf->bf_desc);
34966 }
34967 -
34968 - ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
34969 - list_add_tail(&tbf->list, &bf_head);
34970 - } else {
34971 - /*
34972 - * Clear descriptor status words for
34973 - * software retry
34974 - */
34975 - ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
34976 }
34977
34978 /*
34979 @@ -665,7 +673,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
34980 bpad = PADBYTES(al_delta) + (ndelim << 2);
34981
34982 bf->bf_next = NULL;
34983 - bf->bf_desc->ds_link = 0;
34984 + ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
34985
34986 /* link buffers of this frame to the aggregate */
34987 ath_tx_addto_baw(sc, tid, bf);
34988 @@ -673,7 +681,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_
34989 list_move_tail(&bf->list, bf_q);
34990 if (bf_prev) {
34991 bf_prev->bf_next = bf;
34992 - bf_prev->bf_desc->ds_link = bf->bf_daddr;
34993 + ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
34994 + bf->bf_daddr);
34995 }
34996 bf_prev = bf;
34997
34998 @@ -853,7 +862,7 @@ struct ath_txq *ath_txq_setup(struct ath
34999 struct ath_hw *ah = sc->sc_ah;
35000 struct ath_common *common = ath9k_hw_common(ah);
35001 struct ath9k_tx_queue_info qi;
35002 - int qnum;
35003 + int qnum, i;
35004
35005 memset(&qi, 0, sizeof(qi));
35006 qi.tqi_subtype = subtype;
35007 @@ -877,11 +886,16 @@ struct ath_txq *ath_txq_setup(struct ath
35008 * The UAPSD queue is an exception, since we take a desc-
35009 * based intr on the EOSP frames.
35010 */
35011 - if (qtype == ATH9K_TX_QUEUE_UAPSD)
35012 - qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
35013 - else
35014 - qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
35015 - TXQ_FLAG_TXDESCINT_ENABLE;
35016 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35017 + qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
35018 + TXQ_FLAG_TXERRINT_ENABLE;
35019 + } else {
35020 + if (qtype == ATH9K_TX_QUEUE_UAPSD)
35021 + qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
35022 + else
35023 + qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
35024 + TXQ_FLAG_TXDESCINT_ENABLE;
35025 + }
35026 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
35027 if (qnum == -1) {
35028 /*
35029 @@ -908,6 +922,11 @@ struct ath_txq *ath_txq_setup(struct ath
35030 txq->axq_depth = 0;
35031 txq->axq_tx_inprogress = false;
35032 sc->tx.txqsetup |= 1<<qnum;
35033 +
35034 + txq->txq_headidx = txq->txq_tailidx = 0;
35035 + for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
35036 + INIT_LIST_HEAD(&txq->txq_fifo[i]);
35037 + INIT_LIST_HEAD(&txq->txq_fifo_pending);
35038 }
35039 return &sc->tx.txq[qnum];
35040 }
35041 @@ -1035,36 +1054,54 @@ void ath_draintxq(struct ath_softc *sc,
35042 struct ath_tx_status ts;
35043
35044 memset(&ts, 0, sizeof(ts));
35045 - if (!retry_tx)
35046 - ts.ts_flags = ATH9K_TX_SW_ABORTED;
35047 -
35048 INIT_LIST_HEAD(&bf_head);
35049
35050 for (;;) {
35051 spin_lock_bh(&txq->axq_lock);
35052
35053 - if (list_empty(&txq->axq_q)) {
35054 - txq->axq_link = NULL;
35055 - spin_unlock_bh(&txq->axq_lock);
35056 - break;
35057 - }
35058 -
35059 - bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
35060 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35061 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
35062 + txq->txq_headidx = txq->txq_tailidx = 0;
35063 + spin_unlock_bh(&txq->axq_lock);
35064 + break;
35065 + } else {
35066 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
35067 + struct ath_buf, list);
35068 + }
35069 + } else {
35070 + if (list_empty(&txq->axq_q)) {
35071 + txq->axq_link = NULL;
35072 + spin_unlock_bh(&txq->axq_lock);
35073 + break;
35074 + }
35075 + bf = list_first_entry(&txq->axq_q, struct ath_buf,
35076 + list);
35077
35078 - if (bf->bf_stale) {
35079 - list_del(&bf->list);
35080 - spin_unlock_bh(&txq->axq_lock);
35081 + if (bf->bf_stale) {
35082 + list_del(&bf->list);
35083 + spin_unlock_bh(&txq->axq_lock);
35084
35085 - spin_lock_bh(&sc->tx.txbuflock);
35086 - list_add_tail(&bf->list, &sc->tx.txbuf);
35087 - spin_unlock_bh(&sc->tx.txbuflock);
35088 - continue;
35089 + spin_lock_bh(&sc->tx.txbuflock);
35090 + list_add_tail(&bf->list, &sc->tx.txbuf);
35091 + spin_unlock_bh(&sc->tx.txbuflock);
35092 + continue;
35093 + }
35094 }
35095
35096 lastbf = bf->bf_lastbf;
35097 + if (!retry_tx)
35098 + lastbf->bf_tx_aborted = true;
35099 +
35100 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35101 + list_cut_position(&bf_head,
35102 + &txq->txq_fifo[txq->txq_tailidx],
35103 + &lastbf->list);
35104 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
35105 + } else {
35106 + /* remove ath_buf's of the same mpdu from txq */
35107 + list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
35108 + }
35109
35110 - /* remove ath_buf's of the same mpdu from txq */
35111 - list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
35112 txq->axq_depth--;
35113
35114 spin_unlock_bh(&txq->axq_lock);
35115 @@ -1087,6 +1124,27 @@ void ath_draintxq(struct ath_softc *sc,
35116 spin_unlock_bh(&txq->axq_lock);
35117 }
35118 }
35119 +
35120 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35121 + spin_lock_bh(&txq->axq_lock);
35122 + while (!list_empty(&txq->txq_fifo_pending)) {
35123 + bf = list_first_entry(&txq->txq_fifo_pending,
35124 + struct ath_buf, list);
35125 + list_cut_position(&bf_head,
35126 + &txq->txq_fifo_pending,
35127 + &bf->bf_lastbf->list);
35128 + spin_unlock_bh(&txq->axq_lock);
35129 +
35130 + if (bf_isampdu(bf))
35131 + ath_tx_complete_aggr(sc, txq, bf, &bf_head,
35132 + &ts, 0);
35133 + else
35134 + ath_tx_complete_buf(sc, bf, txq, &bf_head,
35135 + &ts, 0, 0);
35136 + spin_lock_bh(&txq->axq_lock);
35137 + }
35138 + spin_unlock_bh(&txq->axq_lock);
35139 + }
35140 }
35141
35142 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
35143 @@ -1224,25 +1282,47 @@ static void ath_tx_txqaddbuf(struct ath_
35144
35145 bf = list_first_entry(head, struct ath_buf, list);
35146
35147 - list_splice_tail_init(head, &txq->axq_q);
35148 - txq->axq_depth++;
35149 -
35150 ath_print(common, ATH_DBG_QUEUE,
35151 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
35152
35153 - if (txq->axq_link == NULL) {
35154 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35155 + if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
35156 + list_splice_tail_init(head, &txq->txq_fifo_pending);
35157 + return;
35158 + }
35159 + if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
35160 + ath_print(common, ATH_DBG_XMIT,
35161 + "Initializing tx fifo %d which "
35162 + "is non-empty\n",
35163 + txq->txq_headidx);
35164 + INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
35165 + list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
35166 + INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
35167 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
35168 ath_print(common, ATH_DBG_XMIT,
35169 "TXDP[%u] = %llx (%p)\n",
35170 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
35171 } else {
35172 - *txq->axq_link = bf->bf_daddr;
35173 - ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
35174 - txq->axq_qnum, txq->axq_link,
35175 - ito64(bf->bf_daddr), bf->bf_desc);
35176 + list_splice_tail_init(head, &txq->axq_q);
35177 +
35178 + if (txq->axq_link == NULL) {
35179 + ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
35180 + ath_print(common, ATH_DBG_XMIT,
35181 + "TXDP[%u] = %llx (%p)\n",
35182 + txq->axq_qnum, ito64(bf->bf_daddr),
35183 + bf->bf_desc);
35184 + } else {
35185 + *txq->axq_link = bf->bf_daddr;
35186 + ath_print(common, ATH_DBG_XMIT,
35187 + "link[%u] (%p)=%llx (%p)\n",
35188 + txq->axq_qnum, txq->axq_link,
35189 + ito64(bf->bf_daddr), bf->bf_desc);
35190 + }
35191 + ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
35192 + &txq->axq_link);
35193 + ath9k_hw_txstart(ah, txq->axq_qnum);
35194 }
35195 - txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
35196 - ath9k_hw_txstart(ah, txq->axq_qnum);
35197 + txq->axq_depth++;
35198 }
35199
35200 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
35201 @@ -1408,8 +1488,7 @@ static void assign_aggr_tid_seqno(struct
35202 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
35203 }
35204
35205 -static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
35206 - struct ath_txq *txq)
35207 +static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
35208 {
35209 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
35210 int flags = 0;
35211 @@ -1420,6 +1499,9 @@ static int setup_tx_flags(struct ath_sof
35212 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
35213 flags |= ATH9K_TXDESC_NOACK;
35214
35215 + if (use_ldpc)
35216 + flags |= ATH9K_TXDESC_LDPC;
35217 +
35218 return flags;
35219 }
35220
35221 @@ -1571,6 +1653,7 @@ static int ath_tx_setup_buffer(struct ie
35222 int hdrlen;
35223 __le16 fc;
35224 int padpos, padsize;
35225 + bool use_ldpc = false;
35226
35227 tx_info->pad[0] = 0;
35228 switch (txctl->frame_type) {
35229 @@ -1597,10 +1680,13 @@ static int ath_tx_setup_buffer(struct ie
35230 bf->bf_frmlen -= padsize;
35231 }
35232
35233 - if (conf_is_ht(&hw->conf))
35234 + if (conf_is_ht(&hw->conf)) {
35235 bf->bf_state.bf_type |= BUF_HT;
35236 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
35237 + use_ldpc = true;
35238 + }
35239
35240 - bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
35241 + bf->bf_flags = setup_tx_flags(skb, use_ldpc);
35242
35243 bf->bf_keytype = get_hw_crypto_keytype(skb);
35244 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
35245 @@ -1659,8 +1745,7 @@ static void ath_tx_start_dma(struct ath_
35246 list_add_tail(&bf->list, &bf_head);
35247
35248 ds = bf->bf_desc;
35249 - ds->ds_link = 0;
35250 - ds->ds_data = bf->bf_buf_addr;
35251 + ath9k_hw_set_desc_link(ah, ds, 0);
35252
35253 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
35254 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
35255 @@ -1669,7 +1754,9 @@ static void ath_tx_start_dma(struct ath_
35256 skb->len, /* segment length */
35257 true, /* first segment */
35258 true, /* last segment */
35259 - ds); /* first descriptor */
35260 + ds, /* first descriptor */
35261 + bf->bf_buf_addr,
35262 + txctl->txq->axq_qnum);
35263
35264 spin_lock_bh(&txctl->txq->axq_lock);
35265
35266 @@ -1896,7 +1983,7 @@ static int ath_tx_num_badfrms(struct ath
35267 int nbad = 0;
35268 int isaggr = 0;
35269
35270 - if (ts->ts_flags == ATH9K_TX_SW_ABORTED)
35271 + if (bf->bf_tx_aborted)
35272 return 0;
35273
35274 isaggr = bf_isaggr(bf);
35275 @@ -2138,10 +2225,119 @@ void ath_tx_tasklet(struct ath_softc *sc
35276 }
35277 }
35278
35279 +void ath_tx_edma_tasklet(struct ath_softc *sc)
35280 +{
35281 + struct ath_tx_status txs;
35282 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
35283 + struct ath_hw *ah = sc->sc_ah;
35284 + struct ath_txq *txq;
35285 + struct ath_buf *bf, *lastbf;
35286 + struct list_head bf_head;
35287 + int status;
35288 + int txok;
35289 +
35290 + for (;;) {
35291 + status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
35292 + if (status == -EINPROGRESS)
35293 + break;
35294 + if (status == -EIO) {
35295 + ath_print(common, ATH_DBG_XMIT,
35296 + "Error processing tx status\n");
35297 + break;
35298 + }
35299 +
35300 + /* Skip beacon completions */
35301 + if (txs.qid == sc->beacon.beaconq)
35302 + continue;
35303 +
35304 + txq = &sc->tx.txq[txs.qid];
35305 +
35306 + spin_lock_bh(&txq->axq_lock);
35307 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
35308 + spin_unlock_bh(&txq->axq_lock);
35309 + return;
35310 + }
35311 +
35312 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
35313 + struct ath_buf, list);
35314 + lastbf = bf->bf_lastbf;
35315 +
35316 + INIT_LIST_HEAD(&bf_head);
35317 + list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
35318 + &lastbf->list);
35319 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
35320 + txq->axq_depth--;
35321 + txq->axq_tx_inprogress = false;
35322 + spin_unlock_bh(&txq->axq_lock);
35323 +
35324 + txok = !(txs.ts_status & ATH9K_TXERR_MASK);
35325 +
35326 + if (!bf_isampdu(bf)) {
35327 + bf->bf_retries = txs.ts_longretry;
35328 + if (txs.ts_status & ATH9K_TXERR_XRETRY)
35329 + bf->bf_state.bf_type |= BUF_XRETRY;
35330 + ath_tx_rc_status(bf, &txs, 0, txok, true);
35331 + }
35332 +
35333 + if (bf_isampdu(bf))
35334 + ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
35335 + else
35336 + ath_tx_complete_buf(sc, bf, txq, &bf_head,
35337 + &txs, txok, 0);
35338 +
35339 + spin_lock_bh(&txq->axq_lock);
35340 + if (!list_empty(&txq->txq_fifo_pending)) {
35341 + INIT_LIST_HEAD(&bf_head);
35342 + bf = list_first_entry(&txq->txq_fifo_pending,
35343 + struct ath_buf, list);
35344 + list_cut_position(&bf_head, &txq->txq_fifo_pending,
35345 + &bf->bf_lastbf->list);
35346 + ath_tx_txqaddbuf(sc, txq, &bf_head);
35347 + } else if (sc->sc_flags & SC_OP_TXAGGR)
35348 + ath_txq_schedule(sc, txq);
35349 + spin_unlock_bh(&txq->axq_lock);
35350 + }
35351 +}
35352 +
35353 /*****************/
35354 /* Init, Cleanup */
35355 /*****************/
35356
35357 +static int ath_txstatus_setup(struct ath_softc *sc, int size)
35358 +{
35359 + struct ath_descdma *dd = &sc->txsdma;
35360 + u8 txs_len = sc->sc_ah->caps.txs_len;
35361 +
35362 + dd->dd_desc_len = size * txs_len;
35363 + dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
35364 + &dd->dd_desc_paddr, GFP_KERNEL);
35365 + if (!dd->dd_desc)
35366 + return -ENOMEM;
35367 +
35368 + return 0;
35369 +}
35370 +
35371 +static int ath_tx_edma_init(struct ath_softc *sc)
35372 +{
35373 + int err;
35374 +
35375 + err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
35376 + if (!err)
35377 + ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
35378 + sc->txsdma.dd_desc_paddr,
35379 + ATH_TXSTATUS_RING_SIZE);
35380 +
35381 + return err;
35382 +}
35383 +
35384 +static void ath_tx_edma_cleanup(struct ath_softc *sc)
35385 +{
35386 + struct ath_descdma *dd = &sc->txsdma;
35387 +
35388 + dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
35389 + dd->dd_desc_paddr);
35390 +}
35391 +
35392 int ath_tx_init(struct ath_softc *sc, int nbufs)
35393 {
35394 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
35395 @@ -2150,7 +2346,7 @@ int ath_tx_init(struct ath_softc *sc, in
35396 spin_lock_init(&sc->tx.txbuflock);
35397
35398 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
35399 - "tx", nbufs, 1);
35400 + "tx", nbufs, 1, 1);
35401 if (error != 0) {
35402 ath_print(common, ATH_DBG_FATAL,
35403 "Failed to allocate tx descriptors: %d\n", error);
35404 @@ -2158,7 +2354,7 @@ int ath_tx_init(struct ath_softc *sc, in
35405 }
35406
35407 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
35408 - "beacon", ATH_BCBUF, 1);
35409 + "beacon", ATH_BCBUF, 1, 1);
35410 if (error != 0) {
35411 ath_print(common, ATH_DBG_FATAL,
35412 "Failed to allocate beacon descriptors: %d\n", error);
35413 @@ -2167,6 +2363,12 @@ int ath_tx_init(struct ath_softc *sc, in
35414
35415 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
35416
35417 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
35418 + error = ath_tx_edma_init(sc);
35419 + if (error)
35420 + goto err;
35421 + }
35422 +
35423 err:
35424 if (error != 0)
35425 ath_tx_cleanup(sc);
35426 @@ -2181,6 +2383,9 @@ void ath_tx_cleanup(struct ath_softc *sc
35427
35428 if (sc->tx.txdma.dd_desc_len != 0)
35429 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
35430 +
35431 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
35432 + ath_tx_edma_cleanup(sc);
35433 }
35434
35435 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
35436 --- a/include/net/mac80211.h
35437 +++ b/include/net/mac80211.h
35438 @@ -274,6 +274,7 @@ struct ieee80211_bss_conf {
35439 * @IEEE80211_TX_INTFL_NL80211_FRAME_TX: Frame was requested through nl80211
35440 * MLME command (internal to mac80211 to figure out whether to send TX
35441 * status to user space)
35442 + * @IEEE80211_TX_CTL_LDPC: tells the driver to use LDPC for this frame
35443 */
35444 enum mac80211_tx_control_flags {
35445 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
35446 @@ -297,6 +298,7 @@ enum mac80211_tx_control_flags {
35447 IEEE80211_TX_INTFL_RETRANSMISSION = BIT(19),
35448 IEEE80211_TX_INTFL_HAS_RADIOTAP = BIT(20),
35449 IEEE80211_TX_INTFL_NL80211_FRAME_TX = BIT(21),
35450 + IEEE80211_TX_CTL_LDPC = BIT(22),
35451 };
35452
35453 /**
Personal OpenWRT clone
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