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[xburst] sound jz4740_pcm: Set dma channel to NULL after it has been freed,
[openwrt.git] / target / linux / coldfire / patches / 019-m5445x_spi.patch
1 From bc755a3b8859e7307a8b10f39ca4cb6401c51987 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Tue, 27 Nov 2007 14:39:37 -0700
4 Subject: [PATCH] Add M5445x SPI support.
5
6 LTIBName: m5445x-spi
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 ---
9 arch/m68k/configs/m54455evb_defconfig | 24 +-
10 drivers/spi/Kconfig | 36 +
11 drivers/spi/Makefile | 4 +
12 drivers/spi/coldfire_edma.c | 358 ++++++++
13 drivers/spi/spi-m5445x.c | 156 ++++
14 drivers/spi/spi_coldfire.c | 1552 +++++++++++++++++++++++++++++++++
15 drivers/spi/ssi_audio.c | 906 +++++++++++++++++++
16 include/asm-m68k/coldfire_edma.h | 101 ++-
17 include/linux/spi/mcfqspi.h | 80 ++
18 9 files changed, 3196 insertions(+), 21 deletions(-)
19 create mode 100644 drivers/spi/coldfire_edma.c
20 create mode 100644 drivers/spi/spi-m5445x.c
21 create mode 100644 drivers/spi/spi_coldfire.c
22 create mode 100644 drivers/spi/ssi_audio.c
23 create mode 100644 include/linux/spi/mcfqspi.h
24
25 --- a/arch/m68k/configs/m54455evb_defconfig
26 +++ b/arch/m68k/configs/m54455evb_defconfig
27 @@ -321,6 +321,8 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=1
28 #
29 # Self-contained MTD device drivers
30 #
31 +# CONFIG_MTD_DATAFLASH is not set
32 +# CONFIG_MTD_M25P80 is not set
33 # CONFIG_MTD_SLRAM is not set
34 # CONFIG_MTD_PHRAM is not set
35 # CONFIG_MTD_MTDRAM is not set
36 @@ -497,8 +499,26 @@ CONFIG_UNIX98_PTYS=y
37 #
38 # SPI support
39 #
40 -# CONFIG_SPI is not set
41 -# CONFIG_SPI_MASTER is not set
42 +CONFIG_SPI=y
43 +# CONFIG_SPI_DEBUG is not set
44 +CONFIG_COLDFIRE_EDMA=y
45 +CONFIG_SPI_MASTER=y
46 +
47 +#
48 +# SPI Master Controller Drivers
49 +#
50 +# CONFIG_SPI_BITBANG is not set
51 +CONFIG_SPI_COLDFIRE=y
52 +CONFIG_SPI_COLDFIRE_DSPI_EDMA=y
53 +
54 +#
55 +# SPI Protocol Masters
56 +#
57 +# CONFIG_SPI_AT25 is not set
58 +# CONFIG_SPI_SPIDEV is not set
59 +# CONFIG_SPI_TLE62X0 is not set
60 +CONFIG_SPI_COLDFIRE_SSI_AUDIO=y
61 +# CONFIG_SSIAUDIO_USE_EDMA is not set
62 # CONFIG_W1 is not set
63 # CONFIG_POWER_SUPPLY is not set
64 # CONFIG_HWMON is not set
65 --- a/drivers/spi/Kconfig
66 +++ b/drivers/spi/Kconfig
67 @@ -35,6 +35,15 @@ config SPI_DEBUG
68 Say "yes" to enable debug messaging (like dev_dbg and pr_debug),
69 sysfs, and debugfs support in SPI controller and protocol drivers.
70
71 +config COLDFIRE_EDMA
72 + tristate "Coldfire eDMA"
73 + depends on COLDFIRE && EXPERIMENTAL
74 + help
75 + Support for Coldfire eDMA controller. Required for example
76 + by SSI audio device driver.
77 +
78 +
79 +
80 #
81 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
82 #
83 @@ -113,6 +122,21 @@ config SPI_GPIO
84
85 If unsure, say N.
86
87 +config SPI_COLDFIRE
88 + tristate "Coldfire QSPI/DSPI SPI Master"
89 + depends on SPI_MASTER && COLDFIRE && EXPERIMENTAL
90 + help
91 + SPI driver for Freescale Coldfire QSPI module in master mode.
92 + Tested with the 5282 processor, but should also work with other
93 + Coldfire variants.
94 +
95 +config SPI_COLDFIRE_DSPI_EDMA
96 + boolean "Coldfire DSPI master driver uses eDMA"
97 + depends on SPI_MASTER && COLDFIRE && SPI_COLDFIRE && EXPERIMENTAL && COLDFIRE_EDMA
98 + default n
99 + help
100 + Say "yes" if you want DSPI master driver to use eDMA for transfers.
101 +
102 config SPI_IMX
103 tristate "Freescale iMX SPI controller"
104 depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL
105 @@ -255,6 +279,18 @@ config SPI_TLE62X0
106 #
107 # Add new SPI protocol masters in alphabetical order above this line
108 #
109 +config SPI_COLDFIRE_SSI_AUDIO
110 + tristate "Coldfire SSI AUDIO"
111 + depends on SPI_MASTER && SPI_COLDFIRE && EXPERIMENTAL
112 + help
113 + SSI audio device driver
114 +
115 +config SSIAUDIO_USE_EDMA
116 + boolean "Coldfire DSPI master driver uses eDMA"
117 + default y
118 + depends on EXPERIMENTAL && COLDFIRE_EDMA && SPI_COLDFIRE_SSI_AUDIO
119 + help
120 + Say "yes" if you want SSI audio driver to use eDMA for SSI transfers.
121
122 # (slave support would go here)
123
124 --- a/drivers/spi/Makefile
125 +++ b/drivers/spi/Makefile
126 @@ -6,6 +6,8 @@ ifeq ($(CONFIG_SPI_DEBUG),y)
127 EXTRA_CFLAGS += -DDEBUG
128 endif
129
130 +obj-$(CONFIG_COLDFIRE_EDMA) += coldfire_edma.o
131 +
132 # small core, mostly translating board-specific
133 # config declarations into driver model code
134 obj-$(CONFIG_SPI_MASTER) += spi.o
135 @@ -16,6 +18,7 @@ obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.
136 obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
137 obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
138 obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
139 +obj-$(CONFIG_SPI_COLDFIRE) += spi_coldfire.o spi-m5445x.o
140 obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
141 obj-$(CONFIG_SPI_IMX) += spi_imx.o
142 obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
143 @@ -35,6 +38,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
144 obj-$(CONFIG_SPI_AT25) += at25.o
145 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
146 obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
147 +obj-$(CONFIG_SPI_COLDFIRE_SSI_AUDIO) += ssi_audio.o
148 # ... add above this line ...
149
150 # SPI slave controller drivers (upstream link)
151 --- /dev/null
152 +++ b/drivers/spi/coldfire_edma.c
153 @@ -0,0 +1,358 @@
154 +/*
155 + *
156 + * coldfire_edma.c - eDMA driver for Coldfire MCF5445x
157 + *
158 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
159 + *
160 + * Copyright Freescale Semiconductor, Inc. 2007
161 + *
162 + * This program is free software; you can redistribute it and/or modify it
163 + * under the terms of the GNU General Public License as published by the
164 + * Free Software Foundation; either version 2 of the License, or (at your
165 + * option) any later version.
166 + */
167 +
168 +#include <linux/init.h>
169 +#include <linux/module.h>
170 +#include <asm/virtconvert.h>
171 +#include <asm/coldfire.h>
172 +#include <linux/fs.h>
173 +#include <linux/cdev.h>
174 +#include <linux/seq_file.h>
175 +#include <linux/proc_fs.h>
176 +#include <asm/mcf5445x_edma.h>
177 +#include <asm/mcf5445x_intc.h>
178 +#include <asm/coldfire_edma.h>
179 +
180 +
181 +/* callback handler data for each TCD */
182 +struct edma_isr_record {
183 + edma_irq_handler irq_handler; /* interrupt handler */
184 + edma_error_handler error_handler; /* error interrupt handler */
185 + void* dev; /* device used for the channel */
186 + int allocated; /* busy flag */
187 + spinlock_t *lock; /* spin lock (if needs to be locked in interrupt) */
188 + const char* device_id; /* device id string, used in proc file system */
189 +};
190 +
191 +/* device structure */
192 +struct coldfire_edma_dev {
193 + struct cdev cdev; /* character device */
194 + struct edma_isr_record dma_interrupt_handlers[EDMA_CHANNELS]; /* channel handlers */
195 +};
196 +
197 +/* allocated major device number */
198 +static int coldfire_dma_major;
199 +/* device driver structure */
200 +static struct coldfire_edma_dev* devp = NULL;
201 +
202 +/* device driver file operations */
203 +struct file_operations coldfire_edma_fops = {
204 + .owner = THIS_MODULE,
205 +};
206 +
207 +/* eDMA channel interrupt handler */
208 +static int dmaisr(int irq, void *dev_id)
209 +{
210 + int channel = irq - EDMA_INT_CONTROLLER_BASE - EDMA_INT_CHANNEL_BASE;
211 + int result = IRQ_HANDLED;
212 +
213 + if (devp!=NULL && devp->dma_interrupt_handlers[channel].lock) {
214 + spin_lock(devp->dma_interrupt_handlers[channel].lock);
215 + }
216 +
217 + if (devp!=NULL && devp->dma_interrupt_handlers[channel].irq_handler) {
218 + result = devp->dma_interrupt_handlers[channel].irq_handler(channel,
219 + devp->dma_interrupt_handlers[channel].dev);
220 + } else {
221 + confirm_edma_interrupt_handled(channel);
222 + printk(EDMA_DRIVER_NAME ": No handler for DMA channel %d\n", channel);
223 + }
224 +
225 + if (devp!=NULL && devp->dma_interrupt_handlers[channel].lock) {
226 + spin_unlock(devp->dma_interrupt_handlers[channel].lock);
227 + }
228 +
229 + return result;
230 +}
231 +
232 +/* eDMA error interrupt handler */
233 +static int dma_error_isr(int irq, void* dev_id)
234 +{
235 + u16 err;
236 + int i;
237 +
238 + err = MCF_EDMA_ERR;
239 + for (i=0;i<EDMA_CHANNELS;i++) {
240 + if (err & (1<<i)) {
241 + if (devp!=NULL && devp->dma_interrupt_handlers[i].error_handler) {
242 + devp->dma_interrupt_handlers[i].error_handler(i, devp->dma_interrupt_handlers[i].dev);
243 + } else {
244 + printk(KERN_WARNING EDMA_DRIVER_NAME ": DMA error on channel %d\n", i);
245 + }
246 + }
247 + }
248 +
249 + MCF_EDMA_CERR = MCF_EDMA_CERR_CAER;
250 + return IRQ_HANDLED;
251 +}
252 +
253 +/* sets channel parameters */
254 +void set_edma_params(int channel, u32 source, u32 dest,
255 + u32 attr, u32 soff, u32 nbytes, u32 slast,
256 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
257 + int major_int, int disable_req)
258 +{
259 +
260 + if (channel<0 || channel>EDMA_CHANNELS)
261 + return;
262 +
263 + MCF_EDMA_TCD_SADDR(channel) = source;
264 + MCF_EDMA_TCD_DADDR(channel) = dest;
265 + MCF_EDMA_TCD_ATTR(channel) = attr;
266 + MCF_EDMA_TCD_SOFF(channel) = MCF_EDMA_TCD_SOFF_SOFF(soff);
267 + MCF_EDMA_TCD_NBYTES(channel) = MCF_EDMA_TCD_NBYTES_NBYTES(nbytes);
268 + MCF_EDMA_TCD_SLAST(channel) = MCF_EDMA_TCD_SLAST_SLAST(slast);
269 + MCF_EDMA_TCD_CITER(channel) = MCF_EDMA_TCD_CITER_CITER(citer);
270 + MCF_EDMA_TCD_BITER(channel)=MCF_EDMA_TCD_BITER_BITER(biter);
271 + MCF_EDMA_TCD_DOFF(channel) = MCF_EDMA_TCD_DOFF_DOFF(doff);
272 + MCF_EDMA_TCD_DLAST_SGA(channel) = MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga);
273 + /* interrupt at the end of major loop */
274 + if (major_int) {
275 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_INT_MAJOR;
276 + } else {
277 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_INT_MAJOR;
278 + }
279 + /* disable request at the end of major loop of transfer or not*/
280 + if (disable_req) {
281 + MCF_EDMA_TCD_CSR(channel) |= MCF_EDMA_TCD_CSR_D_REQ;
282 + } else {
283 + MCF_EDMA_TCD_CSR(channel) &= ~MCF_EDMA_TCD_CSR_D_REQ;
284 + }
285 +
286 +}
287 +EXPORT_SYMBOL(set_edma_params);
288 +
289 +/* init eDMA controller */
290 +void init_edma(void)
291 +{
292 + MCF_EDMA_CR = 0;
293 +}
294 +EXPORT_SYMBOL(init_edma);
295 +
296 +/* request eDMA channel */
297 +int request_edma_channel(int channel,
298 + edma_irq_handler handler,
299 + edma_error_handler error_handler,
300 + void* dev,
301 + spinlock_t *lock,
302 + const char* device_id )
303 +{
304 + if (devp!=NULL && channel>=0 && channel<=EDMA_CHANNELS) {
305 + if (devp->dma_interrupt_handlers[channel].allocated) {
306 + return -EBUSY;
307 + }
308 + devp->dma_interrupt_handlers[channel].allocated = 1;
309 + devp->dma_interrupt_handlers[channel].irq_handler = handler;
310 + devp->dma_interrupt_handlers[channel].error_handler = error_handler;
311 + devp->dma_interrupt_handlers[channel].dev = dev;
312 + devp->dma_interrupt_handlers[channel].lock = lock;
313 + devp->dma_interrupt_handlers[channel].device_id = device_id;
314 + return 0;
315 + }
316 + return -EINVAL;
317 +}
318 +EXPORT_SYMBOL(request_edma_channel);
319 +
320 +/* free eDMA channel */
321 +int free_edma_channel(int channel, void* dev)
322 +{
323 + if (devp!=NULL && channel>=0 && channel<=EDMA_CHANNELS) {
324 + if (devp->dma_interrupt_handlers[channel].allocated) {
325 + if (devp->dma_interrupt_handlers[channel].dev != dev) {
326 + return -EBUSY;
327 + }
328 + devp->dma_interrupt_handlers[channel].allocated = 0;
329 + devp->dma_interrupt_handlers[channel].dev = NULL;
330 + devp->dma_interrupt_handlers[channel].irq_handler = NULL;
331 + devp->dma_interrupt_handlers[channel].error_handler = NULL;
332 + devp->dma_interrupt_handlers[channel].lock = NULL;
333 + }
334 + return 0;
335 + }
336 + return -EINVAL;
337 +}
338 +EXPORT_SYMBOL(free_edma_channel);
339 +
340 +/* clean-up device driver allocated resources */
341 +static void coldfire_edma_cleanup(void)
342 +{
343 + dev_t devno;
344 + int i;
345 +
346 + /* free interrupts/memory */
347 + if (devp) {
348 + for (i=0;i<EDMA_CHANNELS;i++)
349 + {
350 + MCF_INTC0_SIMR = EDMA_INT_CHANNEL_BASE+i;
351 + free_irq(EDMA_INT_CHANNEL_BASE+EDMA_INT_CONTROLLER_BASE+i, devp);
352 + }
353 + MCF_INTC0_SIMR = EDMA_INT_CHANNEL_BASE+EDMA_CHANNELS;
354 + free_irq(EDMA_INT_CHANNEL_BASE+EDMA_INT_CONTROLLER_BASE+EDMA_CHANNELS, devp);
355 + cdev_del(&devp->cdev);
356 + kfree(devp);
357 + }
358 +
359 + /* unregister character device */
360 + devno = MKDEV(coldfire_dma_major, 0);
361 + unregister_chrdev_region(devno, 1);
362 +}
363 +
364 +#ifdef CONFIG_PROC_FS
365 +/* proc file system support */
366 +
367 +#define FREE_CHANNEL "free"
368 +#define DEVICE_UNKNOWN "device unknown"
369 +
370 +static int proc_edma_show(struct seq_file *m, void *v)
371 +{
372 + int i;
373 +
374 + if (devp==NULL) return 0;
375 +
376 + for (i = 0 ; i < EDMA_CHANNELS ; i++) {
377 + if (devp->dma_interrupt_handlers[i].allocated) {
378 + if (devp->dma_interrupt_handlers[i].device_id)
379 + seq_printf(m, "%2d: %s\n", i, devp->dma_interrupt_handlers[i].device_id);
380 + else
381 + seq_printf(m, "%2d: %s\n", i, DEVICE_UNKNOWN);
382 + } else {
383 + seq_printf(m, "%2d: %s\n", i, FREE_CHANNEL);
384 + }
385 + }
386 + return 0;
387 +}
388 +
389 +static int proc_edma_open(struct inode *inode, struct file *file)
390 +{
391 + return single_open(file, proc_edma_show, NULL);
392 +}
393 +
394 +static const struct file_operations proc_edma_operations = {
395 + .open = proc_edma_open,
396 + .read = seq_read,
397 + .llseek = seq_lseek,
398 + .release = single_release,
399 +};
400 +
401 +static int __init proc_edma_init(void)
402 +{
403 + struct proc_dir_entry *e;
404 +
405 + e = create_proc_entry("edma", 0, NULL);
406 + if (e)
407 + e->proc_fops = &proc_edma_operations;
408 +
409 + return 0;
410 +}
411 +
412 +#endif
413 +
414 +/* initializes device driver */
415 +static int __init coldfire_edma_init(void)
416 +{
417 + dev_t dev;
418 + int result;
419 + int i;
420 +
421 + /* allocate free major number */
422 + result = alloc_chrdev_region(&dev, DMA_DEV_MINOR, 1, EDMA_DRIVER_NAME);
423 + if (result<0) {
424 + printk(KERN_WARNING EDMA_DRIVER_NAME": can't get major %d\n", result);
425 + return result;
426 + }
427 + coldfire_dma_major = MAJOR(dev);
428 +
429 + /* allocate device driver structure */
430 + devp = kmalloc(sizeof(struct coldfire_edma_dev), GFP_KERNEL);
431 + if (!devp) {
432 + result = -ENOMEM;
433 + goto fail;
434 + }
435 +
436 + /* init handlers (no handlers for beggining) */
437 + for (i=0;i<EDMA_CHANNELS;i++) {
438 + devp->dma_interrupt_handlers[i].irq_handler = NULL;
439 + devp->dma_interrupt_handlers[i].error_handler = NULL;
440 + devp->dma_interrupt_handlers[i].dev = NULL;
441 + devp->dma_interrupt_handlers[i].allocated = 0;
442 + devp->dma_interrupt_handlers[i].lock = NULL;
443 + devp->dma_interrupt_handlers[i].device_id = NULL;
444 + }
445 +
446 + /* register char device */
447 + cdev_init(&devp->cdev, &coldfire_edma_fops);
448 + devp->cdev.owner = THIS_MODULE;
449 + devp->cdev.ops = &coldfire_edma_fops;
450 + result = cdev_add(&devp->cdev, dev, 1);
451 + if (result) {
452 + printk(KERN_NOTICE EDMA_DRIVER_NAME": Error %d adding coldfire-dma device\n", result);
453 + result = -ENODEV;
454 + goto fail;
455 + }
456 +
457 + /* request/enable irq for each eDMA channel */
458 + for (i=0;i<EDMA_CHANNELS;i++)
459 + {
460 + result = request_irq(EDMA_INT_CHANNEL_BASE+EDMA_INT_CONTROLLER_BASE+i,
461 + dmaisr, SA_INTERRUPT, EDMA_DRIVER_NAME, devp);
462 + if (result) {
463 + printk(KERN_WARNING EDMA_DRIVER_NAME": Cannot request irq %d\n",
464 + EDMA_INT_CHANNEL_BASE+EDMA_INT_CONTROLLER_BASE+i);
465 + result = -EBUSY;
466 + goto fail;
467 + }
468 +
469 + MCF_INTC0_ICR(EDMA_INT_CHANNEL_BASE+i) = EDMA_IRQ_LEVEL;
470 + MCF_INTC0_CIMR = EDMA_INT_CHANNEL_BASE+i;
471 +
472 + }
473 +
474 + /* request error interrupt */
475 + result = request_irq(EDMA_INT_CHANNEL_BASE + EDMA_INT_CONTROLLER_BASE + EDMA_CHANNELS,
476 + dma_error_isr, SA_INTERRUPT, EDMA_DRIVER_NAME, devp);
477 + if (result) {
478 + printk(KERN_WARNING EDMA_DRIVER_NAME": Cannot request irq %d\n",
479 + EDMA_INT_CHANNEL_BASE+EDMA_INT_CONTROLLER_BASE+EDMA_CHANNELS);
480 + result = -EBUSY;
481 + goto fail;
482 + }
483 +
484 + /* enable error interrupt in interrupt controller */
485 + MCF_INTC0_ICR(EDMA_INT_CHANNEL_BASE+EDMA_CHANNELS) = EDMA_IRQ_LEVEL;
486 + MCF_INTC0_CIMR = EDMA_INT_CHANNEL_BASE+EDMA_CHANNELS;
487 +
488 +#ifdef CONFIG_PROC_FS
489 + proc_edma_init();
490 +#endif
491 +
492 + printk(EDMA_DRIVER_NAME ": initialized successfully\n");
493 +
494 + return 0;
495 +fail:
496 + coldfire_edma_cleanup();
497 + return result;
498 +
499 +}
500 +
501 +static void __exit coldfire_edma_exit(void)
502 +{
503 + coldfire_edma_cleanup();
504 +}
505 +
506 +module_init(coldfire_edma_init);
507 +module_exit(coldfire_edma_exit);
508 +
509 +MODULE_LICENSE("GPL");
510 +MODULE_AUTHOR("Yaroslav Vinogradov, Freescale Inc.");
511 +MODULE_DESCRIPTION("eDMA library for Coldfire 5445x");
512 --- /dev/null
513 +++ b/drivers/spi/spi-m5445x.c
514 @@ -0,0 +1,156 @@
515 +/***************************************************************************/
516 +/*
517 + * linux/arch/m68k/coldfire/spi-m5445x.c
518 + *
519 + * Sub-architcture dependant initialization code for the Freescale
520 + * 5445x SPI module
521 + *
522 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
523 + * Copyright Freescale Semiconductor, Inc 2007
524 + *
525 + * This program is free software; you can redistribute it and/or modify
526 + * it under the terms of the GNU General Public License as published by
527 + * the Free Software Foundation; either version 2 of the License, or
528 + * (at your option) any later version.
529 + */
530 +/***************************************************************************/
531 +
532 +
533 +#include <linux/kernel.h>
534 +#include <linux/sched.h>
535 +#include <linux/param.h>
536 +#include <linux/init.h>
537 +#include <linux/interrupt.h>
538 +#include <linux/device.h>
539 +#include <linux/platform_device.h>
540 +#include <linux/spi/spi.h>
541 +
542 +#include <asm/dma.h>
543 +#include <asm/traps.h>
544 +#include <asm/machdep.h>
545 +#include <asm/coldfire.h>
546 +#include <asm/mcfsim.h>
547 +#include <asm/mcfqspi.h>
548 +#include <asm/mcf5445x_gpio.h>
549 +
550 +#define SPI_NUM_CHIPSELECTS 0x10
551 +#define SPI_PAR_VAL (0 | MCF_GPIO_PAR_DSPI_PCS5_PCS5 | MCF_GPIO_PAR_DSPI_PCS2_PCS2 \
552 + | MCF_GPIO_PAR_DSPI_PCS1_PCS1 | MCF_GPIO_PAR_DSPI_PCS0_PCS0 | MCF_GPIO_PAR_DSPI_SIN_SIN \
553 + | MCF_GPIO_PAR_DSPI_SOUT_SOUT | MCF_GPIO_PAR_DSPI_SCK_SCK)
554 +
555 +#define MCF5445x_DSPI_IRQ_SOURCE (31)
556 +#define MCF5445x_DSPI_IRQ_VECTOR (64 + MCF5445x_DSPI_IRQ_SOURCE)
557 +
558 +#define MCF5445x_DSPI_PAR (0xFC0A4063)
559 +#define MCF5445x_DSPI_MCR (0xFC05C000)
560 +#define MCF5445x_INTC0_ICR (0xFC048040)
561 +#define MCF5445x_INTC0_IMRL (0xFC04800C)
562 +
563 +
564 +#define M5445x_AUDIO_IRQ_SOURCE 49
565 +#define M5445x_AUDIO_IRQ_VECTOR (128+M5445x_AUDIO_IRQ_SOURCE)
566 +#define M5445x_AUDIO_IRQ_LEVEL 4
567 +
568 +void coldfire_qspi_cs_control(u8 cs, u8 command)
569 +{
570 +}
571 +
572 +#if defined(CONFIG_SPI_COLDFIRE_SSI_AUDIO)
573 +static struct coldfire_spi_chip ssi_audio_chip_info = {
574 + .mode = SPI_MODE_0,
575 + .bits_per_word = 16,
576 + .del_cs_to_clk = 16,
577 + .del_after_trans = 16,
578 + .void_write_data = 0
579 +};
580 +
581 +#endif
582 +
583 +static struct spi_board_info spi_board_info[] = {
584 +
585 +#if defined(CONFIG_SPI_COLDFIRE_SSI_AUDIO)
586 + {
587 + .modalias = "ssi_audio",
588 + .max_speed_hz = 300000,
589 + .bus_num = 1,
590 + .chip_select = 5,
591 + .irq = M5445x_AUDIO_IRQ_VECTOR,
592 + .platform_data = NULL,
593 + .controller_data = &ssi_audio_chip_info
594 + }
595 +#endif
596 +
597 +};
598 +
599 +static struct coldfire_spi_master coldfire_master_info = {
600 + .bus_num = 1,
601 + .num_chipselect = SPI_NUM_CHIPSELECTS,
602 + .irq_source = MCF5445x_DSPI_IRQ_SOURCE,
603 + .irq_vector = MCF5445x_DSPI_IRQ_VECTOR,
604 + .irq_mask = (0x01 << MCF5445x_DSPI_IRQ_SOURCE),
605 + .irq_lp = 0x2, /* Level */
606 + .par_val = SPI_PAR_VAL,
607 +// .par_val16 = SPI_PAR_VAL,
608 + .cs_control = coldfire_qspi_cs_control,
609 +};
610 +
611 +static struct resource coldfire_spi_resources[] = {
612 + [0] = {
613 + .name = "qspi-par",
614 + .start = MCF5445x_DSPI_PAR,
615 + .end = MCF5445x_DSPI_PAR,
616 + .flags = IORESOURCE_MEM
617 + },
618 +
619 + [1] = {
620 + .name = "qspi-module",
621 + .start = MCF5445x_DSPI_MCR,
622 + .end = MCF5445x_DSPI_MCR + 0xB8,
623 + .flags = IORESOURCE_MEM
624 + },
625 +
626 + [2] = {
627 + .name = "qspi-int-level",
628 + .start = MCF5445x_INTC0_ICR + MCF5445x_DSPI_IRQ_SOURCE,
629 + .end = MCF5445x_INTC0_ICR + MCF5445x_DSPI_IRQ_SOURCE,
630 + .flags = IORESOURCE_MEM
631 + },
632 +
633 + [3] = {
634 + .name = "qspi-int-mask",
635 + .start = MCF5445x_INTC0_IMRL,
636 + .end = MCF5445x_INTC0_IMRL,
637 + .flags = IORESOURCE_MEM
638 + }
639 +};
640 +
641 +static struct platform_device coldfire_spi = {
642 + .name = "spi_coldfire", //"coldfire-qspi",
643 + .id = -1,
644 + .resource = coldfire_spi_resources,
645 + .num_resources = ARRAY_SIZE(coldfire_spi_resources),
646 + .dev = {
647 + .platform_data = &coldfire_master_info,
648 + }
649 +};
650 +
651 +static int __init spi_dev_init(void)
652 +{
653 + int retval = 0;
654 +
655 + retval = platform_device_register(&coldfire_spi);
656 +
657 + if (retval < 0) {
658 + printk(KERN_ERR "SPI-m5445x: platform_device_register failed with code=%d\n", retval);
659 + goto out;
660 + }
661 +
662 + if (ARRAY_SIZE(spi_board_info))
663 + retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
664 +
665 +
666 +out:
667 + return retval;
668 +}
669 +
670 +arch_initcall(spi_dev_init);
671 --- /dev/null
672 +++ b/drivers/spi/spi_coldfire.c
673 @@ -0,0 +1,1552 @@
674 +/****************************************************************************/
675 +
676 +/*
677 + * spi_coldfire.c - Master QSPI/DSPI controller for the ColdFire processors
678 + *
679 + * (C) Copyright 2005, Intec Automation,
680 + * Mike Lavender (mike@steroidmicros)
681 + *
682 + * (C) Copyright 2007, Freescale Inc,
683 + * Yaroslav Vinogradov (yaroslav.vinogradov@freescale.com)
684 + *
685 +
686 + This program is free software; you can redistribute it and/or modify
687 + it under the terms of the GNU General Public License as published by
688 + the Free Software Foundation; either version 2 of the License, or
689 + (at your option) any later version.
690 +
691 + This program is distributed in the hope that it will be useful,
692 + but WITHOUT ANY WARRANTY; without even the implied warranty of
693 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
694 + GNU General Public License for more details.
695 +
696 + You should have received a copy of the GNU General Public License
697 + along with this program; if not, write to the Free Software
698 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
699 +/* ------------------------------------------------------------------------- */
700 +
701 +
702 +/****************************************************************************/
703 +
704 +/*
705 + * Includes
706 + */
707 +
708 +#include <linux/autoconf.h>
709 +#include <linux/init.h>
710 +#include <linux/module.h>
711 +#include <linux/device.h>
712 +#include <linux/interrupt.h>
713 +#include <linux/platform_device.h>
714 +#include <linux/spi/spi.h>
715 +#include <linux/workqueue.h>
716 +#include <linux/delay.h>
717 +
718 +#include <asm/delay.h>
719 +#include <asm/mcfsim.h>
720 +#include <asm/mcfqspi.h>
721 +#include <asm/coldfire.h>
722 +#include <asm/virtconvert.h>
723 +
724 +#if defined(CONFIG_M54455)
725 + #define SPI_DSPI
726 + #if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
727 + #define SPI_DSPI_EDMA
728 + #ifdef CONFIG_MMU
729 + #define SPI_USE_MMU
730 + #endif
731 + #endif
732 +#endif
733 +
734 +#ifdef SPI_DSPI
735 +#include <asm/mcf5445x_dspi.h>
736 +
737 +
738 +#endif
739 +
740 +#if defined(SPI_DSPI_EDMA)
741 +
742 +/* edma buffer size in transfer units (32bits) */
743 +#define EDMA_BUFFER_SIZE (PAGE_SIZE/4)
744 +#define EDMA_BUFSIZE_KMALLOC (EDMA_BUFFER_SIZE*4)
745 +
746 +#define DSPI_DMA_RX_TCD 12
747 +#define DSPI_DMA_TX_TCD 13
748 +
749 +
750 +#include <asm/coldfire_edma.h>
751 +#include <asm/mcf5445x_edma.h>
752 +#endif
753 +
754 +
755 +MODULE_AUTHOR("Mike Lavender");
756 +MODULE_DESCRIPTION("ColdFire QSPI Contoller");
757 +MODULE_LICENSE("GPL");
758 +
759 +#define DRIVER_NAME "Coldfire QSPI/DSPI"
760 +
761 +/****************************************************************************/
762 +
763 +/*
764 + * Local constants and macros
765 + */
766 +
767 +#define QSPI_RAM_SIZE 0x10 /* 16 word table */
768 +
769 +#define QSPI_TRANSMIT_RAM 0x00
770 +#define QSPI_RECEIVE_RAM 0x10
771 +#define QSPI_COMMAND_RAM 0x20
772 +
773 +#define QSPI_COMMAND 0x7000 /* 15: X = Continuous CS
774 + * 14: 1 = Get BITSE from QMR[BITS]
775 + * 13: 1 = Get DT from QDLYR[DTL]
776 + * 12: 1 = Get DSK from QDLYR[QCD]
777 + * 8-11: XXXX = next 4 bytes for CS
778 + * 0-7: 0000 0000 Reserved
779 + */
780 +
781 +#define QIR_WCEF 0x0008 /* write collison */
782 +#define QIR_ABRT 0x0004 /* abort */
783 +#define QIR_SPIF 0x0001 /* finished */
784 +
785 +#define QIR_WCEFE 0x0800
786 +#define QIR_ABRTE 0x0400
787 +#define QIR_SPIFE 0x0100
788 +
789 +#define QIR_WCEFB 0x8000
790 +#define QIR_ABRTB 0x4000
791 +#define QIR_ABRTL 0x1000
792 +
793 +#define QMR_BITS 0x3C00
794 +#define QMR_BITS_8 0x2000
795 +
796 +#define QCR_CONT 0x8000
797 +
798 +#define QDLYR_SPE 0x8000
799 +
800 +#define QWR_ENDQP_MASK 0x0F00
801 +#define QWR_CSIV 0x1000 /* 1 = active low chip selects */
802 +
803 +
804 +#define START_STATE ((void*)0)
805 +#define RUNNING_STATE ((void*)1)
806 +#define DONE_STATE ((void*)2)
807 +#define ERROR_STATE ((void*)-1)
808 +
809 +#define QUEUE_RUNNING 0
810 +#define QUEUE_STOPPED 1
811 +
812 +/****************************************************************************/
813 +
814 +/*
815 + * Local Data Structures
816 + */
817 +
818 +struct transfer_state {
819 + u32 index;
820 + u32 len;
821 + void *tx;
822 + void *tx_end;
823 + void *rx;
824 + void *rx_end;
825 + char flags;
826 +#define TRAN_STATE_RX_VOID 0x01
827 +#define TRAN_STATE_TX_VOID 0x02
828 +#define TRAN_STATE_WORD_ODD_NUM 0x04
829 + u8 cs;
830 + u16 void_write_data;
831 + unsigned cs_change:1;
832 +};
833 +
834 +typedef struct {
835 + unsigned master:1;
836 + unsigned dohie:1;
837 + unsigned bits:4;
838 + unsigned cpol:1;
839 + unsigned cpha:1;
840 + unsigned baud:8;
841 +} QMR;
842 +
843 +typedef struct {
844 + unsigned spe:1;
845 + unsigned qcd:7;
846 + unsigned dtl:8;
847 +} QDLYR;
848 +
849 +typedef struct {
850 + unsigned halt:1;
851 + unsigned wren:1;
852 + unsigned wrto:1;
853 + unsigned csiv:1;
854 + unsigned endqp:4;
855 + unsigned cptqp:4;
856 + unsigned newqp:4;
857 +} QWR;
858 +
859 +
860 +typedef struct {
861 + unsigned master:1;
862 + unsigned cont_scke:1;
863 + unsigned dconf:2;
864 + unsigned frz:1;
865 + unsigned mtfe:1;
866 + unsigned pcsse:1;
867 + unsigned rooe:1;
868 + unsigned pcsis:8;
869 + unsigned reserved15:1;
870 + unsigned mdis:1;
871 + unsigned dis_tx:1;
872 + unsigned dis_rxf:1;
873 + unsigned clr_tx:1;
874 + unsigned clr_rxf:1;
875 + unsigned smpl_pt:2;
876 + unsigned reserved71:7;
877 + unsigned halt:1;
878 +} DSPI_MCR;
879 +
880 +typedef struct {
881 + unsigned dbr:1;
882 + unsigned fmsz:4;
883 + unsigned cpol:1;
884 + unsigned cpha:1;
885 + unsigned lsbfe:1;
886 + unsigned pcssck:2;
887 + unsigned pasc:2;
888 + unsigned pdt:2;
889 + unsigned pbr:2;
890 + unsigned cssck:4;
891 + unsigned asc:4;
892 + unsigned dt:4;
893 + unsigned br:4;
894 +} DSPI_CTAR;
895 +
896 +struct chip_data {
897 +#if defined(SPI_DSPI)
898 + /* dspi data */
899 + union {
900 + u32 mcr_val;
901 + DSPI_MCR mcr;
902 + };
903 + union {
904 + u32 ctar_val;
905 + DSPI_CTAR ctar;
906 + };
907 +#else
908 + union {
909 + u16 qmr_val;
910 + QMR qmr;
911 + };
912 + union {
913 + u16 qdlyr_val;
914 + QDLYR qdlyr;
915 + };
916 + union {
917 + u16 qwr_val;
918 + QWR qwr;
919 + };
920 +#endif
921 +
922 + u16 void_write_data;
923 +};
924 +
925 +
926 +struct driver_data {
927 + /* Driver model hookup */
928 + struct platform_device *pdev;
929 +
930 + /* SPI framework hookup */
931 + struct spi_master *master;
932 +
933 + /* Driver message queue */
934 + struct workqueue_struct *workqueue;
935 + struct work_struct pump_messages;
936 + spinlock_t lock;
937 + struct list_head queue;
938 + int busy;
939 + int run;
940 +
941 + /* Message Transfer pump */
942 + struct tasklet_struct pump_transfers;
943 +
944 + /* Current message transfer state info */
945 + struct spi_message* cur_msg;
946 + struct spi_transfer* cur_transfer;
947 + struct chip_data *cur_chip;
948 + size_t len;
949 + void *tx;
950 + void *tx_end;
951 + void *rx;
952 + void *rx_end;
953 + char flags;
954 +#define TRAN_STATE_RX_VOID 0x01
955 +#define TRAN_STATE_TX_VOID 0x02
956 +#define TRAN_STATE_WORD_ODD_NUM 0x04
957 + u8 cs;
958 + u16 void_write_data;
959 + unsigned cs_change:1;
960 +
961 + u32 trans_cnt;
962 + u32 wce_cnt;
963 + u32 abrt_cnt;
964 +#if defined(SPI_DSPI)
965 + u32 *mcr; /* DSPI MCR register */
966 + u32 *ctar; /* DSPI CTAR register */
967 + u32 *dspi_dtfr; /* DSPI DTFR register */
968 + u32 *dspi_drfr; /* DSPI DRFR register */
969 + u32 *dspi_rser; /* DSPI RSER register */
970 + u32 *dspi_sr; /* DSPI status register */
971 + u8 dspi_ctas; /* DSPI CTAS value*/
972 +
973 +#if defined(SPI_DSPI_EDMA)
974 + void* edma_tx_buf;
975 + void* edma_rx_buf;
976 +#endif
977 +
978 +
979 +#else
980 + u16 *qmr; /* QSPI mode register */
981 + u16 *qdlyr; /* QSPI delay register */
982 + u16 *qwr; /* QSPI wrap register */
983 + u16 *qir; /* QSPI interrupt register */
984 + u16 *qar; /* QSPI address register */
985 + u16 *qdr; /* QSPI data register */
986 + u16 *qcr; /* QSPI command register */
987 +#endif
988 + u8 *par; /* Pin assignment register */
989 + u8 *int_icr; /* Interrupt level and priority register */
990 + u32 *int_mr; /* Interrupt mask register */
991 + void (*cs_control)(u8 cs, u8 command);
992 +};
993 +
994 +#define DSPI_CS(cs) ((1<<(cs))<<16)
995 +
996 +
997 +/****************************************************************************/
998 +
999 +/*
1000 + * SPI local functions
1001 + */
1002 +
1003 +//#define SPI_COLDFIRE_DEBUG
1004 +
1005 +static void *next_transfer(struct driver_data *drv_data)
1006 +{
1007 + struct spi_message *msg = drv_data->cur_msg;
1008 + struct spi_transfer *trans = drv_data->cur_transfer;
1009 +
1010 + /* Move to next transfer */
1011 + if (trans->transfer_list.next != &msg->transfers) {
1012 + drv_data->cur_transfer =
1013 + list_entry(trans->transfer_list.next,
1014 + struct spi_transfer,
1015 + transfer_list);
1016 + return RUNNING_STATE;
1017 + } else
1018 + return DONE_STATE;
1019 +}
1020 +
1021 +
1022 +#define DSPI_BITS MCF_DSPI_DCTAR_FMSZ(15)
1023 +#define DSPI_BITS_16 MCF_DSPI_DCTAR_FMSZ(15)
1024 +#define DSPI_BITS_8 MCF_DSPI_DCTAR_FMSZ(7)
1025 +#define DSPI_FIFO_SIZE 16
1026 +
1027 +static inline int is_word_transfer(struct driver_data *drv_data)
1028 +{
1029 +#if defined(SPI_DSPI)
1030 + return ((*drv_data->ctar & DSPI_BITS_16) == DSPI_BITS_8) ? 0 : 1;
1031 +#else
1032 + return ((*drv_data->qmr & QMR_BITS) == QMR_BITS_8) ? 0 : 1;
1033 +#endif
1034 +}
1035 +
1036 +static void inline set_8bit_transfer_mode(struct driver_data *drv_data)
1037 +{
1038 +#if defined(SPI_DSPI)
1039 + *drv_data->ctar |= (*drv_data->ctar & ~DSPI_BITS) | DSPI_BITS_8;
1040 +#else
1041 + *drv_data->qmr |= (*drv_data->qmr & ~QMR_BITS) | QMR_BITS_8;
1042 +#endif
1043 +}
1044 +
1045 +static void inline set_16bit_transfer_mode(struct driver_data *drv_data)
1046 +{
1047 +#if defined(SPI_DSPI)
1048 + *drv_data->ctar |= (*drv_data->ctar & ~DSPI_BITS) | DSPI_BITS_16;
1049 +#else
1050 + *drv_data->qmr |= (*drv_data->qmr & ~QMR_BITS);
1051 +#endif
1052 +}
1053 +
1054 +static int write(struct driver_data *drv_data)
1055 +{
1056 + int tx_count = 0;
1057 +#ifndef SPI_DSPI
1058 + int cmd_count = 0;
1059 +#endif
1060 + int tx_word;
1061 +
1062 +#if defined(SPI_DSPI)
1063 +
1064 +#if defined(SPI_DSPI_EDMA)
1065 + u32* edma_wr;
1066 +#endif
1067 +
1068 + u16 d16;
1069 + u8 d8;
1070 + u32 dspi_pushr;
1071 + int first = 1;
1072 +#endif
1073 +
1074 + tx_word = is_word_transfer(drv_data);
1075 +
1076 + // If we are in word mode, but only have a single byte to transfer
1077 + // then switch to byte mode temporarily. Will switch back at the
1078 + // end of the transfer.
1079 + if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
1080 + drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
1081 + set_8bit_transfer_mode(drv_data);
1082 + tx_word = 0;
1083 + }
1084 +
1085 +
1086 +#if defined(SPI_DSPI)
1087 +
1088 +#if defined(SPI_DSPI_EDMA)
1089 + edma_wr = (u32*)(drv_data->edma_tx_buf);
1090 +#endif
1091 +
1092 +
1093 +#if defined(SPI_DSPI_EDMA)
1094 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < EDMA_BUFFER_SIZE)) {
1095 +#else
1096 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < DSPI_FIFO_SIZE)) {
1097 +#endif
1098 + if (tx_word) {
1099 + if ((drv_data->tx_end - drv_data->tx) == 1)
1100 + break;
1101 + if (!(drv_data->flags & TRAN_STATE_TX_VOID)) {
1102 + d16 = *(u16 *)drv_data->tx;
1103 + } else {
1104 + d16 = drv_data->void_write_data;
1105 + }
1106 +
1107 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16)
1108 + | DSPI_CS(drv_data->cs)
1109 + | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas)
1110 + //| MCF_DSPI_DTFR_CONT
1111 + ;
1112 +
1113 + drv_data->tx += 2;
1114 +
1115 +#if defined(SPI_DSPI_EDMA)
1116 + if (drv_data->tx == drv_data->tx_end || tx_count==EDMA_BUFFER_SIZE-1) {
1117 +#else
1118 + if (drv_data->tx == drv_data->tx_end || tx_count==DSPI_FIFO_SIZE-1) {
1119 +#endif
1120 + // last transfer in queue
1121 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
1122 + if (drv_data->cs_change) {
1123 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
1124 + }
1125 + }
1126 +
1127 + if (first) {
1128 + first = 0;
1129 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; // clear counter
1130 + }
1131 +#if defined(SPI_DSPI_EDMA)
1132 + *edma_wr = dspi_pushr;
1133 + edma_wr++;
1134 +#else
1135 + *drv_data->dspi_dtfr = dspi_pushr;
1136 + //MCF_DSPI_DTFR = dspi_pushr;
1137 +#endif
1138 +
1139 +
1140 + } else {
1141 + if (!(drv_data->flags & TRAN_STATE_TX_VOID)) {
1142 + d8 = *(u8 *)drv_data->tx;
1143 + } else {
1144 + d8 = *(u8 *)&drv_data->void_write_data;
1145 + }
1146 +
1147 + dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8)
1148 + | DSPI_CS(drv_data->cs)
1149 + /* | MCF_DSPI_DTFR_PCS5 | */
1150 + | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas)
1151 + | MCF_DSPI_DTFR_CONT;
1152 +
1153 + drv_data->tx++;
1154 +
1155 + if (drv_data->tx == drv_data->tx_end || tx_count==DSPI_FIFO_SIZE-1) {
1156 + // last transfer in queue
1157 + dspi_pushr |= MCF_DSPI_DTFR_EOQ;
1158 + if (drv_data->cs_change) {
1159 + dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
1160 + }
1161 + }
1162 +
1163 + if (first) {
1164 + first = 0;
1165 + dspi_pushr |= MCF_DSPI_DTFR_CTCNT; // clear counter
1166 + }
1167 +
1168 +#if defined(SPI_DSPI_EDMA)
1169 + *edma_wr = dspi_pushr;
1170 + edma_wr++;
1171 +#else
1172 + *drv_data->dspi_dtfr = dspi_pushr;
1173 + //MCF_DSPI_DTFR = dspi_pushr;
1174 +#endif
1175 +
1176 + }
1177 + tx_count++;
1178 + }
1179 +
1180 +#if defined(SPI_DSPI_EDMA)
1181 +
1182 + if (tx_count>0) {
1183 +
1184 + // TODO: initiate eDMA transfer
1185 + set_edma_params(DSPI_DMA_TX_TCD,
1186 +#ifdef SPI_USE_MMU
1187 + virt_to_phys(drv_data->edma_tx_buf),
1188 +#else
1189 + drv_data->edma_tx_buf,
1190 +#endif
1191 + (u32)drv_data->dspi_dtfr,
1192 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
1193 + 4, // soff
1194 + 4, // nbytes
1195 + 0, // slast
1196 + tx_count, // citer
1197 + tx_count, // biter
1198 + 0, // doff
1199 + 0, // dlastsga
1200 + 0, // major_int
1201 + 1 // disable_req
1202 + );
1203 +
1204 + set_edma_params(DSPI_DMA_RX_TCD,
1205 + (u32)drv_data->dspi_drfr,
1206 +#ifdef SPI_USE_MMU
1207 + virt_to_phys(drv_data->edma_rx_buf),
1208 +#else
1209 + drv_data->edma_rx_buf,
1210 +#endif
1211 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
1212 + 0, // soff
1213 + 4, // nbytes
1214 + 0, // slast
1215 + tx_count, // citer
1216 + tx_count, // biter
1217 + 4, // doff
1218 + 0, // dlastsga
1219 + 0, // major_int
1220 + 1 // disable_req
1221 + );
1222 +
1223 +
1224 + start_edma_transfer(DSPI_DMA_TX_TCD); // transmit SPI data
1225 + start_edma_transfer(DSPI_DMA_RX_TCD); // receive SPI data
1226 + }
1227 +#endif
1228 +
1229 +#else
1230 +
1231 + *drv_data->qar = QSPI_TRANSMIT_RAM;
1232 + while ((drv_data->tx < drv_data->tx_end) && (tx_count < QSPI_RAM_SIZE)) {
1233 + if (tx_word) {
1234 + if ((drv_data->tx_end - drv_data->tx) == 1)
1235 + break;
1236 +
1237 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
1238 + *drv_data->qdr = *(u16 *)drv_data->tx;
1239 + else
1240 + *drv_data->qdr = drv_data->void_write_data;
1241 + drv_data->tx += 2;
1242 + } else {
1243 + if (!(drv_data->flags & TRAN_STATE_TX_VOID))
1244 + *drv_data->qdr = *(u8 *)drv_data->tx;
1245 + else
1246 + *drv_data->qdr = *(u8 *)&drv_data->void_write_data;
1247 + drv_data->tx++;
1248 + }
1249 + tx_count++;
1250 + }
1251 +
1252 +
1253 + *drv_data->qar = QSPI_COMMAND_RAM;
1254 + while (cmd_count < tx_count) {
1255 + u16 qcr = QSPI_COMMAND
1256 + | QCR_CONT
1257 + | (~((0x01 << drv_data->cs) << 8) & 0x0F00);
1258 +
1259 + if ( (cmd_count == tx_count - 1)
1260 + && (drv_data->tx == drv_data->tx_end)
1261 + && (drv_data->cs_change) ) {
1262 + qcr &= ~QCR_CONT;
1263 + }
1264 + *drv_data->qcr = qcr;
1265 + cmd_count++;
1266 + }
1267 +
1268 + *drv_data->qwr = (*drv_data->qwr & ~QWR_ENDQP_MASK) | ((cmd_count - 1) << 8);
1269 +
1270 + /* Fire it up! */
1271 + *drv_data->qdlyr |= QDLYR_SPE;
1272 +#endif
1273 +
1274 + return tx_count;
1275 +}
1276 +
1277 +
1278 +static int read(struct driver_data *drv_data)
1279 +{
1280 + int rx_count = 0;
1281 + int rx_word;
1282 +#if defined(SPI_DSPI_EDMA)
1283 + u32* rx_edma;
1284 +#endif
1285 + u16 d;
1286 + rx_word = is_word_transfer(drv_data);
1287 +
1288 +#if defined(SPI_DSPI)
1289 +
1290 +#if defined(SPI_DSPI_EDMA)
1291 + rx_edma = (u32*) drv_data->edma_tx_buf;
1292 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < EDMA_BUFFER_SIZE)) {
1293 +#else
1294 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < DSPI_FIFO_SIZE)) {
1295 +#endif
1296 + if (rx_word) {
1297 + if ((drv_data->rx_end - drv_data->rx) == 1)
1298 + break;
1299 +#if defined(SPI_DSPI_EDMA)
1300 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
1301 + rx_edma++;
1302 +#else
1303 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
1304 +#endif
1305 +
1306 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
1307 + *(u16 *)drv_data->rx = d;
1308 + drv_data->rx += 2;
1309 + } else {
1310 +#if defined(SPI_DSPI_EDMA)
1311 + d = MCF_DSPI_DRFR_RXDATA(*rx_edma);
1312 + rx_edma++;
1313 +#else
1314 + d = MCF_DSPI_DRFR_RXDATA(*drv_data->dspi_drfr);
1315 +#endif
1316 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
1317 + *(u8 *)drv_data->rx = d;
1318 + drv_data->rx++;
1319 + }
1320 + rx_count++;
1321 + }
1322 +
1323 +
1324 +#else
1325 +
1326 + *drv_data->qar = QSPI_RECEIVE_RAM;
1327 + while ((drv_data->rx < drv_data->rx_end) && (rx_count < QSPI_RAM_SIZE)) {
1328 + if (rx_word) {
1329 + if ((drv_data->rx_end - drv_data->rx) == 1)
1330 + break;
1331 +
1332 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
1333 + *(u16 *)drv_data->rx = *drv_data->qdr;
1334 + drv_data->rx += 2;
1335 + } else {
1336 + if (!(drv_data->flags & TRAN_STATE_RX_VOID))
1337 + *(u8 *)drv_data->rx = *drv_data->qdr;
1338 + drv_data->rx++;
1339 + }
1340 + rx_count++;
1341 + }
1342 +#endif
1343 +
1344 + return rx_count;
1345 +}
1346 +
1347 +
1348 +static inline void qspi_setup_chip(struct driver_data *drv_data)
1349 +{
1350 + struct chip_data *chip = drv_data->cur_chip;
1351 +
1352 +#if defined(SPI_DSPI)
1353 +
1354 + *drv_data->mcr = chip->mcr_val;
1355 +
1356 + // TODO: remove later
1357 + chip->ctar_val = 0x78560118;
1358 +
1359 + *drv_data->ctar = chip->ctar_val;
1360 + *drv_data->dspi_rser = 0
1361 + | MCF_DSPI_DRSER_EOQFE
1362 +#if defined(SPI_DSPI_EDMA)
1363 + | MCF_DSPI_DRSER_TFFFE
1364 + | MCF_DSPI_DRSER_TFFFS
1365 +#endif
1366 + ;
1367 +
1368 +
1369 +#else
1370 + *drv_data->qmr = chip->qmr_val;
1371 + *drv_data->qdlyr = chip->qdlyr_val;
1372 + *drv_data->qwr = chip->qwr_val;
1373 +
1374 + /*
1375 + * Enable all the interrupts and clear all the flags
1376 + */
1377 + *drv_data->qir = (QIR_SPIFE | QIR_ABRTE | QIR_WCEFE)
1378 + | (QIR_WCEFB | QIR_ABRTB | QIR_ABRTL)
1379 + | (QIR_SPIF | QIR_ABRT | QIR_WCEF);
1380 +#endif
1381 +}
1382 +
1383 +#if defined(SPI_DSPI_EDMA)
1384 +static int edma_tx_handler(int channel, void* dev)
1385 +{
1386 + if (channel == DSPI_DMA_TX_TCD) {
1387 + stop_edma_transfer(DSPI_DMA_TX_TCD);
1388 + }
1389 + return IRQ_HANDLED;
1390 +}
1391 +
1392 +static int edma_rx_handler(int channel, void* dev)
1393 +{
1394 + if (channel == DSPI_DMA_RX_TCD) {
1395 + stop_edma_transfer(DSPI_DMA_RX_TCD);
1396 + }
1397 +
1398 + return IRQ_HANDLED;
1399 +}
1400 +#endif
1401 +
1402 +static irqreturn_t qspi_interrupt(int irq, void *dev_id)
1403 +{
1404 + struct driver_data *drv_data = (struct driver_data *)dev_id;
1405 + struct spi_message *msg = drv_data->cur_msg;
1406 +#if defined(SPI_DSPI)
1407 +#if !defined(SPI_DSPI_EDMA)
1408 + u32 irq_status = *drv_data->dspi_sr;
1409 +#endif
1410 +#else
1411 + u16 irq_status = *drv_data->qir;
1412 +#endif
1413 +
1414 + /* Clear all flags immediately */
1415 +#if defined(SPI_DSPI)
1416 + *drv_data->dspi_sr = MCF_DSPI_DSR_EOQF;
1417 +#else
1418 + *drv_data->qir |= (QIR_SPIF | QIR_ABRT | QIR_WCEF);
1419 +#endif
1420 +
1421 + if (!drv_data->cur_msg || !drv_data->cur_msg->state) {
1422 +#if !defined(SPI_DSPI_EDMA)
1423 + /* if eDMA is used it happens some time (at least once)*/
1424 + printk(KERN_ERR "coldfire-qspi: bad message or transfer "
1425 + "state in interrupt handler. IRQ status=%x\n", irq_status);
1426 +#endif
1427 + return IRQ_NONE;
1428 + }
1429 +
1430 +#if !defined(SPI_DSPI)
1431 + if (irq_status & QIR_SPIF) {
1432 +#endif
1433 + /*
1434 + * Read the data into the buffer and reload and start
1435 + * queue with new data if not finished. If finished
1436 + * then setup the next transfer
1437 + */
1438 + read(drv_data);
1439 +
1440 + if (drv_data->rx == drv_data->rx_end) {
1441 + /*
1442 + * Finished now - fall through and schedule next
1443 + * transfer tasklet
1444 + */
1445 + if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) {
1446 + //*drv_data->qmr &= ~QMR_BITS;
1447 + set_16bit_transfer_mode(drv_data);
1448 + }
1449 +
1450 + msg->state = next_transfer(drv_data);
1451 + msg->actual_length += drv_data->len;
1452 + } else {
1453 + /* not finished yet - keep going */
1454 + write(drv_data);
1455 + return IRQ_HANDLED;
1456 + }
1457 +#if !defined(SPI_DSPI)
1458 + } else {
1459 + if (irq_status & QIR_WCEF)
1460 + drv_data->wce_cnt++;
1461 +
1462 + if (irq_status & QIR_ABRT)
1463 + drv_data->abrt_cnt++;
1464 +
1465 + msg->state = ERROR_STATE;
1466 + }
1467 +#endif
1468 +
1469 + tasklet_schedule(&drv_data->pump_transfers);
1470 +
1471 + return IRQ_HANDLED;
1472 +}
1473 +
1474 +/* caller already set message->status; dma and pio irqs are blocked */
1475 +static void giveback(struct driver_data *drv_data)
1476 +{
1477 + struct spi_transfer* last_transfer;
1478 + unsigned long flags;
1479 + struct spi_message *msg;
1480 +
1481 + spin_lock_irqsave(&drv_data->lock, flags);
1482 + msg = drv_data->cur_msg;
1483 + drv_data->cur_msg = NULL;
1484 + drv_data->cur_transfer = NULL;
1485 + drv_data->cur_chip = NULL;
1486 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
1487 + spin_unlock_irqrestore(&drv_data->lock, flags);
1488 +
1489 + last_transfer = list_entry(msg->transfers.prev,
1490 + struct spi_transfer,
1491 + transfer_list);
1492 +
1493 + if (!last_transfer->cs_change)
1494 + drv_data->cs_control(drv_data->cs, QSPI_CS_DROP);
1495 +
1496 + msg->state = NULL;
1497 + if (msg->complete)
1498 + msg->complete(msg->context);
1499 +}
1500 +
1501 +
1502 +static void pump_transfers(unsigned long data)
1503 +{
1504 + struct driver_data *drv_data = (struct driver_data *)data;
1505 + struct spi_message *message = NULL;
1506 + struct spi_transfer *transfer = NULL;
1507 + struct spi_transfer *previous = NULL;
1508 + struct chip_data *chip = NULL;
1509 + unsigned long flags;
1510 +
1511 + /* Get current state information */
1512 + message = drv_data->cur_msg;
1513 + transfer = drv_data->cur_transfer;
1514 + chip = drv_data->cur_chip;
1515 +
1516 + /* Handle for abort */
1517 + if (message->state == ERROR_STATE) {
1518 + message->status = -EIO;
1519 + giveback(drv_data);
1520 + return;
1521 + }
1522 +
1523 + /* Handle end of message */
1524 + if (message->state == DONE_STATE) {
1525 + message->status = 0;
1526 + giveback(drv_data);
1527 + return;
1528 + }
1529 +
1530 + if (message->state == START_STATE) {
1531 + qspi_setup_chip(drv_data);
1532 +
1533 + if (drv_data->cs_control) {
1534 + //printk( "m s\n" );
1535 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
1536 + }
1537 + }
1538 +
1539 + /* Delay if requested at end of transfer*/
1540 + if (message->state == RUNNING_STATE) {
1541 + previous = list_entry(transfer->transfer_list.prev,
1542 + struct spi_transfer,
1543 + transfer_list);
1544 +
1545 + if (drv_data->cs_control && transfer->cs_change)
1546 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_DROP);
1547 +
1548 + if (previous->delay_usecs)
1549 + udelay(previous->delay_usecs);
1550 +
1551 + if (drv_data->cs_control && transfer->cs_change)
1552 + drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
1553 + }
1554 +
1555 + drv_data->flags = 0;
1556 + drv_data->tx = (void *)transfer->tx_buf;
1557 + drv_data->tx_end = drv_data->tx + transfer->len;
1558 + drv_data->rx = transfer->rx_buf;
1559 + drv_data->rx_end = drv_data->rx + transfer->len;
1560 + drv_data->len = transfer->len;
1561 + if (!drv_data->rx)
1562 + drv_data->flags |= TRAN_STATE_RX_VOID;
1563 + if (!drv_data->tx)
1564 + drv_data->flags |= TRAN_STATE_TX_VOID;
1565 + drv_data->cs = message->spi->chip_select;
1566 + drv_data->cs_change = transfer->cs_change;
1567 + drv_data->void_write_data = chip->void_write_data;
1568 +
1569 + message->state = RUNNING_STATE;
1570 +
1571 + /* Go baby, go */
1572 + local_irq_save(flags);
1573 + write(drv_data);
1574 + local_irq_restore(flags);
1575 +}
1576 +
1577 +
1578 +static void pump_messages(struct work_struct * work)
1579 +{
1580 + struct driver_data *drv_data;
1581 + unsigned long flags;
1582 +
1583 + drv_data = container_of(work, struct driver_data, pump_messages);
1584 +
1585 + /* Lock queue and check for queue work */
1586 + spin_lock_irqsave(&drv_data->lock, flags);
1587 + if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1588 + drv_data->busy = 0;
1589 + spin_unlock_irqrestore(&drv_data->lock, flags);
1590 + return;
1591 + }
1592 +
1593 + /* Make sure we are not already running a message */
1594 + if (drv_data->cur_msg) {
1595 + spin_unlock_irqrestore(&drv_data->lock, flags);
1596 + return;
1597 + }
1598 +
1599 + /* Extract head of queue */
1600 + drv_data->cur_msg = list_entry(drv_data->queue.next,
1601 + struct spi_message, queue);
1602 + list_del_init(&drv_data->cur_msg->queue);
1603 +
1604 + /* Initial message state*/
1605 + drv_data->cur_msg->state = START_STATE;
1606 + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1607 + struct spi_transfer,
1608 + transfer_list);
1609 +
1610 + /* Setup the SPI Registers using the per chip configuration */
1611 + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1612 +
1613 + /* Mark as busy and launch transfers */
1614 + tasklet_schedule(&drv_data->pump_transfers);
1615 +
1616 + drv_data->busy = 1;
1617 + spin_unlock_irqrestore(&drv_data->lock, flags);
1618 +}
1619 +
1620 +/****************************************************************************/
1621 +
1622 +/*
1623 + * SPI master implementation
1624 + */
1625 +
1626 +static int transfer(struct spi_device *spi, struct spi_message *msg)
1627 +{
1628 + struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1629 + unsigned long flags;
1630 +
1631 + spin_lock_irqsave(&drv_data->lock, flags);
1632 +
1633 + if (drv_data->run == QUEUE_STOPPED) {
1634 + spin_unlock_irqrestore(&drv_data->lock, flags);
1635 + return -ESHUTDOWN;
1636 + }
1637 +
1638 + msg->actual_length = 0;
1639 + msg->status = -EINPROGRESS;
1640 + msg->state = START_STATE;
1641 +
1642 + list_add_tail(&msg->queue, &drv_data->queue);
1643 +
1644 + if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1645 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
1646 +
1647 + spin_unlock_irqrestore(&drv_data->lock, flags);
1648 +
1649 + return 0;
1650 +}
1651 +
1652 +
1653 +static int setup(struct spi_device *spi)
1654 +{
1655 + struct coldfire_spi_chip *chip_info;
1656 + struct chip_data *chip;
1657 +#ifndef SPI_DSPI
1658 + u32 baud_divisor = 255;
1659 +#endif
1660 +
1661 + chip_info = (struct coldfire_spi_chip *)spi->controller_data;
1662 +
1663 + /* Only alloc on first setup */
1664 + chip = spi_get_ctldata(spi);
1665 + if (chip == NULL) {
1666 + chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL);
1667 + if (!chip)
1668 + return -ENOMEM;
1669 + spi->mode = chip_info->mode;
1670 + spi->bits_per_word = chip_info->bits_per_word;
1671 + }
1672 +
1673 +#if defined(SPI_DSPI)
1674 + chip->mcr.master = 1;
1675 + chip->mcr.cont_scke = 0;
1676 + chip->mcr.dconf = 0;
1677 + chip->mcr.frz = 0;
1678 + chip->mcr.mtfe = 1;
1679 + chip->mcr.pcsse = 0;
1680 + chip->mcr.rooe = 0;
1681 + chip->mcr.pcsis = 0xFF;
1682 + chip->mcr.reserved15 = 0;
1683 + chip->mcr.mdis = 0;
1684 + chip->mcr.dis_tx = 0;
1685 + chip->mcr.dis_rxf = 0;
1686 + chip->mcr.clr_tx = 1;
1687 + chip->mcr.clr_rxf = 1;
1688 + chip->mcr.smpl_pt = 0;
1689 + chip->mcr.reserved71 = 0;
1690 + chip->mcr.halt = 0;
1691 +
1692 + if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
1693 + chip->ctar.fmsz = spi->bits_per_word-1;
1694 + } else {
1695 + printk(KERN_ERR "coldfire-qspi: invalid wordsize\n");
1696 + kfree(chip);
1697 + return -ENODEV;
1698 + }
1699 +
1700 + if (spi->mode & SPI_CPHA)
1701 + chip->ctar.cpha = 1;
1702 + else
1703 + chip->ctar.cpha = 0;
1704 +
1705 + if (spi->mode & SPI_CPOL)
1706 + chip->ctar.cpol = 1;
1707 + else
1708 + chip->ctar.cpol = 0;
1709 +
1710 + if (spi->mode & SPI_LSB_FIRST)
1711 + chip->ctar.lsbfe = 1;
1712 + else
1713 + chip->ctar.lsbfe = 0;
1714 +
1715 + /* This values are default for audio device */
1716 + chip->ctar.dbr = 0;
1717 + chip->ctar.pbr = 2;
1718 + chip->ctar.br = 8;
1719 +
1720 + /* This values are default for audio device */
1721 + chip->ctar.pcssck = 1;
1722 + chip->ctar.pasc = 1;
1723 + chip->ctar.pdt = 1;
1724 + chip->ctar.cssck = 0;
1725 + chip->ctar.asc = 1;
1726 + chip->ctar.dt = 1;
1727 +
1728 + chip->void_write_data = chip_info->void_write_data;
1729 +
1730 +#else
1731 +
1732 + chip->qwr.csiv = 1; // Chip selects are active low
1733 + chip->qmr.master = 1; // Must set to master mode
1734 + chip->qmr.dohie = 1; // Data output high impediance enabled
1735 + chip->void_write_data = chip_info->void_write_data;
1736 +
1737 + chip->qdlyr.qcd = chip_info->del_cs_to_clk;
1738 + chip->qdlyr.dtl = chip_info->del_after_trans;
1739 +
1740 + if (spi->max_speed_hz != 0)
1741 + baud_divisor = (MCF_CLK/(2*spi->max_speed_hz));
1742 +
1743 + if (baud_divisor < 2)
1744 + baud_divisor = 2;
1745 +
1746 + if (baud_divisor > 255)
1747 + baud_divisor = 255;
1748 +
1749 + chip->qmr.baud = baud_divisor;
1750 +
1751 + //printk( "QSPI: spi->max_speed_hz %d\n", spi->max_speed_hz );
1752 + //printk( "QSPI: Baud set to %d\n", chip->qmr.baud );
1753 +
1754 + if (spi->mode & SPI_CPHA)
1755 + chip->qmr.cpha = 1;
1756 +
1757 + if (spi->mode & SPI_CPOL)
1758 + chip->qmr.cpol = 1;
1759 +
1760 + if (spi->bits_per_word == 16) {
1761 + chip->qmr.bits = 0;
1762 + } else if ((spi->bits_per_word >= 8) && (spi->bits_per_word <= 15)) {
1763 + chip->qmr.bits = spi->bits_per_word;
1764 + } else {
1765 + printk(KERN_ERR "coldfire-qspi: invalid wordsize\n");
1766 + kfree(chip);
1767 + return -ENODEV;
1768 + }
1769 +
1770 +#endif
1771 +
1772 + spi_set_ctldata(spi, chip);
1773 +
1774 + return 0;
1775 +}
1776 +
1777 +static int init_queue(struct driver_data *drv_data)
1778 +{
1779 + INIT_LIST_HEAD(&drv_data->queue);
1780 + spin_lock_init(&drv_data->lock);
1781 +
1782 + drv_data->run = QUEUE_STOPPED;
1783 + drv_data->busy = 0;
1784 +
1785 + tasklet_init(&drv_data->pump_transfers,
1786 + pump_transfers, (unsigned long)drv_data);
1787 +
1788 + INIT_WORK(&drv_data->pump_messages, pump_messages/*, drv_data*/);
1789 +
1790 + drv_data->workqueue = create_singlethread_workqueue(
1791 + drv_data->master->cdev.dev->bus_id);
1792 + if (drv_data->workqueue == NULL)
1793 + return -EBUSY;
1794 +
1795 + return 0;
1796 +}
1797 +
1798 +static int start_queue(struct driver_data *drv_data)
1799 +{
1800 + unsigned long flags;
1801 +
1802 + spin_lock_irqsave(&drv_data->lock, flags);
1803 +
1804 + if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1805 + spin_unlock_irqrestore(&drv_data->lock, flags);
1806 + return -EBUSY;
1807 + }
1808 +
1809 + drv_data->run = QUEUE_RUNNING;
1810 + drv_data->cur_msg = NULL;
1811 + drv_data->cur_transfer = NULL;
1812 + drv_data->cur_chip = NULL;
1813 + spin_unlock_irqrestore(&drv_data->lock, flags);
1814 +
1815 + queue_work(drv_data->workqueue, &drv_data->pump_messages);
1816 +
1817 + return 0;
1818 +}
1819 +
1820 +static int stop_queue(struct driver_data *drv_data)
1821 +{
1822 + unsigned long flags;
1823 + unsigned limit = 500;
1824 + int status = 0;
1825 +
1826 + spin_lock_irqsave(&drv_data->lock, flags);
1827 +
1828 + /* This is a bit lame, but is optimized for the common execution path.
1829 + * A wait_queue on the drv_data->busy could be used, but then the common
1830 + * execution path (pump_messages) would be required to call wake_up or
1831 + * friends on every SPI message. Do this instead */
1832 + drv_data->run = QUEUE_STOPPED;
1833 + while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1834 + spin_unlock_irqrestore(&drv_data->lock, flags);
1835 + msleep(10);
1836 + spin_lock_irqsave(&drv_data->lock, flags);
1837 + }
1838 +
1839 + if (!list_empty(&drv_data->queue) || drv_data->busy)
1840 + status = -EBUSY;
1841 +
1842 + spin_unlock_irqrestore(&drv_data->lock, flags);
1843 +
1844 + return status;
1845 +}
1846 +
1847 +static int destroy_queue(struct driver_data *drv_data)
1848 +{
1849 + int status;
1850 +
1851 + status = stop_queue(drv_data);
1852 + if (status != 0)
1853 + return status;
1854 +
1855 + destroy_workqueue(drv_data->workqueue);
1856 +
1857 + return 0;
1858 +}
1859 +
1860 +
1861 +static void cleanup(const struct spi_device *spi)
1862 +{
1863 + struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1864 +
1865 + dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1866 + spi->master->bus_num, spi->chip_select);
1867 +
1868 + kfree(chip);
1869 +}
1870 +
1871 +
1872 +/****************************************************************************/
1873 +
1874 +/*
1875 + * Generic Device driver routines and interface implementation
1876 + */
1877 +
1878 +static int coldfire_spi_probe(struct platform_device *pdev)
1879 +{
1880 + struct device *dev = &pdev->dev;
1881 + struct coldfire_spi_master *platform_info;
1882 + struct spi_master *master;
1883 + struct driver_data *drv_data = 0;
1884 + struct resource *memory_resource;
1885 + int irq;
1886 + int status = 0;
1887 + int i;
1888 +
1889 +#if defined(SPI_DSPI_EDMA)
1890 + init_edma();
1891 +#endif
1892 +
1893 + platform_info = (struct coldfire_spi_master *)pdev->dev.platform_data;
1894 +
1895 + master = spi_alloc_master(dev, sizeof(struct driver_data));
1896 + if (!master)
1897 + return -ENOMEM;
1898 +
1899 + drv_data = class_get_devdata(&master->cdev);
1900 + drv_data->master = master;
1901 +
1902 + INIT_LIST_HEAD(&drv_data->queue);
1903 + spin_lock_init(&drv_data->lock);
1904 +
1905 + master->bus_num = platform_info->bus_num;
1906 + master->num_chipselect = platform_info->num_chipselect;
1907 + master->cleanup = cleanup;
1908 + master->setup = setup;
1909 + master->transfer = transfer;
1910 +
1911 + drv_data->cs_control = platform_info->cs_control;
1912 + if (drv_data->cs_control)
1913 + for(i = 0; i < master->num_chipselect; i++)
1914 + drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
1915 +
1916 + /* Setup register addresses */
1917 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-module");
1918 + if (!memory_resource) {
1919 + dev_dbg(dev, "can not find platform module memory\n");
1920 + goto out_error_master_alloc;
1921 + }
1922 +
1923 +#if defined(SPI_DSPI_EDMA)
1924 + drv_data->edma_tx_buf = kmalloc(EDMA_BUFSIZE_KMALLOC, GFP_DMA);
1925 + if (!drv_data->edma_tx_buf) {
1926 + dev_dbg(dev, "cannot allocate eDMA TX memory\n");
1927 + goto out_error_master_alloc;
1928 + }
1929 + drv_data->edma_rx_buf = kmalloc(EDMA_BUFSIZE_KMALLOC, GFP_DMA);
1930 + if (!drv_data->edma_rx_buf) {
1931 + kfree(drv_data->edma_tx_buf);
1932 + dev_dbg(dev, "cannot allocate eDMA RX memory\n");
1933 + goto out_error_master_alloc;
1934 + }
1935 +#endif
1936 +
1937 +#if defined(SPI_DSPI)
1938 +
1939 + drv_data->mcr = (void *)(memory_resource->start + 0x00000000);
1940 + drv_data->ctar = (void *)(memory_resource->start + 0x0000000C);
1941 + drv_data->dspi_sr = (void *)(memory_resource->start + 0x0000002C);
1942 + drv_data->dspi_rser = (void *)(memory_resource->start + 0x00000030);
1943 + drv_data->dspi_dtfr = (void *)(memory_resource->start + 0x00000034);
1944 + drv_data->dspi_drfr = (void *)(memory_resource->start + 0x00000038);
1945 +
1946 +#else
1947 +
1948 + drv_data->qmr = (void *)(memory_resource->start + 0x00000000);
1949 + drv_data->qdlyr = (void *)(memory_resource->start + 0x00000004);
1950 + drv_data->qwr = (void *)(memory_resource->start + 0x00000008);
1951 + drv_data->qir = (void *)(memory_resource->start + 0x0000000c);
1952 + drv_data->qar = (void *)(memory_resource->start + 0x00000010);
1953 + drv_data->qdr = (void *)(memory_resource->start + 0x00000014);
1954 + drv_data->qcr = (void *)(memory_resource->start + 0x00000014);
1955 +
1956 +#endif
1957 +
1958 + /* Setup register addresses */
1959 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-par");
1960 + if (!memory_resource) {
1961 + dev_dbg(dev, "can not find platform par memory\n");
1962 + goto out_error_master_alloc;
1963 + }
1964 +
1965 + drv_data->par = (void *)memory_resource->start;
1966 +
1967 + /* Setup register addresses */
1968 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-int-level");
1969 + if (!memory_resource) {
1970 + dev_dbg(dev, "can not find platform par memory\n");
1971 + goto out_error_master_alloc;
1972 + }
1973 +
1974 + drv_data->int_icr = (void *)memory_resource->start;
1975 +
1976 + /* Setup register addresses */
1977 + memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-int-mask");
1978 + if (!memory_resource) {
1979 + dev_dbg(dev, "can not find platform par memory\n");
1980 + goto out_error_master_alloc;
1981 + }
1982 +
1983 + drv_data->int_mr = (void *)memory_resource->start;
1984 +
1985 + irq = platform_info->irq_vector;
1986 +
1987 + status = request_irq(platform_info->irq_vector, qspi_interrupt, SA_INTERRUPT, dev->bus_id, drv_data);
1988 + if (status < 0) {
1989 + dev_err(&pdev->dev, "unable to attach ColdFire QSPI interrupt\n");
1990 + goto out_error_master_alloc;
1991 + }
1992 +
1993 + /* Now that we have all the addresses etc. Let's set it up */
1994 + // TODO:
1995 + //*drv_data->par = platform_info->par_val;
1996 +
1997 + MCF_GPIO_PAR_DSPI = 0
1998 + | MCF_GPIO_PAR_DSPI_PCS5_PCS5
1999 + | MCF_GPIO_PAR_DSPI_PCS2_PCS2
2000 + | MCF_GPIO_PAR_DSPI_PCS1_PCS1
2001 + | MCF_GPIO_PAR_DSPI_PCS0_PCS0
2002 + | MCF_GPIO_PAR_DSPI_SIN_SIN
2003 + | MCF_GPIO_PAR_DSPI_SOUT_SOUT
2004 + | MCF_GPIO_PAR_DSPI_SCK_SCK;
2005 +
2006 + *drv_data->int_icr = platform_info->irq_lp;
2007 + *drv_data->int_mr &= ~platform_info->irq_mask;
2008 +
2009 +#ifdef SPI_DSPI
2010 + drv_data->dspi_ctas = 0; // TODO: change later
2011 +#endif
2012 +
2013 + /* Initial and start queue */
2014 + status = init_queue(drv_data);
2015 + if (status != 0) {
2016 + dev_err(&pdev->dev, "problem initializing queue\n");
2017 + goto out_error_irq_alloc;
2018 + }
2019 + status = start_queue(drv_data);
2020 + if (status != 0) {
2021 + dev_err(&pdev->dev, "problem starting queue\n");
2022 + goto out_error_irq_alloc;
2023 + }
2024 +
2025 + /* Register with the SPI framework */
2026 + platform_set_drvdata(pdev, drv_data);
2027 + status = spi_register_master(master);
2028 + if (status != 0) {
2029 + dev_err(&pdev->dev, "problem registering spi master\n");
2030 + status = -EINVAL;
2031 + goto out_error_queue_alloc;
2032 + }
2033 +
2034 +#if defined(SPI_DSPI_EDMA)
2035 + if (request_edma_channel(DSPI_DMA_TX_TCD,
2036 + edma_tx_handler,
2037 + NULL,
2038 + pdev,
2039 + NULL, /* spinlock */
2040 + DRIVER_NAME
2041 + )!=0)
2042 + {
2043 + dev_err(&pdev->dev, "problem requesting edma transmit channel\n");
2044 + status = -EINVAL;
2045 + goto out_error_queue_alloc;
2046 + }
2047 +
2048 + if (request_edma_channel(DSPI_DMA_RX_TCD,
2049 + edma_rx_handler,
2050 + NULL,
2051 + pdev,
2052 + NULL, /* spinlock */
2053 + DRIVER_NAME
2054 + )!=0)
2055 + {
2056 + dev_err(&pdev->dev, "problem requesting edma receive channel\n");
2057 + status = -EINVAL;
2058 + goto out_edma_transmit;
2059 + }
2060 +#endif
2061 +
2062 + printk( "SPI: Coldfire master initialized\n" );
2063 + //dev_info(&pdev->dev, "driver initialized\n");
2064 + return status;
2065 +
2066 +#if defined(SPI_DSPI_EDMA)
2067 +out_edma_transmit:
2068 + free_edma_channel(DSPI_DMA_TX_TCD, pdev);
2069 +#endif
2070 +
2071 +out_error_queue_alloc:
2072 + destroy_queue(drv_data);
2073 +
2074 +out_error_irq_alloc:
2075 + free_irq(irq, drv_data);
2076 +
2077 +out_error_master_alloc:
2078 + spi_master_put(master);
2079 + return status;
2080 +
2081 +}
2082 +
2083 +static int coldfire_spi_remove(struct platform_device *pdev)
2084 +{
2085 + struct driver_data *drv_data = platform_get_drvdata(pdev);
2086 + int irq;
2087 + int status = 0;
2088 +
2089 + if (!drv_data)
2090 + return 0;
2091 +
2092 +#if defined(SPI_DSPI_EDMA)
2093 + free_edma_channel(DSPI_DMA_TX_TCD, pdev);
2094 + free_edma_channel(DSPI_DMA_RX_TCD, pdev);
2095 +#endif
2096 +
2097 + /* Remove the queue */
2098 + status = destroy_queue(drv_data);
2099 + if (status != 0)
2100 + return status;
2101 +
2102 + /* Disable the SSP at the peripheral and SOC level */
2103 + /*write_SSCR0(0, drv_data->ioaddr);
2104 + pxa_set_cken(drv_data->master_info->clock_enable, 0);*/
2105 +
2106 + /* Release DMA */
2107 + /*if (drv_data->master_info->enable_dma) {
2108 + if (drv_data->ioaddr == SSP1_VIRT) {
2109 + DRCMRRXSSDR = 0;
2110 + DRCMRTXSSDR = 0;
2111 + } else if (drv_data->ioaddr == SSP2_VIRT) {
2112 + DRCMRRXSS2DR = 0;
2113 + DRCMRTXSS2DR = 0;
2114 + } else if (drv_data->ioaddr == SSP3_VIRT) {
2115 + DRCMRRXSS3DR = 0;
2116 + DRCMRTXSS3DR = 0;
2117 + }
2118 + pxa_free_dma(drv_data->tx_channel);
2119 + pxa_free_dma(drv_data->rx_channel);
2120 + }*/
2121 +
2122 + /* Release IRQ */
2123 + irq = platform_get_irq(pdev, 0);
2124 + if (irq >= 0)
2125 + free_irq(irq, drv_data);
2126 +
2127 + /* Disconnect from the SPI framework */
2128 + spi_unregister_master(drv_data->master);
2129 +
2130 + /* Prevent double remove */
2131 + platform_set_drvdata(pdev, NULL);
2132 +
2133 + return 0;
2134 +}
2135 +
2136 +static void coldfire_spi_shutdown(struct platform_device *pdev)
2137 +{
2138 + int status = 0;
2139 +
2140 + if ((status = coldfire_spi_remove(pdev)) != 0)
2141 + dev_err(&pdev->dev, "shutdown failed with %d\n", status);
2142 +}
2143 +
2144 +
2145 +#ifdef CONFIG_PM
2146 +static int suspend_devices(struct device *dev, void *pm_message)
2147 +{
2148 + pm_message_t *state = pm_message;
2149 +
2150 + if (dev->power.power_state.event != state->event) {
2151 + dev_warn(dev, "pm state does not match request\n");
2152 + return -1;
2153 + }
2154 +
2155 + return 0;
2156 +}
2157 +
2158 +static int coldfire_spi_suspend(struct platform_device *pdev, pm_message_t state)
2159 +{
2160 + struct driver_data *drv_data = platform_get_drvdata(pdev);
2161 + int status = 0;
2162 +
2163 + /* Check all childern for current power state */
2164 + if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
2165 + dev_warn(&pdev->dev, "suspend aborted\n");
2166 + return -1;
2167 + }
2168 +
2169 + status = stop_queue(drv_data);
2170 + if (status != 0)
2171 + return status;
2172 + /*write_SSCR0(0, drv_data->ioaddr);
2173 + pxa_set_cken(drv_data->master_info->clock_enable, 0);*/
2174 +
2175 + return 0;
2176 +}
2177 +
2178 +static int coldfire_spi_resume(struct platform_device *pdev)
2179 +{
2180 + struct driver_data *drv_data = platform_get_drvdata(pdev);
2181 + int status = 0;
2182 +
2183 + /* Enable the SSP clock */
2184 + /*pxa_set_cken(drv_data->master_info->clock_enable, 1);*/
2185 +
2186 + /* Start the queue running */
2187 + status = start_queue(drv_data);
2188 + if (status != 0) {
2189 + dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
2190 + return status;
2191 + }
2192 +
2193 + return 0;
2194 +}
2195 +#else
2196 +#define coldfire_spi_suspend NULL
2197 +#define coldfire_spi_resume NULL
2198 +#endif /* CONFIG_PM */
2199 +
2200 +static struct platform_driver driver = {
2201 + .driver = {
2202 + .name = "spi_coldfire",
2203 + .bus = &platform_bus_type,
2204 + .owner = THIS_MODULE,
2205 + },
2206 + .probe = coldfire_spi_probe,
2207 + .remove = __devexit_p(coldfire_spi_remove),
2208 + .shutdown = coldfire_spi_shutdown,
2209 + .suspend = coldfire_spi_suspend,
2210 + .resume = coldfire_spi_resume,
2211 +};
2212 +
2213 +static int __init coldfire_spi_init(void)
2214 +{
2215 + platform_driver_register(&driver);
2216 +
2217 + return 0;
2218 +}
2219 +module_init(coldfire_spi_init);
2220 +
2221 +static void __exit coldfire_spi_exit(void)
2222 +{
2223 + platform_driver_unregister(&driver);
2224 +}
2225 +module_exit(coldfire_spi_exit);
2226 --- /dev/null
2227 +++ b/drivers/spi/ssi_audio.c
2228 @@ -0,0 +1,906 @@
2229 +/*
2230 + * MCF5445x audio driver.
2231 + *
2232 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
2233 + * Copyright Freescale Semiconductor, Inc. 2006
2234 + *
2235 + * This program is free software; you can redistribute it and/or modify
2236 + * it under the terms of the GNU General Public License as published by
2237 + * the Free Software Foundation; either version 2 of the License, or
2238 + * (at your option) any later version.
2239 + */
2240 +
2241 +#include <linux/device.h>
2242 +#include <linux/init.h>
2243 +#include <linux/delay.h>
2244 +#include <linux/spi/spi.h>
2245 +#include <linux/fs.h>
2246 +#include <linux/kernel.h>
2247 +#include <linux/major.h>
2248 +#include <asm/mcfsim.h>
2249 +#include <linux/interrupt.h>
2250 +#include <linux/soundcard.h>
2251 +#include <asm/uaccess.h>
2252 +#include <asm/virtconvert.h>
2253 +
2254 +#include <asm/coldfire.h>
2255 +#include <asm/coldfire_edma.h>
2256 +#include <asm/mcf5445x_ssi.h>
2257 +#include <asm/mcf5445x_ccm.h>
2258 +#include <asm/mcf5445x_gpio.h>
2259 +
2260 +#define SOUND_DEVICE_NAME "sound"
2261 +#define DRIVER_NAME "ssi_audio"
2262 +
2263 +
2264 +/* #define AUDIO_DEBUG */
2265 +
2266 +#ifdef CONFIG_MMU
2267 +#define USE_MMU
2268 +#endif
2269 +
2270 +#define MAX_SPEED_HZ 12000000
2271 +
2272 +#define M5445x_AUDIO_IRQ_SOURCE 49
2273 +#define M5445x_AUDIO_IRQ_VECTOR (128+M5445x_AUDIO_IRQ_SOURCE)
2274 +#define M5445x_AUDIO_IRQ_LEVEL 5
2275 +
2276 +/* TLV320DAC23 audio chip registers */
2277 +
2278 +#define CODEC_LEFT_IN_REG (0x00)
2279 +#define CODEC_RIGHT_IN_REG (0x01)
2280 +#define CODEC_LEFT_HP_VOL_REG (0x02)
2281 +#define CODEC_RIGHT_HP_VOL_REG (0x03)
2282 +#define CODEC_ANALOG_APATH_REG (0x04)
2283 +#define CODEC_DIGITAL_APATH_REG (0x05)
2284 +#define CODEC_POWER_DOWN_REG (0x06)
2285 +#define CODEC_DIGITAL_IF_FMT_REG (0x07)
2286 +#define CODEC_SAMPLE_RATE_REG (0x08)
2287 +#define CODEC_DIGITAL_IF_ACT_REG (0x09)
2288 +#define CODEC_RESET_REG (0x0f)
2289 +
2290 +#define CODEC_SAMPLE_8KHZ (0x0C)
2291 +#define CODEC_SAMPLE_16KHZ (0x58)
2292 +#define CODEC_SAMPLE_22KHZ (0x62)
2293 +#define CODEC_SAMPLE_32KHZ (0x18)
2294 +#define CODEC_SAMPLE_44KHZ (0x22)
2295 +#define CODEC_SAMPLE_48KHZ (0x00)
2296 +
2297 +/* Audio buffer data size */
2298 +#define BUFSIZE (64*1024)
2299 +/* DMA transfer size */
2300 +#define DMASIZE (16*1024)
2301 +
2302 +/* transmit eDMA channel for SSI channel 0 */
2303 +#define DMA_TCD 10
2304 +/* transmit eDMA channel for SSI channel 1 */
2305 +#define DMA_TCD2 11
2306 +
2307 +struct ssi_audio {
2308 + struct spi_device *spi;
2309 + u32 speed;
2310 + u32 stereo;
2311 + u32 bits;
2312 + u32 format;
2313 + u8 isopen;
2314 + u8 dmaing;
2315 + u8 ssi_enabled;
2316 + u8 channel;
2317 + spinlock_t lock;
2318 + u8* audio_buf;
2319 +};
2320 +
2321 +static struct ssi_audio* audio_device = NULL;
2322 +volatile u32 audio_start;
2323 +volatile u32 audio_count;
2324 +volatile u32 audio_append;
2325 +volatile u32 audio_appstart;
2326 +volatile u32 audio_txbusy;
2327 +
2328 +struct ssi_audio_format {
2329 + unsigned int format;
2330 + unsigned int bits;
2331 +} ssi_audio_formattable[] = {
2332 + { AFMT_MU_LAW, 8 },
2333 + { AFMT_A_LAW, 8 },
2334 + { AFMT_IMA_ADPCM, 8 },
2335 + { AFMT_U8, 8 },
2336 + { AFMT_S16_LE, 16 },
2337 + { AFMT_S16_BE, 16 },
2338 + { AFMT_S8, 8 },
2339 + { AFMT_U16_LE, 16 },
2340 + { AFMT_U16_BE, 16 },
2341 +};
2342 +
2343 +#define FORMATSIZE (sizeof(ssi_audio_formattable) / sizeof(struct ssi_audio_format))
2344 +
2345 +static void ssi_audio_setsamplesize(int val)
2346 +{
2347 + int i;
2348 +
2349 + if (audio_device == NULL) return;
2350 +
2351 + for (i = 0; (i < FORMATSIZE); i++) {
2352 + if (ssi_audio_formattable[i].format == val) {
2353 + audio_device->format = ssi_audio_formattable[i].format;
2354 + audio_device->bits = ssi_audio_formattable[i].bits;
2355 + break;
2356 + }
2357 + }
2358 +
2359 +#ifdef AUDIO_DEBUG
2360 + printk(DRIVER_NAME ":ssi_audio_setsamplesize %d %d\n", audio_device->format, audio_device->bits);
2361 +#endif
2362 +}
2363 +
2364 +static void ssi_audio_txdrain(void)
2365 +{
2366 +#ifdef AUDIO_DEBUG
2367 + printk(DRIVER_NAME ":ssi_audio_txdrain()\n");
2368 +#endif
2369 +
2370 + if (audio_device == NULL) return;
2371 +
2372 + while (!signal_pending(current)) {
2373 + if (audio_txbusy == 0)
2374 + break;
2375 + current->state = TASK_INTERRUPTIBLE;
2376 + schedule_timeout(1);
2377 + }
2378 +}
2379 +
2380 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
2381 +/*
2382 + * Configure and start DMA engine.
2383 + */
2384 +void __inline__ ssi_audio_dmarun(void)
2385 +{
2386 + set_edma_params(DMA_TCD,
2387 +#ifdef USE_MMU
2388 + virt_to_phys(&(audio_device->audio_buf[audio_start])),
2389 +#else
2390 + (u32)&(audio_device->audio_buf[audio_start]),
2391 +#endif
2392 + (u32)&MCF_SSI_TX0,
2393 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
2394 + 8,
2395 + 4,
2396 + 0,
2397 + audio_count/8,
2398 + audio_count/8,
2399 + 0,
2400 + 0,
2401 + 0, // major_int
2402 + 0 // disable_req
2403 + );
2404 +
2405 + set_edma_params(DMA_TCD2,
2406 +#ifdef USE_MMU
2407 + virt_to_phys(&(audio_device->audio_buf[audio_start+4])),
2408 +#else
2409 + (u32)&(audio_device->audio_buf[audio_start+4]),
2410 +#endif
2411 + (u32)&MCF_SSI_TX1,
2412 + MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
2413 + 8,
2414 + 4,
2415 + 0,
2416 + audio_count/8,
2417 + audio_count/8,
2418 + 0,
2419 + 0,
2420 + 1, // major_int
2421 + 0 // disable_req
2422 + );
2423 +
2424 + audio_device->dmaing = 1;
2425 + audio_txbusy = 1;
2426 +
2427 + start_edma_transfer(DMA_TCD);
2428 + start_edma_transfer(DMA_TCD2);
2429 +#if 0
2430 + MCF_EDMA_ERQ |= (1<<DMA_TCD) | (1<<DMA_TCD2);
2431 + MCF_EDMA_SSRT = DMA_TCD;
2432 + MCF_EDMA_SSRT = DMA_TCD2;
2433 +#endif
2434 +
2435 +}
2436 +
2437 +/*
2438 + * Start DMA'ing a new buffer of data if any available.
2439 + */
2440 +static void ssi_audio_dmabuf(void)
2441 +{
2442 +#ifdef AUDIO_DEBUG
2443 + printk(DRIVER_NAME ":ssi_audio_dmabuf(): append=%x start=%x\n", audio_append, audio_appstart);
2444 +#endif
2445 +
2446 + /* If already running then nothing to do... */
2447 + if (audio_device->dmaing)
2448 + return;
2449 +
2450 + /* Set DMA buffer size */
2451 + audio_count = (audio_append >= audio_appstart) ?
2452 + (audio_append - audio_appstart) :
2453 + (BUFSIZE - audio_appstart);
2454 + if (audio_count > DMASIZE)
2455 + audio_count = DMASIZE;
2456 +
2457 + /* Adjust pointers and counters accordingly */
2458 + audio_appstart += audio_count;
2459 + if (audio_appstart >= BUFSIZE)
2460 + audio_appstart = 0;
2461 +
2462 + if (audio_count > 0)
2463 + ssi_audio_dmarun();
2464 + else {
2465 + audio_txbusy = 0;
2466 +#ifdef AUDIO_DEBUG
2467 + printk(DRIVER_NAME ":DMA buffer is empty!\n");
2468 +#endif
2469 + }
2470 +}
2471 +
2472 +void __inline__ stop_dma(void) {
2473 + stop_edma_transfer(DMA_TCD);
2474 + stop_edma_transfer(DMA_TCD2);
2475 +}
2476 +
2477 +static int ssi_audio_dma_handler_empty(int channel, void *dev_id)
2478 +{
2479 + return IRQ_HANDLED;
2480 +}
2481 +
2482 +static int ssi_audio_dma_handler(int channel, void *dev_id)
2483 +{
2484 +#ifdef AUDIO_DEBUG
2485 + printk(DRIVER_NAME ":ssi_audio_dma_handler(channel=%d)\n", channel);
2486 +#endif
2487 +
2488 + /* Clear DMA interrupt */
2489 + stop_dma();
2490 +
2491 + audio_device->dmaing = 0;
2492 +
2493 + /* Update data pointers and counts */
2494 + audio_start += audio_count;
2495 + if (audio_start >= BUFSIZE)
2496 + audio_start = 0;
2497 + audio_count = 0;
2498 +
2499 + /* Start new DMA buffer if we can */
2500 + ssi_audio_dmabuf();
2501 +
2502 + return IRQ_HANDLED;
2503 +}
2504 +
2505 +static void init_dma(void)
2506 +{
2507 + /* SSI DMA Signals mapped to DMA request */
2508 + MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIMDMA;
2509 + init_edma();
2510 +}
2511 +
2512 +#endif /* CONFIG_SSIAUDIO_USE_EDMA */
2513 +
2514 +
2515 +/* Write CODEC register using SPI
2516 + * address - CODEC register address
2517 + * data - data to be written into register
2518 + */
2519 +static int codec_write(u8 addr, u16 data)
2520 +{
2521 + u16 spi_word;
2522 +
2523 + if (audio_device==NULL || audio_device->spi==NULL)
2524 + return -ENODEV;
2525 +
2526 + spi_word = ((addr & 0x7F)<<9)|(data & 0x1FF);
2527 + return spi_write(audio_device->spi, (const u8*)&spi_word, sizeof(spi_word));
2528 +}
2529 +
2530 +static inline void enable_ssi(void)
2531 +{
2532 + if (audio_device==NULL || audio_device->ssi_enabled) return;
2533 + audio_device->ssi_enabled = 1;
2534 + MCF_SSI_CR |= MCF_SSI_CR_SSI_EN; /* enable SSI module */
2535 + MCF_SSI_CR |= MCF_SSI_CR_TE; /* enable tranmitter */
2536 +}
2537 +
2538 +static inline void disable_ssi(void)
2539 +{
2540 + if (audio_device==NULL || audio_device->ssi_enabled==0) return;
2541 + MCF_SSI_CR &= ~MCF_SSI_CR_TE; /* disable transmitter */
2542 + MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; /* disable SSI module */
2543 + audio_device->ssi_enabled = 0;
2544 +}
2545 +
2546 +/* Audio CODEC initialization */
2547 +/* TODO: also the SSI frequency/dividers must be adjusted */
2548 +static void adjust_codec_speed(void) {
2549 +#ifdef AUDIO_DEBUG
2550 + printk(DRIVER_NAME ":adjust_codec_speed: %d\n", audio_device->speed);
2551 +#endif
2552 +
2553 + if (audio_device->speed == 8000) {
2554 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_8KHZ);
2555 + } else if (audio_device->speed == 16000) {
2556 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_16KHZ);
2557 + } else if (audio_device->speed == 22000) {
2558 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_22KHZ);
2559 + } else if (audio_device->speed == 44000 || audio_device->speed == 44100) {
2560 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_44KHZ);
2561 + } else if (audio_device->speed == 48000) {
2562 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_48KHZ);
2563 + } else {
2564 + /* default 44KHz */
2565 + codec_write(CODEC_SAMPLE_RATE_REG,CODEC_SAMPLE_44KHZ);
2566 + }
2567 +}
2568 +
2569 +static void codec_reset(void)
2570 +{
2571 + codec_write(CODEC_RESET_REG, 0); /* reset the audio chip */
2572 + udelay(1500); /* wait for reset */
2573 +}
2574 +
2575 +static void init_audio_codec(void)
2576 +{
2577 +#ifdef AUDIO_DEBUG
2578 + printk(DRIVER_NAME ":init_audio_codec()\n");
2579 +#endif
2580 + codec_reset();
2581 +
2582 + codec_write(CODEC_LEFT_IN_REG, 0x017);
2583 + codec_write(CODEC_RIGHT_IN_REG, 0x017);
2584 + codec_write(CODEC_POWER_DOWN_REG, 0x000); /* Turn off line input */
2585 + codec_write(CODEC_DIGITAL_IF_FMT_REG, 0x00A); /* I2S slave mode */
2586 + /* codec_write(CODEC_DIGITAL_IF_FMT_REG, 0x042); // I2S master mode */
2587 + codec_write(CODEC_DIGITAL_APATH_REG, 0x007); /* Set A path */
2588 +
2589 + /* set sample rate */
2590 + adjust_codec_speed();
2591 +
2592 + codec_write(CODEC_LEFT_HP_VOL_REG, 0x075); /* set volume */
2593 + codec_write(CODEC_RIGHT_HP_VOL_REG, 0x075); /* set volume */
2594 + codec_write(CODEC_DIGITAL_IF_ACT_REG, 1); /* Activate digital interface */
2595 + codec_write(CODEC_ANALOG_APATH_REG, 0x0F2);
2596 +}
2597 +
2598 +
2599 +static void chip_init(void)
2600 +{
2601 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
2602 + init_dma();
2603 +#endif
2604 +
2605 + /* Enable the SSI pins */
2606 + MCF_GPIO_PAR_SSI = ( 0
2607 + | MCF_GPIO_PAR_SSI_MCLK
2608 + | MCF_GPIO_PAR_SSI_STXD(3)
2609 + | MCF_GPIO_PAR_SSI_SRXD(3)
2610 + | MCF_GPIO_PAR_SSI_FS(3)
2611 + | MCF_GPIO_PAR_SSI_BCLK(3) );
2612 +
2613 +}
2614 +
2615 +static void init_ssi(void)
2616 +{
2617 +#ifdef AUDIO_DEBUG
2618 + printk(DRIVER_NAME ":init_ssi()\n");
2619 +#endif
2620 +
2621 + /* Dividers are for MCF54445 on 266Mhz, the output is 44.1Khz*/
2622 + /* Enable SSI clock in CCM */
2623 + MCF_CCM_CDR = MCF_CCM_CDR_SSIDIV(47);
2624 +
2625 + /* Issue a SSI reset */
2626 + MCF_SSI_CR &= ~MCF_SSI_CR_SSI_EN; /* disable SSI module */
2627 +
2628 + /* SSI module uses internal CPU clock */
2629 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSISRC;
2630 +
2631 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSIPUE;
2632 + MCF_CCM_MISCCR |= MCF_CCM_MISCCR_SSIPUS_UP;
2633 +
2634 + MCF_SSI_CR = 0
2635 + | MCF_SSI_CR_CIS
2636 + | MCF_SSI_CR_TCH /* Enable two channel mode */
2637 + | MCF_SSI_CR_MCE /* Set clock out on SSI_MCLK pin */
2638 + | MCF_SSI_CR_I2S_MASTER /* Set I2S master mode */
2639 + | MCF_SSI_CR_SYN /* Enable synchronous mode */
2640 + | MCF_SSI_CR_NET
2641 + ;
2642 +
2643 + MCF_SSI_TCR = 0
2644 + | MCF_SSI_TCR_TXDIR /* internally generated bit clock */
2645 + | MCF_SSI_TCR_TFDIR /* internally generated frame sync */
2646 + | MCF_SSI_TCR_TSCKP /* Clock data on falling edge of bit clock */
2647 + | MCF_SSI_TCR_TFSI /* Frame sync active low */
2648 + | MCF_SSI_TCR_TEFS /* TX frame sync 1 bit before data */
2649 + | MCF_SSI_TCR_TFEN0 /* TX FIFO 0 enabled */
2650 + | MCF_SSI_TCR_TFEN1 /* TX FIFO 1 enabled */
2651 + | MCF_SSI_TCR_TXBIT0
2652 + ;
2653 +
2654 + MCF_SSI_CCR = MCF_SSI_CCR_WL(7) /* 16 bit word length */
2655 + | MCF_SSI_CCR_DC(1) /* Frame rate divider */
2656 + | MCF_SSI_CCR_PM(0)
2657 + | MCF_SSI_CCR_DIV2
2658 + ;
2659 +
2660 + MCF_SSI_FCSR = 0
2661 + | MCF_SSI_FCSR_TFWM0(0)
2662 + | MCF_SSI_FCSR_TFWM1(0)
2663 + ;
2664 +
2665 + MCF_SSI_IER = 0 // interrupts
2666 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
2667 + | MCF_SSI_IER_TIE /* transmit interrupts */
2668 + | MCF_SSI_IER_TFE0 /* transmit FIFO 0 empty */
2669 + | MCF_SSI_IER_TFE1 /* transmit FIFO 1 empty */
2670 +#else
2671 + | MCF_SSI_IER_TDMAE /* DMA request enabled */
2672 + | MCF_SSI_IER_TFE0 /* transmit FIFO 0 empty */
2673 + | MCF_SSI_IER_TFE1 /* transmit FIFO 1 empty */
2674 +#endif
2675 + ;
2676 +
2677 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
2678 + /* enable IRQ: SSI interrupt */
2679 + MCF_INTC1_ICR(M5445x_AUDIO_IRQ_SOURCE) = M5445x_AUDIO_IRQ_LEVEL;
2680 + MCF_INTC1_CIMR = M5445x_AUDIO_IRQ_SOURCE;
2681 +#endif
2682 +}
2683 +
2684 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
2685 +/* interrupt for SSI */
2686 +static int ssi_audio_isr(int irq, void *dev_id)
2687 +{
2688 + unsigned long *bp;
2689 +
2690 + if (audio_txbusy==0) {
2691 + return IRQ_HANDLED;
2692 + }
2693 +
2694 + spin_lock(&(audio_device->lock));
2695 +
2696 + if (audio_start == audio_append) {
2697 + disable_ssi();
2698 + audio_txbusy = 0;
2699 + } else {
2700 + if (MCF_SSI_ISR & (MCF_SSI_ISR_TFE0|MCF_SSI_ISR_TFE1)) {
2701 + bp = (unsigned long *) &audio_device->audio_buf[audio_start];
2702 + if (audio_device->channel) {
2703 + MCF_SSI_TX1 = *bp;
2704 + audio_device->channel = 0;
2705 + } else {
2706 + MCF_SSI_TX0 = *bp;
2707 + audio_device->channel = 1;
2708 + }
2709 + audio_start += 4;
2710 + if (audio_start >= BUFSIZE)
2711 + audio_start = 0;
2712 + }
2713 + }
2714 +
2715 + spin_unlock(&(audio_device->lock));
2716 +
2717 + return IRQ_HANDLED;
2718 +}
2719 +#endif
2720 +
2721 +/* Set initial driver playback defaults. */
2722 +static void init_driver_variables(void)
2723 +{
2724 + audio_device->speed = 44100;
2725 + audio_device->format = AFMT_S16_LE;
2726 + audio_device->bits = 16;
2727 + audio_device->stereo = 1;
2728 + audio_device->ssi_enabled = 0;
2729 +
2730 + audio_start = 0;
2731 + audio_count = 0;
2732 + audio_append = 0;
2733 + audio_appstart = 0;
2734 + audio_txbusy = 0;
2735 + audio_device->dmaing = 0;
2736 +}
2737 +
2738 +/* open audio device */
2739 +static int ssi_audio_open(struct inode *inode, struct file *filp)
2740 +{
2741 +#ifdef AUDIO_DEBUG
2742 + printk(DRIVER_NAME ":ssi_audio_open()\n");
2743 +#endif
2744 +
2745 + if (audio_device==NULL) return (-ENODEV);
2746 +
2747 + if (audio_device->isopen)
2748 + return(-EBUSY);
2749 +
2750 + spin_lock(&(audio_device->lock));
2751 +
2752 + audio_device->isopen = 1;
2753 +
2754 + init_driver_variables();
2755 + init_ssi();
2756 + init_audio_codec();
2757 +
2758 + spin_unlock(&(audio_device->lock));
2759 +
2760 + udelay(100);
2761 +
2762 + return 0;
2763 +}
2764 +
2765 +/* close audio device */
2766 +static int ssi_audio_close(struct inode *inode, struct file *filp)
2767 +{
2768 +#ifdef AUDIO_DEBUG
2769 + printk(DRIVER_NAME ":ssi_audio_close()\n");
2770 +#endif
2771 +
2772 + if (audio_device==NULL) return (-ENODEV);
2773 +
2774 + ssi_audio_txdrain();
2775 +
2776 + spin_lock(&(audio_device->lock));
2777 +
2778 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
2779 + stop_dma();
2780 +#endif
2781 + disable_ssi();
2782 + codec_reset();
2783 + init_driver_variables();
2784 + audio_device->isopen = 0;
2785 +
2786 + spin_unlock(&(audio_device->lock));
2787 + return 0;
2788 +}
2789 +
2790 +/* write to audio device */
2791 +static ssize_t ssi_audio_write(struct file *filp, const char *buf, size_t count, loff_t *ppos)
2792 +{
2793 + unsigned long *dp, *buflp;
2794 + unsigned short *bufwp;
2795 + unsigned char *bufbp;
2796 + unsigned int slen, bufcnt, i, s, e;
2797 +
2798 +#ifdef AUDIO_DEBUG
2799 + printk(DRIVER_NAME ":ssi_audio_write(buf=%x,count=%d)\n", (int) buf, count);
2800 +#endif
2801 +
2802 + if (audio_device==NULL) return (-ENODEV);
2803 +
2804 + if (count <= 0)
2805 + return 0;
2806 +
2807 + spin_lock(&(audio_device->lock));
2808 +
2809 + buflp = (unsigned long *) buf;
2810 + bufwp = (unsigned short *) buf;
2811 + bufbp = (unsigned char *) buf;
2812 +
2813 + bufcnt = count & ~0x3;
2814 +
2815 + bufcnt <<= 1;
2816 + if (audio_device->stereo == 0)
2817 + bufcnt <<= 1;
2818 + if (audio_device->bits == 8)
2819 + bufcnt <<= 1;
2820 +
2821 +tryagain:
2822 + /*
2823 + * Get a snapshot of buffer, so we can figure out how
2824 + * much data we can fit in...
2825 + */
2826 + s = audio_start;
2827 + e = audio_append;
2828 + dp = (unsigned long *) &(audio_device->audio_buf[e]);
2829 +
2830 + slen = ((s > e) ? (s - e) : (BUFSIZE - (e - s))) - 4;
2831 + if (slen > bufcnt)
2832 + slen = bufcnt;
2833 + if ((BUFSIZE - e) < slen)
2834 + slen = BUFSIZE - e;
2835 +
2836 + if (slen == 0) {
2837 + if (signal_pending(current))
2838 + return(-ERESTARTSYS);
2839 + set_current_state(TASK_INTERRUPTIBLE);
2840 + schedule_timeout(1);
2841 + goto tryagain;
2842 + }
2843 +
2844 + /* For DMA we need to have data as 32 bit
2845 + values (since SSI TX register is 32 bit).
2846 + So, the incomming 16 bit data must be put to buffer as 32 bit values.
2847 + Also, the endianess is converted if needed
2848 + */
2849 + if (audio_device->stereo) {
2850 + if (audio_device->bits == 16) {
2851 + if (audio_device->format==AFMT_S16_LE) {
2852 + /*- convert endianess, probably could be done by SSI also */
2853 + for (i = 0; (i < slen); i += 4) {
2854 + unsigned short val = le16_to_cpu((*bufwp++));
2855 + *dp++ = val;
2856 + }
2857 + } else {
2858 + for (i = 0; (i < slen); i += 4) {
2859 + *dp++ = *bufwp++;
2860 + }
2861 + }
2862 + } else {
2863 + for (i = 0; (i < slen); i += 4) {
2864 + *dp = (((unsigned long) *bufbp++) << 24);
2865 + *dp++ |= (((unsigned long) *bufbp++) << 8);
2866 + }
2867 + }
2868 + } else {
2869 + if (audio_device->bits == 16) {
2870 + for (i = 0; (i < slen); i += 4) {
2871 + *dp++ = (((unsigned long)*bufwp)<<16) | *bufwp;
2872 + bufwp++;
2873 + }
2874 + } else {
2875 + for (i = 0; (i < slen); i += 4) {
2876 + *dp++ = (((unsigned long) *bufbp) << 24) |
2877 + (((unsigned long) *bufbp) << 8);
2878 + bufbp++;
2879 + }
2880 + }
2881 + }
2882 +
2883 + e += slen;
2884 + if (e >= BUFSIZE)
2885 + e = 0;
2886 + audio_append = e;
2887 +
2888 + /* If not outputing audio, then start now */
2889 + if (audio_txbusy == 0) {
2890 + audio_txbusy++;
2891 + audio_device->channel = 0;
2892 + enable_ssi();
2893 +#ifdef CONFIG_SSIAUDIO_USE_EDMA
2894 + ssi_audio_dmabuf(); /* start first DMA transfer */
2895 +#endif
2896 + }
2897 +
2898 + bufcnt -= slen;
2899 +
2900 + if (bufcnt > 0)
2901 + goto tryagain;
2902 +
2903 + spin_unlock(&(audio_device->lock));
2904 +
2905 + return count;
2906 +}
2907 +
2908 +/* ioctl: control the driver */
2909 +static int ssi_audio_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
2910 +{
2911 + long val;
2912 + int rc = 0;
2913 +
2914 +#ifdef AUDIO_DEBUG
2915 + printk(DRIVER_NAME ":ssi_audio_ioctl(cmd=%x,arg=%x)\n", (int) cmd, (int) arg);
2916 +#endif
2917 +
2918 + if (audio_device==NULL) return (-ENODEV);
2919 +
2920 + switch (cmd) {
2921 +
2922 + case SNDCTL_DSP_SPEED:
2923 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
2924 + get_user(val, (unsigned long *) arg);
2925 +#ifdef AUDIO_DEBUG
2926 + printk(DRIVER_NAME ":ssi_audio_ioctl: SNDCTL_DSP_SPEED: %ld\n", val);
2927 +#endif
2928 + ssi_audio_txdrain();
2929 + audio_device->speed = val;
2930 + init_audio_codec();
2931 + } else {
2932 + rc = -EINVAL;
2933 + }
2934 + break;
2935 +
2936 + case SNDCTL_DSP_SAMPLESIZE:
2937 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
2938 + get_user(val, (unsigned long *) arg);
2939 + ssi_audio_txdrain();
2940 + ssi_audio_setsamplesize(val);
2941 + } else {
2942 + rc = -EINVAL;
2943 + }
2944 + break;
2945 +
2946 + case SNDCTL_DSP_STEREO:
2947 + if (access_ok(VERIFY_READ, (void *) arg, sizeof(val))) {
2948 + get_user(val, (unsigned long *) arg);
2949 + ssi_audio_txdrain();
2950 + audio_device->stereo = val;
2951 + } else {
2952 + rc = -EINVAL;
2953 + }
2954 + break;
2955 +
2956 + case SNDCTL_DSP_GETBLKSIZE:
2957 + if (access_ok(VERIFY_WRITE, (void *) arg, sizeof(long)))
2958 + put_user(BUFSIZE, (long *) arg);
2959 + else
2960 + rc = -EINVAL;
2961 + break;
2962 +
2963 + case SNDCTL_DSP_SYNC:
2964 + ssi_audio_txdrain();
2965 + break;
2966 +
2967 + default:
2968 + rc = -EINVAL;
2969 + break;
2970 + }
2971 +
2972 + return rc;
2973 +}
2974 +
2975 +/****************************************************************************/
2976 +
2977 +struct file_operations ssi_audio_fops = {
2978 + open: ssi_audio_open, /* open */
2979 + release: ssi_audio_close, /* close */
2980 + write: ssi_audio_write, /* write */
2981 + ioctl: ssi_audio_ioctl, /* ioctl */
2982 +};
2983 +
2984 +/* initialize audio driver */
2985 +static int __devinit ssi_audio_probe(struct spi_device *spi)
2986 +{
2987 + struct ssi_audio *audio;
2988 + int err;
2989 +
2990 +#ifdef AUDIO_DEBUG
2991 + printk(DRIVER_NAME": probe\n");
2992 +#endif
2993 +
2994 + if (!spi->irq) {
2995 + dev_dbg(&spi->dev, "no IRQ?\n");
2996 + return -ENODEV;
2997 + }
2998 +
2999 + /* don't exceed max specified sample rate */
3000 + if (spi->max_speed_hz > MAX_SPEED_HZ) {
3001 + dev_dbg(&spi->dev, "f(sample) %d KHz?\n",
3002 + (spi->max_speed_hz)/1000);
3003 + return -EINVAL;
3004 + }
3005 +
3006 + /* register charcter device */
3007 + if (register_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME, &ssi_audio_fops) < 0) {
3008 + printk(KERN_WARNING DRIVER_NAME ": failed to register major %d\n", SOUND_MAJOR);
3009 + dev_dbg(&spi->dev, DRIVER_NAME ": failed to register major %d\n", SOUND_MAJOR);
3010 + return -ENODEV;
3011 + }
3012 +
3013 + audio = kzalloc(sizeof(struct ssi_audio), GFP_KERNEL);
3014 + if (!audio) {
3015 + err = -ENOMEM;
3016 + goto err_out;
3017 + }
3018 +
3019 + /* DMA buffer must be from GFP_DMA zone, so it will not be cached */
3020 + audio->audio_buf = kmalloc(BUFSIZE, GFP_DMA);
3021 + if (audio->audio_buf == NULL) {
3022 + dev_dbg(&spi->dev, DRIVER_NAME ": failed to allocate DMA[%d] buffer\n", BUFSIZE);
3023 + err = -ENOMEM;
3024 + goto err_free_mem;
3025 + }
3026 +
3027 + audio_device = audio;
3028 +
3029 + dev_set_drvdata(&spi->dev, audio);
3030 + spi->dev.power.power_state = PMSG_ON;
3031 +
3032 + audio->spi = spi;
3033 +
3034 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
3035 + if (request_irq(spi->irq, ssi_audio_isr, SA_INTERRUPT, spi->dev.bus_id, audio)) {
3036 + dev_dbg(&spi->dev, "irq %d busy?\n", spi->irq);
3037 + err = -EBUSY;
3038 + goto err_free_mem;
3039 + }
3040 +
3041 +#else
3042 + /* request 2 eDMA channels since two channel output mode is used */
3043 + if (request_edma_channel(DMA_TCD,
3044 + ssi_audio_dma_handler_empty,
3045 + NULL,
3046 + audio,
3047 + &(audio_device->lock),
3048 + DRIVER_NAME
3049 + )!=0)
3050 + {
3051 + dev_dbg(&spi->dev, "DMA channel %d busy?\n", DMA_TCD);
3052 + err = -EBUSY;
3053 + goto err_free_mem;
3054 + }
3055 + if (request_edma_channel(DMA_TCD2,
3056 + ssi_audio_dma_handler,
3057 + NULL,
3058 + audio,
3059 + &(audio_device->lock),
3060 + DRIVER_NAME
3061 + )!=0)
3062 + {
3063 + dev_dbg(&spi->dev, "DMA channel %d busy?\n", DMA_TCD2);
3064 + err = -EBUSY;
3065 + goto err_free_mem;
3066 + }
3067 +
3068 +#endif
3069 + chip_init();
3070 + printk(DRIVER_NAME ": Probed successfully\n");
3071 +
3072 + return 0;
3073 +
3074 + err_free_mem:
3075 + kfree(audio);
3076 + audio_device = NULL;
3077 + err_out:
3078 + unregister_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME);
3079 + return err;
3080 +}
3081 +
3082 +static int __devexit ssi_audio_remove(struct spi_device *spi)
3083 +{
3084 + struct ssi_audio *audio = dev_get_drvdata(&spi->dev);
3085 +
3086 + ssi_audio_txdrain();
3087 +#ifndef CONFIG_SSIAUDIO_USE_EDMA
3088 + free_irq(spi->irq, audio);
3089 +#else
3090 + free_edma_channel(DMA_TCD, audio);
3091 + free_edma_channel(DMA_TCD2, audio);
3092 +#endif
3093 + kfree(audio->audio_buf);
3094 + kfree(audio);
3095 + audio_device = NULL;
3096 + unregister_chrdev(SOUND_MAJOR, SOUND_DEVICE_NAME);
3097 + dev_dbg(&spi->dev, "unregistered audio\n");
3098 + return 0;
3099 +}
3100 +
3101 +static int ssi_audio_suspend(struct spi_device *spi, pm_message_t message) {
3102 + return 0;
3103 +}
3104 +
3105 +static int ssi_audio_resume(struct spi_device *spi) {
3106 + return 0;
3107 +}
3108 +
3109 +static struct spi_driver ssi_audio_driver = {
3110 + .driver = {
3111 + .name = DRIVER_NAME,
3112 + .bus = &spi_bus_type,
3113 + .owner = THIS_MODULE,
3114 + },
3115 + .probe = ssi_audio_probe,
3116 + .remove = __devexit_p(ssi_audio_remove),
3117 + .suspend = ssi_audio_suspend,
3118 + .resume = ssi_audio_resume,
3119 +};
3120 +
3121 +static int __init ssi_audio_init(void)
3122 +{
3123 + return spi_register_driver(&ssi_audio_driver);
3124 +}
3125 +module_init(ssi_audio_init);
3126 +
3127 +static void __exit ssi_audio_exit(void)
3128 +{
3129 + spi_unregister_driver(&ssi_audio_driver);
3130 +}
3131 +module_exit(ssi_audio_exit);
3132 +
3133 +MODULE_DESCRIPTION("SSI/I2S Audio Driver");
3134 +MODULE_LICENSE("GPL");
3135 --- a/include/asm-m68k/coldfire_edma.h
3136 +++ b/include/asm-m68k/coldfire_edma.h
3137 @@ -1,39 +1,102 @@
3138 +/*
3139 + * coldfire_edma.h - eDMA driver for Coldfire MCF5445x
3140 + *
3141 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
3142 + *
3143 + * Copyright Freescale Semiconductor, Inc. 2007
3144 + *
3145 + * This program is free software; you can redistribute it and/or modify it
3146 + * under the terms of the GNU General Public License as published by the
3147 + * Free Software Foundation; either version 2 of the License, or (at your
3148 + * option) any later version.
3149 + */
3150 +
3151 #ifndef _LINUX_COLDFIRE_DMA_H
3152 #define _LINUX_COLDFIRE_DMA_H
3153
3154 #include <linux/interrupt.h>
3155 +#include <asm/mcf5445x_edma.h>
3156
3157 -#define EDMA_DRIVER_NAME "ColdFire-eDMA"
3158 -#define DMA_DEV_MINOR 1
3159 +#define EDMA_DRIVER_NAME "ColdFire-eDMA"
3160 +#define DMA_DEV_MINOR 1
3161
3162 #define EDMA_INT_CHANNEL_BASE 8
3163 #define EDMA_INT_CONTROLLER_BASE 64
3164 #define EDMA_CHANNELS 16
3165 -
3166 +
3167 #define EDMA_IRQ_LEVEL 5
3168 -
3169 +
3170 typedef irqreturn_t (*edma_irq_handler)(int, void *);
3171 typedef void (*edma_error_handler)(int, void *);
3172 -
3173 +
3174 +/* Setup transfer control descriptor (TCD)
3175 + * channel - descriptor number
3176 + * source - source address
3177 + * dest - destination address
3178 + * attr - attributes
3179 + * soff - source offset
3180 + * nbytes - number of bytes to be transfered in minor loop
3181 + * slast - last source address adjustment
3182 + * citer - major loop count
3183 + * biter - beggining minor loop count
3184 + * doff - destination offset
3185 + * dlast_sga - last destination address adjustment
3186 + * major_int - generate interrupt after each major loop
3187 + * disable_req - disable DMA request after major loop
3188 + */
3189 void set_edma_params(int channel, u32 source, u32 dest,
3190 - u32 attr, u32 soff, u32 nbytes, u32 slast,
3191 - u32 citer, u32 biter, u32 doff, u32 dlast_sga);
3192 -
3193 -void start_edma_transfer(int channel, int major_int);
3194 -
3195 -void stop_edma_transfer(int channel);
3196 -
3197 -void confirm_edma_interrupt_handled(int channel);
3198 -
3199 + u32 attr, u32 soff, u32 nbytes, u32 slast,
3200 + u32 citer, u32 biter, u32 doff, u32 dlast_sga,
3201 + int major_int, int disable_req);
3202 +
3203 +/* Starts eDMA transfer on specified channel
3204 + * channel - eDMA TCD number
3205 + */
3206 +static inline void start_edma_transfer(int channel)
3207 +{
3208 + MCF_EDMA_SERQ = channel;
3209 + MCF_EDMA_SSRT = channel;
3210 +}
3211 +
3212 +/* Stops eDMA transfer
3213 + * channel - eDMA TCD number
3214 + */
3215 +static inline void stop_edma_transfer(int channel)
3216 +{
3217 + MCF_EDMA_CINT = channel;
3218 + MCF_EDMA_CERQ = channel;
3219 +}
3220 +
3221 +
3222 +/* Confirm that interrupt has been handled
3223 + * channel - eDMA TCD number
3224 + */
3225 +static inline void confirm_edma_interrupt_handled(int channel)
3226 +{
3227 + MCF_EDMA_CINT = channel;
3228 +}
3229 +
3230 +/* Initialize eDMA controller */
3231 void init_edma(void);
3232 -
3233 -int request_edma_channel(int channel,
3234 - edma_irq_handler handler,
3235 - edma_error_handler error_handler,
3236 - void *dev,
3237 - spinlock_t *lock,
3238 - const char *device_id);
3239 -
3240 +
3241 +/* Request eDMA channel:
3242 + * channel - eDMA TCD number
3243 + * handler - channel IRQ callback
3244 + * error_handler - error interrupt handler callback for channel
3245 + * dev - device
3246 + * lock - spinlock to be locked (can be NULL)
3247 + * device_id - device driver name for proc file system output
3248 + */
3249 +int request_edma_channel(int channel,
3250 + edma_irq_handler handler,
3251 + edma_error_handler error_handler,
3252 + void *dev,
3253 + spinlock_t *lock,
3254 + const char *device_id);
3255 +
3256 +/* Free eDMA channel
3257 + * channel - eDMA TCD number
3258 + * dev - device
3259 + */
3260 int free_edma_channel(int channel, void *dev);
3261 -
3262 #endif
3263 --- /dev/null
3264 +++ b/include/linux/spi/mcfqspi.h
3265 @@ -0,0 +1,80 @@
3266 +/****************************************************************************/
3267 +
3268 +/*
3269 + * mcfqspi.c - Master QSPI controller for the ColdFire processors
3270 + *
3271 + * (C) Copyright 2005, Intec Automation,
3272 + * Mike Lavender (mike@steroidmicros)
3273 + *
3274 +
3275 + This program is free software; you can redistribute it and/or modify
3276 + it under the terms of the GNU General Public License as published by
3277 + the Free Software Foundation; either version 2 of the License, or
3278 + (at your option) any later version.
3279 +
3280 + This program is distributed in the hope that it will be useful,
3281 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3282 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3283 + GNU General Public License for more details.
3284 +
3285 + You should have received a copy of the GNU General Public License
3286 + along with this program; if not, write to the Free Software
3287 + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
3288 +/* ------------------------------------------------------------------------- */
3289 +
3290 +#ifndef MCFQSPI_H_
3291 +#define MCFQSPI_H_
3292 +
3293 +#define QSPI_CS_INIT 0x01
3294 +#define QSPI_CS_ASSERT 0x02
3295 +#define QSPI_CS_DROP 0x04
3296 +
3297 +#define QSPIIOCS_DOUT_HIZ 1 /* QMR[DOHIE] set hi-z dout between transfers */
3298 +#define QSPIIOCS_BITS 2 /* QMR[BITS] set transfer size */
3299 +#define QSPIIOCG_BITS 3 /* QMR[BITS] get transfer size */
3300 +#define QSPIIOCS_CPOL 4 /* QMR[CPOL] set SCK inactive state */
3301 +#define QSPIIOCS_CPHA 5 /* QMR[CPHA] set SCK phase, 1=rising edge */
3302 +#define QSPIIOCS_BAUD 6 /* QMR[BAUD] set SCK baud rate divider */
3303 +#define QSPIIOCS_QCD 7 /* QDLYR[QCD] set start delay */
3304 +#define QSPIIOCS_DTL 8 /* QDLYR[DTL] set after delay */
3305 +#define QSPIIOCS_CONT 9 /* continuous CS asserted during transfer */
3306 +#define QSPIIOCS_READDATA 10 /* set data send during read */
3307 +#define QSPIIOCS_ODD_MOD 11 /* if length of buffer is a odd number, 16-bit transfers */
3308 + /* are finalized with a 8-bit transfer */
3309 +#define QSPIIOCS_DSP_MOD 12 /* transfers are bounded to 15/30 bytes (a multiple of 3 bytes = 1 DSPword) */
3310 +#define QSPIIOCS_POLL_MOD 13 /* driver uses polling instead of interrupts */
3311 +
3312 +#define QSPIIOCS_SET_CSIV 14 /* sets CSIV flag (cs inactive level) */
3313 +
3314 +#ifdef CONFIG_M520x
3315 +#undef MCF_GPIO_PAR_QSPI
3316 +#define MCF_GPIO_PAR_QSPI (0xA4034)
3317 +#endif
3318 +
3319 +struct coldfire_spi_master {
3320 + u16 bus_num;
3321 + u16 num_chipselect;
3322 + u8 irq_source;
3323 + u32 irq_vector;
3324 + u32 irq_mask;
3325 + u8 irq_lp;
3326 + u8 par_val;
3327 + u16 par_val16;
3328 + void (*cs_control)(u8 cs, u8 command);
3329 +};
3330 +
3331 +
3332 +struct coldfire_spi_chip {
3333 + u8 mode;
3334 + u8 bits_per_word;
3335 + u8 del_cs_to_clk;
3336 + u8 del_after_trans;
3337 + u16 void_write_data;
3338 +};
3339 +
3340 +typedef struct qspi_read_data {
3341 + __u32 length;
3342 + __u8 *buf; /* data to send during read */
3343 + unsigned int loop : 1;
3344 +} qspi_read_data;
3345 +#endif /*MCFQSPI_H_*/
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