2 * ADMTEK Adm6996 switch configuration module
4 * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
26 #include <linux/if_arp.h>
27 #include <linux/sockios.h>
28 #include <linux/delay.h>
29 #include <asm/uaccess.h>
31 #include "switch-core.h"
34 #define DRIVER_NAME "adm6996"
42 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
43 MODULE_LICENSE("GPL");
44 MODULE_PARM(eecs
, "i");
45 MODULE_PARM(eesk
, "i");
46 MODULE_PARM(eedi
, "i");
47 MODULE_PARM(eerc
, "i");
48 MODULE_PARM(force
, "i");
50 /* Minimum timing constants */
51 #define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
52 #define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */
53 #define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */
55 /* Handy macros for writing fixed length values */
56 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
57 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
58 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
61 extern int getintvar(char **vars
, char *name
);
64 static void adm_write(int cs
, char *buf
, unsigned int bits
)
66 int i
, len
= (bits
+ 7) / 8;
69 gpioout(eecs
, (cs
? eecs
: 0));
70 udelay(EECK_EDGE_TIME
);
72 /* Byte assemble from MSB to LSB */
73 for (i
= 0; i
< len
; i
++) {
74 /* Bit bang from MSB to LSB */
75 for (mask
= 0x80; mask
&& bits
> 0; mask
>>= 1, bits
--) {
78 udelay(EECK_EDGE_TIME
);
80 /* Output on rising edge */
81 gpioout(eedi
, ((mask
& buf
[i
]) ? eedi
: 0));
82 udelay(EEDI_SETUP_TIME
);
86 udelay(EECK_EDGE_TIME
);
92 udelay(EECK_EDGE_TIME
);
99 static void adm_read(int cs
, char *buf
, unsigned int bits
)
101 int i
, len
= (bits
+ 7) / 8;
104 gpioout(eecs
, (cs
? eecs
: 0));
105 udelay(EECK_EDGE_TIME
);
107 /* Byte assemble from MSB to LSB */
108 for (i
= 0; i
< len
; i
++) {
111 /* Bit bang from MSB to LSB */
112 for (mask
= 0x80, byte
= 0; mask
&& bits
> 0; mask
>>= 1, bits
--) {
117 udelay(EECK_EDGE_TIME
);
119 /* Input on rising edge */
126 udelay(EECK_EDGE_TIME
);
134 udelay(EECK_EDGE_TIME
);
141 /* Enable outputs with specified value to the chip */
142 static void adm_enout(__u8 pins
, __u8 val
)
144 /* Prepare GPIO output value */
147 /* Enable GPIO outputs */
148 gpioouten(pins
, pins
);
149 udelay(EECK_EDGE_TIME
);
153 /* Disable outputs to the chip */
154 static void adm_disout(__u8 pins
)
156 /* Disable GPIO outputs */
158 udelay(EECK_EDGE_TIME
);
162 /* Advance clock(s) */
163 static void adm_adclk(int clocks
)
166 for (i
= 0; i
< clocks
; i
++) {
169 udelay(EECK_EDGE_TIME
);
173 udelay(EECK_EDGE_TIME
);
177 static __u32
adm_rreg(__u8 table
, __u8 addr
)
179 /* cmd: 01 10 T DD R RRRRRR */
181 0xFF, 0xFF, 0xFF, 0xFF,
182 (0x06 << 4) | ((table
& 0x01) << 3 | (addr
&64)>>6),
188 /* Enable GPIO outputs with all pins to 0 */
189 adm_enout((__u8
)(eecs
| eesk
| eedi
), 0);
191 adm_write(0, bits
, 46);
192 adm_disout((__u8
)(eedi
));
194 adm_read (0, rbits
, 32);
196 /* Extra clock(s) required per datasheet */
199 /* Disable GPIO outputs */
200 adm_disout((__u8
)(eecs
| eesk
));
202 if (!table
) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
203 return (addr
& 0x01 ? (rbits
[0]<<8) | rbits
[1] : (rbits
[2]<<8) | (rbits
[3]));
205 return (rbits
[0]<<24) | (rbits
[1]<<16) | (rbits
[2]<<8) | rbits
[3];
210 /* Write chip configuration register */
211 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
213 adm_wreg(__u8 addr
, __u16 val
)
215 /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
217 (0x05 << 5) | (addr
>> 3),
218 (addr
<< 5) | (__u8
)(val
>> 11),
223 /* Enable GPIO outputs with all pins to 0 */
224 adm_enout((__u8
)(eecs
| eesk
| eedi
), 0);
226 /* Write cmd. Total 27 bits */
227 adm_write(1, bits
, 27);
229 /* Extra clock(s) required per datasheet */
232 /* Disable GPIO outputs */
233 adm_disout((__u8
)(eecs
| eesk
| eedi
));
237 /* Port configuration registers */
238 static int port_conf
[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
240 /* Bits in VLAN port mapping */
241 static int vlan_ports
[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
243 static int handle_vlan_port_read(void *driver
, char *buf
, int nr
)
245 int ports
, i
, c
, len
= 0;
247 if ((nr
< 0) || (nr
> 15))
250 /* Get VLAN port map */
251 ports
= adm_rreg(0, 0x13 + nr
);
253 for (i
= 0; i
<= 5; i
++) {
254 if (ports
& vlan_ports
[i
]) {
255 c
= adm_rreg(0, port_conf
[i
]);
256 len
+= sprintf(buf
+ len
, (c
& (1 << 4) ? "%dt\t" : (i
== 5 ? "%du\t" : "%d\t")), i
);
259 len
+= sprintf(buf
+ len
, "\n");
264 static int handle_vlan_port_write(void *driver
, char *buf
, int nr
)
267 switch_driver
*d
= (switch_driver
*) driver
;
268 switch_vlan_config
*c
= switch_parse_vlan(d
, buf
);
273 ports
= adm_rreg(0, 0x13 + nr
);
274 for (i
= 0; i
< d
->ports
; i
++) {
275 if (c
->port
& (1 << i
)) {
276 ports
|= vlan_ports
[i
];
278 cfg
= adm_rreg(0, port_conf
[i
]);
281 if (c
->untag
& (1 << i
))
286 if ((c
->untag
| c
->pvid
) & (1 << i
)) {
287 cfg
= (cfg
& ~(0xf << 10)) | (nr
<< 10);
290 adm_wreg(port_conf
[i
], (__u16
) cfg
);
292 ports
&= ~(vlan_ports
[i
]);
295 adm_wreg(0x13 + nr
, (__u16
) ports
);
300 static int handle_port_enable_read(void *driver
, char *buf
, int nr
)
302 return sprintf(buf
, "%d\n", ((adm_rreg(0, port_conf
[nr
]) & (1 << 5)) ? 0 : 1));
305 static int handle_port_enable_write(void *driver
, char *buf
, int nr
)
307 int reg
= adm_rreg(0, port_conf
[nr
]);
311 else if (buf
[0] == '1')
315 adm_wreg(port_conf
[nr
], (__u16
) reg
);
319 static int handle_port_media_read(void *driver
, char *buf
, int nr
)
323 int reg
= adm_rreg(0, port_conf
[nr
]);
326 media
|= SWITCH_MEDIA_AUTO
;
328 media
|= SWITCH_MEDIA_100
;
330 media
|= SWITCH_MEDIA_FD
;
332 len
= switch_print_media(buf
, media
);
333 return len
+ sprintf(buf
+ len
, "\n");
336 static int handle_port_media_write(void *driver
, char *buf
, int nr
)
338 int media
= switch_parse_media(buf
);
339 int reg
= adm_rreg(0, port_conf
[nr
]);
344 reg
&= ~((1 << 1) | (1 << 2) | (1 << 3));
345 if (media
& SWITCH_MEDIA_AUTO
)
347 if (media
& SWITCH_MEDIA_100
)
349 if (media
& SWITCH_MEDIA_FD
)
352 adm_wreg(port_conf
[nr
], reg
);
357 static int handle_vlan_enable_read(void *driver
, char *buf
, int nr
)
359 return sprintf(buf
, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
362 static int handle_vlan_enable_write(void *driver
, char *buf
, int nr
)
364 int reg
= adm_rreg(0, 0x11);
368 else if (buf
[0] == '0')
372 adm_wreg(0x11, (__u16
) reg
);
376 static int handle_reset(void *driver
, char *buf
, int nr
)
381 * Reset sequence: RC high->low(100ms)->high(30ms)
383 * WAR: Certain boards don't have the correct power on
384 * reset logic therefore we must explicitly perform the
385 * sequence in software.
387 /* Keep RC high for at least 20ms */
388 adm_enout(eerc
, eerc
);
389 for (i
= 0; i
< 20; i
++)
391 /* Keep RC low for at least 100ms */
393 for (i
= 0; i
< 100; i
++)
395 /* Set default configuration */
396 adm_enout((__u8
)(eesk
| eedi
), eesk
);
397 /* Keep RC high for at least 30ms */
398 adm_enout(eerc
, eerc
);
399 for (i
= 0; i
< 30; i
++)
401 /* Leave RC high and disable GPIO outputs */
402 adm_disout((__u8
)(eecs
| eesk
| eedi
));
404 /* set up initial configuration for ports */
405 for (i
= 0; i
<= 5; i
++) {
406 int cfg
= 0x8000 | /* Auto MDIX */
407 (((i
== 5) ? 1 : 0) << 4) | /* Tagging */
408 0xf; /* full duplex, 100Mbps, auto neg, flow ctrl */
409 adm_wreg(port_conf
[i
], cfg
);
412 /* vlan mode select register (0x11): vlan on, mac clone */
413 adm_wreg(0x11, 0xff30);
418 static int handle_registers(void *driver
, char *buf
, int nr
)
422 for (i
= 0; i
<= 0x33; i
++) {
423 len
+= sprintf(buf
+ len
, "0x%02x: 0x%04x\n", i
, adm_rreg(0, i
));
429 static int handle_counters(void *driver
, char *buf
, int nr
)
433 for (i
= 0; i
<= 0x3c; i
++) {
434 len
+= sprintf(buf
+ len
, "0x%02x: 0x%08x\n", i
, adm_rreg(1, i
));
440 static int detect_adm()
444 #if defined(BCMGPIO2) || defined(BCMGPIO)
446 int boardflags
= getintvar(NULL
, "boardflags");
448 extern int boardflags
;
450 if ((boardflags
& 0x80) || force
)
453 printk("BFL_ENETADM not set in boardflags. Use force=1 to ignore.\n");
458 int i
= adm_rreg(0, 0);
459 if ((i
== 0) || (i
== 0xffff)) {
460 printk("No ADM6996 chip detected.\n");
468 static int __init
adm_init()
470 switch_config cfg
[] = {
471 {"registers", handle_registers
, NULL
},
472 {"counters", handle_counters
, NULL
},
473 {"reset", NULL
, handle_reset
},
474 {"enable_vlan", handle_vlan_enable_read
, handle_vlan_enable_write
},
477 switch_config port
[] = {
478 {"enabled", handle_port_enable_read
, handle_port_enable_write
},
479 {"media", handle_port_media_read
, handle_port_media_write
},
482 switch_config vlan
[] = {
483 {"ports", handle_vlan_port_read
, handle_vlan_port_write
},
486 switch_driver driver
= {
492 driver_handlers
: cfg
,
504 return switch_register_driver(&driver
);
507 static void __exit
adm_exit()
509 switch_unregister_driver(DRIVER_NAME
);
513 module_init(adm_init
);
514 module_exit(adm_exit
);
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