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[xburst] Cleanup clock module a bit and replace last users of __cpm_*
[openwrt.git] / target / linux / xburst / files-2.6.32 / drivers / usb / gadget / jz4740_udc.c
1 /*
2 * linux/drivers/usb/gadget/jz4740_udc.c
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 /*
16 * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
17 *
18 * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
19 * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/proc_fs.h>
33 #include <linux/usb.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/clk.h>
36
37 #include <asm/byteorder.h>
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/system.h>
41 #include <asm/mach-jz4740/jz4740.h>
42 #include <asm/mach-jz4740/clock.h>
43
44 #include "jz4740_udc.h"
45
46 #define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
47 #define JZ_REG_UDC_POWER 0x01 /* Power Managemetn 8-bit */
48 #define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
49 #define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
50 #define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
51 #define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
52 #define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
53 #define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
54 #define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
55 #define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
56 #define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
57
58 #define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
59 #define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
60 #define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
61 #define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
62 #define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
63 #define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
64 #define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
65 #define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
66
67 #define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
68
69 #define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
70 #define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
71
72 #define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
73 #define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
74 #define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
75 #define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
76 #define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
77 #define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
78 #define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
79
80 /* Power register bit masks */
81 #define USB_POWER_SUSPENDM 0x01
82 #define USB_POWER_RESUME 0x04
83 #define USB_POWER_HSMODE 0x10
84 #define USB_POWER_HSENAB 0x20
85 #define USB_POWER_SOFTCONN 0x40
86
87 /* Interrupt register bit masks */
88 #define USB_INTR_SUSPEND 0x01
89 #define USB_INTR_RESUME 0x02
90 #define USB_INTR_RESET 0x04
91
92 #define USB_INTR_EP0 0x0001
93 #define USB_INTR_INEP1 0x0002
94 #define USB_INTR_INEP2 0x0004
95 #define USB_INTR_OUTEP1 0x0002
96
97 /* CSR0 bit masks */
98 #define USB_CSR0_OUTPKTRDY 0x01
99 #define USB_CSR0_INPKTRDY 0x02
100 #define USB_CSR0_SENTSTALL 0x04
101 #define USB_CSR0_DATAEND 0x08
102 #define USB_CSR0_SETUPEND 0x10
103 #define USB_CSR0_SENDSTALL 0x20
104 #define USB_CSR0_SVDOUTPKTRDY 0x40
105 #define USB_CSR0_SVDSETUPEND 0x80
106
107 /* Endpoint CSR register bits */
108 #define USB_INCSRH_AUTOSET 0x80
109 #define USB_INCSRH_ISO 0x40
110 #define USB_INCSRH_MODE 0x20
111 #define USB_INCSRH_DMAREQENAB 0x10
112 #define USB_INCSRH_DMAREQMODE 0x04
113 #define USB_INCSR_CDT 0x40
114 #define USB_INCSR_SENTSTALL 0x20
115 #define USB_INCSR_SENDSTALL 0x10
116 #define USB_INCSR_FF 0x08
117 #define USB_INCSR_UNDERRUN 0x04
118 #define USB_INCSR_FFNOTEMPT 0x02
119 #define USB_INCSR_INPKTRDY 0x01
120 #define USB_OUTCSRH_AUTOCLR 0x80
121 #define USB_OUTCSRH_ISO 0x40
122 #define USB_OUTCSRH_DMAREQENAB 0x20
123 #define USB_OUTCSRH_DNYT 0x10
124 #define USB_OUTCSRH_DMAREQMODE 0x08
125 #define USB_OUTCSR_CDT 0x80
126 #define USB_OUTCSR_SENTSTALL 0x40
127 #define USB_OUTCSR_SENDSTALL 0x20
128 #define USB_OUTCSR_FF 0x10
129 #define USB_OUTCSR_DATAERR 0x08
130 #define USB_OUTCSR_OVERRUN 0x04
131 #define USB_OUTCSR_FFFULL 0x02
132 #define USB_OUTCSR_OUTPKTRDY 0x01
133
134 /* Testmode register bits */
135 #define USB_TEST_SE0NAK 0x01
136 #define USB_TEST_J 0x02
137 #define USB_TEST_K 0x04
138 #define USB_TEST_PACKET 0x08
139
140 /* DMA control bits */
141 #define USB_CNTL_ENA 0x01
142 #define USB_CNTL_DIR_IN 0x02
143 #define USB_CNTL_MODE_1 0x04
144 #define USB_CNTL_INTR_EN 0x08
145 #define USB_CNTL_EP(n) ((n) << 4)
146 #define USB_CNTL_BURST_0 (0 << 9)
147 #define USB_CNTL_BURST_4 (1 << 9)
148 #define USB_CNTL_BURST_8 (2 << 9)
149 #define USB_CNTL_BURST_16 (3 << 9)
150
151
152 #ifndef DEBUG
153 # define DEBUG(fmt,args...) do {} while(0)
154 #endif
155 #ifndef DEBUG_EP0
156 # define NO_STATES
157 # define DEBUG_EP0(fmt,args...) do {} while(0)
158 #endif
159 #ifndef DEBUG_SETUP
160 # define DEBUG_SETUP(fmt,args...) do {} while(0)
161 #endif
162
163 static unsigned int udc_debug = 0; /* 0: normal mode, 1: test udc cable type mode */
164
165 module_param(udc_debug, int, 0);
166 MODULE_PARM_DESC(udc_debug, "test udc cable or power type");
167
168 static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
169
170 module_param(use_dma, int, 0);
171 MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
172
173 struct jz4740_udc *the_controller;
174
175 /*
176 * Local declarations.
177 */
178 static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
179 static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
180
181 static void done(struct jz4740_ep *ep, struct jz4740_request *req,
182 int status);
183 static void pio_irq_enable(struct jz4740_ep *ep);
184 static void pio_irq_disable(struct jz4740_ep *ep);
185 static void stop_activity(struct jz4740_udc *dev,
186 struct usb_gadget_driver *driver);
187 static void nuke(struct jz4740_ep *ep, int status);
188 static void flush(struct jz4740_ep *ep);
189 static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
190
191 /*-------------------------------------------------------------------------*/
192
193 /* inline functions of register read/write/set/clear */
194
195 static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
196 {
197 return readb(udc->base + reg);
198 }
199
200 static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
201 {
202 return readw(udc->base + reg);
203 }
204
205 static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
206 {
207 return readl(udc->base + reg);
208 }
209
210 static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
211 {
212 writeb(val, udc->base + reg);
213 }
214
215 static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
216 {
217 writew(val, udc->base + reg);
218 }
219
220 static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
221 {
222 writel(val, udc->base + reg);
223 }
224
225 static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
226 {
227 usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
228 }
229
230 static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
231 {
232 usb_writew(udc, reg, usb_readw(udc, reg) | mask);
233 }
234
235 static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
236 {
237 usb_writel(udc, reg, usb_readl(udc, reg) | mask);
238 }
239
240 static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
241 {
242 usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
243 }
244
245 static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
246 {
247 usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
248 }
249
250 static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
251 {
252 usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
253 }
254
255 /*-------------------------------------------------------------------------*/
256
257 static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
258 {
259 usb_writeb(udc, JZ_REG_UDC_INDEX, index);
260 }
261
262 static inline void jz_udc_select_ep(struct jz4740_ep *ep)
263 {
264 jz_udc_set_index(ep->dev, ep_index(ep));
265 }
266
267 static inline int write_packet(struct jz4740_ep *ep,
268 struct jz4740_request *req, int max)
269 {
270 uint8_t *buf;
271 int length, nlong, nbyte;
272 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
273
274 buf = req->req.buf + req->req.actual;
275 prefetch(buf);
276
277 length = req->req.length - req->req.actual;
278 length = min(length, max);
279 req->req.actual += length;
280
281 DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
282
283 nlong = length >> 2;
284 nbyte = length & 0x3;
285 while (nlong--) {
286 usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
287 buf += 4;
288 }
289 while (nbyte--) {
290 usb_writeb(ep->dev, ep->fifo, *buf++);
291 }
292
293 return length;
294 }
295
296 static inline int read_packet(struct jz4740_ep *ep,
297 struct jz4740_request *req, int count)
298 {
299 uint8_t *buf;
300 int length, nlong, nbyte;
301 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
302
303 buf = req->req.buf + req->req.actual;
304 prefetchw(buf);
305
306 length = req->req.length - req->req.actual;
307 length = min(length, count);
308 req->req.actual += length;
309
310 DEBUG("Read %d, fifo %x\n", length, ep->fifo);
311
312 nlong = length >> 2;
313 nbyte = length & 0x3;
314 while (nlong--) {
315 *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
316 buf += 4;
317 }
318 while (nbyte--) {
319 *buf++ = usb_readb(ep->dev, ep->fifo);
320 }
321
322 return length;
323 }
324
325 /*-------------------------------------------------------------------------*/
326
327 /*
328 * udc_disable - disable USB device controller
329 */
330 static void udc_disable(struct jz4740_udc *dev)
331 {
332 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
333
334 udc_set_address(dev, 0);
335
336 /* Disable interrupts */
337 usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
338 usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
339 usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
340
341 /* Disable DMA */
342 usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
343 usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
344
345 /* Disconnect from usb */
346 usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
347
348 /* Disable the USB PHY */
349 clk_disable(dev->clk);
350
351 dev->ep0state = WAIT_FOR_SETUP;
352 dev->gadget.speed = USB_SPEED_UNKNOWN;
353
354 return;
355 }
356
357 /*
358 * udc_reinit - initialize software state
359 */
360 static void udc_reinit(struct jz4740_udc *dev)
361 {
362 int i;
363 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
364
365 /* device/ep0 records init */
366 INIT_LIST_HEAD(&dev->gadget.ep_list);
367 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
368 dev->ep0state = WAIT_FOR_SETUP;
369
370 for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
371 struct jz4740_ep *ep = &dev->ep[i];
372
373 if (i != 0)
374 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
375
376 INIT_LIST_HEAD(&ep->queue);
377 ep->desc = 0;
378 ep->stopped = 0;
379 ep->pio_irqs = 0;
380 }
381 }
382
383 /* until it's enabled, this UDC should be completely invisible
384 * to any USB host.
385 */
386 static void udc_enable(struct jz4740_udc *dev)
387 {
388 int i;
389 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
390
391 /* UDC state is incorrect - Added by River */
392 if (dev->state != UDC_STATE_ENABLE) {
393 return;
394 }
395
396 dev->gadget.speed = USB_SPEED_UNKNOWN;
397
398 /* Flush FIFO for each */
399 for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
400 struct jz4740_ep *ep = &dev->ep[i];
401
402 jz_udc_set_index(dev, ep_index(ep));
403 flush(ep);
404 }
405
406 /* Set this bit to allow the UDC entering low-power mode when
407 * there are no actions on the USB bus.
408 * UDC still works during this bit was set.
409 */
410 jz4740_clock_udc_enable_auto_suspend();
411
412 /* Enable the USB PHY */
413 clk_enable(dev->clk);
414
415 /* Disable interrupts */
416 /* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
417 usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
418 usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
419
420 /* Enable interrupts */
421 usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
422 usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
423 /* Don't enable rest of the interrupts */
424 /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
425 usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
426
427 /* Enable SUSPEND */
428 /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
429
430 /* Enable HS Mode */
431 usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
432
433 /* Let host detect UDC:
434 * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
435 * transistor on and pull the USBDP pin HIGH.
436 */
437 usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
438
439 return;
440 }
441
442 /*-------------------------------------------------------------------------*/
443
444 /* keeping it simple:
445 * - one bus driver, initted first;
446 * - one function driver, initted second
447 */
448
449 /*
450 * Register entry point for the peripheral controller driver.
451 */
452
453 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
454 {
455 struct jz4740_udc *dev = the_controller;
456 int retval;
457
458 if (!driver || !driver->bind) {
459 return -EINVAL;
460 }
461
462 if (!dev) {
463 return -ENODEV;
464 }
465
466 if (dev->driver) {
467 return -EBUSY;
468 }
469
470 /* hook up the driver */
471 dev->driver = driver;
472 dev->gadget.dev.driver = &driver->driver;
473
474 retval = driver->bind(&dev->gadget);
475 if (retval) {
476 DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
477 driver->driver.name, retval);
478 dev->driver = 0;
479 return retval;
480 }
481
482 /* then enable host detection and ep0; and we're ready
483 * for set_configuration as well as eventual disconnect.
484 */
485 udc_enable(dev);
486
487 DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
488 driver->driver.name);
489
490 return 0;
491 }
492
493 EXPORT_SYMBOL(usb_gadget_register_driver);
494
495 static void stop_activity(struct jz4740_udc *dev,
496 struct usb_gadget_driver *driver)
497 {
498 int i;
499
500 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
501
502 /* don't disconnect drivers more than once */
503 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
504 driver = 0;
505 dev->gadget.speed = USB_SPEED_UNKNOWN;
506
507 /* prevent new request submissions, kill any outstanding requests */
508 for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
509 struct jz4740_ep *ep = &dev->ep[i];
510
511 ep->stopped = 1;
512
513 jz_udc_set_index(dev, ep_index(ep));
514 nuke(ep, -ESHUTDOWN);
515 }
516
517 /* report disconnect; the driver is already quiesced */
518 if (driver) {
519 spin_unlock(&dev->lock);
520 driver->disconnect(&dev->gadget);
521 spin_lock(&dev->lock);
522 }
523
524 /* re-init driver-visible data structures */
525 udc_reinit(dev);
526 }
527
528
529 /*
530 * Unregister entry point for the peripheral controller driver.
531 */
532 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
533 {
534 struct jz4740_udc *dev = the_controller;
535 unsigned long flags;
536 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
537
538 if (!dev)
539 return -ENODEV;
540 if (!driver || driver != dev->driver)
541 return -EINVAL;
542 if (!driver->unbind)
543 return -EBUSY;
544
545 spin_lock_irqsave(&dev->lock, flags);
546 dev->driver = 0;
547 stop_activity(dev, driver);
548 spin_unlock_irqrestore(&dev->lock, flags);
549
550 driver->unbind(&dev->gadget);
551
552 udc_disable(dev);
553
554 DEBUG("unregistered driver '%s'\n", driver->driver.name);
555
556 return 0;
557 }
558
559 EXPORT_SYMBOL(usb_gadget_unregister_driver);
560
561 /*-------------------------------------------------------------------------*/
562
563 /*
564 * Starting DMA using mode 1
565 */
566 static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
567 {
568 struct jz4740_udc *dev = ep->dev;
569 uint32_t count = req->req.length;
570 uint32_t physaddr = virt_to_phys((void *)req->req.buf);
571
572 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
573
574 jz_udc_select_ep(ep);
575
576 if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
577 ep->reg_addr = JZ_REG_UDC_ADDR1;
578
579 dma_cache_wback_inv((unsigned long)req->req.buf, count);
580
581 pio_irq_enable(ep);
582
583 usb_writeb(dev, JZ_REG_UDC_INCSRH,
584 USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
585
586 usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
587 usb_writel(dev, JZ_REG_UDC_COUNT1, count);
588 usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
589 USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
590 }
591 else { /* Bulk-OUT transfer using DMA channel 2 */
592 ep->reg_addr = JZ_REG_UDC_ADDR2;
593
594 dma_cache_wback_inv((unsigned long)req->req.buf, count);
595
596 pio_irq_enable(ep);
597
598 usb_setb(dev, JZ_REG_UDC_OUTCSRH,
599 USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
600
601 usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
602 usb_writel(dev, JZ_REG_UDC_COUNT2, count);
603 usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
604 USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
605 }
606 }
607
608 /*-------------------------------------------------------------------------*/
609
610 /** Write request to FIFO (max write == maxp size)
611 * Return: 0 = still running, 1 = completed, negative = errno
612 * NOTE: INDEX register must be set for EP
613 */
614 static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
615 {
616 struct jz4740_udc *dev = ep->dev;
617 uint32_t max, csr;
618 uint32_t physaddr = virt_to_phys((void *)req->req.buf);
619
620 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
621 max = le16_to_cpu(ep->desc->wMaxPacketSize);
622
623 if (use_dma) {
624 uint32_t dma_count;
625
626 /* DMA interrupt generated due to the last packet loaded into the FIFO */
627
628 dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
629 req->req.actual += dma_count;
630
631 if (dma_count % max) {
632 /* If the last packet is less than MAXP, set INPKTRDY manually */
633 usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
634 }
635
636 done(ep, req, 0);
637 if (list_empty(&ep->queue)) {
638 pio_irq_disable(ep);
639 return 1;
640 }
641 else {
642 /* advance the request queue */
643 req = list_entry(ep->queue.next, struct jz4740_request, queue);
644 kick_dma(ep, req);
645 return 0;
646 }
647 }
648
649 /*
650 * PIO mode handling starts here ...
651 */
652
653 csr = usb_readb(dev, ep->csr);
654
655 if (!(csr & USB_INCSR_FFNOTEMPT)) {
656 unsigned count;
657 int is_last, is_short;
658
659 count = write_packet(ep, req, max);
660 usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
661
662 /* last packet is usually short (or a zlp) */
663 if (unlikely(count != max))
664 is_last = is_short = 1;
665 else {
666 if (likely(req->req.length != req->req.actual)
667 || req->req.zero)
668 is_last = 0;
669 else
670 is_last = 1;
671 /* interrupt/iso maxpacket may not fill the fifo */
672 is_short = unlikely(max < ep_maxpacket(ep));
673 }
674
675 DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
676 ep->ep.name, count,
677 is_last ? "/L" : "", is_short ? "/S" : "",
678 req->req.length - req->req.actual, req);
679
680 /* requests complete when all IN data is in the FIFO */
681 if (is_last) {
682 done(ep, req, 0);
683 if (list_empty(&ep->queue)) {
684 pio_irq_disable(ep);
685 }
686 return 1;
687 }
688 } else {
689 DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
690 }
691
692 return 0;
693 }
694
695 /** Read to request from FIFO (max read == bytes in fifo)
696 * Return: 0 = still running, 1 = completed, negative = errno
697 * NOTE: INDEX register must be set for EP
698 */
699 static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
700 {
701 struct jz4740_udc *dev = ep->dev;
702 uint32_t csr;
703 unsigned count, is_short;
704 uint32_t physaddr = virt_to_phys((void *)req->req.buf);
705
706 if (use_dma) {
707 uint32_t dma_count;
708
709 /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
710
711 dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
712 req->req.actual += dma_count;
713
714 /* Disable interrupt and DMA */
715 pio_irq_disable(ep);
716 usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
717
718 /* Read all bytes from this packet */
719 count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
720 count = read_packet(ep, req, count);
721
722 if (count) {
723 /* If the last packet is greater than zero, clear OUTPKTRDY manually */
724 usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
725 }
726 done(ep, req, 0);
727
728 if (!list_empty(&ep->queue)) {
729 /* advance the request queue */
730 req = list_entry(ep->queue.next, struct jz4740_request, queue);
731 kick_dma(ep, req);
732 }
733
734 return 1;
735 }
736
737 /*
738 * PIO mode handling starts here ...
739 */
740
741 /* make sure there's a packet in the FIFO. */
742 csr = usb_readb(dev, ep->csr);
743 if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
744 DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
745 return -EINVAL;
746 }
747
748 /* read all bytes from this packet */
749 count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
750
751 is_short = (count < ep->ep.maxpacket);
752
753 count = read_packet(ep, req, count);
754
755 DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
756 ep->ep.name, csr, count,
757 is_short ? "/S" : "", req, req->req.actual, req->req.length);
758
759 /* Clear OutPktRdy */
760 usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
761
762 /* completion */
763 if (is_short || req->req.actual == req->req.length) {
764 done(ep, req, 0);
765
766 if (list_empty(&ep->queue))
767 pio_irq_disable(ep);
768 return 1;
769 }
770
771 /* finished that packet. the next one may be waiting... */
772 return 0;
773 }
774
775 /*
776 * done - retire a request; caller blocked irqs
777 * INDEX register is preserved to keep same
778 */
779 static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
780 {
781 unsigned int stopped = ep->stopped;
782 unsigned long flags;
783 uint32_t index;
784
785 DEBUG("%s, %p\n", __FUNCTION__, ep);
786 list_del_init(&req->queue);
787
788 if (likely(req->req.status == -EINPROGRESS))
789 req->req.status = status;
790 else
791 status = req->req.status;
792
793 if (status && status != -ESHUTDOWN)
794 DEBUG("complete %s req %p stat %d len %u/%u\n",
795 ep->ep.name, &req->req, status,
796 req->req.actual, req->req.length);
797
798 /* don't modify queue heads during completion callback */
799 ep->stopped = 1;
800 /* Read current index (completion may modify it) */
801 spin_lock_irqsave(&ep->dev->lock, flags);
802 index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
803
804 req->req.complete(&ep->ep, &req->req);
805
806 /* Restore index */
807 jz_udc_set_index(ep->dev, index);
808 spin_unlock_irqrestore(&ep->dev->lock, flags);
809 ep->stopped = stopped;
810 }
811
812 /** Enable EP interrupt */
813 static void pio_irq_enable(struct jz4740_ep *ep)
814 {
815 uint8_t index = ep_index(ep);
816 struct jz4740_udc *dev = ep->dev;
817 DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
818
819 if (ep_is_in(ep)) {
820 switch (index) {
821 case 1:
822 case 2:
823 usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
824 dev->in_mask |= BIT(index);
825 break;
826 default:
827 DEBUG("Unknown endpoint: %d\n", index);
828 break;
829 }
830 }
831 else {
832 switch (index) {
833 case 1:
834 usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
835 dev->out_mask |= BIT(index);
836 break;
837 default:
838 DEBUG("Unknown endpoint: %d\n", index);
839 break;
840 }
841 }
842 }
843
844 /** Disable EP interrupt */
845 static void pio_irq_disable(struct jz4740_ep *ep)
846 {
847 uint8_t index = ep_index(ep);
848 struct jz4740_udc *dev = ep->dev;
849
850 DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
851
852 if (ep_is_in(ep)) {
853 switch (ep_index(ep)) {
854 case 1:
855 case 2:
856 usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
857 dev->in_mask &= ~BIT(index);
858 break;
859 default:
860 DEBUG("Unknown endpoint: %d\n", index);
861 break;
862 }
863 }
864 else {
865 switch (ep_index(ep)) {
866 case 1:
867 usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
868 dev->out_mask &= ~BIT(index);
869 break;
870 default:
871 DEBUG("Unknown endpoint: %d\n", index);
872 break;
873 }
874 }
875 }
876
877 /*
878 * nuke - dequeue ALL requests
879 */
880 static void nuke(struct jz4740_ep *ep, int status)
881 {
882 struct jz4740_request *req;
883
884 DEBUG("%s, %p\n", __FUNCTION__, ep);
885
886 /* Flush FIFO */
887 flush(ep);
888
889 /* called with irqs blocked */
890 while (!list_empty(&ep->queue)) {
891 req = list_entry(ep->queue.next, struct jz4740_request, queue);
892 done(ep, req, status);
893 }
894
895 /* Disable IRQ if EP is enabled (has descriptor) */
896 if (ep->desc)
897 pio_irq_disable(ep);
898 }
899
900 /** Flush EP FIFO
901 * NOTE: INDEX register must be set before this call
902 */
903 static void flush(struct jz4740_ep *ep)
904 {
905 DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
906
907 switch (ep->type) {
908 case ep_bulk_in:
909 case ep_interrupt:
910 usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
911 break;
912 case ep_bulk_out:
913 usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
914 break;
915 case ep_control:
916 break;
917 }
918 }
919
920 /**
921 * jz4740_in_epn - handle IN interrupt
922 */
923 static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
924 {
925 uint32_t csr;
926 struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
927 struct jz4740_request *req;
928 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
929
930 jz_udc_set_index(dev, ep_index(ep));
931
932 csr = usb_readb(dev, ep->csr);
933 DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
934
935 if (csr & USB_INCSR_SENTSTALL) {
936 DEBUG("USB_INCSR_SENTSTALL\n");
937 usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
938 return;
939 }
940
941 if (!ep->desc) {
942 DEBUG("%s: NO EP DESC\n", __FUNCTION__);
943 return;
944 }
945
946 if (list_empty(&ep->queue))
947 req = 0;
948 else
949 req = list_entry(ep->queue.next, struct jz4740_request, queue);
950
951 DEBUG("req: %p\n", req);
952
953 if (!req)
954 return;
955
956 write_fifo(ep, req);
957 }
958
959 /*
960 * Bulk OUT (recv)
961 */
962 static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
963 {
964 struct jz4740_ep *ep = &dev->ep[ep_idx];
965 struct jz4740_request *req;
966
967 DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
968
969 jz_udc_set_index(dev, ep_index(ep));
970 if (ep->desc) {
971 uint32_t csr;
972
973 if (use_dma) {
974 /* DMA starts here ... */
975 if (list_empty(&ep->queue))
976 req = 0;
977 else
978 req = list_entry(ep->queue.next, struct jz4740_request, queue);
979
980 if (req)
981 read_fifo(ep, req);
982 return;
983 }
984
985 /*
986 * PIO mode starts here ...
987 */
988
989 while ((csr = usb_readb(dev, ep->csr)) &
990 (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
991 DEBUG("%s: %x\n", __FUNCTION__, csr);
992
993 if (csr & USB_OUTCSR_SENTSTALL) {
994 DEBUG("%s: stall sent, flush fifo\n",
995 __FUNCTION__);
996 /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
997 flush(ep);
998 } else if (csr & USB_OUTCSR_OUTPKTRDY) {
999 if (list_empty(&ep->queue))
1000 req = 0;
1001 else
1002 req =
1003 list_entry(ep->queue.next,
1004 struct jz4740_request,
1005 queue);
1006
1007 if (!req) {
1008 DEBUG("%s: NULL REQ %d\n",
1009 __FUNCTION__, ep_idx);
1010 break;
1011 } else {
1012 read_fifo(ep, req);
1013 }
1014 }
1015 }
1016 } else {
1017 /* Throw packet away.. */
1018 DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1019 flush(ep);
1020 }
1021 }
1022
1023 /** Halt specific EP
1024 * Return 0 if success
1025 * NOTE: Sets INDEX register to EP !
1026 */
1027 static int jz4740_set_halt(struct usb_ep *_ep, int value)
1028 {
1029 struct jz4740_udc *dev;
1030 struct jz4740_ep *ep;
1031 unsigned long flags;
1032
1033 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1034
1035 ep = container_of(_ep, struct jz4740_ep, ep);
1036 if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1037 DEBUG("%s, bad ep\n", __FUNCTION__);
1038 return -EINVAL;
1039 }
1040
1041 dev = ep->dev;
1042
1043 spin_lock_irqsave(&dev->lock, flags);
1044
1045 jz_udc_select_ep(ep);
1046
1047 DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1048
1049 if (ep_index(ep) == 0) {
1050 /* EP0 */
1051 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1052 } else if (ep_is_in(ep)) {
1053 uint32_t csr = usb_readb(dev, ep->csr);
1054 if (value && ((csr & USB_INCSR_FFNOTEMPT)
1055 || !list_empty(&ep->queue))) {
1056 /*
1057 * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1058 * if any transfer requests are still queued, or if the controller
1059 * FIFO still holds bytes that the host hasn\92t collected.
1060 */
1061 spin_unlock_irqrestore(&dev->lock, flags);
1062 DEBUG
1063 ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1064 (csr & USB_INCSR_FFNOTEMPT),
1065 !list_empty(&ep->queue));
1066 return -EAGAIN;
1067 }
1068 flush(ep);
1069 if (value) {
1070 usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1071 }
1072 else {
1073 usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1074 usb_setb(dev, ep->csr, USB_INCSR_CDT);
1075 }
1076 } else {
1077
1078 flush(ep);
1079 if (value) {
1080 usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1081 }
1082 else {
1083 usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1084 usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1085 }
1086 }
1087
1088 if (value) {
1089 ep->stopped = 1;
1090 } else {
1091 ep->stopped = 0;
1092 }
1093
1094 spin_unlock_irqrestore(&dev->lock, flags);
1095
1096 DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1097
1098 return 0;
1099 }
1100
1101
1102 static int jz4740_ep_enable(struct usb_ep *_ep,
1103 const struct usb_endpoint_descriptor *desc)
1104 {
1105 struct jz4740_ep *ep;
1106 struct jz4740_udc *dev;
1107 unsigned long flags;
1108 uint32_t max, csrh = 0;
1109
1110 DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1111
1112 if (!_ep || !desc)
1113 return -EINVAL;
1114
1115 ep = container_of(_ep, struct jz4740_ep, ep);
1116 if (ep->desc || ep->type == ep_control
1117 || desc->bDescriptorType != USB_DT_ENDPOINT
1118 || ep->bEndpointAddress != desc->bEndpointAddress) {
1119 DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1120 return -EINVAL;
1121 }
1122
1123 /* xfer types must match, except that interrupt ~= bulk */
1124 if (ep->bmAttributes != desc->bmAttributes
1125 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1126 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1127 DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1128 return -EINVAL;
1129 }
1130
1131 dev = ep->dev;
1132 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1133 DEBUG("%s, bogus device state\n", __FUNCTION__);
1134 return -ESHUTDOWN;
1135 }
1136
1137 max = le16_to_cpu(desc->wMaxPacketSize);
1138
1139 spin_lock_irqsave(&ep->dev->lock, flags);
1140
1141 /* Configure the endpoint */
1142 jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1143 if (ep_is_in(ep)) {
1144 usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1145 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1146 case USB_ENDPOINT_XFER_BULK:
1147 case USB_ENDPOINT_XFER_INT:
1148 csrh &= ~USB_INCSRH_ISO;
1149 break;
1150 case USB_ENDPOINT_XFER_ISOC:
1151 csrh |= USB_INCSRH_ISO;
1152 break;
1153 }
1154 usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1155 }
1156 else {
1157 usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1158 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1159 case USB_ENDPOINT_XFER_BULK:
1160 csrh &= ~USB_OUTCSRH_ISO;
1161 break;
1162 case USB_ENDPOINT_XFER_INT:
1163 csrh &= ~USB_OUTCSRH_ISO;
1164 csrh |= USB_OUTCSRH_DNYT;
1165 break;
1166 case USB_ENDPOINT_XFER_ISOC:
1167 csrh |= USB_OUTCSRH_ISO;
1168 break;
1169 }
1170 usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1171 }
1172
1173
1174 ep->stopped = 0;
1175 ep->desc = desc;
1176 ep->pio_irqs = 0;
1177 ep->ep.maxpacket = max;
1178
1179 spin_unlock_irqrestore(&ep->dev->lock, flags);
1180
1181 /* Reset halt state (does flush) */
1182 jz4740_set_halt(_ep, 0);
1183
1184 DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1185
1186 return 0;
1187 }
1188
1189 /** Disable EP
1190 * NOTE: Sets INDEX register
1191 */
1192 static int jz4740_ep_disable(struct usb_ep *_ep)
1193 {
1194 struct jz4740_ep *ep;
1195 unsigned long flags;
1196
1197 DEBUG("%s, %p\n", __FUNCTION__, _ep);
1198
1199 ep = container_of(_ep, struct jz4740_ep, ep);
1200 if (!_ep || !ep->desc) {
1201 DEBUG("%s, %s not enabled\n", __FUNCTION__,
1202 _ep ? ep->ep.name : NULL);
1203 return -EINVAL;
1204 }
1205
1206 spin_lock_irqsave(&ep->dev->lock, flags);
1207
1208 jz_udc_select_ep(ep);
1209
1210 /* Nuke all pending requests (does flush) */
1211 nuke(ep, -ESHUTDOWN);
1212
1213 /* Disable ep IRQ */
1214 pio_irq_disable(ep);
1215
1216 ep->desc = 0;
1217 ep->stopped = 1;
1218
1219 spin_unlock_irqrestore(&ep->dev->lock, flags);
1220
1221 DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1222 return 0;
1223 }
1224
1225 static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1226 {
1227 struct jz4740_request *req;
1228
1229 DEBUG("%s, %p\n", __FUNCTION__, ep);
1230
1231 req = kzalloc(sizeof(*req), gfp_flags);
1232 if (!req)
1233 return 0;
1234
1235 INIT_LIST_HEAD(&req->queue);
1236
1237 return &req->req;
1238 }
1239
1240 static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1241 {
1242 struct jz4740_request *req;
1243
1244 DEBUG("%s, %p\n", __FUNCTION__, ep);
1245
1246 req = container_of(_req, struct jz4740_request, req);
1247 WARN_ON(!list_empty(&req->queue));
1248 kfree(req);
1249 }
1250
1251 /*--------------------------------------------------------------------*/
1252
1253 /** Queue one request
1254 * Kickstart transfer if needed
1255 * NOTE: Sets INDEX register
1256 */
1257 static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1258 gfp_t gfp_flags)
1259 {
1260 struct jz4740_request *req;
1261 struct jz4740_ep *ep;
1262 struct jz4740_udc *dev;
1263 unsigned long flags;
1264
1265 DEBUG("%s, %p\n", __FUNCTION__, _ep);
1266
1267 req = container_of(_req, struct jz4740_request, req);
1268 if (unlikely
1269 (!_req || !_req->complete || !_req->buf
1270 || !list_empty(&req->queue))) {
1271 DEBUG("%s, bad params\n", __FUNCTION__);
1272 return -EINVAL;
1273 }
1274
1275 ep = container_of(_ep, struct jz4740_ep, ep);
1276 if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1277 DEBUG("%s, bad ep\n", __FUNCTION__);
1278 return -EINVAL;
1279 }
1280
1281 dev = ep->dev;
1282 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1283 DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1284 return -ESHUTDOWN;
1285 }
1286
1287 DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1288 _req->buf);
1289
1290 spin_lock_irqsave(&dev->lock, flags);
1291
1292 _req->status = -EINPROGRESS;
1293 _req->actual = 0;
1294
1295 /* kickstart this i/o queue? */
1296 DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1297 ep->stopped);
1298 if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1299 uint32_t csr;
1300
1301 if (unlikely(ep_index(ep) == 0)) {
1302 /* EP0 */
1303 list_add_tail(&req->queue, &ep->queue);
1304 jz4740_ep0_kick(dev, ep);
1305 req = 0;
1306 } else if (use_dma) {
1307 /* DMA */
1308 kick_dma(ep, req);
1309 }
1310 /* PIO */
1311 else if (ep_is_in(ep)) {
1312 /* EP1 & EP2 */
1313 jz_udc_set_index(dev, ep_index(ep));
1314 csr = usb_readb(dev, ep->csr);
1315 pio_irq_enable(ep);
1316 if (!(csr & USB_INCSR_FFNOTEMPT)) {
1317 if (write_fifo(ep, req) == 1)
1318 req = 0;
1319 }
1320 } else {
1321 /* EP1 */
1322 jz_udc_set_index(dev, ep_index(ep));
1323 csr = usb_readb(dev, ep->csr);
1324 pio_irq_enable(ep);
1325 if (csr & USB_OUTCSR_OUTPKTRDY) {
1326 if (read_fifo(ep, req) == 1)
1327 req = 0;
1328 }
1329 }
1330 }
1331
1332 /* pio or dma irq handler advances the queue. */
1333 if (likely(req != 0))
1334 list_add_tail(&req->queue, &ep->queue);
1335
1336 spin_unlock_irqrestore(&dev->lock, flags);
1337
1338 return 0;
1339 }
1340
1341 /* dequeue JUST ONE request */
1342 static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1343 {
1344 struct jz4740_ep *ep;
1345 struct jz4740_request *req;
1346 unsigned long flags;
1347
1348 DEBUG("%s, %p\n", __FUNCTION__, _ep);
1349
1350 ep = container_of(_ep, struct jz4740_ep, ep);
1351 if (!_ep || ep->type == ep_control)
1352 return -EINVAL;
1353
1354 spin_lock_irqsave(&ep->dev->lock, flags);
1355
1356 /* make sure it's actually queued on this endpoint */
1357 list_for_each_entry(req, &ep->queue, queue) {
1358 if (&req->req == _req)
1359 break;
1360 }
1361 if (&req->req != _req) {
1362 spin_unlock_irqrestore(&ep->dev->lock, flags);
1363 return -EINVAL;
1364 }
1365 done(ep, req, -ECONNRESET);
1366
1367 spin_unlock_irqrestore(&ep->dev->lock, flags);
1368 return 0;
1369 }
1370
1371 /** Return bytes in EP FIFO
1372 * NOTE: Sets INDEX register to EP
1373 */
1374 static int jz4740_fifo_status(struct usb_ep *_ep)
1375 {
1376 uint32_t csr;
1377 int count = 0;
1378 struct jz4740_ep *ep;
1379 unsigned long flags;
1380
1381 ep = container_of(_ep, struct jz4740_ep, ep);
1382 if (!_ep) {
1383 DEBUG("%s, bad ep\n", __FUNCTION__);
1384 return -ENODEV;
1385 }
1386
1387 DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1388
1389 /* LPD can't report unclaimed bytes from IN fifos */
1390 if (ep_is_in(ep))
1391 return -EOPNOTSUPP;
1392
1393 spin_lock_irqsave(&ep->dev->lock, flags);
1394 jz_udc_set_index(ep->dev, ep_index(ep));
1395
1396 csr = usb_readb(ep->dev, ep->csr);
1397 if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1398 csr & 0x1) {
1399 count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1400 }
1401
1402 spin_unlock_irqrestore(&ep->dev->lock, flags);
1403
1404 return count;
1405 }
1406
1407 /** Flush EP FIFO
1408 * NOTE: Sets INDEX register to EP
1409 */
1410 static void jz4740_fifo_flush(struct usb_ep *_ep)
1411 {
1412 struct jz4740_ep *ep;
1413 unsigned long flags;
1414
1415 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1416
1417 ep = container_of(_ep, struct jz4740_ep, ep);
1418 if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1419 DEBUG("%s, bad ep\n", __FUNCTION__);
1420 return;
1421 }
1422
1423 spin_lock_irqsave(&ep->dev->lock, flags);
1424
1425 jz_udc_set_index(ep->dev, ep_index(ep));
1426 flush(ep);
1427
1428 spin_unlock_irqrestore(&ep->dev->lock, flags);
1429 }
1430
1431 /****************************************************************/
1432 /* End Point 0 related functions */
1433 /****************************************************************/
1434
1435 /* return: 0 = still running, 1 = completed, negative = errno */
1436 static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1437 {
1438 uint32_t max;
1439 unsigned count;
1440 int is_last;
1441
1442 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1443 max = ep_maxpacket(ep);
1444
1445 count = write_packet(ep, req, max);
1446
1447 /* last packet is usually short (or a zlp) */
1448 if (unlikely(count != max))
1449 is_last = 1;
1450 else {
1451 if (likely(req->req.length != req->req.actual) || req->req.zero)
1452 is_last = 0;
1453 else
1454 is_last = 1;
1455 }
1456
1457 DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1458 ep->ep.name, count,
1459 is_last ? "/L" : "", req->req.length - req->req.actual, req);
1460
1461 /* requests complete when all IN data is in the FIFO */
1462 if (is_last) {
1463 done(ep, req, 0);
1464 return 1;
1465 }
1466
1467 return 0;
1468 }
1469
1470 static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1471 unsigned char *cp, int max)
1472 {
1473 int bytes;
1474 int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1475
1476 if (count > max)
1477 count = max;
1478 bytes = count;
1479 while (count--)
1480 *cp++ = usb_readb(ep->dev, ep->fifo);
1481
1482 return bytes;
1483 }
1484
1485 static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1486 unsigned char *cp, int count)
1487 {
1488 DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1489 while (count--)
1490 usb_writeb(ep->dev, ep->fifo, *cp++);
1491 }
1492
1493 static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1494 {
1495 struct jz4740_udc *dev = ep->dev;
1496 uint32_t csr;
1497 uint8_t *buf;
1498 unsigned bufferspace, count, is_short;
1499
1500 DEBUG_EP0("%s\n", __FUNCTION__);
1501
1502 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1503 if (!(csr & USB_CSR0_OUTPKTRDY))
1504 return 0;
1505
1506 buf = req->req.buf + req->req.actual;
1507 prefetchw(buf);
1508 bufferspace = req->req.length - req->req.actual;
1509
1510 /* read all bytes from this packet */
1511 if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1512 count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1513 req->req.actual += min(count, bufferspace);
1514 } else /* zlp */
1515 count = 0;
1516
1517 is_short = (count < ep->ep.maxpacket);
1518 DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1519 ep->ep.name, csr, count,
1520 is_short ? "/S" : "", req, req->req.actual, req->req.length);
1521
1522 while (likely(count-- != 0)) {
1523 uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1524
1525 if (unlikely(bufferspace == 0)) {
1526 /* this happens when the driver's buffer
1527 * is smaller than what the host sent.
1528 * discard the extra data.
1529 */
1530 if (req->req.status != -EOVERFLOW)
1531 DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1532 count);
1533 req->req.status = -EOVERFLOW;
1534 } else {
1535 *buf++ = byte;
1536 bufferspace--;
1537 }
1538 }
1539
1540 /* completion */
1541 if (is_short || req->req.actual == req->req.length) {
1542 done(ep, req, 0);
1543 return 1;
1544 }
1545
1546 /* finished that packet. the next one may be waiting... */
1547 return 0;
1548 }
1549
1550 /**
1551 * udc_set_address - set the USB address for this device
1552 * @address:
1553 *
1554 * Called from control endpoint function after it decodes a set address setup packet.
1555 */
1556 static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1557 {
1558 DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1559
1560 dev->usb_address = address;
1561 usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1562 }
1563
1564 /*
1565 * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1566 * - if error
1567 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1568 * - else
1569 * set USB_CSR0_SVDOUTPKTRDY bit
1570 if last set USB_CSR0_DATAEND bit
1571 */
1572 static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1573 {
1574 struct jz4740_request *req;
1575 struct jz4740_ep *ep = &dev->ep[0];
1576 int ret;
1577
1578 DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1579
1580 if (list_empty(&ep->queue))
1581 req = 0;
1582 else
1583 req = list_entry(ep->queue.next, struct jz4740_request, queue);
1584
1585 if (req) {
1586 if (req->req.length == 0) {
1587 DEBUG_EP0("ZERO LENGTH OUT!\n");
1588 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1589 dev->ep0state = WAIT_FOR_SETUP;
1590 return;
1591 } else if (kickstart) {
1592 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1593 return;
1594 }
1595 ret = read_fifo_ep0(ep, req);
1596 if (ret) {
1597 /* Done! */
1598 DEBUG_EP0("%s: finished, waiting for status\n",
1599 __FUNCTION__);
1600 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1601 dev->ep0state = WAIT_FOR_SETUP;
1602 } else {
1603 /* Not done yet.. */
1604 DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1605 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1606 }
1607 } else {
1608 DEBUG_EP0("NO REQ??!\n");
1609 }
1610 }
1611
1612 /*
1613 * DATA_STATE_XMIT
1614 */
1615 static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1616 {
1617 struct jz4740_request *req;
1618 struct jz4740_ep *ep = &dev->ep[0];
1619 int ret, need_zlp = 0;
1620
1621 DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1622
1623 if (list_empty(&ep->queue))
1624 req = 0;
1625 else
1626 req = list_entry(ep->queue.next, struct jz4740_request, queue);
1627
1628 if (!req) {
1629 DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1630 return 0;
1631 }
1632
1633 if (req->req.length == 0) {
1634 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1635 dev->ep0state = WAIT_FOR_SETUP;
1636 return 1;
1637 }
1638
1639 if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1640 /* Next write will end with the packet size, */
1641 /* so we need zero-length-packet */
1642 need_zlp = 1;
1643 }
1644
1645 ret = write_fifo_ep0(ep, req);
1646
1647 if (ret == 1 && !need_zlp) {
1648 /* Last packet */
1649 DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1650
1651 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1652 dev->ep0state = WAIT_FOR_SETUP;
1653 } else {
1654 DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1655 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1656 }
1657
1658 if (need_zlp) {
1659 DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1660 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1661 dev->ep0state = DATA_STATE_NEED_ZLP;
1662 }
1663
1664 return 1;
1665 }
1666
1667 static int jz4740_handle_get_status(struct jz4740_udc *dev,
1668 struct usb_ctrlrequest *ctrl)
1669 {
1670 struct jz4740_ep *ep0 = &dev->ep[0];
1671 struct jz4740_ep *qep;
1672 int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1673 uint16_t val = 0;
1674
1675 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1676
1677 if (reqtype == USB_RECIP_INTERFACE) {
1678 /* This is not supported.
1679 * And according to the USB spec, this one does nothing..
1680 * Just return 0
1681 */
1682 DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1683 } else if (reqtype == USB_RECIP_DEVICE) {
1684 DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1685 val |= (1 << 0); /* Self powered */
1686 /*val |= (1<<1); *//* Remote wakeup */
1687 } else if (reqtype == USB_RECIP_ENDPOINT) {
1688 int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1689
1690 DEBUG_SETUP
1691 ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1692 ep_num, ctrl->wLength);
1693
1694 if (ctrl->wLength > 2 || ep_num > 3)
1695 return -EOPNOTSUPP;
1696
1697 qep = &dev->ep[ep_num];
1698 if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1699 && ep_index(qep) != 0) {
1700 return -EOPNOTSUPP;
1701 }
1702
1703 jz_udc_set_index(dev, ep_index(qep));
1704
1705 /* Return status on next IN token */
1706 switch (qep->type) {
1707 case ep_control:
1708 val =
1709 (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1710 USB_CSR0_SENDSTALL;
1711 break;
1712 case ep_bulk_in:
1713 case ep_interrupt:
1714 val =
1715 (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1716 USB_INCSR_SENDSTALL;
1717 break;
1718 case ep_bulk_out:
1719 val =
1720 (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1721 USB_OUTCSR_SENDSTALL;
1722 break;
1723 }
1724
1725 /* Back to EP0 index */
1726 jz_udc_set_index(dev, 0);
1727
1728 DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1729 ctrl->wIndex, val);
1730 } else {
1731 DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1732 return -EOPNOTSUPP;
1733 }
1734
1735 /* Clear "out packet ready" */
1736 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1737 /* Put status to FIFO */
1738 jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1739 /* Issue "In packet ready" */
1740 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1741
1742 return 0;
1743 }
1744
1745 /*
1746 * WAIT_FOR_SETUP (OUTPKTRDY)
1747 * - read data packet from EP0 FIFO
1748 * - decode command
1749 * - if error
1750 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1751 * - else
1752 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1753 */
1754 static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1755 {
1756 struct jz4740_ep *ep = &dev->ep[0];
1757 struct usb_ctrlrequest ctrl;
1758 int i;
1759
1760 DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1761
1762 /* Nuke all previous transfers */
1763 nuke(ep, -EPROTO);
1764
1765 /* read control req from fifo (8 bytes) */
1766 jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1767
1768 DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1769 ctrl.bRequestType, ctrl.bRequest,
1770 ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1771
1772 /* Set direction of EP0 */
1773 if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1774 ep->bEndpointAddress |= USB_DIR_IN;
1775 } else {
1776 ep->bEndpointAddress &= ~USB_DIR_IN;
1777 }
1778
1779 /* Handle some SETUP packets ourselves */
1780 switch (ctrl.bRequest) {
1781 case USB_REQ_SET_ADDRESS:
1782 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1783 break;
1784
1785 DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1786 udc_set_address(dev, ctrl.wValue);
1787 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1788 return;
1789
1790 case USB_REQ_SET_CONFIGURATION:
1791 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1792 break;
1793
1794 DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1795 /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1796
1797 /* Enable RESUME and SUSPEND interrupts */
1798 usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1799 break;
1800
1801 case USB_REQ_SET_INTERFACE:
1802 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1803 break;
1804
1805 DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1806 /* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1807 break;
1808
1809 case USB_REQ_GET_STATUS:
1810 if (jz4740_handle_get_status(dev, &ctrl) == 0)
1811 return;
1812
1813 case USB_REQ_CLEAR_FEATURE:
1814 case USB_REQ_SET_FEATURE:
1815 if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1816 struct jz4740_ep *qep;
1817 int ep_num = (ctrl.wIndex & 0x0f);
1818
1819 /* Support only HALT feature */
1820 if (ctrl.wValue != 0 || ctrl.wLength != 0
1821 || ep_num > 3 || ep_num < 1)
1822 break;
1823
1824 qep = &dev->ep[ep_num];
1825 spin_unlock(&dev->lock);
1826 if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1827 DEBUG_SETUP("SET_FEATURE (%d)\n",
1828 ep_num);
1829 jz4740_set_halt(&qep->ep, 1);
1830 } else {
1831 DEBUG_SETUP("CLR_FEATURE (%d)\n",
1832 ep_num);
1833 jz4740_set_halt(&qep->ep, 0);
1834 }
1835 spin_lock(&dev->lock);
1836
1837 jz_udc_set_index(dev, 0);
1838
1839 /* Reply with a ZLP on next IN token */
1840 usb_setb(dev, JZ_REG_UDC_CSR0,
1841 (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1842 return;
1843 }
1844 break;
1845
1846 default:
1847 break;
1848 }
1849
1850 /* gadget drivers see class/vendor specific requests,
1851 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1852 * and more.
1853 */
1854 if (dev->driver) {
1855 /* device-2-host (IN) or no data setup command, process immediately */
1856 spin_unlock(&dev->lock);
1857
1858 i = dev->driver->setup(&dev->gadget, &ctrl);
1859 spin_lock(&dev->lock);
1860
1861 if (unlikely(i < 0)) {
1862 /* setup processing failed, force stall */
1863 DEBUG_SETUP
1864 (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1865 i);
1866 jz_udc_set_index(dev, 0);
1867 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1868
1869 /* ep->stopped = 1; */
1870 dev->ep0state = WAIT_FOR_SETUP;
1871 }
1872 else {
1873 DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1874 /* if (!ctrl.wLength) {
1875 usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1876 }*/
1877 }
1878 }
1879 }
1880
1881 /*
1882 * DATA_STATE_NEED_ZLP
1883 */
1884 static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1885 {
1886 DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1887
1888 usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1889 dev->ep0state = WAIT_FOR_SETUP;
1890 }
1891
1892 /*
1893 * handle ep0 interrupt
1894 */
1895 static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1896 {
1897 struct jz4740_ep *ep = &dev->ep[0];
1898 uint32_t csr;
1899
1900 DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1901 /* Set index 0 */
1902 jz_udc_set_index(dev, 0);
1903 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1904
1905 DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1906
1907 /*
1908 * if SENT_STALL is set
1909 * - clear the SENT_STALL bit
1910 */
1911 if (csr & USB_CSR0_SENTSTALL) {
1912 DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1913 usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1914 nuke(ep, -ECONNABORTED);
1915 dev->ep0state = WAIT_FOR_SETUP;
1916 return;
1917 }
1918
1919 /*
1920 * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1921 * - fill EP0 FIFO
1922 * - if last packet
1923 * - set IN_PKT_RDY | DATA_END
1924 * - else
1925 * set IN_PKT_RDY
1926 */
1927 if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1928 DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1929 __FUNCTION__);
1930
1931 switch (dev->ep0state) {
1932 case DATA_STATE_XMIT:
1933 DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1934 jz4740_ep0_in(dev, csr);
1935 return;
1936 case DATA_STATE_NEED_ZLP:
1937 DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1938 jz4740_ep0_in_zlp(dev, csr);
1939 return;
1940 default:
1941 /* Stall? */
1942 // DEBUG_EP0("Odd state!! state = %s\n",
1943 // state_names[dev->ep0state]);
1944 dev->ep0state = WAIT_FOR_SETUP;
1945 /* nuke(ep, 0); */
1946 /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1947 // break;
1948 return;
1949 }
1950 }
1951
1952 /*
1953 * if SETUPEND is set
1954 * - abort the last transfer
1955 * - set SERVICED_SETUP_END_BIT
1956 */
1957 if (csr & USB_CSR0_SETUPEND) {
1958 DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1959
1960 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1961 nuke(ep, 0);
1962 dev->ep0state = WAIT_FOR_SETUP;
1963 }
1964
1965 /*
1966 * if USB_CSR0_OUTPKTRDY is set
1967 * - read data packet from EP0 FIFO
1968 * - decode command
1969 * - if error
1970 * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1971 * - else
1972 * set SVDOUTPKTRDY | DATAEND bits
1973 */
1974 if (csr & USB_CSR0_OUTPKTRDY) {
1975
1976 DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1977 csr);
1978
1979 switch (dev->ep0state) {
1980 case WAIT_FOR_SETUP:
1981 DEBUG_EP0("WAIT_FOR_SETUP\n");
1982 jz4740_ep0_setup(dev, csr);
1983 break;
1984
1985 case DATA_STATE_RECV:
1986 DEBUG_EP0("DATA_STATE_RECV\n");
1987 jz4740_ep0_out(dev, csr, 0);
1988 break;
1989
1990 default:
1991 /* send stall? */
1992 DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1993 dev->ep0state);
1994 break;
1995 }
1996 }
1997 }
1998
1999 static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2000 {
2001 uint32_t csr;
2002
2003 jz_udc_set_index(dev, 0);
2004
2005 DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2006
2007 /* Clear "out packet ready" */
2008
2009 if (ep_is_in(ep)) {
2010 usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2011 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2012 dev->ep0state = DATA_STATE_XMIT;
2013 jz4740_ep0_in(dev, csr);
2014 } else {
2015 csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2016 dev->ep0state = DATA_STATE_RECV;
2017 jz4740_ep0_out(dev, csr, 1);
2018 }
2019 }
2020
2021 /** Handle USB RESET interrupt
2022 */
2023 static void jz4740_reset_irq(struct jz4740_udc *dev)
2024 {
2025 dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2026 USB_SPEED_HIGH : USB_SPEED_FULL;
2027
2028 DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2029 (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2030 }
2031
2032 /*
2033 * jz4740 usb device interrupt handler.
2034 */
2035 static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2036 {
2037 struct jz4740_udc *dev = _dev;
2038 uint8_t index;
2039
2040 uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2041 uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
2042 uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2043 uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2044
2045 if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2046 return IRQ_HANDLED;
2047
2048
2049 DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2050 intr_out, intr_in, intr_usb);
2051
2052 spin_lock(&dev->lock);
2053 index = usb_readb(dev, JZ_REG_UDC_INDEX);
2054
2055 /* Check for resume from suspend mode */
2056 if ((intr_usb & USB_INTR_RESUME) &&
2057 (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2058 DEBUG("USB resume\n");
2059 dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2060 }
2061
2062 /* Check for system interrupts */
2063 if (intr_usb & USB_INTR_RESET) {
2064 DEBUG("USB reset\n");
2065 jz4740_reset_irq(dev);
2066 }
2067
2068 /* Check for endpoint 0 interrupt */
2069 if (intr_in & USB_INTR_EP0) {
2070 DEBUG("USB_INTR_EP0 (control)\n");
2071 jz4740_handle_ep0(dev, intr_in);
2072 }
2073
2074 /* Check for Bulk-IN DMA interrupt */
2075 if (intr_dma & 0x1) {
2076 int ep_num;
2077 struct jz4740_ep *ep;
2078 ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2079 ep = &dev->ep[ep_num + 1];
2080 jz_udc_set_index(dev, ep_num);
2081 usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2082 /* jz4740_in_epn(dev, ep_num, intr_in);*/
2083 }
2084
2085 /* Check for Bulk-OUT DMA interrupt */
2086 if (intr_dma & 0x2) {
2087 int ep_num;
2088 ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2089 jz4740_out_epn(dev, ep_num, intr_out);
2090 }
2091
2092 /* Check for each configured endpoint interrupt */
2093 if (intr_in & USB_INTR_INEP1) {
2094 DEBUG("USB_INTR_INEP1\n");
2095 jz4740_in_epn(dev, 1, intr_in);
2096 }
2097
2098 if (intr_in & USB_INTR_INEP2) {
2099 DEBUG("USB_INTR_INEP2\n");
2100 jz4740_in_epn(dev, 2, intr_in);
2101 }
2102
2103 if (intr_out & USB_INTR_OUTEP1) {
2104 DEBUG("USB_INTR_OUTEP1\n");
2105 jz4740_out_epn(dev, 1, intr_out);
2106 }
2107
2108 /* Check for suspend mode */
2109 if ((intr_usb & USB_INTR_SUSPEND) &&
2110 (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2111 DEBUG("USB suspend\n");
2112 dev->driver->suspend(&dev->gadget);
2113 /* Host unloaded from us, can do something, such as flushing
2114 the NAND block cache etc. */
2115 }
2116
2117 jz_udc_set_index(dev, index);
2118
2119 spin_unlock(&dev->lock);
2120
2121 return IRQ_HANDLED;
2122 }
2123
2124
2125
2126 /*-------------------------------------------------------------------------*/
2127
2128 /* Common functions - Added by River */
2129 static struct jz4740_udc udc_dev;
2130
2131 static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2132 {
2133 return container_of(gadget, struct jz4740_udc, gadget);
2134 }
2135 /* End added */
2136
2137 static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2138 {
2139 DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2140 return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2141 }
2142
2143 static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2144 {
2145 /* host may not have enabled remote wakeup */
2146 /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2147 return -EHOSTUNREACH;
2148 udc_set_mask_UDCCR(UDCCR_RSM); */
2149 return -ENOTSUPP;
2150 }
2151
2152 static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2153 {
2154 struct jz4740_udc *udc = gadget_to_udc(_gadget);
2155
2156 unsigned long flags;
2157
2158 local_irq_save(flags);
2159
2160 if (on) {
2161 udc->state = UDC_STATE_ENABLE;
2162 udc_enable(udc);
2163 } else {
2164 udc->state = UDC_STATE_DISABLE;
2165 udc_disable(udc);
2166 }
2167
2168 local_irq_restore(flags);
2169
2170 return 0;
2171 }
2172
2173 static const struct usb_gadget_ops jz4740_udc_ops = {
2174 .get_frame = jz4740_udc_get_frame,
2175 .wakeup = jz4740_udc_wakeup,
2176 .pullup = jz4740_udc_pullup,
2177 /* current versions must always be self-powered */
2178 };
2179
2180 static struct usb_ep_ops jz4740_ep_ops = {
2181 .enable = jz4740_ep_enable,
2182 .disable = jz4740_ep_disable,
2183
2184 .alloc_request = jz4740_alloc_request,
2185 .free_request = jz4740_free_request,
2186
2187 .queue = jz4740_queue,
2188 .dequeue = jz4740_dequeue,
2189
2190 .set_halt = jz4740_set_halt,
2191 .fifo_status = jz4740_fifo_status,
2192 .fifo_flush = jz4740_fifo_flush,
2193 };
2194
2195
2196 /*-------------------------------------------------------------------------*/
2197
2198 static struct jz4740_udc udc_dev = {
2199 .usb_address = 0,
2200 .gadget = {
2201 .ops = &jz4740_udc_ops,
2202 .ep0 = &udc_dev.ep[0].ep,
2203 .name = "jz-udc",
2204 .dev = {
2205 .init_name = "gadget",
2206 },
2207 },
2208
2209 /* control endpoint */
2210 .ep[0] = {
2211 .ep = {
2212 .name = "ep0",
2213 .ops = &jz4740_ep_ops,
2214 .maxpacket = EP0_MAXPACKETSIZE,
2215 },
2216 .dev = &udc_dev,
2217
2218 .bEndpointAddress = 0,
2219 .bmAttributes = 0,
2220
2221 .type = ep_control,
2222 .fifo = JZ_REG_UDC_EP_FIFO(0),
2223 .csr = JZ_REG_UDC_CSR0,
2224 },
2225
2226 /* bulk out endpoint */
2227 .ep[1] = {
2228 .ep = {
2229 .name = "ep1out-bulk",
2230 .ops = &jz4740_ep_ops,
2231 .maxpacket = EPBULK_MAXPACKETSIZE,
2232 },
2233 .dev = &udc_dev,
2234
2235 .bEndpointAddress = 1,
2236 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2237
2238 .type = ep_bulk_out,
2239 .fifo = JZ_REG_UDC_EP_FIFO(1),
2240 .csr = JZ_REG_UDC_OUTCSR,
2241 },
2242
2243 /* bulk in endpoint */
2244 .ep[2] = {
2245 .ep = {
2246 .name = "ep1in-bulk",
2247 .ops = &jz4740_ep_ops,
2248 .maxpacket = EPBULK_MAXPACKETSIZE,
2249 },
2250 .dev = &udc_dev,
2251
2252 .bEndpointAddress = 1 | USB_DIR_IN,
2253 .bmAttributes = USB_ENDPOINT_XFER_BULK,
2254
2255 .type = ep_bulk_in,
2256 .fifo = JZ_REG_UDC_EP_FIFO(1),
2257 .csr = JZ_REG_UDC_INCSR,
2258 },
2259
2260 /* interrupt in endpoint */
2261 .ep[3] = {
2262 .ep = {
2263 .name = "ep2in-int",
2264 .ops = &jz4740_ep_ops,
2265 .maxpacket = EPINTR_MAXPACKETSIZE,
2266 },
2267 .dev = &udc_dev,
2268
2269 .bEndpointAddress = 2 | USB_DIR_IN,
2270 .bmAttributes = USB_ENDPOINT_XFER_INT,
2271
2272 .type = ep_interrupt,
2273 .fifo = JZ_REG_UDC_EP_FIFO(2),
2274 .csr = JZ_REG_UDC_INCSR,
2275 },
2276 };
2277
2278 static void gadget_release(struct device *_dev)
2279 {
2280 }
2281
2282
2283 static int jz4740_udc_probe(struct platform_device *pdev)
2284 {
2285 struct jz4740_udc *dev = &udc_dev;
2286 int ret;
2287
2288 spin_lock_init(&dev->lock);
2289 the_controller = dev;
2290
2291 dev->dev = &pdev->dev;
2292 dev_set_name(&dev->gadget.dev, "gadget");
2293 dev->gadget.dev.parent = &pdev->dev;
2294 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2295 dev->gadget.dev.release = gadget_release;
2296
2297 ret = device_register(&dev->gadget.dev);
2298 if (ret)
2299 return ret;
2300
2301 dev->clk = clk_get(&pdev->dev, "udc");
2302 if (IS_ERR(dev->clk)) {
2303 ret = PTR_ERR(dev->clk);
2304 dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2305 goto err_device_unregister;
2306 }
2307
2308 platform_set_drvdata(pdev, dev);
2309
2310 dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311
2312 if (!dev->mem) {
2313 ret = -ENOENT;
2314 dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2315 goto err_clk_put;
2316 }
2317
2318 dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2319
2320 if (!dev->mem) {
2321 ret = -EBUSY;
2322 dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2323 goto err_device_unregister;
2324 }
2325
2326 dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2327
2328 if (!dev->base) {
2329 ret = -EBUSY;
2330 dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2331 goto err_release_mem_region;
2332 }
2333
2334 dev->irq = platform_get_irq(pdev, 0);
2335
2336 ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2337 pdev->name, dev);
2338 if (ret) {
2339 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2340 goto err_iounmap;
2341 }
2342
2343 udc_disable(dev);
2344 udc_reinit(dev);
2345
2346 return 0;
2347
2348 err_iounmap:
2349 iounmap(dev->base);
2350 err_release_mem_region:
2351 release_mem_region(dev->mem->start, resource_size(dev->mem));
2352 err_clk_put:
2353 clk_put(dev->clk);
2354 err_device_unregister:
2355 device_unregister(&dev->gadget.dev);
2356 platform_set_drvdata(pdev, NULL);
2357
2358 the_controller = 0;
2359
2360 return ret;
2361 }
2362
2363 static int jz4740_udc_remove(struct platform_device *pdev)
2364 {
2365 struct jz4740_udc *dev = platform_get_drvdata(pdev);
2366
2367 if (dev->driver)
2368 return -EBUSY;
2369
2370 udc_disable(dev);
2371
2372 free_irq(dev->irq, dev);
2373 iounmap(dev->base);
2374 release_mem_region(dev->mem->start, resource_size(dev->mem));
2375 clk_put(dev->clk);
2376
2377 platform_set_drvdata(pdev, NULL);
2378 device_unregister(&dev->gadget.dev);
2379 the_controller = NULL;
2380
2381 return 0;
2382 }
2383
2384 static struct platform_driver udc_driver = {
2385 .probe = jz4740_udc_probe,
2386 .remove = jz4740_udc_remove,
2387 .driver = {
2388 .name = "jz-udc",
2389 .owner = THIS_MODULE,
2390 },
2391 };
2392
2393 /*-------------------------------------------------------------------------*/
2394
2395 static int __init udc_init (void)
2396 {
2397 return platform_driver_register(&udc_driver);
2398 }
2399
2400 static void __exit udc_exit (void)
2401 {
2402 platform_driver_unregister(&udc_driver);
2403 }
2404
2405 module_init(udc_init);
2406 module_exit(udc_exit);
2407
2408 MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2409 MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2410 MODULE_LICENSE("GPL");
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