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[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 003-bcm47xx_cache_fixes.patch
1 diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
2 --- linux.old/arch/mips/kernel/entry.S 2005-06-26 16:27:01.000000000 +0200
3 +++ linux.dev/arch/mips/kernel/entry.S 2005-06-29 20:24:54.000000000 +0200
4 @@ -100,6 +100,10 @@
5 * and R4400 SC and MC versions.
6 */
7 NESTED(except_vec3_generic, 0, sp)
8 +#ifdef CONFIG_BCM4710
9 + nop
10 + nop
11 +#endif
12 #if R5432_CP0_INTERRUPT_WAR
13 mfc0 k0, CP0_INDEX
14 #endif
15 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16 --- linux.old/arch/mips/mm/c-r4k.c 2005-06-26 16:27:01.000000000 +0200
17 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-30 22:24:29.000000000 +0200
18 @@ -14,6 +14,12 @@
19 #include <linux/mm.h>
20 #include <linux/bitops.h>
21
22 +#ifdef CONFIG_BCM4710
23 +#include "../bcm947xx/include/typedefs.h"
24 +#include "../bcm947xx/include/sbconfig.h"
25 +#include <asm/paccess.h>
26 +#endif
27 +
28 #include <asm/bcache.h>
29 #include <asm/bootinfo.h>
30 #include <asm/cacheops.h>
31 @@ -40,6 +46,7 @@
32 .bc_inv = (void *)no_sc_noop
33 };
34
35 +static int bcm4710 = 0;
36 struct bcache_ops *bcops = &no_sc_ops;
37
38 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
39 @@ -266,6 +273,7 @@
40 r4k_blast_dcache();
41 r4k_blast_icache();
42
43 + if (!bcm4710)
44 switch (current_cpu_data.cputype) {
45 case CPU_R4000SC:
46 case CPU_R4000MC:
47 @@ -304,10 +312,10 @@
48 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
49 * only flush the primary caches but R10000 and R12000 behave sane ...
50 */
51 - if (current_cpu_data.cputype == CPU_R4000SC ||
52 + if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
53 current_cpu_data.cputype == CPU_R4000MC ||
54 current_cpu_data.cputype == CPU_R4400SC ||
55 - current_cpu_data.cputype == CPU_R4400MC)
56 + current_cpu_data.cputype == CPU_R4400MC))
57 r4k_blast_scache();
58 }
59
60 @@ -383,12 +391,15 @@
61 unsigned long ic_lsize = current_cpu_data.icache.linesz;
62 unsigned long addr, aend;
63
64 + addr = start & ~(dc_lsize - 1);
65 + aend = (end - 1) & ~(dc_lsize - 1);
66 +
67 if (!cpu_has_ic_fills_f_dc) {
68 if (end - start > dcache_size)
69 r4k_blast_dcache();
70 else {
71 - addr = start & ~(dc_lsize - 1);
72 - aend = (end - 1) & ~(dc_lsize - 1);
73 + BCM4710_PROTECTED_FILL_TLB(addr);
74 + BCM4710_PROTECTED_FILL_TLB(aend);
75
76 while (1) {
77 /* Hit_Writeback_Inv_D */
78 @@ -403,8 +414,6 @@
79 if (end - start > icache_size)
80 r4k_blast_icache();
81 else {
82 - addr = start & ~(ic_lsize - 1);
83 - aend = (end - 1) & ~(ic_lsize - 1);
84 while (1) {
85 /* Hit_Invalidate_I */
86 protected_flush_icache_line(addr);
87 @@ -443,7 +452,8 @@
88 if (cpu_has_subset_pcaches) {
89 unsigned long addr = (unsigned long) page_address(page);
90
91 - r4k_blast_scache_page(addr);
92 + if (!bcm4710)
93 + r4k_blast_scache_page(addr);
94 ClearPageDcacheDirty(page);
95
96 return;
97 @@ -451,6 +461,7 @@
98
99 if (!cpu_has_ic_fills_f_dc) {
100 unsigned long addr = (unsigned long) page_address(page);
101 +
102 r4k_blast_dcache_page(addr);
103 ClearPageDcacheDirty(page);
104 }
105 @@ -477,7 +488,7 @@
106 /* Catch bad driver code */
107 BUG_ON(size == 0);
108
109 - if (cpu_has_subset_pcaches) {
110 + if (!bcm4710 && cpu_has_subset_pcaches) {
111 unsigned long sc_lsize = current_cpu_data.scache.linesz;
112
113 if (size >= scache_size) {
114 @@ -509,6 +520,8 @@
115 R4600_HIT_CACHEOP_WAR_IMPL;
116 a = addr & ~(dc_lsize - 1);
117 end = (addr + size - 1) & ~(dc_lsize - 1);
118 + BCM4710_FILL_TLB(a);
119 + BCM4710_FILL_TLB(end);
120 while (1) {
121 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
122 if (a == end)
123 @@ -527,7 +540,7 @@
124 /* Catch bad driver code */
125 BUG_ON(size == 0);
126
127 - if (cpu_has_subset_pcaches) {
128 + if (!bcm4710 && (cpu_has_subset_pcaches)) {
129 unsigned long sc_lsize = current_cpu_data.scache.linesz;
130
131 if (size >= scache_size) {
132 @@ -554,6 +567,8 @@
133 R4600_HIT_CACHEOP_WAR_IMPL;
134 a = addr & ~(dc_lsize - 1);
135 end = (addr + size - 1) & ~(dc_lsize - 1);
136 + BCM4710_FILL_TLB(a);
137 + BCM4710_FILL_TLB(end);
138 while (1) {
139 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
140 if (a == end)
141 @@ -577,6 +592,8 @@
142 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
143
144 R4600_HIT_CACHEOP_WAR_IMPL;
145 + BCM4710_PROTECTED_FILL_TLB(addr);
146 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
147 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
148 protected_flush_icache_line(addr & ~(ic_lsize - 1));
149 if (MIPS4K_ICACHE_REFILL_WAR) {
150 @@ -986,10 +1003,12 @@
151 case CPU_R4000MC:
152 case CPU_R4400SC:
153 case CPU_R4400MC:
154 - probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
155 - sc_present = probe_scache_kseg1(config);
156 - if (sc_present)
157 - c->options |= MIPS_CPU_CACHE_CDEX_S;
158 + if (!bcm4710) {
159 + probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
160 + sc_present = probe_scache_kseg1(config);
161 + if (sc_present)
162 + c->options |= MIPS_CPU_CACHE_CDEX_S;
163 + }
164 break;
165
166 case CPU_R10000:
167 @@ -1041,6 +1060,19 @@
168 static inline void coherency_setup(void)
169 {
170 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
171 +
172 +#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
173 + if (BCM330X(current_cpu_data.processor_id)) {
174 + uint32 cm;
175 +
176 + cm = read_c0_diag();
177 + /* Enable icache */
178 + cm |= (1 << 31);
179 + /* Enable dcache */
180 + cm |= (1 << 30);
181 + write_c0_diag(cm);
182 + }
183 +#endif
184
185 /*
186 * c0_status.cu=0 specifies that updates by the sc instruction use
187 @@ -1062,6 +1094,42 @@
188
189 }
190
191 +#ifdef CONFIG_BCM4704
192 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
193 +{
194 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
195 + int i;
196 + for (i = 0; i < nbytes; i += ic_lsize)
197 + fill_icache_line((addr + i));
198 +}
199 +
200 +/*
201 + * This must be run from the cache on 4704A0
202 + * so there are no mips core BIU ops in progress
203 + * when the PFC is enabled.
204 + */
205 +#define PFC_CR0 0xff400000 /* control reg 0 */
206 +#define PFC_CR1 0xff400004 /* control reg 1 */
207 +static void __init enable_pfc(u32 mode)
208 +{
209 + /* write range */
210 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
211 +
212 + /* enable */
213 + *(volatile u32 *)PFC_CR0 = mode;
214 +}
215 +
216 +void check_enable_mips_pfc(int val)
217 +{
218 + /* enable prefetch cache */
219 + if (BCM330X(current_cpu_data.processor_id)
220 + && (read_c0_diag() & (1 << 29))) {
221 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
222 + enable_pfc(val);
223 + }
224 +}
225 +#endif
226 +
227 void __init ld_mmu_r4xx0(void)
228 {
229 extern void build_clear_page(void);
230 @@ -1073,6 +1141,11 @@
231 memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
232 memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
233
234 + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0)
235 + bcm4710 = 1;
236 + else
237 + bcm4710 = 0;
238 +
239 probe_pcache();
240 setup_scache();
241
242 @@ -1117,47 +1190,9 @@
243
244 build_clear_page();
245 build_copy_page();
246 -}
247 -
248 -#ifdef CONFIG_BCM4704
249 -static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
250 -{
251 - unsigned long ic_lsize = current_cpu_data.icache.linesz;
252 - int i;
253 - for (i = 0; i < nbytes; i += ic_lsize)
254 - fill_icache_line((addr + i));
255 -}
256 -
257 -/*
258 - * This must be run from the cache on 4704A0
259 - * so there are no mips core BIU ops in progress
260 - * when the PFC is enabled.
261 - */
262 -#define PFC_CR0 0xff400000 /* control reg 0 */
263 -#define PFC_CR1 0xff400004 /* control reg 1 */
264 -static void __init enable_pfc(u32 mode)
265 -{
266 - /* write range */
267 - *(volatile u32 *)PFC_CR1 = 0xffff0000;
268 -
269 - /* enable */
270 - *(volatile u32 *)PFC_CR0 = mode;
271 -}
272 -#endif
273 -
274 -
275 -void check_enable_mips_pfc(int val)
276 -{
277 -
278 +
279 #ifdef CONFIG_BCM4704
280 - struct cpuinfo_mips *c = &current_cpu_data;
281 -
282 - /* enable prefetch cache */
283 - if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
284 - && (read_c0_diag() & (1 << 29))) {
285 - mips32_icache_fill((unsigned long) &enable_pfc, 64);
286 - enable_pfc(val);
287 - }
288 + check_enable_mips_pfc(0x15);
289 #endif
290 }
291
292 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
293 --- linux.old/arch/mips/mm/tlb-r4k.c 2005-06-26 16:24:26.000000000 +0200
294 +++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-06-29 20:29:16.000000000 +0200
295 @@ -38,6 +38,7 @@
296 old_ctx = read_c0_entryhi();
297 write_c0_entrylo0(0);
298 write_c0_entrylo1(0);
299 + BARRIER;
300
301 entry = read_c0_wired();
302
303 @@ -47,6 +48,7 @@
304 write_c0_index(entry);
305 mtc0_tlbw_hazard();
306 tlb_write_indexed();
307 + BARRIER;
308 entry++;
309 }
310 tlbw_use_hazard();
311 @@ -98,6 +100,7 @@
312 write_c0_entryhi(KSEG0 + idx*0x2000);
313 mtc0_tlbw_hazard();
314 tlb_write_indexed();
315 + BARRIER;
316 }
317 tlbw_use_hazard();
318 write_c0_entryhi(oldpid);
319 @@ -136,6 +139,7 @@
320 tlbw_use_hazard();
321
322 finish:
323 + BARRIER;
324 write_c0_entryhi(oldpid);
325 local_irq_restore(flags);
326 }
327 @@ -204,6 +208,7 @@
328 pmdp = pmd_offset(pgdp, address);
329 idx = read_c0_index();
330 ptep = pte_offset(pmdp, address);
331 + BARRIER;
332 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
333 write_c0_entrylo0(ptep->pte_high);
334 ptep++;
335 @@ -220,6 +225,7 @@
336 tlb_write_indexed();
337 tlbw_use_hazard();
338 write_c0_entryhi(pid);
339 + BARRIER;
340 local_irq_restore(flags);
341 }
342
343 @@ -317,6 +323,7 @@
344 }
345
346 write_c0_index(temp_tlb_entry);
347 + BARRIER;
348 write_c0_pagemask(pagemask);
349 write_c0_entryhi(entryhi);
350 write_c0_entrylo0(entrylo0);
351 diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
352 --- linux.old/arch/mips/mm/tlbex-mips32.S 2005-06-26 16:27:01.000000000 +0200
353 +++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-06-29 20:24:54.000000000 +0200
354 @@ -90,6 +90,9 @@
355 .set noat
356 LEAF(except_vec0_r4000)
357 .set mips3
358 +#ifdef CONFIG_BCM4704
359 + nop
360 +#endif
361 #ifdef CONFIG_SMP
362 mfc0 k1, CP0_CONTEXT
363 la k0, pgd_current
364 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
365 --- linux.old/include/asm-mips/r4kcache.h 2005-06-26 16:27:01.000000000 +0200
366 +++ linux.dev/include/asm-mips/r4kcache.h 2005-06-30 22:39:42.000000000 +0200
367 @@ -15,6 +15,18 @@
368 #include <asm/asm.h>
369 #include <asm/cacheops.h>
370
371 +#ifdef CONFIG_BCM4710
372 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
373 +
374 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
375 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
376 +#else
377 +#define BCM4710_DUMMY_RREG()
378 +
379 +#define BCM4710_FILL_TLB(addr)
380 +#define BCM4710_PROTECTED_FILL_TLB(addr)
381 +#endif
382 +
383 #define cache_op(op,addr) \
384 __asm__ __volatile__( \
385 " .set noreorder \n" \
386 @@ -32,6 +44,7 @@
387
388 static inline void flush_dcache_line_indexed(unsigned long addr)
389 {
390 + BCM4710_DUMMY_RREG();
391 cache_op(Index_Writeback_Inv_D, addr);
392 }
393
394 @@ -47,6 +60,7 @@
395
396 static inline void flush_dcache_line(unsigned long addr)
397 {
398 + BCM4710_DUMMY_RREG();
399 cache_op(Hit_Writeback_Inv_D, addr);
400 }
401
402 @@ -91,6 +105,7 @@
403 */
404 static inline void protected_writeback_dcache_line(unsigned long addr)
405 {
406 + BCM4710_DUMMY_RREG();
407 __asm__ __volatile__(
408 ".set noreorder\n\t"
409 ".set mips3\n"
410 @@ -148,8 +163,10 @@
411 unsigned long ws, addr;
412
413 for (ws = 0; ws < ws_end; ws += ws_inc)
414 - for (addr = start; addr < end; addr += 0x200)
415 + for (addr = start; addr < end; addr += 0x200) {
416 + BCM4710_DUMMY_RREG();
417 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
418 + }
419 }
420
421 static inline void blast_dcache16_page(unsigned long page)
422 @@ -157,7 +174,9 @@
423 unsigned long start = page;
424 unsigned long end = start + PAGE_SIZE;
425
426 + BCM4710_FILL_TLB(start);
427 do {
428 + BCM4710_DUMMY_RREG();
429 cache16_unroll32(start,Hit_Writeback_Inv_D);
430 start += 0x200;
431 } while (start < end);
432 @@ -173,8 +192,10 @@
433 unsigned long ws, addr;
434
435 for (ws = 0; ws < ws_end; ws += ws_inc)
436 - for (addr = start; addr < end; addr += 0x200)
437 + for (addr = start; addr < end; addr += 0x200) {
438 + BCM4710_DUMMY_RREG();
439 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
440 + }
441 }
442
443 static inline void blast_icache16(void)
444 @@ -196,6 +217,7 @@
445 unsigned long start = page;
446 unsigned long end = start + PAGE_SIZE;
447
448 + BCM4710_FILL_TLB(start);
449 do {
450 cache16_unroll32(start,Hit_Invalidate_I);
451 start += 0x200;
452 @@ -281,6 +303,7 @@
453 : "r" (base), \
454 "i" (op));
455
456 +
457 static inline void blast_dcache32(void)
458 {
459 unsigned long start = KSEG0;
460 @@ -291,8 +314,10 @@
461 unsigned long ws, addr;
462
463 for (ws = 0; ws < ws_end; ws += ws_inc)
464 - for (addr = start; addr < end; addr += 0x400)
465 + for (addr = start; addr < end; addr += 0x400) {
466 + BCM4710_DUMMY_RREG();
467 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
468 + }
469 }
470
471 static inline void blast_dcache32_page(unsigned long page)
472 @@ -300,7 +325,9 @@
473 unsigned long start = page;
474 unsigned long end = start + PAGE_SIZE;
475
476 + BCM4710_FILL_TLB(start);
477 do {
478 + BCM4710_DUMMY_RREG();
479 cache32_unroll32(start,Hit_Writeback_Inv_D);
480 start += 0x400;
481 } while (start < end);
482 @@ -316,8 +343,10 @@
483 unsigned long ws, addr;
484
485 for (ws = 0; ws < ws_end; ws += ws_inc)
486 - for (addr = start; addr < end; addr += 0x400)
487 + for (addr = start; addr < end; addr += 0x400) {
488 + BCM4710_DUMMY_RREG();
489 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
490 + }
491 }
492
493 static inline void blast_icache32(void)
494 @@ -339,6 +368,7 @@
495 unsigned long start = page;
496 unsigned long end = start + PAGE_SIZE;
497
498 + BCM4710_FILL_TLB(start);
499 do {
500 cache32_unroll32(start,Hit_Invalidate_I);
501 start += 0x400;
502 @@ -443,6 +473,7 @@
503 unsigned long start = page;
504 unsigned long end = start + PAGE_SIZE;
505
506 + BCM4710_FILL_TLB(start);
507 do {
508 cache64_unroll32(start,Hit_Invalidate_I);
509 start += 0x800;
510 diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
511 --- linux.old/include/asm-mips/stackframe.h 2005-06-26 16:27:01.000000000 +0200
512 +++ linux.dev/include/asm-mips/stackframe.h 2005-06-30 19:04:46.000000000 +0200
513 @@ -172,6 +172,46 @@
514 rfe; \
515 .set pop
516
517 +#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
518 +
519 +#define RESTORE_SOME \
520 + .set push; \
521 + .set reorder; \
522 + mfc0 t0, CP0_STATUS; \
523 + .set pop; \
524 + ori t0, 0x1f; \
525 + xori t0, 0x1f; \
526 + mtc0 t0, CP0_STATUS; \
527 + li v1, 0xff00; \
528 + and t0, v1; \
529 + lw v0, PT_STATUS(sp); \
530 + nor v1, $0, v1; \
531 + and v0, v1; \
532 + or v0, t0; \
533 + ori v1, v0, ST0_IE; \
534 + xori v1, v1, ST0_IE; \
535 + mtc0 v1, CP0_STATUS; \
536 + mtc0 v0, CP0_STATUS; \
537 + lw v1, PT_EPC(sp); \
538 + mtc0 v1, CP0_EPC; \
539 + lw $31, PT_R31(sp); \
540 + lw $28, PT_R28(sp); \
541 + lw $25, PT_R25(sp); \
542 + lw $7, PT_R7(sp); \
543 + lw $6, PT_R6(sp); \
544 + lw $5, PT_R5(sp); \
545 + lw $4, PT_R4(sp); \
546 + lw $3, PT_R3(sp); \
547 + lw $2, PT_R2(sp)
548 +
549 +#define RESTORE_SP_AND_RET \
550 + lw sp, PT_R29(sp); \
551 + nop; \
552 + nop; \
553 + .set mips3; \
554 + eret; \
555 + .set mips0
556 +
557 #else
558
559 #define RESTORE_SOME \
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