target/linux/at91-2.6/patches/009-fdl-uartinit.patch

   1 diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c linux-2.6.19.2/arch/arm/mach-at91rm9200/at91rm9200_devices.c
   2 --- linux-2.6.19.2.old/arch/arm/mach-at91rm9200/at91rm9200_devices.c    2007-05-01 13:08:02.000000000 +0200
   3 +++ linux-2.6.19.2/arch/arm/mach-at91rm9200/at91rm9200_devices.c        2007-05-09 12:59:58.000000000 +0200
   4 @@ -709,6 +709,10 @@
   5          *  We need to drive the pin manually.  Default is off (RTS is active low).
   6          */
   7         at91_set_gpio_output(AT91_PIN_PA21, 1);
   8 +       at91_set_gpio_output(AT91_PIN_PB6, 1);  /* DTR0 */
   9 +       at91_set_gpio_output(AT91_PIN_PB7, 1);  /* RI0 */
  10 +       at91_set_gpio_input(AT91_PIN_PA19, 1);  /* DCD0 */
  11 +       at91_set_deglitch(AT91_PIN_PA19, 1);
  12  }
  13
  14  static struct resource uart1_resources[] = {
  15 @@ -820,6 +824,12 @@
  16  {
  17         at91_set_B_periph(AT91_PIN_PA5, 1);             /* TXD3 */
  18         at91_set_B_periph(AT91_PIN_PA6, 0);             /* RXD3 */
  19 +       at91_set_B_periph(AT91_PIN_PB0, 0);             /* RTS3 */
  20 +       at91_set_B_periph(AT91_PIN_PB1, 0);             /* CTS3 */
  21 +       at91_set_gpio_output(AT91_PIN_PB29, 1); /* DTR0 */
  22 +       at91_set_gpio_output(AT91_PIN_PB2, 1);  /* RI0 */
  23 +       at91_set_gpio_input(AT91_PIN_PA24, 1);  /* DCD0 */
  24 +       at91_set_deglitch(AT91_PIN_PA24, 1);
  25  }
  26
  27  struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
  28 diff -urN linux-2.6.19.2.old/arch/arm/mach-at91rm9200/vlink_leds.c linux-2.6.19.2/arch/arm/mach-at91rm9200/vlink_leds.c
  29 --- linux-2.6.19.2.old/arch/arm/mach-at91rm9200/vlink_leds.c    2007-05-01 13:08:03.000000000 +0200
  30 +++ linux-2.6.19.2/arch/arm/mach-at91rm9200/vlink_leds.c        2007-05-09 12:58:42.000000000 +0200
  31 @@ -114,12 +114,6 @@
  32
  33         at91_set_gpio_input(AT91_PIN_PB8, 1);   // JIGPRESENT
  34         at91_set_gpio_input(AT91_PIN_PB22, 1);  // PWR_IND
  35 -       at91_set_gpio_input(AT91_PIN_PA19, 1);  // P1DTR
  36 -       at91_set_gpio_input(AT91_PIN_PA24, 1);  // P2DTR
  37 -       at91_set_gpio_output(AT91_PIN_PB29, 1); // P2DCD
  38 -       at91_set_gpio_output(AT91_PIN_PB2, 1);  // P2RI
  39 -       at91_set_gpio_output(AT91_PIN_PB6, 1);  // P1DCD
  40 -       at91_set_gpio_output(AT91_PIN_PB7, 1);  // P1RI
  41
  42         at91_set_gpio_input(AT91_PIN_PB27, 1);  // UDB_CNX
  43         at91_set_gpio_output(AT91_PIN_PB28, 1); // UDB_PUP