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add ar7 adsl driver support
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN kernel-base/arch/mips/ar7/ar7/ar7_jump.S kernel-current/arch/mips/ar7/ar7/ar7_jump.S
2 --- kernel-base/arch/mips/ar7/ar7/ar7_jump.S 1970-01-01 01:00:00.000000000 +0100
3 +++ kernel-current/arch/mips/ar7/ar7/ar7_jump.S 2005-07-10 06:40:39.582267168 +0200
4 @@ -0,0 +1,89 @@
5 +/*
6 + * $Id$
7 + * Copyright (C) $Date$ $Author$
8 + *
9 + * This program is free software; you can redistribute it and/or modify
10 + * it under the terms of the GNU General Public License as published by
11 + * the Free Software Foundation; either version 2 of the License, or
12 + * (at your option) any later version.
13 + *
14 + * This program is distributed in the hope that it will be useful,
15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 + * GNU General Public License for more details.
18 + *
19 + * You should have received a copy of the GNU General Public License
20 + * along with this program; if not, write to the Free Software
21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 + *
23 + */
24 +
25 +#include <linux/config.h>
26 +#include <linux/threads.h>
27 +
28 +#include <asm/asm.h>
29 +#include <asm/cacheops.h>
30 +#include <asm/current.h>
31 +#include <asm/offset.h>
32 +#include <asm/processor.h>
33 +#include <asm/regdef.h>
34 +#include <asm/cachectl.h>
35 +#include <asm/mipsregs.h>
36 +#include <asm/stackframe.h>
37 +
38 +.text
39 +
40 +.set noreorder
41 +.set noat
42 +
43 +/* TLB Miss Vector */
44 +
45 +LEAF(jump_tlb_miss)
46 + .set mips2
47 + lui k0,0x9400
48 + ori k0,0
49 + jr k0
50 + nop
51 +END(jump_tlb_miss)
52 +
53 + /* Unused TLB Miss Vector */
54 +
55 +LEAF(jump_tlb_miss_unused)
56 + .set mips2
57 + lui k0,0x9400
58 + ori k0,0x80
59 + jr k0
60 + nop
61 +END(jump_tlb_miss_unused)
62 +
63 + /* Cache Error Vector */
64 +
65 +LEAF(jump_cache_error)
66 + .set mips2
67 + lui k0,0x9400
68 + ori k0,0x100
69 + jr k0
70 + nop
71 +END(jump_cache_error)
72 +
73 + /* General Exception */
74 +
75 +LEAF(jump_general_exception)
76 + .set mips2
77 + lui k0,0x9400
78 + ori k0,0x180
79 + jr k0
80 + nop
81 +END(jump_general_exception)
82 +
83 + /* Dedicated Interrupt */
84 +
85 +LEAF(jump_dedicated_interrupt)
86 + .set mips2
87 + lui k0,0x9400
88 + ori k0,0x200
89 + jr k0
90 + nop
91 +END(jump_dedicated_interrupt)
92 +
93 + .set at
94 diff -urN kernel-base/arch/mips/ar7/ar7/ar7_paging.c kernel-current/arch/mips/ar7/ar7/ar7_paging.c
95 --- kernel-base/arch/mips/ar7/ar7/ar7_paging.c 1970-01-01 01:00:00.000000000 +0100
96 +++ kernel-current/arch/mips/ar7/ar7/ar7_paging.c 2005-07-10 07:08:33.725758672 +0200
97 @@ -0,0 +1,314 @@
98 +/*
99 + * -*- linux-c -*-
100 + * This file is subject to the terms and conditions of the GNU General Public
101 + * License. See the file "COPYING" in the main directory of this archive
102 + * for more details.
103 + *
104 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
105 + * Copyright (C) 2002 Texas Instruments, Inc.
106 + *
107 + */
108 +
109 +/*
110 + * This file takes care of the "memory hole" issue that exists with the standard
111 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
112 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
113 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
114 + *
115 + * -JAH
116 + */
117 +#include <linux/config.h>
118 +#include <linux/signal.h>
119 +#include <linux/sched.h>
120 +#include <linux/kernel.h>
121 +#include <linux/errno.h>
122 +#include <linux/string.h>
123 +#include <linux/types.h>
124 +#include <linux/ptrace.h>
125 +#include <linux/mman.h>
126 +#include <linux/mm.h>
127 +#include <linux/swap.h>
128 +#include <linux/smp.h>
129 +#include <linux/init.h>
130 +#ifdef CONFIG_BLK_DEV_INITRD
131 +#include <linux/blk.h>
132 +#endif /* CONFIG_BLK_DEV_INITRD */
133 +#include <linux/highmem.h>
134 +#include <linux/bootmem.h>
135 +
136 +#include <asm/processor.h>
137 +#include <asm/system.h>
138 +#include <asm/uaccess.h>
139 +#include <asm/pgtable.h>
140 +#include <asm/pgalloc.h>
141 +#include <asm/mmu_context.h>
142 +#include <asm/io.h>
143 +#include <asm/tlb.h>
144 +#include <asm/cpu.h>
145 +
146 +#define __MEMORY_START CONFIG_AR7_MEMORY
147 +
148 +#ifdef CONFIG_DISCONTIGMEM
149 +pg_data_t discontig_page_data[NR_NODES];
150 +bootmem_data_t discontig_node_bdata[NR_NODES];
151 +#endif
152 +
153 +static unsigned long totalram_pages;
154 +/* static unsigned long totalhigh_pages; */
155 +
156 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
157 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
158 +
159 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
160 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
161 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
162 +
163 +unsigned long bootmap_size;
164 +
165 +extern char *prom_getenv(char *envname);
166 +
167 +/*
168 + * We have upto 8 empty zeroed pages so we can map one of the right colour
169 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
170 + * where we have to avoid VCED / VECI exceptions for good performance at
171 + * any price. Since page is never written to after the initialization we
172 + * don't have to care about aliases on other CPUs.
173 + */
174 +
175 +static inline unsigned long setup_zero_pages(void)
176 +{
177 + unsigned long order, size;
178 + struct page *page;
179 + if(current_cpu_data.options & MIPS_CPU_VCE)
180 + order = 3;
181 + else
182 + order = 0;
183 +
184 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
185 +
186 + if (!empty_zero_page)
187 + panic("Oh boy, that early out of memory?");
188 +
189 + page = virt_to_page(empty_zero_page);
190 +
191 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
192 + set_bit(PG_reserved, &page->flags);
193 + set_page_count(page, 0);
194 + page++;
195 + }
196 +
197 + size = PAGE_SIZE << order;
198 + zero_page_mask = (size - 1) & PAGE_MASK;
199 + memset((void *)empty_zero_page, 0, size);
200 +
201 + return 1UL << order;
202 +}
203 +
204 +/*
205 + * paging_init() sets up the page tables
206 + *
207 + * This routines also unmaps the page at virtual kernel address 0, so
208 + * that we can trap those pesky NULL-reference errors in the kernel.
209 + */
210 +void __init paging_init(void)
211 +{
212 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
213 + unsigned long low, start_pfn;
214 +
215 + /* Initialize the entire pgd. */
216 + pgd_init((unsigned long)swapper_pg_dir);
217 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
218 +
219 +
220 + start_pfn = START_PFN;
221 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
222 + low = MAX_LOW_PFN;
223 +
224 + /* Avalanche DMA-able memory 0x14000000+memsize */
225 +
226 + zones_size[ZONE_DMA] = low - start_pfn;
227 +
228 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
229 +
230 +#ifdef CONFIG_DISCONTIGMEM
231 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
232 + zones_size[ZONE_NORMAL] = 0;
233 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
234 +#endif /* CONFIG_DISCONTIGMEM */
235 +
236 +}
237 +
238 +extern char _ftext, _etext, _fdata, _edata, _end;
239 +extern char __init_begin, __init_end;
240 +
241 +void __init mem_init(void)
242 +{
243 + int codesize, reservedpages, datasize, initsize;
244 + int tmp;
245 +
246 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
247 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
248 +
249 + /* free up the memory associated with Adam2 -
250 + * that is the, after the first page that is
251 + * reserved all the way up to the start of the kernel
252 + */
253 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
254 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
255 +
256 + /* this will put all low memory onto the freelists */
257 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
258 +
259 + /* Setup zeroed pages */
260 + totalram_pages -= setup_zero_pages();
261 +
262 +
263 +#ifdef CONFIG_DISCONTIGMEM
264 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
265 +#endif
266 + reservedpages = 0;
267 + for (tmp = 0; tmp < num_physpages; tmp++)
268 + /*
269 + * Only count reserved RAM pages
270 + */
271 + if (PageReserved(mem_map+tmp))
272 + reservedpages++;
273 +
274 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
275 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
276 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
277 +
278 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
279 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
280 + max_mapnr << (PAGE_SHIFT-10),
281 + codesize >> 10,
282 + reservedpages << (PAGE_SHIFT-10),
283 + datasize >> 10,
284 + initsize >> 10);
285 +
286 +}
287 +
288 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
289 +
290 +void avalanche_bootmem_init(void)
291 +{
292 + unsigned long start_pfn, max_pfn;
293 + unsigned long max_low_pfn;
294 + unsigned int memsize,memory_end,memory_start;
295 + char *memsize_str;
296 +
297 + memsize_str = prom_getenv("memsize");
298 + if (!memsize_str) {
299 + memsize = 0x02000000;
300 + } else {
301 + memsize = simple_strtol(memsize_str, NULL, 0);
302 + }
303 +
304 +
305 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
306 + memory_end = memory_start + memsize;
307 +
308 + /*
309 + * Find the highest memory page fram number we have available
310 + */
311 +
312 + max_pfn = PFN_DOWN(__pa(memory_end));
313 +
314 + /*
315 + * Determine the low and high memory ranges
316 + */
317 +
318 + max_low_pfn = max_pfn;
319 +
320 + /*
321 + * Partially used pages are not usable - thus we are
322 + * rounding upwards:
323 + */
324 +
325 + start_pfn = PFN_UP(__pa(&_end));
326 +
327 + /*
328 + * Find a proper area for the bootmem bitmap. After this
329 + * bootstrap step all allocations (until the page allocator is
330 + * intact) must be done via bootmem_alloc().
331 + */
332 +
333 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
334 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
335 +
336 +
337 + /*
338 + * Register fully available low RAM pages with the bootmem allocator.
339 + */
340 +
341 + {
342 + unsigned long curr_pfn, last_pfn, pages;
343 +
344 + /*
345 + * We are rounding up the start address of usable memory:
346 + */
347 + curr_pfn = PFN_UP(__MEMORY_START);
348 +
349 + /*
350 + * ... and at the end of the usable range downwards:
351 + */
352 + last_pfn = PFN_DOWN(__pa(memory_end));
353 +
354 + if (last_pfn > max_low_pfn)
355 + last_pfn = max_low_pfn;
356 +
357 + pages = last_pfn - curr_pfn;
358 +
359 +
360 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
361 + PFN_PHYS(pages));
362 + }
363 +
364 + /*
365 + * Reserve the kernel text and
366 + * Reserve the bootmem bitmap. We do this in two steps (first step
367 + * was init_bootmem()), because this catches the (definitely buggy)
368 + * case of us accidentally initializing the bootmem allocator with
369 + * an invalid RAM area.
370 + */
371 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
372 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
373 +
374 + /*
375 + * reserve physical page 0 - it's a special BIOS page on many boxes,
376 + * enabling clean reboots, SMP operation, laptop functions.
377 + */
378 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
379 +}
380 +
381 +extern char __init_begin, __init_end;
382 +
383 +void free_initmem(void)
384 +{
385 + unsigned long addr;
386 + // prom_free_prom_memory ();
387 +
388 + addr = (unsigned long) &__init_begin;
389 + while (addr < (unsigned long) &__init_end) {
390 + ClearPageReserved(virt_to_page(addr));
391 + set_page_count(virt_to_page(addr), 1);
392 + free_page(addr);
393 + totalram_pages++;
394 + addr += PAGE_SIZE;
395 + }
396 + printk("Freeing unused kernel memory: %dk freed\n",
397 + (&__init_end - &__init_begin) >> 10);
398 +}
399 +
400 +void si_meminfo(struct sysinfo *val)
401 +{
402 + val->totalram = totalram_pages;
403 + val->sharedram = 0;
404 + val->freeram = nr_free_pages();
405 + val->bufferram = atomic_read(&buffermem_pages);
406 + val->totalhigh = 0;
407 + val->freehigh = nr_free_highpages();
408 + val->mem_unit = PAGE_SIZE;
409 +
410 + return;
411 +}
412 diff -urN kernel-base/arch/mips/ar7/ar7/gpio.c kernel-current/arch/mips/ar7/ar7/gpio.c
413 --- kernel-base/arch/mips/ar7/ar7/gpio.c 1970-01-01 01:00:00.000000000 +0100
414 +++ kernel-current/arch/mips/ar7/ar7/gpio.c 2005-07-10 09:46:52.164776456 +0200
415 @@ -0,0 +1,132 @@
416 +#include <linux/kernel.h>
417 +#include <asm/uaccess.h>
418 +#include <linux/spinlock.h>
419 +#include <linux/proc_fs.h>
420 +#include <linux/fs.h>
421 +#include <linux/timer.h>
422 +#include <linux/module.h>
423 +#include <linux/stddef.h>
424 +
425 +#include <asm/ar7/tnetd73xx_err.h>
426 +#include <asm/ar7/tnetd73xx_misc.h>
427 +#include <asm/ar7/ledapp.h>
428 +
429 +
430 +#if defined (CONFIG_AR7RD) || defined(CONFIG_AR7WRD)
431 +
432 +#define AR7_RESET_FILE "led_mod/ar7reset"
433 +#define AR7_RESET_GPIO 11
434 +#define RESET_POLL_TIME 1
435 +#define RESET_HOLD_TIME 4
436 +#define NO_OF_LEDS
437 +#define TRUE 1
438 +#define FALSE 0
439 +
440 +static struct proc_dir_entry *reset_file;
441 +static int res_state = 0;
442 +static int count;
443 +static struct timer_list *pTimer = NULL;
444 +static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
445 +
446 +struct file_operations reset_fops = {
447 + read:proc_read_reset_fops
448 +};
449 +
450 +#endif
451 +
452 +static spinlock_t device_lock;
453 +led_reg_t temp[15];
454 +
455 +static void gpio_led_on(unsigned long param)
456 +{
457 + unsigned int flags;
458 +
459 + spin_lock_irqsave(&device_lock, flags);
460 + tnetd73xx_gpio_out(param, FALSE);
461 + spin_unlock_irqrestore(&device_lock, flags);
462 +}
463 +
464 +static void gpio_led_off(unsigned long param)
465 +{
466 + unsigned int flags = 0x00;
467 +
468 + spin_lock_irqsave(&device_lock, flags);
469 + tnetd73xx_gpio_out(param, TRUE);
470 + spin_unlock_irqrestore(&device_lock, flags);
471 +}
472 +
473 +static void gpio_led_init(unsigned long param)
474 +{
475 + tnetd73xx_gpio_ctrl(param, GPIO_PIN, GPIO_OUTPUT_PIN);
476 +}
477 +
478 +static void board_gpio_reset(void)
479 +{
480 + tnetd73xx_gpio_init();
481 +
482 + /* Initialize the link mask */
483 + device_lock = SPIN_LOCK_UNLOCKED;
484 + return;
485 +}
486 +
487 +#if defined(CONFIG_AR7WRD)
488 +
489 +static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp)
490 +{
491 + char *pdata = NULL;
492 + char line[3];
493 + int len = 0;
494 + if (*offp != 0)
495 + return 0;
496 +
497 + pdata = buf;
498 + len = sprintf(line, "%d\n", res_state);
499 + res_state = 0;
500 + copy_to_user(buf, line, len);
501 + *offp = len;
502 + return len;
503 +}
504 +
505 +static void reset_timer_func(unsigned long data)
506 +{
507 + count = (tnetd73xx_gpio_in(AR7_RESET_GPIO) == 0) ? count + 1 : 0;
508 + if (count >= RESET_HOLD_TIME / RESET_POLL_TIME)
509 + res_state = 1;
510 + pTimer->expires = jiffies + HZ * RESET_POLL_TIME;
511 + add_timer(pTimer);
512 + return;
513 +}
514 +
515 +static void reset_init(void)
516 +{
517 + /* Create board reset proc file */
518 + reset_file = create_proc_entry(AR7_RESET_FILE, 0777, NULL);
519 + if (reset_file == NULL)
520 + goto reset_file;
521 + reset_file->owner = THIS_MODULE;
522 + reset_file->proc_fops = &reset_fops;
523 +
524 + /* Initialise GPIO 11 for input */
525 + tnetd73xx_gpio_ctrl(AR7_RESET_GPIO, GPIO_PIN, GPIO_INPUT_PIN);
526 +
527 + /* Create a timer which fires every seconds */
528 + pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
529 + init_timer(pTimer);
530 + pTimer->function = reset_timer_func;
531 + pTimer->data = 0;
532 + /* Start the timer */
533 + reset_timer_func(0);
534 + return;
535 +
536 + reset_file:
537 + remove_proc_entry(AR7_RESET_FILE, NULL);
538 + return;
539 +}
540 +#endif
541 +
542 +
543 +void board_gpio_init(void)
544 +{
545 + board_gpio_reset();
546 + return;
547 +}
548 diff -urN kernel-base/arch/mips/ar7/ar7/ledmod.c kernel-current/arch/mips/ar7/ar7/ledmod.c
549 --- kernel-base/arch/mips/ar7/ar7/ledmod.c 1970-01-01 01:00:00.000000000 +0100
550 +++ kernel-current/arch/mips/ar7/ar7/ledmod.c 2005-07-10 09:45:36.692250024 +0200
551 @@ -0,0 +1,712 @@
552 +#include <linux/config.h>
553 +#include <linux/init.h>
554 +#include <linux/kernel.h>
555 +#include <linux/proc_fs.h>
556 +#include <asm/uaccess.h>
557 +#include <linux/fs.h>
558 +#include <linux/timer.h>
559 +#include <linux/delay.h>
560 +#include <linux/spinlock.h>
561 +#include <asm/ar7/avalanche_regs.h>
562 +#include <asm/ar7/ledapp.h>
563 +#include <linux/module.h>
564 +
565 +#define LED_ON 1
566 +#define LED_OFF 2
567 +#define LED_BLINK 3
568 +#define LED_FLASH 4
569 +
570 +#define LED_BLINK_UP 5
571 +#define LED_BLINK_DOWN 6
572 +
573 +typedef struct state_entry {
574 + unsigned char mode;
575 + unsigned char led;
576 + void (*handler) (struct state_entry * pState);
577 + unsigned long param;
578 +} state_entry_t;
579 +
580 +typedef struct mod_entry {
581 + state_entry_t *states[MAX_STATE_ID];
582 +} mod_entry_t;
583 +
584 +static mod_entry_t *modArr[MAX_MOD_ID];
585 +static struct proc_dir_entry *led_proc_dir, *led_file;
586 +
587 +/* index of the array is the led number HARDWARE SPECIFIC*/
588 +typedef struct led_data {
589 + led_reg_t *led;
590 + int state;
591 + struct timer_list *pTimer;
592 + unsigned char timer_running;
593 + unsigned long param;
594 +} led_data_t;
595 +
596 +led_data_t led_arr[MAX_LED_ID + 1];
597 +/*!!! The last device is actually being used for ar7 reset to factory default */
598 +#if 1
599 +/* Ron add for adsl LED blink */
600 +#define GPIO_ADSL_ACT (1<<6)
601 +#define GPIO_ADSL_DOWN (1<<8)
602 +#define BLINK_FAST 5*HZ/100
603 +#define BLINK_SLOW 15*HZ/100
604 +static struct timer_list my_led_timer;
605 +static int my_blink_count = 0;
606 +static int my_mode = 1;
607 +void led_operation(int mod, int state);
608 +
609 +static void my_led_on(unsigned long gpio, int logic)
610 +{
611 + if (logic > 0)
612 + GPIO_DATA_OUTPUT |= gpio;
613 + else
614 + GPIO_DATA_OUTPUT &= ~gpio;
615 +
616 +}
617 +static void my_led_off(unsigned long gpio, int logic)
618 +{
619 + if (logic > 0)
620 + GPIO_DATA_OUTPUT &= ~gpio;
621 + else
622 + GPIO_DATA_OUTPUT |= gpio;
623 +
624 +}
625 +
626 +static void my_led_init(unsigned long gpio, int init, int logic)
627 +{
628 + GPIO_DATA_ENABLE |= gpio;
629 + GPIO_DATA_DIR &= ~gpio;
630 + if (init)
631 + my_led_on(gpio, logic);
632 + else
633 + my_led_off(gpio, logic);
634 +}
635 +
636 +static void my_led_blink_timer(unsigned long data)
637 +{
638 + unsigned long gpio = GPIO_ADSL_ACT;
639 + unsigned int speed = BLINK_FAST;
640 + if (my_mode == 2) {
641 + gpio = GPIO_ADSL_DOWN;
642 + speed = BLINK_SLOW;
643 + }
644 + if (my_blink_count) {
645 + if (GPIO_DATA_OUTPUT & gpio) {
646 + GPIO_DATA_OUTPUT &= ~gpio;
647 + if (my_mode != 2)
648 + my_blink_count = 0;
649 + } else {
650 + GPIO_DATA_OUTPUT |= gpio;
651 + }
652 + }
653 + my_led_timer.expires = jiffies + speed;
654 + add_timer(&my_led_timer);
655 +}
656 +
657 +/* Ron add for ADSL led blink */
658 +#endif
659 +static spinlock_t config_lock;
660 +
661 +static void board_led_link_up(state_entry_t * pState);
662 +static void board_led_link_down(state_entry_t * pState);
663 +static void board_led_activity_on(state_entry_t * pState);
664 +static void board_led_activity_off(state_entry_t * pState);
665 +static void led_timer_func(unsigned long data);
666 +
667 +extern void board_gpio_init(void);
668 +extern void uart_led_init(void);
669 +
670 +static ssize_t proc_read_led_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
671 +static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp);
672 +static int config_led(unsigned long y);
673 +
674 +struct file_operations led_fops = {
675 + read:proc_read_led_fops,
676 + write:proc_write_led_fops,
677 +};
678 +
679 +static int led_atoi(char *name)
680 +{
681 + int val = 0;
682 + for (;; name++) {
683 + switch (*name) {
684 + case '0'...'9':
685 + val = val * 10 + (*name - '0');
686 + break;
687 + default:
688 + return val;
689 + }
690 + }
691 +}
692 +
693 +static int free_memory(void)
694 +{
695 + int i, j;
696 +
697 + for (i = 0; i < MAX_MOD_ID; i++) {
698 + if (modArr[i] != NULL) {
699 + for (j = 0; j < MAX_STATE_ID; j++) {
700 + if (modArr[i]->states[j] != NULL)
701 + kfree(modArr[i]->states[j]);
702 + }
703 + kfree(modArr[i]);
704 + modArr[i] = NULL;
705 + }
706 + }
707 + return 0;
708 +}
709 +
710 +static int led_on(state_entry_t * pState)
711 +{
712 + if (led_arr[pState->led].led == NULL)
713 + return -1;
714 + led_arr[pState->led].led->onfunc(led_arr[pState->led].led->param);
715 + return 0;
716 +}
717 +
718 +static int led_off(state_entry_t * pState)
719 +{
720 + if (led_arr[pState->led].led == NULL)
721 + return -1;
722 + led_arr[pState->led].led->offfunc(led_arr[pState->led].led->param);
723 + return 0;
724 +}
725 +
726 +static void board_led_link_up(state_entry_t * pState)
727 +{
728 + led_arr[pState->led].state = LED_ON;
729 + if (led_arr[pState->led].timer_running == 0)
730 + led_on(pState);
731 + return;
732 +}
733 +
734 +static void board_led_link_down(state_entry_t * pState)
735 +{
736 + led_arr[pState->led].state = LED_OFF;
737 + if (led_arr[pState->led].timer_running == 0)
738 + led_off(pState);
739 + return;
740 +}
741 +
742 +static void add_led_timer(state_entry_t * pState)
743 +{
744 + led_arr[pState->led].pTimer->expires =
745 + jiffies + HZ * (pState->param) / 1000;
746 + led_arr[pState->led].param = pState->param;
747 + led_arr[pState->led].pTimer->data = pState;
748 + add_timer(led_arr[pState->led].pTimer);
749 +}
750 +
751 +static void board_led_activity_on(state_entry_t * pState)
752 +{
753 + if (led_arr[pState->led].timer_running == 0) {
754 + led_on(pState);
755 + add_led_timer(pState);
756 + led_arr[pState->led].timer_running = 1;
757 + led_arr[pState->led].state = LED_BLINK_UP;
758 + } else if (led_arr[pState->led].timer_running > 0xF0) {
759 + led_arr[pState->led].state = LED_BLINK_UP;
760 + led_arr[pState->led].pTimer->expires =
761 + jiffies + HZ * (pState->param) / 1000;
762 + led_arr[pState->led].param = pState->param;
763 + led_arr[pState->led].pTimer->data = pState;
764 + }
765 + return;
766 +}
767 +
768 +static void board_led_activity_off(state_entry_t * pState)
769 +{
770 + if (led_arr[pState->led].timer_running == 0) {
771 + led_off(pState);
772 + add_led_timer(pState);
773 + led_arr[pState->led].timer_running = 1;
774 + led_arr[pState->led].state = LED_BLINK_UP;
775 + } else if (led_arr[pState->led].timer_running > 0xF0) {
776 + led_arr[pState->led].state = LED_BLINK_UP;
777 + led_arr[pState->led].pTimer->expires =
778 + jiffies + HZ * (pState->param) / 1000;
779 + led_arr[pState->led].param = pState->param;
780 + led_arr[pState->led].pTimer->data = pState;
781 + }
782 + return;
783 +}
784 +
785 +static void board_led_link_flash(state_entry_t * pState)
786 +{
787 + if (led_on(pState))
788 + return;
789 + if (led_arr[pState->led].timer_running == 0)
790 + add_led_timer(pState);
791 + else
792 + led_arr[pState->led].param = pState->param;
793 + led_arr[pState->led].timer_running = 0xFF;
794 + led_arr[pState->led].state = LED_FLASH;
795 + return;
796 +}
797 +
798 +static void led_timer_func(unsigned long data)
799 +{
800 + state_entry_t *pState = NULL;
801 + mod_entry_t *pMod = NULL;
802 + unsigned int flags;
803 +
804 + spin_lock_irqsave(&config_lock, flags);
805 +
806 + pState = (state_entry_t *) data;
807 +
808 + if (led_arr[pState->led].state == LED_BLINK_DOWN) {
809 + led_arr[pState->led].timer_running = 0;
810 + if (pState->mode == 2)
811 + led_arr[pState->led].state = LED_OFF;
812 + else
813 + led_arr[pState->led].state = LED_ON;
814 + } else if (led_arr[pState->led].state == LED_BLINK_UP) {
815 + led_arr[pState->led].pTimer->expires =
816 + jiffies + HZ * (led_arr[pState->led].param) / 1000;
817 + led_arr[pState->led].pTimer->data = pState;
818 + add_timer(led_arr[pState->led].pTimer);
819 + if (pState->mode == 2) {
820 + led_off(pState);
821 + led_arr[pState->led].state = LED_BLINK_DOWN;
822 + } else {
823 + led_on(pState);
824 + led_arr[pState->led].state = LED_BLINK_DOWN;
825 + }
826 + led_arr[pState->led].timer_running = 1;
827 + } else if (led_arr[pState->led].state == LED_FLASH) {
828 + led_arr[pState->led].pTimer->expires =
829 + jiffies + HZ * (led_arr[pState->led].param) / 1000;
830 + led_arr[pState->led].pTimer->data = pState;
831 + add_timer(led_arr[pState->led].pTimer);
832 +
833 + if (led_arr[pState->led].timer_running == 0xFF) {
834 + led_off(pState);
835 + led_arr[pState->led].timer_running--;
836 + } else {
837 + led_on(pState);
838 + led_arr[pState->led].timer_running++;
839 + }
840 + spin_unlock_irqrestore(&config_lock, flags);
841 + return;
842 + } else if (led_arr[pState->led].state == LED_OFF) {
843 + led_off(pState);
844 + led_arr[pState->led].timer_running = 0;
845 + } else if (led_arr[pState->led].state == LED_ON) {
846 + led_on(pState);
847 + led_arr[pState->led].timer_running = 0;
848 + }
849 + spin_unlock_irqrestore(&config_lock, flags);
850 + return;
851 +}
852 +
853 +static ssize_t proc_read_led_fops(struct file *filp,
854 + char *buf, size_t count, loff_t * offp)
855 +{
856 + char *pdata = NULL;
857 + int i = 0, j = 0, len = 0, totallen = 0;
858 + char line[255];
859 +
860 + if (*offp != 0)
861 + return 0;
862 +
863 + pdata = buf;
864 + len += sprintf(line, "LEDS Registered for use are:");
865 + for (i = 0; i < MAX_LED_ID; i++)
866 + if (led_arr[i].led != NULL)
867 + len += sprintf(&line[len], " %d ", i);
868 + line[len++] = '\n';
869 +
870 + copy_to_user(pdata, line, len);
871 + pdata += len;
872 + totallen += len;
873 + len = 0;
874 + len = sprintf(line, "USER MODULE INFORMATION:\n");
875 + copy_to_user(pdata, line, len);
876 + pdata += len;
877 + totallen += len;
878 + len = 0;
879 + for (i = 0; i < MAX_MOD_ID; i++) {
880 + if (modArr[i] != NULL) {
881 + len = sprintf(line, " Module ID = %d \n", i);
882 + copy_to_user(pdata, line, len);
883 + pdata += len;
884 + totallen += len;
885 + len = 0;
886 + for (j = 0; j < MAX_STATE_ID; j++) {
887 + if (modArr[i]->states[j] != NULL) {
888 + len = sprintf(line, " State = %d , Led = %d,", j,
889 + modArr[i]->states[j]->led);
890 + copy_to_user(pdata, line, len);
891 + pdata += len;
892 + totallen += len;
893 +
894 + len = 0;
895 + switch (modArr[i]->states[j]->mode) {
896 + case 1:
897 + len = sprintf(line, " Mode = OFF\n");
898 + break;
899 + case 2:
900 + len = sprintf(line, " Mode = BLINK_ON , On Time(ms) = %d\n",
901 + (unsigned int) modArr[i]->states[j]->
902 + param);
903 + break;
904 + case 3:
905 + len = sprintf(line, " Mode = BLINK_OFF , Off Time(ms) = %d\n",
906 + (unsigned int) modArr[i]->states[j]->
907 + param);
908 + break;
909 + case 4:
910 + len = sprintf(line, " Mode = ON \n");
911 + break;
912 + case 5:
913 + len = sprintf(line, " Mode = FLASH , Time Period(ms) = %d\n",
914 + (unsigned int) modArr[i]->states[j]->
915 + param);
916 + break;
917 + default:
918 + break;
919 +
920 + }
921 + copy_to_user(pdata, line, len);
922 + pdata += len;
923 + totallen += len;
924 +
925 + len = 0;
926 + }
927 + }
928 + }
929 + }
930 + /* Return with configuration information for LEDs */
931 + *offp = totallen;
932 + return totallen;
933 +}
934 +
935 +static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp)
936 +{
937 + char *pdata = NULL, *ptemp = NULL;
938 + char line[10], temp[10];
939 + int i = 0;
940 + int mod = 0xFFFF, state = 0xFFFF;
941 + int flag = 0;
942 +
943 + /* Check if this write is for configuring stuff */
944 + if (*(int *) (buffer) == 0xFFEEDDCC) {
945 + printk("<1>proc write:Calling Configuration\n");
946 + config_led((unsigned long) (buffer + sizeof(int)));
947 + return count;
948 + }
949 +
950 + if (count >= 10) {
951 + printk("<1>proc write:Input too long,max length = %d\n", 10);
952 + return count;
953 + }
954 + memset(temp, 0x00, 10);
955 + memset(line, 0x00, 10);
956 + copy_from_user(line, buffer, count);
957 + line[count] = 0x00;
958 + pdata = line;
959 + ptemp = temp;
960 + while (flag == 0) {
961 + if (i > 10)
962 + break;
963 + if (((*pdata) >= '0') && ((*pdata) <= '9')) {
964 + *ptemp = *pdata;
965 + ptemp++;
966 + } else if ((*pdata) == ',') {
967 + *ptemp = 0x00;
968 + flag = 1;
969 + }
970 + pdata++;
971 + i++;
972 + };
973 + if (flag == 1)
974 + mod = led_atoi(temp);
975 + else
976 + return count;
977 +
978 + ptemp = temp;
979 + *ptemp = 0x00;
980 + flag = 0;
981 + while (flag == 0) {
982 + if (i > 10)
983 + break;
984 + if (((*pdata) >= '0') && ((*pdata) <= '9')) {
985 + *ptemp = *pdata;
986 + ptemp++;
987 + } else if ((*pdata) == 0x00) {
988 + *ptemp = 0x00;
989 + flag = 1;
990 + }
991 + pdata++;
992 + i++;
993 + };
994 + if (flag == 1)
995 + state = led_atoi(temp);
996 + else
997 + return count;
998 + if ((mod == 0xFFFF) || (state == 0xFFFF))
999 + return count;
1000 + else
1001 + led_operation(mod, state);
1002 + return count;
1003 +}
1004 +
1005 +static int config_led(unsigned long y)
1006 +{
1007 + config_elem_t *pcfg = NULL;
1008 + char *pdata = NULL;
1009 + int i;
1010 + int length = 0, number = 0;
1011 + unsigned int flags;
1012 +
1013 + spin_lock_irqsave(&config_lock, flags);
1014 +
1015 + /* ioctl to configure */
1016 + length = *((int *) y);
1017 + pdata = (char *) y + sizeof(int);
1018 + number = (length - sizeof(int)) / sizeof(config_elem_t);
1019 + pcfg = (config_elem_t *) (pdata);
1020 +
1021 + /* Check if an earlier configuration exists IF yes free it up */
1022 + free_memory();
1023 +
1024 + for (i = 0; i < number; i++) {
1025 + /* If no structure has been allocated for the module do so */
1026 + if (modArr[pcfg->name] == NULL) {
1027 + printk("<1>module = %d\n", pcfg->name);
1028 + if (pcfg->name >= MAX_MOD_ID) {
1029 + printk
1030 + ("<1>Exiting Configuration: Module ID too large %d\n",
1031 + pcfg->name);
1032 + free_memory();
1033 + spin_unlock_irqrestore(&config_lock, flags);
1034 + return -1;
1035 + }
1036 + modArr[pcfg->name] = kmalloc(sizeof(mod_entry_t), GFP_KERNEL);
1037 + if (modArr[pcfg->name] == NULL) {
1038 + printk
1039 + ("<1>Exiting Configuration: Error in allocating memory\n");
1040 + free_memory();
1041 + spin_unlock_irqrestore(&config_lock, flags);
1042 + return -1;
1043 + }
1044 + memset(modArr[pcfg->name], 0x00, sizeof(mod_entry_t));
1045 + }
1046 +
1047 + /* if no structure is allocated previously for this state
1048 + allocate a structure, if it's already there fill it up */
1049 + if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
1050 + printk("<1>STATE = %d\n", pcfg->state);
1051 + if (pcfg->state >= MAX_STATE_ID) {
1052 + printk("<1>Exiting Configuration: State ID too large\n");
1053 + free_memory();
1054 + spin_unlock_irqrestore(&config_lock, flags);
1055 + return -1;
1056 + }
1057 + modArr[pcfg->name]->states[pcfg->state] =
1058 + kmalloc(sizeof(state_entry_t), GFP_KERNEL);
1059 + if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
1060 + free_memory();
1061 + spin_unlock_irqrestore(&config_lock, flags);
1062 + return -1;
1063 + }
1064 + memset(modArr[pcfg->name]->states[pcfg->state], 0x00,
1065 + sizeof(state_entry_t));
1066 + }
1067 + /* Fill up the fields of the state */
1068 + if (pcfg->led >= MAX_LED_ID) {
1069 + printk("<1>led = %d\n", pcfg->led);
1070 + free_memory();
1071 + spin_unlock_irqrestore(&config_lock, flags);
1072 + return -1;
1073 + }
1074 + modArr[pcfg->name]->states[pcfg->state]->led = pcfg->led;
1075 + modArr[pcfg->name]->states[pcfg->state]->mode = pcfg->mode;
1076 + modArr[pcfg->name]->states[pcfg->state]->param = pcfg->param;
1077 + switch (pcfg->mode) {
1078 + case 1:
1079 + modArr[pcfg->name]->states[pcfg->state]->handler =
1080 + board_led_link_down;
1081 + break;
1082 + case 2:
1083 + case 3:
1084 + case 5:
1085 + if (pcfg->mode == 2)
1086 + modArr[pcfg->name]->states[pcfg->state]->handler =
1087 + board_led_activity_on;
1088 + else if (pcfg->mode == 3)
1089 + modArr[pcfg->name]->states[pcfg->state]->handler =
1090 + board_led_activity_off;
1091 + else
1092 + modArr[pcfg->name]->states[pcfg->state]->handler =
1093 + board_led_link_flash;
1094 + break;
1095 + case 4:
1096 + modArr[pcfg->name]->states[pcfg->state]->handler =
1097 + board_led_link_up;
1098 + break;
1099 + default:
1100 + printk("<1>Exiting Configuration: Unknown LED Mode\n");
1101 + free_memory();
1102 + spin_unlock_irqrestore(&config_lock, flags);
1103 + return -1;
1104 + }
1105 + pcfg++;
1106 + }
1107 + spin_unlock_irqrestore(&config_lock, flags);
1108 + return 0;
1109 +}
1110 +
1111 +
1112 +int led_init(void)
1113 +{
1114 +
1115 + /* Clear our memory */
1116 + memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
1117 + memset(led_arr, 0x00, sizeof(led_data_t *) * MAX_LED_ID);
1118 +
1119 + /* Create spin lock for config data structure */
1120 + config_lock = SPIN_LOCK_UNLOCKED;
1121 +
1122 + /* Create directory */
1123 + led_proc_dir = proc_mkdir("led_mod", NULL);
1124 + if (led_proc_dir == NULL)
1125 + goto out;
1126 +
1127 + /* Create adsl file */
1128 + led_file = create_proc_entry("led", 0777, led_proc_dir);
1129 + if (led_file == NULL)
1130 + goto led_file;
1131 + led_file->owner = THIS_MODULE;
1132 + led_file->proc_fops = &led_fops;
1133 +
1134 + memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
1135 + /* Reset the GPIO pins */
1136 + board_gpio_init();
1137 +
1138 + /* Ron add for ADSL LED blink */
1139 + my_mode = 1;
1140 + my_led_init(GPIO_ADSL_ACT, 0, -1);
1141 + my_led_init(GPIO_ADSL_DOWN, 0, -1);
1142 + init_timer(&my_led_timer);
1143 + my_led_timer.function = my_led_blink_timer;
1144 + my_led_timer.data = 0;
1145 + my_led_timer.expires = jiffies + BLINK_SLOW;
1146 + add_timer(&my_led_timer);
1147 + /* Ron add for ADSL LED blink */
1148 + return 0;
1149 +
1150 + led_file:
1151 + remove_proc_entry("led", led_proc_dir);
1152 + out:
1153 + return 0;
1154 +
1155 +}
1156 +
1157 +void led_operation(int mod, int state)
1158 +{
1159 +
1160 + unsigned int flags;
1161 +
1162 + spin_lock_irqsave(&config_lock, flags);
1163 +#if 1
1164 + /* Ron Add for ADSL LED blink */
1165 + //printk("mod==%d state==%d\n",mod,state);
1166 +
1167 + if (mod == 1) {
1168 + switch (state) {
1169 + /* off */
1170 + case 1:
1171 + my_mode = 1;
1172 + my_blink_count = 0;
1173 + my_led_off(GPIO_ADSL_ACT, -1);
1174 + my_led_off(GPIO_ADSL_DOWN, -1);
1175 + break;
1176 + /* sync */
1177 + case 2:
1178 + if (my_mode == 1) {
1179 + my_mode = 2;
1180 + my_led_off(GPIO_ADSL_ACT, -1);
1181 + my_blink_count++;
1182 + }
1183 + break;
1184 + /* on */
1185 + case 3:
1186 + my_mode = 3;
1187 + my_blink_count = 0;
1188 + my_led_off(GPIO_ADSL_DOWN, -1);
1189 + my_led_on(GPIO_ADSL_ACT, -1);
1190 + break;
1191 + /* off */
1192 + case 4:
1193 + my_mode = 4;
1194 + my_led_off(GPIO_ADSL_DOWN, -1);
1195 + my_blink_count++;
1196 + break;
1197 + }
1198 + } /* Ron add for ADSL LED Blink */
1199 +#endif
1200 + if ((mod >= MAX_MOD_ID) || (state >= MAX_STATE_ID)) {
1201 + spin_unlock_irqrestore(&config_lock, flags);
1202 + return;
1203 + }
1204 + if (modArr[mod] == NULL) {
1205 + spin_unlock_irqrestore(&config_lock, flags);
1206 + return;
1207 + }
1208 + if (modArr[mod]->states[state] == NULL) {
1209 + spin_unlock_irqrestore(&config_lock, flags);
1210 + return;
1211 + }
1212 + /* Call the function handler */
1213 + modArr[mod]->states[state]->handler(modArr[mod]->states[state]);
1214 +
1215 + spin_unlock_irqrestore(&config_lock, flags);
1216 +}
1217 +
1218 +void register_led_drv(int device, led_reg_t * pInfo)
1219 +{
1220 + unsigned int flags;
1221 + struct timer_list *pTimer = NULL;
1222 +
1223 + spin_lock_irqsave(&config_lock, flags);
1224 +
1225 + led_arr[device].led = pInfo;
1226 + if (led_arr[device].led->init != 0x00)
1227 + led_arr[device].led->init(led_arr[device].led->param);
1228 + if (led_arr[device].led->offfunc != 0x00)
1229 + led_arr[device].led->offfunc(led_arr[device].led->param);
1230 +
1231 + /* Create a timer for blinking */
1232 + pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
1233 + init_timer(pTimer);
1234 + pTimer->function = led_timer_func;
1235 + pTimer->data = 0;
1236 + led_arr[device].pTimer = pTimer;
1237 + led_arr[device].timer_running = 0;
1238 +
1239 + spin_unlock_irqrestore(&config_lock, flags);
1240 +
1241 + return;
1242 +}
1243 +
1244 +void deregister_led_drv(int device)
1245 +{
1246 + unsigned int flags;
1247 +
1248 + spin_lock_irqsave(&config_lock, flags);
1249 + led_arr[device].led = NULL;
1250 +
1251 + if (led_arr[device].pTimer != NULL) {
1252 + del_timer(led_arr[device].pTimer);
1253 + kfree(led_arr[device].pTimer);
1254 + }
1255 + spin_unlock_irqrestore(&config_lock, flags);
1256 +
1257 + return;
1258 +}
1259 +
1260 +EXPORT_SYMBOL_NOVERS(led_init);
1261 +EXPORT_SYMBOL_NOVERS(led_operation);
1262 +EXPORT_SYMBOL_NOVERS(register_led_drv);
1263 +EXPORT_SYMBOL_NOVERS(deregister_led_drv);
1264 diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile
1265 --- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
1266 +++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 09:31:33.038504888 +0200
1267 @@ -0,0 +1,31 @@
1268 +# $Id$
1269 +# Copyright (C) $Date$ $Author$
1270 +#
1271 +# This program is free software; you can redistribute it and/or modify
1272 +# it under the terms of the GNU General Public License as published by
1273 +# the Free Software Foundation; either version 2 of the License, or
1274 +# (at your option) any later version.
1275 +#
1276 +# This program is distributed in the hope that it will be useful,
1277 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1278 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1279 +# GNU General Public License for more details.
1280 +#
1281 +# You should have received a copy of the GNU General Public License
1282 +# along with this program; if not, write to the Free Software
1283 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1284 +
1285 +.S.s:
1286 + $(CPP) $(AFLAGS) $< -o $*.s
1287 +
1288 +.S.o:
1289 + $(CC) $(AFLAGS) -c $< -o $*.o
1290 +
1291 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
1292 +
1293 +O_TARGET := ar7.o
1294 +
1295 +export-objs:= ledmod.o gpio.o
1296 +obj-y += ar7_paging.o ar7_jump.o ledmod.o gpio.o tnetd73xx_misc.o
1297 +
1298 +include $(TOPDIR)/Rules.make
1299 diff -urN kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c
1300 --- kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
1301 +++ kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c 2005-07-10 09:57:09.935860976 +0200
1302 @@ -0,0 +1,926 @@
1303 +/******************************************************************************
1304 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1305 + ******************************************************************************
1306 + * FILE NAME: tnetd73xx_misc.c
1307 + *
1308 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1309 + * FSER Modules API
1310 + * As per TNETD73xx specifications
1311 + *
1312 + * REVISION HISTORY:
1313 + * 27 Nov 02 - Sharath Kumar PSP TII
1314 + * 14 Feb 03 - Anant Gole PSP TII
1315 + *
1316 + * (C) Copyright 2002, Texas Instruments, Inc
1317 + *******************************************************************************/
1318 +
1319 +
1320 +#include <linux/stddef.h>
1321 +#include <linux/types.h>
1322 +#include <asm/ar7/tnetd73xx.h>
1323 +#include <asm/ar7/tnetd73xx_misc.h>
1324 +
1325 +#define TRUE 1
1326 +#define FALSE 0
1327 +
1328 +/* TNETD73XX Revision */
1329 +__u32 tnetd73xx_get_revision(void)
1330 +{
1331 + /* Read Chip revision register - This register is from GPIO module */
1332 + return ( (__u32) REG32_DATA(TNETD73XX_CVR));
1333 +}
1334 +
1335 +/*****************************************************************************
1336 + * Reset Control Module
1337 + *****************************************************************************/
1338 +
1339 +
1340 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
1341 +{
1342 + __u32 reset_status;
1343 +
1344 + /* read current reset register */
1345 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
1346 +
1347 + if (reset_ctrl == OUT_OF_RESET)
1348 + {
1349 + /* bring module out of reset */
1350 + reset_status |= (1 << reset_module);
1351 + }
1352 + else
1353 + {
1354 + /* put module in reset */
1355 + reset_status &= (~(1 << reset_module));
1356 + }
1357 +
1358 + /* write to the reset register */
1359 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
1360 +}
1361 +
1362 +
1363 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
1364 +{
1365 + __u32 reset_status;
1366 +
1367 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
1368 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
1369 +}
1370 +
1371 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
1372 +{
1373 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
1374 +}
1375 +
1376 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
1377 +
1378 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
1379 +{
1380 + __u32 sys_reset_status;
1381 +
1382 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
1383 +
1384 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
1385 +}
1386 +
1387 +
1388 +/*****************************************************************************
1389 + * Power Control Module
1390 + *****************************************************************************/
1391 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1392 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1393 +
1394 +
1395 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
1396 +{
1397 + __u32 power_status;
1398 +
1399 + /* read current power down control register */
1400 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
1401 +
1402 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1403 + {
1404 + /* power down the module */
1405 + power_status |= (1 << power_module);
1406 + }
1407 + else
1408 + {
1409 + /* power on the module */
1410 + power_status &= (~(1 << power_module));
1411 + }
1412 +
1413 + /* write to the reset register */
1414 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
1415 +}
1416 +
1417 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
1418 +{
1419 + __u32 power_status;
1420 +
1421 + /* read current power down control register */
1422 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
1423 +
1424 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
1425 +}
1426 +
1427 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
1428 +{
1429 + __u32 power_status;
1430 +
1431 + /* read current power down control register */
1432 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
1433 +
1434 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
1435 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
1436 +
1437 + /* write to power down control register */
1438 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
1439 +}
1440 +
1441 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
1442 +{
1443 + __u32 power_status;
1444 +
1445 + /* read current power down control register */
1446 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
1447 +
1448 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
1449 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
1450 +
1451 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
1452 +}
1453 +
1454 +
1455 +/*****************************************************************************
1456 + * Wakeup Control
1457 + *****************************************************************************/
1458 +
1459 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
1460 +
1461 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
1462 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
1463 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
1464 +{
1465 + __u32 wakeup_status;
1466 +
1467 + /* read the wakeup control register */
1468 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
1469 +
1470 + /* enable/disable */
1471 + if (wakeup_ctrl == WAKEUP_ENABLED)
1472 + {
1473 + /* enable wakeup */
1474 + wakeup_status |= wakeup_int;
1475 + }
1476 + else
1477 + {
1478 + /* disable wakeup */
1479 + wakeup_status &= (~wakeup_int);
1480 + }
1481 +
1482 + /* set polarity */
1483 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1484 + {
1485 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
1486 + }
1487 + else
1488 + {
1489 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
1490 + }
1491 +
1492 + /* write the wakeup control register */
1493 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
1494 +}
1495 +
1496 +
1497 +/*****************************************************************************
1498 + * FSER Control
1499 + *****************************************************************************/
1500 +
1501 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
1502 +{
1503 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
1504 +}
1505 +
1506 +/*****************************************************************************
1507 + * Clock Control
1508 + *****************************************************************************/
1509 +
1510 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
1511 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
1512 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
1513 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
1514 +
1515 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
1516 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
1517 +
1518 +#define CLKC_PRE_DIVIDER 0x0000001F
1519 +#define CLKC_POST_DIVIDER 0x001F0000
1520 +
1521 +#define CLKC_PLL_STATUS 0x1
1522 +#define CLKC_PLL_FACTOR 0x0000F000
1523 +
1524 +#define BOOTCR_PLL_BYPASS (1 << 5)
1525 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
1526 +
1527 +#define MIPS_PLL_SELECT 0x00030000
1528 +#define SYSTEM_PLL_SELECT 0x0000C000
1529 +#define USB_PLL_SELECT 0x000C0000
1530 +#define ADSLSS_PLL_SELECT 0x00C00000
1531 +
1532 +#define MIPS_AFECLKI_SELECT 0x00000000
1533 +#define MIPS_REFCLKI_SELECT 0x00010000
1534 +#define MIPS_XTAL3IN_SELECT 0x00020000
1535 +
1536 +#define SYSTEM_AFECLKI_SELECT 0x00000000
1537 +#define SYSTEM_REFCLKI_SELECT 0x00004000
1538 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
1539 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
1540 +
1541 +#define USB_SYSPLL_SELECT 0x00000000
1542 +#define USB_REFCLKI_SELECT 0x00040000
1543 +#define USB_XTAL3IN_SELECT 0x00080000
1544 +#define USB_MIPSPLL_SELECT 0x000C0000
1545 +
1546 +#define ADSLSS_AFECLKI_SELECT 0x00000000
1547 +#define ADSLSS_REFCLKI_SELECT 0x00400000
1548 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
1549 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
1550 +
1551 +#define SYS_MAX CLK_MHZ(150)
1552 +#define SYS_MIN CLK_MHZ(1)
1553 +
1554 +#define MIPS_SYNC_MAX SYS_MAX
1555 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
1556 +#define MIPS_MIN CLK_MHZ(1)
1557 +
1558 +#define USB_MAX CLK_MHZ(100)
1559 +#define USB_MIN CLK_MHZ(1)
1560 +
1561 +#define ADSL_MAX CLK_MHZ(180)
1562 +#define ADSL_MIN CLK_MHZ(1)
1563 +
1564 +#define PLL_MUL_MAXFACTOR 15
1565 +#define MAX_DIV_VALUE 32
1566 +#define MIN_DIV_VALUE 1
1567 +
1568 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
1569 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
1570 +
1571 +#define DIVIDER_LOCK_TIME 10100
1572 +#define PLL_LOCK_TIME 10100 * 75
1573 +
1574 +
1575 +
1576 +/****************************************************************************
1577 + * DATA PURPOSE: PRIVATE Variables
1578 + **************************************************************************/
1579 +static __u32 *clk_src[4];
1580 +static __u32 mips_pll_out;
1581 +static __u32 sys_pll_out;
1582 +static __u32 afeclk_inp;
1583 +static __u32 refclk_inp;
1584 +static __u32 xtal_inp;
1585 +static __u32 present_min;
1586 +static __u32 present_max;
1587 +
1588 +/* Forward References */
1589 +static __u32 find_gcd(__u32 min, __u32 max);
1590 +static __u32 compute_prediv( __u32 divider, __u32 min, __u32 max);
1591 +static void get_val(__u32 base_freq, __u32 output_freq,__u32 *multiplier, __u32 *divider);
1592 +static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
1593 +static void find_approx(__u32 *,__u32 *,__u32);
1594 +
1595 +/****************************************************************************
1596 + * FUNCTION: tnetd73xx_clkc_init
1597 + ****************************************************************************
1598 + * Description: The routine initializes the internal variables depending on
1599 + * on the sources selected for different clocks.
1600 + ***************************************************************************/
1601 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in)
1602 +{
1603 +
1604 + __u32 choice;
1605 +
1606 + afeclk_inp = afeclk;
1607 + refclk_inp = refclk;
1608 + xtal_inp = xtal3in;
1609 +
1610 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
1611 + switch(choice)
1612 + {
1613 + case MIPS_AFECLKI_SELECT:
1614 + clk_src[CLKC_MIPS] = &afeclk_inp;
1615 + break;
1616 +
1617 + case MIPS_REFCLKI_SELECT:
1618 + clk_src[CLKC_MIPS] = &refclk_inp;
1619 + break;
1620 +
1621 + case MIPS_XTAL3IN_SELECT:
1622 + clk_src[CLKC_MIPS] = &xtal_inp;
1623 + break;
1624 +
1625 + default :
1626 + clk_src[CLKC_MIPS] = 0;
1627 +
1628 + }
1629 +
1630 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
1631 + switch(choice)
1632 + {
1633 + case SYSTEM_AFECLKI_SELECT:
1634 + clk_src[CLKC_SYS] = &afeclk_inp;
1635 + break;
1636 +
1637 + case SYSTEM_REFCLKI_SELECT:
1638 + clk_src[CLKC_SYS] = &refclk_inp;
1639 + break;
1640 +
1641 + case SYSTEM_XTAL3IN_SELECT:
1642 + clk_src[CLKC_SYS] = &xtal_inp;
1643 + break;
1644 +
1645 + case SYSTEM_MIPSPLL_SELECT:
1646 + clk_src[CLKC_SYS] = &mips_pll_out;
1647 + break;
1648 +
1649 + default :
1650 + clk_src[CLKC_SYS] = 0;
1651 +
1652 + }
1653 +
1654 +
1655 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
1656 + switch(choice)
1657 + {
1658 + case ADSLSS_AFECLKI_SELECT:
1659 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
1660 + break;
1661 +
1662 + case ADSLSS_REFCLKI_SELECT:
1663 + clk_src[CLKC_ADSLSS] = &refclk_inp;
1664 + break;
1665 +
1666 + case ADSLSS_XTAL3IN_SELECT:
1667 + clk_src[CLKC_ADSLSS] = &xtal_inp;
1668 + break;
1669 +
1670 + case ADSLSS_MIPSPLL_SELECT:
1671 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
1672 + break;
1673 +
1674 + default :
1675 + clk_src[CLKC_ADSLSS] = 0;
1676 +
1677 + }
1678 +
1679 +
1680 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
1681 + switch(choice)
1682 + {
1683 + case USB_SYSPLL_SELECT:
1684 + clk_src[CLKC_USB] = &sys_pll_out ;
1685 + break;
1686 +
1687 + case USB_REFCLKI_SELECT:
1688 + clk_src[CLKC_USB] = &refclk_inp;
1689 + break;
1690 +
1691 + case USB_XTAL3IN_SELECT:
1692 + clk_src[CLKC_USB] = &xtal_inp;
1693 + break;
1694 +
1695 + case USB_MIPSPLL_SELECT:
1696 + clk_src[CLKC_USB] = &mips_pll_out;
1697 + break;
1698 +
1699 + default :
1700 + clk_src[CLKC_USB] = 0;
1701 +
1702 + }
1703 +}
1704 +
1705 +
1706 +
1707 +/****************************************************************************
1708 + * FUNCTION: tnetd73xx_clkc_set_freq
1709 + ****************************************************************************
1710 + * Description: The above routine is called to set the output_frequency of the
1711 + * selected clock(using clk_id) to the required value given
1712 + * by the variable output_freq.
1713 + ***************************************************************************/
1714 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
1715 +(
1716 + TNETD73XX_CLKC_ID_T clk_id,
1717 + __u32 output_freq
1718 +)
1719 +{
1720 + __u32 base_freq;
1721 + __u32 multiplier;
1722 + __u32 divider;
1723 + __u32 min_prediv;
1724 + __u32 max_prediv;
1725 + __u32 prediv;
1726 + __u32 postdiv;
1727 + __u32 temp;
1728 +
1729 + /* check if PLLs are bypassed*/
1730 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
1731 + {
1732 + return TNETD73XX_ERR_ERROR;
1733 + }
1734 +
1735 + /*check if the requested output_frequency is in valid range*/
1736 + switch( clk_id )
1737 + {
1738 + case CLKC_SYS:
1739 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
1740 + {
1741 + return TNETD73XX_ERR_ERROR;
1742 + }
1743 + present_min = SYS_MIN;
1744 + present_max = SYS_MAX;
1745 + break;
1746 +
1747 + case CLKC_MIPS:
1748 + if((output_freq < MIPS_MIN) ||
1749 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
1750 + {
1751 + return TNETD73XX_ERR_ERROR;
1752 + }
1753 + present_min = MIPS_MIN;
1754 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
1755 + break;
1756 +
1757 + case CLKC_USB:
1758 + if( output_freq < USB_MIN || output_freq > USB_MAX)
1759 + {
1760 + return TNETD73XX_ERR_ERROR;
1761 + }
1762 + present_min = USB_MIN;
1763 + present_max = USB_MAX;
1764 + break;
1765 +
1766 + case CLKC_ADSLSS:
1767 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
1768 + {
1769 + return TNETD73XX_ERR_ERROR;
1770 + }
1771 + present_min = ADSL_MIN;
1772 + present_max = ADSL_MAX;
1773 + break;
1774 + }
1775 +
1776 +
1777 + base_freq = get_base_frequency(clk_id);
1778 +
1779 +
1780 + /* check for minimum base frequency value */
1781 + if( base_freq < MIN_PLL_INP_FREQ)
1782 + {
1783 + return TNETD73XX_ERR_ERROR;
1784 + }
1785 +
1786 + get_val(output_freq, base_freq, &multiplier, &divider);
1787 +
1788 + /* check multiplier range */
1789 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
1790 + {
1791 + return TNETD73XX_ERR_ERROR;
1792 + }
1793 +
1794 + /* check divider value */
1795 + if( divider == 0 )
1796 + {
1797 + return TNETD73XX_ERR_ERROR;
1798 + }
1799 +
1800 + /*compute minimum and maximum predivider values */
1801 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
1802 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
1803 +
1804 + /*adjust the value of divider so that it not less than minimum predivider value*/
1805 + if (divider < min_prediv)
1806 + {
1807 + temp = CEIL(min_prediv, divider);
1808 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
1809 + {
1810 + return TNETD73XX_ERR_ERROR ;
1811 + }
1812 + else
1813 + {
1814 + multiplier = temp * multiplier;
1815 + divider = min_prediv;
1816 + }
1817 +
1818 + }
1819 +
1820 + /* compute predivider and postdivider values */
1821 + prediv = compute_prediv (divider, min_prediv, max_prediv);
1822 + postdiv = CEIL(divider,prediv);
1823 +
1824 + /*return fail if postdivider value falls out of range */
1825 + if(postdiv > MAX_DIV_VALUE)
1826 + {
1827 + return TNETD73XX_ERR_ERROR;
1828 + }
1829 +
1830 +
1831 + /*write predivider and postdivider values*/
1832 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
1833 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
1834 +
1835 + /*wait for divider output to stabilise*/
1836 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
1837 +
1838 + /*write to PLL clock register*/
1839 +
1840 + if(clk_id == CLKC_SYS)
1841 + {
1842 + /* but before writing put DRAM to hold mode */
1843 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
1844 + }
1845 + /*Bring PLL into div mode */
1846 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
1847 +
1848 + /*compute the word to be written to PLLCR
1849 + *corresponding to multiplier value
1850 + */
1851 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
1852 +
1853 + /* wait till PLL enters div mode */
1854 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
1855 + /*nothing*/;
1856 +
1857 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
1858 +
1859 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
1860 + /*nothing*/;
1861 +
1862 +
1863 + /*wait for External pll to lock*/
1864 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
1865 +
1866 + if(clk_id == CLKC_SYS)
1867 + {
1868 + /* Bring DRAM out of hold */
1869 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
1870 + }
1871 +
1872 + return TNETD73XX_ERR_OK ;
1873 +}
1874 +
1875 +/****************************************************************************
1876 + * FUNCTION: tnetd73xx_clkc_get_freq
1877 + ****************************************************************************
1878 + * Description: The above routine is called to get the output_frequency of the
1879 + * selected clock( clk_id)
1880 + ***************************************************************************/
1881 +__u32 tnetd73xx_clkc_get_freq
1882 +(
1883 + TNETD73XX_CLKC_ID_T clk_id
1884 +)
1885 +{
1886 +
1887 + __u32 clk_ctrl_register;
1888 + __u32 clk_pll_setting;
1889 + __u32 clk_predivider;
1890 + __u32 clk_postdivider;
1891 + __u16 pll_factor;
1892 + __u32 base_freq;
1893 + __u32 divider;
1894 +
1895 + base_freq = get_base_frequency(clk_id);
1896 +
1897 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
1898 +
1899 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
1900 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
1901 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
1902 +
1903 + divider = clk_predivider * clk_postdivider;
1904 +
1905 +
1906 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
1907 + {
1908 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
1909 + }
1910 +
1911 +
1912 + else
1913 + {
1914 + /* return the current clock speed based upon the PLL setting */
1915 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
1916 +
1917 + /* Get the PLL multiplication factor */
1918 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
1919 +
1920 + /* Check if we're in divide mode or multiply mode */
1921 + if((clk_pll_setting & 0x1) == 0)
1922 + {
1923 + /* We're in divide mode */
1924 + if(pll_factor < 0x10)
1925 + return (CEIL(base_freq >> 1, divider));
1926 + else
1927 + return (CEIL(base_freq >> 2, divider));
1928 + }
1929 +
1930 + else /* We're in PLL mode */
1931 + {
1932 + /* See if PLLNDIV & PLLDIV are set */
1933 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
1934 + {
1935 + if(clk_pll_setting & 0x1000)
1936 + {
1937 + /* clk = base_freq * k/2 */
1938 + return(CEIL((base_freq * pll_factor) >> 1, divider));
1939 + }
1940 + else
1941 + {
1942 + /* clk = base_freq * (k-1) / 4)*/
1943 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
1944 + }
1945 + }
1946 + else
1947 + {
1948 + if(pll_factor < 0x10)
1949 + {
1950 + /* clk = base_freq * k */
1951 + return(CEIL(base_freq * pll_factor, divider));
1952 + }
1953 +
1954 + else
1955 + {
1956 + /* clk = base_freq */
1957 + return(CEIL(base_freq, divider));
1958 + }
1959 + }
1960 + }
1961 + return(0); /* Should never reach here */
1962 +
1963 + }
1964 +
1965 +}
1966 +
1967 +
1968 +/* local helper functions */
1969 +
1970 + /****************************************************************************
1971 + * FUNCTION: get_base_frequency
1972 + ****************************************************************************
1973 + * Description: The above routine is called to get base frequency of the clocks.
1974 + ***************************************************************************/
1975 +
1976 +static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
1977 +{
1978 + /* update the current MIPs PLL output value, if the required
1979 + * source is MIPS PLL
1980 + */
1981 + if ( clk_src[clk_id] == &mips_pll_out)
1982 + {
1983 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
1984 + }
1985 +
1986 +
1987 + /* update the current System PLL output value, if the required
1988 + * source is system PLL
1989 + */
1990 + if ( clk_src[clk_id] == &sys_pll_out)
1991 + {
1992 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
1993 + }
1994 +
1995 + return (*clk_src[clk_id]);
1996 +
1997 +}
1998 +
1999 +
2000 +
2001 +/****************************************************************************
2002 + * FUNCTION: find_gcd
2003 + ****************************************************************************
2004 + * Description: The above routine is called to find gcd of 2 numbers.
2005 + ***************************************************************************/
2006 +static __u32 find_gcd
2007 +(
2008 +__u32 min,
2009 +__u32 max
2010 +)
2011 +{
2012 + if (max % min == 0)
2013 + {
2014 + return min;
2015 + }
2016 + else
2017 + {
2018 + return find_gcd(max % min, min);
2019 + }
2020 +}
2021 +
2022 +/****************************************************************************
2023 + * FUNCTION: compute_prediv
2024 + ****************************************************************************
2025 + * Description: The above routine is called to compute predivider value
2026 + ***************************************************************************/
2027 +static __u32 compute_prediv(__u32 divider, __u32 min, __u32 max)
2028 +{
2029 +__u16 prediv;
2030 +
2031 +/* return the divider itself it it falls within the range of predivider*/
2032 +if (min <= divider && divider <= max)
2033 +{
2034 + return divider;
2035 +}
2036 +
2037 +/* find a value for prediv such that it is a factor of divider */
2038 +for (prediv = max; prediv >= min ; prediv--)
2039 +{
2040 + if ( (divider % prediv) == 0 )
2041 + {
2042 + return prediv;
2043 + }
2044 +}
2045 +
2046 +/* No such factor exists, return min as prediv */
2047 +return min;
2048 +}
2049 +
2050 +/****************************************************************************
2051 + * FUNCTION: get_val
2052 + ****************************************************************************
2053 + * Description: This routine is called to get values of divider and multiplier.
2054 + ***************************************************************************/
2055 +
2056 +static void get_val(__u32 output_freq, __u32 base_freq,__u32 *multiplier, __u32 *divider)
2057 +{
2058 + __u32 temp_mul;
2059 + __u32 temp_div;
2060 + __u32 gcd;
2061 + __u32 min_freq;
2062 + __u32 max_freq;
2063 +
2064 + /* find gcd of base_freq, output_freq */
2065 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2066 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2067 + gcd = find_gcd(min_freq , max_freq);
2068 +
2069 + if(gcd == 0)
2070 + return; /* ERROR */
2071 +
2072 + /* compute values of multiplier and divider */
2073 + temp_mul = output_freq / gcd;
2074 + temp_div = base_freq / gcd;
2075 +
2076 +
2077 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2078 + if( temp_mul > PLL_MUL_MAXFACTOR )
2079 + {
2080 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2081 + return;
2082 +
2083 + find_approx(&temp_mul,&temp_div,base_freq);
2084 + }
2085 +
2086 + *multiplier = temp_mul;
2087 + *divider = temp_div;
2088 +}
2089 +
2090 +/****************************************************************************
2091 + * FUNCTION: find_approx
2092 + ****************************************************************************
2093 + * Description: This function gets the approx value of num/denom.
2094 + ***************************************************************************/
2095 +
2096 +static void find_approx(__u32 *num,__u32 *denom,__u32 base_freq)
2097 +{
2098 + __u32 num1;
2099 + __u32 denom1;
2100 + __u32 num2;
2101 + __u32 denom2;
2102 + int closest;
2103 + int prev_closest;
2104 + __u32 temp_num;
2105 + __u32 temp_denom;
2106 + __u32 normalize;
2107 + __u32 gcd;
2108 + __u32 output_freq;
2109 +
2110 + num1 = *num;
2111 + denom1 = *denom;
2112 +
2113 + prev_closest = 0x7fffffff; /* maximum possible value */
2114 + num2 = num1;
2115 + denom2 = denom1;
2116 +
2117 + /* start with max */
2118 + for(temp_num = 15; temp_num >=1; temp_num--)
2119 + {
2120 +
2121 + temp_denom = CEIL(temp_num * denom1, num1);
2122 + output_freq = (temp_num * base_freq) / temp_denom;
2123 +
2124 + if(temp_denom < 1)
2125 + {
2126 + break;
2127 + }
2128 + else
2129 + {
2130 + normalize = CEIL(num1,temp_num);
2131 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2132 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2133 + {
2134 + prev_closest = closest;
2135 + num2 = temp_num;
2136 + denom2 = temp_denom;
2137 + }
2138 +
2139 + }
2140 +
2141 + }
2142 +
2143 + gcd = find_gcd(num2,denom2);
2144 + num2 = num2 / gcd;
2145 + denom2 = denom2 /gcd;
2146 +
2147 + *num = num2;
2148 + *denom = denom2;
2149 +}
2150 +
2151 +
2152 +/*****************************************************************************
2153 + * GPIO Control
2154 + *****************************************************************************/
2155 +
2156 +/****************************************************************************
2157 + * FUNCTION: tnetd73xx_gpio_init
2158 + ***************************************************************************/
2159 +void tnetd73xx_gpio_init()
2160 +{
2161 + /* Bring module out of reset */
2162 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2163 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2164 +}
2165 +
2166 +/****************************************************************************
2167 + * FUNCTION: tnetd73xx_gpio_ctrl
2168 + ***************************************************************************/
2169 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2170 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2171 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2172 +{
2173 + __u32 pin_status;
2174 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2175 + if (pin_mode == GPIO_PIN)
2176 + {
2177 + pin_status |= (1 << gpio_pin);
2178 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2179 +
2180 + /* Set pin direction */
2181 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2182 + if (pin_direction == GPIO_INPUT_PIN)
2183 + {
2184 + pin_status |= (1 << gpio_pin);
2185 + }
2186 + else /* GPIO_OUTPUT_PIN */
2187 + {
2188 + pin_status &= (~(1 << gpio_pin));
2189 + }
2190 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2191 + }
2192 + else /* FUNCTIONAL PIN */
2193 + {
2194 + pin_status &= (~(1 << gpio_pin));
2195 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2196 + }
2197 +
2198 +}
2199 +
2200 +/****************************************************************************
2201 + * FUNCTION: tnetd73xx_gpio_out
2202 + ***************************************************************************/
2203 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2204 +{
2205 + __u32 pin_value;
2206 +
2207 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2208 + if (value == TRUE)
2209 + {
2210 + pin_value |= (1 << gpio_pin);
2211 + }
2212 + else
2213 + {
2214 + pin_value &= (~(1 << gpio_pin));
2215 + }
2216 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2217 +}
2218 +
2219 +/****************************************************************************
2220 + * FUNCTION: tnetd73xx_gpio_in
2221 + ***************************************************************************/
2222 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2223 +{
2224 + __u32 pin_value;
2225 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2226 + return ( (pin_value & (1 << gpio_pin)) ? TRUE : FALSE );
2227 +}
2228 +
2229 diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-current/arch/mips/ar7/cmdline.c
2230 --- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
2231 +++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266864 +0200
2232 @@ -0,0 +1,64 @@
2233 +/*
2234 + * Carsten Langgaard, carstenl@mips.com
2235 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2236 + *
2237 + * This program is free software; you can distribute it and/or modify it
2238 + * under the terms of the GNU General Public License (Version 2) as
2239 + * published by the Free Software Foundation.
2240 + *
2241 + * This program is distributed in the hope it will be useful, but WITHOUT
2242 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2243 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2244 + * for more details.
2245 + *
2246 + * You should have received a copy of the GNU General Public License along
2247 + * with this program; if not, write to the Free Software Foundation, Inc.,
2248 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2249 + *
2250 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
2251 + */
2252 +#include <linux/init.h>
2253 +#include <linux/string.h>
2254 +
2255 +#include <asm/bootinfo.h>
2256 +
2257 +extern int prom_argc;
2258 +extern int *_prom_argv;
2259 +
2260 +/*
2261 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
2262 + * This macro take care of sign extension.
2263 + */
2264 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
2265 +
2266 +char arcs_cmdline[CL_SIZE];
2267 +
2268 +char * __init prom_getcmdline(void)
2269 +{
2270 + return &(arcs_cmdline[0]);
2271 +}
2272 +
2273 +
2274 +void __init prom_init_cmdline(void)
2275 +{
2276 + char *cp;
2277 + int actr;
2278 +
2279 + actr = 1; /* Always ignore argv[0] */
2280 +
2281 + cp = &(arcs_cmdline[0]);
2282 +#ifdef CONFIG_CMDLINE_BOOL
2283 + strcpy(cp, CONFIG_CMDLINE);
2284 + cp += strlen(CONFIG_CMDLINE);
2285 + *cp++ = ' ';
2286 +#endif
2287 + while(actr < prom_argc) {
2288 + strcpy(cp, prom_argv(actr));
2289 + cp += strlen(prom_argv(actr));
2290 + *cp++ = ' ';
2291 + actr++;
2292 + }
2293 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
2294 + --cp;
2295 + *cp = '\0';
2296 +}
2297 diff -urN kernel-base/arch/mips/ar7/init.c kernel-current/arch/mips/ar7/init.c
2298 --- kernel-base/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
2299 +++ kernel-current/arch/mips/ar7/init.c 2005-07-10 06:40:39.584266864 +0200
2300 @@ -0,0 +1,146 @@
2301 +/*
2302 + * Carsten Langgaard, carstenl@mips.com
2303 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2304 + *
2305 + * This program is free software; you can distribute it and/or modify it
2306 + * under the terms of the GNU General Public License (Version 2) as
2307 + * published by the Free Software Foundation.
2308 + *
2309 + * This program is distributed in the hope it will be useful, but WITHOUT
2310 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2311 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2312 + * for more details.
2313 + *
2314 + * You should have received a copy of the GNU General Public License along
2315 + * with this program; if not, write to the Free Software Foundation, Inc.,
2316 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2317 + *
2318 + * PROM library initialisation code.
2319 + */
2320 +#include <linux/config.h>
2321 +#include <linux/init.h>
2322 +#include <linux/string.h>
2323 +#include <linux/kernel.h>
2324 +#include <linux/module.h>
2325 +
2326 +#include <asm/io.h>
2327 +#include <asm/mips-boards/prom.h>
2328 +#include <asm/mips-boards/generic.h>
2329 +
2330 +/* Environment variable */
2331 +typedef struct {
2332 + char *name;
2333 + char *val;
2334 +} t_env_var;
2335 +
2336 +int prom_argc;
2337 +int *_prom_argv, *_prom_envp;
2338 +
2339 +/* max # of Adam2 environment variables */
2340 +#define MAX_ENV_ENTRY 80
2341 +
2342 +static t_env_var local_envp[MAX_ENV_ENTRY];
2343 +int init_debug = 0;
2344 +
2345 +char *prom_getenv(char *envname)
2346 +{
2347 + /*
2348 + * Return a pointer to the given environment variable.
2349 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
2350 + * in the PROM structures are only 32-bit, so we need some
2351 + * workarounds, if we are running in 64-bit mode.
2352 + */
2353 + int i, index=0;
2354 + t_env_var *env = (t_env_var *) local_envp;
2355 +
2356 + i = strlen(envname);
2357 + while (env->name) {
2358 + if(strncmp(envname, env->name, i) == 0) {
2359 + return(env->val);
2360 + }
2361 + env++;
2362 + }
2363 +
2364 + return NULL;
2365 +}
2366 +
2367 +static inline unsigned char str2hexnum(unsigned char c)
2368 +{
2369 + if (c >= '0' && c <= '9')
2370 + return c - '0';
2371 + if (c >= 'a' && c <= 'f')
2372 + return c - 'a' + 10;
2373 + return 0; /* foo */
2374 +}
2375 +
2376 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
2377 +{
2378 + int i;
2379 +
2380 + for (i = 0; i < 6; i++) {
2381 + unsigned char num;
2382 +
2383 + if((*str == '.') || (*str == ':'))
2384 + str++;
2385 + num = str2hexnum(*str++) << 4;
2386 + num |= (str2hexnum(*str++));
2387 + ea[i] = num;
2388 + }
2389 +}
2390 +
2391 +int get_ethernet_addr(char *ethernet_addr)
2392 +{
2393 + char *ethaddr_str;
2394 +
2395 + ethaddr_str = prom_getenv("ethaddr");
2396 + if (!ethaddr_str) {
2397 + printk("ethaddr not set in boot prom\n");
2398 + return -1;
2399 + }
2400 + str2eaddr(ethernet_addr, ethaddr_str);
2401 +
2402 + if (init_debug > 1) {
2403 + int i;
2404 + printk("get_ethernet_addr: ");
2405 + for (i=0; i<5; i++)
2406 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
2407 + printk("%02x\n", *(ethernet_addr+i));
2408 + }
2409 +
2410 + return 0;
2411 +}
2412 +
2413 +int __init prom_init(int argc, char **argv, char **envp)
2414 +{
2415 + int i;
2416 + t_env_var *env = (t_env_var *) envp;
2417 +
2418 + prom_argc = argc;
2419 + _prom_argv = (int *)argv;
2420 + _prom_envp = (int *)envp;
2421 +
2422 + /* Copy what we need locally so we are not dependent on
2423 + * bootloader RAM. In Adam2, the environment parameters
2424 + * are in flash but the table that references them is in
2425 + * RAM
2426 + */
2427 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
2428 + if (env->name) {
2429 + local_envp[i].name = env->name;
2430 + local_envp[i].val = env->val;
2431 + } else {
2432 + local_envp[i].name = NULL;
2433 + local_envp[i].val = NULL;
2434 + }
2435 + }
2436 +
2437 + set_io_port_base(0);
2438 +
2439 + prom_printf("\nLINUX started...\n");
2440 + prom_init_cmdline();
2441 + prom_meminit();
2442 +
2443 + return 0;
2444 +}
2445 +
2446 +EXPORT_SYMBOL(prom_getenv);
2447 diff -urN kernel-base/arch/mips/ar7/irq.c kernel-current/arch/mips/ar7/irq.c
2448 --- kernel-base/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
2449 +++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 10:02:30.212171576 +0200
2450 @@ -0,0 +1,705 @@
2451 +/*
2452 + * Nitin Dhingra, iamnd@ti.com
2453 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
2454 + *
2455 + * ########################################################################
2456 + *
2457 + * This program is free software; you can distribute it and/or modify it
2458 + * under the terms of the GNU General Public License (Version 2) as
2459 + * published by the Free Software Foundation.
2460 + *
2461 + * This program is distributed in the hope it will be useful, but WITHOUT
2462 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2463 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2464 + * for more details.
2465 + *
2466 + * You should have received a copy of the GNU General Public License along
2467 + * with this program; if not, write to the Free Software Foundation, Inc.,
2468 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2469 + *
2470 + * ########################################################################
2471 + *
2472 + * Routines for generic manipulation of the interrupts found on the Texas
2473 + * Instruments avalanche board
2474 + *
2475 + */
2476 +
2477 +#include <linux/config.h>
2478 +#include <linux/init.h>
2479 +#include <linux/sched.h>
2480 +#include <linux/slab.h>
2481 +#include <linux/interrupt.h>
2482 +#include <linux/kernel_stat.h>
2483 +#include <linux/proc_fs.h>
2484 +#include <asm/irq.h>
2485 +#include <asm/mips-boards/prom.h>
2486 +#include <asm/ar7/ar7.h>
2487 +#include <asm/ar7/avalanche_intc.h>
2488 +#include <asm/gdb-stub.h>
2489 +
2490 +
2491 +#define shutdown_avalanche_irq disable_avalanche_irq
2492 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
2493 +
2494 +static unsigned int startup_avalanche_irq(unsigned int irq);
2495 +static void end_avalanche_irq(unsigned int irq);
2496 +void enable_avalanche_irq(unsigned int irq_nr);
2497 +void disable_avalanche_irq(unsigned int irq_nr);
2498 +
2499 +static struct hw_interrupt_type avalanche_irq_type = {
2500 + "TI AVALANCHE",
2501 + startup_avalanche_irq,
2502 + shutdown_avalanche_irq,
2503 + enable_avalanche_irq,
2504 + disable_avalanche_irq,
2505 + mask_and_ack_avalanche_irq,
2506 + end_avalanche_irq,
2507 + NULL
2508 +};
2509 +
2510 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
2511 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
2512 +
2513 +
2514 +unsigned long spurious_count = 0;
2515 +
2516 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
2517 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
2518 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
2519 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
2520 +
2521 +extern asmlinkage void mipsIRQ(void);
2522 +
2523 +
2524 +/*
2525 + * The avalanche/MIPS interrupt line numbers are used to represent the
2526 + * interrupts within the irqaction arrays. The index notation is
2527 + * is as follows:
2528 + *
2529 + * 0-7 MIPS CPU Exceptions (HW/SW)
2530 + * 8-47 Primary Interrupts (Avalanche)
2531 + * 48-79 Secondary Interrupts (Avalanche)
2532 + *
2533 + */
2534 +
2535 +
2536 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
2537 +{
2538 + NULL, NULL, NULL, NULL,
2539 + NULL, NULL, NULL, NULL,
2540 + NULL, NULL, NULL, NULL,
2541 + NULL, NULL, NULL, NULL,
2542 + NULL, NULL, NULL, NULL,
2543 + NULL, NULL, NULL, NULL,
2544 + NULL, NULL, NULL, NULL,
2545 + NULL, NULL, NULL, NULL,
2546 + NULL, NULL, NULL, NULL,
2547 + NULL, NULL, NULL, NULL
2548 +};
2549 +
2550 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
2551 +{
2552 + NULL, NULL, NULL, NULL,
2553 + NULL, NULL, NULL, NULL,
2554 + NULL, NULL, NULL, NULL,
2555 + NULL, NULL, NULL, NULL,
2556 + NULL, NULL, NULL, NULL,
2557 + NULL, NULL, NULL, NULL,
2558 + NULL, NULL, NULL, NULL,
2559 + NULL, NULL, NULL, NULL
2560 +};
2561 +
2562 +/*
2563 + This remaps interrupts to exist on other channels than the default
2564 + channels. essentially we can use the line # as the index for this
2565 + array
2566 + */
2567 +
2568 +
2569 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
2570 +unsigned long uni_secondary_interrupt = 0;
2571 +
2572 +static struct irqaction r4ktimer_action = {
2573 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
2574 +};
2575 +
2576 +static struct irqaction *irq_action[8] = {
2577 + NULL, /* SW int 0 */
2578 + NULL, /* SW int 1 */
2579 + NULL, /* HW int 0 */
2580 + NULL,
2581 + NULL,
2582 + NULL, /* HW int 3 */
2583 + NULL, /* HW int 4 */
2584 + &r4ktimer_action /* HW int 5 */
2585 +};
2586 +
2587 +static void end_avalanche_irq(unsigned int irq)
2588 +{
2589 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
2590 + enable_avalanche_irq(irq);
2591 +}
2592 +
2593 +void disable_avalanche_irq(unsigned int irq_nr)
2594 +{
2595 + unsigned long flags;
2596 + unsigned long chan_nr=0;
2597 + unsigned long int_bit=0;
2598 +
2599 + if(irq_nr >= AVALANCHE_INT_END)
2600 + {
2601 + printk("whee, invalid irq_nr %d\n", irq_nr);
2602 + panic("IRQ, you lose...");
2603 + }
2604 +
2605 + save_and_cli(flags);
2606 +
2607 +
2608 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
2609 + {
2610 + /* disable mips exception */
2611 +
2612 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
2613 + change_c0_status(ST0_IM,int_bit);
2614 + restore_flags(flags);
2615 + return;
2616 + }
2617 +
2618 + /* irq_nr represents the line number for the interrupt. We must
2619 + * disable the channel number associated with that line number.
2620 + */
2621 +
2622 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
2623 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
2624 + else
2625 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
2626 +
2627 + /* disable the interrupt channel bit */
2628 +
2629 + /* primary interrupt #'s 0-31 */
2630 +
2631 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
2632 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
2633 +
2634 + /* primary interrupt #'s 32-39 */
2635 +
2636 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
2637 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
2638 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
2639 +
2640 + else /* secondary interrupt #'s 0-31 */
2641 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
2642 +
2643 + restore_flags(flags);
2644 +}
2645 +
2646 +void enable_avalanche_irq(unsigned int irq_nr)
2647 +{
2648 + unsigned long flags;
2649 + unsigned long chan_nr=0;
2650 + unsigned long int_bit=0;
2651 +
2652 + if(irq_nr > AVALANCHE_INT_END) {
2653 + printk("whee, invalid irq_nr %d\n", irq_nr);
2654 + panic("IRQ, you lose...");
2655 + }
2656 +
2657 + save_and_cli(flags);
2658 +
2659 +
2660 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
2661 + {
2662 + /* Enable MIPS exceptions */
2663 + int_bit = read_c0_status();
2664 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
2665 + restore_flags(flags);
2666 + return;
2667 + }
2668 +
2669 + /* irq_nr represents the line number for the interrupt. We must
2670 + * disable the channel number associated with that line number.
2671 + */
2672 +
2673 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
2674 + chan_nr = AVINTNUM(irq_nr);
2675 + else
2676 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
2677 +
2678 + /* enable the interrupt channel bit */
2679 +
2680 + /* primary interrupt #'s 0-31 */
2681 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
2682 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
2683 +
2684 + /* primary interrupt #'s 32 throuth 39 */
2685 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
2686 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
2687 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
2688 +
2689 + else /* secondary interrupt #'s 0-31 */
2690 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
2691 +
2692 + restore_flags(flags);
2693 +}
2694 +
2695 +static unsigned int startup_avalanche_irq(unsigned int irq)
2696 +{
2697 + enable_avalanche_irq(irq);
2698 + return 0; /* never anything pending */
2699 +}
2700 +
2701 +
2702 +int get_irq_list(char *buf)
2703 +{
2704 + int i, len = 0;
2705 + int num = 0;
2706 + struct irqaction *action;
2707 +
2708 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
2709 + {
2710 + action = irq_action[i];
2711 + if (!action)
2712 + continue;
2713 + len += sprintf(buf+len, "%2d: %8d %c %s",
2714 + num, kstat.irqs[0][num],
2715 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
2716 + action->name);
2717 + for (action=action->next; action; action = action->next) {
2718 + len += sprintf(buf+len, ",%s %s",
2719 + (action->flags & SA_INTERRUPT) ? " +" : "",
2720 + action->name);
2721 + }
2722 + len += sprintf(buf+len, " [MIPS interrupt]\n");
2723 + }
2724 +
2725 +
2726 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
2727 + {
2728 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
2729 + action = hw0_irq_action_primary[i];
2730 + else
2731 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
2732 + if (!action)
2733 + continue;
2734 + len += sprintf(buf+len, "%2d: %8d %c %s",
2735 + num, kstat.irqs[0][ LNXINTNUM(i) ],
2736 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
2737 + action->name);
2738 +
2739 + for (action=action->next; action; action = action->next)
2740 + {
2741 + len += sprintf(buf+len, ",%s %s",
2742 + (action->flags & SA_INTERRUPT) ? " +" : "",
2743 + action->name);
2744 + }
2745 +
2746 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
2747 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
2748 + else
2749 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
2750 +
2751 + }
2752 +
2753 + return len;
2754 +}
2755 +
2756 +int request_irq(unsigned int irq,
2757 + void (*handler)(int, void *, struct pt_regs *),
2758 + unsigned long irqflags,
2759 + const char * devname,
2760 + void *dev_id)
2761 +{
2762 + struct irqaction *action;
2763 +
2764 + if (irq > AVALANCHE_INT_END)
2765 + return -EINVAL;
2766 + if (!handler)
2767 + return -EINVAL;
2768 +
2769 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
2770 + if(!action)
2771 + return -ENOMEM;
2772 +
2773 + action->handler = handler;
2774 + action->flags = irqflags;
2775 + action->mask = 0;
2776 + action->name = devname;
2777 + irq_desc_ti[irq].action = action;
2778 + action->dev_id = dev_id;
2779 +
2780 + action->next = 0;
2781 +
2782 + if(irq < MIPS_EXCEPTION_OFFSET)
2783 + {
2784 + irq_action[irq] = action;
2785 + enable_avalanche_irq(irq);
2786 + return 0;
2787 + }
2788 +
2789 + if(irq < AVALANCHE_INT_END_PRIMARY)
2790 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
2791 + else
2792 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
2793 +
2794 + enable_avalanche_irq(irq);
2795 +
2796 + return 0;
2797 +}
2798 +
2799 +void free_irq(unsigned int irq, void *dev_id)
2800 +{
2801 + struct irqaction *action;
2802 +
2803 + if (irq > AVALANCHE_INT_END) {
2804 + printk("Trying to free IRQ%d\n",irq);
2805 + return;
2806 + }
2807 +
2808 + if(irq < MIPS_EXCEPTION_OFFSET)
2809 + {
2810 + action = irq_action[irq];
2811 + irq_action[irq] = NULL;
2812 + irq_desc_ti[irq].action = NULL;
2813 + disable_avalanche_irq(irq);
2814 + kfree(action);
2815 + return;
2816 + }
2817 +
2818 + if(irq < AVALANCHE_INT_END_PRIMARY) {
2819 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
2820 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
2821 + irq_desc_ti[irq].action = NULL;
2822 + }
2823 + else {
2824 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
2825 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
2826 + irq_desc_ti[irq].action = NULL;
2827 + }
2828 +
2829 + disable_avalanche_irq(irq);
2830 + kfree(action);
2831 +}
2832 +
2833 +#ifdef CONFIG_KGDB
2834 +extern void breakpoint(void);
2835 +extern int remote_debug;
2836 +#endif
2837 +
2838 +//void init_IRQ(void) __init;
2839 +void __init init_IRQ(void)
2840 +{
2841 + int i;
2842 +
2843 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
2844 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
2845 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
2846 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
2847 +
2848 + /* Disable interrupts and clear pending
2849 + */
2850 +
2851 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
2852 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
2853 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
2854 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
2855 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
2856 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
2857 +
2858 +
2859 + /* Channel to line mapping, Line to Channel mapping */
2860 +
2861 + for(i = 0; i < 40; i++)
2862 + avalanche_int_set(i,i);
2863 +
2864 + /* Now safe to set the exception vector. */
2865 + set_except_vector(0, mipsIRQ);
2866 +
2867 + /* Setup the IRQ description array. These will be mapped
2868 + * as flat interrupts numbers. The mapping is as follows
2869 + *
2870 + * 0-7 MIPS CPU Exceptions (HW/SW)
2871 + * 8-46 Primary Interrupts (Avalanche)
2872 + * 47-78 Secondary Interrupts (Avalanche)
2873 + */
2874 +
2875 + for (i = 0; i <= AVALANCHE_INT_END; i++)
2876 + {
2877 + irq_desc_ti[i].status = IRQ_DISABLED;
2878 + irq_desc_ti[i].action = 0;
2879 + irq_desc_ti[i].depth = 1;
2880 + irq_desc_ti[i].handler = &avalanche_irq_type;
2881 + }
2882 +
2883 +#ifdef CONFIG_KGDB
2884 + if (remote_debug)
2885 + {
2886 + set_debug_traps();
2887 + breakpoint();
2888 + }
2889 +#endif
2890 +}
2891 +
2892 +
2893 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
2894 +{
2895 + struct irqaction *action;
2896 + int irq, cpu = smp_processor_id();
2897 + unsigned long int_line_number,status;
2898 + int i,secondary = 0;
2899 + int chan_nr=0;
2900 +
2901 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
2902 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
2903 +
2904 +
2905 + if(chan_nr < 32)
2906 + {
2907 + if( chan_nr != uni_secondary_interrupt)
2908 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
2909 +
2910 + }
2911 +
2912 + if((chan_nr < 40) && (chan_nr > 31))
2913 + {
2914 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
2915 + }
2916 +
2917 +
2918 + /* If the Priority Interrupt Index Register returns 40 then no
2919 + * interrupts are pending
2920 + */
2921 +
2922 + if(chan_nr == 40)
2923 + return;
2924 +
2925 + if(chan_nr == uni_secondary_interrupt)
2926 + {
2927 + status = avalanche_hw0_ecregs->exsr;
2928 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
2929 + {
2930 + if (status & 1<<i)
2931 + {
2932 + /* clear secondary interrupt */
2933 + avalanche_hw0_ecregs->excr = 1 << i;
2934 + break;
2935 + }
2936 + }
2937 + irq = i;
2938 + secondary = 1;
2939 +
2940 + /* clear the universal secondary interrupt */
2941 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
2942 +
2943 + }
2944 + else
2945 + irq = chan_nr;
2946 +
2947 + /* Suraj Add code to clear secondary interrupt */
2948 +
2949 + if(secondary)
2950 + action = hw0_irq_action_secondary[irq];
2951 + else
2952 + action = hw0_irq_action_primary[irq];
2953 +
2954 + /* if action == NULL, then we don't have a handler for the irq */
2955 +
2956 + if ( action == NULL ) {
2957 + printk("No handler for hw0 irq: %i\n", irq);
2958 + return;
2959 + }
2960 +
2961 + irq_enter(cpu,irq);
2962 + if(secondary)
2963 + {
2964 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
2965 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
2966 + }
2967 + else
2968 + {
2969 + kstat.irqs[0][irq + 8]++;
2970 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
2971 + }
2972 +
2973 + irq_exit(cpu,irq);
2974 +
2975 + if(softirq_pending(cpu))
2976 + do_softirq();
2977 +
2978 + return;
2979 +}
2980 +
2981 +void avalanche_int_set(int channel, int line)
2982 +{
2983 + switch(channel)
2984 + {
2985 + case(0):
2986 + avalanche_hw0_chregs->cintnr0 = line;
2987 + break;
2988 + case(1):
2989 + avalanche_hw0_chregs->cintnr1 = line;
2990 + break;
2991 + case(2):
2992 + avalanche_hw0_chregs->cintnr2 = line;
2993 + break;
2994 + case(3):
2995 + avalanche_hw0_chregs->cintnr3 = line;
2996 + break;
2997 + case(4):
2998 + avalanche_hw0_chregs->cintnr4 = line;
2999 + break;
3000 + case(5):
3001 + avalanche_hw0_chregs->cintnr5 = line;
3002 + break;
3003 + case(6):
3004 + avalanche_hw0_chregs->cintnr6 = line;
3005 + break;
3006 + case(7):
3007 + avalanche_hw0_chregs->cintnr7 = line;
3008 + break;
3009 + case(8):
3010 + avalanche_hw0_chregs->cintnr8 = line;
3011 + break;
3012 + case(9):
3013 + avalanche_hw0_chregs->cintnr9 = line;
3014 + break;
3015 + case(10):
3016 + avalanche_hw0_chregs->cintnr10 = line;
3017 + break;
3018 + case(11):
3019 + avalanche_hw0_chregs->cintnr11 = line;
3020 + break;
3021 + case(12):
3022 + avalanche_hw0_chregs->cintnr12 = line;
3023 + break;
3024 + case(13):
3025 + avalanche_hw0_chregs->cintnr13 = line;
3026 + break;
3027 + case(14):
3028 + avalanche_hw0_chregs->cintnr14 = line;
3029 + break;
3030 + case(15):
3031 + avalanche_hw0_chregs->cintnr15 = line;
3032 + break;
3033 + case(16):
3034 + avalanche_hw0_chregs->cintnr16 = line;
3035 + break;
3036 + case(17):
3037 + avalanche_hw0_chregs->cintnr17 = line;
3038 + break;
3039 + case(18):
3040 + avalanche_hw0_chregs->cintnr18 = line;
3041 + break;
3042 + case(19):
3043 + avalanche_hw0_chregs->cintnr19 = line;
3044 + break;
3045 + case(20):
3046 + avalanche_hw0_chregs->cintnr20 = line;
3047 + break;
3048 + case(21):
3049 + avalanche_hw0_chregs->cintnr21 = line;
3050 + break;
3051 + case(22):
3052 + avalanche_hw0_chregs->cintnr22 = line;
3053 + break;
3054 + case(23):
3055 + avalanche_hw0_chregs->cintnr23 = line;
3056 + break;
3057 + case(24):
3058 + avalanche_hw0_chregs->cintnr24 = line;
3059 + break;
3060 + case(25):
3061 + avalanche_hw0_chregs->cintnr25 = line;
3062 + break;
3063 + case(26):
3064 + avalanche_hw0_chregs->cintnr26 = line;
3065 + break;
3066 + case(27):
3067 + avalanche_hw0_chregs->cintnr27 = line;
3068 + break;
3069 + case(28):
3070 + avalanche_hw0_chregs->cintnr28 = line;
3071 + break;
3072 + case(29):
3073 + avalanche_hw0_chregs->cintnr29 = line;
3074 + break;
3075 + case(30):
3076 + avalanche_hw0_chregs->cintnr30 = line;
3077 + break;
3078 + case(31):
3079 + avalanche_hw0_chregs->cintnr31 = line;
3080 + break;
3081 + case(32):
3082 + avalanche_hw0_chregs->cintnr32 = line;
3083 + break;
3084 + case(33):
3085 + avalanche_hw0_chregs->cintnr33 = line;
3086 + break;
3087 + case(34):
3088 + avalanche_hw0_chregs->cintnr34 = line;
3089 + break;
3090 + case(35):
3091 + avalanche_hw0_chregs->cintnr35 = line;
3092 + break;
3093 + case(36):
3094 + avalanche_hw0_chregs->cintnr36 = line;
3095 + break;
3096 + case(37):
3097 + avalanche_hw0_chregs->cintnr37 = line;
3098 + break;
3099 + case(38):
3100 + avalanche_hw0_chregs->cintnr38 = line;
3101 + break;
3102 + case(39):
3103 + avalanche_hw0_chregs->cintnr39 = line;
3104 + break;
3105 + default:
3106 + printk("Error: Unknown Avalanche interrupt channel\n");
3107 + }
3108 +
3109 + line_to_channel[line] = channel; /* Suraj check */
3110 +
3111 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
3112 + uni_secondary_interrupt = line;
3113 +
3114 +}
3115 +
3116 +
3117 +#define AVALANCHE_MAX_PACING_BLK 3
3118 +#define AVALANCHE_PACING_LOW_VAL 2
3119 +#define AVALANCHE_PACING_HIGH_VAL 63
3120 +
3121 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
3122 + unsigned int pace_value)
3123 +{
3124 + unsigned int blk_offset;
3125 + unsigned long flags;
3126 +
3127 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
3128 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
3129 + return (0);
3130 +
3131 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
3132 + return(-1);
3133 +
3134 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
3135 + pace_value < AVALANCHE_PACING_LOW_VAL)
3136 + return(-1);
3137 +
3138 + blk_offset = blk_num*8;
3139 +
3140 + save_and_cli(flags);
3141 +
3142 + /* disable the interrupt pacing, if enabled previously */
3143 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
3144 +
3145 + /* clear the pacing map */
3146 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
3147 +
3148 + /* setup the new values */
3149 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
3150 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
3151 +
3152 + restore_flags(flags);
3153 +
3154 + return(0);
3155 +}
3156 diff -urN kernel-base/arch/mips/ar7/Makefile kernel-current/arch/mips/ar7/Makefile
3157 --- kernel-base/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
3158 +++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 08:23:55.081408136 +0200
3159 @@ -0,0 +1,29 @@
3160 +# $Id$
3161 +# Copyright (C) $Date$ $Author$
3162 +#
3163 +# This program is free software; you can redistribute it and/or modify
3164 +# it under the terms of the GNU General Public License as published by
3165 +# the Free Software Foundation; either version 2 of the License, or
3166 +# (at your option) any later version.
3167 +#
3168 +# This program is distributed in the hope that it will be useful,
3169 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
3170 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3171 +# GNU General Public License for more details.
3172 +#
3173 +# You should have received a copy of the GNU General Public License
3174 +# along with this program; if not, write to the Free Software
3175 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3176 +
3177 +.S.s:
3178 + $(CPP) $(AFLAGS) $< -o $*.s
3179 +
3180 +.S.o:
3181 + $(CC) $(AFLAGS) -c $< -o $*.o
3182 +
3183 +O_TARGET := ar7.o
3184 +
3185 +export-objs := init.o irq.o
3186 +obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
3187 +
3188 +include $(TOPDIR)/Rules.make
3189 diff -urN kernel-base/arch/mips/ar7/memory.c kernel-current/arch/mips/ar7/memory.c
3190 --- kernel-base/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
3191 +++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266560 +0200
3192 @@ -0,0 +1,130 @@
3193 +/*
3194 + * Carsten Langgaard, carstenl@mips.com
3195 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
3196 + *
3197 + * ########################################################################
3198 + *
3199 + * This program is free software; you can distribute it and/or modify it
3200 + * under the terms of the GNU General Public License (Version 2) as
3201 + * published by the Free Software Foundation.
3202 + *
3203 + * This program is distributed in the hope it will be useful, but WITHOUT
3204 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3205 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3206 + * for more details.
3207 + *
3208 + * You should have received a copy of the GNU General Public License along
3209 + * with this program; if not, write to the Free Software Foundation, Inc.,
3210 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3211 + *
3212 + * ########################################################################
3213 + *
3214 + * PROM library functions for acquiring/using memory descriptors given to
3215 + * us from the YAMON.
3216 + *
3217 + */
3218 +#include <linux/config.h>
3219 +#include <linux/init.h>
3220 +#include <linux/mm.h>
3221 +#include <linux/bootmem.h>
3222 +
3223 +#include <asm/bootinfo.h>
3224 +#include <asm/page.h>
3225 +#include <asm/mips-boards/prom.h>
3226 +#include <asm/ar7/ar7.h>
3227 +
3228 +enum yamon_memtypes {
3229 + yamon_dontuse,
3230 + yamon_prom,
3231 + yamon_free,
3232 +};
3233 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
3234 +
3235 +/* References to section boundaries */
3236 +extern char _end;
3237 +
3238 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
3239 +
3240 +
3241 +struct prom_pmemblock * __init prom_getmdesc(void)
3242 +{
3243 + char *memsize_str;
3244 + unsigned int memsize;
3245 +
3246 + memsize_str = prom_getenv("memsize");
3247 + if (!memsize_str) {
3248 + memsize = 0x02000000;
3249 + } else {
3250 + memsize = simple_strtol(memsize_str, NULL, 0);
3251 + }
3252 +
3253 + memset(mdesc, 0, sizeof(mdesc));
3254 +
3255 + mdesc[0].type = yamon_dontuse;
3256 + mdesc[0].base = 0x00000000;
3257 + mdesc[0].size = CONFIG_AR7_MEMORY;
3258 +
3259 + mdesc[1].type = yamon_prom;
3260 + mdesc[1].base = CONFIG_AR7_MEMORY;
3261 + mdesc[1].size = 0x00020000;
3262 +
3263 + mdesc[2].type = yamon_free;
3264 + mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
3265 + mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
3266 +
3267 + return &mdesc[0];
3268 +}
3269 +
3270 +static int __init prom_memtype_classify (unsigned int type)
3271 +{
3272 + switch (type) {
3273 + case yamon_free:
3274 + return BOOT_MEM_RAM;
3275 + case yamon_prom:
3276 + return BOOT_MEM_ROM_DATA;
3277 + default:
3278 + return BOOT_MEM_RESERVED;
3279 + }
3280 +}
3281 +
3282 +void __init prom_meminit(void)
3283 +{
3284 + struct prom_pmemblock *p;
3285 +
3286 + p = prom_getmdesc();
3287 +
3288 + while (p->size) {
3289 + long type;
3290 + unsigned long base, size;
3291 +
3292 + type = prom_memtype_classify (p->type);
3293 + base = p->base;
3294 + size = p->size;
3295 +
3296 + add_memory_region(base, size, type);
3297 + p++;
3298 + }
3299 +}
3300 +
3301 +void __init prom_free_prom_memory (void)
3302 +{
3303 + int i;
3304 + unsigned long freed = 0;
3305 + unsigned long addr;
3306 +
3307 + for (i = 0; i < boot_mem_map.nr_map; i++) {
3308 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
3309 + continue;
3310 +
3311 + addr = boot_mem_map.map[i].addr;
3312 + while (addr < boot_mem_map.map[i].addr
3313 + + boot_mem_map.map[i].size) {
3314 + ClearPageReserved(virt_to_page(__va(addr)));
3315 + set_page_count(virt_to_page(__va(addr)), 1);
3316 + free_page((unsigned long)__va(addr));
3317 + addr += PAGE_SIZE;
3318 + freed += PAGE_SIZE;
3319 + }
3320 + }
3321 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
3322 +}
3323 diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-current/arch/mips/ar7/mipsIRQ.S
3324 --- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
3325 +++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266408 +0200
3326 @@ -0,0 +1,120 @@
3327 +/*
3328 + * Carsten Langgaard, carstenl@mips.com
3329 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
3330 + *
3331 + * ########################################################################
3332 + *
3333 + * This program is free software; you can distribute it and/or modify it
3334 + * under the terms of the GNU General Public License (Version 2) as
3335 + * published by the Free Software Foundation.
3336 + *
3337 + * This program is distributed in the hope it will be useful, but WITHOUT
3338 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3339 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3340 + * for more details.
3341 + *
3342 + * You should have received a copy of the GNU General Public License along
3343 + * with this program; if not, write to the Free Software Foundation, Inc.,
3344 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3345 + *
3346 + * ########################################################################
3347 + *
3348 + * Interrupt exception dispatch code.
3349 + *
3350 + */
3351 +#include <linux/config.h>
3352 +
3353 +#include <asm/asm.h>
3354 +#include <asm/mipsregs.h>
3355 +#include <asm/regdef.h>
3356 +#include <asm/stackframe.h>
3357 +
3358 +/* A lot of complication here is taken away because:
3359 + *
3360 + * 1) We handle one interrupt and return, sitting in a loop and moving across
3361 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
3362 + * common case is one pending IRQ so optimize in that direction.
3363 + *
3364 + * 2) We need not check against bits in the status register IRQ mask, that
3365 + * would make this routine slow as hell.
3366 + *
3367 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
3368 + * between like BSD spl() brain-damage.
3369 + *
3370 + * Furthermore, the IRQs on the MIPS board look basically (barring software
3371 + * IRQs which we don't use at all and all external interrupt sources are
3372 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
3373 + *
3374 + * MIPS IRQ Source
3375 + * -------- ------
3376 + * 0 Software (ignored)
3377 + * 1 Software (ignored)
3378 + * 2 Combined hardware interrupt (hw0)
3379 + * 3 Hardware (ignored)
3380 + * 4 Hardware (ignored)
3381 + * 5 Hardware (ignored)
3382 + * 6 Hardware (ignored)
3383 + * 7 R4k timer (what we use)
3384 + *
3385 + * Note: On the SEAD board thing are a little bit different.
3386 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
3387 + * wired to UART1.
3388 + *
3389 + * We handle the IRQ according to _our_ priority which is:
3390 + *
3391 + * Highest ---- R4k Timer
3392 + * Lowest ---- Combined hardware interrupt
3393 + *
3394 + * then we just return, if multiple IRQs are pending then we will just take
3395 + * another exception, big deal.
3396 + */
3397 +
3398 +.text
3399 +.set noreorder
3400 +.set noat
3401 + .align 5
3402 +NESTED(mipsIRQ, PT_SIZE, sp)
3403 + SAVE_ALL
3404 + CLI
3405 + .set at
3406 +
3407 + mfc0 s0, CP0_CAUSE # get irq bits
3408 +
3409 + /* First we check for r4k counter/timer IRQ. */
3410 + andi a0, s0, CAUSEF_IP7
3411 + beq a0, zero, 1f
3412 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
3413 +
3414 + /* Wheee, a timer interrupt. */
3415 + move a0, sp
3416 + jal ar7_timer_interrupt
3417 + nop
3418 +
3419 + j ret_from_irq
3420 + nop
3421 +
3422 + 1:
3423 + beq a0, zero, 1f # delay slot, check hw3 interrupt
3424 + nop
3425 +
3426 + /* Wheee, combined hardware level zero interrupt. */
3427 + jal avalanche_hw0_irqdispatch
3428 + move a0, sp # delay slot
3429 +
3430 + j ret_from_irq
3431 + nop # delay slot
3432 +
3433 + 1:
3434 + /*
3435 + * Here by mistake? This is possible, what can happen is that by the
3436 + * time we take the exception the IRQ pin goes low, so just leave if
3437 + * this is the case.
3438 + */
3439 + move a1,s0
3440 + PRINT("Got interrupt: c0_cause = %08x\n")
3441 + mfc0 a1, CP0_EPC
3442 + PRINT("c0_epc = %08x\n")
3443 +
3444 + j ret_from_irq
3445 + nop
3446 +END(mipsIRQ)
3447 diff -urN kernel-base/arch/mips/ar7/printf.c kernel-current/arch/mips/ar7/printf.c
3448 --- kernel-base/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
3449 +++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266408 +0200
3450 @@ -0,0 +1,54 @@
3451 +/*
3452 + * Carsten Langgaard, carstenl@mips.com
3453 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
3454 + *
3455 + * This program is free software; you can distribute it and/or modify it
3456 + * under the terms of the GNU General Public License (Version 2) as
3457 + * published by the Free Software Foundation.
3458 + *
3459 + * This program is distributed in the hope it will be useful, but WITHOUT
3460 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3461 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3462 + * for more details.
3463 + *
3464 + * You should have received a copy of the GNU General Public License along
3465 + * with this program; if not, write to the Free Software Foundation, Inc.,
3466 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3467 + *
3468 + * Putting things on the screen/serial line using Adam2 facilities.
3469 + */
3470 +
3471 +#include <linux/config.h>
3472 +#include <linux/init.h>
3473 +#include <linux/kernel.h>
3474 +#include <linux/serial_reg.h>
3475 +#include <linux/spinlock.h>
3476 +#include <asm/io.h>
3477 +#include <asm/serial.h>
3478 +#include <asm/addrspace.h>
3479 +#include <asm/ar7/ar7.h>
3480 +
3481 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3482 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3483 +
3484 +static char ppbuf[1024];
3485 +
3486 +void (*prom_print_str)(unsigned int out, char *s, int len);
3487 +
3488 +void prom_printf(char *fmt, ...) __init;
3489 +void prom_printf(char *fmt, ...)
3490 +{
3491 + va_list args;
3492 + int len;
3493 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
3494 +
3495 + va_start(args, fmt);
3496 + vsprintf(ppbuf, fmt, args);
3497 + len = strlen(ppbuf);
3498 +
3499 + prom_print_str(1, ppbuf, len);
3500 +
3501 + va_end(args);
3502 + return;
3503 +
3504 +}
3505 diff -urN kernel-base/arch/mips/ar7/reset.c kernel-current/arch/mips/ar7/reset.c
3506 --- kernel-base/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
3507 +++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266408 +0200
3508 @@ -0,0 +1,54 @@
3509 +/*
3510 + * Carsten Langgaard, carstenl@mips.com
3511 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
3512 + *
3513 + * ########################################################################
3514 + *
3515 + * This program is free software; you can distribute it and/or modify it
3516 + * under the terms of the GNU General Public License (Version 2) as
3517 + * published by the Free Software Foundation.
3518 + *
3519 + * This program is distributed in the hope it will be useful, but WITHOUT
3520 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3521 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3522 + * for more details.
3523 + *
3524 + * You should have received a copy of the GNU General Public License along
3525 + * with this program; if not, write to the Free Software Foundation, Inc.,
3526 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3527 + *
3528 + * ########################################################################
3529 + *
3530 + * Reset the MIPS boards.
3531 + *
3532 + */
3533 +#include <linux/config.h>
3534 +
3535 +#include <asm/reboot.h>
3536 +#include <asm/mips-boards/generic.h>
3537 +
3538 +static void ar7_machine_restart(char *command);
3539 +static void ar7_machine_halt(void);
3540 +static void ar7_machine_power_off(void);
3541 +
3542 +static void ar7_machine_restart(char *command)
3543 +{
3544 +
3545 +}
3546 +
3547 +static void ar7_machine_halt(void)
3548 +{
3549 +
3550 +}
3551 +
3552 +static void ar7_machine_power_off(void)
3553 +{
3554 +
3555 +}
3556 +
3557 +void ar7_reboot_setup(void)
3558 +{
3559 + _machine_restart = ar7_machine_restart;
3560 + _machine_halt = ar7_machine_halt;
3561 + _machine_power_off = ar7_machine_power_off;
3562 +}
3563 diff -urN kernel-base/arch/mips/ar7/setup.c kernel-current/arch/mips/ar7/setup.c
3564 --- kernel-base/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
3565 +++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266256 +0200
3566 @@ -0,0 +1,120 @@
3567 +/*
3568 + * Carsten Langgaard, carstenl@mips.com
3569 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
3570 + *
3571 + * This program is free software; you can distribute it and/or modify it
3572 + * under the terms of the GNU General Public License (Version 2) as
3573 + * published by the Free Software Foundation.
3574 + *
3575 + * This program is distributed in the hope it will be useful, but WITHOUT
3576 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3577 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3578 + * for more details.
3579 + *
3580 + * You should have received a copy of the GNU General Public License along
3581 + * with this program; if not, write to the Free Software Foundation, Inc.,
3582 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3583 + */
3584 +#include <linux/config.h>
3585 +#include <linux/init.h>
3586 +#include <linux/sched.h>
3587 +#include <linux/mc146818rtc.h>
3588 +#include <linux/ioport.h>
3589 +
3590 +#include <asm/cpu.h>
3591 +#include <asm/bootinfo.h>
3592 +#include <asm/irq.h>
3593 +#include <asm/mips-boards/generic.h>
3594 +#include <asm/mips-boards/prom.h>
3595 +
3596 +#include <asm/dma.h>
3597 +#include <asm/time.h>
3598 +#include <asm/traps.h>
3599 +
3600 +#ifdef CONFIG_KGDB
3601 +extern void rs_kgdb_hook(int);
3602 +int remote_debug = 0;
3603 +#endif
3604 +
3605 +extern struct rtc_ops no_rtc_ops;
3606 +
3607 +extern void ar7_reboot_setup(void);
3608 +
3609 +extern void ar7_time_init(void);
3610 +extern void ar7_timer_setup(struct irqaction *irq);
3611 +
3612 +const char *get_system_type(void)
3613 +{
3614 + return "Texas Instruments AR7";
3615 +}
3616 +
3617 +void __init ar7_setup(void)
3618 +{
3619 +#ifdef CONFIG_KGDB
3620 + int rs_putDebugChar(char);
3621 + char rs_getDebugChar(void);
3622 + extern int (*generic_putDebugChar)(char);
3623 + extern char (*generic_getDebugChar)(void);
3624 +#endif
3625 + char *argptr;
3626 +#ifdef CONFIG_SERIAL_CONSOLE
3627 + argptr = prom_getcmdline();
3628 + if ((argptr = strstr(argptr, "console=")) == NULL) {
3629 + char console[20];
3630 + char *s;
3631 + int i = 0;
3632 +
3633 + s = prom_getenv("modetty0");
3634 + strcpy(console, "38400");
3635 +
3636 + if (s != NULL) {
3637 + while (s[i] >= '0' && s[i] <= '9')
3638 + i++;
3639 +
3640 + if (i > 0) {
3641 + strncpy(console, s, i);
3642 + console[i] = 0;
3643 + }
3644 + }
3645 +
3646 + argptr = prom_getcmdline();
3647 + strcat(argptr, " console=ttyS0,");
3648 + strcat(argptr, console);
3649 + }
3650 +#endif
3651 +
3652 +#ifdef CONFIG_KGDB
3653 + argptr = prom_getcmdline();
3654 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
3655 + int line;
3656 + argptr += strlen("kgdb=ttyS");
3657 + if (*argptr != '0' && *argptr != '1')
3658 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
3659 + "falling back to /dev/ttyS1\n", *argptr);
3660 + line = *argptr == '0' ? 0 : 1;
3661 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
3662 + line ? 1 : 0);
3663 +
3664 + rs_kgdb_hook(line);
3665 + generic_putDebugChar = rs_putDebugChar;
3666 + generic_getDebugChar = rs_getDebugChar;
3667 +
3668 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
3669 + "please connect your debugger\n", line ? 1 : 0);
3670 +
3671 + remote_debug = 1;
3672 + /* Breakpoints are in init_IRQ() */
3673 + }
3674 +#endif
3675 +
3676 + argptr = prom_getcmdline();
3677 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
3678 + cpu_data[0].options &= ~MIPS_CPU_FPU;
3679 +
3680 + rtc_ops = &no_rtc_ops;
3681 +
3682 + ar7_reboot_setup();
3683 +
3684 + board_time_init = ar7_time_init;
3685 + board_timer_setup = ar7_timer_setup;
3686 +}
3687 diff -urN kernel-base/arch/mips/ar7/time.c kernel-current/arch/mips/ar7/time.c
3688 --- kernel-base/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
3689 +++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266256 +0200
3690 @@ -0,0 +1,125 @@
3691 +/*
3692 + * Carsten Langgaard, carstenl@mips.com
3693 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
3694 + *
3695 + * ########################################################################
3696 + *
3697 + * This program is free software; you can distribute it and/or modify it
3698 + * under the terms of the GNU General Public License (Version 2) as
3699 + * published by the Free Software Foundation.
3700 + *
3701 + * This program is distributed in the hope it will be useful, but WITHOUT
3702 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3703 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3704 + * for more details.
3705 + *
3706 + * You should have received a copy of the GNU General Public License along
3707 + * with this program; if not, write to the Free Software Foundation, Inc.,
3708 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3709 + *
3710 + * ########################################################################
3711 + *
3712 + * Setting up the clock on the MIPS boards.
3713 + *
3714 + */
3715 +
3716 +#include <linux/types.h>
3717 +#include <linux/config.h>
3718 +#include <linux/init.h>
3719 +#include <linux/kernel_stat.h>
3720 +#include <linux/sched.h>
3721 +#include <linux/spinlock.h>
3722 +
3723 +#include <asm/mipsregs.h>
3724 +#include <asm/ptrace.h>
3725 +#include <asm/hardirq.h>
3726 +#include <asm/div64.h>
3727 +
3728 +#include <linux/interrupt.h>
3729 +#include <linux/mc146818rtc.h>
3730 +#include <linux/timex.h>
3731 +
3732 +#include <asm/mips-boards/generic.h>
3733 +#include <asm/mips-boards/prom.h>
3734 +#include <asm/ar7/ar7.h>
3735 +
3736 +extern asmlinkage void mipsIRQ(void);
3737 +
3738 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
3739 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
3740 +
3741 +#define MIPS_CPU_TIMER_IRQ 7
3742 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
3743 +
3744 +static inline void ack_r4ktimer(unsigned long newval)
3745 +{
3746 + write_c0_compare(newval);
3747 +}
3748 +
3749 +void ar7_timer_interrupt(struct pt_regs *regs)
3750 +{
3751 + int cpu = smp_processor_id();
3752 +
3753 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
3754 +
3755 + if (r4k_offset == 0)
3756 + goto null;
3757 +
3758 + do {
3759 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
3760 + do_timer(regs);
3761 + r4k_cur += r4k_offset;
3762 + ack_r4ktimer(r4k_cur);
3763 +
3764 + } while (((unsigned long)read_c0_count()
3765 + - r4k_cur) < 0x7fffffff);
3766 +
3767 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
3768 +
3769 + if (softirq_pending(cpu))
3770 + do_softirq();
3771 +
3772 + return;
3773 +
3774 +null:
3775 + ack_r4ktimer(0);
3776 +}
3777 +
3778 +/*
3779 + * Figure out the r4k offset, the amount to increment the compare
3780 + * register for each time tick.
3781 + */
3782 +static unsigned long __init cal_r4koff(void)
3783 +{
3784 + return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ);
3785 +}
3786 +
3787 +void __init ar7_time_init(void)
3788 +{
3789 + unsigned long flags;
3790 + unsigned int est_freq;
3791 +
3792 + set_except_vector(0, mipsIRQ);
3793 + write_c0_count(0);
3794 +
3795 + printk("calculating r4koff... ");
3796 + r4k_offset = cal_r4koff();
3797 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
3798 +
3799 + est_freq = 2*r4k_offset*HZ;
3800 + est_freq += 5000; /* round */
3801 + est_freq -= est_freq%10000;
3802 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
3803 + (est_freq%1000000)*100/1000000);
3804 +}
3805 +
3806 +void __init ar7_timer_setup(struct irqaction *irq)
3807 +{
3808 + /* we are using the cpu counter for timer interrupts */
3809 + irq->handler = no_action; /* we use our own handler */
3810 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
3811 +
3812 + r4k_cur = (read_c0_count() + r4k_offset);
3813 + write_c0_compare(r4k_cur);
3814 + set_c0_status(ALLINTS);
3815 +}
3816 diff -urN kernel-base/arch/mips/config-shared.in kernel-current/arch/mips/config-shared.in
3817 --- kernel-base/arch/mips/config-shared.in 2005-07-10 03:00:44.784181376 +0200
3818 +++ kernel-current/arch/mips/config-shared.in 2005-07-10 06:40:39.589266104 +0200
3819 @@ -20,6 +20,16 @@
3820 mainmenu_option next_comment
3821 comment 'Machine selection'
3822 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3823 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3824 +if [ "$CONFIG_AR7" = "y" ]; then
3825 + choice 'Texas Instruments Reference Platform' \
3826 + "AR7DB CONFIG_AR7DB \
3827 + AR7RD CONFIG_AR7RD \
3828 + AR7WRD CONFIG_AR7WRD" AR7DB
3829 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU_FREQUENCY 150
3830 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS_FREQUENCY 125
3831 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3832 +fi
3833 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3834 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3835 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3836 @@ -239,6 +249,11 @@
3837 define_bool CONFIG_NONCOHERENT_IO y
3838 define_bool CONFIG_PC_KEYB y
3839 fi
3840 +if [ "$CONFIG_AR7" = "y" ]; then
3841 + define_bool CONFIG_NONCOHERENT_IO y
3842 + define_bool CONFIG_SWAP_IO_SPACE y
3843 + define_bool CONFIG_AR7_PAGING y
3844 +fi
3845 if [ "$CONFIG_CASIO_E55" = "y" ]; then
3846 define_bool CONFIG_IRQ_CPU y
3847 define_bool CONFIG_NONCOHERENT_IO y
3848 @@ -736,6 +751,7 @@
3849 mainmenu_option next_comment
3850 comment 'General setup'
3851 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3852 + "$CONFIG_AR7" = "y" -o \
3853 "$CONFIG_CASIO_E55" = "y" -o \
3854 "$CONFIG_DDB5074" = "y" -o \
3855 "$CONFIG_DDB5476" = "y" -o \
3856 @@ -797,6 +813,7 @@
3857 bool 'Networking support' CONFIG_NET
3858
3859 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3860 + "$CONFIG_AR7" = "y" -o \
3861 "$CONFIG_CASIO_E55" = "y" -o \
3862 "$CONFIG_DECSTATION" = "y" -o \
3863 "$CONFIG_IBM_WORKPAD" = "y" -o \
3864 diff -urN kernel-base/arch/mips/kernel/irq.c kernel-current/arch/mips/kernel/irq.c
3865 --- kernel-base/arch/mips/kernel/irq.c 2005-07-10 03:00:44.784181376 +0200
3866 +++ kernel-current/arch/mips/kernel/irq.c 2005-07-10 06:40:39.589266104 +0200
3867 @@ -76,6 +76,7 @@
3868 * Generic, controller-independent functions:
3869 */
3870
3871 +#ifndef CONFIG_AR7
3872 int get_irq_list(char *buf)
3873 {
3874 int i, j;
3875 @@ -110,6 +111,7 @@
3876 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3877 return p - buf;
3878 }
3879 +#endif
3880
3881 #ifdef CONFIG_SMP
3882 int global_irq_holder = NO_PROC_ID;
3883 @@ -525,6 +527,7 @@
3884 *
3885 */
3886
3887 +#ifndef CONFIG_AR7
3888 int request_irq(unsigned int irq,
3889 void (*handler)(int, void *, struct pt_regs *),
3890 unsigned long irqflags,
3891 @@ -569,6 +572,7 @@
3892 kfree(action);
3893 return retval;
3894 }
3895 +#endif
3896
3897 /**
3898 * free_irq - free an interrupt
3899 @@ -588,6 +592,7 @@
3900 * the machine.
3901 */
3902
3903 +#ifndef CONFIG_AR7
3904 void free_irq(unsigned int irq, void *dev_id)
3905 {
3906 irq_desc_t *desc;
3907 @@ -629,6 +634,7 @@
3908 return;
3909 }
3910 }
3911 +#endif
3912
3913 /*
3914 * IRQ autodetection code..
3915 diff -urN kernel-base/arch/mips/kernel/mips_ksyms.c kernel-current/arch/mips/kernel/mips_ksyms.c
3916 --- kernel-base/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
3917 +++ kernel-current/arch/mips/kernel/mips_ksyms.c 2005-07-10 10:08:15.469684456 +0200
3918 @@ -40,6 +40,10 @@
3919 extern long __strnlen_user_nocheck_asm(const char *s);
3920 extern long __strnlen_user_asm(const char *s);
3921
3922 +#ifdef CONFIG_AR7
3923 +extern int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3924 +#endif
3925 +
3926 EXPORT_SYMBOL(mips_machtype);
3927 #ifdef CONFIG_EISA
3928 EXPORT_SYMBOL(EISA_bus);
3929 @@ -102,4 +106,8 @@
3930 EXPORT_SYMBOL(ide_ops);
3931 #endif
3932
3933 +#ifdef CONFIG_AR7
3934 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3935 +#endif
3936 +
3937 EXPORT_SYMBOL(get_wchan);
3938 diff -urN kernel-base/arch/mips/kernel/setup.c kernel-current/arch/mips/kernel/setup.c
3939 --- kernel-base/arch/mips/kernel/setup.c 2005-07-10 03:00:44.785181224 +0200
3940 +++ kernel-current/arch/mips/kernel/setup.c 2005-07-10 06:40:39.590265952 +0200
3941 @@ -109,6 +109,7 @@
3942 unsigned long isa_slot_offset;
3943 EXPORT_SYMBOL(isa_slot_offset);
3944
3945 +extern void avalanche_bootmem_init(void);
3946 extern void SetUpBootInfo(void);
3947 extern void load_mmu(void);
3948 extern asmlinkage void start_kernel(void);
3949 @@ -267,6 +268,9 @@
3950 #endif /* CONFIG_BLK_DEV_INITRD */
3951
3952 /* Find the highest page frame number we have available. */
3953 +#ifdef CONFIG_AR7_PAGING
3954 + avalanche_bootmem_init();
3955 +#else
3956 max_pfn = 0;
3957 first_usable_pfn = -1UL;
3958 for (i = 0; i < boot_mem_map.nr_map; i++) {
3959 @@ -377,6 +381,7 @@
3960 /* Reserve the bootmap memory. */
3961 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3962
3963 +#endif
3964 #ifdef CONFIG_BLK_DEV_INITRD
3965 /* Board specific code should have set up initrd_start and initrd_end */
3966 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3967 @@ -494,6 +499,7 @@
3968 void hp_setup(void);
3969 void au1x00_setup(void);
3970 void frame_info_init(void);
3971 + void ar7_setup(void);
3972
3973 frame_info_init();
3974 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3975 @@ -691,6 +697,11 @@
3976 pmc_yosemite_setup();
3977 break;
3978 #endif
3979 +#ifdef CONFIG_AR7
3980 + case MACH_GROUP_UNKNOWN:
3981 + ar7_setup();
3982 + break;
3983 +#endif
3984 default:
3985 panic("Unsupported architecture");
3986 }
3987 diff -urN kernel-base/arch/mips/kernel/traps.c kernel-current/arch/mips/kernel/traps.c
3988 --- kernel-base/arch/mips/kernel/traps.c 2005-07-10 03:00:44.786181072 +0200
3989 +++ kernel-current/arch/mips/kernel/traps.c 2005-07-10 06:40:39.591265800 +0200
3990 @@ -40,6 +40,10 @@
3991 #include <asm/uaccess.h>
3992 #include <asm/mmu_context.h>
3993
3994 +#ifdef CONFIG_AR7
3995 +#include <asm/ar7/ar7.h>
3996 +#endif
3997 +
3998 extern asmlinkage void handle_mod(void);
3999 extern asmlinkage void handle_tlbl(void);
4000 extern asmlinkage void handle_tlbs(void);
4001 @@ -869,9 +873,15 @@
4002
4003 exception_handlers[n] = handler;
4004 if (n == 0 && cpu_has_divec) {
4005 +#ifdef CONFIG_AR7
4006 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
4007 + (0x03ffffff & (handler >> 2));
4008 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
4009 +#else
4010 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
4011 (0x03ffffff & (handler >> 2));
4012 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
4013 +#endif
4014 }
4015 return (void *)old_handler;
4016 }
4017 @@ -920,14 +930,46 @@
4018 void __init trap_init(void)
4019 {
4020 extern char except_vec1_generic;
4021 + extern char except_vec2_generic;
4022 extern char except_vec3_generic, except_vec3_r4000;
4023 extern char except_vec_ejtag_debug;
4024 extern char except_vec4;
4025 unsigned long i;
4026
4027 +#ifdef CONFIG_AR7
4028 + extern char jump_tlb_miss, jump_tlb_miss_unused;
4029 + extern char jump_cache_error,jump_general_exception;
4030 + extern char jump_dedicated_interrupt;
4031 + clear_c0_status(ST0_BEV);
4032 +#endif
4033 +
4034 /* Copy the generic exception handler code to it's final destination. */
4035 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
4036 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
4037 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
4038
4039 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
4040 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
4041 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
4042 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
4043 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
4044 +
4045 +#ifdef CONFIG_AR7
4046 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
4047 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
4048 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
4049 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
4050 +
4051 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
4052 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
4053 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
4054 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
4055 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
4056 +#else
4057 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
4058 +#endif
4059 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
4060 +
4061 /*
4062 * Setup default vectors
4063 */
4064 @@ -951,8 +993,12 @@
4065 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
4066 * interrupt processing overhead. Use it where available.
4067 */
4068 +#ifdef CONFIG_AR7
4069 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
4070 +#else
4071 if (cpu_has_divec)
4072 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
4073 +#endif
4074
4075 /*
4076 * Some CPUs can enable/disable for cache parity detection, but does
4077 @@ -991,12 +1037,17 @@
4078 if (cpu_has_mcheck)
4079 set_except_vector(24, handle_mcheck);
4080
4081 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
4082 +#ifdef CONFIG_AR7
4083 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
4084 +#else
4085 if (cpu_has_vce)
4086 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
4087 else if (cpu_has_4kex)
4088 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
4089 else
4090 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
4091 +#endif
4092
4093 if (current_cpu_data.cputype == CPU_R6000 ||
4094 current_cpu_data.cputype == CPU_R6000A) {
4095 @@ -1023,7 +1074,11 @@
4096 if (board_nmi_handler_setup)
4097 board_nmi_handler_setup();
4098
4099 +#ifdef CONFIG_AR7
4100 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
4101 +#else
4102 flush_icache_range(KSEG0, KSEG0 + 0x400);
4103 +#endif
4104
4105 per_cpu_trap_init();
4106 }
4107 diff -urN kernel-base/arch/mips/lib/promlib.c kernel-current/arch/mips/lib/promlib.c
4108 --- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
4109 +++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265800 +0200
4110 @@ -1,3 +1,4 @@
4111 +#ifndef CONFIG_AR7
4112 #include <stdarg.h>
4113 #include <linux/kernel.h>
4114
4115 @@ -22,3 +23,4 @@
4116 }
4117 va_end(args);
4118 }
4119 +#endif
4120 diff -urN kernel-base/arch/mips/Makefile kernel-current/arch/mips/Makefile
4121 --- kernel-base/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200
4122 +++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265800 +0200
4123 @@ -369,6 +369,16 @@
4124 endif
4125
4126 #
4127 +# Texas Instruments AR7
4128 +#
4129 +
4130 +ifdef CONFIG_AR7
4131 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
4132 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/ar7
4133 +LOADADDR += 0x94020000
4134 +endif
4135 +
4136 +#
4137 # DECstation family
4138 #
4139 ifdef CONFIG_DECSTATION
4140 diff -urN kernel-base/arch/mips/mm/init.c kernel-current/arch/mips/mm/init.c
4141 --- kernel-base/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200
4142 +++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216728 +0200
4143 @@ -40,8 +40,10 @@
4144
4145 mmu_gather_t mmu_gathers[NR_CPUS];
4146 unsigned long highstart_pfn, highend_pfn;
4147 +#ifndef CONFIG_AR7_PAGING
4148 static unsigned long totalram_pages;
4149 static unsigned long totalhigh_pages;
4150 +#endif
4151
4152 void pgd_init(unsigned long page)
4153 {
4154 @@ -235,6 +237,7 @@
4155 #endif
4156 }
4157
4158 +#ifndef CONFIG_AR7_PAGING
4159 void __init paging_init(void)
4160 {
4161 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
4162 @@ -272,6 +275,7 @@
4163
4164 free_area_init(zones_size);
4165 }
4166 +#endif
4167
4168 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
4169 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
4170 @@ -298,6 +302,7 @@
4171 return 0;
4172 }
4173
4174 +#ifndef CONFIG_AR7_PAGING
4175 void __init mem_init(void)
4176 {
4177 unsigned long codesize, reservedpages, datasize, initsize;
4178 @@ -359,6 +364,7 @@
4179 initsize >> 10,
4180 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
4181 }
4182 +#endif
4183
4184 #ifdef CONFIG_BLK_DEV_INITRD
4185 void free_initrd_mem(unsigned long start, unsigned long end)
4186 @@ -376,6 +382,7 @@
4187 }
4188 #endif
4189
4190 +#ifndef CONFIG_AR7_PAGING
4191 extern char __init_begin, __init_end;
4192 extern void prom_free_prom_memory(void) __init;
4193
4194 @@ -383,7 +390,9 @@
4195 {
4196 unsigned long addr;
4197
4198 +#ifndef CONFIG_AR7
4199 prom_free_prom_memory ();
4200 +#endif
4201
4202 addr = (unsigned long) &__init_begin;
4203 while (addr < (unsigned long) &__init_end) {
4204 @@ -409,3 +418,4 @@
4205
4206 return;
4207 }
4208 +#endif
4209 diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-current/arch/mips/mm/tlb-r4k.c
4210 --- kernel-base/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200
4211 +++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265648 +0200
4212 @@ -20,6 +20,10 @@
4213 #include <asm/pgtable.h>
4214 #include <asm/system.h>
4215
4216 +#ifdef CONFIG_AR7
4217 +#include <asm/ar7/ar7.h>
4218 +#endif
4219 +
4220 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
4221
4222 /* CP0 hazard avoidance. */
4223 @@ -375,7 +379,12 @@
4224 else if (current_cpu_data.cputype == CPU_R4600)
4225 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
4226 else
4227 +#ifdef CONFIG_AR7
4228 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
4229 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
4230 +#else
4231 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
4232 flush_icache_range(KSEG0, KSEG0 + 0x80);
4233 +#endif
4234 }
4235 }
4236 diff -urN kernel-base/drivers/char/serial.c kernel-current/drivers/char/serial.c
4237 --- kernel-base/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200
4238 +++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600552 +0200
4239 @@ -419,7 +419,40 @@
4240 return 0;
4241 }
4242
4243 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
4244 +#if defined(CONFIG_AR7)
4245 +
4246 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
4247 +{
4248 + return (inb(info->port + (offset * 4)) & 0xff);
4249 +}
4250 +
4251 +
4252 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
4253 +{
4254 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
4255 + return (inb(info->port + (offset * 4)) & 0xff);
4256 +#else
4257 + return (inb_p(info->port + (offset * 4)) & 0xff);
4258 +#endif
4259 +}
4260 +
4261 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
4262 +{
4263 + outb(value, info->port + (offset * 4));
4264 +}
4265 +
4266 +
4267 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
4268 + int value)
4269 +{
4270 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
4271 + outb(value, info->port + (offset * 4));
4272 +#else
4273 + outb_p(value, info->port + (offset * 4));
4274 +#endif
4275 +}
4276 +
4277 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
4278
4279 #include <asm/mips-boards/atlas.h>
4280
4281 @@ -478,8 +511,10 @@
4282 * needed for certain old 386 machines, I've left these #define's
4283 * in....
4284 */
4285 +#ifndef CONFIG_AR7
4286 #define serial_inp(info, offset) serial_in(info, offset)
4287 #define serial_outp(info, offset, value) serial_out(info, offset, value)
4288 +#endif
4289
4290
4291 /*
4292 @@ -1728,7 +1763,16 @@
4293 /* Special case since 134 is really 134.5 */
4294 quot = (2*baud_base / 269);
4295 else if (baud)
4296 +#ifdef CONFIG_AR7
4297 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
4298 + //quot = get_avalanche_vbus_freq() / baud;
4299 +
4300 + if ((quot%16)>7)
4301 + quot += 8;
4302 + quot /=16;
4303 +#else
4304 quot = baud_base / baud;
4305 +#endif
4306 }
4307 /* If the quotient is zero refuse the change */
4308 if (!quot && old_termios) {
4309 @@ -5552,8 +5596,10 @@
4310 state->irq = irq_cannonicalize(state->irq);
4311 if (state->hub6)
4312 state->io_type = SERIAL_IO_HUB6;
4313 +#ifndef CONFIG_AR7
4314 if (state->port && check_region(state->port,8))
4315 continue;
4316 +#endif
4317 #ifdef CONFIG_MCA
4318 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
4319 continue;
4320 @@ -6009,7 +6055,16 @@
4321 info->io_type = state->io_type;
4322 info->iomem_base = state->iomem_base;
4323 info->iomem_reg_shift = state->iomem_reg_shift;
4324 +#ifdef CONFIG_AR7
4325 + //quot = get_avalanche_vbus_freq() / baud;
4326 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
4327 +
4328 + if ((quot%16)>7)
4329 + quot += 8;
4330 + quot /=16;
4331 +#else
4332 quot = state->baud_base / baud;
4333 +#endif
4334 cval = cflag & (CSIZE | CSTOPB);
4335 #if defined(__powerpc__) || defined(__alpha__)
4336 cval >>= 8;
4337 diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-current/include/asm-mips/ar7/ar7.h
4338 --- kernel-base/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
4339 +++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261088 +0200
4340 @@ -0,0 +1,33 @@
4341 +/*
4342 + * $Id$
4343 + * Copyright (C) $Date$ $Author$
4344 + *
4345 + * This program is free software; you can redistribute it and/or modify
4346 + * it under the terms of the GNU General Public License as published by
4347 + * the Free Software Foundation; either version 2 of the License, or
4348 + * (at your option) any later version.
4349 + *
4350 + * This program is distributed in the hope that it will be useful,
4351 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4352 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4353 + * GNU General Public License for more details.
4354 + *
4355 + * You should have received a copy of the GNU General Public License
4356 + * along with this program; if not, write to the Free Software
4357 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4358 + *
4359 + */
4360 +
4361 +#ifndef _AR7_H
4362 +#define _AR7_H
4363 +
4364 +#include <asm/addrspace.h>
4365 +#include <linux/config.h>
4366 +
4367 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
4368 +
4369 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
4370 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00))
4371 +#define AR7_BASE_BAUD ( 3686400 / 16 )
4372 +
4373 +#endif
4374 diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-current/include/asm-mips/ar7/avalanche_intc.h
4375 --- kernel-base/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
4376 +++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261088 +0200
4377 @@ -0,0 +1,278 @@
4378 + /*
4379 + * Nitin Dhingra, iamnd@ti.com
4380 + * Copyright (C) 2000 Texas Instruments Inc.
4381 + *
4382 + *
4383 + * ########################################################################
4384 + *
4385 + * This program is free software; you can distribute it and/or modify it
4386 + * under the terms of the GNU General Public License (Version 2) as
4387 + * published by the Free Software Foundation.
4388 + *
4389 + * This program is distributed in the hope it will be useful, but WITHOUT
4390 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4391 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4392 + * for more details.
4393 + *
4394 + * You should have received a copy of the GNU General Public License along
4395 + * with this program; if not, write to the Free Software Foundation, Inc.,
4396 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4397 + *
4398 + * ########################################################################
4399 + *
4400 + * Defines of the Sead board specific address-MAP, registers, etc.
4401 + *
4402 + */
4403 +#ifndef _AVALANCHE_INTC_H
4404 +#define _AVALANCHE_INTC_H
4405 +
4406 +#define MIPS_EXCEPTION_OFFSET 8
4407 +
4408 +/******************************************************************************
4409 + Avalanche Interrupt number
4410 +******************************************************************************/
4411 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
4412 +
4413 +/*******************************************************************************
4414 +*Linux Interrupt number
4415 +*******************************************************************************/
4416 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
4417 +
4418 +
4419 +
4420 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
4421 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
4422 +
4423 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
4424 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
4425 +
4426 +
4427 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
4428 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
4429 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
4430 +
4431 +
4432 +/*
4433 + * Avalanche interrupt controller register base (primary)
4434 + */
4435 +#define KSEG1_BASE 0xA0000000
4436 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
4437 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
4438 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
4439 +
4440 +#define AVALANCHE_ICTRL_REGS_BASE KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE
4441 +
4442 +/******************************************************************************
4443 + * Avalanche exception controller register base (secondary)
4444 + ******************************************************************************/
4445 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
4446 +
4447 +
4448 +/******************************************************************************
4449 + * Avalanche Interrupt pacing register base (secondary)
4450 + ******************************************************************************/
4451 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
4452 +
4453 +
4454 +
4455 +/******************************************************************************
4456 + * Avalanche Interrupt Channel Control register base
4457 + *****************************************************************************/
4458 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
4459 +
4460 +
4461 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
4462 +{
4463 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
4464 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
4465 + volatile unsigned long unused1; /*0x08 */
4466 + volatile unsigned long unused2; /*0x0C */
4467 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
4468 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
4469 + volatile unsigned long unused3; /*0x18 */
4470 + volatile unsigned long unused4; /*0x1C */
4471 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
4472 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
4473 + volatile unsigned long unused5; /*0x28 */
4474 + volatile unsigned long unused6; /*0x2C */
4475 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
4476 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
4477 + volatile unsigned long unused7; /* 0x38 */
4478 + volatile unsigned long unused8; /* 0x3c */
4479 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
4480 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
4481 + volatile unsigned long unused9; /* 0x48 */
4482 + volatile unsigned long unused10; /* 0x4C */
4483 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
4484 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
4485 + volatile unsigned long unused11; /* 0x58 */
4486 + volatile unsigned long unused12; /*0x5C */
4487 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
4488 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
4489 +};
4490 +
4491 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
4492 +{
4493 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
4494 + volatile unsigned long reserved; /*0x84 */
4495 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
4496 + volatile unsigned long reserved1; /*0x8c */
4497 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
4498 + volatile unsigned long reserved2; /*0x94 */
4499 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
4500 +};
4501 +struct avalanche_ipace_regs
4502 +{
4503 +
4504 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
4505 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
4506 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
4507 +};
4508 +struct avalanche_channel_int_number
4509 +{
4510 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
4511 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
4512 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
4513 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
4514 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
4515 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
4516 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
4517 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
4518 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
4519 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
4520 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
4521 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
4522 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
4523 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
4524 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
4525 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
4526 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
4527 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
4528 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
4529 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
4530 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
4531 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
4532 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
4533 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
4534 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
4535 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
4536 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
4537 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
4538 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
4539 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
4540 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
4541 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
4542 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
4543 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
4544 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
4545 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
4546 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
4547 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
4548 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
4549 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
4550 +};
4551 +
4552 +struct avalanche_interrupt_line_to_channel
4553 +{
4554 + unsigned long int_line0; /* Start of primary interrupts */
4555 + unsigned long int_line1;
4556 + unsigned long int_line2;
4557 + unsigned long int_line3;
4558 + unsigned long int_line4;
4559 + unsigned long int_line5;
4560 + unsigned long int_line6;
4561 + unsigned long int_line7;
4562 + unsigned long int_line8;
4563 + unsigned long int_line9;
4564 + unsigned long int_line10;
4565 + unsigned long int_line11;
4566 + unsigned long int_line12;
4567 + unsigned long int_line13;
4568 + unsigned long int_line14;
4569 + unsigned long int_line15;
4570 + unsigned long int_line16;
4571 + unsigned long int_line17;
4572 + unsigned long int_line18;
4573 + unsigned long int_line19;
4574 + unsigned long int_line20;
4575 + unsigned long int_line21;
4576 + unsigned long int_line22;
4577 + unsigned long int_line23;
4578 + unsigned long int_line24;
4579 + unsigned long int_line25;
4580 + unsigned long int_line26;
4581 + unsigned long int_line27;
4582 + unsigned long int_line28;
4583 + unsigned long int_line29;
4584 + unsigned long int_line30;
4585 + unsigned long int_line31;
4586 + unsigned long int_line32;
4587 + unsigned long int_line33;
4588 + unsigned long int_line34;
4589 + unsigned long int_line35;
4590 + unsigned long int_line36;
4591 + unsigned long int_line37;
4592 + unsigned long int_line38;
4593 + unsigned long int_line39;
4594 +};
4595 +
4596 +
4597 +/* Interrupt Line #'s (Sangam peripherals) */
4598 +
4599 +/*------------------------------*/
4600 +/* Sangam primary interrupts */
4601 +/*------------------------------*/
4602 +
4603 +#define UNIFIED_SECONDARY_INTERRUPT 0
4604 +#define AVALANCHE_EXT_INT_0 1
4605 +#define AVALANCHE_EXT_INT_1 2
4606 +/* Line #3 Reserved */
4607 +/* Line #4 Reserved */
4608 +#define AVALANCHE_TIMER_0_INT 5
4609 +#define AVALANCHE_TIMER_1_INT 6
4610 +#define AVALANCHE_UART0_INT 7
4611 +#define AVALANCHE_UART1_INT 8
4612 +#define AVALANCHE_PDMA_INT0 9
4613 +#define AVALANCHE_PDMA_INT1 10
4614 +/* Line #11 Reserved */
4615 +/* Line #12 Reserved */
4616 +/* Line #13 Reserved */
4617 +/* Line #14 Reserved */
4618 +#define AVALANCHE_ATM_SAR_INT 15
4619 +/* Line #16 Reserved */
4620 +/* Line #17 Reserved */
4621 +/* Line #18 Reserved */
4622 +#define AVALANCHE_MAC0_INT 19
4623 +/* Line #20 Reserved */
4624 +#define AVALANCHE_VLYNQ0_INT 21
4625 +#define AVALANCHE_CODEC_WAKE_INT 22
4626 +/* Line #23 Reserved */
4627 +#define AVALANCHE_USB_INT 24
4628 +#define AVALANCHE_VLYNQ1_INT 25
4629 +/* Line #26 Reserved */
4630 +/* Line #27 Reserved */
4631 +#define AVALANCHE_MAC1_INT 28
4632 +#define AVALANCHE_I2CM_INT 29
4633 +#define AVALANCHE_PDMA_INT2 30
4634 +#define AVALANCHE_PDMA_INT3 31
4635 +/* Line #32 Reserved */
4636 +/* Line #33 Reserved */
4637 +/* Line #34 Reserved */
4638 +/* Line #35 Reserved */
4639 +/* Line #36 Reserved */
4640 +#define AVALANCHE_VDMA_VT_RX_INT 37
4641 +#define AVALANCHE_VDMA_VT_TX_INT 38
4642 +#define AVALANCHE_ADSLSS_INT 39
4643 +
4644 +/*-----------------------------------*/
4645 +/* Sangam Secondary Interrupts */
4646 +/*-----------------------------------*/
4647 +#define PRIMARY_INTS 40
4648 +
4649 +#define EMIF_INT (7 + PRIMARY_INTS)
4650 +
4651 +
4652 +extern void avalanche_int_set(int channel, int line);
4653 +
4654 +
4655 +#endif /* _AVALANCHE_INTC_H */
4656 diff -urN kernel-base/include/asm-mips/ar7/avalanche_regs.h kernel-current/include/asm-mips/ar7/avalanche_regs.h
4657 --- kernel-base/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4658 +++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 09:27:48.638618856 +0200
4659 @@ -0,0 +1,567 @@
4660 +/*
4661 + * $Id$
4662 + * Avalanche Register Descriptions
4663 + *
4664 + * Jeff Harrell, jharrell@ti.com
4665 + * 2000 (c) Texas Instruments Inc.
4666 + */
4667 +
4668 +#ifndef __AVALANCHE_REGS_H
4669 +#define __AVALANCHE_REGS_H
4670 +
4671 +#include <asm/addrspace.h>
4672 +#include <linux/config.h>
4673 +
4674 +/*----------------------------------------*/
4675 +/* Base offsets within the Avalanche ASIC */
4676 +/*----------------------------------------*/
4677 +
4678 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4679 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4680 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4681 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4682 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4683 +#define DES_BASE (KSEG1ADDR(0x08600000))
4684 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4685 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4686 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4687 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4688 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4689 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4690 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4691 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4692 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4693 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4694 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4695 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4696 +#define USB_BASE (KSEG1ADDR(0x08611200))
4697 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4698 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4699 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4700 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4701 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4702 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4703 +
4704 +/*---------------------------------*/
4705 +/* Device ID, chip version number */
4706 +/*---------------------------------*/
4707 +
4708 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4709 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4710 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4711 +
4712 +/*----------------------------------*/
4713 +/* Reset Control VW changed to ptrs */
4714 +/*----------------------------------*/
4715 +
4716 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4717 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4718 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4719 +
4720 +/* reset control bits */
4721 +
4722 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4723 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4724 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4725 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4726 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4727 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4728 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4729 +/*
4730 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4731 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4732 + interface pins are inputs and must be reconfigured so as not to lose the
4733 + serial console interface
4734 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4735 +*/
4736 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4737 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4738 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4739 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4740 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4741 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4742 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4743 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4744 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4745 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4746 +
4747 +/*----------------------*/
4748 +/* Physical interfaces */
4749 +/*----------------------*/
4750 +
4751 +/* Phy loopback */
4752 +#define PHY_LOOPBACK 1
4753 +
4754 +
4755 +/* Phy 0 */
4756 +#define PHY0BASE (PHY_BASE)
4757 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4758 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4759 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4760 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4761 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4762 +
4763 +
4764 +/* Phy 1 */
4765 +
4766 +#define PHY1BASE (PHY_BASE + 0x100000)
4767 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4768 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4769 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4770 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4771 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4772 +
4773 +/* Phy 2 */
4774 +
4775 +#define PHY2BASE (PHY_BASE + 0x200000)
4776 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4777 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4778 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4779 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4780 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4781 +
4782 +/*-------------------*/
4783 +/* Avalanche ATM SAR */
4784 +/*-------------------*/
4785 +
4786 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4787 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4788 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4789 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4790 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4791 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4792 +
4793 +/* Transmit completion ring registers */
4794 +
4795 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4796 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4797 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4798 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4799 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4800 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4801 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4802 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4803 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4804 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4805 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4806 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4807 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4808 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4809 +
4810 +/* Transmit Queue Packet registers */
4811 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4812 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4813 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4814 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4815 +/* Receive completion ring registers */
4816 +
4817 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4818 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4819 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4820 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4821 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4822 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4823 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4824 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4825 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4826 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4827 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4828 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4829 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4830 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4831 +
4832 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4833 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4834 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4835 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4836 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4837 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4838 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4839 +
4840 +
4841 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4842 +
4843 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4844 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4845 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4846 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4847 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4848 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4849 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4850 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4851 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4852 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4853 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4854 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4855 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4856 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4857 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4858 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4859 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4860 +
4861 +
4862 +/*
4863 +
4864 +#define OAM_CPID_ADD 0xa30104e0
4865 +
4866 +#define OAM_LLID_ADD 0xa30104f0
4867 +
4868 +#define OAM_LLID_VAL 0xffffffff
4869 +
4870 +#define OAM_CORR_TAG 0xa3010500
4871 +
4872 +#define OAM_FAR_COUNT_ADD 0xa3010520
4873 +
4874 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4875 +
4876 +#define OAM_CONFIG_REG_ADD 0xa3000018
4877 +*/
4878 +
4879 +
4880 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4881 +
4882 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4883 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4884 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4885 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4886 +
4887 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4888 +
4889 +
4890 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4891 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4892 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4893 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4894 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4895 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4896 +
4897 +/*------------------------------------------*/
4898 +/* DSL Interface */
4899 +/*------------------------------------------*/
4900 +
4901 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4902 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4903 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4904 +
4905 +/* Fast */
4906 +
4907 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4908 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4909 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4910 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4911 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4912 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4913 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4914 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4915 +
4916 +/* Interleaved */
4917 +
4918 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4919 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4920 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4921 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4922 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4923 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4924 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4925 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4926 +
4927 +/*------------------------------------------*/
4928 +/* Broadband I/F */
4929 +/*------------------------------------------*/
4930 +
4931 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4932 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4933 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4934 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4935 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4936 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4937 +
4938 +#define AVBBIF_DISABLED 0x0
4939 +#define AVBBIF_LBT4040_INT 0x1
4940 +#define AVBBIF_XBUS 0x2
4941 +#define AVBBIF_LBT4040_EXT 0x4
4942 +
4943 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4944 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4945 +#define AVBBIF_TRANS_MASK 0xff000000
4946 +/*------------------------------------------*/
4947 +/* GPIO I/F */
4948 +/*------------------------------------------*/
4949 +
4950 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4951 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4952 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4953 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4954 +
4955 +#define GPIO_0 (1<<21)
4956 +#define GPIO_1 (1<<22)
4957 +#define GPIO_2 (1<<23)
4958 +#define GPIO_3 (1<<24)
4959 +#define EINT_1 (1<<18)
4960 +
4961 +/*
4962 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4963 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4964 + interface pins are inputs and must be reconfigured so as not to lose the
4965 + serial console interface
4966 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4967 +*/
4968 +
4969 +/*------------------------------------------*/
4970 +/* CLK_CTRL */
4971 +/*------------------------------------------*/
4972 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4973 +
4974 +#define PCLK_0_HALF_VBUS (0<<16)
4975 +#define PCLK_EQ_INPUT (1<<16)
4976 +#define BBIF_CLK_HALF_VBUS (0<<17)
4977 +#define BBIF_CLK_EQ_VBUS (1<<17)
4978 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4979 +#define DSP_MODCLK_DSPCLKI (0<<20)
4980 +#define DSP_MODCLK_REFCLKI (1<<20)
4981 +#define USB_CLK_EQ_USBCLKI (0<<21)
4982 +#define USB_CLK_EQ_REFCLKI (1<<21)
4983 +
4984 +/*------------------------------------------*/
4985 +/* PCI Control Registers */
4986 +/*------------------------------------------*/
4987 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4988 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4989 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4990 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4991 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4992 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4993 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4994 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4995 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4996 +#define PCIC_CONTROL_IO_MASK (1<<8)
4997 +/* PCIC_CONTROL_RESERVED (1<<9) */
4998 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4999 +#define PCIC_CONTROL_BASE1_EN (1<<11)
5000 +#define PCIC_CONTROL_BASE2_EN (1<<12)
5001 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
5002 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
5003 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
5004 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
5005 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
5006 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
5007 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
5008 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
5009 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
5010 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
5011 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
5012 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
5013 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
5014 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
5015 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
5016 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
5017 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
5018 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
5019 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
5020 +#define PCIC_INT_CLEAR_PM (1<<0)
5021 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
5022 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
5023 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
5024 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
5025 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
5026 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
5027 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
5028 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
5029 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
5030 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
5031 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
5032 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
5033 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
5034 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
5035 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
5036 +#define PCIC_INT_EN_AVAL_PM (1<<0)
5037 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
5038 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
5039 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
5040 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
5041 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
5042 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
5043 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
5044 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
5045 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
5046 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
5047 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
5048 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
5049 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
5050 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
5051 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
5052 +#define PCIC_INT_EN_PCI_PM (1<<0)
5053 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
5054 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
5055 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
5056 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
5057 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
5058 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
5059 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
5060 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
5061 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
5062 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
5063 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
5064 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
5065 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
5066 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
5067 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
5068 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
5069 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
5070 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
5071 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
5072 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
5073 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
5074 +/* PCIC_PM_CTL_RESERVED (1<<2) */
5075 +/* PCIC_PM_CTL_RESERVED (1<<3) */
5076 +/* PCIC_PM_CTL_RESERVED (1<<4) */
5077 +/* PCIC_PM_CTL_RESERVED (1<<5) */
5078 +/* PCIC_PM_CTL_RESERVED (1<<6) */
5079 +/* PCIC_PM_CTL_RESERVED (1<<7) */
5080 +/* PCIC_PM_CTL_RESERVED (1<<8) */
5081 +/* PCIC_PM_CTL_RESERVED (1<<9) */
5082 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
5083 +#define PCIC_PM_CTL_PMEIN (1<<11)
5084 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
5085 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
5086 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
5087 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
5088 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
5089 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
5090 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
5091 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
5092 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
5093 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
5094 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
5095 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
5096 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
5097 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
5098 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
5099 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
5100 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
5101 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
5102 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
5103 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
5104 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
5105 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
5106 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
5107 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
5108 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
5109 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
5110 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
5111 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
5112 +
5113 +/*------------------------------------------*/
5114 +/* IIC_INTERFACE */
5115 +/*------------------------------------------*/
5116 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
5117 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
5118 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
5119 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
5120 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
5121 +
5122 +#define I2CWRITE 0x200
5123 +#define I2CREAD 0x300
5124 +#define I2C_END_BURST 0x400
5125 +
5126 +/* read bits */
5127 +#define I2C_READ_ERROR 0x8000
5128 +#define I2C_READ_COMPLETE 0x4000
5129 +#define I2C_READ_BUSY 0x2000
5130 +
5131 +/* device types */
5132 +#define I2C_IO_EXPANDER 0x2
5133 +#define I2C_RTC 0xd
5134 +
5135 +/* device Addresses on I2C bus (EVM3) */
5136 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
5137 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
5138 +#define EVM3_RTC_I2C_ADDR 0x0
5139 +
5140 +/*------------------------------------------*/
5141 +/* Ethernet MAC register offset definitions */
5142 +/*------------------------------------------*/
5143 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
5144 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
5145 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
5146 +
5147 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
5148 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
5149 +
5150 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
5151 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
5152 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
5153 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
5154 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
5155 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
5156 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
5157 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
5158 +
5159 +
5160 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
5161 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
5162 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
5163 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
5164 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
5165 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
5166 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
5167 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
5168 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
5169 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
5170 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
5171 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
5172 +
5173 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
5174 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
5175 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
5176 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
5177 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
5178 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
5179 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
5180 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
5181 +
5182 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
5183 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
5184 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
5185 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
5186 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
5187 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
5188 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
5189 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
5190 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
5191 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
5192 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
5193 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
5194 +
5195 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
5196 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
5197 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
5198 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
5199 +
5200 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
5201 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
5202 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
5203 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
5204 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
5205 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
5206 +
5207 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
5208 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
5209 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
5210 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
5211 +
5212 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
5213 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
5214 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
5215 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
5216 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
5217 +
5218 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
5219 +
5220 +#endif __AVALANCHE_REGS_H
5221 +
5222 +
5223 +
5224 +
5225 +
5226 +
5227 diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-current/include/asm-mips/ar7/if_port.h
5228 --- kernel-base/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
5229 +++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260936 +0200
5230 @@ -0,0 +1,26 @@
5231 +/*******************************************************************************
5232 + * FILE PURPOSE: Interface port id Header file
5233 + *******************************************************************************
5234 + * FILE NAME: if_port.h
5235 + *
5236 + * DESCRIPTION: Header file carrying information about port ids of interfaces
5237 + *
5238 + *
5239 + * (C) Copyright 2003, Texas Instruments, Inc
5240 + ******************************************************************************/
5241 +#ifndef _IF_PORT_H_
5242 +#define _IF_PORT_H_
5243 +
5244 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
5245 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
5246 +#define AVALANCHE_USB_PORT_ID 2
5247 +#define AVALANCHE_WLAN_PORT_ID 3
5248 +
5249 +
5250 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
5251 +
5252 +/* The marvell ports occupy port ids from 4 to 8 */
5253 +/* so the next port id number should start at 9 */
5254 +
5255 +
5256 +#endif /* _IF_PORT_H_ */
5257 diff -urN kernel-base/include/asm-mips/ar7/ledapp.h kernel-current/include/asm-mips/ar7/ledapp.h
5258 --- kernel-base/include/asm-mips/ar7/ledapp.h 1970-01-01 01:00:00.000000000 +0100
5259 +++ kernel-current/include/asm-mips/ar7/ledapp.h 2005-07-10 08:26:11.663644480 +0200
5260 @@ -0,0 +1,59 @@
5261 +#ifndef __LED_APP__
5262 +#define __LED_APP__
5263 +
5264 +#define CONF_FILE "/etc/led.conf"
5265 +#define LED_PROC_FILE "/proc/led_mod/led"
5266 +
5267 +#define CONFIG_LED_MODULE
5268 +
5269 +#define MAX_MOD_ID 25
5270 +#define MAX_STATE_ID 25
5271 +#define MAX_LED_ID 25
5272 +
5273 +#define MOD_ADSL 1
5274 +#define DEF_ADSL_IDLE 1
5275 +#define DEF_ADSL_TRAINING 2
5276 +#define DEF_ADSL_SYNC 3
5277 +#define DEF_ADSL_ACTIVITY 4
5278 +
5279 +#define MOD_WAN 2
5280 +#define DEF_WAN_IDLE 1
5281 +#define DEF_WAN_NEGOTIATE 2
5282 +#define DEF_WAN_SESSION 3
5283 +
5284 +#define MOD_LAN 3
5285 +#define DEF_LAN_IDLE 1
5286 +#define DEF_LAN_LINK_UP 2
5287 +#define DEF_LAN_ACTIVITY 3
5288 +
5289 +#define MOD_WLAN 4
5290 +#define DEF_WLAN_IDLE 1
5291 +#define DEF_WLAN_LINK_UP 2
5292 +#define DEF_WLAN_ACTIVITY 3
5293 +
5294 +#define MOD_USB 5
5295 +#define DEF_USB_IDLE 1
5296 +#define DEF_USB_LINK_UP 2
5297 +#define DEF_USB_ACTIVITY 3
5298 +
5299 +#define MOD_ETH 6
5300 +#define DEF_ETH_IDLE 1
5301 +#define DEF_ETH_LINK_UP 2
5302 +#define DEF_ETH_ACTIVITY 3
5303 +
5304 +typedef struct config_elem{
5305 + unsigned char name;
5306 + unsigned char state;
5307 + unsigned char mode;
5308 + unsigned char led;
5309 + int param;
5310 +}config_elem_t;
5311 +
5312 +typedef struct led_reg{
5313 + unsigned int param;
5314 + void (*init)(unsigned long param);
5315 + void (*onfunc)(unsigned long param);
5316 + void (*offfunc)(unsigned long param);
5317 +}led_reg_t;
5318 +
5319 +#endif
5320 diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-current/include/asm-mips/ar7/sangam_boards.h
5321 --- kernel-base/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
5322 +++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260936 +0200
5323 @@ -0,0 +1,77 @@
5324 +#ifndef _SANGAM_BOARDS_H
5325 +#define _SANGAM_BOARDS_H
5326 +
5327 +// Let us define board specific information here.
5328 +
5329 +
5330 +#if defined(CONFIG_AR7DB)
5331 +
5332 +#define AFECLK_FREQ 35328000
5333 +#define REFCLK_FREQ 25000000
5334 +#define OSC3_FREQ 24000000
5335 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5336 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
5337 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5338 +
5339 +#endif
5340 +
5341 +
5342 +#if defined(CONFIG_AR7RD)
5343 +#define AFECLK_FREQ 35328000
5344 +#define REFCLK_FREQ 25000000
5345 +#define OSC3_FREQ 24000000
5346 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5347 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5348 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5349 +#endif
5350 +
5351 +
5352 +#if defined(CONFIG_AR7WI)
5353 +#define AFECLK_FREQ 35328000
5354 +#define REFCLK_FREQ 25000000
5355 +#define OSC3_FREQ 24000000
5356 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5357 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5358 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5359 +#endif
5360 +
5361 +
5362 +#if defined(CONFIG_AR7V)
5363 +#define AFECLK_FREQ 35328000
5364 +#define REFCLK_FREQ 25000000
5365 +#define OSC3_FREQ 24000000
5366 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5367 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5368 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5369 +#endif
5370 +
5371 +
5372 +#if defined(CONFIG_AR7WRD)
5373 +#define AFECLK_FREQ 35328000
5374 +#define REFCLK_FREQ 25000000
5375 +#define OSC3_FREQ 24000000
5376 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5377 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
5378 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5379 +#endif
5380 +
5381 +
5382 +#if defined(CONFIG_AR7VWI)
5383 +#define AFECLK_FREQ 35328000
5384 +#define REFCLK_FREQ 25000000
5385 +#define OSC3_FREQ 24000000
5386 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5387 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
5388 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5389 +#endif
5390 +
5391 +
5392 +#if defined CONFIG_SEAD2
5393 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
5394 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
5395 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
5396 +#include <asm/mips-boards/sead.h>
5397 +#endif
5398 +
5399 +
5400 +#endif
5401 diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-current/include/asm-mips/ar7/sangam.h
5402 --- kernel-base/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
5403 +++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260784 +0200
5404 @@ -0,0 +1,180 @@
5405 +#ifndef _SANGAM_H_
5406 +#define _SANGAM_H_
5407 +
5408 +#include <linux/config.h>
5409 +#include <asm/addrspace.h>
5410 +
5411 +/*----------------------------------------------------
5412 + * Sangam's Module Base Addresses
5413 + *--------------------------------------------------*/
5414 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
5415 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
5416 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
5417 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
5418 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
5419 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
5420 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
5421 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
5422 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
5423 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
5424 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
5425 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
5426 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
5427 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
5428 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
5429 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
5430 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
5431 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
5432 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
5433 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
5434 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
5435 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
5436 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
5437 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
5438 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
5439 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
5440 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
5441 +
5442 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
5443 +
5444 +
5445 +/*----------------------------------------------------
5446 + * Sangam Interrupt Map (Primary Interrupts)
5447 + *--------------------------------------------------*/
5448 +
5449 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
5450 +#define AVALANCHE_EXT_INT_0 1
5451 +#define AVALANCHE_EXT_INT_1 2
5452 +/* Line# 3 to 4 are reserved */
5453 +#define AVALANCHE_TIMER_0_INT 5
5454 +#define AVALANCHE_TIMER_1_INT 6
5455 +#define AVALANCHE_UART0_INT 7
5456 +#define AVALANCHE_UART1_INT 8
5457 +#define AVALANCHE_DMA_INT0 9
5458 +#define AVALANCHE_DMA_INT1 10
5459 +/* Line# 11 to 14 are reserved */
5460 +#define AVALANCHE_ATM_SAR_INT 15
5461 +/* Line# 16 to 18 are reserved */
5462 +#define AVALANCHE_LOW_CPMAC_INT 19
5463 +/* Line# 20 is reserved */
5464 +#define AVALANCHE_LOW_VLYNQ_INT 21
5465 +#define AVALANCHE_CODEC_WAKEUP_INT 22
5466 +/* Line# 23 is reserved */
5467 +#define AVALANCHE_USB_SLAVE_INT 24
5468 +#define AVALANCHE_HIGH_VLYNQ_INT 25
5469 +/* Line# 26 to 27 are reserved */
5470 +#define AVALANCHE_UNIFIED_PHY_INT 28
5471 +#define AVALANCHE_I2C_INT 29
5472 +#define AVALANCHE_DMA_INT2 30
5473 +#define AVALANCHE_DMA_INT3 31
5474 +/* Line# 32 is reserved */
5475 +#define AVALANCHE_HIGH_CPMAC_INT 33
5476 +/* Line# 34 to 36 is reserved */
5477 +#define AVALANCHE_VDMA_VT_RX_INT 37
5478 +#define AVALANCHE_VDMA_VT_TX_INT 38
5479 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
5480 +
5481 +
5482 +#define AVALANCHE_EMIF_INT 47
5483 +
5484 +
5485 +
5486 +/*-----------------------------------------------------------
5487 + * Sangam's Reset Bits
5488 + *---------------------------------------------------------*/
5489 +
5490 +#define AVALANCHE_UART0_RESET_BIT 0
5491 +#define AVALANCHE_UART1_RESET_BIT 1
5492 +#define AVALANCHE_I2C_RESET_BIT 2
5493 +#define AVALANCHE_TIMER0_RESET_BIT 3
5494 +#define AVALANCHE_TIMER1_RESET_BIT 4
5495 +/* Reset bit 5 is reserved. */
5496 +#define AVALANCHE_GPIO_RESET_BIT 6
5497 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
5498 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
5499 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
5500 +/* Reset bit 10 is reserved. */
5501 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
5502 +#define AVALANCHE_FSER_RESET_BIT 12
5503 +/* Reset bit 13 to 15 are reserved */
5504 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
5505 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
5506 +#define AVALANCHE_MCDMA_RESET_BIT 18
5507 +#define AVALANCHE_BIST_RESET_BIT 19
5508 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
5509 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
5510 +#define AVALANCHE_MDIO_RESET_BIT 22
5511 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
5512 +/* Reset bit 24 to 25 are reserved */
5513 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
5514 +/* Reset bit 27 to 31 are reserved */
5515 +
5516 +
5517 +#define AVALANCHE_POWER_MODULE_USBSP 0
5518 +#define AVALANCHE_POWER_MODULE_WDTP 1
5519 +#define AVALANCHE_POWER_MODULE_UT0P 2
5520 +#define AVALANCHE_POWER_MODULE_UT1P 3
5521 +#define AVALANCHE_POWER_MODULE_IICP 4
5522 +#define AVALANCHE_POWER_MODULE_VDMAP 5
5523 +#define AVALANCHE_POWER_MODULE_GPIOP 6
5524 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
5525 +#define AVALANCHE_POWER_MODULE_SARP 8
5526 +#define AVALANCHE_POWER_MODULE_ADSLP 9
5527 +#define AVALANCHE_POWER_MODULE_EMIFP 10
5528 +#define AVALANCHE_POWER_MODULE_ADSPP 12
5529 +#define AVALANCHE_POWER_MODULE_RAMP 13
5530 +#define AVALANCHE_POWER_MODULE_ROMP 14
5531 +#define AVALANCHE_POWER_MODULE_DMAP 15
5532 +#define AVALANCHE_POWER_MODULE_BISTP 16
5533 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
5534 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
5535 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
5536 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
5537 +#define AVALANCHE_POWER_MODULE_EPHYP 24
5538 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
5539 +
5540 +
5541 +
5542 +
5543 +
5544 +/*
5545 + * Sangam board vectors
5546 + */
5547 +
5548 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
5549 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
5550 +
5551 +/*-----------------------------------------------------------------------------
5552 + * Sangam's system register.
5553 + *
5554 + *---------------------------------------------------------------------------*/
5555 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
5556 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
5557 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
5558 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
5559 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
5560 +
5561 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
5562 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
5563 +
5564 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
5565 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
5566 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
5567 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
5568 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
5569 +
5570 +/*
5571 + * Yamon Prom print address.
5572 + */
5573 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
5574 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
5575 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
5576 +
5577 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
5578 +
5579 +#define AVALANCHE_GPIO_PIN_COUNT 32
5580 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
5581 +
5582 +#include "sangam_boards.h"
5583 +
5584 +#endif /*_SANGAM_H_ */
5585 diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_err.h kernel-current/include/asm-mips/ar7/tnetd73xx_err.h
5586 --- kernel-base/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
5587 +++ kernel-current/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-10 09:34:36.482617144 +0200
5588 @@ -0,0 +1,42 @@
5589 +/******************************************************************************
5590 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5591 + ******************************************************************************
5592 + * FILE NAME: tnetd73xx_err.h
5593 + *
5594 + * DESCRIPTION: Error definations for TNETD73XX
5595 + *
5596 + * REVISION HISTORY:
5597 + * 27 Nov 02 - PSP TII
5598 + *
5599 + * (C) Copyright 2002, Texas Instruments, Inc
5600 + *******************************************************************************/
5601 +
5602 +
5603 +#ifndef __TNETD73XX_ERR_H__
5604 +#define __TNETD73XX_ERR_H__
5605 +
5606 +typedef enum TNETD73XX_ERR_t
5607 +{
5608 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5609 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5610 +
5611 + /* Pointers and args */
5612 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5613 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5614 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5615 +
5616 + /* Memory issues */
5617 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5618 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5619 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5620 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5621 +
5622 + /* Device issues */
5623 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5624 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5625 +
5626 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5627 +
5628 +} TNETD73XX_ERR;
5629 +
5630 +#endif /* __TNETD73XX_ERR_H__ */
5631 diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx.h kernel-current/include/asm-mips/ar7/tnetd73xx.h
5632 --- kernel-base/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
5633 +++ kernel-current/include/asm-mips/ar7/tnetd73xx.h 2005-07-10 09:51:18.910224984 +0200
5634 @@ -0,0 +1,338 @@
5635 +/******************************************************************************
5636 + * FILE PURPOSE: TNETD73xx Common Header File
5637 + ******************************************************************************
5638 + * FILE NAME: tnetd73xx.h
5639 + *
5640 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
5641 + *
5642 + * REVISION HISTORY:
5643 + * 27 Nov 02 - PSP TII
5644 + *
5645 + * (C) Copyright 2002, Texas Instruments, Inc
5646 + *******************************************************************************/
5647 +
5648 +/*
5649 + *
5650 + *
5651 + * These are const, typedef, and api definitions for tnetd73xx.
5652 + *
5653 + * NOTES:
5654 + * 1. This file may be included into both C and Assembly files.
5655 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5656 + * avoid C data types (typedefs) below;
5657 + * - for .c files, you don't have to do anything special.
5658 + *
5659 + * 2. This file has a number of sections for each SOC subsystem. When adding
5660 + * a new constant, find the subsystem you are working on and follow the
5661 + * name pattern. If you are adding another typedef for your interface, please,
5662 + * place it with other typedefs and function prototypes.
5663 + *
5664 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5665 + * cluttering. Include such items directly into the module's .c file or have a
5666 + * local .h file to pass data between smaller modules. This file defines only
5667 + * shared items.
5668 + */
5669 +
5670 +#ifndef __TNETD73XX_H__
5671 +#define __TNETD73XX_H__
5672 +
5673 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
5674 +
5675 +extern unsigned int tnetd73xx_mips_freq;
5676 +extern unsigned int tnetd73xx_vbus_freq;
5677 +
5678 +#include "tnetd73xx_err.h"
5679 +
5680 +#endif /* _ASMLANGUAGE */
5681 +
5682 +
5683 +/*******************************************************************************************
5684 +* Emerald core specific
5685 +******************************************************************************************** */
5686 +
5687 +#ifdef BIG_ENDIAN
5688 +#elif defined(LITTLE_ENDIAN)
5689 +#else
5690 +#error Need to define endianism
5691 +#endif
5692 +
5693 +#ifndef KSEG_MSK
5694 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5695 +#endif
5696 +
5697 +#ifndef KSEG_INV_MASK
5698 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5699 +#endif
5700 +
5701 +#ifndef KSEG0_BASE
5702 +#define KSEG0_BASE 0x80000000
5703 +#endif
5704 +
5705 +#ifndef KSEG1_BASE
5706 +#define KSEG1_BASE 0xA0000000
5707 +#endif
5708 +
5709 +#ifndef KSEG0
5710 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5711 +#endif
5712 +
5713 +#ifndef KSEG1
5714 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5715 +#endif
5716 +
5717 +#ifndef KUSEG
5718 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
5719 +#endif
5720 +
5721 +#ifndef PHYS_ADDR
5722 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5723 +#endif
5724 +
5725 +#ifndef PHYS_TO_K0
5726 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5727 +#endif
5728 +
5729 +#ifndef PHYS_TO_K1
5730 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5731 +#endif
5732 +
5733 +#ifndef REG8_ADDR
5734 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
5735 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
5736 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5737 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
5738 +#endif
5739 +
5740 +#ifndef REG16_ADDR
5741 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
5742 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
5743 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5744 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
5745 +#endif
5746 +
5747 +#ifndef REG32_ADDR
5748 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
5749 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
5750 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5751 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
5752 +#endif
5753 +
5754 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5755 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5756 +#endif
5757 +
5758 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5759 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5760 +#endif
5761 +
5762 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5763 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5764 +#endif
5765 +
5766 +/* TNETD73XX chip definations */
5767 +
5768 +#define FREQ_1MHZ 1000000
5769 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5770 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5771 +
5772 +#ifdef AR7SEAD2
5773 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5774 +#else
5775 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5776 +#endif
5777 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5778 +
5779 +
5780 +
5781 +/* Module base addresses */
5782 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5783 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5784 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5785 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5786 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5787 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5788 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5789 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5790 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5791 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5792 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5793 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5794 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5795 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5796 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5797 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5798 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5799 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5800 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5801 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5802 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5803 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5804 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5805 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5806 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5807 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5808 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5809 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5810 +
5811 +/* BBIF Registers */
5812 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5813 +
5814 +/* Device Configuration Latch Registers */
5815 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5816 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5817 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5818 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5819 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5820 +
5821 +/* GPIO Control */
5822 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5823 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5824 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5825 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5826 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5827 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5828 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5829 +
5830 +/* Reset Control */
5831 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5832 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5833 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5834 +
5835 +/* Power Control */
5836 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5837 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5838 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5839 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5840 +
5841 +/* Clock Control */
5842 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5843 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5844 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5845 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5846 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5847 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5848 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5849 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5850 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5851 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5852 +
5853 +/* EMIF control */
5854 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5855 +
5856 +/* UART */
5857 +#ifdef AR7SEAD2
5858 +#define TNETD73XX_UART_FREQ 3686400
5859 +#else
5860 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5861 +#endif
5862 +
5863 +/* Interrupt Controller */
5864 +
5865 +/* Primary interrupts */
5866 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5867 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5868 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5869 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5870 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5871 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5872 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5873 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5874 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5875 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5876 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5877 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5878 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5879 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5880 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5881 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5882 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5883 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5884 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5885 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5886 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5887 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5888 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5889 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5890 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5891 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5892 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5893 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5894 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5895 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5896 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5897 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5898 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5899 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5900 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5901 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5902 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5903 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5904 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5905 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5906 +
5907 +/* Secondary interrupts */
5908 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5909 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5910 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5911 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5912 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5913 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5914 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5915 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5916 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5917 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5918 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5919 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5920 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5921 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5922 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5923 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5924 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5925 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5926 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5927 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5928 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5929 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5930 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5931 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5932 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5933 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5934 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5935 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5936 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5937 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5938 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5939 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5940 +
5941 +/* These ugly macros are to access the -1 registers, like config1 */
5942 +#define MFC0_SEL1_OPCODE(dst, src)\
5943 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5944 + nop; \
5945 + nop; \
5946 + nop
5947 +
5948 +#define MTC0_SEL1_OPCODE(dst, src)\
5949 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5950 + nop; \
5951 + nop; \
5952 + nop
5953 +
5954 +
5955 +/* Below are Jade core specific */
5956 +#define CFG0_4K_IL_MASK 0x00380000
5957 +#define CFG0_4K_IL_SHIFT 19
5958 +#define CFG0_4K_IA_MASK 0x00070000
5959 +#define CFG0_4K_IA_SHIFT 16
5960 +#define CFG0_4K_IS_MASK 0x01c00000
5961 +#define CFG0_4K_IS_SHIFT 22
5962 +
5963 +#define CFG0_4K_DL_MASK 0x00001c00
5964 +#define CFG0_4K_DL_SHIFT 10
5965 +#define CFG0_4K_DA_MASK 0x00000380
5966 +#define CFG0_4K_DA_SHIFT 7
5967 +#define CFG0_4K_DS_MASK 0x0000E000
5968 +#define CFG0_4K_DS_SHIFT 13
5969 +
5970 +
5971 +
5972 +#endif /* __TNETD73XX_H_ */
5973 diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h
5974 --- kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5975 +++ kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-10 09:53:49.418344272 +0200
5976 @@ -0,0 +1,239 @@
5977 +/******************************************************************************
5978 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5979 + ******************************************************************************
5980 + * FILE NAME: tnetd73xx_misc.h
5981 + *
5982 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5983 + * FSER Modules API
5984 + * As per TNETD73xx specifications
5985 + *
5986 + * REVISION HISTORY:
5987 + * 27 Nov 02 - Sharath Kumar PSP TII
5988 + * 14 Feb 03 - Anant Gole PSP TII
5989 + *
5990 + * (C) Copyright 2002, Texas Instruments, Inc
5991 + *******************************************************************************/
5992 +
5993 +#ifndef __TNETD73XX_MISC_H__
5994 +#define __TNETD73XX_MISC_H__
5995 +
5996 +/*****************************************************************************
5997 + * Reset Control Module
5998 + *****************************************************************************/
5999 +
6000 +typedef enum TNETD73XX_RESET_MODULE_tag
6001 +{
6002 + RESET_MODULE_UART0 = 0,
6003 + RESET_MODULE_UART1 = 1,
6004 + RESET_MODULE_I2C = 2,
6005 + RESET_MODULE_TIMER0 = 3,
6006 + RESET_MODULE_TIMER1 = 4,
6007 + RESET_MODULE_GPIO = 6,
6008 + RESET_MODULE_ADSLSS = 7,
6009 + RESET_MODULE_USBS = 8,
6010 + RESET_MODULE_SAR = 9,
6011 + RESET_MODULE_VDMA_VT = 11,
6012 + RESET_MODULE_FSER = 12,
6013 + RESET_MODULE_VLYNQ1 = 16,
6014 + RESET_MODULE_EMAC0 = 17,
6015 + RESET_MODULE_DMA = 18,
6016 + RESET_MODULE_BIST = 19,
6017 + RESET_MODULE_VLYNQ0 = 20,
6018 + RESET_MODULE_EMAC1 = 21,
6019 + RESET_MODULE_MDIO = 22,
6020 + RESET_MODULE_ADSLSS_DSP = 23,
6021 + RESET_MODULE_EPHY = 26
6022 +} TNETD73XX_RESET_MODULE_T;
6023 +
6024 +typedef enum TNETD73XX_RESET_CTRL_tag
6025 +{
6026 + IN_RESET = 0,
6027 + OUT_OF_RESET
6028 +} TNETD73XX_RESET_CTRL_T;
6029 +
6030 +typedef enum TNETD73XX_SYS_RST_MODE_tag
6031 +{
6032 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
6033 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
6034 +} TNETD73XX_SYS_RST_MODE_T;
6035 +
6036 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
6037 +{
6038 + HARDWARE_RESET = 0,
6039 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
6040 + WATCHDOG_RESET,
6041 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
6042 +} TNETD73XX_SYS_RESET_STATUS_T;
6043 +
6044 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
6045 + TNETD73XX_RESET_CTRL_T reset_ctrl);
6046 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
6047 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
6048 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
6049 +
6050 +/*****************************************************************************
6051 + * Power Control Module
6052 + *****************************************************************************/
6053 +
6054 +typedef enum TNETD73XX_POWER_MODULE_tag
6055 +{
6056 + POWER_MODULE_USBSP = 0,
6057 + POWER_MODULE_WDTP = 1,
6058 + POWER_MODULE_UT0P = 2,
6059 + POWER_MODULE_UT1P = 3,
6060 + POWER_MODULE_IICP = 4,
6061 + POWER_MODULE_VDMAP = 5,
6062 + POWER_MODULE_GPIOP = 6,
6063 + POWER_MODULE_VLYNQ1P = 7,
6064 + POWER_MODULE_SARP = 8,
6065 + POWER_MODULE_ADSLP = 9,
6066 + POWER_MODULE_EMIFP = 10,
6067 + POWER_MODULE_ADSPP = 12,
6068 + POWER_MODULE_RAMP = 13,
6069 + POWER_MODULE_ROMP = 14,
6070 + POWER_MODULE_DMAP = 15,
6071 + POWER_MODULE_BISTP = 16,
6072 + POWER_MODULE_TIMER0P = 18,
6073 + POWER_MODULE_TIMER1P = 19,
6074 + POWER_MODULE_EMAC0P = 20,
6075 + POWER_MODULE_EMAC1P = 22,
6076 + POWER_MODULE_EPHYP = 24,
6077 + POWER_MODULE_VLYNQ0P = 27,
6078 +} TNETD73XX_POWER_MODULE_T;
6079 +
6080 +typedef enum TNETD73XX_POWER_CTRL_tag
6081 +{
6082 + POWER_CTRL_POWER_UP = 0,
6083 + POWER_CTRL_POWER_DOWN
6084 +} TNETD73XX_POWER_CTRL_T;
6085 +
6086 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
6087 +{
6088 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
6089 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
6090 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
6091 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
6092 +} TNETD73XX_SYS_POWER_MODE_T;
6093 +
6094 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
6095 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
6096 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
6097 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
6098 +
6099 +/*****************************************************************************
6100 + * Wakeup Control
6101 + *****************************************************************************/
6102 +
6103 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
6104 +{
6105 + WAKEUP_INT0 = 1,
6106 + WAKEUP_INT1 = 2,
6107 + WAKEUP_INT2 = 4,
6108 + WAKEUP_INT3 = 8
6109 +} TNETD73XX_WAKEUP_INTERRUPT_T;
6110 +
6111 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
6112 +{
6113 + WAKEUP_DISABLED = 0,
6114 + WAKEUP_ENABLED
6115 +} TNETD73XX_WAKEUP_CTRL_T;
6116 +
6117 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
6118 +{
6119 + WAKEUP_ACTIVE_HIGH = 0,
6120 + WAKEUP_ACTIVE_LOW
6121 +} TNETD73XX_WAKEUP_POLARITY_T;
6122 +
6123 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
6124 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
6125 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
6126 +
6127 +/*****************************************************************************
6128 + * FSER Control
6129 + *****************************************************************************/
6130 +
6131 +typedef enum TNETD73XX_FSER_MODE_tag
6132 +{
6133 + FSER_I2C = 0,
6134 + FSER_UART = 1
6135 +} TNETD73XX_FSER_MODE_T;
6136 +
6137 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
6138 +
6139 +/*****************************************************************************
6140 + * Clock Control
6141 + *****************************************************************************/
6142 +
6143 +#define CLK_MHZ(x) ( (x) * 1000000 )
6144 +
6145 +typedef enum TNETD73XX_CLKC_ID_tag
6146 +{
6147 + CLKC_SYS = 0,
6148 + CLKC_MIPS,
6149 + CLKC_USB,
6150 + CLKC_ADSLSS
6151 +} TNETD73XX_CLKC_ID_T;
6152 +
6153 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
6154 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
6155 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
6156 +
6157 +/*****************************************************************************
6158 + * GPIO Control
6159 + *****************************************************************************/
6160 +
6161 +typedef enum TNETD73XX_GPIO_PIN_tag
6162 +{
6163 + GPIO_UART0_RD = 0,
6164 + GPIO_UART0_TD = 1,
6165 + GPIO_UART0_RTS = 2,
6166 + GPIO_UART0_CTS = 3,
6167 + GPIO_FSER_CLK = 4,
6168 + GPIO_FSER_D = 5,
6169 + GPIO_EXT_AFE_SCLK = 6,
6170 + GPIO_EXT_AFE_TX_FS = 7,
6171 + GPIO_EXT_AFE_TXD = 8,
6172 + GPIO_EXT_AFE_RS_FS = 9,
6173 + GPIO_EXT_AFE_RXD1 = 10,
6174 + GPIO_EXT_AFE_RXD0 = 11,
6175 + GPIO_EXT_AFE_CDIN = 12,
6176 + GPIO_EXT_AFE_CDOUT = 13,
6177 + GPIO_EPHY_SPEED100 = 14,
6178 + GPIO_EPHY_LINKON = 15,
6179 + GPIO_EPHY_ACTIVITY = 16,
6180 + GPIO_EPHY_FDUPLEX = 17,
6181 + GPIO_EINT0 = 18,
6182 + GPIO_EINT1 = 19,
6183 + GPIO_MBSP0_TCLK = 20,
6184 + GPIO_MBSP0_RCLK = 21,
6185 + GPIO_MBSP0_RD = 22,
6186 + GPIO_MBSP0_TD = 23,
6187 + GPIO_MBSP0_RFS = 24,
6188 + GPIO_MBSP0_TFS = 25,
6189 + GPIO_MII_DIO = 26,
6190 + GPIO_MII_DCLK = 27,
6191 +} TNETD73XX_GPIO_PIN_T;
6192 +
6193 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
6194 +{
6195 + FUNCTIONAL_PIN = 0,
6196 + GPIO_PIN = 1
6197 +} TNETD73XX_GPIO_PIN_MODE_T;
6198 +
6199 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
6200 +{
6201 + GPIO_OUTPUT_PIN = 0,
6202 + GPIO_INPUT_PIN = 1
6203 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
6204 +
6205 +void tnetd73xx_gpio_init(void);
6206 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
6207 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
6208 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
6209 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
6210 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
6211 +
6212 +/* TNETD73XX Revision */
6213 +__u32 tnetd73xx_get_revision(void);
6214 +
6215 +#endif /* __TNETD73XX_MISC_H__ */
6216 diff -urN kernel-base/include/asm-mips/io.h kernel-current/include/asm-mips/io.h
6217 --- kernel-base/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200
6218 +++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260784 +0200
6219 @@ -63,8 +63,12 @@
6220 #ifdef CONFIG_64BIT_PHYS_ADDR
6221 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
6222 #else
6223 +#ifdef CONFIG_AR7_PAGING
6224 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
6225 +#else
6226 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
6227 #endif
6228 +#endif
6229
6230 #define IO_SPACE_LIMIT 0xffff
6231
6232 diff -urN kernel-base/include/asm-mips/irq.h kernel-current/include/asm-mips/irq.h
6233 --- kernel-base/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200
6234 +++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260784 +0200
6235 @@ -14,7 +14,12 @@
6236 #include <linux/config.h>
6237 #include <linux/linkage.h>
6238
6239 +#ifdef CONFIG_AR7
6240 +#include <asm/ar7/avalanche_intc.h>
6241 +#define NR_IRQS AVALANCHE_INT_END + 1
6242 +#else
6243 #define NR_IRQS 128 /* Largest number of ints of all machines. */
6244 +#endif
6245
6246 #ifdef CONFIG_I8259
6247 static inline int irq_cannonicalize(int irq)
6248 diff -urN kernel-base/include/asm-mips/page.h kernel-current/include/asm-mips/page.h
6249 --- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
6250 +++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260632 +0200
6251 @@ -129,7 +129,11 @@
6252
6253 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
6254 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
6255 +#ifdef CONFIG_AR7_PAGING
6256 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
6257 +#else
6258 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
6259 +#endif
6260 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
6261
6262 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
6263 diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-current/include/asm-mips/pgtable-32.h
6264 --- kernel-base/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200
6265 +++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260632 +0200
6266 @@ -108,7 +108,18 @@
6267 * and a page entry and page directory to the page they refer to.
6268 */
6269
6270 -#ifdef CONFIG_CPU_VR41XX
6271 +#if defined(CONFIG_AR7_PAGING)
6272 +#define mk_pte(page, pgprot) \
6273 +({ \
6274 + pte_t __pte; \
6275 + \
6276 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
6277 + CONFIG_AR7_MEMORY) | \
6278 + pgprot_val(pgprot); \
6279 + \
6280 + __pte; \
6281 +})
6282 +#elif defined(CONFIG_CPU_VR41XX)
6283 #define mk_pte(page, pgprot) \
6284 ({ \
6285 pte_t __pte; \
6286 @@ -130,6 +141,7 @@
6287 })
6288 #endif
6289
6290 +
6291 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
6292 {
6293 #ifdef CONFIG_CPU_VR41XX
6294 @@ -175,7 +187,10 @@
6295 set_pte(ptep, __pte(0));
6296 }
6297
6298 -#ifdef CONFIG_CPU_VR41XX
6299 +#if defined(CONFIG_AR7_PAGING)
6300 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
6301 +#define pte_page(x) phys_to_page(pte_val(x))
6302 +#elif defined(CONFIG_CPU_VR41XX)
6303 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
6304 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
6305 #else
6306 diff -urN kernel-base/include/asm-mips/serial.h kernel-current/include/asm-mips/serial.h
6307 --- kernel-base/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200
6308 +++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260632 +0200
6309 @@ -65,6 +65,15 @@
6310
6311 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
6312
6313 +#ifdef CONFIG_AR7
6314 +#include <asm/ar7/ar7.h>
6315 +#define AR7_SERIAL_PORT_DEFNS \
6316 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
6317 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
6318 +#else
6319 +#define AR7_SERIAL_PORT_DEFNS
6320 +#endif
6321 +
6322 #ifdef CONFIG_MIPS_JAZZ
6323 #define _JAZZ_SERIAL_INIT(int, base) \
6324 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
6325 @@ -468,6 +477,7 @@
6326 #endif
6327
6328 #define SERIAL_PORT_DFNS \
6329 + AR7_SERIAL_PORT_DEFNS \
6330 ATLAS_SERIAL_PORT_DEFNS \
6331 AU1000_SERIAL_PORT_DEFNS \
6332 COBALT_SERIAL_PORT_DEFNS \
6333 diff -urN kernel-base/Makefile kernel-current/Makefile
6334 --- kernel-base/Makefile 2005-07-10 03:00:44.799179096 +0200
6335 +++ kernel-current/Makefile 2005-07-10 06:40:39.626260480 +0200
6336 @@ -91,7 +91,7 @@
6337
6338 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
6339
6340 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
6341 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
6342 -fno-strict-aliasing -fno-common
6343 ifndef CONFIG_FRAME_POINTER
6344 CFLAGS += -fomit-frame-pointer
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