target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19
  20 #include <asm/mach-ar71xx/ar71xx.h>
  21 #include <asm/mach-ar71xx/pci.h>
  22
  23 #undef DEBUG
  24 #ifdef DEBUG
  25 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  26 #else
  27 #define DBG(fmt, args...)
  28 #endif
  29
  30 static void __iomem *ar724x_pci_localcfg_base;
  31 static void __iomem *ar724x_pci_devcfg_base;
  32
  33 static DEFINE_SPINLOCK(ar724x_pci_lock);
  34
  35 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  36 {
  37         unsigned long flags;
  38         u32 data;
  39
  40         spin_lock_irqsave(&ar724x_pci_lock, flags);
  41         data = __raw_readl(base + (where & ~3));
  42
  43         switch (size) {
  44         case 1:
  45                 if (where & 1)
  46                         data >>= 8;
  47                 if (where & 2)
  48                         data >>= 16;
  49                 data &= 0xFF;
  50                 break;
  51         case 2:
  52                 if (where & 2)
  53                         data >>= 16;
  54                 data &= 0xFFFF;
  55                 break;
  56         }
  57
  58         *value = data;
  59         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  60 }
  61
  62 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  63 {
  64         unsigned long flags;
  65         u32 data;
  66         int s;
  67
  68         spin_lock_irqsave(&ar724x_pci_lock, flags);
  69         data = __raw_readl(base + (where & ~3));
  70
  71         switch (size) {
  72         case 1:
  73                 s = ((where & 3) << 3);
  74                 data &= ~(0xFF << s);
  75                 data |= ((value & 0xFF) << s);
  76                 break;
  77         case 2:
  78                 s = ((where & 2) << 3);
  79                 data &= ~(0xFFFF << s);
  80                 data |= ((value & 0xFFFF) << s);
  81                 break;
  82         case 4:
  83                 data = value;
  84                 break;
  85         }
  86
  87         __raw_writel(data, base + (where & ~3));
  88         /* flush write */
  89         (void)__raw_readl(base + (where & ~3));
  90         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  91 }
  92
  93 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  94                                   int where, int size, u32 *value)
  95 {
  96
  97         if (bus->number != 0 || devfn != 0)
  98                 return PCIBIOS_DEVICE_NOT_FOUND;
  99
 100         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 101
 102         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 103                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 104                         where, size, *value);
 105
 106         /*
 107          * WAR for BAR issue - We are unable to access the PCI device space
 108          * if we set the BAR with proper base address
 109          */
 110         if ((where == 0x10) && (size == 4))
 111                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 112
 113         return PCIBIOS_SUCCESSFUL;
 114 }
 115
 116 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 117                                    int where, int size, u32 value)
 118 {
 119         if (bus->number != 0 || devfn != 0)
 120                 return PCIBIOS_DEVICE_NOT_FOUND;
 121
 122         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 123                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 124                 where, size, value);
 125
 126         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 127
 128         return PCIBIOS_SUCCESSFUL;
 129 }
 130
 131 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 132                                   uint8_t pin)
 133 {
 134         int irq = -1;
 135         int i;
 136
 137         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 138                 struct ar71xx_pci_irq *entry;
 139                 entry = &ar71xx_pci_irq_map[i];
 140
 141                 if (entry->slot == slot && entry->pin == pin) {
 142                         irq = entry->irq;
 143                         break;
 144                 }
 145         }
 146
 147         if (irq < 0)
 148                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 149                                 pin, pci_name((struct pci_dev *)dev));
 150         else
 151                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 152                                 irq, pin, pci_name((struct pci_dev *)dev));
 153
 154         return irq;
 155 }
 156
 157 static struct pci_ops ar724x_pci_ops = {
 158         .read   = ar724x_pci_read_config,
 159         .write  = ar724x_pci_write_config,
 160 };
 161
 162 static struct resource ar724x_pci_io_resource = {
 163         .name           = "PCI IO space",
 164         .start          = 0,
 165         .end            = 0,
 166         .flags          = IORESOURCE_IO,
 167 };
 168
 169 static struct resource ar724x_pci_mem_resource = {
 170         .name           = "PCI memory space",
 171         .start          = AR71XX_PCI_MEM_BASE,
 172         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 173         .flags          = IORESOURCE_MEM
 174 };
 175
 176 static struct pci_controller ar724x_pci_controller = {
 177         .pci_ops        = &ar724x_pci_ops,
 178         .mem_resource   = &ar724x_pci_mem_resource,
 179         .io_resource    = &ar724x_pci_io_resource,
 180 };
 181
 182 int __init ar724x_pcibios_init(void)
 183 {
 184         u32 t;
 185
 186         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 187                                                    AR724X_PCI_CRP_SIZE);
 188
 189         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 190                                                  AR724X_PCI_CFG_SIZE);
 191
 192         /* setup COMMAND register */
 193         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 194             PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 195
 196         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 197
 198         register_pci_controller(&ar724x_pci_controller);
 199
 200         return 0;
 201 }