use kernel abs(), remove recursion in gcd() (closes: #2307)
[openwrt.git] / target / linux / ar7-2.6 / files / arch / mips / ar7 / clock.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/init.h>
22 #include <linux/types.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <asm/addrspace.h>
26 #include <asm/io.h>
27 #include <asm/ar7/ar7.h>
28
29 #define BOOT_PLL_SOURCE_MASK 0x3
30 #define CPU_PLL_SOURCE_SHIFT 16
31 #define BUS_PLL_SOURCE_SHIFT 14
32 #define USB_PLL_SOURCE_SHIFT 18
33 #define DSP_PLL_SOURCE_SHIFT 22
34 #define BOOT_PLL_SOURCE_AFE 0
35 #define BOOT_PLL_SOURCE_BUS 0
36 #define BOOT_PLL_SOURCE_REF 1
37 #define BOOT_PLL_SOURCE_XTAL 2
38 #define BOOT_PLL_SOURCE_CPU 3
39 #define BOOT_PLL_BYPASS 0x00000020
40 #define BOOT_PLL_ASYNC_MODE 0x02000000
41 #define BOOT_PLL_2TO1_MODE 0x00008000
42
43 #define TNETD7200_CLOCK_ID_CPU 0
44 #define TNETD7200_CLOCK_ID_DSP 1
45 #define TNETD7200_CLOCK_ID_USB 2
46
47 #define TNETD7200_DEF_CPU_CLK 211000000
48 #define TNETD7200_DEF_DSP_CLK 125000000
49 #define TNETD7200_DEF_USB_CLK 48000000
50
51 struct tnetd7300_clock {
52 volatile u32 ctrl;
53 #define PREDIV_MASK 0x001f0000
54 #define PREDIV_SHIFT 16
55 #define POSTDIV_MASK 0x0000001f
56 u32 unused1[3];
57 volatile u32 pll;
58 #define MUL_MASK 0x0000f000
59 #define MUL_SHIFT 12
60 #define PLL_MODE_MASK 0x00000001
61 #define PLL_NDIV 0x00000800
62 #define PLL_DIV 0x00000002
63 #define PLL_STATUS 0x00000001
64 u32 unused2[3];
65 } __attribute__ ((packed));
66
67 struct tnetd7300_clocks {
68 struct tnetd7300_clock bus;
69 struct tnetd7300_clock cpu;
70 struct tnetd7300_clock usb;
71 struct tnetd7300_clock dsp;
72 } __attribute__ ((packed));
73
74 struct tnetd7200_clock {
75 volatile u32 ctrl;
76 u32 unused1[3];
77 #define DIVISOR_ENABLE_MASK 0x00008000
78 volatile u32 mul;
79 volatile u32 prediv;
80 volatile u32 postdiv;
81 volatile u32 postdiv2;
82 u32 unused2[6];
83 volatile u32 cmd;
84 volatile u32 status;
85 volatile u32 cmden;
86 u32 padding[15];
87 } __attribute__ ((packed));
88
89 struct tnetd7200_clocks {
90 struct tnetd7200_clock cpu;
91 struct tnetd7200_clock dsp;
92 struct tnetd7200_clock usb;
93 } __attribute__ ((packed));
94
95 int ar7_cpu_clock = 150000000;
96 EXPORT_SYMBOL(ar7_cpu_clock);
97 int ar7_bus_clock = 125000000;
98 EXPORT_SYMBOL(ar7_bus_clock);
99 int ar7_dsp_clock = 0;
100 EXPORT_SYMBOL(ar7_dsp_clock);
101
102 static int gcd(int a, int b)
103 {
104 int c;
105
106 if ( a < b) {
107 c = a;
108 a = b;
109 b = c;
110 }
111 while (c = (a % b)) {
112 a = b;
113 b = c;
114 }
115 return b;
116 }
117
118 static void approximate(int base, int target, int *prediv,
119 int *postdiv, int *mul)
120 {
121 int i, j, k, freq, res = target;
122 for (i = 1; i <= 16; i++) {
123 for (j = 1; j <= 32; j++) {
124 for (k = 1; k <= 32; k++) {
125 freq = abs(base / j * i / k - target);
126 if (freq < res) {
127 res = freq;
128 *mul = i;
129 *prediv = j;
130 *postdiv = k;
131 }
132 }
133 }
134 }
135 }
136
137 static void calculate(int base, int target, int *prediv, int *postdiv,
138 int *mul)
139 {
140 int tmp_gcd, tmp_base, tmp_freq;
141
142 for (*prediv = 1; *prediv <= 32; (*prediv)++) {
143 tmp_base = base / *prediv;
144 tmp_gcd = gcd(target, tmp_base);
145 *mul = target / tmp_gcd;
146 *postdiv = tmp_base / tmp_gcd;
147 if ((*mul < 1) || (*mul >= 16))
148 continue;
149 if ((*postdiv > 0) & (*postdiv <= 32))
150 break;
151 }
152
153 if (base / (*prediv) * (*mul) / (*postdiv) != target) {
154 approximate(base, target, prediv, postdiv, mul);
155 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
156 printk(KERN_WARNING
157 "Adjusted requested frequency %d to %d\n",
158 target, tmp_freq);
159 }
160
161 printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
162 *prediv, *postdiv, *mul);
163 }
164
165 static int tnetd7300_dsp_clock(void)
166 {
167 u32 didr1, didr2;
168 u8 rev = ar7_chip_rev();
169 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
170 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
171 if (didr2 & (1 << 23))
172 return 0;
173 if ((rev >= 0x23) && (rev != 0x57))
174 return 250000000;
175 if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
176 > 4208000)
177 return 250000000;
178 return 0;
179 }
180
181 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
182 u32 *bootcr, u32 bus_clock)
183 {
184 int product;
185 int base_clock = AR7_REF_CLOCK;
186 u32 ctrl = clock->ctrl;
187 u32 pll = clock->pll;
188 int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
189 int postdiv = (ctrl & POSTDIV_MASK) + 1;
190 int divisor = prediv * postdiv;
191 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
192
193 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
194 case BOOT_PLL_SOURCE_BUS:
195 base_clock = bus_clock;
196 break;
197 case BOOT_PLL_SOURCE_REF:
198 base_clock = AR7_REF_CLOCK;
199 break;
200 case BOOT_PLL_SOURCE_XTAL:
201 base_clock = AR7_XTAL_CLOCK;
202 break;
203 case BOOT_PLL_SOURCE_CPU:
204 base_clock = ar7_cpu_clock;
205 break;
206 }
207
208 if (*bootcr & BOOT_PLL_BYPASS)
209 return base_clock / divisor;
210
211 if ((pll & PLL_MODE_MASK) == 0)
212 return (base_clock >> (mul / 16 + 1)) / divisor;
213
214 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
215 product = (mul & 1) ?
216 (base_clock * mul) >> 1 :
217 (base_clock * (mul - 1)) >> 2;
218 return product / divisor;
219 }
220
221 if (mul == 16)
222 return base_clock / divisor;
223
224 return base_clock * mul / divisor;
225 }
226
227 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
228 u32 *bootcr, u32 frequency)
229 {
230 u32 status;
231 int prediv, postdiv, mul;
232 int base_clock = ar7_bus_clock;
233
234 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
235 case BOOT_PLL_SOURCE_BUS:
236 base_clock = ar7_bus_clock;
237 break;
238 case BOOT_PLL_SOURCE_REF:
239 base_clock = AR7_REF_CLOCK;
240 break;
241 case BOOT_PLL_SOURCE_XTAL:
242 base_clock = AR7_XTAL_CLOCK;
243 break;
244 case BOOT_PLL_SOURCE_CPU:
245 base_clock = ar7_cpu_clock;
246 break;
247 }
248
249 calculate(base_clock, frequency, &prediv, &postdiv, &mul);
250
251 clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
252 mdelay(1);
253 clock->pll = 4;
254 do {
255 status = clock->pll;
256 } while (status & PLL_STATUS);
257 clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
258 mdelay(75);
259 }
260
261 static void __init tnetd7300_init_clocks(void)
262 {
263 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
264 struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
265
266 ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
267 &clocks->bus, bootcr, AR7_AFE_CLOCK);
268
269 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
270 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
271 &clocks->cpu, bootcr, AR7_AFE_CLOCK);
272 } else {
273 ar7_cpu_clock = ar7_bus_clock;
274 }
275
276 tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
277 bootcr, 48000000);
278
279 if (ar7_dsp_clock == 250000000)
280 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
281 bootcr, ar7_dsp_clock);
282
283 iounmap(clocks);
284 iounmap(bootcr);
285 }
286
287 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
288 u32 *bootcr, u32 bus_clock)
289 {
290 int divisor = ((clock->prediv & 0x1f) + 1) *
291 ((clock->postdiv & 0x1f) + 1);
292
293 if (*bootcr & BOOT_PLL_BYPASS)
294 return base / divisor;
295
296 return base * ((clock->mul & 0xf) + 1) / divisor;
297 }
298
299
300 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
301 int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
302 {
303 printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n",
304 base, frequency, prediv, postdiv, postdiv2, mul);
305
306 clock->ctrl = 0;
307 clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
308 clock->mul = ((mul - 1) & 0xF);
309
310 for(mul = 0; mul < 2000; mul++) /* nop */;
311
312 while(clock->status & 0x1) /* nop */;
313
314 clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
315
316 clock->cmden |= 1;
317 clock->cmd |= 1;
318
319 while(clock->status & 0x1) /* nop */;
320
321 clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
322
323 clock->cmden |= 1;
324 clock->cmd |= 1;
325
326 while(clock->status & 0x1) /* nop */;
327
328 clock->ctrl |= 1;
329 }
330
331 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
332 {
333 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
334 // Async
335 switch (clock_id) {
336 case TNETD7200_CLOCK_ID_DSP:
337 return AR7_REF_CLOCK;
338 default:
339 return AR7_AFE_CLOCK;
340 }
341 } else {
342 // Sync
343 if (*bootcr & BOOT_PLL_2TO1_MODE) {
344 // 2:1
345 switch (clock_id) {
346 case TNETD7200_CLOCK_ID_DSP:
347 return AR7_REF_CLOCK;
348 default:
349 return AR7_AFE_CLOCK;
350 }
351 } else {
352 // 1:1
353 return AR7_REF_CLOCK;
354 }
355 }
356 }
357
358
359 static void __init tnetd7200_init_clocks(void)
360 {
361 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
362 struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
363 int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
364 int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
365 int usb_base, usb_mul, usb_prediv, usb_postdiv;
366
367 /*
368 Log from Fritz!Box 7170 Annex B:
369
370 CPU revision is: 00018448
371 Clocks: Async mode
372 Clocks: Setting DSP clock
373 Clocks: prediv: 1, postdiv: 1, mul: 5
374 Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
375 Clocks: Setting CPU clock
376 Adjusted requested frequency 211000000 to 211968000
377 Clocks: prediv: 1, postdiv: 1, mul: 6
378 Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
379 Clocks: Setting USB clock
380 Adjusted requested frequency 48000000 to 48076920
381 Clocks: prediv: 13, postdiv: 1, mul: 5
382 Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5
383
384 DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup.
385 Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock
386 */
387
388 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
389 dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
390
391 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
392 printk("Clocks: Async mode\n");
393
394 printk("Clocks: Setting DSP clock\n");
395 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
396 ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
397 tnetd7200_set_clock(dsp_base, &clocks->dsp,
398 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
399 ar7_bus_clock);
400
401 printk("Clocks: Setting CPU clock\n");
402 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
403 ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
404 tnetd7200_set_clock(cpu_base, &clocks->cpu,
405 cpu_prediv, cpu_postdiv, -1, cpu_mul,
406 ar7_cpu_clock);
407
408 } else {
409 if (*bootcr & BOOT_PLL_2TO1_MODE) {
410 printk("Clocks: Sync 2:1 mode\n");
411
412 printk("Clocks: Setting CPU clock\n");
413 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
414 ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
415 tnetd7200_set_clock(cpu_base, &clocks->cpu,
416 cpu_prediv, cpu_postdiv, -1, cpu_mul,
417 ar7_cpu_clock);
418
419 printk("Clocks: Setting DSP clock\n");
420 calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
421 ar7_bus_clock = ar7_cpu_clock / 2;
422 tnetd7200_set_clock(dsp_base, &clocks->dsp,
423 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
424 ar7_bus_clock);
425 } else {
426 printk("Clocks: Sync 1:1 mode\n");
427
428 printk("Clocks: Setting DSP clock\n");
429 calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
430 ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
431 tnetd7200_set_clock(dsp_base, &clocks->dsp,
432 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
433 ar7_bus_clock);
434
435 ar7_cpu_clock = ar7_bus_clock;
436 }
437 }
438
439 printk("Clocks: Setting USB clock\n");
440 usb_base = ar7_bus_clock;
441 calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul);
442 tnetd7200_set_clock(usb_base, &clocks->usb,
443 usb_prediv, usb_postdiv, -1, usb_mul,
444 TNETD7200_DEF_USB_CLK);
445
446 #warning FIXME: ????! Hrmm
447 ar7_dsp_clock = ar7_cpu_clock;
448
449 iounmap(clocks);
450 iounmap(bootcr);
451 }
452
453 void __init ar7_init_clocks(void)
454 {
455 switch (ar7_chip_id()) {
456 case AR7_CHIP_7100:
457 #warning FIXME: Check if the new 7200 clock init works for 7100
458 tnetd7200_init_clocks();
459 break;
460 case AR7_CHIP_7200:
461 tnetd7200_init_clocks();
462 break;
463 case AR7_CHIP_7300:
464 ar7_dsp_clock = tnetd7300_dsp_clock();
465 tnetd7300_init_clocks();
466 break;
467 default:
468 break;
469 }
470 }
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