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add minor code cleanup and a core reset for internal sb devices that need it
[openwrt.git] / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2005-12-15 13:26:49.758027500 +0100
3 +++ linux.dev/arch/mips/Kconfig 2005-12-15 12:57:27.889182500 +0100
4 @@ -244,6 +244,17 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SYS_SUPPORTS_LITTLE_ENDIAN
16 + help
17 + Support for BCM947xx based boards
18 +
19 config LASAT
20 bool "Support for LASAT Networks platforms"
21 select DMA_NONCOHERENT
22 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
23 --- linux.old/arch/mips/Makefile 2005-12-15 13:26:49.766024000 +0100
24 +++ linux.dev/arch/mips/Makefile 2005-12-15 12:57:27.921168500 +0100
25 @@ -689,6 +689,13 @@
26 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
27
28 #
29 +# Broadcom BCM47XX boards
30 +#
31 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
32 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
33 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
34 +
35 +#
36 # SNI RM200 PCI
37 #
38 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
39 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
40 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-12-15 14:32:03.580639500 +0100
42 @@ -0,0 +1,6 @@
43 +#
44 +# Makefile for the BCM47xx specific kernel interface routines
45 +# under Linux.
46 +#
47 +
48 +obj-y := irq.o int-handler.o prom.o setup.o time.o pci.o
49 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
50 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2005-12-17 20:51:17.749271000 +0100
52 @@ -0,0 +1,6 @@
53 +#
54 +# Makefile for the BCM47xx specific kernel interface routines
55 +# under Linux.
56 +#
57 +
58 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
59 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
60 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
61 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-12-17 01:21:23.007883000 +0100
62 @@ -0,0 +1,481 @@
63 +/*
64 + * Misc useful routines to access NIC SROM/OTP .
65 + *
66 + * Copyright 2005, Broadcom Corporation
67 + * All Rights Reserved.
68 + *
69 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
70 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
71 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
72 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
73 + * $Id$
74 + */
75 +
76 +#include <typedefs.h>
77 +#include <osl.h>
78 +#include <bcmutils.h>
79 +#include <bcmsrom.h>
80 +#include <bcmdevs.h>
81 +#include <bcmendian.h>
82 +#include <pcicfg.h>
83 +#include <sbutils.h>
84 +
85 +#include <proto/ethernet.h> /* for sprom content groking */
86 +
87 +#define VARS_MAX 4096 /* should be reduced */
88 +
89 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
90 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
91 +
92 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
93 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
94 +
95 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
96 +
97 +/*
98 + * Initialize local vars from the right source for this platform.
99 + * Return 0 on success, nonzero on error.
100 + */
101 +int
102 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
103 +{
104 + ASSERT(bustype == BUSTYPE(bustype));
105 + if (vars == NULL || count == NULL)
106 + return (0);
107 +
108 + switch (BUSTYPE(bustype)) {
109 +
110 + case PCI_BUS:
111 + ASSERT(curmap); /* can not be NULL */
112 + return initvars_srom_pci(sbh, curmap, vars, count);
113 +
114 + default:
115 + return 0;
116 + }
117 + return (-1);
118 +}
119 +
120 +/* support only 16-bit word read from srom */
121 +int
122 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
123 +{
124 + void *srom;
125 + uint off, nw;
126 +
127 + ASSERT(bustype == BUSTYPE(bustype));
128 +
129 + /* check input - 16-bit access only */
130 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
131 + return 1;
132 +
133 + off = byteoff / 2;
134 + nw = nbytes / 2;
135 +
136 + if (BUSTYPE(bustype) == PCI_BUS) {
137 + if (!curmap)
138 + return 1;
139 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
140 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
141 + return 1;
142 + } else {
143 + return 1;
144 + }
145 +
146 + return 0;
147 +}
148 +
149 +/* support only 16-bit word write into srom */
150 +int
151 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
152 +{
153 + uint16 *srom;
154 + uint i, off, nw, crc_range;
155 + uint16 image[SPROM_SIZE], *p;
156 + uint8 crc;
157 + volatile uint32 val32;
158 +
159 + ASSERT(bustype == BUSTYPE(bustype));
160 +
161 + /* check input - 16-bit access only */
162 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
163 + return 1;
164 +
165 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
166 +
167 + /* if changes made inside crc cover range */
168 + if (byteoff < crc_range) {
169 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
170 + /* read data including entire first 64 words from srom */
171 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
172 + return 1;
173 + /* make changes */
174 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
175 + /* calculate crc */
176 + htol16_buf(image, crc_range);
177 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
178 + ltoh16_buf(image, crc_range);
179 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
180 + p = image;
181 + off = 0;
182 + } else {
183 + p = buf;
184 + off = byteoff / 2;
185 + nw = nbytes / 2;
186 + }
187 +
188 + if (BUSTYPE(bustype) == PCI_BUS) {
189 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
190 + /* enable writes to the SPROM */
191 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
192 + val32 |= SPROM_WRITEEN;
193 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
194 + bcm_mdelay(WRITE_ENABLE_DELAY);
195 + /* write srom */
196 + for (i = 0; i < nw; i++) {
197 + W_REG(&srom[off + i], p[i]);
198 + bcm_mdelay(WRITE_WORD_DELAY);
199 + }
200 + /* disable writes to the SPROM */
201 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
202 + } else {
203 + return 1;
204 + }
205 +
206 + bcm_mdelay(WRITE_ENABLE_DELAY);
207 + return 0;
208 +}
209 +
210 +
211 +/*
212 + * Read in and validate sprom.
213 + * Return 0 on success, nonzero on error.
214 + */
215 +static int
216 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
217 +{
218 + int err = 0;
219 + uint i;
220 +
221 + /* read the sprom */
222 + for (i = 0; i < nwords; i++)
223 + buf[i] = R_REG(&sprom[wordoff + i]);
224 +
225 + if (check_crc) {
226 + /* fixup the endianness so crc8 will pass */
227 + htol16_buf(buf, nwords * 2);
228 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
229 + err = 1;
230 + /* now correct the endianness of the byte array */
231 + ltoh16_buf(buf, nwords * 2);
232 + }
233 +
234 + return err;
235 +}
236 +
237 +/*
238 +* Create variable table from memory.
239 +* Return 0 on success, nonzero on error.
240 +*/
241 +static int
242 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
243 +{
244 + int c = (int)(end - start);
245 +
246 + /* do it only when there is more than just the null string */
247 + if (c > 1) {
248 + char *vp = MALLOC(osh, c);
249 + ASSERT(vp);
250 + if (!vp)
251 + return BCME_NOMEM;
252 + bcopy(start, vp, c);
253 + *vars = vp;
254 + *count = c;
255 + }
256 + else {
257 + *vars = NULL;
258 + *count = 0;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +/*
265 + * Initialize nonvolatile variable table from sprom.
266 + * Return 0 on success, nonzero on error.
267 + */
268 +static int
269 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
270 +{
271 + uint16 w, b[64];
272 + uint8 sromrev;
273 + struct ether_addr ea;
274 + char eabuf[32];
275 + uint32 w32;
276 + int woff, i;
277 + char *vp, *base;
278 + osl_t *osh = sb_osh(sbh);
279 + int err;
280 +
281 + /*
282 + * Apply CRC over SROM content regardless SROM is present or not,
283 + * and use variable <devpath>sromrev's existance in flash to decide
284 + * if we should return an error when CRC fails or read SROM variables
285 + * from flash.
286 + */
287 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
288 +
289 + /* top word of sprom contains version and crc8 */
290 + sromrev = b[63] & 0xff;
291 + /* bcm4401 sroms misprogrammed */
292 + if (sromrev == 0x10)
293 + sromrev = 1;
294 +
295 + /* srom version check */
296 + if (sromrev > 3)
297 + return (-2);
298 +
299 + ASSERT(vars);
300 + ASSERT(count);
301 +
302 + base = vp = MALLOC(osh, VARS_MAX);
303 + ASSERT(vp);
304 + if (!vp)
305 + return -2;
306 +
307 + vp += sprintf(vp, "sromrev=%d", sromrev);
308 + vp++;
309 +
310 + if (sromrev >= 3) {
311 + /* New section takes over the 3th hardware function space */
312 +
313 + /* Words 22+23 are 11a (mid) ofdm power offsets */
314 + w32 = ((uint32)b[23] << 16) | b[22];
315 + vp += sprintf(vp, "ofdmapo=%d", w32);
316 + vp++;
317 +
318 + /* Words 24+25 are 11a (low) ofdm power offsets */
319 + w32 = ((uint32)b[25] << 16) | b[24];
320 + vp += sprintf(vp, "ofdmalpo=%d", w32);
321 + vp++;
322 +
323 + /* Words 26+27 are 11a (high) ofdm power offsets */
324 + w32 = ((uint32)b[27] << 16) | b[26];
325 + vp += sprintf(vp, "ofdmahpo=%d", w32);
326 + vp++;
327 +
328 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
329 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
330 + vp += sprintf(vp, "gpiotimerval=%d", w32);
331 +
332 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
333 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
334 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
335 + vp += sprintf(vp, "gpiotimerval=%d", w32);
336 +
337 + vp++;
338 + }
339 +
340 + if (sromrev >= 2) {
341 + /* New section takes over the 4th hardware function space */
342 +
343 + /* Word 29 is max power 11a high/low */
344 + w = b[29];
345 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
346 + vp++;
347 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
348 + vp++;
349 +
350 + /* Words 30-32 set the 11alow pa settings,
351 + * 33-35 are the 11ahigh ones.
352 + */
353 + for (i = 0; i < 3; i++) {
354 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
355 + vp++;
356 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
357 + vp++;
358 + }
359 + w = b[59];
360 + if (w == 0)
361 + vp += sprintf(vp, "ccode=");
362 + else
363 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
364 + vp++;
365 +
366 + }
367 +
368 + /* parameter section of sprom starts at byte offset 72 */
369 + woff = 72/2;
370 +
371 + /* first 6 bytes are il0macaddr */
372 + ea.octet[0] = (b[woff] >> 8) & 0xff;
373 + ea.octet[1] = b[woff] & 0xff;
374 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
375 + ea.octet[3] = b[woff+1] & 0xff;
376 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
377 + ea.octet[5] = b[woff+2] & 0xff;
378 + woff += ETHER_ADDR_LEN/2 ;
379 + bcm_ether_ntoa((uchar*)&ea, eabuf);
380 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
381 + vp++;
382 +
383 + /* next 6 bytes are et0macaddr */
384 + ea.octet[0] = (b[woff] >> 8) & 0xff;
385 + ea.octet[1] = b[woff] & 0xff;
386 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
387 + ea.octet[3] = b[woff+1] & 0xff;
388 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
389 + ea.octet[5] = b[woff+2] & 0xff;
390 + woff += ETHER_ADDR_LEN/2 ;
391 + bcm_ether_ntoa((uchar*)&ea, eabuf);
392 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
393 + vp++;
394 +
395 + /* next 6 bytes are et1macaddr */
396 + ea.octet[0] = (b[woff] >> 8) & 0xff;
397 + ea.octet[1] = b[woff] & 0xff;
398 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
399 + ea.octet[3] = b[woff+1] & 0xff;
400 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
401 + ea.octet[5] = b[woff+2] & 0xff;
402 + woff += ETHER_ADDR_LEN/2 ;
403 + bcm_ether_ntoa((uchar*)&ea, eabuf);
404 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
405 + vp++;
406 +
407 + /*
408 + * Enet phy settings one or two singles or a dual
409 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
410 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
411 + * Bit 14 : Mdio for enet0
412 + * Bit 15 : Mdio for enet1
413 + */
414 + w = b[woff];
415 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
416 + vp++;
417 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
418 + vp++;
419 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
420 + vp++;
421 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
422 + vp++;
423 +
424 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
425 + w = b[46];
426 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
427 + vp++;
428 +
429 + if (sromrev > 1)
430 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
431 + else
432 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
433 + vp++;
434 +
435 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
436 + vp++;
437 +
438 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
439 + vp++;
440 +
441 + /* Words 47-49 set the (wl) pa settings */
442 + woff = 47;
443 +
444 + for (i = 0; i < 3; i++) {
445 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
446 + vp++;
447 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
448 + vp++;
449 + }
450 +
451 + /*
452 + * Words 50-51 set the customer-configured wl led behavior.
453 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
454 + * LED behavior values defined in wlioctl.h .
455 + */
456 + w = b[50];
457 + if ((w != 0) && (w != 0xffff)) {
458 + /* gpio0 */
459 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
460 + vp++;
461 +
462 + /* gpio1 */
463 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
464 + vp++;
465 + }
466 + w = b[51];
467 + if ((w != 0) && (w != 0xffff)) {
468 + /* gpio2 */
469 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
470 + vp++;
471 +
472 + /* gpio3 */
473 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
474 + vp++;
475 + }
476 +
477 + /* Word 52 is max power 0/1 */
478 + w = b[52];
479 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
480 + vp++;
481 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
482 + vp++;
483 +
484 + /* Word 56 is idle tssi target 0/1 */
485 + w = b[56];
486 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
487 + vp++;
488 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
489 + vp++;
490 +
491 + /* Word 57 is boardflags, if not programmed make it zero */
492 + w32 = (uint32)b[57];
493 + if (w32 == 0xffff) w32 = 0;
494 + if (sromrev > 1) {
495 + /* Word 28 is the high bits of boardflags */
496 + w32 |= (uint32)b[28] << 16;
497 + }
498 + vp += sprintf(vp, "boardflags=%d", w32);
499 + vp++;
500 +
501 + /* Word 58 is antenna gain 0/1 */
502 + w = b[58];
503 + vp += sprintf(vp, "ag0=%d", w & 0xff);
504 + vp++;
505 +
506 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
507 + vp++;
508 +
509 + if (sromrev == 1) {
510 + /* set the oem string */
511 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
512 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
513 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
514 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
515 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
516 + vp++;
517 + } else if (sromrev == 2) {
518 + /* Word 60 OFDM tx power offset from CCK level */
519 + /* OFDM Power Offset - opo */
520 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
521 + vp++;
522 + } else {
523 + /* Word 60: cck power offsets */
524 + vp += sprintf(vp, "cckpo=%d", b[60]);
525 + vp++;
526 +
527 + /* Words 61+62: 11g ofdm power offsets */
528 + w32 = ((uint32)b[62] << 16) | b[61];
529 + vp += sprintf(vp, "ofdmgpo=%d", w32);
530 + vp++;
531 + }
532 +
533 + /* final nullbyte terminator */
534 + *vp++ = '\0';
535 +
536 + ASSERT((vp - base) <= VARS_MAX);
537 +
538 + err = initvars_table(osh, base, vp, vars, count);
539 +
540 + MFREE(osh, base, VARS_MAX);
541 + return err;
542 +}
543 +
544 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
545 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
546 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-12-17 17:53:52.387365000 +0100
547 @@ -0,0 +1,356 @@
548 +/*
549 + * Misc useful OS-independent routines.
550 + *
551 + * Copyright 2005, Broadcom Corporation
552 + * All Rights Reserved.
553 + *
554 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
555 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
556 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
557 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
558 + * $Id$
559 + */
560 +
561 +#include <typedefs.h>
562 +#include <osl.h>
563 +#include <sbutils.h>
564 +#include <bcmnvram.h>
565 +#include <bcmutils.h>
566 +#include <bcmendian.h>
567 +#include <bcmdevs.h>
568 +
569 +unsigned char bcm_ctype[] = {
570 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
571 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
572 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
573 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
574 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
575 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
576 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
577 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
578 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
579 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
580 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
581 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
582 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
583 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
584 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
585 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
586 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
587 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
588 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
589 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
590 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
591 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
592 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
593 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
594 +};
595 +
596 +uchar
597 +bcm_toupper(uchar c)
598 +{
599 + if (bcm_islower(c))
600 + c -= 'a'-'A';
601 + return (c);
602 +}
603 +
604 +ulong
605 +bcm_strtoul(char *cp, char **endp, uint base)
606 +{
607 + ulong result, value;
608 + bool minus;
609 +
610 + minus = FALSE;
611 +
612 + while (bcm_isspace(*cp))
613 + cp++;
614 +
615 + if (cp[0] == '+')
616 + cp++;
617 + else if (cp[0] == '-') {
618 + minus = TRUE;
619 + cp++;
620 + }
621 +
622 + if (base == 0) {
623 + if (cp[0] == '0') {
624 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
625 + base = 16;
626 + cp = &cp[2];
627 + } else {
628 + base = 8;
629 + cp = &cp[1];
630 + }
631 + } else
632 + base = 10;
633 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
634 + cp = &cp[2];
635 + }
636 +
637 + result = 0;
638 +
639 + while (bcm_isxdigit(*cp) &&
640 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
641 + result = result*base + value;
642 + cp++;
643 + }
644 +
645 + if (minus)
646 + result = (ulong)(result * -1);
647 +
648 + if (endp)
649 + *endp = (char *)cp;
650 +
651 + return (result);
652 +}
653 +
654 +uint
655 +bcm_atoi(char *s)
656 +{
657 + uint n;
658 +
659 + n = 0;
660 +
661 + while (bcm_isdigit(*s))
662 + n = (n * 10) + *s++ - '0';
663 + return (n);
664 +}
665 +
666 +/* return pointer to location of substring 'needle' in 'haystack' */
667 +char*
668 +bcmstrstr(char *haystack, char *needle)
669 +{
670 + int len, nlen;
671 + int i;
672 +
673 + if ((haystack == NULL) || (needle == NULL))
674 + return (haystack);
675 +
676 + nlen = strlen(needle);
677 + len = strlen(haystack) - nlen + 1;
678 +
679 + for (i = 0; i < len; i++)
680 + if (bcmp(needle, &haystack[i], nlen) == 0)
681 + return (&haystack[i]);
682 + return (NULL);
683 +}
684 +
685 +char*
686 +bcmstrcat(char *dest, const char *src)
687 +{
688 + strcpy(&dest[strlen(dest)], src);
689 + return (dest);
690 +}
691 +
692 +
693 +char*
694 +bcm_ether_ntoa(char *ea, char *buf)
695 +{
696 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
697 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
698 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
699 + return (buf);
700 +}
701 +
702 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
703 +int
704 +bcm_ether_atoe(char *p, char *ea)
705 +{
706 + int i = 0;
707 +
708 + for (;;) {
709 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
710 + if (!*p++ || i == 6)
711 + break;
712 + }
713 +
714 + return (i == 6);
715 +}
716 +
717 +void
718 +bcm_mdelay(uint ms)
719 +{
720 + uint i;
721 +
722 + for (i = 0; i < ms; i++) {
723 + OSL_DELAY(1000);
724 + }
725 +}
726 +
727 +/*
728 + * Search the name=value vars for a specific one and return its value.
729 + * Returns NULL if not found.
730 + */
731 +char*
732 +getvar(char *vars, char *name)
733 +{
734 + char *s;
735 + int len;
736 +
737 + len = strlen(name);
738 +
739 + /* first look in vars[] */
740 + for (s = vars; s && *s; ) {
741 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
742 + return (&s[len+1]);
743 +
744 + while (*s++)
745 + ;
746 + }
747 +
748 + /* then query nvram */
749 + return (BCMINIT(nvram_get)(name));
750 +}
751 +
752 +/*
753 + * Search the vars for a specific one and return its value as
754 + * an integer. Returns 0 if not found.
755 + */
756 +int
757 +getintvar(char *vars, char *name)
758 +{
759 + char *val;
760 +
761 + if ((val = getvar(vars, name)) == NULL)
762 + return (0);
763 +
764 + return (bcm_strtoul(val, NULL, 0));
765 +}
766 +
767 +
768 +/* Search for token in comma separated token-string */
769 +static int
770 +findmatch(char *string, char *name)
771 +{
772 + uint len;
773 + char *c;
774 +
775 + len = strlen(name);
776 + while ((c = strchr(string, ',')) != NULL) {
777 + if (len == (uint)(c - string) && !strncmp(string, name, len))
778 + return 1;
779 + string = c + 1;
780 + }
781 +
782 + return (!strcmp(string, name));
783 +}
784 +
785 +/* Return gpio pin number assigned to the named pin */
786 +/*
787 +* Variable should be in format:
788 +*
789 +* gpio<N>=pin_name,pin_name
790 +*
791 +* This format allows multiple features to share the gpio with mutual
792 +* understanding.
793 +*
794 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
795 +* and if def_pin is not used by others.
796 +*/
797 +uint
798 +getgpiopin(char *vars, char *pin_name, uint def_pin)
799 +{
800 + char name[] = "gpioXXXX";
801 + char *val;
802 + uint pin;
803 +
804 + /* Go thru all possibilities till a match in pin name */
805 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
806 + sprintf(name, "gpio%d", pin);
807 + val = getvar(vars, name);
808 + if (val && findmatch(val, pin_name))
809 + return pin;
810 + }
811 +
812 + if (def_pin != GPIO_PIN_NOTDEFINED) {
813 + /* make sure the default pin is not used by someone else */
814 + sprintf(name, "gpio%d", def_pin);
815 + if (getvar(vars, name)) {
816 + def_pin = GPIO_PIN_NOTDEFINED;
817 + }
818 + }
819 +
820 + return def_pin;
821 +}
822 +
823 +
824 +/*******************************************************************************
825 + * crc8
826 + *
827 + * Computes a crc8 over the input data using the polynomial:
828 + *
829 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
830 + *
831 + * The caller provides the initial value (either CRC8_INIT_VALUE
832 + * or the previous returned value) to allow for processing of
833 + * discontiguous blocks of data. When generating the CRC the
834 + * caller is responsible for complementing the final return value
835 + * and inserting it into the byte stream. When checking, a final
836 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
837 + *
838 + * Reference: Dallas Semiconductor Application Note 27
839 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
840 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
841 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
842 + *
843 + ******************************************************************************/
844 +
845 +static uint8 crc8_table[256] = {
846 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
847 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
848 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
849 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
850 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
851 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
852 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
853 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
854 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
855 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
856 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
857 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
858 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
859 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
860 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
861 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
862 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
863 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
864 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
865 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
866 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
867 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
868 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
869 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
870 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
871 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
872 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
873 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
874 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
875 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
876 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
877 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
878 +};
879 +
880 +#define CRC_INNER_LOOP(n, c, x) \
881 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
882 +
883 +uint8
884 +hndcrc8(
885 + uint8 *pdata, /* pointer to array of data to process */
886 + uint nbytes, /* number of input data bytes to process */
887 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
888 +)
889 +{
890 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
891 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
892 + while (nbytes-- > 0)
893 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
894 +
895 + return crc;
896 +}
897 +
898 +#ifdef notdef
899 +#define CLEN 1499
900 +#define CBUFSIZ (CLEN+4)
901 +#define CNBUFS 5
902 +
903 +#endif
904 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
905 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
906 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2005-12-17 21:40:08.166726750 +0100
907 @@ -0,0 +1,234 @@
908 +/*
909 + * NVRAM variable manipulation (Linux kernel half)
910 + *
911 + * Copyright 2001-2003, Broadcom Corporation
912 + * All Rights Reserved.
913 + *
914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
918 + *
919 + * $Id$
920 + */
921 +
922 +#include <linux/config.h>
923 +#include <linux/init.h>
924 +#include <linux/module.h>
925 +#include <linux/kernel.h>
926 +#include <linux/string.h>
927 +#include <asm/io.h>
928 +#include <asm/uaccess.h>
929 +
930 +#include <typedefs.h>
931 +#include <osl.h>
932 +#include <bcmendian.h>
933 +#include <bcmutils.h>
934 +
935 +#define NVRAM_SIZE (0x1ff0)
936 +static char _nvdata[NVRAM_SIZE] __initdata;
937 +static char _valuestr[256] __initdata;
938 +
939 +/*
940 + * TLV types. These codes are used in the "type-length-value"
941 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
942 + *
943 + * The layout of the flash/nvram is as follows:
944 + *
945 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
946 + *
947 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
948 + * The "length" field marks the length of the data section, not
949 + * including the type and length fields.
950 + *
951 + * Environment variables are stored as follows:
952 + *
953 + * <type_env> <length> <flags> <name> = <value>
954 + *
955 + * If bit 0 (low bit) is set, the length is an 8-bit value.
956 + * If bit 0 (low bit) is clear, the length is a 16-bit value
957 + *
958 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
959 + * indicates the size of the length field.
960 + *
961 + * Flags are from the constants below:
962 + *
963 + */
964 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
965 +#define ENV_LENGTH_8BITS 0x01
966 +
967 +#define ENV_TYPE_USER 0x80
968 +
969 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
970 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
971 +
972 +/*
973 + * The actual TLV types we support
974 + */
975 +
976 +#define ENV_TLV_TYPE_END 0x00
977 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
978 +
979 +/*
980 + * Environment variable flags
981 + */
982 +
983 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
984 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
985 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
986 +
987 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
988 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
989 +
990 +
991 +/* *********************************************************************
992 + * _nvram_read(buffer,offset,length)
993 + *
994 + * Read data from the NVRAM device
995 + *
996 + * Input parameters:
997 + * buffer - destination buffer
998 + * offset - offset of data to read
999 + * length - number of bytes to read
1000 + *
1001 + * Return value:
1002 + * number of bytes read, or <0 if error occured
1003 + ********************************************************************* */
1004 +static int
1005 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1006 +{
1007 + int i;
1008 + if (offset > NVRAM_SIZE)
1009 + return -1;
1010 +
1011 + for ( i = 0; i < length; i++) {
1012 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1013 + }
1014 + return length;
1015 +}
1016 +
1017 +
1018 +static char*
1019 +_strnchr(const char *dest,int c,size_t cnt)
1020 +{
1021 + while (*dest && (cnt > 0)) {
1022 + if (*dest == c) return (char *) dest;
1023 + dest++;
1024 + cnt--;
1025 + }
1026 + return NULL;
1027 +}
1028 +
1029 +
1030 +
1031 +/*
1032 + * Core support API: Externally visible.
1033 + */
1034 +
1035 +/*
1036 + * Get the value of an NVRAM variable
1037 + * @param name name of variable to get
1038 + * @return value of variable or NULL if undefined
1039 + */
1040 +
1041 +char*
1042 +cfe_env_get(unsigned char *nv_buf, char* name)
1043 +{
1044 + int size;
1045 + unsigned char *buffer;
1046 + unsigned char *ptr;
1047 + unsigned char *envval;
1048 + unsigned int reclen;
1049 + unsigned int rectype;
1050 + int offset;
1051 + int flg;
1052 +
1053 + size = NVRAM_SIZE;
1054 + buffer = &_nvdata[0];
1055 +
1056 + ptr = buffer;
1057 + offset = 0;
1058 +
1059 + /* Read the record type and length */
1060 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1061 + goto error;
1062 + }
1063 +
1064 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1065 +
1066 + /* Adjust pointer for TLV type */
1067 + rectype = *(ptr);
1068 + offset++;
1069 + size--;
1070 +
1071 + /*
1072 + * Read the length. It can be either 1 or 2 bytes
1073 + * depending on the code
1074 + */
1075 + if (rectype & ENV_LENGTH_8BITS) {
1076 + /* Read the record type and length - 8 bits */
1077 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1078 + goto error;
1079 + }
1080 + reclen = *(ptr);
1081 + size--;
1082 + offset++;
1083 + }
1084 + else {
1085 + /* Read the record type and length - 16 bits, MSB first */
1086 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1087 + goto error;
1088 + }
1089 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1090 + size -= 2;
1091 + offset += 2;
1092 + }
1093 +
1094 + if (reclen > size)
1095 + break; /* should not happen, bad NVRAM */
1096 +
1097 + switch (rectype) {
1098 + case ENV_TLV_TYPE_ENV:
1099 + /* Read the TLV data */
1100 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1101 + goto error;
1102 + flg = *ptr++;
1103 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1104 + if (envval) {
1105 + *envval++ = '\0';
1106 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1107 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1108 +#if 0
1109 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1110 +#endif
1111 + if(!strcmp(ptr, name)){
1112 + return _valuestr;
1113 + }
1114 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1115 + return _valuestr;
1116 + }
1117 + break;
1118 +
1119 + default:
1120 + /* Unknown TLV type, skip it. */
1121 + break;
1122 + }
1123 +
1124 + /*
1125 + * Advance to next TLV
1126 + */
1127 +
1128 + size -= (int)reclen;
1129 + offset += reclen;
1130 +
1131 + /* Read the next record type */
1132 + ptr = buffer;
1133 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1134 + goto error;
1135 + }
1136 +
1137 +error:
1138 + return NULL;
1139 +
1140 +}
1141 +
1142 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1143 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1144 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-12-15 17:11:05.818041750 +0100
1145 @@ -0,0 +1,102 @@
1146 +/*
1147 + * Linux OS Independent Layer
1148 + *
1149 + * Copyright 2005, Broadcom Corporation
1150 + * All Rights Reserved.
1151 + *
1152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1156 + *
1157 + * $Id$
1158 + */
1159 +
1160 +#define LINUX_OSL
1161 +
1162 +#include <typedefs.h>
1163 +#include <bcmendian.h>
1164 +#include <linux/module.h>
1165 +#include <linuxver.h>
1166 +#include <osl.h>
1167 +#include <bcmutils.h>
1168 +#include <linux/delay.h>
1169 +#ifdef mips
1170 +#include <asm/paccess.h>
1171 +#endif
1172 +#include <pcicfg.h>
1173 +
1174 +#define PCI_CFG_RETRY 10
1175 +
1176 +#define OS_HANDLE_MAGIC 0x1234abcd
1177 +#define BCM_MEM_FILENAME_LEN 24
1178 +
1179 +typedef struct bcm_mem_link {
1180 + struct bcm_mem_link *prev;
1181 + struct bcm_mem_link *next;
1182 + uint size;
1183 + int line;
1184 + char file[BCM_MEM_FILENAME_LEN];
1185 +} bcm_mem_link_t;
1186 +
1187 +struct os_handle {
1188 + uint magic;
1189 + void *pdev;
1190 + uint malloced;
1191 + uint failed;
1192 + bcm_mem_link_t *dbgmem_list;
1193 +};
1194 +
1195 +uint32
1196 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1197 +{
1198 + uint val;
1199 + uint retry=PCI_CFG_RETRY;
1200 +
1201 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1202 +
1203 + /* only 4byte access supported */
1204 + ASSERT(size == 4);
1205 +
1206 + do {
1207 + pci_read_config_dword(osh->pdev, offset, &val);
1208 + if (val != 0xffffffff)
1209 + break;
1210 + } while (retry--);
1211 +
1212 +
1213 + return (val);
1214 +}
1215 +
1216 +void
1217 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1218 +{
1219 + uint retry=PCI_CFG_RETRY;
1220 +
1221 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1222 +
1223 + /* only 4byte access supported */
1224 + ASSERT(size == 4);
1225 +
1226 + do {
1227 + pci_write_config_dword(osh->pdev, offset, val);
1228 + if (offset!=PCI_BAR0_WIN)
1229 + break;
1230 + if (osl_pci_read_config(osh,offset,size) == val)
1231 + break;
1232 + } while (retry--);
1233 +
1234 +}
1235 +
1236 +void
1237 +osl_delay(uint usec)
1238 +{
1239 + uint d;
1240 +
1241 + while (usec > 0) {
1242 + d = MIN(usec, 1000);
1243 + udelay(d);
1244 + usec -= d;
1245 + }
1246 +}
1247 +
1248 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1249 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1250 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2005-12-18 04:59:36.185204500 +0100
1251 @@ -0,0 +1,165 @@
1252 +/*
1253 + * NVRAM variable manipulation (Linux kernel half)
1254 + *
1255 + * Copyright 2005, Broadcom Corporation
1256 + * All Rights Reserved.
1257 + *
1258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1262 + *
1263 + * $Id$
1264 + */
1265 +
1266 +#include <linux/config.h>
1267 +#include <linux/init.h>
1268 +#include <linux/module.h>
1269 +#include <linux/kernel.h>
1270 +#include <linux/string.h>
1271 +#include <linux/interrupt.h>
1272 +#include <linux/spinlock.h>
1273 +#include <linux/slab.h>
1274 +#include <asm/bootinfo.h>
1275 +#include <asm/addrspace.h>
1276 +#include <asm/io.h>
1277 +#include <asm/uaccess.h>
1278 +
1279 +#include <typedefs.h>
1280 +#include <bcmendian.h>
1281 +#include <bcmnvram.h>
1282 +#include <bcmutils.h>
1283 +#include <sbconfig.h>
1284 +#include <sbchipc.h>
1285 +#include <sbutils.h>
1286 +#include <sbmips.h>
1287 +#include <sflash.h>
1288 +
1289 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1290 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1291 +
1292 +/* Global SB handle */
1293 +extern void *sbh;
1294 +extern spinlock_t bcm947xx_sbh_lock;
1295 +static int cfe_env;
1296 +
1297 +extern char *cfe_env_get(char *nv_buf, const char *name);
1298 +
1299 +
1300 +/* Convenience */
1301 +#define sbh_lock bcm947xx_sbh_lock
1302 +#define KB * 1024
1303 +#define MB * 1024 * 1024
1304 +
1305 +/* Probe for NVRAM header */
1306 +static void __init
1307 +early_nvram_init(void)
1308 +{
1309 + struct nvram_header *header;
1310 + chipcregs_t *cc;
1311 + struct sflash *info = NULL;
1312 + int i;
1313 + uint32 base, off, lim;
1314 + u32 *src, *dst;
1315 +
1316 + cfe_env = 0;
1317 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1318 + base = KSEG1ADDR(SB_FLASH2);
1319 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1320 + case PFLASH:
1321 + lim = SB_FLASH2_SZ;
1322 + break;
1323 +
1324 + case SFLASH_ST:
1325 + case SFLASH_AT:
1326 + if ((info = sflash_init(cc)) == NULL)
1327 + return;
1328 + lim = info->size;
1329 + break;
1330 +
1331 + case FLASH_NONE:
1332 + default:
1333 + return;
1334 + }
1335 + } else {
1336 + /* extif assumed, Stop at 4 MB */
1337 + base = KSEG1ADDR(SB_FLASH1);
1338 + lim = SB_FLASH1_SZ;
1339 + }
1340 +
1341 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1342 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1343 + dst = (u32 *) nvram_buf;
1344 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1345 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1346 +
1347 + for (i = 0; i < 0x1ff0; i++) {
1348 + if (*src == 0xFFFFFFFF)
1349 + break;
1350 + *dst++ = *src++;
1351 + }
1352 + cfe_env = 1;
1353 + return;
1354 + }
1355 +
1356 + off = FLASH_MIN;
1357 + while (off <= lim) {
1358 + /* Windowed flash access */
1359 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1360 + if (header->magic == NVRAM_MAGIC)
1361 + goto found;
1362 + off <<= 1;
1363 + }
1364 +
1365 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1366 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1367 + if (header->magic == NVRAM_MAGIC)
1368 + goto found;
1369 +
1370 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1371 + if (header->magic == NVRAM_MAGIC)
1372 + goto found;
1373 +
1374 + return;
1375 +
1376 +found:
1377 + src = (u32 *) header;
1378 + dst = (u32 *) nvram_buf;
1379 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1380 + *dst++ = *src++;
1381 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1382 + *dst++ = ltoh32(*src++);
1383 +}
1384 +
1385 +/* Early (before mm or mtd) read-only access to NVRAM */
1386 +char * __init nvram_get(const char *name)
1387 +{
1388 + char *var, *value, *end, *eq;
1389 +
1390 + if (!name)
1391 + return NULL;
1392 +
1393 + /* Too early? */
1394 + if (sbh == NULL)
1395 + return NULL;
1396 +
1397 + if (!nvram_buf[0])
1398 + early_nvram_init();
1399 +
1400 + if (cfe_env)
1401 + return cfe_env_get(nvram_buf, name);
1402 +
1403 + /* Look for name=value and return value */
1404 + var = &nvram_buf[sizeof(struct nvram_header)];
1405 + end = nvram_buf + sizeof(nvram_buf) - 2;
1406 + end[0] = end[1] = '\0';
1407 + for (; *var; var = value + strlen(value) + 1) {
1408 + if (!(eq = strchr(var, '=')))
1409 + break;
1410 + value = eq + 1;
1411 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1412 + return value;
1413 + }
1414 +
1415 + return NULL;
1416 +}
1417 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1418 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1419 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2005-12-15 16:46:31.122961250 +0100
1420 @@ -0,0 +1,1038 @@
1421 +/*
1422 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1423 + *
1424 + * Copyright 2005, Broadcom Corporation
1425 + * All Rights Reserved.
1426 + *
1427 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1428 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1429 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1430 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1431 + *
1432 + * $Id$
1433 + */
1434 +
1435 +#include <typedefs.h>
1436 +#include <osl.h>
1437 +#include <sbutils.h>
1438 +#include <bcmdevs.h>
1439 +#include <bcmnvram.h>
1440 +#include <bcmutils.h>
1441 +#include <hndmips.h>
1442 +#include <sbconfig.h>
1443 +#include <sbextif.h>
1444 +#include <sbchipc.h>
1445 +#include <sbmemc.h>
1446 +#include <mipsinc.h>
1447 +#include <sbutils.h>
1448 +
1449 +/*
1450 + * Returns TRUE if an external UART exists at the given base
1451 + * register.
1452 + */
1453 +static bool
1454 +BCMINITFN(serial_exists)(uint8 *regs)
1455 +{
1456 + uint8 save_mcr, status1;
1457 +
1458 + save_mcr = R_REG(&regs[UART_MCR]);
1459 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1460 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1461 + W_REG(&regs[UART_MCR], save_mcr);
1462 +
1463 + return (status1 == 0x90);
1464 +}
1465 +
1466 +/*
1467 + * Initializes UART access. The callback function will be called once
1468 + * per found UART.
1469 + */
1470 +void
1471 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1472 +{
1473 + void *regs;
1474 + ulong base;
1475 + uint irq;
1476 + int i, n;
1477 +
1478 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1479 + extifregs_t *eir = (extifregs_t *) regs;
1480 + sbconfig_t *sb;
1481 +
1482 + /* Determine external UART register base */
1483 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1484 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1485 +
1486 + /* Determine IRQ */
1487 + irq = sb_irq(sbh);
1488 +
1489 + /* Disable GPIO interrupt initially */
1490 + W_REG(&eir->gpiointpolarity, 0);
1491 + W_REG(&eir->gpiointmask, 0);
1492 +
1493 + /* Search for external UARTs */
1494 + n = 2;
1495 + for (i = 0; i < 2; i++) {
1496 + regs = (void *) REG_MAP(base + (i * 8), 8);
1497 + if (BCMINIT(serial_exists)(regs)) {
1498 + /* Set GPIO 1 to be the external UART IRQ */
1499 + W_REG(&eir->gpiointmask, 2);
1500 + if (add)
1501 + add(regs, irq, 13500000, 0);
1502 + }
1503 + }
1504 +
1505 + /* Add internal UART if enabled */
1506 + if (R_REG(&eir->corecontrol) & CC_UE)
1507 + if (add)
1508 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1509 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1510 + chipcregs_t *cc = (chipcregs_t *) regs;
1511 + uint32 rev, cap, pll, baud_base, div;
1512 +
1513 + /* Determine core revision and capabilities */
1514 + rev = sb_corerev(sbh);
1515 + cap = R_REG(&cc->capabilities);
1516 + pll = cap & CAP_PLL_MASK;
1517 +
1518 + /* Determine IRQ */
1519 + irq = sb_irq(sbh);
1520 +
1521 + if (pll == PLL_TYPE1) {
1522 + /* PLL clock */
1523 + baud_base = sb_clock_rate(pll,
1524 + R_REG(&cc->clockcontrol_n),
1525 + R_REG(&cc->clockcontrol_m2));
1526 + div = 1;
1527 + } else {
1528 + if (rev >= 11) {
1529 + /* Fixed ALP clock */
1530 + baud_base = 20000000;
1531 + div = 1;
1532 + /* Set the override bit so we don't divide it */
1533 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1534 + } else if (rev >= 3) {
1535 + /* Internal backplane clock */
1536 + baud_base = sb_clock(sbh);
1537 + div = 2; /* Minimum divisor */
1538 + W_REG(&cc->clkdiv,
1539 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1540 + } else {
1541 + /* Fixed internal backplane clock */
1542 + baud_base = 88000000;
1543 + div = 48;
1544 + }
1545 +
1546 + /* Clock source depends on strapping if UartClkOverride is unset */
1547 + if ((rev > 0) &&
1548 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1549 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1550 + /* Internal divided backplane clock */
1551 + baud_base /= div;
1552 + } else {
1553 + /* Assume external clock of 1.8432 MHz */
1554 + baud_base = 1843200;
1555 + }
1556 + }
1557 + }
1558 +
1559 + /* Add internal UARTs */
1560 + n = cap & CAP_UARTS_MASK;
1561 + for (i = 0; i < n; i++) {
1562 + /* Register offset changed after revision 0 */
1563 + if (rev)
1564 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1565 + else
1566 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1567 +
1568 + if (add)
1569 + add(regs, irq, baud_base, 0);
1570 + }
1571 + }
1572 +}
1573 +
1574 +/*
1575 + * Initialize jtag master and return handle for
1576 + * jtag_rwreg. Returns NULL on failure.
1577 + */
1578 +void *
1579 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1580 +{
1581 + void *regs;
1582 +
1583 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1584 + chipcregs_t *cc = (chipcregs_t *) regs;
1585 + uint32 tmp;
1586 +
1587 + /*
1588 + * Determine jtagm availability from
1589 + * core revision and capabilities.
1590 + */
1591 + tmp = sb_corerev(sbh);
1592 + /*
1593 + * Corerev 10 has jtagm, but the only chip
1594 + * with it does not have a mips, and
1595 + * the layout of the jtagcmd register is
1596 + * different. We'll only accept >= 11.
1597 + */
1598 + if (tmp < 11)
1599 + return (NULL);
1600 +
1601 + tmp = R_REG(&cc->capabilities);
1602 + if ((tmp & CAP_JTAGP) == 0)
1603 + return (NULL);
1604 +
1605 + /* Set clock divider if requested */
1606 + if (clkd != 0) {
1607 + tmp = R_REG(&cc->clkdiv);
1608 + tmp = (tmp & ~CLKD_JTAG) |
1609 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1610 + W_REG(&cc->clkdiv, tmp);
1611 + }
1612 +
1613 + /* Enable jtagm */
1614 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1615 + W_REG(&cc->jtagctrl, tmp);
1616 + }
1617 +
1618 + return (regs);
1619 +}
1620 +
1621 +void
1622 +sb_jtagm_disable(void *h)
1623 +{
1624 + chipcregs_t *cc = (chipcregs_t *)h;
1625 +
1626 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1627 +}
1628 +
1629 +/*
1630 + * Read/write a jtag register. Assumes a target with
1631 + * 8 bit IR and 32 bit DR.
1632 + */
1633 +#define IRWIDTH 8
1634 +#define DRWIDTH 32
1635 +uint32
1636 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1637 +{
1638 + chipcregs_t *cc = (chipcregs_t *) h;
1639 + uint32 tmp;
1640 +
1641 + W_REG(&cc->jtagir, ir);
1642 + W_REG(&cc->jtagdr, dr);
1643 + tmp = JCMD_START | JCMD_ACC_IRDR |
1644 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1645 + (DRWIDTH - 1);
1646 + W_REG(&cc->jtagcmd, tmp);
1647 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1648 + /* OSL_DELAY(1); */
1649 + }
1650 +
1651 + tmp = R_REG(&cc->jtagdr);
1652 + return (tmp);
1653 +}
1654 +
1655 +/* Returns the SB interrupt flag of the current core. */
1656 +uint32
1657 +sb_flag(sb_t *sbh)
1658 +{
1659 + void *regs;
1660 + sbconfig_t *sb;
1661 +
1662 + regs = sb_coreregs(sbh);
1663 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1664 +
1665 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1666 +}
1667 +
1668 +static const uint32 sbips_int_mask[] = {
1669 + 0,
1670 + SBIPS_INT1_MASK,
1671 + SBIPS_INT2_MASK,
1672 + SBIPS_INT3_MASK,
1673 + SBIPS_INT4_MASK
1674 +};
1675 +
1676 +static const uint32 sbips_int_shift[] = {
1677 + 0,
1678 + 0,
1679 + SBIPS_INT2_SHIFT,
1680 + SBIPS_INT3_SHIFT,
1681 + SBIPS_INT4_SHIFT
1682 +};
1683 +
1684 +/*
1685 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1686 + * 0 is returned.
1687 + */
1688 +uint
1689 +sb_irq(sb_t *sbh)
1690 +{
1691 + uint idx;
1692 + void *regs;
1693 + sbconfig_t *sb;
1694 + uint32 flag, sbipsflag;
1695 + uint irq = 0;
1696 +
1697 + flag = sb_flag(sbh);
1698 +
1699 + idx = sb_coreidx(sbh);
1700 +
1701 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1702 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1703 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1704 +
1705 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1706 + sbipsflag = R_REG(&sb->sbipsflag);
1707 + for (irq = 1; irq <= 4; irq++) {
1708 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1709 + break;
1710 + }
1711 + if (irq == 5)
1712 + irq = 0;
1713 + }
1714 +
1715 + sb_setcoreidx(sbh, idx);
1716 +
1717 + return irq;
1718 +}
1719 +
1720 +/* Clears the specified MIPS IRQ. */
1721 +static void
1722 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 +
1727 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1728 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1729 + ASSERT(regs);
1730 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1731 +
1732 + if (irq == 0)
1733 + W_REG(&sb->sbintvec, 0);
1734 + else
1735 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1736 +}
1737 +
1738 +/*
1739 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1740 + * IRQ 0 may be assigned more than once.
1741 + */
1742 +static void
1743 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1744 +{
1745 + void *regs;
1746 + sbconfig_t *sb;
1747 + uint32 flag;
1748 +
1749 + regs = sb_setcore(sbh, coreid, coreunit);
1750 + ASSERT(regs);
1751 + flag = sb_flag(sbh);
1752 +
1753 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1754 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1755 + ASSERT(regs);
1756 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1757 +
1758 + if (irq == 0)
1759 + OR_REG(&sb->sbintvec, 1 << flag);
1760 + else {
1761 + flag <<= sbips_int_shift[irq];
1762 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1763 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1764 + W_REG(&sb->sbipsflag, flag);
1765 + }
1766 +}
1767 +
1768 +/*
1769 + * Initializes clocks and interrupts. SB and NVRAM access must be
1770 + * initialized prior to calling.
1771 + */
1772 +void
1773 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1774 +{
1775 + ulong hz, ns, tmp;
1776 + extifregs_t *eir;
1777 + chipcregs_t *cc;
1778 + char *value;
1779 + uint irq;
1780 +
1781 + /* Figure out current SB clock speed */
1782 + if ((hz = sb_clock(sbh)) == 0)
1783 + hz = 100000000;
1784 + ns = 1000000000 / hz;
1785 +
1786 + /* Setup external interface timing */
1787 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1788 + /* Initialize extif so we can get to the LEDs and external UART */
1789 + W_REG(&eir->prog_config, CF_EN);
1790 +
1791 + /* Set timing for the flash */
1792 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1793 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1794 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1795 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1796 +
1797 + /* Set programmable interface timing for external uart */
1798 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1799 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1800 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1801 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1802 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1803 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1804 + /* Set timing for the flash */
1805 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1806 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1807 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1808 +
1809 + // Added by Chen-I for 5365
1810 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1811 + {
1812 + W_REG(&cc->flash_waitcount, tmp);
1813 + W_REG(&cc->pcmcia_memwait, tmp);
1814 + }
1815 + else
1816 + {
1817 + if (sb_corerev(sbh) < 9)
1818 + W_REG(&cc->flash_waitcount, tmp);
1819 +
1820 + if ((sb_corerev(sbh) < 9) ||
1821 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1822 + W_REG(&cc->pcmcia_memwait, tmp);
1823 + }
1824 + }
1825 + }
1826 +
1827 + /* Chip specific initialization */
1828 + switch (BCMINIT(sb_chip)(sbh)) {
1829 + case BCM4710_DEVICE_ID:
1830 + /* Clear interrupt map */
1831 + for (irq = 0; irq <= 4; irq++)
1832 + BCMINIT(sb_clearirq)(sbh, irq);
1833 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1834 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1835 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1836 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1837 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1838 + ASSERT(eir);
1839 + value = BCMINIT(nvram_get)("et0phyaddr");
1840 + if (value && !strcmp(value, "31")) {
1841 + /* Enable internal UART */
1842 + W_REG(&eir->corecontrol, CC_UE);
1843 + /* Give USB its own interrupt */
1844 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1845 + } else {
1846 + /* Disable internal UART */
1847 + W_REG(&eir->corecontrol, 0);
1848 + /* Give Ethernet its own interrupt */
1849 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1850 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1851 + }
1852 + break;
1853 + case BCM5350_DEVICE_ID:
1854 + /* Clear interrupt map */
1855 + for (irq = 0; irq <= 4; irq++)
1856 + BCMINIT(sb_clearirq)(sbh, irq);
1857 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1858 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1859 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1860 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1861 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1862 + break;
1863 + }
1864 +}
1865 +
1866 +uint32
1867 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1868 +{
1869 + extifregs_t *eir;
1870 + chipcregs_t *cc;
1871 + uint32 n, m;
1872 + uint idx;
1873 + uint32 pll_type, rate = 0;
1874 +
1875 + /* get index of the current core */
1876 + idx = sb_coreidx(sbh);
1877 + pll_type = PLL_TYPE1;
1878 +
1879 + /* switch to extif or chipc core */
1880 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1881 + n = R_REG(&eir->clockcontrol_n);
1882 + m = R_REG(&eir->clockcontrol_sb);
1883 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1884 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1885 + n = R_REG(&cc->clockcontrol_n);
1886 + if ((pll_type == PLL_TYPE2) ||
1887 + (pll_type == PLL_TYPE4) ||
1888 + (pll_type == PLL_TYPE6) ||
1889 + (pll_type == PLL_TYPE7))
1890 + m = R_REG(&cc->clockcontrol_mips);
1891 + else if (pll_type == PLL_TYPE5) {
1892 + rate = 200000000;
1893 + goto out;
1894 + }
1895 + else if (pll_type == PLL_TYPE3) {
1896 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1897 + rate = 200000000;
1898 + goto out;
1899 + } else
1900 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1901 + } else
1902 + m = R_REG(&cc->clockcontrol_sb);
1903 + } else
1904 + goto out;
1905 +
1906 + // Added by Chen-I for 5365
1907 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1908 + rate = 100000000;
1909 + else
1910 + /* calculate rate */
1911 + rate = sb_clock_rate(pll_type, n, m);
1912 +
1913 + if (pll_type == PLL_TYPE6)
1914 + rate = SB2MIPS_T6(rate);
1915 +
1916 +out:
1917 + /* switch back to previous core */
1918 + sb_setcoreidx(sbh, idx);
1919 +
1920 + return rate;
1921 +}
1922 +
1923 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1924 +
1925 +static void
1926 +BCMINITFN(handler)(void)
1927 +{
1928 + /* Step 11 */
1929 + __asm__ (
1930 + ".set\tmips32\n\t"
1931 + "ssnop\n\t"
1932 + "ssnop\n\t"
1933 + /* Disable interrupts */
1934 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1935 + "mfc0 $15, $12\n\t"
1936 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1937 + "li $14, -31746\n\t"
1938 + "and $15, $15, $14\n\t"
1939 + "mtc0 $15, $12\n\t"
1940 + "eret\n\t"
1941 + "nop\n\t"
1942 + "nop\n\t"
1943 + ".set\tmips0"
1944 + );
1945 +}
1946 +
1947 +/* The following MUST come right after handler() */
1948 +static void
1949 +BCMINITFN(afterhandler)(void)
1950 +{
1951 +}
1952 +
1953 +/*
1954 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1955 + */
1956 +bool
1957 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1958 +{
1959 + extifregs_t *eir = NULL;
1960 + chipcregs_t *cc = NULL;
1961 + mipsregs_t *mipsr = NULL;
1962 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1963 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1964 + uint32 pll_type, sync_mode;
1965 + uint ic_size, ic_lsize;
1966 + uint idx, i;
1967 + typedef struct {
1968 + uint32 mipsclock;
1969 + uint16 n;
1970 + uint32 sb;
1971 + uint32 pci33;
1972 + uint32 pci25;
1973 + } n3m_table_t;
1974 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1975 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1976 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1977 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1978 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1979 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1980 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1981 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1982 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1983 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1984 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1985 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1986 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1987 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1988 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1989 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1990 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1991 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1992 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1993 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1994 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1995 + };
1996 + typedef struct {
1997 + uint32 mipsclock;
1998 + uint16 n;
1999 + uint32 m2; /* that is the clockcontrol_m2 */
2000 + } type3_table_t;
2001 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
2002 + { 150000000, 0x311, 0x4020005 },
2003 + { 200000000, 0x311, 0x4020003 },
2004 + };
2005 + typedef struct {
2006 + uint32 mipsclock;
2007 + uint32 sbclock;
2008 + uint16 n;
2009 + uint32 sb;
2010 + uint32 pci33;
2011 + uint32 m2;
2012 + uint32 m3;
2013 + uint32 ratio_cfg;
2014 + uint32 ratio_parm;
2015 + } n4m_table_t;
2016 +
2017 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2018 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2019 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2020 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2021 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2023 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2026 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2027 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2028 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2029 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2031 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2032 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2033 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2034 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2035 + };
2036 +
2037 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2038 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2039 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2041 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2042 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2043 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2045 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2047 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2048 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2049 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2050 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2051 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2052 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2053 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2054 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2055 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2056 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2057 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2058 + };
2059 +
2060 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2061 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2062 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2063 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2065 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2066 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2067 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2068 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2070 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2071 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2072 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2073 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2074 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2075 + };
2076 +
2077 + ulong start, end, dst;
2078 + bool ret = FALSE;
2079 +
2080 + /* get index of the current core */
2081 + idx = sb_coreidx(sbh);
2082 + clockcontrol_m2 = NULL;
2083 +
2084 + /* switch to extif or chipc core */
2085 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2086 + pll_type = PLL_TYPE1;
2087 + clockcontrol_n = &eir->clockcontrol_n;
2088 + clockcontrol_sb = &eir->clockcontrol_sb;
2089 + clockcontrol_pci = &eir->clockcontrol_pci;
2090 + clockcontrol_m2 = &cc->clockcontrol_m2;
2091 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2092 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2093 + if (pll_type == PLL_TYPE6) {
2094 + clockcontrol_n = NULL;
2095 + clockcontrol_sb = NULL;
2096 + clockcontrol_pci = NULL;
2097 + } else {
2098 + clockcontrol_n = &cc->clockcontrol_n;
2099 + clockcontrol_sb = &cc->clockcontrol_sb;
2100 + clockcontrol_pci = &cc->clockcontrol_pci;
2101 + clockcontrol_m2 = &cc->clockcontrol_m2;
2102 + }
2103 + } else
2104 + goto done;
2105 +
2106 + if (pll_type == PLL_TYPE6) {
2107 + /* Silence compilers */
2108 + orig_n = orig_sb = orig_pci = 0;
2109 + } else {
2110 + /* Store the current clock register values */
2111 + orig_n = R_REG(clockcontrol_n);
2112 + orig_sb = R_REG(clockcontrol_sb);
2113 + orig_pci = R_REG(clockcontrol_pci);
2114 + }
2115 +
2116 + if (pll_type == PLL_TYPE1) {
2117 + /* Keep the current PCI clock if not specified */
2118 + if (pciclock == 0) {
2119 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2120 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2121 + }
2122 +
2123 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2124 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2125 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2126 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2127 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2128 + break;
2129 + }
2130 + if (i == 0) {
2131 + ret = FALSE;
2132 + goto done;
2133 + } else {
2134 + ret = TRUE;
2135 + i--;
2136 + }
2137 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2138 +
2139 + /* No PLL change */
2140 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2141 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2142 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2143 + goto done;
2144 +
2145 + /* Set the PLL controls */
2146 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2147 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2148 + if (pciclock == 25000000)
2149 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2150 + else
2151 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2152 +
2153 + /* Reset */
2154 + sb_watchdog(sbh, 1);
2155 +
2156 + while (1);
2157 + } else if ((pll_type == PLL_TYPE3) &&
2158 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2159 + /* 5350 */
2160 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2161 +
2162 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2163 + if (type3_table[i].mipsclock > mipsclock)
2164 + break;
2165 + }
2166 + if (i == 0) {
2167 + ret = FALSE;
2168 + goto done;
2169 + } else {
2170 + ret = TRUE;
2171 + i--;
2172 + }
2173 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2174 +
2175 + /* No PLL change */
2176 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2177 + if ((orig_n == type3_table[i].n) &&
2178 + (orig_m2 == type3_table[i].m2)) {
2179 + goto done;
2180 + }
2181 +
2182 + /* Set the PLL controls */
2183 + W_REG(clockcontrol_n, type3_table[i].n);
2184 + W_REG(clockcontrol_m2, type3_table[i].m2);
2185 +
2186 + /* Reset */
2187 + sb_watchdog(sbh, 1);
2188 + while (1);
2189 + } else if ((pll_type == PLL_TYPE2) ||
2190 + (pll_type == PLL_TYPE4) ||
2191 + (pll_type == PLL_TYPE6) ||
2192 + (pll_type == PLL_TYPE7)) {
2193 + n4m_table_t *table = NULL, *te;
2194 + uint tabsz = 0;
2195 +
2196 + ASSERT(cc);
2197 +
2198 + orig_mips = R_REG(&cc->clockcontrol_mips);
2199 +
2200 + if (pll_type == PLL_TYPE6) {
2201 + uint32 new_mips = 0;
2202 +
2203 + ret = TRUE;
2204 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2205 + new_mips = CC_T6_MMASK;
2206 +
2207 + if (orig_mips == new_mips)
2208 + goto done;
2209 +
2210 + W_REG(&cc->clockcontrol_mips, new_mips);
2211 + goto end_fill;
2212 + }
2213 +
2214 + if (pll_type == PLL_TYPE2) {
2215 + table = BCMINIT(type2_table);
2216 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2217 + } else if (pll_type == PLL_TYPE4) {
2218 + table = BCMINIT(type4_table);
2219 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2220 + } else if (pll_type == PLL_TYPE7) {
2221 + table = BCMINIT(type7_table);
2222 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2223 + } else
2224 + ASSERT("No table for plltype" == NULL);
2225 +
2226 + /* Store the current clock register values */
2227 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2228 + orig_ratio_parm = 0;
2229 + orig_ratio_cfg = 0;
2230 +
2231 + /* Look up current ratio */
2232 + for (i = 0; i < tabsz; i++) {
2233 + if ((orig_n == table[i].n) &&
2234 + (orig_sb == table[i].sb) &&
2235 + (orig_pci == table[i].pci33) &&
2236 + (orig_m2 == table[i].m2) &&
2237 + (orig_mips == table[i].m3)) {
2238 + orig_ratio_parm = table[i].ratio_parm;
2239 + orig_ratio_cfg = table[i].ratio_cfg;
2240 + break;
2241 + }
2242 + }
2243 +
2244 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2245 + for (i = 0; i < tabsz; i++) {
2246 + ASSERT(table[i].mipsclock ==
2247 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2248 + if ((mipsclock <= table[i].mipsclock) &&
2249 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2250 + break;
2251 + }
2252 + if (i == tabsz) {
2253 + ret = FALSE;
2254 + goto done;
2255 + } else {
2256 + te = &table[i];
2257 + ret = TRUE;
2258 + }
2259 +
2260 + /* No PLL change */
2261 + if ((orig_n == te->n) &&
2262 + (orig_sb == te->sb) &&
2263 + (orig_pci == te->pci33) &&
2264 + (orig_m2 == te->m2) &&
2265 + (orig_mips == te->m3))
2266 + goto done;
2267 +
2268 + /* Set the PLL controls */
2269 + W_REG(clockcontrol_n, te->n);
2270 + W_REG(clockcontrol_sb, te->sb);
2271 + W_REG(clockcontrol_pci, te->pci33);
2272 + W_REG(&cc->clockcontrol_m2, te->m2);
2273 + W_REG(&cc->clockcontrol_mips, te->m3);
2274 +
2275 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2276 + if ((pll_type == PLL_TYPE7) &&
2277 + (te->sb != te->m2) &&
2278 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2279 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2280 +
2281 + /* No ratio change */
2282 + if (orig_ratio_parm == te->ratio_parm)
2283 + goto end_fill;
2284 +
2285 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2286 +
2287 + /* Preload the code into the cache */
2288 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2289 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2290 + while (start < end) {
2291 + cache_op(start, Fill_I);
2292 + start += ic_lsize;
2293 + }
2294 +
2295 + /* Copy the handler */
2296 + start = (ulong) &BCMINIT(handler);
2297 + end = (ulong) &BCMINIT(afterhandler);
2298 + dst = KSEG1ADDR(0x180);
2299 + for (i = 0; i < (end - start); i += 4)
2300 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2301 +
2302 + /* Preload handler into the cache one line at a time */
2303 + for (i = 0; i < (end - start); i += 4)
2304 + cache_op(dst + i, Fill_I);
2305 +
2306 + /* Clear BEV bit */
2307 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2308 +
2309 + /* Enable interrupts */
2310 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2311 +
2312 + /* Enable MIPS timer interrupt */
2313 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2314 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2315 + ASSERT(mipsr);
2316 + W_REG(&mipsr->intmask, 1);
2317 +
2318 + start_fill:
2319 + /* step 1, set clock ratios */
2320 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2321 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2322 +
2323 + /* step 2: program timer intr */
2324 + W_REG(&mipsr->timer, 100);
2325 + (void) R_REG(&mipsr->timer);
2326 +
2327 + /* step 3, switch to async */
2328 + sync_mode = MFC0(C0_BROADCOM, 4);
2329 + MTC0(C0_BROADCOM, 4, 1 << 22);
2330 +
2331 + /* step 4, set cfg active */
2332 + MTC0(C0_BROADCOM, 2, 0x9);
2333 +
2334 +
2335 + /* steps 5 & 6 */
2336 + __asm__ __volatile__ (
2337 + ".set\tmips3\n\t"
2338 + "wait\n\t"
2339 + ".set\tmips0"
2340 + );
2341 +
2342 + /* step 7, clear cfg_active */
2343 + MTC0(C0_BROADCOM, 2, 0);
2344 +
2345 + /* Additional Step: set back to orig sync mode */
2346 + MTC0(C0_BROADCOM, 4, sync_mode);
2347 +
2348 + /* step 8, fake soft reset */
2349 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2350 +
2351 + end_fill:
2352 + /* step 9 set watchdog timer */
2353 + sb_watchdog(sbh, 20);
2354 + (void) R_REG(&cc->chipid);
2355 +
2356 + /* step 11 */
2357 + __asm__ __volatile__ (
2358 + ".set\tmips3\n\t"
2359 + "sync\n\t"
2360 + "wait\n\t"
2361 + ".set\tmips0"
2362 + );
2363 + while (1);
2364 + }
2365 +
2366 +done:
2367 + /* switch back to previous core */
2368 + sb_setcoreidx(sbh, idx);
2369 +
2370 + return ret;
2371 +}
2372 +
2373 +/*
2374 + * This also must be run from the cache on 47xx
2375 + * so there are no mips core BIU ops in progress
2376 + * when the PFC is enabled.
2377 + */
2378 +
2379 +static void
2380 +BCMINITFN(_enable_pfc)(uint32 mode)
2381 +{
2382 + /* write range */
2383 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2384 +
2385 + /* enable */
2386 + *(volatile uint32 *)PFC_CR0 = mode;
2387 +}
2388 +
2389 +void
2390 +BCMINITFN(enable_pfc)(uint32 mode)
2391 +{
2392 + ulong start, end;
2393 + int i;
2394 +
2395 + /* If auto then choose the correct mode for this
2396 + platform, currently we only ever select one mode */
2397 + if (mode == PFC_AUTO)
2398 + mode = PFC_INST;
2399 +
2400 + /* enable prefetch cache if available */
2401 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2402 + start = (ulong) &BCMINIT(_enable_pfc);
2403 + end = (ulong) &BCMINIT(enable_pfc);
2404 +
2405 + /* Preload handler into the cache one line at a time */
2406 + for (i = 0; i < (end - start); i += 4)
2407 + cache_op(start + i, Fill_I);
2408 +
2409 + BCMINIT(_enable_pfc)(mode);
2410 + }
2411 +}
2412 +
2413 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2414 +uint32
2415 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2416 +{
2417 + sbmemcregs_t *memc;
2418 + uint32 ret = 0;
2419 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2420 + uint idx, rev;
2421 +
2422 + idx = sb_coreidx(sbh);
2423 +
2424 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2425 + if (memc == 0)
2426 + goto out;
2427 +
2428 + rev = sb_corerev(sbh);
2429 +
2430 + config = R_REG(&memc->config);
2431 + wr = R_REG(&memc->wrncdlcor);
2432 + rd = R_REG(&memc->rdncdlcor);
2433 + misc = R_REG(&memc->miscdlyctl);
2434 + dqsg = R_REG(&memc->dqsgatencdl);
2435 +
2436 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2437 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2438 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2439 +
2440 + if (config & MEMC_CONFIG_DDR) {
2441 + ret = (wr << 16) | (rd << 8) | dqsg;
2442 + } else {
2443 + if (rev > 0)
2444 + cd = rd;
2445 + else
2446 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2447 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2448 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2449 + ret = (sm << 16) | (sd << 8) | cd;
2450 + }
2451 +
2452 +out:
2453 + /* switch back to previous core */
2454 + sb_setcoreidx(sbh, idx);
2455 +
2456 + return ret;
2457 +}
2458 +
2459 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2460 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2461 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2005-12-18 05:36:53.351735500 +0100
2462 @@ -0,0 +1,533 @@
2463 +/*
2464 + * Low-Level PCI and SB support for BCM47xx
2465 + *
2466 + * Copyright 2005, Broadcom Corporation
2467 + * All Rights Reserved.
2468 + *
2469 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2470 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2471 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2472 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2473 + *
2474 + * $Id$
2475 + */
2476 +
2477 +#include <typedefs.h>
2478 +#include <pcicfg.h>
2479 +#include <bcmdevs.h>
2480 +#include <sbconfig.h>
2481 +#include <osl.h>
2482 +#include <sbutils.h>
2483 +#include <sbpci.h>
2484 +#include <bcmendian.h>
2485 +#include <bcmutils.h>
2486 +#include <bcmnvram.h>
2487 +#include <hndmips.h>
2488 +
2489 +/* Can free sbpci_init() memory after boot */
2490 +#ifndef linux
2491 +#define __init
2492 +#endif
2493 +
2494 +/* Emulated configuration space */
2495 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2496 +
2497 +/* Banned cores */
2498 +static uint16 pci_ban[32] = { 0 };
2499 +static uint pci_banned = 0;
2500 +
2501 +/* CardBus mode */
2502 +static bool cardbus = FALSE;
2503 +
2504 +/* Disable PCI host core */
2505 +static bool pci_disabled = FALSE;
2506 +
2507 +/*
2508 + * Functions for accessing external PCI configuration space
2509 + */
2510 +
2511 +/* Assume one-hot slot wiring */
2512 +#define PCI_SLOT_MAX 16
2513 +
2514 +static uint32
2515 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2516 +{
2517 + uint coreidx;
2518 + sbpciregs_t *regs;
2519 + uint32 addr = 0;
2520 +
2521 + /* CardBusMode supports only one device */
2522 + if (cardbus && dev > 1)
2523 + return 0;
2524 +
2525 + coreidx = sb_coreidx(sbh);
2526 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2527 +
2528 + /* Type 0 transaction */
2529 + if (bus == 1) {
2530 + /* Skip unwired slots */
2531 + if (dev < PCI_SLOT_MAX) {
2532 + /* Slide the PCI window to the appropriate slot */
2533 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2534 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2535 + (func << 8) | (off & ~3);
2536 + }
2537 + }
2538 +
2539 + /* Type 1 transaction */
2540 + else {
2541 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2542 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2543 + }
2544 +
2545 + sb_setcoreidx(sbh, coreidx);
2546 +
2547 + return addr;
2548 +}
2549 +
2550 +static int
2551 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2552 +{
2553 + uint32 addr, *reg = NULL, val;
2554 + int ret = 0;
2555 +
2556 + if (pci_disabled ||
2557 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2558 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2559 + BUSPROBE(val, reg))
2560 + val = 0xffffffff;
2561 +
2562 + val >>= 8 * (off & 3);
2563 + if (len == 4)
2564 + *((uint32 *) buf) = val;
2565 + else if (len == 2)
2566 + *((uint16 *) buf) = (uint16) val;
2567 + else if (len == 1)
2568 + *((uint8 *) buf) = (uint8) val;
2569 + else
2570 + ret = -1;
2571 +
2572 + if (reg)
2573 + REG_UNMAP(reg);
2574 +
2575 + return ret;
2576 +}
2577 +
2578 +static int
2579 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2580 +{
2581 + uint32 addr, *reg = NULL, val;
2582 + int ret = 0;
2583 +
2584 + if (pci_disabled ||
2585 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2586 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2587 + BUSPROBE(val, reg))
2588 + goto done;
2589 +
2590 + if (len == 4)
2591 + val = *((uint32 *) buf);
2592 + else if (len == 2) {
2593 + val &= ~(0xffff << (8 * (off & 3)));
2594 + val |= *((uint16 *) buf) << (8 * (off & 3));
2595 + } else if (len == 1) {
2596 + val &= ~(0xff << (8 * (off & 3)));
2597 + val |= *((uint8 *) buf) << (8 * (off & 3));
2598 + } else
2599 + ret = -1;
2600 +
2601 + W_REG(reg, val);
2602 +
2603 + done:
2604 + if (reg)
2605 + REG_UNMAP(reg);
2606 +
2607 + return ret;
2608 +}
2609 +
2610 +/*
2611 + * Functions for accessing translated SB configuration space
2612 + */
2613 +
2614 +static int
2615 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2616 +{
2617 + pci_config_regs *cfg;
2618 +
2619 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2620 + return -1;
2621 + cfg = &sb_config_regs[dev];
2622 +
2623 + ASSERT(ISALIGNED(off, len));
2624 + ASSERT(ISALIGNED((uintptr)buf, len));
2625 +
2626 + if (len == 4)
2627 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2628 + else if (len == 2)
2629 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2630 + else if (len == 1)
2631 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2632 + else
2633 + return -1;
2634 +
2635 + return 0;
2636 +}
2637 +
2638 +static int
2639 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2640 +{
2641 + uint coreidx, n;
2642 + void *regs;
2643 + sbconfig_t *sb;
2644 + pci_config_regs *cfg;
2645 +
2646 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2647 + return -1;
2648 + cfg = &sb_config_regs[dev];
2649 +
2650 + ASSERT(ISALIGNED(off, len));
2651 + ASSERT(ISALIGNED((uintptr)buf, len));
2652 +
2653 + /* Emulate BAR sizing */
2654 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2655 + len == 4 && *((uint32 *) buf) == ~0) {
2656 + coreidx = sb_coreidx(sbh);
2657 + if ((regs = sb_setcoreidx(sbh, dev))) {
2658 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2659 + /* Highest numbered address match register */
2660 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2661 + if (off == OFFSETOF(pci_config_regs, base[0]))
2662 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2663 +#if 0
2664 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2665 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2666 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2667 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2668 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2669 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2670 +#endif
2671 + }
2672 + sb_setcoreidx(sbh, coreidx);
2673 + return 0;
2674 + }
2675 +
2676 + if (len == 4)
2677 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2678 + else if (len == 2)
2679 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2680 + else if (len == 1)
2681 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2682 + else
2683 + return -1;
2684 +
2685 + return 0;
2686 +}
2687 +
2688 +int
2689 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2690 +{
2691 + if (bus == 0)
2692 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2693 + else
2694 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2695 +}
2696 +
2697 +int
2698 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2699 +{
2700 + if (bus == 0)
2701 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2702 + else
2703 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2704 +}
2705 +
2706 +void
2707 +sbpci_ban(uint16 core)
2708 +{
2709 + if (pci_banned < ARRAYSIZE(pci_ban))
2710 + pci_ban[pci_banned++] = core;
2711 +}
2712 +
2713 +static int
2714 +sbpci_init_pci(sb_t *sbh)
2715 +{
2716 + uint chip, chiprev, chippkg, host;
2717 + uint32 boardflags;
2718 + sbpciregs_t *pci;
2719 + sbconfig_t *sb;
2720 + uint32 val;
2721 +
2722 + chip = sb_chip(sbh);
2723 + chiprev = sb_chiprev(sbh);
2724 + chippkg = sb_chippkg(sbh);
2725 +
2726 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2727 + printf("PCI: no core\n");
2728 + pci_disabled = TRUE;
2729 + return -1;
2730 + }
2731 + sb_core_reset(sbh, 0);
2732 +
2733 + boardflags = (uint32) getintvar(NULL, "boardflags");
2734 +
2735 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2736 + pci_disabled = TRUE;
2737 +
2738 + /*
2739 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2740 + * PCI is bonded out, some boards may leave the pins
2741 + * floating.
2742 + */
2743 + if (((chip == BCM4712_DEVICE_ID) &&
2744 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2745 + (chippkg == BCM4712MID_PKG_ID))) ||
2746 + (boardflags & BFL_NOPCI))
2747 + pci_disabled = TRUE;
2748 +
2749 + /*
2750 + * If the PCI core should not be touched (disabled, not bonded
2751 + * out, or pins floating), do not even attempt to access core
2752 + * registers. Otherwise, try to determine if it is in host
2753 + * mode.
2754 + */
2755 + if (pci_disabled)
2756 + host = 0;
2757 + else
2758 + host = !BUSPROBE(val, &pci->control);
2759 +
2760 + if (!host) {
2761 + /* Disable PCI interrupts in client mode */
2762 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2763 + W_REG(&sb->sbintvec, 0);
2764 +
2765 + /* Disable the PCI bridge in client mode */
2766 + sbpci_ban(SB_PCI);
2767 + printf("PCI: Disabled\n");
2768 + } else {
2769 + /* Reset the external PCI bus and enable the clock */
2770 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2771 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2772 + OSL_DELAY(150); /* delay > 100 us */
2773 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2774 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2775 + OSL_DELAY(1); /* delay 1 us */
2776 +
2777 + /* Enable CardBusMode */
2778 + cardbus = nvram_match("cardbus", "1");
2779 + if (cardbus) {
2780 + printf("PCI: Enabling CardBus\n");
2781 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2782 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2783 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2784 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2785 + }
2786 +
2787 + /* 64 MB I/O access window */
2788 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2789 + /* 64 MB configuration access window */
2790 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2791 + /* 1 GB memory access window */
2792 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2793 +
2794 + /* Enable PCI bridge BAR0 prefetch and burst */
2795 + val = 6;
2796 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2797 +
2798 + /* Enable PCI interrupts */
2799 + W_REG(&pci->intmask, PCI_INTA);
2800 + }
2801 +
2802 + return 0;
2803 +}
2804 +
2805 +static int
2806 +sbpci_init_cores(sb_t *sbh)
2807 +{
2808 + uint chip, chiprev, chippkg, coreidx, i;
2809 + sbconfig_t *sb;
2810 + pci_config_regs *cfg;
2811 + void *regs;
2812 + char varname[8];
2813 + uint wlidx = 0;
2814 + uint16 vendor, core;
2815 + uint8 class, subclass, progif;
2816 + uint32 val;
2817 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2818 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2819 +
2820 + chip = sb_chip(sbh);
2821 + chiprev = sb_chiprev(sbh);
2822 + chippkg = sb_chippkg(sbh);
2823 + coreidx = sb_coreidx(sbh);
2824 +
2825 + /* Scan the SB bus */
2826 + bzero(sb_config_regs, sizeof(sb_config_regs));
2827 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2828 + cfg->vendor = 0xffff;
2829 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2830 + continue;
2831 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2832 +
2833 + /* Read ID register and parse vendor and core */
2834 + val = R_REG(&sb->sbidhigh);
2835 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2836 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2837 + progif = 0;
2838 +
2839 + /* Check if this core is banned */
2840 + for (i = 0; i < pci_banned; i++)
2841 + if (core == pci_ban[i])
2842 + break;
2843 + if (i < pci_banned)
2844 + continue;
2845 +
2846 + /* Known vendor translations */
2847 + switch (vendor) {
2848 + case SB_VEND_BCM:
2849 + vendor = VENDOR_BROADCOM;
2850 + break;
2851 + }
2852 +
2853 + /* Determine class based on known core codes */
2854 + switch (core) {
2855 + case SB_ILINE20:
2856 + class = PCI_CLASS_NET;
2857 + subclass = PCI_NET_ETHER;
2858 + core = BCM47XX_ILINE_ID;
2859 + break;
2860 + case SB_ILINE100:
2861 + class = PCI_CLASS_NET;
2862 + subclass = PCI_NET_ETHER;
2863 + core = BCM4610_ILINE_ID;
2864 + break;
2865 + case SB_ENET:
2866 + class = PCI_CLASS_NET;
2867 + subclass = PCI_NET_ETHER;
2868 + core = BCM47XX_ENET_ID;
2869 + break;
2870 + case SB_SDRAM:
2871 + case SB_MEMC:
2872 + class = PCI_CLASS_MEMORY;
2873 + subclass = PCI_MEMORY_RAM;
2874 + break;
2875 + case SB_PCI:
2876 +#if 0
2877 + class = PCI_CLASS_BRIDGE;
2878 + subclass = PCI_BRIDGE_PCI;
2879 + break;
2880 +#endif
2881 + case SB_MIPS:
2882 + case SB_MIPS33:
2883 + class = PCI_CLASS_CPU;
2884 + subclass = PCI_CPU_MIPS;
2885 + break;
2886 + case SB_CODEC:
2887 + class = PCI_CLASS_COMM;
2888 + subclass = PCI_COMM_MODEM;
2889 + core = BCM47XX_V90_ID;
2890 + break;
2891 + case SB_USB:
2892 + class = PCI_CLASS_SERIAL;
2893 + subclass = PCI_SERIAL_USB;
2894 + progif = 0x10; /* OHCI */
2895 + core = BCM47XX_USB_ID;
2896 + break;
2897 + case SB_USB11H:
2898 + class = PCI_CLASS_SERIAL;
2899 + subclass = PCI_SERIAL_USB;
2900 + progif = 0x10; /* OHCI */
2901 + core = BCM47XX_USBH_ID;
2902 + break;
2903 + case SB_USB11D:
2904 + class = PCI_CLASS_SERIAL;
2905 + subclass = PCI_SERIAL_USB;
2906 + core = BCM47XX_USBD_ID;
2907 + break;
2908 + case SB_IPSEC:
2909 + class = PCI_CLASS_CRYPT;
2910 + subclass = PCI_CRYPT_NETWORK;
2911 + core = BCM47XX_IPSEC_ID;
2912 + break;
2913 + case SB_ROBO:
2914 + class = PCI_CLASS_NET;
2915 + subclass = PCI_NET_OTHER;
2916 + core = BCM47XX_ROBO_ID;
2917 + break;
2918 + case SB_EXTIF:
2919 + case SB_CC:
2920 + class = PCI_CLASS_MEMORY;
2921 + subclass = PCI_MEMORY_FLASH;
2922 + break;
2923 + case SB_D11:
2924 + class = PCI_CLASS_NET;
2925 + subclass = PCI_NET_OTHER;
2926 + /* Let an nvram variable override this */
2927 + sprintf(varname, "wl%did", wlidx);
2928 + wlidx++;
2929 + if ((core = getintvar(NULL, varname)) == 0) {
2930 + if (chip == BCM4712_DEVICE_ID) {
2931 + if (chippkg == BCM4712SMALL_PKG_ID)
2932 + core = BCM4306_D11G_ID;
2933 + else
2934 + core = BCM4306_D11DUAL_ID;
2935 + } else {
2936 + /* 4310 */
2937 + core = BCM4310_D11B_ID;
2938 + }
2939 + }
2940 + break;
2941 +
2942 + default:
2943 + class = subclass = progif = 0xff;
2944 + break;
2945 + }
2946 +
2947 + /* Supported translations */
2948 + cfg->vendor = htol16(vendor);
2949 + cfg->device = htol16(core);
2950 + cfg->rev_id = chiprev;
2951 + cfg->prog_if = progif;
2952 + cfg->sub_class = subclass;
2953 + cfg->base_class = class;
2954 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2955 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
2956 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
2957 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
2958 + cfg->base[4] = 0;
2959 + cfg->base[5] = 0;
2960 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2961 + cfg->header_type = PCI_HEADER_BRIDGE;
2962 + else
2963 + cfg->header_type = PCI_HEADER_NORMAL;
2964 + /* Save core interrupt flag */
2965 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2966 + /* Default to MIPS shared interrupt 0 */
2967 + cfg->int_line = 0;
2968 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2969 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2970 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2971 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2972 + val = R_REG(&sb->sbipsflag);
2973 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
2974 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
2975 + break;
2976 + }
2977 + if (cfg->int_line > 4)
2978 + cfg->int_line = 0;
2979 + }
2980 + /* Emulated core */
2981 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
2982 + }
2983 +
2984 + sb_setcoreidx(sbh, coreidx);
2985 + return 0;
2986 +}
2987 +
2988 +int __init
2989 +sbpci_init(sb_t *sbh)
2990 +{
2991 + sbpci_init_pci(sbh);
2992 + sbpci_init_cores(sbh);
2993 + return 0;
2994 +}
2995 +
2996 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
2997 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
2998 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2005-12-17 01:21:12.951254500 +0100
2999 @@ -0,0 +1,2370 @@
3000 +/*
3001 + * Misc utility routines for accessing chip-specific features
3002 + * of the SiliconBackplane-based Broadcom chips.
3003 + *
3004 + * Copyright 2005, Broadcom Corporation
3005 + * All Rights Reserved.
3006 + *
3007 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3008 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3009 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3010 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3011 + * $Id$
3012 + */
3013 +
3014 +#include <typedefs.h>
3015 +#include <osl.h>
3016 +#include <sbutils.h>
3017 +#include <bcmutils.h>
3018 +#include <bcmdevs.h>
3019 +#include <sbconfig.h>
3020 +#include <sbchipc.h>
3021 +#include <sbpci.h>
3022 +#include <pcicfg.h>
3023 +#include <sbextif.h>
3024 +#include <bcmsrom.h>
3025 +
3026 +/* debug/trace */
3027 +#define SB_ERROR(args)
3028 +
3029 +
3030 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3031 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3032 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3033 +
3034 +/* misc sb info needed by some of the routines */
3035 +typedef struct sb_info {
3036 +
3037 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3038 +
3039 + void *osh; /* osl os handle */
3040 + void *sdh; /* bcmsdh handle */
3041 +
3042 + void *curmap; /* current regs va */
3043 + void *regs[SB_MAXCORES]; /* other regs va */
3044 +
3045 + uint curidx; /* current core index */
3046 + uint dev_coreid; /* the core provides driver functions */
3047 +
3048 + uint gpioidx; /* gpio control core index */
3049 + uint gpioid; /* gpio control coretype */
3050 +
3051 + uint numcores; /* # discovered cores */
3052 + uint coreid[SB_MAXCORES]; /* id of each core */
3053 +
3054 + void *intr_arg; /* interrupt callback function arg */
3055 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3056 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3057 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3058 +
3059 +} sb_info_t;
3060 +
3061 +/* local prototypes */
3062 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3063 + uint bustype, void *sdh, char **vars, int *varsz);
3064 +static void BCMINIT(sb_scan)(sb_info_t *si);
3065 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3066 +static uint _sb_coreidx(sb_info_t *si);
3067 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3068 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3069 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3070 +static int sb_pci_fixcfg(sb_info_t *si);
3071 +
3072 +/* delay needed between the mdio control/ mdiodata register data access */
3073 +#define PR28829_DELAY() OSL_DELAY(10)
3074 +
3075 +
3076 +/* global variable to indicate reservation/release of gpio's*/
3077 +static uint32 sb_gpioreservation = 0;
3078 +
3079 +#define SB_INFO(sbh) (sb_info_t*)sbh
3080 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3081 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3082 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3083 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3084 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3085 +#define BADIDX (SB_MAXCORES+1)
3086 +#define NOREV -1
3087 +
3088 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3089 +
3090 +/* sonicsrev */
3091 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3092 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3093 +
3094 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3095 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3096 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3097 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3098 +
3099 +/*
3100 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3101 + * after core switching to avoid invalid register accesss inside ISR.
3102 + */
3103 +#define INTR_OFF(si, intr_val) \
3104 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3105 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3106 +#define INTR_RESTORE(si, intr_val) \
3107 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3108 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3109 +
3110 +/* dynamic clock control defines */
3111 +#define LPOMINFREQ 25000 /* low power oscillator min */
3112 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3113 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3114 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3115 +#define PCIMINFREQ 25000000 /* 25 MHz */
3116 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3117 +
3118 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3119 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3120 +
3121 +#define MIN_DUMPBUFLEN 32 /* debug */
3122 +
3123 +/* GPIO Based LED powersave defines */
3124 +#define DEFAULT_GPIO_ONTIME 10
3125 +#define DEFAULT_GPIO_OFFTIME 90
3126 +
3127 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3128 +
3129 +static uint32
3130 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3131 +{
3132 + uint32 val = R_REG(sbr);
3133 +
3134 + return (val);
3135 +}
3136 +
3137 +static void
3138 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3139 +{
3140 + W_REG(sbr, v);
3141 +}
3142 +
3143 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3144 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3145 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3146 +
3147 +/* global kernel resource */
3148 +static sb_info_t ksi;
3149 +
3150 +/* generic kernel variant of sb_attach() */
3151 +sb_t *
3152 +BCMINITFN(sb_kattach)()
3153 +{
3154 + uint32 *regs;
3155 +
3156 + if (ksi.curmap == NULL) {
3157 + uint32 cid;
3158 +
3159 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3160 + cid = R_REG((uint32 *)regs);
3161 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3162 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3163 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3164 + uint32 *scc, val;
3165 +
3166 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3167 + val = R_REG(scc);
3168 + SB_ERROR((" initial scc = 0x%x\n", val));
3169 + val |= SCC_SS_XTAL;
3170 + W_REG(scc, val);
3171 + }
3172 +
3173 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3174 + SB_BUS, NULL, NULL, NULL) == NULL) {
3175 + return NULL;
3176 + }
3177 + }
3178 +
3179 + return (sb_t *)&ksi;
3180 +}
3181 +#endif
3182 +
3183 +static sb_info_t *
3184 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3185 + uint bustype, void *sdh, char **vars, int *varsz)
3186 +{
3187 + uint origidx;
3188 + chipcregs_t *cc;
3189 + sbconfig_t *sb;
3190 + uint32 w;
3191 +
3192 + ASSERT(GOODREGS(regs));
3193 +
3194 + bzero((uchar*)si, sizeof (sb_info_t));
3195 +
3196 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3197 +
3198 + si->osh = osh;
3199 + si->curmap = regs;
3200 + si->sdh = sdh;
3201 +
3202 + /* check to see if we are a sb core mimic'ing a pci core */
3203 + if (bustype == PCI_BUS) {
3204 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3205 + bustype = SB_BUS;
3206 + else
3207 + bustype = PCI_BUS;
3208 + }
3209 +
3210 + si->sb.bustype = bustype;
3211 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3212 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3213 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3214 + return NULL;
3215 + }
3216 +
3217 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3218 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3219 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3220 +
3221 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3222 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3223 + if (!GOODCOREADDR(w))
3224 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3225 + }
3226 +
3227 + /* initialize current core index value */
3228 + si->curidx = _sb_coreidx(si);
3229 +
3230 + if (si->curidx == BADIDX) {
3231 + SB_ERROR(("sb_doattach: bad core index\n"));
3232 + return NULL;
3233 + }
3234 +
3235 + /* get sonics backplane revision */
3236 + sb = REGS2SB(si->curmap);
3237 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3238 +
3239 + /* keep and reuse the initial register mapping */
3240 + origidx = si->curidx;
3241 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3242 + si->regs[origidx] = regs;
3243 +
3244 + /* is core-0 a chipcommon core? */
3245 + si->numcores = 1;
3246 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3247 + if (sb_coreid(&si->sb) != SB_CC)
3248 + cc = NULL;
3249 +
3250 + /* determine chip id and rev */
3251 + if (cc) {
3252 + /* chip common core found! */
3253 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3254 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3255 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3256 + } else {
3257 + /* no chip common core -- must convert device id to chip id */
3258 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3259 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3260 + sb_setcoreidx(&si->sb, origidx);
3261 + return NULL;
3262 + }
3263 + }
3264 +
3265 + /* get chipcommon rev */
3266 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3267 +
3268 + /* determine numcores */
3269 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3270 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3271 + else
3272 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3273 +
3274 + /* return to original core */
3275 + sb_setcoreidx(&si->sb, origidx);
3276 +
3277 + /* sanity checks */
3278 + ASSERT(si->sb.chip);
3279 +
3280 + /* scan for cores */
3281 + BCMINIT(sb_scan)(si);
3282 +
3283 + /* fixup necessary chip/core configurations */
3284 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3285 + if (sb_pci_fixcfg(si)) {
3286 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3287 + return NULL;
3288 + }
3289 + }
3290 +
3291 + /* srom_var_init() depends on sb_scan() info */
3292 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3293 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3294 + return (NULL);
3295 + }
3296 +
3297 + if (cc == NULL) {
3298 + /*
3299 + * The chip revision number is hardwired into all
3300 + * of the pci function config rev fields and is
3301 + * independent from the individual core revision numbers.
3302 + * For example, the "A0" silicon of each chip is chip rev 0.
3303 + */
3304 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3305 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3306 + si->sb.chiprev = w & 0xff;
3307 + } else
3308 + si->sb.chiprev = 0;
3309 + }
3310 +
3311 + /* gpio control core is required */
3312 + if (!GOODIDX(si->gpioidx)) {
3313 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3314 + return NULL;
3315 + }
3316 +
3317 + /* get boardtype and boardrev */
3318 + switch (BUSTYPE(si->sb.bustype)) {
3319 + case PCI_BUS:
3320 + /* do a pci config read to get subsystem id and subvendor id */
3321 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3322 + si->sb.boardvendor = w & 0xffff;
3323 + si->sb.boardtype = (w >> 16) & 0xffff;
3324 + break;
3325 +
3326 + case SB_BUS:
3327 + case JTAG_BUS:
3328 + si->sb.boardvendor = VENDOR_BROADCOM;
3329 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3330 + si->sb.boardtype = 0xffff;
3331 + break;
3332 + }
3333 +
3334 + if (si->sb.boardtype == 0) {
3335 + SB_ERROR(("sb_doattach: unknown board type\n"));
3336 + ASSERT(si->sb.boardtype);
3337 + }
3338 +
3339 + /* setup the GPIO based LED powersave register */
3340 + if (si->sb.ccrev >= 16) {
3341 + w = getintvar(*vars, "gpiotimerval");
3342 + if (!w)
3343 + w = DEFAULT_GPIOTIMERVAL;
3344 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3345 + }
3346 +
3347 +
3348 + return (si);
3349 +}
3350 +
3351 +uint
3352 +sb_coreid(sb_t *sbh)
3353 +{
3354 + sb_info_t *si;
3355 + sbconfig_t *sb;
3356 +
3357 + si = SB_INFO(sbh);
3358 + sb = REGS2SB(si->curmap);
3359 +
3360 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3361 +}
3362 +
3363 +uint
3364 +sb_coreidx(sb_t *sbh)
3365 +{
3366 + sb_info_t *si;
3367 +
3368 + si = SB_INFO(sbh);
3369 + return (si->curidx);
3370 +}
3371 +
3372 +/* return current index of core */
3373 +static uint
3374 +_sb_coreidx(sb_info_t *si)
3375 +{
3376 + sbconfig_t *sb;
3377 + uint32 sbaddr = 0;
3378 +
3379 + ASSERT(si);
3380 +
3381 + switch (BUSTYPE(si->sb.bustype)) {
3382 + case SB_BUS:
3383 + sb = REGS2SB(si->curmap);
3384 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3385 + break;
3386 +
3387 + case PCI_BUS:
3388 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3389 + break;
3390 +
3391 +#ifdef BCMJTAG
3392 + case JTAG_BUS:
3393 + sbaddr = (uint32)si->curmap;
3394 + break;
3395 +#endif /* BCMJTAG */
3396 +
3397 + default:
3398 + ASSERT(0);
3399 + }
3400 +
3401 + if (!GOODCOREADDR(sbaddr))
3402 + return BADIDX;
3403 +
3404 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3405 +}
3406 +
3407 +uint
3408 +sb_corevendor(sb_t *sbh)
3409 +{
3410 + sb_info_t *si;
3411 + sbconfig_t *sb;
3412 +
3413 + si = SB_INFO(sbh);
3414 + sb = REGS2SB(si->curmap);
3415 +
3416 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3417 +}
3418 +
3419 +uint
3420 +sb_corerev(sb_t *sbh)
3421 +{
3422 + sb_info_t *si;
3423 + sbconfig_t *sb;
3424 + uint sbidh;
3425 +
3426 + si = SB_INFO(sbh);
3427 + sb = REGS2SB(si->curmap);
3428 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3429 +
3430 + return (SBCOREREV(sbidh));
3431 +}
3432 +
3433 +void *
3434 +sb_osh(sb_t *sbh)
3435 +{
3436 + sb_info_t *si;
3437 +
3438 + si = SB_INFO(sbh);
3439 + return si->osh;
3440 +}
3441 +
3442 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3443 +
3444 +/* set/clear sbtmstatelow core-specific flags */
3445 +uint32
3446 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3447 +{
3448 + sb_info_t *si;
3449 + sbconfig_t *sb;
3450 + uint32 w;
3451 +
3452 + si = SB_INFO(sbh);
3453 + sb = REGS2SB(si->curmap);
3454 +
3455 + ASSERT((val & ~mask) == 0);
3456 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3457 +
3458 + /* mask and set */
3459 + if (mask || val) {
3460 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3461 + W_SBREG(si, &sb->sbtmstatelow, w);
3462 + }
3463 +
3464 + /* return the new value */
3465 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3466 +}
3467 +
3468 +/* set/clear sbtmstatehigh core-specific flags */
3469 +uint32
3470 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3471 +{
3472 + sb_info_t *si;
3473 + sbconfig_t *sb;
3474 + uint32 w;
3475 +
3476 + si = SB_INFO(sbh);
3477 + sb = REGS2SB(si->curmap);
3478 +
3479 + ASSERT((val & ~mask) == 0);
3480 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3481 +
3482 + /* mask and set */
3483 + if (mask || val) {
3484 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3485 + W_SBREG(si, &sb->sbtmstatehigh, w);
3486 + }
3487 +
3488 + /* return the new value */
3489 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3490 +}
3491 +
3492 +/* caller needs to take care of core-specific bist hazards */
3493 +int
3494 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3495 +{
3496 + uint32 sblo;
3497 + uint coreidx;
3498 + sb_info_t *si;
3499 + int result = 0;
3500 +
3501 + si = SB_INFO(sbh);
3502 +
3503 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3504 + if (!GOODIDX(coreidx))
3505 + result = BCME_ERROR;
3506 + else {
3507 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3508 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3509 +
3510 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3511 +
3512 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3513 + result = BCME_ERROR;
3514 +
3515 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3516 + }
3517 +
3518 + return result;
3519 +}
3520 +
3521 +bool
3522 +sb_iscoreup(sb_t *sbh)
3523 +{
3524 + sb_info_t *si;
3525 + sbconfig_t *sb;
3526 +
3527 + si = SB_INFO(sbh);
3528 + sb = REGS2SB(si->curmap);
3529 +
3530 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3531 +}
3532 +
3533 +/*
3534 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3535 + * switch back to the original core, and return the new value.
3536 + */
3537 +static uint
3538 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3539 +{
3540 + uint origidx;
3541 + uint32 *r;
3542 + uint w;
3543 + uint intr_val = 0;
3544 +
3545 + ASSERT(GOODIDX(coreidx));
3546 + ASSERT(regoff < SB_CORE_SIZE);
3547 + ASSERT((val & ~mask) == 0);
3548 +
3549 + INTR_OFF(si, intr_val);
3550 +
3551 + /* save current core index */
3552 + origidx = sb_coreidx(&si->sb);
3553 +
3554 + /* switch core */
3555 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3556 +
3557 + /* mask and set */
3558 + if (mask || val) {
3559 + if (regoff >= SBCONFIGOFF) {
3560 + w = (R_SBREG(si, r) & ~mask) | val;
3561 + W_SBREG(si, r, w);
3562 + } else {
3563 + w = (R_REG(r) & ~mask) | val;
3564 + W_REG(r, w);
3565 + }
3566 + }
3567 +
3568 + /* readback */
3569 + if (regoff >= SBCONFIGOFF)
3570 + w = R_SBREG(si, r);
3571 + else
3572 + w = R_REG(r);
3573 +
3574 + /* restore core index */
3575 + if (origidx != coreidx)
3576 + sb_setcoreidx(&si->sb, origidx);
3577 +
3578 + INTR_RESTORE(si, intr_val);
3579 + return (w);
3580 +}
3581 +
3582 +#define DWORD_ALIGN(x) (x & ~(0x03))
3583 +#define BYTE_POS(x) (x & 0x3)
3584 +#define WORD_POS(x) (x & 0x1)
3585 +
3586 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3587 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3588 +
3589 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3590 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3591 +
3592 +#define read_pci_cfg_byte(a) \
3593 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3594 +
3595 +#define read_pci_cfg_write(a) \
3596 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3597 +
3598 +
3599 +/* scan the sb enumerated space to identify all cores */
3600 +static void
3601 +BCMINITFN(sb_scan)(sb_info_t *si)
3602 +{
3603 + uint origidx;
3604 + uint i;
3605 + bool pci;
3606 + uint pciidx;
3607 + uint pcirev;
3608 +
3609 +
3610 +
3611 + /* numcores should already be set */
3612 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3613 +
3614 + /* save current core index */
3615 + origidx = sb_coreidx(&si->sb);
3616 +
3617 + si->sb.buscorerev = NOREV;
3618 + si->sb.buscoreidx = BADIDX;
3619 +
3620 + si->gpioidx = BADIDX;
3621 +
3622 + pci = FALSE;
3623 + pcirev = NOREV;
3624 + pciidx = BADIDX;
3625 +
3626 + for (i = 0; i < si->numcores; i++) {
3627 + sb_setcoreidx(&si->sb, i);
3628 + si->coreid[i] = sb_coreid(&si->sb);
3629 +
3630 + if (si->coreid[i] == SB_PCI) {
3631 + pciidx = i;
3632 + pcirev = sb_corerev(&si->sb);
3633 + pci = TRUE;
3634 + }
3635 + }
3636 + if (pci) {
3637 + si->sb.buscoretype = SB_PCI;
3638 + si->sb.buscorerev = pcirev;
3639 + si->sb.buscoreidx = pciidx;
3640 + }
3641 +
3642 + /*
3643 + * Find the gpio "controlling core" type and index.
3644 + * Precedence:
3645 + * - if there's a chip common core - use that
3646 + * - else if there's a pci core (rev >= 2) - use that
3647 + * - else there had better be an extif core (4710 only)
3648 + */
3649 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3650 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3651 + si->gpioid = SB_CC;
3652 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3653 + si->gpioidx = si->sb.buscoreidx;
3654 + si->gpioid = SB_PCI;
3655 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3656 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3657 + si->gpioid = SB_EXTIF;
3658 + } else
3659 + ASSERT(si->gpioidx != BADIDX);
3660 +
3661 + /* return to original core index */
3662 + sb_setcoreidx(&si->sb, origidx);
3663 +}
3664 +
3665 +/* may be called with core in reset */
3666 +void
3667 +sb_detach(sb_t *sbh)
3668 +{
3669 + sb_info_t *si;
3670 + uint idx;
3671 +
3672 + si = SB_INFO(sbh);
3673 +
3674 + if (si == NULL)
3675 + return;
3676 +
3677 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3678 + for (idx = 0; idx < SB_MAXCORES; idx++)
3679 + if (si->regs[idx]) {
3680 + REG_UNMAP(si->regs[idx]);
3681 + si->regs[idx] = NULL;
3682 + }
3683 +
3684 + if (si != &ksi)
3685 + MFREE(si->osh, si, sizeof (sb_info_t));
3686 +}
3687 +
3688 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3689 +static uint
3690 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3691 +{
3692 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3693 + return (BCM4710_DEVICE_ID);
3694 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3695 + return (BCM4402_DEVICE_ID);
3696 + if (pcidev == BCM4401_ENET_ID)
3697 + return (BCM4402_DEVICE_ID);
3698 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3699 + return (BCM4307_DEVICE_ID);
3700 + if (pcidev == BCM4301_DEVICE_ID)
3701 + return (BCM4301_DEVICE_ID);
3702 +
3703 + return (0);
3704 +}
3705 +
3706 +/* convert chip number to number of i/o cores */
3707 +static uint
3708 +BCMINITFN(sb_chip2numcores)(uint chip)
3709 +{
3710 + if (chip == BCM4710_DEVICE_ID)
3711 + return (9);
3712 + if (chip == BCM4402_DEVICE_ID)
3713 + return (3);
3714 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3715 + return (5);
3716 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3717 + return (6);
3718 + if (chip == BCM4704_DEVICE_ID)
3719 + return (9);
3720 + if (chip == BCM5365_DEVICE_ID)
3721 + return (7);
3722 +
3723 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3724 + ASSERT(0);
3725 + return (1);
3726 +}
3727 +
3728 +/* return index of coreid or BADIDX if not found */
3729 +static uint
3730 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3731 +{
3732 + uint found;
3733 + uint i;
3734 +
3735 + found = 0;
3736 +
3737 + for (i = 0; i < si->numcores; i++)
3738 + if (si->coreid[i] == coreid) {
3739 + if (found == coreunit)
3740 + return (i);
3741 + found++;
3742 + }
3743 +
3744 + return (BADIDX);
3745 +}
3746 +
3747 +/*
3748 + * this function changes logical "focus" to the indiciated core,
3749 + * must be called with interrupt off.
3750 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3751 + */
3752 +void*
3753 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3754 +{
3755 + sb_info_t *si;
3756 + uint32 sbaddr;
3757 +
3758 + si = SB_INFO(sbh);
3759 +
3760 + if (coreidx >= si->numcores)
3761 + return (NULL);
3762 +
3763 + /*
3764 + * If the user has provided an interrupt mask enabled function,
3765 + * then assert interrupts are disabled before switching the core.
3766 + */
3767 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3768 +
3769 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3770 +
3771 + switch (BUSTYPE(si->sb.bustype)) {
3772 + case SB_BUS:
3773 + /* map new one */
3774 + if (!si->regs[coreidx]) {
3775 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3776 + ASSERT(GOODREGS(si->regs[coreidx]));
3777 + }
3778 + si->curmap = si->regs[coreidx];
3779 + break;
3780 +
3781 + case PCI_BUS:
3782 + /* point bar0 window */
3783 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3784 + break;
3785 +
3786 +#ifdef BCMJTAG
3787 + case JTAG_BUS:
3788 + /* map new one */
3789 + if (!si->regs[coreidx]) {
3790 + si->regs[coreidx] = (void *)sbaddr;
3791 + ASSERT(GOODREGS(si->regs[coreidx]));
3792 + }
3793 + si->curmap = si->regs[coreidx];
3794 + break;
3795 +#endif /* BCMJTAG */
3796 + }
3797 +
3798 + si->curidx = coreidx;
3799 +
3800 + return (si->curmap);
3801 +}
3802 +
3803 +/*
3804 + * this function changes logical "focus" to the indiciated core,
3805 + * must be called with interrupt off.
3806 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3807 + */
3808 +void*
3809 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3810 +{
3811 + sb_info_t *si;
3812 + uint idx;
3813 +
3814 + si = SB_INFO(sbh);
3815 + idx = sb_findcoreidx(si, coreid, coreunit);
3816 + if (!GOODIDX(idx))
3817 + return (NULL);
3818 +
3819 + return (sb_setcoreidx(sbh, idx));
3820 +}
3821 +
3822 +/* return chip number */
3823 +uint
3824 +BCMINITFN(sb_chip)(sb_t *sbh)
3825 +{
3826 + sb_info_t *si;
3827 +
3828 + si = SB_INFO(sbh);
3829 + return (si->sb.chip);
3830 +}
3831 +
3832 +/* return chip revision number */
3833 +uint
3834 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3835 +{
3836 + sb_info_t *si;
3837 +
3838 + si = SB_INFO(sbh);
3839 + return (si->sb.chiprev);
3840 +}
3841 +
3842 +/* return chip common revision number */
3843 +uint
3844 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3845 +{
3846 + sb_info_t *si;
3847 +
3848 + si = SB_INFO(sbh);
3849 + return (si->sb.ccrev);
3850 +}
3851 +
3852 +/* return chip package option */
3853 +uint
3854 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3855 +{
3856 + sb_info_t *si;
3857 +
3858 + si = SB_INFO(sbh);
3859 + return (si->sb.chippkg);
3860 +}
3861 +
3862 +/* return PCI core rev. */
3863 +uint
3864 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3865 +{
3866 + sb_info_t *si;
3867 +
3868 + si = SB_INFO(sbh);
3869 + return (si->sb.buscorerev);
3870 +}
3871 +
3872 +bool
3873 +BCMINITFN(sb_war16165)(sb_t *sbh)
3874 +{
3875 + sb_info_t *si;
3876 +
3877 + si = SB_INFO(sbh);
3878 +
3879 + return (PCI(si) && (si->sb.buscorerev <= 10));
3880 +}
3881 +
3882 +/* return board vendor id */
3883 +uint
3884 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3885 +{
3886 + sb_info_t *si;
3887 +
3888 + si = SB_INFO(sbh);
3889 + return (si->sb.boardvendor);
3890 +}
3891 +
3892 +/* return boardtype */
3893 +uint
3894 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3895 +{
3896 + sb_info_t *si;
3897 + char *var;
3898 +
3899 + si = SB_INFO(sbh);
3900 +
3901 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3902 + /* boardtype format is a hex string */
3903 + si->sb.boardtype = getintvar(NULL, "boardtype");
3904 +
3905 + /* backward compatibility for older boardtype string format */
3906 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3907 + if (!strcmp(var, "bcm94710dev"))
3908 + si->sb.boardtype = BCM94710D_BOARD;
3909 + else if (!strcmp(var, "bcm94710ap"))
3910 + si->sb.boardtype = BCM94710AP_BOARD;
3911 + else if (!strcmp(var, "bu4710"))
3912 + si->sb.boardtype = BU4710_BOARD;
3913 + else if (!strcmp(var, "bcm94702mn"))
3914 + si->sb.boardtype = BCM94702MN_BOARD;
3915 + else if (!strcmp(var, "bcm94710r1"))
3916 + si->sb.boardtype = BCM94710R1_BOARD;
3917 + else if (!strcmp(var, "bcm94710r4"))
3918 + si->sb.boardtype = BCM94710R4_BOARD;
3919 + else if (!strcmp(var, "bcm94702cpci"))
3920 + si->sb.boardtype = BCM94702CPCI_BOARD;
3921 + else if (!strcmp(var, "bcm95380_rr"))
3922 + si->sb.boardtype = BCM95380RR_BOARD;
3923 + }
3924 + }
3925 +
3926 + return (si->sb.boardtype);
3927 +}
3928 +
3929 +/* return bus type of sbh device */
3930 +uint
3931 +sb_bus(sb_t *sbh)
3932 +{
3933 + sb_info_t *si;
3934 +
3935 + si = SB_INFO(sbh);
3936 + return (si->sb.bustype);
3937 +}
3938 +
3939 +/* return bus core type */
3940 +uint
3941 +sb_buscoretype(sb_t *sbh)
3942 +{
3943 + sb_info_t *si;
3944 +
3945 + si = SB_INFO(sbh);
3946 +
3947 + return (si->sb.buscoretype);
3948 +}
3949 +
3950 +/* return bus core revision */
3951 +uint
3952 +sb_buscorerev(sb_t *sbh)
3953 +{
3954 + sb_info_t *si;
3955 + si = SB_INFO(sbh);
3956 +
3957 + return (si->sb.buscorerev);
3958 +}
3959 +
3960 +/* return list of found cores */
3961 +uint
3962 +sb_corelist(sb_t *sbh, uint coreid[])
3963 +{
3964 + sb_info_t *si;
3965 +
3966 + si = SB_INFO(sbh);
3967 +
3968 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
3969 + return (si->numcores);
3970 +}
3971 +
3972 +/* return current register mapping */
3973 +void *
3974 +sb_coreregs(sb_t *sbh)
3975 +{
3976 + sb_info_t *si;
3977 +
3978 + si = SB_INFO(sbh);
3979 + ASSERT(GOODREGS(si->curmap));
3980 +
3981 + return (si->curmap);
3982 +}
3983 +
3984 +
3985 +/* do buffered registers update */
3986 +void
3987 +sb_commit(sb_t *sbh)
3988 +{
3989 + sb_info_t *si;
3990 + uint origidx;
3991 + uint intr_val = 0;
3992 +
3993 + si = SB_INFO(sbh);
3994 +
3995 + origidx = si->curidx;
3996 + ASSERT(GOODIDX(origidx));
3997 +
3998 + INTR_OFF(si, intr_val);
3999 +
4000 + /* switch over to chipcommon core if there is one, else use pci */
4001 + if (si->sb.ccrev != NOREV) {
4002 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4003 +
4004 + /* do the buffer registers update */
4005 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4006 + W_REG(&ccregs->broadcastdata, 0x0);
4007 + } else if (PCI(si)) {
4008 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4009 +
4010 + /* do the buffer registers update */
4011 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4012 + W_REG(&pciregs->bcastdata, 0x0);
4013 + } else
4014 + ASSERT(0);
4015 +
4016 + /* restore core index */
4017 + sb_setcoreidx(sbh, origidx);
4018 + INTR_RESTORE(si, intr_val);
4019 +}
4020 +
4021 +/* reset and re-enable a core */
4022 +void
4023 +sb_core_reset(sb_t *sbh, uint32 bits)
4024 +{
4025 + sb_info_t *si;
4026 + sbconfig_t *sb;
4027 + volatile uint32 dummy;
4028 +
4029 + si = SB_INFO(sbh);
4030 + ASSERT(GOODREGS(si->curmap));
4031 + sb = REGS2SB(si->curmap);
4032 +
4033 + /*
4034 + * Must do the disable sequence first to work for arbitrary current core state.
4035 + */
4036 + sb_core_disable(sbh, bits);
4037 +
4038 + /*
4039 + * Now do the initialization sequence.
4040 + */
4041 +
4042 + /* set reset while enabling the clock and forcing them on throughout the core */
4043 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4044 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4045 + OSL_DELAY(1);
4046 +
4047 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4048 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4049 + }
4050 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4051 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4052 + }
4053 +
4054 + /* clear reset and allow it to propagate throughout the core */
4055 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4056 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4057 + OSL_DELAY(1);
4058 +
4059 + /* leave clock enabled */
4060 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4061 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4062 + OSL_DELAY(1);
4063 +}
4064 +
4065 +void
4066 +sb_core_tofixup(sb_t *sbh)
4067 +{
4068 + sb_info_t *si;
4069 + sbconfig_t *sb;
4070 +
4071 + si = SB_INFO(sbh);
4072 +
4073 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4074 + return;
4075 +
4076 + ASSERT(GOODREGS(si->curmap));
4077 + sb = REGS2SB(si->curmap);
4078 +
4079 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4080 + SET_SBREG(si, &sb->sbimconfiglow,
4081 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4082 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4083 + } else {
4084 + if (sb_coreid(sbh) == SB_PCI) {
4085 + SET_SBREG(si, &sb->sbimconfiglow,
4086 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4087 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4088 + } else {
4089 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4090 + }
4091 + }
4092 +
4093 + sb_commit(sbh);
4094 +}
4095 +
4096 +/*
4097 + * Set the initiator timeout for the "master core".
4098 + * The master core is defined to be the core in control
4099 + * of the chip and so it issues accesses to non-memory
4100 + * locations (Because of dma *any* core can access memeory).
4101 + *
4102 + * The routine uses the bus to decide who is the master:
4103 + * SB_BUS => mips
4104 + * JTAG_BUS => chipc
4105 + * PCI_BUS => pci
4106 + *
4107 + * This routine exists so callers can disable initiator
4108 + * timeouts so accesses to very slow devices like otp
4109 + * won't cause an abort. The routine allows arbitrary
4110 + * settings of the service and request timeouts, though.
4111 + *
4112 + * Returns the timeout state before changing it or -1
4113 + * on error.
4114 + */
4115 +
4116 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4117 +
4118 +uint32
4119 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4120 +{
4121 + sb_info_t *si;
4122 + uint origidx, idx;
4123 + uint intr_val = 0;
4124 + uint32 tmp, ret = 0xffffffff;
4125 + sbconfig_t *sb;
4126 +
4127 + si = SB_INFO(sbh);
4128 +
4129 + if ((to & ~TO_MASK) != 0)
4130 + return ret;
4131 +
4132 + /* Figure out the master core */
4133 + idx = BADIDX;
4134 + switch (BUSTYPE(si->sb.bustype)) {
4135 + case PCI_BUS:
4136 + idx = si->sb.buscoreidx;
4137 + break;
4138 + case JTAG_BUS:
4139 + idx = SB_CC_IDX;
4140 + break;
4141 + case SB_BUS:
4142 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4143 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4144 + break;
4145 + default:
4146 + ASSERT(0);
4147 + }
4148 + if (idx == BADIDX)
4149 + return ret;
4150 +
4151 + INTR_OFF(si, intr_val);
4152 + origidx = sb_coreidx(sbh);
4153 +
4154 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4155 +
4156 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4157 + ret = tmp & TO_MASK;
4158 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4159 +
4160 + sb_commit(sbh);
4161 + sb_setcoreidx(sbh, origidx);
4162 + INTR_RESTORE(si, intr_val);
4163 + return ret;
4164 +}
4165 +
4166 +void
4167 +sb_core_disable(sb_t *sbh, uint32 bits)
4168 +{
4169 + sb_info_t *si;
4170 + volatile uint32 dummy;
4171 + uint32 rej;
4172 + sbconfig_t *sb;
4173 +
4174 + si = SB_INFO(sbh);
4175 +
4176 + ASSERT(GOODREGS(si->curmap));
4177 + sb = REGS2SB(si->curmap);
4178 +
4179 + /* if core is already in reset, just return */
4180 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4181 + return;
4182 +
4183 + /* reject value changed between sonics 2.2 and 2.3 */
4184 + if (si->sb.sonicsrev == SONICS_2_2)
4185 + rej = (1 << SBTML_REJ_SHIFT);
4186 + else
4187 + rej = (2 << SBTML_REJ_SHIFT);
4188 +
4189 + /* if clocks are not enabled, put into reset and return */
4190 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4191 + goto disable;
4192 +
4193 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4194 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4195 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4196 + OSL_DELAY(1);
4197 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4198 +
4199 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4200 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4201 + dummy = R_SBREG(si, &sb->sbimstate);
4202 + OSL_DELAY(1);
4203 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4204 + }
4205 +
4206 + /* set reset and reject while enabling the clocks */
4207 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4208 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4209 + OSL_DELAY(10);
4210 +
4211 + /* don't forget to clear the initiator reject bit */
4212 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4213 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4214 +
4215 +disable:
4216 + /* leave reset and reject asserted */
4217 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4218 + OSL_DELAY(1);
4219 +}
4220 +
4221 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4222 +void
4223 +sb_watchdog(sb_t *sbh, uint ticks)
4224 +{
4225 + sb_info_t *si = SB_INFO(sbh);
4226 +
4227 + /* instant NMI */
4228 + switch (si->gpioid) {
4229 + case SB_CC:
4230 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4231 + break;
4232 + case SB_EXTIF:
4233 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4234 + break;
4235 + }
4236 +}
4237 +
4238 +
4239 +/*
4240 + * Configure the pci core for pci client (NIC) action
4241 + * coremask is the bitvec of cores by index to be enabled.
4242 + */
4243 +void
4244 +sb_pci_setup(sb_t *sbh, uint coremask)
4245 +{
4246 + sb_info_t *si;
4247 + sbconfig_t *sb;
4248 + sbpciregs_t *pciregs;
4249 + uint32 sbflag;
4250 + uint32 w;
4251 + uint idx;
4252 +
4253 + si = SB_INFO(sbh);
4254 +
4255 + /* if not pci bus, we're done */
4256 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4257 + return;
4258 +
4259 + ASSERT(PCI(si));
4260 + ASSERT(si->sb.buscoreidx != BADIDX);
4261 +
4262 + /* get current core index */
4263 + idx = si->curidx;
4264 +
4265 + /* we interrupt on this backplane flag number */
4266 + ASSERT(GOODREGS(si->curmap));
4267 + sb = REGS2SB(si->curmap);
4268 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4269 +
4270 + /* switch over to pci core */
4271 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4272 + sb = REGS2SB(pciregs);
4273 +
4274 + /*
4275 + * Enable sb->pci interrupts. Assume
4276 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4277 + */
4278 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4279 + /* pci config write to set this core bit in PCIIntMask */
4280 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4281 + w |= (coremask << PCI_SBIM_SHIFT);
4282 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4283 + } else {
4284 + /* set sbintvec bit for our flag number */
4285 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4286 + }
4287 +
4288 + if (PCI(si)) {
4289 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4290 + if (si->sb.buscorerev >= 11)
4291 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4292 + if (si->sb.buscorerev < 5) {
4293 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4294 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4295 + sb_commit(sbh);
4296 + }
4297 + }
4298 +
4299 + /* switch back to previous core */
4300 + sb_setcoreidx(sbh, idx);
4301 +}
4302 +
4303 +uint32
4304 +sb_base(uint32 admatch)
4305 +{
4306 + uint32 base;
4307 + uint type;
4308 +
4309 + type = admatch & SBAM_TYPE_MASK;
4310 + ASSERT(type < 3);
4311 +
4312 + base = 0;
4313 +
4314 + if (type == 0) {
4315 + base = admatch & SBAM_BASE0_MASK;
4316 + } else if (type == 1) {
4317 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4318 + base = admatch & SBAM_BASE1_MASK;
4319 + } else if (type == 2) {
4320 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4321 + base = admatch & SBAM_BASE2_MASK;
4322 + }
4323 +
4324 + return (base);
4325 +}
4326 +
4327 +uint32
4328 +sb_size(uint32 admatch)
4329 +{
4330 + uint32 size;
4331 + uint type;
4332 +
4333 + type = admatch & SBAM_TYPE_MASK;
4334 + ASSERT(type < 3);
4335 +
4336 + size = 0;
4337 +
4338 + if (type == 0) {
4339 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4340 + } else if (type == 1) {
4341 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4342 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4343 + } else if (type == 2) {
4344 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4345 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4346 + }
4347 +
4348 + return (size);
4349 +}
4350 +
4351 +/* return the core-type instantiation # of the current core */
4352 +uint
4353 +sb_coreunit(sb_t *sbh)
4354 +{
4355 + sb_info_t *si;
4356 + uint idx;
4357 + uint coreid;
4358 + uint coreunit;
4359 + uint i;
4360 +
4361 + si = SB_INFO(sbh);
4362 + coreunit = 0;
4363 +
4364 + idx = si->curidx;
4365 +
4366 + ASSERT(GOODREGS(si->curmap));
4367 + coreid = sb_coreid(sbh);
4368 +
4369 + /* count the cores of our type */
4370 + for (i = 0; i < idx; i++)
4371 + if (si->coreid[i] == coreid)
4372 + coreunit++;
4373 +
4374 + return (coreunit);
4375 +}
4376 +
4377 +static INLINE uint32
4378 +factor6(uint32 x)
4379 +{
4380 + switch (x) {
4381 + case CC_F6_2: return 2;
4382 + case CC_F6_3: return 3;
4383 + case CC_F6_4: return 4;
4384 + case CC_F6_5: return 5;
4385 + case CC_F6_6: return 6;
4386 + case CC_F6_7: return 7;
4387 + default: return 0;
4388 + }
4389 +}
4390 +
4391 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4392 +uint32
4393 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4394 +{
4395 + uint32 n1, n2, clock, m1, m2, m3, mc;
4396 +
4397 + n1 = n & CN_N1_MASK;
4398 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4399 +
4400 + if (pll_type == PLL_TYPE6) {
4401 + if (m & CC_T6_MMASK)
4402 + return CC_T6_M1;
4403 + else
4404 + return CC_T6_M0;
4405 + } else if ((pll_type == PLL_TYPE1) ||
4406 + (pll_type == PLL_TYPE3) ||
4407 + (pll_type == PLL_TYPE4) ||
4408 + (pll_type == PLL_TYPE7)) {
4409 + n1 = factor6(n1);
4410 + n2 += CC_F5_BIAS;
4411 + } else if (pll_type == PLL_TYPE2) {
4412 + n1 += CC_T2_BIAS;
4413 + n2 += CC_T2_BIAS;
4414 + ASSERT((n1 >= 2) && (n1 <= 7));
4415 + ASSERT((n2 >= 5) && (n2 <= 23));
4416 + } else if (pll_type == PLL_TYPE5) {
4417 + return (100000000);
4418 + } else
4419 + ASSERT(0);
4420 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4421 + if ((pll_type == PLL_TYPE3) ||
4422 + (pll_type == PLL_TYPE7)) {
4423 + clock = CC_CLOCK_BASE2 * n1 * n2;
4424 + }
4425 + else
4426 + clock = CC_CLOCK_BASE1 * n1 * n2;
4427 +
4428 + if (clock == 0)
4429 + return 0;
4430 +
4431 + m1 = m & CC_M1_MASK;
4432 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4433 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4434 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4435 +
4436 + if ((pll_type == PLL_TYPE1) ||
4437 + (pll_type == PLL_TYPE3) ||
4438 + (pll_type == PLL_TYPE4) ||
4439 + (pll_type == PLL_TYPE7)) {
4440 + m1 = factor6(m1);
4441 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4442 + m2 += CC_F5_BIAS;
4443 + else
4444 + m2 = factor6(m2);
4445 + m3 = factor6(m3);
4446 +
4447 + switch (mc) {
4448 + case CC_MC_BYPASS: return (clock);
4449 + case CC_MC_M1: return (clock / m1);
4450 + case CC_MC_M1M2: return (clock / (m1 * m2));
4451 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4452 + case CC_MC_M1M3: return (clock / (m1 * m3));
4453 + default: return (0);
4454 + }
4455 + } else {
4456 + ASSERT(pll_type == PLL_TYPE2);
4457 +
4458 + m1 += CC_T2_BIAS;
4459 + m2 += CC_T2M2_BIAS;
4460 + m3 += CC_T2_BIAS;
4461 + ASSERT((m1 >= 2) && (m1 <= 7));
4462 + ASSERT((m2 >= 3) && (m2 <= 10));
4463 + ASSERT((m3 >= 2) && (m3 <= 7));
4464 +
4465 + if ((mc & CC_T2MC_M1BYP) == 0)
4466 + clock /= m1;
4467 + if ((mc & CC_T2MC_M2BYP) == 0)
4468 + clock /= m2;
4469 + if ((mc & CC_T2MC_M3BYP) == 0)
4470 + clock /= m3;
4471 +
4472 + return(clock);
4473 + }
4474 +}
4475 +
4476 +/* returns the current speed the SB is running at */
4477 +uint32
4478 +sb_clock(sb_t *sbh)
4479 +{
4480 + sb_info_t *si;
4481 + extifregs_t *eir;
4482 + chipcregs_t *cc;
4483 + uint32 n, m;
4484 + uint idx;
4485 + uint32 pll_type, rate;
4486 + uint intr_val = 0;
4487 +
4488 + si = SB_INFO(sbh);
4489 + idx = si->curidx;
4490 + pll_type = PLL_TYPE1;
4491 +
4492 + INTR_OFF(si, intr_val);
4493 +
4494 + /* switch to extif or chipc core */
4495 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4496 + n = R_REG(&eir->clockcontrol_n);
4497 + m = R_REG(&eir->clockcontrol_sb);
4498 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4499 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4500 + n = R_REG(&cc->clockcontrol_n);
4501 + if (pll_type == PLL_TYPE6)
4502 + m = R_REG(&cc->clockcontrol_mips);
4503 + else if (pll_type == PLL_TYPE3)
4504 + {
4505 + // Added by Chen-I for 5365
4506 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4507 + m = R_REG(&cc->clockcontrol_sb);
4508 + else
4509 + m = R_REG(&cc->clockcontrol_m2);
4510 + }
4511 + else
4512 + m = R_REG(&cc->clockcontrol_sb);
4513 + } else {
4514 + INTR_RESTORE(si, intr_val);
4515 + return 0;
4516 + }
4517 +
4518 + // Added by Chen-I for 5365
4519 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4520 + {
4521 + rate = 100000000;
4522 + }
4523 + else
4524 + {
4525 + /* calculate rate */
4526 + rate = sb_clock_rate(pll_type, n, m);
4527 + if (pll_type == PLL_TYPE3)
4528 + rate = rate / 2;
4529 + }
4530 +
4531 + /* switch back to previous core */
4532 + sb_setcoreidx(sbh, idx);
4533 +
4534 + INTR_RESTORE(si, intr_val);
4535 +
4536 + return rate;
4537 +}
4538 +
4539 +/* change logical "focus" to the gpio core for optimized access */
4540 +void*
4541 +sb_gpiosetcore(sb_t *sbh)
4542 +{
4543 + sb_info_t *si;
4544 +
4545 + si = SB_INFO(sbh);
4546 +
4547 + return (sb_setcoreidx(sbh, si->gpioidx));
4548 +}
4549 +
4550 +/* mask&set gpiocontrol bits */
4551 +uint32
4552 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4553 +{
4554 + sb_info_t *si;
4555 + uint regoff;
4556 +
4557 + si = SB_INFO(sbh);
4558 + regoff = 0;
4559 +
4560 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4561 +
4562 + /* gpios could be shared on router platforms */
4563 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4564 + mask = priority ? (sb_gpioreservation & mask) :
4565 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4566 + val &= mask;
4567 + }
4568 +
4569 + switch (si->gpioid) {
4570 + case SB_CC:
4571 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4572 + break;
4573 +
4574 + case SB_PCI:
4575 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4576 + break;
4577 +
4578 + case SB_EXTIF:
4579 + return (0);
4580 + }
4581 +
4582 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4583 +}
4584 +
4585 +/* mask&set gpio output enable bits */
4586 +uint32
4587 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4588 +{
4589 + sb_info_t *si;
4590 + uint regoff;
4591 +
4592 + si = SB_INFO(sbh);
4593 + regoff = 0;
4594 +
4595 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4596 +
4597 + /* gpios could be shared on router platforms */
4598 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4599 + mask = priority ? (sb_gpioreservation & mask) :
4600 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4601 + val &= mask;
4602 + }
4603 +
4604 + switch (si->gpioid) {
4605 + case SB_CC:
4606 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4607 + break;
4608 +
4609 + case SB_PCI:
4610 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4611 + break;
4612 +
4613 + case SB_EXTIF:
4614 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4615 + break;
4616 + }
4617 +
4618 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4619 +}
4620 +
4621 +/* mask&set gpio output bits */
4622 +uint32
4623 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4624 +{
4625 + sb_info_t *si;
4626 + uint regoff;
4627 +
4628 + si = SB_INFO(sbh);
4629 + regoff = 0;
4630 +
4631 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4632 +
4633 + /* gpios could be shared on router platforms */
4634 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4635 + mask = priority ? (sb_gpioreservation & mask) :
4636 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4637 + val &= mask;
4638 + }
4639 +
4640 + switch (si->gpioid) {
4641 + case SB_CC:
4642 + regoff = OFFSETOF(chipcregs_t, gpioout);
4643 + break;
4644 +
4645 + case SB_PCI:
4646 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4647 + break;
4648 +
4649 + case SB_EXTIF:
4650 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4651 + break;
4652 + }
4653 +
4654 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4655 +}
4656 +
4657 +/* reserve one gpio */
4658 +uint32
4659 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4660 +{
4661 + sb_info_t *si;
4662 +
4663 + si = SB_INFO(sbh);
4664 +
4665 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4666 +
4667 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4668 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4669 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4670 + return -1;
4671 + }
4672 + /* make sure only one bit is set */
4673 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4674 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4675 + return -1;
4676 + }
4677 +
4678 + /* already reserved */
4679 + if (sb_gpioreservation & gpio_bitmask)
4680 + return -1;
4681 + /* set reservation */
4682 + sb_gpioreservation |= gpio_bitmask;
4683 +
4684 + return sb_gpioreservation;
4685 +}
4686 +
4687 +/* release one gpio */
4688 +/*
4689 + * releasing the gpio doesn't change the current value on the GPIO last write value
4690 + * persists till some one overwrites it
4691 +*/
4692 +
4693 +uint32
4694 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4695 +{
4696 + sb_info_t *si;
4697 +
4698 + si = SB_INFO(sbh);
4699 +
4700 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4701 +
4702 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4703 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4704 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4705 + return -1;
4706 + }
4707 + /* make sure only one bit is set */
4708 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4709 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4710 + return -1;
4711 + }
4712 +
4713 + /* already released */
4714 + if (!(sb_gpioreservation & gpio_bitmask))
4715 + return -1;
4716 +
4717 + /* clear reservation */
4718 + sb_gpioreservation &= ~gpio_bitmask;
4719 +
4720 + return sb_gpioreservation;
4721 +}
4722 +
4723 +/* return the current gpioin register value */
4724 +uint32
4725 +sb_gpioin(sb_t *sbh)
4726 +{
4727 + sb_info_t *si;
4728 + uint regoff;
4729 +
4730 + si = SB_INFO(sbh);
4731 + regoff = 0;
4732 +
4733 + switch (si->gpioid) {
4734 + case SB_CC:
4735 + regoff = OFFSETOF(chipcregs_t, gpioin);
4736 + break;
4737 +
4738 + case SB_PCI:
4739 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4740 + break;
4741 +
4742 + case SB_EXTIF:
4743 + regoff = OFFSETOF(extifregs_t, gpioin);
4744 + break;
4745 + }
4746 +
4747 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4748 +}
4749 +
4750 +/* mask&set gpio interrupt polarity bits */
4751 +uint32
4752 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4753 +{
4754 + sb_info_t *si;
4755 + uint regoff;
4756 +
4757 + si = SB_INFO(sbh);
4758 + regoff = 0;
4759 +
4760 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4761 +
4762 + /* gpios could be shared on router platforms */
4763 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4764 + mask = priority ? (sb_gpioreservation & mask) :
4765 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4766 + val &= mask;
4767 + }
4768 +
4769 + switch (si->gpioid) {
4770 + case SB_CC:
4771 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4772 + break;
4773 +
4774 + case SB_PCI:
4775 + /* pci gpio implementation does not support interrupt polarity */
4776 + ASSERT(0);
4777 + break;
4778 +
4779 + case SB_EXTIF:
4780 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4781 + break;
4782 + }
4783 +
4784 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4785 +}
4786 +
4787 +/* mask&set gpio interrupt mask bits */
4788 +uint32
4789 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4790 +{
4791 + sb_info_t *si;
4792 + uint regoff;
4793 +
4794 + si = SB_INFO(sbh);
4795 + regoff = 0;
4796 +
4797 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4798 +
4799 + /* gpios could be shared on router platforms */
4800 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4801 + mask = priority ? (sb_gpioreservation & mask) :
4802 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4803 + val &= mask;
4804 + }
4805 +
4806 + switch (si->gpioid) {
4807 + case SB_CC:
4808 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4809 + break;
4810 +
4811 + case SB_PCI:
4812 + /* pci gpio implementation does not support interrupt mask */
4813 + ASSERT(0);
4814 + break;
4815 +
4816 + case SB_EXTIF:
4817 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4818 + break;
4819 + }
4820 +
4821 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4822 +}
4823 +
4824 +/* assign the gpio to an led */
4825 +uint32
4826 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4827 +{
4828 + sb_info_t *si;
4829 +
4830 + si = SB_INFO(sbh);
4831 + if (si->sb.ccrev < 16)
4832 + return -1;
4833 +
4834 + /* gpio led powersave reg */
4835 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4836 +}
4837 +
4838 +/* mask&set gpio timer val */
4839 +uint32
4840 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4841 +{
4842 + sb_info_t *si;
4843 + si = SB_INFO(sbh);
4844 +
4845 + if (si->sb.ccrev < 16)
4846 + return -1;
4847 +
4848 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4849 +}
4850 +
4851 +
4852 +/* return the slow clock source - LPO, XTAL, or PCI */
4853 +static uint
4854 +sb_slowclk_src(sb_info_t *si)
4855 +{
4856 + chipcregs_t *cc;
4857 +
4858 +
4859 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4860 +
4861 + if (si->sb.ccrev < 6) {
4862 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4863 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4864 + return (SCC_SS_PCI);
4865 + else
4866 + return (SCC_SS_XTAL);
4867 + } else if (si->sb.ccrev < 10) {
4868 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4869 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4870 + } else /* Insta-clock */
4871 + return (SCC_SS_XTAL);
4872 +}
4873 +
4874 +/* return the ILP (slowclock) min or max frequency */
4875 +static uint
4876 +sb_slowclk_freq(sb_info_t *si, bool max)
4877 +{
4878 + chipcregs_t *cc;
4879 + uint32 slowclk;
4880 + uint div;
4881 +
4882 +
4883 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4884 +
4885 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4886 +
4887 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4888 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4889 +
4890 + slowclk = sb_slowclk_src(si);
4891 + if (si->sb.ccrev < 6) {
4892 + if (slowclk == SCC_SS_PCI)
4893 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4894 + else
4895 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4896 + } else if (si->sb.ccrev < 10) {
4897 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4898 + if (slowclk == SCC_SS_LPO)
4899 + return (max? LPOMAXFREQ : LPOMINFREQ);
4900 + else if (slowclk == SCC_SS_XTAL)
4901 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4902 + else if (slowclk == SCC_SS_PCI)
4903 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4904 + else
4905 + ASSERT(0);
4906 + } else {
4907 + /* Chipc rev 10 is InstaClock */
4908 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4909 + div = 4 * (div + 1);
4910 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4911 + }
4912 + return (0);
4913 +}
4914 +
4915 +static void
4916 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4917 +{
4918 + chipcregs_t * cc;
4919 + uint slowmaxfreq, pll_delay, slowclk;
4920 + uint pll_on_delay, fref_sel_delay;
4921 +
4922 + pll_delay = PLL_DELAY;
4923 +
4924 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4925 + * since the xtal will also be powered down by dynamic clk control logic.
4926 + */
4927 + slowclk = sb_slowclk_src(si);
4928 + if (slowclk != SCC_SS_XTAL)
4929 + pll_delay += XTAL_ON_DELAY;
4930 +
4931 + /* Starting with 4318 it is ILP that is used for the delays */
4932 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4933 +
4934 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4935 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4936 +
4937 + cc = (chipcregs_t *)chipcregs;
4938 + W_REG(&cc->pll_on_delay, pll_on_delay);
4939 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4940 +}
4941 +
4942 +int
4943 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4944 +{
4945 + sb_info_t *si;
4946 + uint origidx;
4947 + chipcregs_t *cc;
4948 + uint intr_val = 0;
4949 + uint err = 0;
4950 +
4951 + si = SB_INFO(sbh);
4952 +
4953 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4954 + if (si->sb.ccrev < 6)
4955 + return 1;
4956 +
4957 + /* chipcommon cores rev10 are a whole new ball game */
4958 + if (si->sb.ccrev >= 10)
4959 + return 1;
4960 +
4961 + if (set && ((*div % 4) || (*div < 4)))
4962 + return 2;
4963 +
4964 + INTR_OFF(si, intr_val);
4965 + origidx = si->curidx;
4966 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4967 + ASSERT(cc != NULL);
4968 +
4969 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
4970 + err = 3;
4971 + goto done;
4972 + }
4973 +
4974 + if (set) {
4975 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
4976 + sb_clkctl_setdelay(sbh, (void *)cc);
4977 + } else
4978 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4979 +
4980 +done:
4981 + sb_setcoreidx(sbh, origidx);
4982 + INTR_RESTORE(si, intr_val);
4983 + return err;
4984 +}
4985 +
4986 +/* initialize power control delay registers */
4987 +void sb_clkctl_init(sb_t *sbh)
4988 +{
4989 + sb_info_t *si;
4990 + uint origidx;
4991 + chipcregs_t *cc;
4992 +
4993 + si = SB_INFO(sbh);
4994 +
4995 + origidx = si->curidx;
4996 +
4997 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
4998 + return;
4999 +
5000 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5001 + goto done;
5002 +
5003 + /* set all Instaclk chip ILP to 1 MHz */
5004 + if (si->sb.ccrev >= 10)
5005 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5006 +
5007 + sb_clkctl_setdelay(si, (void *)cc);
5008 +
5009 +done:
5010 + sb_setcoreidx(sbh, origidx);
5011 +}
5012 +void sb_pwrctl_init(sb_t *sbh)
5013 +{
5014 +sb_clkctl_init(sbh);
5015 +}
5016 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5017 +uint16
5018 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5019 +{
5020 + sb_info_t *si;
5021 + uint origidx;
5022 + chipcregs_t *cc;
5023 + uint slowminfreq;
5024 + uint16 fpdelay;
5025 + uint intr_val = 0;
5026 +
5027 + si = SB_INFO(sbh);
5028 + fpdelay = 0;
5029 + origidx = si->curidx;
5030 +
5031 + INTR_OFF(si, intr_val);
5032 +
5033 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5034 + goto done;
5035 +
5036 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5037 + goto done;
5038 +
5039 + slowminfreq = sb_slowclk_freq(si, FALSE);
5040 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5041 +
5042 +done:
5043 + sb_setcoreidx(sbh, origidx);
5044 + INTR_RESTORE(si, intr_val);
5045 + return (fpdelay);
5046 +}
5047 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5048 +{
5049 +return sb_clkctl_fast_pwrup_delay(sbh);
5050 +}
5051 +/* turn primary xtal and/or pll off/on */
5052 +int
5053 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5054 +{
5055 + sb_info_t *si;
5056 + uint32 in, out, outen;
5057 +
5058 + si = SB_INFO(sbh);
5059 +
5060 + switch (BUSTYPE(si->sb.bustype)) {
5061 + case PCI_BUS:
5062 +
5063 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5064 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5065 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5066 +
5067 + /*
5068 + * Avoid glitching the clock if GPRS is already using it.
5069 + * We can't actually read the state of the PLLPD so we infer it
5070 + * by the value of XTAL_PU which *is* readable via gpioin.
5071 + */
5072 + if (on && (in & PCI_CFG_GPIO_XTAL))
5073 + return (0);
5074 +
5075 + if (what & XTAL)
5076 + outen |= PCI_CFG_GPIO_XTAL;
5077 + if (what & PLL)
5078 + outen |= PCI_CFG_GPIO_PLL;
5079 +
5080 + if (on) {
5081 + /* turn primary xtal on */
5082 + if (what & XTAL) {
5083 + out |= PCI_CFG_GPIO_XTAL;
5084 + if (what & PLL)
5085 + out |= PCI_CFG_GPIO_PLL;
5086 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5087 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5088 + OSL_DELAY(XTAL_ON_DELAY);
5089 + }
5090 +
5091 + /* turn pll on */
5092 + if (what & PLL) {
5093 + out &= ~PCI_CFG_GPIO_PLL;
5094 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5095 + OSL_DELAY(2000);
5096 + }
5097 + } else {
5098 + if (what & XTAL)
5099 + out &= ~PCI_CFG_GPIO_XTAL;
5100 + if (what & PLL)
5101 + out |= PCI_CFG_GPIO_PLL;
5102 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5103 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5104 + }
5105 +
5106 + default:
5107 + return (-1);
5108 + }
5109 +
5110 + return (0);
5111 +}
5112 +
5113 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5114 +{
5115 +return sb_clkctl_xtal(sbh,what,on);
5116 +}
5117 +
5118 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5119 +/* returns true if ignore pll off is set and false if it is not */
5120 +bool
5121 +sb_clkctl_clk(sb_t *sbh, uint mode)
5122 +{
5123 + sb_info_t *si;
5124 + uint origidx;
5125 + chipcregs_t *cc;
5126 + uint32 scc;
5127 + bool forcefastclk=FALSE;
5128 + uint intr_val = 0;
5129 +
5130 + si = SB_INFO(sbh);
5131 +
5132 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5133 + if (si->sb.ccrev < 6)
5134 + return (FALSE);
5135 +
5136 + /* chipcommon cores rev10 are a whole new ball game */
5137 + if (si->sb.ccrev >= 10)
5138 + return (FALSE);
5139 +
5140 + INTR_OFF(si, intr_val);
5141 +
5142 + origidx = si->curidx;
5143 +
5144 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5145 + ASSERT(cc != NULL);
5146 +
5147 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5148 + goto done;
5149 +
5150 + switch (mode) {
5151 + case CLK_FAST: /* force fast (pll) clock */
5152 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5153 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5154 +
5155 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5156 + break;
5157 +
5158 + case CLK_DYNAMIC: /* enable dynamic clock control */
5159 + scc = R_REG(&cc->slow_clk_ctl);
5160 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5161 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5162 + scc |= SCC_XC;
5163 + W_REG(&cc->slow_clk_ctl, scc);
5164 +
5165 + /* for dynamic control, we have to release our xtal_pu "force on" */
5166 + if (scc & SCC_XC)
5167 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5168 + break;
5169 +
5170 + default:
5171 + ASSERT(0);
5172 + }
5173 +
5174 + /* Is the h/w forcing the use of the fast clk */
5175 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5176 +
5177 +done:
5178 + sb_setcoreidx(sbh, origidx);
5179 + INTR_RESTORE(si, intr_val);
5180 + return (forcefastclk);
5181 +}
5182 +
5183 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5184 +{
5185 +return sb_clkctl_clk(sbh, mode);
5186 +}
5187 +/* register driver interrupt disabling and restoring callback functions */
5188 +void
5189 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5190 +{
5191 + sb_info_t *si;
5192 +
5193 + si = SB_INFO(sbh);
5194 + si->intr_arg = intr_arg;
5195 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5196 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5197 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5198 + /* save current core id. when this function called, the current core
5199 + * must be the core which provides driver functions(il, et, wl, etc.)
5200 + */
5201 + si->dev_coreid = si->coreid[si->curidx];
5202 +}
5203 +
5204 +
5205 +void
5206 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5207 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5208 +{
5209 + uint vendor, core, unit;
5210 + uint chip, chippkg;
5211 + char varname[8];
5212 + uint8 class, subclass, progif;
5213 +
5214 + vendor = sb_corevendor(sbh);
5215 + core = sb_coreid(sbh);
5216 + unit = sb_coreunit(sbh);
5217 +
5218 + chip = BCMINIT(sb_chip)(sbh);
5219 + chippkg = BCMINIT(sb_chippkg)(sbh);
5220 +
5221 + progif = 0;
5222 +
5223 + /* Known vendor translations */
5224 + switch (vendor) {
5225 + case SB_VEND_BCM:
5226 + vendor = VENDOR_BROADCOM;
5227 + break;
5228 + }
5229 +
5230 + /* Determine class based on known core codes */
5231 + switch (core) {
5232 + case SB_ILINE20:
5233 + class = PCI_CLASS_NET;
5234 + subclass = PCI_NET_ETHER;
5235 + core = BCM47XX_ILINE_ID;
5236 + break;
5237 + case SB_ENET:
5238 + class = PCI_CLASS_NET;
5239 + subclass = PCI_NET_ETHER;
5240 + core = BCM47XX_ENET_ID;
5241 + break;
5242 + case SB_SDRAM:
5243 + case SB_MEMC:
5244 + class = PCI_CLASS_MEMORY;
5245 + subclass = PCI_MEMORY_RAM;
5246 + break;
5247 + case SB_PCI:
5248 + class = PCI_CLASS_BRIDGE;
5249 + subclass = PCI_BRIDGE_PCI;
5250 + break;
5251 + case SB_MIPS:
5252 + case SB_MIPS33:
5253 + class = PCI_CLASS_CPU;
5254 + subclass = PCI_CPU_MIPS;
5255 + break;
5256 + case SB_CODEC:
5257 + class = PCI_CLASS_COMM;
5258 + subclass = PCI_COMM_MODEM;
5259 + core = BCM47XX_V90_ID;
5260 + break;
5261 + case SB_USB:
5262 + class = PCI_CLASS_SERIAL;
5263 + subclass = PCI_SERIAL_USB;
5264 + progif = 0x10; /* OHCI */
5265 + core = BCM47XX_USB_ID;
5266 + break;
5267 + case SB_USB11H:
5268 + class = PCI_CLASS_SERIAL;
5269 + subclass = PCI_SERIAL_USB;
5270 + progif = 0x10; /* OHCI */
5271 + core = BCM47XX_USBH_ID;
5272 + break;
5273 + case SB_USB11D:
5274 + class = PCI_CLASS_SERIAL;
5275 + subclass = PCI_SERIAL_USB;
5276 + core = BCM47XX_USBD_ID;
5277 + break;
5278 + case SB_IPSEC:
5279 + class = PCI_CLASS_CRYPT;
5280 + subclass = PCI_CRYPT_NETWORK;
5281 + core = BCM47XX_IPSEC_ID;
5282 + break;
5283 + case SB_ROBO:
5284 + class = PCI_CLASS_NET;
5285 + subclass = PCI_NET_OTHER;
5286 + core = BCM47XX_ROBO_ID;
5287 + break;
5288 + case SB_EXTIF:
5289 + case SB_CC:
5290 + class = PCI_CLASS_MEMORY;
5291 + subclass = PCI_MEMORY_FLASH;
5292 + break;
5293 + case SB_D11:
5294 + class = PCI_CLASS_NET;
5295 + subclass = PCI_NET_OTHER;
5296 + /* Let an nvram variable override this */
5297 + sprintf(varname, "wl%did", unit);
5298 + if ((core = getintvar(NULL, varname)) == 0) {
5299 + if (chip == BCM4712_DEVICE_ID) {
5300 + if (chippkg == BCM4712SMALL_PKG_ID)
5301 + core = BCM4306_D11G_ID;
5302 + else
5303 + core = BCM4306_D11DUAL_ID;
5304 + }
5305 + }
5306 + break;
5307 +
5308 + default:
5309 + class = subclass = progif = 0xff;
5310 + break;
5311 + }
5312 +
5313 + *pcivendor = (uint16)vendor;
5314 + *pcidevice = (uint16)core;
5315 + *pciclass = class;
5316 + *pcisubclass = subclass;
5317 + *pciprogif = progif;
5318 +}
5319 +
5320 +/* Fix chip's configuration. The current core may be changed upon return */
5321 +static int
5322 +sb_pci_fixcfg(sb_info_t *si)
5323 +{
5324 + uint origidx, pciidx;
5325 + sbpciregs_t *pciregs;
5326 + uint16 val16, *reg16;
5327 +
5328 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5329 +
5330 + /* Fix PCI(e) SROM shadow area */
5331 + /* save the current index */
5332 + origidx = sb_coreidx(&si->sb);
5333 +
5334 + if (si->sb.buscoretype == SB_PCI) {
5335 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5336 + ASSERT(pciregs);
5337 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5338 + }
5339 + else {
5340 + ASSERT(0);
5341 + return -1;
5342 + }
5343 + pciidx = sb_coreidx(&si->sb);
5344 + val16 = R_REG(reg16);
5345 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5346 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5347 + W_REG(reg16, val16);
5348 + }
5349 +
5350 + /* restore the original index */
5351 + sb_setcoreidx(&si->sb, origidx);
5352 +
5353 + return 0;
5354 +}
5355 +
5356 +EXPORT_SYMBOL(sb_boardtype);
5357 +EXPORT_SYMBOL(sb_boardvendor);
5358 +EXPORT_SYMBOL(sb_gpiocontrol);
5359 +EXPORT_SYMBOL(sb_gpioin);
5360 +EXPORT_SYMBOL(sb_gpiointmask);
5361 +EXPORT_SYMBOL(sb_gpiointpolarity);
5362 +EXPORT_SYMBOL(sb_gpioled);
5363 +EXPORT_SYMBOL(sb_gpioout);
5364 +EXPORT_SYMBOL(sb_gpioouten);
5365 +EXPORT_SYMBOL(sb_gpiorelease);
5366 +EXPORT_SYMBOL(sb_gpioreserve);
5367 +EXPORT_SYMBOL(sb_gpiosetcore);
5368 +EXPORT_SYMBOL(sb_gpiotimerval);
5369 +EXPORT_SYMBOL(sb_watchdog);
5370 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5371 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5372 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2005-12-15 16:59:20.045933750 +0100
5373 @@ -0,0 +1,418 @@
5374 +/*
5375 + * Broadcom SiliconBackplane chipcommon serial flash interface
5376 + *
5377 + * Copyright 2005, Broadcom Corporation
5378 + * All Rights Reserved.
5379 + *
5380 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5381 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5382 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5383 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5384 + *
5385 + * $Id$
5386 + */
5387 +
5388 +#include <osl.h>
5389 +#include <typedefs.h>
5390 +#include <sbconfig.h>
5391 +#include <sbchipc.h>
5392 +#include <mipsinc.h>
5393 +#include <bcmutils.h>
5394 +#include <bcmdevs.h>
5395 +#include <sflash.h>
5396 +
5397 +/* Private global state */
5398 +static struct sflash sflash;
5399 +
5400 +/* Issue a serial flash command */
5401 +static INLINE void
5402 +sflash_cmd(chipcregs_t *cc, uint opcode)
5403 +{
5404 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5405 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5406 +}
5407 +
5408 +/* Initialize serial flash access */
5409 +struct sflash *
5410 +sflash_init(chipcregs_t *cc)
5411 +{
5412 + uint32 id, id2;
5413 +
5414 + bzero(&sflash, sizeof(sflash));
5415 +
5416 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5417 +
5418 + switch (sflash.type) {
5419 + case SFLASH_ST:
5420 + /* Probe for ST chips */
5421 + sflash_cmd(cc, SFLASH_ST_DP);
5422 + sflash_cmd(cc, SFLASH_ST_RES);
5423 + id = R_REG(&cc->flashdata);
5424 + switch (id) {
5425 + case 0x11:
5426 + /* ST M25P20 2 Mbit Serial Flash */
5427 + sflash.blocksize = 64 * 1024;
5428 + sflash.numblocks = 4;
5429 + break;
5430 + case 0x12:
5431 + /* ST M25P40 4 Mbit Serial Flash */
5432 + sflash.blocksize = 64 * 1024;
5433 + sflash.numblocks = 8;
5434 + break;
5435 + case 0x13:
5436 + /* ST M25P80 8 Mbit Serial Flash */
5437 + sflash.blocksize = 64 * 1024;
5438 + sflash.numblocks = 16;
5439 + break;
5440 + case 0x14:
5441 + /* ST M25P16 16 Mbit Serial Flash */
5442 + sflash.blocksize = 64 * 1024;
5443 + sflash.numblocks = 32;
5444 + break;
5445 + case 0x15:
5446 + /* ST M25P32 32 Mbit Serial Flash */
5447 + sflash.blocksize = 64 * 1024;
5448 + sflash.numblocks = 64;
5449 + break;
5450 + case 0xbf:
5451 + W_REG(&cc->flashaddress, 1);
5452 + sflash_cmd(cc, SFLASH_ST_RES);
5453 + id2 = R_REG(&cc->flashdata);
5454 + if (id2 == 0x44) {
5455 + /* SST M25VF80 4 Mbit Serial Flash */
5456 + sflash.blocksize = 64 * 1024;
5457 + sflash.numblocks = 8;
5458 + }
5459 + break;
5460 + }
5461 + break;
5462 +
5463 + case SFLASH_AT:
5464 + /* Probe for Atmel chips */
5465 + sflash_cmd(cc, SFLASH_AT_STATUS);
5466 + id = R_REG(&cc->flashdata) & 0x3c;
5467 + switch (id) {
5468 + case 0xc:
5469 + /* Atmel AT45DB011 1Mbit Serial Flash */
5470 + sflash.blocksize = 256;
5471 + sflash.numblocks = 512;
5472 + break;
5473 + case 0x14:
5474 + /* Atmel AT45DB021 2Mbit Serial Flash */
5475 + sflash.blocksize = 256;
5476 + sflash.numblocks = 1024;
5477 + break;
5478 + case 0x1c:
5479 + /* Atmel AT45DB041 4Mbit Serial Flash */
5480 + sflash.blocksize = 256;
5481 + sflash.numblocks = 2048;
5482 + break;
5483 + case 0x24:
5484 + /* Atmel AT45DB081 8Mbit Serial Flash */
5485 + sflash.blocksize = 256;
5486 + sflash.numblocks = 4096;
5487 + break;
5488 + case 0x2c:
5489 + /* Atmel AT45DB161 16Mbit Serial Flash */
5490 + sflash.blocksize = 512;
5491 + sflash.numblocks = 4096;
5492 + break;
5493 + case 0x34:
5494 + /* Atmel AT45DB321 32Mbit Serial Flash */
5495 + sflash.blocksize = 512;
5496 + sflash.numblocks = 8192;
5497 + break;
5498 + case 0x3c:
5499 + /* Atmel AT45DB642 64Mbit Serial Flash */
5500 + sflash.blocksize = 1024;
5501 + sflash.numblocks = 8192;
5502 + break;
5503 + }
5504 + break;
5505 + }
5506 +
5507 + sflash.size = sflash.blocksize * sflash.numblocks;
5508 + return sflash.size ? &sflash : NULL;
5509 +}
5510 +
5511 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5512 +int
5513 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5514 +{
5515 + int cnt;
5516 + uint32 *from, *to;
5517 +
5518 + if (!len)
5519 + return 0;
5520 +
5521 + if ((offset + len) > sflash.size)
5522 + return -22;
5523 +
5524 + if ((len >= 4) && (offset & 3))
5525 + cnt = 4 - (offset & 3);
5526 + else if ((len >= 4) && ((uint32)buf & 3))
5527 + cnt = 4 - ((uint32)buf & 3);
5528 + else
5529 + cnt = len;
5530 +
5531 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5532 + to = (uint32 *)buf;
5533 +
5534 + if (cnt < 4) {
5535 + bcopy(from, to, cnt);
5536 + return cnt;
5537 + }
5538 +
5539 + while (cnt >= 4) {
5540 + *to++ = *from++;
5541 + cnt -= 4;
5542 + }
5543 +
5544 + return (len - cnt);
5545 +}
5546 +
5547 +/* Poll for command completion. Returns zero when complete. */
5548 +int
5549 +sflash_poll(chipcregs_t *cc, uint offset)
5550 +{
5551 + if (offset >= sflash.size)
5552 + return -22;
5553 +
5554 + switch (sflash.type) {
5555 + case SFLASH_ST:
5556 + /* Check for ST Write In Progress bit */
5557 + sflash_cmd(cc, SFLASH_ST_RDSR);
5558 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5559 + case SFLASH_AT:
5560 + /* Check for Atmel Ready bit */
5561 + sflash_cmd(cc, SFLASH_AT_STATUS);
5562 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5563 + }
5564 +
5565 + return 0;
5566 +}
5567 +
5568 +/* Write len bytes starting at offset into buf. Returns number of bytes
5569 + * written. Caller should poll for completion.
5570 + */
5571 +int
5572 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5573 +{
5574 + struct sflash *sfl;
5575 + int ret = 0;
5576 + bool is4712b0;
5577 + uint32 page, byte, mask;
5578 +
5579 + if (!len)
5580 + return 0;
5581 +
5582 + if ((offset + len) > sflash.size)
5583 + return -22;
5584 +
5585 + sfl = &sflash;
5586 + switch (sfl->type) {
5587 + case SFLASH_ST:
5588 + mask = R_REG(&cc->chipid);
5589 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5590 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5591 + /* Enable writes */
5592 + sflash_cmd(cc, SFLASH_ST_WREN);
5593 + if (is4712b0) {
5594 + mask = 1 << 14;
5595 + W_REG(&cc->flashaddress, offset);
5596 + W_REG(&cc->flashdata, *buf++);
5597 + /* Set chip select */
5598 + OR_REG(&cc->gpioout, mask);
5599 + /* Issue a page program with the first byte */
5600 + sflash_cmd(cc, SFLASH_ST_PP);
5601 + ret = 1;
5602 + offset++;
5603 + len--;
5604 + while (len > 0) {
5605 + if ((offset & 255) == 0) {
5606 + /* Page boundary, drop cs and return */
5607 + AND_REG(&cc->gpioout, ~mask);
5608 + if (!sflash_poll(cc, offset)) {
5609 + /* Flash rejected command */
5610 + return -11;
5611 + }
5612 + return ret;
5613 + } else {
5614 + /* Write single byte */
5615 + sflash_cmd(cc, *buf++);
5616 + }
5617 + ret++;
5618 + offset++;
5619 + len--;
5620 + }
5621 + /* All done, drop cs if needed */
5622 + if ((offset & 255) != 1) {
5623 + /* Drop cs */
5624 + AND_REG(&cc->gpioout, ~mask);
5625 + if (!sflash_poll(cc, offset)) {
5626 + /* Flash rejected command */
5627 + return -12;
5628 + }
5629 + }
5630 + } else {
5631 + ret = 1;
5632 + W_REG(&cc->flashaddress, offset);
5633 + W_REG(&cc->flashdata, *buf);
5634 + /* Page program */
5635 + sflash_cmd(cc, SFLASH_ST_PP);
5636 + }
5637 + break;
5638 + case SFLASH_AT:
5639 + mask = sfl->blocksize - 1;
5640 + page = (offset & ~mask) << 1;
5641 + byte = offset & mask;
5642 + /* Read main memory page into buffer 1 */
5643 + if (byte || len < sfl->blocksize) {
5644 + W_REG(&cc->flashaddress, page);
5645 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5646 + /* 250 us for AT45DB321B */
5647 + SPINWAIT(sflash_poll(cc, offset), 1000);
5648 + ASSERT(!sflash_poll(cc, offset));
5649 + }
5650 + /* Write into buffer 1 */
5651 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5652 + W_REG(&cc->flashaddress, byte++);
5653 + W_REG(&cc->flashdata, *buf++);
5654 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5655 + }
5656 + /* Write buffer 1 into main memory page */
5657 + W_REG(&cc->flashaddress, page);
5658 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5659 + break;
5660 + }
5661 +
5662 + return ret;
5663 +}
5664 +
5665 +/* Erase a region. Returns number of bytes scheduled for erasure.
5666 + * Caller should poll for completion.
5667 + */
5668 +int
5669 +sflash_erase(chipcregs_t *cc, uint offset)
5670 +{
5671 + struct sflash *sfl;
5672 +
5673 + if (offset >= sflash.size)
5674 + return -22;
5675 +
5676 + sfl = &sflash;
5677 + switch (sfl->type) {
5678 + case SFLASH_ST:
5679 + sflash_cmd(cc, SFLASH_ST_WREN);
5680 + W_REG(&cc->flashaddress, offset);
5681 + sflash_cmd(cc, SFLASH_ST_SE);
5682 + return sfl->blocksize;
5683 + case SFLASH_AT:
5684 + W_REG(&cc->flashaddress, offset << 1);
5685 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5686 + return sfl->blocksize;
5687 + }
5688 +
5689 + return 0;
5690 +}
5691 +
5692 +/*
5693 + * writes the appropriate range of flash, a NULL buf simply erases
5694 + * the region of flash
5695 + */
5696 +int
5697 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5698 +{
5699 + struct sflash *sfl;
5700 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5701 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5702 + uint blk_offset, blk_len, copied;
5703 + int bytes, ret = 0;
5704 +
5705 + /* Check address range */
5706 + if (len <= 0)
5707 + return 0;
5708 +
5709 + sfl = &sflash;
5710 + if ((offset + len) > sfl->size)
5711 + return -1;
5712 +
5713 + blocksize = sfl->blocksize;
5714 + mask = blocksize - 1;
5715 +
5716 + /* Allocate a block of mem */
5717 + if (!(block = MALLOC(NULL, blocksize)))
5718 + return -1;
5719 +
5720 + while (len) {
5721 + /* Align offset */
5722 + cur_offset = offset & ~mask;
5723 + cur_length = blocksize;
5724 + cur_ptr = block;
5725 +
5726 + remainder = blocksize - (offset & mask);
5727 + if (len < remainder)
5728 + cur_retlen = len;
5729 + else
5730 + cur_retlen = remainder;
5731 +
5732 + /* buf == NULL means erase only */
5733 + if (buf) {
5734 + /* Copy existing data into holding block if necessary */
5735 + if ((offset & mask) || (len < blocksize)) {
5736 + blk_offset = cur_offset;
5737 + blk_len = cur_length;
5738 + blk_ptr = cur_ptr;
5739 +
5740 + /* Copy entire block */
5741 + while(blk_len) {
5742 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5743 + blk_offset += copied;
5744 + blk_len -= copied;
5745 + blk_ptr += copied;
5746 + }
5747 + }
5748 +
5749 + /* Copy input data into holding block */
5750 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5751 + }
5752 +
5753 + /* Erase block */
5754 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5755 + goto done;
5756 + while (sflash_poll(cc, (uint) cur_offset));
5757 +
5758 + /* buf == NULL means erase only */
5759 + if (!buf) {
5760 + offset += cur_retlen;
5761 + len -= cur_retlen;
5762 + continue;
5763 + }
5764 +
5765 + /* Write holding block */
5766 + while (cur_length > 0) {
5767 + if ((bytes = sflash_write(cc,
5768 + (uint) cur_offset,
5769 + (uint) cur_length,
5770 + (uchar *) cur_ptr)) < 0) {
5771 + ret = bytes;
5772 + goto done;
5773 + }
5774 + while (sflash_poll(cc, (uint) cur_offset));
5775 + cur_offset += bytes;
5776 + cur_length -= bytes;
5777 + cur_ptr += bytes;
5778 + }
5779 +
5780 + offset += cur_retlen;
5781 + len -= cur_retlen;
5782 + buf += cur_retlen;
5783 + }
5784 +
5785 + ret = len;
5786 +done:
5787 + if (block)
5788 + MFREE(NULL, block, blocksize);
5789 + return ret;
5790 +}
5791 +
5792 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5793 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5794 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-15 15:25:24.905340500 +0100
5795 @@ -0,0 +1,391 @@
5796 +/*
5797 + * Broadcom device-specific manifest constants.
5798 + *
5799 + * Copyright 2005, Broadcom Corporation
5800 + * All Rights Reserved.
5801 + *
5802 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5803 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5804 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5805 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5806 + * $Id$
5807 + */
5808 +
5809 +#ifndef _BCMDEVS_H
5810 +#define _BCMDEVS_H
5811 +
5812 +
5813 +/* Known PCI vendor Id's */
5814 +#define VENDOR_EPIGRAM 0xfeda
5815 +#define VENDOR_BROADCOM 0x14e4
5816 +#define VENDOR_3COM 0x10b7
5817 +#define VENDOR_NETGEAR 0x1385
5818 +#define VENDOR_DIAMOND 0x1092
5819 +#define VENDOR_DELL 0x1028
5820 +#define VENDOR_HP 0x0e11
5821 +#define VENDOR_APPLE 0x106b
5822 +
5823 +/* PCI Device Id's */
5824 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5825 +#define BCM4211_DEVICE_ID 0x4211
5826 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5827 +#define BCM4231_DEVICE_ID 0x4231
5828 +
5829 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5830 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5831 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5832 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5833 +
5834 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5835 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5836 +
5837 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5838 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5839 +
5840 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5841 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5842 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5843 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5844 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5845 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5846 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5847 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5848 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5849 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5850 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5851 +
5852 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5853 +
5854 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5855 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5856 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5857 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5858 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5859 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5860 +
5861 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5862 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5863 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5864 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5865 +
5866 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5867 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5868 +
5869 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5870 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5871 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5872 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5873 +
5874 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5875 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5876 +#define BCM4306_D11G_ID2 0x4325
5877 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5878 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5879 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5880 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5881 +
5882 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5883 +
5884 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5885 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5886 +
5887 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5888 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5889 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5890 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5891 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5892 +
5893 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5894 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5895 +
5896 +
5897 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5898 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5899 +
5900 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5901 +
5902 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5903 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5904 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5905 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5906 +
5907 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5908 +
5909 +/* Address map */
5910 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5911 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5912 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5913 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5914 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5915 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5916 +
5917 +/* Core register space */
5918 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5919 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5920 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5921 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5922 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5923 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5924 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5925 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5926 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5927 +
5928 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5929 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5930 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5931 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5932 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5933 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5934 +
5935 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5936 +
5937 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5938 +
5939 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5940 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5941 +
5942 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5943 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5944 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5945 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5946 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5947 +
5948 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5949 +
5950 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5951 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5952 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5953 +
5954 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
5955 +
5956 +/* PCMCIA vendor Id's */
5957 +
5958 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
5959 +
5960 +/* SDIO vendor Id's */
5961 +#define VENDOR_BROADCOM_SDIO 0x00BF
5962 +
5963 +
5964 +/* boardflags */
5965 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
5966 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
5967 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
5968 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
5969 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
5970 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
5971 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
5972 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
5973 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
5974 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
5975 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
5976 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
5977 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
5978 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
5979 +
5980 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
5981 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
5982 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
5983 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
5984 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
5985 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
5986 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
5987 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
5988 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
5989 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5990 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5991 +
5992 +/* Bus types */
5993 +#define SB_BUS 0 /* Silicon Backplane */
5994 +#define PCI_BUS 1 /* PCI target */
5995 +#define PCMCIA_BUS 2 /* PCMCIA target */
5996 +#define SDIO_BUS 3 /* SDIO target */
5997 +#define JTAG_BUS 4 /* JTAG */
5998 +
5999 +/* Allows optimization for single-bus support */
6000 +#ifdef BCMBUSTYPE
6001 +#define BUSTYPE(bus) (BCMBUSTYPE)
6002 +#else
6003 +#define BUSTYPE(bus) (bus)
6004 +#endif
6005 +
6006 +/* power control defines */
6007 +#define PLL_DELAY 150 /* us pll on delay */
6008 +#define FREF_DELAY 200 /* us fref change delay */
6009 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6010 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6011 +
6012 +/* Reference Board Types */
6013 +
6014 +#define BU4710_BOARD 0x0400
6015 +#define VSIM4710_BOARD 0x0401
6016 +#define QT4710_BOARD 0x0402
6017 +
6018 +#define BU4610_BOARD 0x0403
6019 +#define VSIM4610_BOARD 0x0404
6020 +
6021 +#define BU4307_BOARD 0x0405
6022 +#define BCM94301CB_BOARD 0x0406
6023 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6024 +#define BCM94301MP_BOARD 0x0407
6025 +#define BCM94307MP_BOARD 0x0408
6026 +#define BCMAP4307_BOARD 0x0409
6027 +
6028 +#define BU4309_BOARD 0x040a
6029 +#define BCM94309CB_BOARD 0x040b
6030 +#define BCM94309MP_BOARD 0x040c
6031 +#define BCM4309AP_BOARD 0x040d
6032 +
6033 +#define BCM94302MP_BOARD 0x040e
6034 +
6035 +#define VSIM4310_BOARD 0x040f
6036 +#define BU4711_BOARD 0x0410
6037 +#define BCM94310U_BOARD 0x0411
6038 +#define BCM94310AP_BOARD 0x0412
6039 +#define BCM94310MP_BOARD 0x0414
6040 +
6041 +#define BU4306_BOARD 0x0416
6042 +#define BCM94306CB_BOARD 0x0417
6043 +#define BCM94306MP_BOARD 0x0418
6044 +
6045 +#define BCM94710D_BOARD 0x041a
6046 +#define BCM94710R1_BOARD 0x041b
6047 +#define BCM94710R4_BOARD 0x041c
6048 +#define BCM94710AP_BOARD 0x041d
6049 +
6050 +
6051 +#define BU2050_BOARD 0x041f
6052 +
6053 +
6054 +#define BCM94309G_BOARD 0x0421
6055 +
6056 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6057 +
6058 +#define BU4704_BOARD 0x0423
6059 +#define BU4702_BOARD 0x0424
6060 +
6061 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6062 +
6063 +#define BU4317_BOARD 0x0426
6064 +
6065 +
6066 +#define BCM94702MN_BOARD 0x0428
6067 +
6068 +/* BCM4702 1U CompactPCI Board */
6069 +#define BCM94702CPCI_BOARD 0x0429
6070 +
6071 +/* BCM4702 with BCM95380 VLAN Router */
6072 +#define BCM95380RR_BOARD 0x042a
6073 +
6074 +/* cb4306 with SiGe PA */
6075 +#define BCM94306CBSG_BOARD 0x042b
6076 +
6077 +/* mp4301 with 2050 radio */
6078 +#define BCM94301MPL_BOARD 0x042c
6079 +
6080 +/* cb4306 with SiGe PA */
6081 +#define PCSG94306_BOARD 0x042d
6082 +
6083 +/* bu4704 with sdram */
6084 +#define BU4704SD_BOARD 0x042e
6085 +
6086 +/* Dual 11a/11g Router */
6087 +#define BCM94704AGR_BOARD 0x042f
6088 +
6089 +/* 11a-only minipci */
6090 +#define BCM94308MP_BOARD 0x0430
6091 +
6092 +
6093 +
6094 +/* BCM94317 boards */
6095 +#define BCM94317CB_BOARD 0x0440
6096 +#define BCM94317MP_BOARD 0x0441
6097 +#define BCM94317PCMCIA_BOARD 0x0442
6098 +#define BCM94317SDIO_BOARD 0x0443
6099 +
6100 +#define BU4712_BOARD 0x0444
6101 +#define BU4712SD_BOARD 0x045d
6102 +#define BU4712L_BOARD 0x045f
6103 +
6104 +/* BCM4712 boards */
6105 +#define BCM94712AP_BOARD 0x0445
6106 +#define BCM94712P_BOARD 0x0446
6107 +
6108 +/* BCM4318 boards */
6109 +#define BU4318_BOARD 0x0447
6110 +#define CB4318_BOARD 0x0448
6111 +#define MPG4318_BOARD 0x0449
6112 +#define MP4318_BOARD 0x044a
6113 +#define SD4318_BOARD 0x044b
6114 +
6115 +/* BCM63XX boards */
6116 +#define BCM96338_BOARD 0x6338
6117 +#define BCM96345_BOARD 0x6345
6118 +#define BCM96348_BOARD 0x6348
6119 +
6120 +/* Another mp4306 with SiGe */
6121 +#define BCM94306P_BOARD 0x044c
6122 +
6123 +/* CF-like 4317 modules */
6124 +#define BCM94317CF_BOARD 0x044d
6125 +
6126 +/* mp4303 */
6127 +#define BCM94303MP_BOARD 0x044e
6128 +
6129 +/* mpsgh4306 */
6130 +#define BCM94306MPSGH_BOARD 0x044f
6131 +
6132 +/* BRCM 4306 w/ Front End Modules */
6133 +#define BCM94306MPM 0x0450
6134 +#define BCM94306MPL 0x0453
6135 +
6136 +/* 4712agr */
6137 +#define BCM94712AGR_BOARD 0x0451
6138 +
6139 +/* The real CF 4317 board */
6140 +#define CFI4317_BOARD 0x0452
6141 +
6142 +/* pcmcia 4303 */
6143 +#define PC4303_BOARD 0x0454
6144 +
6145 +/* 5350K */
6146 +#define BCM95350K_BOARD 0x0455
6147 +
6148 +/* 5350R */
6149 +#define BCM95350R_BOARD 0x0456
6150 +
6151 +/* 4306mplna */
6152 +#define BCM94306MPLNA_BOARD 0x0457
6153 +
6154 +/* 4320 boards */
6155 +#define BU4320_BOARD 0x0458
6156 +#define BU4320S_BOARD 0x0459
6157 +#define BCM94320PH_BOARD 0x045a
6158 +
6159 +/* 4306mph */
6160 +#define BCM94306MPH_BOARD 0x045b
6161 +
6162 +/* 4306pciv */
6163 +#define BCM94306PCIV_BOARD 0x045c
6164 +
6165 +#define BU4712SD_BOARD 0x045d
6166 +
6167 +#define BCM94320PFLSH_BOARD 0x045e
6168 +
6169 +#define BU4712L_BOARD 0x045f
6170 +#define BCM94712LGR_BOARD 0x0460
6171 +#define BCM94320R_BOARD 0x0461
6172 +
6173 +#define BU5352_BOARD 0x0462
6174 +
6175 +#define BCM94318MPGH_BOARD 0x0463
6176 +
6177 +
6178 +#define BCM95352GR_BOARD 0x0467
6179 +
6180 +/* bcm95351agr */
6181 +#define BCM95351AGR_BOARD 0x0470
6182 +
6183 +/* # of GPIO pins */
6184 +#define GPIO_NUMPINS 16
6185 +
6186 +#endif /* _BCMDEVS_H */
6187 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6188 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6189 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-12-15 15:25:47.146730500 +0100
6190 @@ -0,0 +1,152 @@
6191 +/*
6192 + * local version of endian.h - byte order defines
6193 + *
6194 + * Copyright 2005, Broadcom Corporation
6195 + * All Rights Reserved.
6196 + *
6197 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6198 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6199 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6200 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6201 + *
6202 + * $Id$
6203 +*/
6204 +
6205 +#ifndef _BCMENDIAN_H_
6206 +#define _BCMENDIAN_H_
6207 +
6208 +#include <typedefs.h>
6209 +
6210 +/* Byte swap a 16 bit value */
6211 +#define BCMSWAP16(val) \
6212 + ((uint16)( \
6213 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6214 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6215 +
6216 +/* Byte swap a 32 bit value */
6217 +#define BCMSWAP32(val) \
6218 + ((uint32)( \
6219 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6220 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6221 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6222 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6223 +
6224 +/* 2 Byte swap a 32 bit value */
6225 +#define BCMSWAP32BY16(val) \
6226 + ((uint32)( \
6227 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6228 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6229 +
6230 +
6231 +static INLINE uint16
6232 +bcmswap16(uint16 val)
6233 +{
6234 + return BCMSWAP16(val);
6235 +}
6236 +
6237 +static INLINE uint32
6238 +bcmswap32(uint32 val)
6239 +{
6240 + return BCMSWAP32(val);
6241 +}
6242 +
6243 +static INLINE uint32
6244 +bcmswap32by16(uint32 val)
6245 +{
6246 + return BCMSWAP32BY16(val);
6247 +}
6248 +
6249 +/* buf - start of buffer of shorts to swap */
6250 +/* len - byte length of buffer */
6251 +static INLINE void
6252 +bcmswap16_buf(uint16 *buf, uint len)
6253 +{
6254 + len = len/2;
6255 +
6256 + while(len--){
6257 + *buf = bcmswap16(*buf);
6258 + buf++;
6259 + }
6260 +}
6261 +
6262 +#ifndef hton16
6263 +#ifndef IL_BIGENDIAN
6264 +#define HTON16(i) BCMSWAP16(i)
6265 +#define hton16(i) bcmswap16(i)
6266 +#define hton32(i) bcmswap32(i)
6267 +#define ntoh16(i) bcmswap16(i)
6268 +#define ntoh32(i) bcmswap32(i)
6269 +#define ltoh16(i) (i)
6270 +#define ltoh32(i) (i)
6271 +#define htol16(i) (i)
6272 +#define htol32(i) (i)
6273 +#else
6274 +#define HTON16(i) (i)
6275 +#define hton16(i) (i)
6276 +#define hton32(i) (i)
6277 +#define ntoh16(i) (i)
6278 +#define ntoh32(i) (i)
6279 +#define ltoh16(i) bcmswap16(i)
6280 +#define ltoh32(i) bcmswap32(i)
6281 +#define htol16(i) bcmswap16(i)
6282 +#define htol32(i) bcmswap32(i)
6283 +#endif
6284 +#endif
6285 +
6286 +#ifndef IL_BIGENDIAN
6287 +#define ltoh16_buf(buf, i)
6288 +#define htol16_buf(buf, i)
6289 +#else
6290 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6291 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6292 +#endif
6293 +
6294 +/*
6295 +* load 16-bit value from unaligned little endian byte array.
6296 +*/
6297 +static INLINE uint16
6298 +ltoh16_ua(uint8 *bytes)
6299 +{
6300 + return (bytes[1]<<8)+bytes[0];
6301 +}
6302 +
6303 +/*
6304 +* load 32-bit value from unaligned little endian byte array.
6305 +*/
6306 +static INLINE uint32
6307 +ltoh32_ua(uint8 *bytes)
6308 +{
6309 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6310 +}
6311 +
6312 +/*
6313 +* load 16-bit value from unaligned big(network) endian byte array.
6314 +*/
6315 +static INLINE uint16
6316 +ntoh16_ua(uint8 *bytes)
6317 +{
6318 + return (bytes[0]<<8)+bytes[1];
6319 +}
6320 +
6321 +/*
6322 +* load 32-bit value from unaligned big(network) endian byte array.
6323 +*/
6324 +static INLINE uint32
6325 +ntoh32_ua(uint8 *bytes)
6326 +{
6327 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6328 +}
6329 +
6330 +#define ltoh_ua(ptr) ( \
6331 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6332 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6333 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6334 +)
6335 +
6336 +#define ntoh_ua(ptr) ( \
6337 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6338 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6339 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6340 +)
6341 +
6342 +#endif /* _BCMENDIAN_H_ */
6343 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6344 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6345 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-15 16:04:35.850827500 +0100
6346 @@ -0,0 +1,87 @@
6347 +/*
6348 + * NVRAM variable manipulation
6349 + *
6350 + * Copyright 2005, Broadcom Corporation
6351 + * All Rights Reserved.
6352 + *
6353 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6354 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6355 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6356 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6357 + *
6358 + * $Id$
6359 + */
6360 +
6361 +#ifndef _bcmnvram_h_
6362 +#define _bcmnvram_h_
6363 +
6364 +#ifndef _LANGUAGE_ASSEMBLY
6365 +
6366 +#include <typedefs.h>
6367 +
6368 +struct nvram_header {
6369 + uint32 magic;
6370 + uint32 len;
6371 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6372 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6373 + uint32 config_ncdl; /* ncdl values for memc */
6374 +};
6375 +
6376 +struct nvram_tuple {
6377 + char *name;
6378 + char *value;
6379 + struct nvram_tuple *next;
6380 +};
6381 +
6382 +/*
6383 + * Get the value of an NVRAM variable. The pointer returned may be
6384 + * invalid after a set.
6385 + * @param name name of variable to get
6386 + * @return value of variable or NULL if undefined
6387 + */
6388 +extern char * __init nvram_get(const char *name);
6389 +
6390 +/*
6391 + * Get the value of an NVRAM variable.
6392 + * @param name name of variable to get
6393 + * @return value of variable or NUL if undefined
6394 + */
6395 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
6396 +
6397 +/*
6398 + * Match an NVRAM variable.
6399 + * @param name name of variable to match
6400 + * @param match value to compare against value of variable
6401 + * @return TRUE if variable is defined and its value is string equal
6402 + * to match or FALSE otherwise
6403 + */
6404 +static inline int
6405 +nvram_match(char *name, char *match) {
6406 + const char *value = BCMINIT(nvram_get)(name);
6407 + return (value && !strcmp(value, match));
6408 +}
6409 +
6410 +/*
6411 + * Inversely match an NVRAM variable.
6412 + * @param name name of variable to match
6413 + * @param match value to compare against value of variable
6414 + * @return TRUE if variable is defined and its value is not string
6415 + * equal to invmatch or FALSE otherwise
6416 + */
6417 +static inline int
6418 +nvram_invmatch(char *name, char *invmatch) {
6419 + const char *value = BCMINIT(nvram_get)(name);
6420 + return (value && strcmp(value, invmatch));
6421 +}
6422 +
6423 +#endif /* _LANGUAGE_ASSEMBLY */
6424 +
6425 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6426 +#define NVRAM_VERSION 1
6427 +#define NVRAM_HEADER_SIZE 20
6428 +#define NVRAM_SPACE 0x8000
6429 +
6430 +#define NVRAM_MAX_VALUE_LEN 255
6431 +#define NVRAM_MAX_PARAM_LEN 64
6432 +
6433 +#endif /* _bcmnvram_h_ */
6434 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6435 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6436 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-15 15:34:32.919589250 +0100
6437 @@ -0,0 +1,23 @@
6438 +/*
6439 + * Misc useful routines to access NIC local SROM/OTP .
6440 + *
6441 + * Copyright 2005, Broadcom Corporation
6442 + * All Rights Reserved.
6443 + *
6444 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6445 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6446 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6447 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6448 + *
6449 + * $Id$
6450 + */
6451 +
6452 +#ifndef _bcmsrom_h_
6453 +#define _bcmsrom_h_
6454 +
6455 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6456 +
6457 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6458 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6459 +
6460 +#endif /* _bcmsrom_h_ */
6461 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6462 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6463 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-12-15 16:44:25.619117750 +0100
6464 @@ -0,0 +1,308 @@
6465 +/*
6466 + * Misc useful os-independent macros and functions.
6467 + *
6468 + * Copyright 2005, Broadcom Corporation
6469 + * All Rights Reserved.
6470 + *
6471 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6472 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6473 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6474 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6475 + * $Id$
6476 + */
6477 +
6478 +#ifndef _bcmutils_h_
6479 +#define _bcmutils_h_
6480 +
6481 +/*** driver-only section ***/
6482 +#include <osl.h>
6483 +
6484 +#define _BCM_U 0x01 /* upper */
6485 +#define _BCM_L 0x02 /* lower */
6486 +#define _BCM_D 0x04 /* digit */
6487 +#define _BCM_C 0x08 /* cntrl */
6488 +#define _BCM_P 0x10 /* punct */
6489 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6490 +#define _BCM_X 0x40 /* hex digit */
6491 +#define _BCM_SP 0x80 /* hard space (0x20) */
6492 +
6493 +#define GPIO_PIN_NOTDEFINED 0x20
6494 +
6495 +extern unsigned char bcm_ctype[];
6496 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6497 +
6498 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6499 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6500 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6501 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6502 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6503 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6504 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6505 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6506 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6507 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6508 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6509 +
6510 +/*
6511 + * Spin at most 'us' microseconds while 'exp' is true.
6512 + * Caller should explicitly test 'exp' when this completes
6513 + * and take appropriate error action if 'exp' is still true.
6514 + */
6515 +#define SPINWAIT(exp, us) { \
6516 + uint countdown = (us) + 9; \
6517 + while ((exp) && (countdown >= 10)) {\
6518 + OSL_DELAY(10); \
6519 + countdown -= 10; \
6520 + } \
6521 +}
6522 +
6523 +/* generic osl packet queue */
6524 +struct pktq {
6525 + void *head; /* first packet to dequeue */
6526 + void *tail; /* last packet to dequeue */
6527 + uint len; /* number of queued packets */
6528 + uint maxlen; /* maximum number of queued packets */
6529 + bool priority; /* enqueue by packet priority */
6530 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6531 +};
6532 +#define DEFAULT_QLEN 128
6533 +
6534 +#define pktq_len(q) ((q)->len)
6535 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6536 +#define pktq_head(q) ((q)->head)
6537 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6538 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6539 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6540 +
6541 +/* externs */
6542 +/* packet */
6543 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6544 +extern uint pkttotlen(osl_t *osh, void *);
6545 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6546 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6547 +extern void *pktdeq(struct pktq *q);
6548 +extern void *pktdeqtail(struct pktq *q);
6549 +/* string */
6550 +extern uint bcm_atoi(char *s);
6551 +extern uchar bcm_toupper(uchar c);
6552 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6553 +extern char *bcmstrstr(char *haystack, char *needle);
6554 +extern char *bcmstrcat(char *dest, const char *src);
6555 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6556 +/* ethernet address */
6557 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6558 +extern int bcm_ether_atoe(char *p, char *ea);
6559 +/* delay */
6560 +extern void bcm_mdelay(uint ms);
6561 +/* variable access */
6562 +extern char *getvar(char *vars, char *name);
6563 +extern int getintvar(char *vars, char *name);
6564 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6565 +#define bcmlog(fmt, a1, a2)
6566 +#define bcmdumplog(buf, size) *buf = '\0'
6567 +#define bcmdumplogent(buf, idx) -1
6568 +
6569 +/*** driver/apps-shared section ***/
6570 +
6571 +#define BCME_STRLEN 64
6572 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6573 +
6574 +
6575 +/*
6576 + * error codes could be added but the defined ones shouldn't be changed/deleted
6577 + * these error codes are exposed to the user code
6578 + * when ever a new error code is added to this list
6579 + * please update errorstring table with the related error string and
6580 + * update osl files with os specific errorcode map
6581 +*/
6582 +
6583 +#define BCME_ERROR -1 /* Error generic */
6584 +#define BCME_BADARG -2 /* Bad Argument */
6585 +#define BCME_BADOPTION -3 /* Bad option */
6586 +#define BCME_NOTUP -4 /* Not up */
6587 +#define BCME_NOTDOWN -5 /* Not down */
6588 +#define BCME_NOTAP -6 /* Not AP */
6589 +#define BCME_NOTSTA -7 /* Not STA */
6590 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6591 +#define BCME_RADIOOFF -9 /* Radio Off */
6592 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6593 +#define BCME_NOCLK -11 /* No Clock*/
6594 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6595 +#define BCME_BADBAND -13 /* BAD Band */
6596 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6597 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6598 +#define BCME_BUSY -16 /* Busy*/
6599 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6600 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6601 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6602 +#define BCME_BADCHAN -20 /* BAD Channel */
6603 +#define BCME_BADADDR -21 /* BAD Address*/
6604 +#define BCME_NORESOURCE -22 /* No resources*/
6605 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6606 +#define BCME_BADLEN -24 /* Bad Length*/
6607 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6608 +#define BCME_EPERM -26 /* Not Permitted */
6609 +#define BCME_NOMEM -27 /* No Memory */
6610 +#define BCME_ASSOCIATED -28 /* Associated */
6611 +#define BCME_RANGE -29 /* Range Error*/
6612 +#define BCME_NOTFOUND -30 /* Not found */
6613 +#define BCME_LAST BCME_NOTFOUND
6614 +
6615 +#ifndef ABS
6616 +#define ABS(a) (((a)<0)?-(a):(a))
6617 +#endif
6618 +
6619 +#ifndef MIN
6620 +#define MIN(a, b) (((a)<(b))?(a):(b))
6621 +#endif
6622 +
6623 +#ifndef MAX
6624 +#define MAX(a, b) (((a)>(b))?(a):(b))
6625 +#endif
6626 +
6627 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6628 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6629 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6630 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6631 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6632 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6633 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6634 +
6635 +/* bit map related macros */
6636 +#ifndef setbit
6637 +#define NBBY 8 /* 8 bits per byte */
6638 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6639 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6640 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6641 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6642 +#endif
6643 +
6644 +#define NBITS(type) (sizeof(type) * 8)
6645 +#define NBITVAL(bits) (1 << (bits))
6646 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6647 +
6648 +/* crc defines */
6649 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6650 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6651 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6652 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6653 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6654 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6655 +
6656 +/* bcm_format_flags() bit description structure */
6657 +typedef struct bcm_bit_desc {
6658 + uint32 bit;
6659 + char* name;
6660 +} bcm_bit_desc_t;
6661 +
6662 +/* tag_ID/length/value_buffer tuple */
6663 +typedef struct bcm_tlv {
6664 + uint8 id;
6665 + uint8 len;
6666 + uint8 data[1];
6667 +} bcm_tlv_t;
6668 +
6669 +/* Check that bcm_tlv_t fits into the given buflen */
6670 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6671 +
6672 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6673 +#define ETHER_ADDR_STR_LEN 18
6674 +
6675 +/* unaligned load and store macros */
6676 +#ifdef IL_BIGENDIAN
6677 +static INLINE uint32
6678 +load32_ua(uint8 *a)
6679 +{
6680 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6681 +}
6682 +
6683 +static INLINE void
6684 +store32_ua(uint8 *a, uint32 v)
6685 +{
6686 + a[0] = (v >> 24) & 0xff;
6687 + a[1] = (v >> 16) & 0xff;
6688 + a[2] = (v >> 8) & 0xff;
6689 + a[3] = v & 0xff;
6690 +}
6691 +
6692 +static INLINE uint16
6693 +load16_ua(uint8 *a)
6694 +{
6695 + return ((a[0] << 8) | a[1]);
6696 +}
6697 +
6698 +static INLINE void
6699 +store16_ua(uint8 *a, uint16 v)
6700 +{
6701 + a[0] = (v >> 8) & 0xff;
6702 + a[1] = v & 0xff;
6703 +}
6704 +
6705 +#else
6706 +
6707 +static INLINE uint32
6708 +load32_ua(uint8 *a)
6709 +{
6710 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6711 +}
6712 +
6713 +static INLINE void
6714 +store32_ua(uint8 *a, uint32 v)
6715 +{
6716 + a[3] = (v >> 24) & 0xff;
6717 + a[2] = (v >> 16) & 0xff;
6718 + a[1] = (v >> 8) & 0xff;
6719 + a[0] = v & 0xff;
6720 +}
6721 +
6722 +static INLINE uint16
6723 +load16_ua(uint8 *a)
6724 +{
6725 + return ((a[1] << 8) | a[0]);
6726 +}
6727 +
6728 +static INLINE void
6729 +store16_ua(uint8 *a, uint16 v)
6730 +{
6731 + a[1] = (v >> 8) & 0xff;
6732 + a[0] = v & 0xff;
6733 +}
6734 +
6735 +#endif
6736 +
6737 +/* externs */
6738 +/* crc */
6739 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6740 +/* format/print */
6741 +/* IE parsing */
6742 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6743 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6744 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6745 +
6746 +/* bcmerror*/
6747 +extern const char *bcmerrorstr(int bcmerror);
6748 +
6749 +/* multi-bool data type: set of bools, mbool is true if any is set */
6750 +typedef uint32 mbool;
6751 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6752 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6753 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6754 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6755 +
6756 +/* power conversion */
6757 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6758 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6759 +
6760 +/* generic datastruct to help dump routines */
6761 +struct fielddesc {
6762 + char *nameandfmt;
6763 + uint32 offset;
6764 + uint32 len;
6765 +};
6766 +
6767 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6768 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6769 +
6770 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6771 +
6772 +#endif /* _bcmutils_h_ */
6773 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6774 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6775 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-15 15:34:40.268048500 +0100
6776 @@ -0,0 +1,85 @@
6777 +/*
6778 + * bit manipulation utility functions
6779 + *
6780 + * Copyright 2005, Broadcom Corporation
6781 + * All Rights Reserved.
6782 + *
6783 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6784 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6785 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6786 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6787 + * $Id$
6788 + */
6789 +
6790 +#ifndef _BITFUNCS_H
6791 +#define _BITFUNCS_H
6792 +
6793 +#include <typedefs.h>
6794 +
6795 +/* local prototypes */
6796 +static INLINE uint32 find_msbit(uint32 x);
6797 +
6798 +
6799 +/*
6800 + * find_msbit: returns index of most significant set bit in x, with index
6801 + * range defined as 0-31. NOTE: returns zero if input is zero.
6802 + */
6803 +
6804 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6805 +
6806 +/*
6807 + * Implementation for Pentium processors and gcc. Note that this
6808 + * instruction is actually very slow on some processors (e.g., family 5,
6809 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6810 + * implementation instead.
6811 + */
6812 +static INLINE uint32 find_msbit(uint32 x)
6813 +{
6814 + uint msbit;
6815 + __asm__("bsrl %1,%0"
6816 + :"=r" (msbit)
6817 + :"r" (x));
6818 + return msbit;
6819 +}
6820 +
6821 +#else
6822 +
6823 +/*
6824 + * Generic Implementation
6825 + */
6826 +
6827 +#define DB_POW_MASK16 0xffff0000
6828 +#define DB_POW_MASK8 0x0000ff00
6829 +#define DB_POW_MASK4 0x000000f0
6830 +#define DB_POW_MASK2 0x0000000c
6831 +#define DB_POW_MASK1 0x00000002
6832 +
6833 +static INLINE uint32 find_msbit(uint32 x)
6834 +{
6835 + uint32 temp_x = x;
6836 + uint msbit = 0;
6837 + if (temp_x & DB_POW_MASK16) {
6838 + temp_x >>= 16;
6839 + msbit = 16;
6840 + }
6841 + if (temp_x & DB_POW_MASK8) {
6842 + temp_x >>= 8;
6843 + msbit += 8;
6844 + }
6845 + if (temp_x & DB_POW_MASK4) {
6846 + temp_x >>= 4;
6847 + msbit += 4;
6848 + }
6849 + if (temp_x & DB_POW_MASK2) {
6850 + temp_x >>= 2;
6851 + msbit += 2;
6852 + }
6853 + if (temp_x & DB_POW_MASK1) {
6854 + msbit += 1;
6855 + }
6856 + return(msbit);
6857 +}
6858 +
6859 +#endif
6860 +
6861 +#endif /* _BITFUNCS_H */
6862 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6863 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6864 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-12-15 15:34:44.280299250 +0100
6865 @@ -0,0 +1,188 @@
6866 +/*
6867 + * flash.h: Common definitions for flash access.
6868 + *
6869 + * Copyright 2005, Broadcom Corporation
6870 + * All Rights Reserved.
6871 + *
6872 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6873 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6874 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6875 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6876 + *
6877 + * $Id$
6878 + */
6879 +
6880 +/* Types of flashes we know about */
6881 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6882 +
6883 +/* Commands to write/erase the flases */
6884 +typedef struct _flash_cmds{
6885 + flash_type_t type;
6886 + bool need_unlock;
6887 + uint16 pre_erase;
6888 + uint16 erase_block;
6889 + uint16 erase_chip;
6890 + uint16 write_word;
6891 + uint16 write_buf;
6892 + uint16 clear_csr;
6893 + uint16 read_csr;
6894 + uint16 read_id;
6895 + uint16 confirm;
6896 + uint16 read_array;
6897 +} flash_cmds_t;
6898 +
6899 +#define UNLOCK_CMD_WORDS 2
6900 +
6901 +typedef struct _unlock_cmd {
6902 + uint addr[UNLOCK_CMD_WORDS];
6903 + uint16 cmd[UNLOCK_CMD_WORDS];
6904 +} unlock_cmd_t;
6905 +
6906 +/* Flash descriptors */
6907 +typedef struct _flash_desc {
6908 + uint16 mfgid; /* Manufacturer Id */
6909 + uint16 devid; /* Device Id */
6910 + uint size; /* Total size in bytes */
6911 + uint width; /* Device width in bytes */
6912 + flash_type_t type; /* Device type old, S, J */
6913 + uint bsize; /* Block size */
6914 + uint nb; /* Number of blocks */
6915 + uint ff; /* First full block */
6916 + uint lf; /* Last full block */
6917 + uint nsub; /* Number of subblocks */
6918 + uint *subblocks; /* Offsets for subblocks */
6919 + char *desc; /* Description */
6920 +} flash_desc_t;
6921 +
6922 +
6923 +#ifdef DECLARE_FLASHES
6924 +flash_cmds_t sflash_cmd_t =
6925 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6926 +
6927 +flash_cmds_t flash_cmds[] = {
6928 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6929 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6930 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6931 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6932 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6933 + { 0 }
6934 +};
6935 +
6936 +unlock_cmd_t unlock_cmd_amd = {
6937 +#ifdef MIPSEB
6938 +/* addr: */ { 0x0aa8, 0x0556},
6939 +#else
6940 +/* addr: */ { 0x0aaa, 0x0554},
6941 +#endif
6942 +/* data: */ { 0xaa, 0x55}
6943 +};
6944 +
6945 +unlock_cmd_t unlock_cmd_sst = {
6946 +#ifdef MIPSEB
6947 +/* addr: */ { 0xaaa8, 0x5556},
6948 +#else
6949 +/* addr: */ { 0xaaaa, 0x5554},
6950 +#endif
6951 +/* data: */ { 0xaa, 0x55}
6952 +};
6953 +
6954 +#define AMD_CMD 0xaaa
6955 +#define SST_CMD 0xaaaa
6956 +
6957 +/* intel unlock block cmds */
6958 +#define INTEL_UNLOCK1 0x60
6959 +#define INTEL_UNLOCK2 0xD0
6960 +
6961 +/* Just eight blocks of 8KB byte each */
6962 +
6963 +uint blk8x8k[] = { 0x00000000,
6964 + 0x00002000,
6965 + 0x00004000,
6966 + 0x00006000,
6967 + 0x00008000,
6968 + 0x0000a000,
6969 + 0x0000c000,
6970 + 0x0000e000,
6971 + 0x00010000
6972 +};
6973 +
6974 +/* Funky AMD arrangement for 29xx800's */
6975 +uint amd800[] = { 0x00000000, /* 16KB */
6976 + 0x00004000, /* 32KB */
6977 + 0x0000c000, /* 8KB */
6978 + 0x0000e000, /* 8KB */
6979 + 0x00010000, /* 8KB */
6980 + 0x00012000, /* 8KB */
6981 + 0x00014000, /* 32KB */
6982 + 0x0001c000, /* 16KB */
6983 + 0x00020000
6984 +};
6985 +
6986 +/* AMD arrangement for 29xx160's */
6987 +uint amd4112[] = { 0x00000000, /* 32KB */
6988 + 0x00008000, /* 8KB */
6989 + 0x0000a000, /* 8KB */
6990 + 0x0000c000, /* 16KB */
6991 + 0x00010000
6992 +};
6993 +uint amd2114[] = { 0x00000000, /* 16KB */
6994 + 0x00004000, /* 8KB */
6995 + 0x00006000, /* 8KB */
6996 + 0x00008000, /* 32KB */
6997 + 0x00010000
6998 +};
6999 +
7000 +
7001 +flash_desc_t sflash_desc =
7002 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7003 +
7004 +flash_desc_t flashes[] = {
7005 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7006 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7007 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7008 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7009 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7010 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7011 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7012 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7013 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7014 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7015 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7016 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7017 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7018 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7019 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7020 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7021 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7022 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7023 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7024 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7025 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7026 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7027 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7028 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7029 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7030 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7031 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7032 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7033 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7034 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7035 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7036 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7037 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7038 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7039 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7040 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7041 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7042 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7043 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7044 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7045 +};
7046 +
7047 +#else
7048 +
7049 +extern flash_cmds_t flash_cmds[];
7050 +extern unlock_cmd_t unlock_cmd;
7051 +extern flash_desc_t flashes[];
7052 +
7053 +#endif
7054 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7055 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7056 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-12-15 15:34:48.160541750 +0100
7057 @@ -0,0 +1,27 @@
7058 +/*
7059 + * BCM47XX FLASH driver interface
7060 + *
7061 + * Copyright 2005, Broadcom Corporation
7062 + * All Rights Reserved.
7063 + *
7064 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7065 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7066 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7067 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7068 + * $Id$
7069 + */
7070 +
7071 +#ifndef _flashutl_h_
7072 +#define _flashutl_h_
7073 +
7074 +
7075 +#ifndef _LANGUAGE_ASSEMBLY
7076 +
7077 +int sysFlashInit(char *flash_str);
7078 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7079 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7080 +void nvWrite(unsigned short *data, unsigned int len);
7081 +
7082 +#endif /* _LANGUAGE_ASSEMBLY */
7083 +
7084 +#endif /* _flashutl_h_ */
7085 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7086 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7087 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-12-15 15:34:53.396869000 +0100
7088 @@ -0,0 +1,16 @@
7089 +/*
7090 + * Alternate include file for HND sbmips.h since CFE also ships with
7091 + * a sbmips.h.
7092 + *
7093 + * Copyright 2005, Broadcom Corporation
7094 + * All Rights Reserved.
7095 + *
7096 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7097 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7098 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7099 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7100 + *
7101 + * $Id$
7102 + */
7103 +
7104 +#include "sbmips.h"
7105 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7106 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7107 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-12-15 17:23:39.225126750 +0100
7108 @@ -0,0 +1,331 @@
7109 +/*
7110 + * Linux OS Independent Layer
7111 + *
7112 + * Copyright 2005, Broadcom Corporation
7113 + * All Rights Reserved.
7114 + *
7115 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7116 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7117 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7118 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7119 + *
7120 + * $Id$
7121 + */
7122 +
7123 +#ifndef _linux_osl_h_
7124 +#define _linux_osl_h_
7125 +
7126 +#include <typedefs.h>
7127 +
7128 +/* use current 2.4.x calling conventions */
7129 +#include <linuxver.h>
7130 +
7131 +/* assert and panic */
7132 +#ifdef __GNUC__
7133 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7134 +#if GCC_VERSION > 30100
7135 +#define ASSERT(exp) do {} while (0)
7136 +#else
7137 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7138 +#define ASSERT(exp)
7139 +#endif
7140 +#endif
7141 +
7142 +/* microsecond delay */
7143 +#define OSL_DELAY(usec) osl_delay(usec)
7144 +extern void osl_delay(uint usec);
7145 +
7146 +/* PCI configuration space access macros */
7147 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7148 + osl_pci_read_config((osh), (offset), (size))
7149 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7150 + osl_pci_write_config((osh), (offset), (size), (val))
7151 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7152 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7153 +
7154 +/* PCI device bus # and slot # */
7155 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7156 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7157 +extern uint osl_pci_bus(osl_t *osh);
7158 +extern uint osl_pci_slot(osl_t *osh);
7159 +
7160 +/* OSL initialization */
7161 +extern osl_t *osl_attach(void *pdev);
7162 +extern void osl_detach(osl_t *osh);
7163 +
7164 +/* host/bus architecture-specific byte swap */
7165 +#define BUS_SWAP32(v) (v)
7166 +
7167 +/* general purpose memory allocation */
7168 +
7169 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7170 +#define MFREE(osh, addr, size) kfree(addr);
7171 +
7172 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7173 +
7174 +extern void *osl_malloc(osl_t *osh, uint size);
7175 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7176 +extern uint osl_malloced(osl_t *osh);
7177 +extern uint osl_malloc_failed(osl_t *osh);
7178 +
7179 +/* allocate/free shared (dma-able) consistent memory */
7180 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7181 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7182 + osl_dma_alloc_consistent((osh), (size), (pap))
7183 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7184 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7185 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7186 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7187 +
7188 +/* map/unmap direction */
7189 +#define DMA_TX 1
7190 +#define DMA_RX 2
7191 +
7192 +/* register access macros */
7193 +#if defined(BCMJTAG)
7194 +#include <bcmjtag.h>
7195 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7196 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7197 +#endif
7198 +
7199 +/*
7200 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7201 + * Macros expand to calls to functions defined in linux_osl.c .
7202 + */
7203 +#ifndef BINOSL
7204 +
7205 +/* string library, kernel mode */
7206 +#define printf(fmt, args...) printk(fmt, ## args)
7207 +#include <linux/kernel.h>
7208 +#include <linux/string.h>
7209 +
7210 +/* register access macros */
7211 +#if !defined(BCMJTAG)
7212 +#ifndef IL_BIGENDIAN
7213 +#define R_REG(r) ( \
7214 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7215 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7216 + readl((volatile uint32*)(r)) \
7217 +)
7218 +#define W_REG(r, v) do { \
7219 + switch (sizeof(*(r))) { \
7220 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7221 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7222 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7223 + } \
7224 +} while (0)
7225 +#else /* IL_BIGENDIAN */
7226 +#define R_REG(r) ({ \
7227 + __typeof(*(r)) __osl_v; \
7228 + switch (sizeof(*(r))) { \
7229 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7230 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7231 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7232 + } \
7233 + __osl_v; \
7234 +})
7235 +#define W_REG(r, v) do { \
7236 + switch (sizeof(*(r))) { \
7237 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7238 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7239 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7240 + } \
7241 +} while (0)
7242 +#endif
7243 +#endif
7244 +
7245 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7246 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7247 +
7248 +/* bcopy, bcmp, and bzero */
7249 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7250 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7251 +#define bzero(b, len) memset((b), '\0', (len))
7252 +
7253 +/* uncached virtual address */
7254 +#ifdef mips
7255 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7256 +#include <asm/addrspace.h>
7257 +#else
7258 +#define OSL_UNCACHED(va) (va)
7259 +#endif
7260 +
7261 +/* get processor cycle count */
7262 +#if defined(mips)
7263 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7264 +#elif defined(__i386__)
7265 +#define OSL_GETCYCLES(x) rdtscl((x))
7266 +#else
7267 +#define OSL_GETCYCLES(x) ((x) = 0)
7268 +#endif
7269 +
7270 +/* dereference an address that may cause a bus exception */
7271 +#ifdef mips
7272 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7273 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7274 +#else
7275 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7276 +#include <asm/paccess.h>
7277 +#endif
7278 +#else
7279 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7280 +#endif
7281 +
7282 +/* map/unmap physical to virtual I/O */
7283 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7284 +#define REG_UNMAP(va) iounmap((void *)(va))
7285 +
7286 +/* shared (dma-able) memory access macros */
7287 +#define R_SM(r) *(r)
7288 +#define W_SM(r, v) (*(r) = (v))
7289 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7290 +
7291 +/* packet primitives */
7292 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7293 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7294 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7295 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7296 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7297 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7298 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7299 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7300 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7301 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7302 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7303 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7304 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7305 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7306 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7307 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7308 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7309 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7310 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7311 +extern void osl_pktfree(void *skb);
7312 +
7313 +#else /* BINOSL */
7314 +
7315 +/* string library */
7316 +#ifndef LINUX_OSL
7317 +#undef printf
7318 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7319 +#undef sprintf
7320 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7321 +#undef strcmp
7322 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7323 +#undef strncmp
7324 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7325 +#undef strlen
7326 +#define strlen(s) osl_strlen((s))
7327 +#undef strcpy
7328 +#define strcpy(d, s) osl_strcpy((d), (s))
7329 +#undef strncpy
7330 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7331 +#endif
7332 +extern int osl_printf(const char *format, ...);
7333 +extern int osl_sprintf(char *buf, const char *format, ...);
7334 +extern int osl_strcmp(const char *s1, const char *s2);
7335 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7336 +extern int osl_strlen(const char *s);
7337 +extern char* osl_strcpy(char *d, const char *s);
7338 +extern char* osl_strncpy(char *d, const char *s, uint n);
7339 +
7340 +/* register access macros */
7341 +#if !defined(BCMJTAG)
7342 +#define R_REG(r) ( \
7343 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7344 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7345 + osl_readl((volatile uint32*)(r)) \
7346 +)
7347 +#define W_REG(r, v) do { \
7348 + switch (sizeof(*(r))) { \
7349 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7350 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7351 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7352 + } \
7353 +} while (0)
7354 +#endif
7355 +
7356 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7357 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7358 +extern uint8 osl_readb(volatile uint8 *r);
7359 +extern uint16 osl_readw(volatile uint16 *r);
7360 +extern uint32 osl_readl(volatile uint32 *r);
7361 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7362 +extern void osl_writew(uint16 v, volatile uint16 *r);
7363 +extern void osl_writel(uint32 v, volatile uint32 *r);
7364 +
7365 +/* bcopy, bcmp, and bzero */
7366 +extern void bcopy(const void *src, void *dst, int len);
7367 +extern int bcmp(const void *b1, const void *b2, int len);
7368 +extern void bzero(void *b, int len);
7369 +
7370 +/* uncached virtual address */
7371 +#define OSL_UNCACHED(va) osl_uncached((va))
7372 +extern void *osl_uncached(void *va);
7373 +
7374 +/* get processor cycle count */
7375 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7376 +extern uint osl_getcycles(void);
7377 +
7378 +/* dereference an address that may target abort */
7379 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7380 +extern int osl_busprobe(uint32 *val, uint32 addr);
7381 +
7382 +/* map/unmap physical to virtual */
7383 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7384 +#define REG_UNMAP(va) osl_reg_unmap((va))
7385 +extern void *osl_reg_map(uint32 pa, uint size);
7386 +extern void osl_reg_unmap(void *va);
7387 +
7388 +/* shared (dma-able) memory access macros */
7389 +#define R_SM(r) *(r)
7390 +#define W_SM(r, v) (*(r) = (v))
7391 +#define BZERO_SM(r, len) bzero((r), (len))
7392 +
7393 +/* packet primitives */
7394 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7395 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7396 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7397 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7398 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7399 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7400 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7401 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7402 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7403 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7404 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7405 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7406 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7407 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7408 +#define PKTLINK(skb) osl_pktlink((skb))
7409 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7410 +#define PKTPRIO(skb) osl_pktprio((skb))
7411 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7412 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7413 +extern void osl_pktfree(void *skb);
7414 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7415 +extern uint osl_pktlen(osl_t *osh, void *skb);
7416 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7417 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7418 +extern void *osl_pktnext(osl_t *osh, void *skb);
7419 +extern void osl_pktsetnext(void *skb, void *x);
7420 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7421 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7422 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7423 +extern void *osl_pktdup(osl_t *osh, void *skb);
7424 +extern void *osl_pktcookie(void *skb);
7425 +extern void osl_pktsetcookie(void *skb, void *x);
7426 +extern void *osl_pktlink(void *skb);
7427 +extern void osl_pktsetlink(void *skb, void *x);
7428 +extern uint osl_pktprio(void *skb);
7429 +extern void osl_pktsetprio(void *skb, uint x);
7430 +
7431 +#endif /* BINOSL */
7432 +
7433 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7434 +extern int osl_error(int bcmerror);
7435 +
7436 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7437 +#define PKTBUFSZ 2048
7438 +
7439 +#endif /* _linux_osl_h_ */
7440 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7441 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7442 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-12-15 16:02:45.467929000 +0100
7443 @@ -0,0 +1,389 @@
7444 +/*
7445 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7446 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7447 + *
7448 + * Copyright 2005, Broadcom Corporation
7449 + * All Rights Reserved.
7450 + *
7451 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7452 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7453 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7454 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7455 + *
7456 + * $Id$
7457 + */
7458 +
7459 +#ifndef _linuxver_h_
7460 +#define _linuxver_h_
7461 +
7462 +#include <linux/config.h>
7463 +#include <linux/version.h>
7464 +
7465 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7466 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7467 +#ifdef __UNDEF_NO_VERSION__
7468 +#undef __NO_VERSION__
7469 +#else
7470 +#define __NO_VERSION__
7471 +#endif
7472 +#endif
7473 +
7474 +#if defined(MODULE) && defined(MODVERSIONS)
7475 +#include <linux/modversions.h>
7476 +#endif
7477 +
7478 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7479 +#include <linux/moduleparam.h>
7480 +#endif
7481 +
7482 +
7483 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7484 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7485 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7486 +#endif
7487 +
7488 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7489 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7490 +#include <linux/malloc.h>
7491 +#else
7492 +#include <linux/slab.h>
7493 +#endif
7494 +
7495 +#include <linux/types.h>
7496 +#include <linux/init.h>
7497 +#include <linux/mm.h>
7498 +#include <linux/string.h>
7499 +#include <linux/pci.h>
7500 +#include <linux/interrupt.h>
7501 +#include <linux/netdevice.h>
7502 +#include <asm/io.h>
7503 +
7504 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7505 +#include <linux/workqueue.h>
7506 +#else
7507 +#include <linux/tqueue.h>
7508 +#ifndef work_struct
7509 +#define work_struct tq_struct
7510 +#endif
7511 +#ifndef INIT_WORK
7512 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7513 +#endif
7514 +#ifndef schedule_work
7515 +#define schedule_work(_work) schedule_task((_work))
7516 +#endif
7517 +#ifndef flush_scheduled_work
7518 +#define flush_scheduled_work() flush_scheduled_tasks()
7519 +#endif
7520 +#endif
7521 +
7522 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7523 +/* Some distributions have their own 2.6.x compatibility layers */
7524 +#ifndef IRQ_NONE
7525 +typedef void irqreturn_t;
7526 +#define IRQ_NONE
7527 +#define IRQ_HANDLED
7528 +#define IRQ_RETVAL(x)
7529 +#endif
7530 +#else
7531 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7532 +#endif
7533 +
7534 +#ifndef __exit
7535 +#define __exit
7536 +#endif
7537 +#ifndef __devexit
7538 +#define __devexit
7539 +#endif
7540 +#ifndef __devinit
7541 +#define __devinit __init
7542 +#endif
7543 +#ifndef __devinitdata
7544 +#define __devinitdata
7545 +#endif
7546 +#ifndef __devexit_p
7547 +#define __devexit_p(x) x
7548 +#endif
7549 +
7550 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7551 +
7552 +#define pci_get_drvdata(dev) (dev)->sysdata
7553 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7554 +
7555 +/*
7556 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7557 + */
7558 +
7559 +struct pci_device_id {
7560 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7561 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7562 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7563 + unsigned long driver_data; /* Data private to the driver */
7564 +};
7565 +
7566 +struct pci_driver {
7567 + struct list_head node;
7568 + char *name;
7569 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7570 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7571 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7572 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7573 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7574 +};
7575 +
7576 +#define MODULE_DEVICE_TABLE(type, name)
7577 +#define PCI_ANY_ID (~0)
7578 +
7579 +/* compatpci.c */
7580 +#define pci_module_init pci_register_driver
7581 +extern int pci_register_driver(struct pci_driver *drv);
7582 +extern void pci_unregister_driver(struct pci_driver *drv);
7583 +
7584 +#endif /* PCI registration */
7585 +
7586 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7587 +#ifdef MODULE
7588 +#define module_init(x) int init_module(void) { return x(); }
7589 +#define module_exit(x) void cleanup_module(void) { x(); }
7590 +#else
7591 +#define module_init(x) __initcall(x);
7592 +#define module_exit(x) __exitcall(x);
7593 +#endif
7594 +#endif
7595 +
7596 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7597 +#define list_for_each(pos, head) \
7598 + for (pos = (head)->next; pos != (head); pos = pos->next)
7599 +#endif
7600 +
7601 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7602 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7603 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7604 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7605 +#endif
7606 +
7607 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7608 +#define pci_enable_device(dev) do { } while (0)
7609 +#endif
7610 +
7611 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7612 +#define net_device device
7613 +#endif
7614 +
7615 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7616 +
7617 +/*
7618 + * DMA mapping
7619 + *
7620 + * See linux/Documentation/DMA-mapping.txt
7621 + */
7622 +
7623 +#ifndef PCI_DMA_TODEVICE
7624 +#define PCI_DMA_TODEVICE 1
7625 +#define PCI_DMA_FROMDEVICE 2
7626 +#endif
7627 +
7628 +typedef u32 dma_addr_t;
7629 +
7630 +/* Pure 2^n version of get_order */
7631 +static inline int get_order(unsigned long size)
7632 +{
7633 + int order;
7634 +
7635 + size = (size-1) >> (PAGE_SHIFT-1);
7636 + order = -1;
7637 + do {
7638 + size >>= 1;
7639 + order++;
7640 + } while (size);
7641 + return order;
7642 +}
7643 +
7644 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7645 + dma_addr_t *dma_handle)
7646 +{
7647 + void *ret;
7648 + int gfp = GFP_ATOMIC | GFP_DMA;
7649 +
7650 + ret = (void *)__get_free_pages(gfp, get_order(size));
7651 +
7652 + if (ret != NULL) {
7653 + memset(ret, 0, size);
7654 + *dma_handle = virt_to_bus(ret);
7655 + }
7656 + return ret;
7657 +}
7658 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7659 + void *vaddr, dma_addr_t dma_handle)
7660 +{
7661 + free_pages((unsigned long)vaddr, get_order(size));
7662 +}
7663 +#ifdef ILSIM
7664 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7665 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7666 +#else
7667 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7668 +#define pci_unmap_single(cookie, address, size, dir)
7669 +#endif
7670 +
7671 +#endif /* DMA mapping */
7672 +
7673 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7674 +
7675 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7676 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7677 +
7678 +/* pcmcia-cs provides its own netdevice compatibility layer */
7679 +#ifndef _COMPAT_NETDEVICE_H
7680 +
7681 +/*
7682 + * SoftNet
7683 + *
7684 + * For pre-softnet kernels we need to tell the upper layer not to
7685 + * re-enter start_xmit() while we are in there. However softnet
7686 + * guarantees not to enter while we are in there so there is no need
7687 + * to do the netif_stop_queue() dance unless the transmit queue really
7688 + * gets stuck. This should also improve performance according to tests
7689 + * done by Aman Singla.
7690 + */
7691 +
7692 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7693 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7694 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7695 +
7696 +static inline void netif_start_queue(struct net_device *dev)
7697 +{
7698 + dev->tbusy = 0;
7699 + dev->interrupt = 0;
7700 + dev->start = 1;
7701 +}
7702 +
7703 +#define netif_queue_stopped(dev) (dev)->tbusy
7704 +#define netif_running(dev) (dev)->start
7705 +
7706 +#endif /* _COMPAT_NETDEVICE_H */
7707 +
7708 +#define netif_device_attach(dev) netif_start_queue(dev)
7709 +#define netif_device_detach(dev) netif_stop_queue(dev)
7710 +
7711 +/* 2.4.x renamed bottom halves to tasklets */
7712 +#define tasklet_struct tq_struct
7713 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7714 +{
7715 + queue_task(tasklet, &tq_immediate);
7716 + mark_bh(IMMEDIATE_BH);
7717 +}
7718 +
7719 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7720 + void (*func)(unsigned long),
7721 + unsigned long data)
7722 +{
7723 + tasklet->next = NULL;
7724 + tasklet->sync = 0;
7725 + tasklet->routine = (void (*)(void *))func;
7726 + tasklet->data = (void *)data;
7727 +}
7728 +#define tasklet_kill(tasklet) {do{} while(0);}
7729 +
7730 +/* 2.4.x introduced del_timer_sync() */
7731 +#define del_timer_sync(timer) del_timer(timer)
7732 +
7733 +#else
7734 +
7735 +#define netif_down(dev)
7736 +
7737 +#endif /* SoftNet */
7738 +
7739 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7740 +
7741 +/*
7742 + * Emit code to initialise a tq_struct's routine and data pointers
7743 + */
7744 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7745 + do { \
7746 + (_tq)->routine = _routine; \
7747 + (_tq)->data = _data; \
7748 + } while (0)
7749 +
7750 +/*
7751 + * Emit code to initialise all of a tq_struct
7752 + */
7753 +#define INIT_TQUEUE(_tq, _routine, _data) \
7754 + do { \
7755 + INIT_LIST_HEAD(&(_tq)->list); \
7756 + (_tq)->sync = 0; \
7757 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7758 + } while (0)
7759 +
7760 +#endif
7761 +
7762 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7763 +
7764 +/* Power management related routines */
7765 +
7766 +static inline int
7767 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7768 +{
7769 + int i;
7770 + if (buffer) {
7771 + for (i = 0; i < 16; i++)
7772 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7773 + }
7774 + return 0;
7775 +}
7776 +
7777 +static inline int
7778 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7779 +{
7780 + int i;
7781 +
7782 + if (buffer) {
7783 + for (i = 0; i < 16; i++)
7784 + pci_write_config_dword(dev,i * 4, buffer[i]);
7785 + }
7786 + /*
7787 + * otherwise, write the context information we know from bootup.
7788 + * This works around a problem where warm-booting from Windows
7789 + * combined with a D3(hot)->D0 transition causes PCI config
7790 + * header data to be forgotten.
7791 + */
7792 + else {
7793 + for (i = 0; i < 6; i ++)
7794 + pci_write_config_dword(dev,
7795 + PCI_BASE_ADDRESS_0 + (i * 4),
7796 + pci_resource_start(dev, i));
7797 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7798 + }
7799 + return 0;
7800 +}
7801 +
7802 +#endif /* PCI power management */
7803 +
7804 +/* Old cp0 access macros deprecated in 2.4.19 */
7805 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7806 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7807 +#endif
7808 +
7809 +/* Module refcount handled internally in 2.6.x */
7810 +#ifndef SET_MODULE_OWNER
7811 +#define SET_MODULE_OWNER(dev) do {} while (0)
7812 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7813 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7814 +#else
7815 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7816 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7817 +#endif
7818 +
7819 +#ifndef SET_NETDEV_DEV
7820 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7821 +#endif
7822 +
7823 +#ifndef HAVE_FREE_NETDEV
7824 +#define free_netdev(dev) kfree(dev)
7825 +#endif
7826 +
7827 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7828 +/* struct packet_type redefined in 2.6.x */
7829 +#define af_packet_priv data
7830 +#endif
7831 +
7832 +#endif /* _linuxver_h_ */
7833 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7834 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7835 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-12-15 16:47:29.886633750 +0100
7836 @@ -0,0 +1,552 @@
7837 +/*
7838 + * HND Run Time Environment for standalone MIPS programs.
7839 + *
7840 + * Copyright 2005, Broadcom Corporation
7841 + * All Rights Reserved.
7842 + *
7843 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7844 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7845 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7846 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7847 + *
7848 + * $Id$
7849 + */
7850 +
7851 +#ifndef _MISPINC_H
7852 +#define _MISPINC_H
7853 +
7854 +
7855 +/* MIPS defines */
7856 +
7857 +#ifdef _LANGUAGE_ASSEMBLY
7858 +
7859 +/*
7860 + * Symbolic register names for 32 bit ABI
7861 + */
7862 +#define zero $0 /* wired zero */
7863 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7864 +#define v0 $2 /* return value */
7865 +#define v1 $3
7866 +#define a0 $4 /* argument registers */
7867 +#define a1 $5
7868 +#define a2 $6
7869 +#define a3 $7
7870 +#define t0 $8 /* caller saved */
7871 +#define t1 $9
7872 +#define t2 $10
7873 +#define t3 $11
7874 +#define t4 $12
7875 +#define t5 $13
7876 +#define t6 $14
7877 +#define t7 $15
7878 +#define s0 $16 /* callee saved */
7879 +#define s1 $17
7880 +#define s2 $18
7881 +#define s3 $19
7882 +#define s4 $20
7883 +#define s5 $21
7884 +#define s6 $22
7885 +#define s7 $23
7886 +#define t8 $24 /* caller saved */
7887 +#define t9 $25
7888 +#define jp $25 /* PIC jump register */
7889 +#define k0 $26 /* kernel scratch */
7890 +#define k1 $27
7891 +#define gp $28 /* global pointer */
7892 +#define sp $29 /* stack pointer */
7893 +#define fp $30 /* frame pointer */
7894 +#define s8 $30 /* same like fp! */
7895 +#define ra $31 /* return address */
7896 +
7897 +
7898 +/*
7899 + * CP0 Registers
7900 + */
7901 +
7902 +#define C0_INX $0
7903 +#define C0_RAND $1
7904 +#define C0_TLBLO0 $2
7905 +#define C0_TLBLO C0_TLBLO0
7906 +#define C0_TLBLO1 $3
7907 +#define C0_CTEXT $4
7908 +#define C0_PGMASK $5
7909 +#define C0_WIRED $6
7910 +#define C0_BADVADDR $8
7911 +#define C0_COUNT $9
7912 +#define C0_TLBHI $10
7913 +#define C0_COMPARE $11
7914 +#define C0_SR $12
7915 +#define C0_STATUS C0_SR
7916 +#define C0_CAUSE $13
7917 +#define C0_EPC $14
7918 +#define C0_PRID $15
7919 +#define C0_CONFIG $16
7920 +#define C0_LLADDR $17
7921 +#define C0_WATCHLO $18
7922 +#define C0_WATCHHI $19
7923 +#define C0_XCTEXT $20
7924 +#define C0_DIAGNOSTIC $22
7925 +#define C0_BROADCOM C0_DIAGNOSTIC
7926 +#define C0_PERFORMANCE $25
7927 +#define C0_ECC $26
7928 +#define C0_CACHEERR $27
7929 +#define C0_TAGLO $28
7930 +#define C0_TAGHI $29
7931 +#define C0_ERREPC $30
7932 +#define C0_DESAVE $31
7933 +
7934 +/*
7935 + * LEAF - declare leaf routine
7936 + */
7937 +#define LEAF(symbol) \
7938 + .globl symbol; \
7939 + .align 2; \
7940 + .type symbol,@function; \
7941 + .ent symbol,0; \
7942 +symbol: .frame sp,0,ra
7943 +
7944 +/*
7945 + * END - mark end of function
7946 + */
7947 +#define END(function) \
7948 + .end function; \
7949 + .size function,.-function
7950 +
7951 +#define _ULCAST_
7952 +
7953 +#else
7954 +
7955 +/*
7956 + * The following macros are especially useful for __asm__
7957 + * inline assembler.
7958 + */
7959 +#ifndef __STR
7960 +#define __STR(x) #x
7961 +#endif
7962 +#ifndef STR
7963 +#define STR(x) __STR(x)
7964 +#endif
7965 +
7966 +#define _ULCAST_ (unsigned long)
7967 +
7968 +
7969 +/*
7970 + * CP0 Registers
7971 + */
7972 +
7973 +#define C0_INX 0 /* CP0: TLB Index */
7974 +#define C0_RAND 1 /* CP0: TLB Random */
7975 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
7976 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
7977 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
7978 +#define C0_CTEXT 4 /* CP0: Context */
7979 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
7980 +#define C0_WIRED 6 /* CP0: TLB Wired */
7981 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
7982 +#define C0_COUNT 9 /* CP0: Count */
7983 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
7984 +#define C0_COMPARE 11 /* CP0: Compare */
7985 +#define C0_SR 12 /* CP0: Processor Status */
7986 +#define C0_STATUS C0_SR /* CP0: Processor Status */
7987 +#define C0_CAUSE 13 /* CP0: Exception Cause */
7988 +#define C0_EPC 14 /* CP0: Exception PC */
7989 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
7990 +#define C0_CONFIG 16 /* CP0: Config */
7991 +#define C0_LLADDR 17 /* CP0: LLAddr */
7992 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
7993 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
7994 +#define C0_XCTEXT 20 /* CP0: XContext */
7995 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
7996 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
7997 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
7998 +#define C0_ECC 26 /* CP0: ECC */
7999 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8000 +#define C0_TAGLO 28 /* CP0: TagLo */
8001 +#define C0_TAGHI 29 /* CP0: TagHi */
8002 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8003 +#define C0_DESAVE 31 /* CP0: DebugSave */
8004 +
8005 +#endif /* _LANGUAGE_ASSEMBLY */
8006 +
8007 +/*
8008 + * Memory segments (32bit kernel mode addresses)
8009 + */
8010 +#undef KUSEG
8011 +#undef KSEG0
8012 +#undef KSEG1
8013 +#undef KSEG2
8014 +#undef KSEG3
8015 +#define KUSEG 0x00000000
8016 +#define KSEG0 0x80000000
8017 +#define KSEG1 0xa0000000
8018 +#define KSEG2 0xc0000000
8019 +#define KSEG3 0xe0000000
8020 +#define PHYSADDR_MASK 0x1fffffff
8021 +
8022 +/*
8023 + * Map an address to a certain kernel segment
8024 + */
8025 +#undef PHYSADDR
8026 +#undef KSEG0ADDR
8027 +#undef KSEG1ADDR
8028 +#undef KSEG2ADDR
8029 +#undef KSEG3ADDR
8030 +
8031 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8032 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8033 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8034 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8035 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8036 +
8037 +
8038 +#ifndef Index_Invalidate_I
8039 +/*
8040 + * Cache Operations
8041 + */
8042 +#define Index_Invalidate_I 0x00
8043 +#define Index_Writeback_Inv_D 0x01
8044 +#define Index_Invalidate_SI 0x02
8045 +#define Index_Writeback_Inv_SD 0x03
8046 +#define Index_Load_Tag_I 0x04
8047 +#define Index_Load_Tag_D 0x05
8048 +#define Index_Load_Tag_SI 0x06
8049 +#define Index_Load_Tag_SD 0x07
8050 +#define Index_Store_Tag_I 0x08
8051 +#define Index_Store_Tag_D 0x09
8052 +#define Index_Store_Tag_SI 0x0A
8053 +#define Index_Store_Tag_SD 0x0B
8054 +#define Create_Dirty_Excl_D 0x0d
8055 +#define Create_Dirty_Excl_SD 0x0f
8056 +#define Hit_Invalidate_I 0x10
8057 +#define Hit_Invalidate_D 0x11
8058 +#define Hit_Invalidate_SI 0x12
8059 +#define Hit_Invalidate_SD 0x13
8060 +#define Fill_I 0x14
8061 +#define Hit_Writeback_Inv_D 0x15
8062 + /* 0x16 is unused */
8063 +#define Hit_Writeback_Inv_SD 0x17
8064 +#define R5K_Page_Invalidate_S 0x17
8065 +#define Hit_Writeback_I 0x18
8066 +#define Hit_Writeback_D 0x19
8067 + /* 0x1a is unused */
8068 +#define Hit_Writeback_SD 0x1b
8069 + /* 0x1c is unused */
8070 + /* 0x1e is unused */
8071 +#define Hit_Set_Virtual_SI 0x1e
8072 +#define Hit_Set_Virtual_SD 0x1f
8073 +#endif
8074 +
8075 +
8076 +/*
8077 + * R4x00 interrupt enable / cause bits
8078 + */
8079 +#define IE_SW0 (_ULCAST_(1) << 8)
8080 +#define IE_SW1 (_ULCAST_(1) << 9)
8081 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8082 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8083 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8084 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8085 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8086 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8087 +
8088 +#ifndef ST0_UM
8089 +/*
8090 + * Bitfields in the mips32 cp0 status register
8091 + */
8092 +#define ST0_IE 0x00000001
8093 +#define ST0_EXL 0x00000002
8094 +#define ST0_ERL 0x00000004
8095 +#define ST0_UM 0x00000010
8096 +#define ST0_SWINT0 0x00000100
8097 +#define ST0_SWINT1 0x00000200
8098 +#define ST0_HWINT0 0x00000400
8099 +#define ST0_HWINT1 0x00000800
8100 +#define ST0_HWINT2 0x00001000
8101 +#define ST0_HWINT3 0x00002000
8102 +#define ST0_HWINT4 0x00004000
8103 +#define ST0_HWINT5 0x00008000
8104 +#define ST0_IM 0x0000ff00
8105 +#define ST0_NMI 0x00080000
8106 +#define ST0_SR 0x00100000
8107 +#define ST0_TS 0x00200000
8108 +#define ST0_BEV 0x00400000
8109 +#define ST0_RE 0x02000000
8110 +#define ST0_RP 0x08000000
8111 +#define ST0_CU 0xf0000000
8112 +#define ST0_CU0 0x10000000
8113 +#define ST0_CU1 0x20000000
8114 +#define ST0_CU2 0x40000000
8115 +#define ST0_CU3 0x80000000
8116 +#endif
8117 +
8118 +
8119 +/*
8120 + * Bitfields in the mips32 cp0 cause register
8121 + */
8122 +#define C_EXC 0x0000007c
8123 +#define C_EXC_SHIFT 2
8124 +#define C_INT 0x0000ff00
8125 +#define C_INT_SHIFT 8
8126 +#define C_SW0 (_ULCAST_(1) << 8)
8127 +#define C_SW1 (_ULCAST_(1) << 9)
8128 +#define C_IRQ0 (_ULCAST_(1) << 10)
8129 +#define C_IRQ1 (_ULCAST_(1) << 11)
8130 +#define C_IRQ2 (_ULCAST_(1) << 12)
8131 +#define C_IRQ3 (_ULCAST_(1) << 13)
8132 +#define C_IRQ4 (_ULCAST_(1) << 14)
8133 +#define C_IRQ5 (_ULCAST_(1) << 15)
8134 +#define C_WP 0x00400000
8135 +#define C_IV 0x00800000
8136 +#define C_CE 0x30000000
8137 +#define C_CE_SHIFT 28
8138 +#define C_BD 0x80000000
8139 +
8140 +/* Values in C_EXC */
8141 +#define EXC_INT 0
8142 +#define EXC_TLBM 1
8143 +#define EXC_TLBL 2
8144 +#define EXC_TLBS 3
8145 +#define EXC_AEL 4
8146 +#define EXC_AES 5
8147 +#define EXC_IBE 6
8148 +#define EXC_DBE 7
8149 +#define EXC_SYS 8
8150 +#define EXC_BPT 9
8151 +#define EXC_RI 10
8152 +#define EXC_CU 11
8153 +#define EXC_OV 12
8154 +#define EXC_TR 13
8155 +#define EXC_WATCH 23
8156 +#define EXC_MCHK 24
8157 +
8158 +
8159 +/*
8160 + * Bits in the cp0 config register.
8161 + */
8162 +#define CONF_CM_CACHABLE_NO_WA 0
8163 +#define CONF_CM_CACHABLE_WA 1
8164 +#define CONF_CM_UNCACHED 2
8165 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8166 +#define CONF_CM_CACHABLE_CE 4
8167 +#define CONF_CM_CACHABLE_COW 5
8168 +#define CONF_CM_CACHABLE_CUW 6
8169 +#define CONF_CM_CACHABLE_ACCELERATED 7
8170 +#define CONF_CM_CMASK 7
8171 +#define CONF_CU (_ULCAST_(1) << 3)
8172 +#define CONF_DB (_ULCAST_(1) << 4)
8173 +#define CONF_IB (_ULCAST_(1) << 5)
8174 +#define CONF_SE (_ULCAST_(1) << 12)
8175 +#define CONF_SC (_ULCAST_(1) << 17)
8176 +#define CONF_AC (_ULCAST_(1) << 23)
8177 +#define CONF_HALT (_ULCAST_(1) << 25)
8178 +
8179 +
8180 +/*
8181 + * Bits in the cp0 config register select 1.
8182 + */
8183 +#define CONF1_FP 0x00000001 /* FPU present */
8184 +#define CONF1_EP 0x00000002 /* EJTAG present */
8185 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8186 +#define CONF1_WR 0x00000008 /* Watch registers present */
8187 +#define CONF1_PC 0x00000010 /* Performance counters present */
8188 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8189 +#define CONF1_DA_MASK 0x00000380
8190 +#define CONF1_DA_BASE 1
8191 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8192 +#define CONF1_DL_MASK 0x00001c00
8193 +#define CONF1_DL_BASE 2
8194 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8195 +#define CONF1_DS_MASK 0x0000e000
8196 +#define CONF1_DS_BASE 64
8197 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8198 +#define CONF1_IA_MASK 0x00070000
8199 +#define CONF1_IA_BASE 1
8200 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8201 +#define CONF1_IL_MASK 0x00380000
8202 +#define CONF1_IL_BASE 2
8203 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8204 +#define CONF1_IS_MASK 0x01c00000
8205 +#define CONF1_IS_BASE 64
8206 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8207 +#define CONF1_MS_SHIFT 25
8208 +
8209 +/* PRID register */
8210 +#define PRID_COPT_MASK 0xff000000
8211 +#define PRID_COMP_MASK 0x00ff0000
8212 +#define PRID_IMP_MASK 0x0000ff00
8213 +#define PRID_REV_MASK 0x000000ff
8214 +
8215 +#define PRID_COMP_LEGACY 0x000000
8216 +#define PRID_COMP_MIPS 0x010000
8217 +#define PRID_COMP_BROADCOM 0x020000
8218 +#define PRID_COMP_ALCHEMY 0x030000
8219 +#define PRID_COMP_SIBYTE 0x040000
8220 +#define PRID_IMP_BCM4710 0x4000
8221 +#define PRID_IMP_BCM3302 0x9000
8222 +#define PRID_IMP_BCM3303 0x9100
8223 +
8224 +#define PRID_IMP_UNKNOWN 0xff00
8225 +
8226 +#define BCM330X(id) \
8227 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8228 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8229 +
8230 +/* Bits in C0_BROADCOM */
8231 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8232 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8233 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8234 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8235 +
8236 +/* PreFetch Cache aka Read Ahead Cache */
8237 +
8238 +#define PFC_CR0 0xff400000 /* control reg 0 */
8239 +#define PFC_CR1 0xff400004 /* control reg 1 */
8240 +
8241 +/* PFC operations */
8242 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8243 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8244 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8245 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8246 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8247 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8248 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8249 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8250 +#define PFC_BRR 0x40000000 /* Bus error indication */
8251 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8252 +
8253 +/* Handy defaults */
8254 +#define PFC_DISABLED 0
8255 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8256 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8257 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8258 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8259 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8260 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8261 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8262 +
8263 +
8264 +/*
8265 + * These are the UART port assignments, expressed as offsets from the base
8266 + * register. These assignments should hold for any serial port based on
8267 + * a 8250, 16450, or 16550(A).
8268 + */
8269 +
8270 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8271 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8272 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8273 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8274 +#define UART_LCR 3 /* Out: Line Control Register */
8275 +#define UART_MCR 4 /* Out: Modem Control Register */
8276 +#define UART_LSR 5 /* In: Line Status Register */
8277 +#define UART_MSR 6 /* In: Modem Status Register */
8278 +#define UART_SCR 7 /* I/O: Scratch Register */
8279 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8280 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8281 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8282 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8283 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8284 +
8285 +
8286 +#ifndef _LANGUAGE_ASSEMBLY
8287 +
8288 +/*
8289 + * Macros to access the system control coprocessor
8290 + */
8291 +
8292 +#define MFC0(source, sel) \
8293 +({ \
8294 + int __res; \
8295 + __asm__ __volatile__( \
8296 + ".set\tnoreorder\n\t" \
8297 + ".set\tnoat\n\t" \
8298 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8299 + "move\t%0,$1\n\t" \
8300 + ".set\tat\n\t" \
8301 + ".set\treorder" \
8302 + :"=r" (__res) \
8303 + : \
8304 + :"$1"); \
8305 + __res; \
8306 +})
8307 +
8308 +#define MTC0(source, sel, value) \
8309 +do { \
8310 + __asm__ __volatile__( \
8311 + ".set\tnoreorder\n\t" \
8312 + ".set\tnoat\n\t" \
8313 + "move\t$1,%z0\n\t" \
8314 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8315 + ".set\tat\n\t" \
8316 + ".set\treorder" \
8317 + : \
8318 + :"jr" (value) \
8319 + :"$1"); \
8320 +} while (0)
8321 +
8322 +#define get_c0_count() \
8323 +({ \
8324 + int __res; \
8325 + __asm__ __volatile__( \
8326 + ".set\tnoreorder\n\t" \
8327 + ".set\tnoat\n\t" \
8328 + "mfc0\t%0,$9\n\t" \
8329 + ".set\tat\n\t" \
8330 + ".set\treorder" \
8331 + :"=r" (__res)); \
8332 + __res; \
8333 +})
8334 +
8335 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8336 +{
8337 + uint lsz, sets, ways;
8338 +
8339 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8340 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8341 + lsz = CONF1_IL_BASE << lsz;
8342 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8343 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8344 + *size = lsz * sets * ways;
8345 + *lsize = lsz;
8346 +}
8347 +
8348 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8349 +{
8350 + uint lsz, sets, ways;
8351 +
8352 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8353 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8354 + lsz = CONF1_DL_BASE << lsz;
8355 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8356 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8357 + *size = lsz * sets * ways;
8358 + *lsize = lsz;
8359 +}
8360 +
8361 +#define cache_op(base, op) \
8362 + __asm__ __volatile__(" \
8363 + .set noreorder; \
8364 + .set mips3; \
8365 + cache %1, (%0); \
8366 + .set mips0; \
8367 + .set reorder" \
8368 + : \
8369 + : "r" (base), \
8370 + "i" (op));
8371 +
8372 +#define cache_unroll4(base, delta, op) \
8373 + __asm__ __volatile__(" \
8374 + .set noreorder; \
8375 + .set mips3; \
8376 + cache %1,0(%0); \
8377 + cache %1,delta(%0); \
8378 + cache %1,(2 * delta)(%0); \
8379 + cache %1,(3 * delta)(%0); \
8380 + .set mips0; \
8381 + .set reorder" \
8382 + : \
8383 + : "r" (base), \
8384 + "i" (op));
8385 +
8386 +#endif /* !_LANGUAGE_ASSEMBLY */
8387 +
8388 +#endif /* _MISPINC_H */
8389 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8390 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8391 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-12-15 15:35:08.321801750 +0100
8392 @@ -0,0 +1,42 @@
8393 +/*
8394 + * OS Abstraction Layer
8395 + *
8396 + * Copyright 2005, Broadcom Corporation
8397 + * All Rights Reserved.
8398 + *
8399 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8400 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8401 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8402 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8403 + * $Id$
8404 + */
8405 +
8406 +#ifndef _osl_h_
8407 +#define _osl_h_
8408 +
8409 +/* osl handle type forward declaration */
8410 +typedef struct os_handle osl_t;
8411 +
8412 +#if defined(linux)
8413 +#include <linux_osl.h>
8414 +#elif defined(NDIS)
8415 +#include <ndis_osl.h>
8416 +#elif defined(_CFE_)
8417 +#include <cfe_osl.h>
8418 +#elif defined(_HNDRTE_)
8419 +#include <hndrte_osl.h>
8420 +#elif defined(_MINOSL_)
8421 +#include <min_osl.h>
8422 +#elif PMON
8423 +#include <pmon_osl.h>
8424 +#elif defined(MACOSX)
8425 +#include <macosx_osl.h>
8426 +#else
8427 +#error "Unsupported OSL requested"
8428 +#endif
8429 +
8430 +/* handy */
8431 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8432 +#define MAXPRIO 7 /* 0-7 */
8433 +
8434 +#endif /* _osl_h_ */
8435 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8436 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8437 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-12-15 15:36:31.719013750 +0100
8438 @@ -0,0 +1,398 @@
8439 +/*
8440 + * pcicfg.h: PCI configuration constants and structures.
8441 + *
8442 + * Copyright 2005, Broadcom Corporation
8443 + * All Rights Reserved.
8444 + *
8445 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8446 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8447 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8448 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8449 + *
8450 + * $Id$
8451 + */
8452 +
8453 +#ifndef _h_pci_
8454 +#define _h_pci_
8455 +
8456 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8457 +#ifndef PCI_MAX_BUS
8458 +#define PCI_MAX_BUS 0x100
8459 +#endif
8460 +#ifndef PCI_MAX_DEVICES
8461 +#define PCI_MAX_DEVICES 0x20
8462 +#endif
8463 +#ifndef PCI_MAX_FUNCTION
8464 +#define PCI_MAX_FUNCTION 0x8
8465 +#endif
8466 +
8467 +#ifndef PCI_INVALID_VENDORID
8468 +#define PCI_INVALID_VENDORID 0xffff
8469 +#endif
8470 +#ifndef PCI_INVALID_DEVICEID
8471 +#define PCI_INVALID_DEVICEID 0xffff
8472 +#endif
8473 +
8474 +
8475 +/* Convert between bus-slot-function-register and config addresses */
8476 +
8477 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8478 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8479 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8480 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8481 +
8482 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8483 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8484 +#define PCICFG_FUN_MASK 7 /* Function mask */
8485 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8486 +
8487 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8488 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8489 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8490 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8491 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8492 +
8493 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8494 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8495 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8496 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8497 +
8498 +/* The actual config space */
8499 +
8500 +#define PCI_BAR_MAX 6
8501 +
8502 +#define PCI_ROM_BAR 8
8503 +
8504 +#define PCR_RSVDA_MAX 2
8505 +
8506 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8507 +
8508 +#define PCI_CAPPTR_PRESENT 0x0010
8509 +
8510 +typedef struct _pci_config_regs {
8511 + unsigned short vendor;
8512 + unsigned short device;
8513 + unsigned short command;
8514 + unsigned short status;
8515 + unsigned char rev_id;
8516 + unsigned char prog_if;
8517 + unsigned char sub_class;
8518 + unsigned char base_class;
8519 + unsigned char cache_line_size;
8520 + unsigned char latency_timer;
8521 + unsigned char header_type;
8522 + unsigned char bist;
8523 + unsigned long base[PCI_BAR_MAX];
8524 + unsigned long cardbus_cis;
8525 + unsigned short subsys_vendor;
8526 + unsigned short subsys_id;
8527 + unsigned long baserom;
8528 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8529 + unsigned char int_line;
8530 + unsigned char int_pin;
8531 + unsigned char min_gnt;
8532 + unsigned char max_lat;
8533 + unsigned char dev_dep[192];
8534 +} pci_config_regs;
8535 +
8536 +#define SZPCR (sizeof (pci_config_regs))
8537 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8538 +
8539 +/* A structure for the config registers is nice, but in most
8540 + * systems the config space is not memory mapped, so we need
8541 + * filed offsetts. :-(
8542 + */
8543 +#define PCI_CFG_VID 0
8544 +#define PCI_CFG_DID 2
8545 +#define PCI_CFG_CMD 4
8546 +#define PCI_CFG_STAT 6
8547 +#define PCI_CFG_REV 8
8548 +#define PCI_CFG_PROGIF 9
8549 +#define PCI_CFG_SUBCL 0xa
8550 +#define PCI_CFG_BASECL 0xb
8551 +#define PCI_CFG_CLSZ 0xc
8552 +#define PCI_CFG_LATTIM 0xd
8553 +#define PCI_CFG_HDR 0xe
8554 +#define PCI_CFG_BIST 0xf
8555 +#define PCI_CFG_BAR0 0x10
8556 +#define PCI_CFG_BAR1 0x14
8557 +#define PCI_CFG_BAR2 0x18
8558 +#define PCI_CFG_BAR3 0x1c
8559 +#define PCI_CFG_BAR4 0x20
8560 +#define PCI_CFG_BAR5 0x24
8561 +#define PCI_CFG_CIS 0x28
8562 +#define PCI_CFG_SVID 0x2c
8563 +#define PCI_CFG_SSID 0x2e
8564 +#define PCI_CFG_ROMBAR 0x30
8565 +#define PCI_CFG_CAPPTR 0x34
8566 +#define PCI_CFG_INT 0x3c
8567 +#define PCI_CFG_PIN 0x3d
8568 +#define PCI_CFG_MINGNT 0x3e
8569 +#define PCI_CFG_MAXLAT 0x3f
8570 +
8571 +/* Classes and subclasses */
8572 +
8573 +typedef enum {
8574 + PCI_CLASS_OLD = 0,
8575 + PCI_CLASS_DASDI,
8576 + PCI_CLASS_NET,
8577 + PCI_CLASS_DISPLAY,
8578 + PCI_CLASS_MMEDIA,
8579 + PCI_CLASS_MEMORY,
8580 + PCI_CLASS_BRIDGE,
8581 + PCI_CLASS_COMM,
8582 + PCI_CLASS_BASE,
8583 + PCI_CLASS_INPUT,
8584 + PCI_CLASS_DOCK,
8585 + PCI_CLASS_CPU,
8586 + PCI_CLASS_SERIAL,
8587 + PCI_CLASS_INTELLIGENT = 0xe,
8588 + PCI_CLASS_SATELLITE,
8589 + PCI_CLASS_CRYPT,
8590 + PCI_CLASS_DSP,
8591 + PCI_CLASS_MAX
8592 +} pci_classes;
8593 +
8594 +typedef enum {
8595 + PCI_DASDI_SCSI,
8596 + PCI_DASDI_IDE,
8597 + PCI_DASDI_FLOPPY,
8598 + PCI_DASDI_IPI,
8599 + PCI_DASDI_RAID,
8600 + PCI_DASDI_OTHER = 0x80
8601 +} pci_dasdi_subclasses;
8602 +
8603 +typedef enum {
8604 + PCI_NET_ETHER,
8605 + PCI_NET_TOKEN,
8606 + PCI_NET_FDDI,
8607 + PCI_NET_ATM,
8608 + PCI_NET_OTHER = 0x80
8609 +} pci_net_subclasses;
8610 +
8611 +typedef enum {
8612 + PCI_DISPLAY_VGA,
8613 + PCI_DISPLAY_XGA,
8614 + PCI_DISPLAY_3D,
8615 + PCI_DISPLAY_OTHER = 0x80
8616 +} pci_display_subclasses;
8617 +
8618 +typedef enum {
8619 + PCI_MMEDIA_VIDEO,
8620 + PCI_MMEDIA_AUDIO,
8621 + PCI_MMEDIA_PHONE,
8622 + PCI_MEDIA_OTHER = 0x80
8623 +} pci_mmedia_subclasses;
8624 +
8625 +typedef enum {
8626 + PCI_MEMORY_RAM,
8627 + PCI_MEMORY_FLASH,
8628 + PCI_MEMORY_OTHER = 0x80
8629 +} pci_memory_subclasses;
8630 +
8631 +typedef enum {
8632 + PCI_BRIDGE_HOST,
8633 + PCI_BRIDGE_ISA,
8634 + PCI_BRIDGE_EISA,
8635 + PCI_BRIDGE_MC,
8636 + PCI_BRIDGE_PCI,
8637 + PCI_BRIDGE_PCMCIA,
8638 + PCI_BRIDGE_NUBUS,
8639 + PCI_BRIDGE_CARDBUS,
8640 + PCI_BRIDGE_RACEWAY,
8641 + PCI_BRIDGE_OTHER = 0x80
8642 +} pci_bridge_subclasses;
8643 +
8644 +typedef enum {
8645 + PCI_COMM_UART,
8646 + PCI_COMM_PARALLEL,
8647 + PCI_COMM_MULTIUART,
8648 + PCI_COMM_MODEM,
8649 + PCI_COMM_OTHER = 0x80
8650 +} pci_comm_subclasses;
8651 +
8652 +typedef enum {
8653 + PCI_BASE_PIC,
8654 + PCI_BASE_DMA,
8655 + PCI_BASE_TIMER,
8656 + PCI_BASE_RTC,
8657 + PCI_BASE_PCI_HOTPLUG,
8658 + PCI_BASE_OTHER = 0x80
8659 +} pci_base_subclasses;
8660 +
8661 +typedef enum {
8662 + PCI_INPUT_KBD,
8663 + PCI_INPUT_PEN,
8664 + PCI_INPUT_MOUSE,
8665 + PCI_INPUT_SCANNER,
8666 + PCI_INPUT_GAMEPORT,
8667 + PCI_INPUT_OTHER = 0x80
8668 +} pci_input_subclasses;
8669 +
8670 +typedef enum {
8671 + PCI_DOCK_GENERIC,
8672 + PCI_DOCK_OTHER = 0x80
8673 +} pci_dock_subclasses;
8674 +
8675 +typedef enum {
8676 + PCI_CPU_386,
8677 + PCI_CPU_486,
8678 + PCI_CPU_PENTIUM,
8679 + PCI_CPU_ALPHA = 0x10,
8680 + PCI_CPU_POWERPC = 0x20,
8681 + PCI_CPU_MIPS = 0x30,
8682 + PCI_CPU_COPROC = 0x40,
8683 + PCI_CPU_OTHER = 0x80
8684 +} pci_cpu_subclasses;
8685 +
8686 +typedef enum {
8687 + PCI_SERIAL_IEEE1394,
8688 + PCI_SERIAL_ACCESS,
8689 + PCI_SERIAL_SSA,
8690 + PCI_SERIAL_USB,
8691 + PCI_SERIAL_FIBER,
8692 + PCI_SERIAL_SMBUS,
8693 + PCI_SERIAL_OTHER = 0x80
8694 +} pci_serial_subclasses;
8695 +
8696 +typedef enum {
8697 + PCI_INTELLIGENT_I2O,
8698 +} pci_intelligent_subclasses;
8699 +
8700 +typedef enum {
8701 + PCI_SATELLITE_TV,
8702 + PCI_SATELLITE_AUDIO,
8703 + PCI_SATELLITE_VOICE,
8704 + PCI_SATELLITE_DATA,
8705 + PCI_SATELLITE_OTHER = 0x80
8706 +} pci_satellite_subclasses;
8707 +
8708 +typedef enum {
8709 + PCI_CRYPT_NETWORK,
8710 + PCI_CRYPT_ENTERTAINMENT,
8711 + PCI_CRYPT_OTHER = 0x80
8712 +} pci_crypt_subclasses;
8713 +
8714 +typedef enum {
8715 + PCI_DSP_DPIO,
8716 + PCI_DSP_OTHER = 0x80
8717 +} pci_dsp_subclasses;
8718 +
8719 +/* Header types */
8720 +typedef enum {
8721 + PCI_HEADER_NORMAL,
8722 + PCI_HEADER_BRIDGE,
8723 + PCI_HEADER_CARDBUS
8724 +} pci_header_types;
8725 +
8726 +
8727 +/* Overlay for a PCI-to-PCI bridge */
8728 +
8729 +#define PPB_RSVDA_MAX 2
8730 +#define PPB_RSVDD_MAX 8
8731 +
8732 +typedef struct _ppb_config_regs {
8733 + unsigned short vendor;
8734 + unsigned short device;
8735 + unsigned short command;
8736 + unsigned short status;
8737 + unsigned char rev_id;
8738 + unsigned char prog_if;
8739 + unsigned char sub_class;
8740 + unsigned char base_class;
8741 + unsigned char cache_line_size;
8742 + unsigned char latency_timer;
8743 + unsigned char header_type;
8744 + unsigned char bist;
8745 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8746 + unsigned char prim_bus;
8747 + unsigned char sec_bus;
8748 + unsigned char sub_bus;
8749 + unsigned char sec_lat;
8750 + unsigned char io_base;
8751 + unsigned char io_lim;
8752 + unsigned short sec_status;
8753 + unsigned short mem_base;
8754 + unsigned short mem_lim;
8755 + unsigned short pf_mem_base;
8756 + unsigned short pf_mem_lim;
8757 + unsigned long pf_mem_base_hi;
8758 + unsigned long pf_mem_lim_hi;
8759 + unsigned short io_base_hi;
8760 + unsigned short io_lim_hi;
8761 + unsigned short subsys_vendor;
8762 + unsigned short subsys_id;
8763 + unsigned long rsvd_b;
8764 + unsigned char rsvd_c;
8765 + unsigned char int_pin;
8766 + unsigned short bridge_ctrl;
8767 + unsigned char chip_ctrl;
8768 + unsigned char diag_ctrl;
8769 + unsigned short arb_ctrl;
8770 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8771 + unsigned char dev_dep[192];
8772 +} ppb_config_regs;
8773 +
8774 +
8775 +/* PCI CAPABILITY DEFINES */
8776 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8777 +#define PCI_CAP_MSICAP_ID 0x05
8778 +
8779 +/* Data structure to define the Message Signalled Interrupt facility
8780 + * Valid for PCI and PCIE configurations */
8781 +typedef struct _pciconfig_cap_msi {
8782 + unsigned char capID;
8783 + unsigned char nextptr;
8784 + unsigned short msgctrl;
8785 + unsigned int msgaddr;
8786 +} pciconfig_cap_msi;
8787 +
8788 +/* Data structure to define the Power managment facility
8789 + * Valid for PCI and PCIE configurations */
8790 +typedef struct _pciconfig_cap_pwrmgmt {
8791 + unsigned char capID;
8792 + unsigned char nextptr;
8793 + unsigned short pme_cap;
8794 + unsigned short pme_sts_ctrl;
8795 + unsigned char pme_bridge_ext;
8796 + unsigned char data;
8797 +} pciconfig_cap_pwrmgmt;
8798 +
8799 +/* Everything below is BRCM HND proprietary */
8800 +
8801 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8802 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8803 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8804 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8805 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8806 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8807 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8808 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8809 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8810 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8811 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8812 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8813 +
8814 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8815 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8816 +
8817 +/* PCI_INT_STATUS */
8818 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8819 +
8820 +/* PCI_INT_MASK */
8821 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8822 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8823 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8824 +
8825 +/* PCI_SPROM_CONTROL */
8826 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8827 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8828 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8829 +
8830 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8831 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8832 +
8833 +/* PCI_CFG_CMD_STAT */
8834 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8835 +
8836 +#endif
8837 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8838 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8839 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-15 12:57:27.869191250 +0100
8840 @@ -0,0 +1,145 @@
8841 +/*******************************************************************************
8842 + * $Id$
8843 + * Copyright 2001-2003, Broadcom Corporation
8844 + * All Rights Reserved.
8845 + *
8846 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8847 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8848 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8849 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8850 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8851 + ******************************************************************************/
8852 +
8853 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8854 +#define _NET_ETHERNET_H_
8855 +
8856 +#ifndef _TYPEDEFS_H_
8857 +#include "typedefs.h"
8858 +#endif
8859 +
8860 +#if defined(__GNUC__)
8861 +#define PACKED __attribute__((packed))
8862 +#else
8863 +#define PACKED
8864 +#endif
8865 +
8866 +/*
8867 + * The number of bytes in an ethernet (MAC) address.
8868 + */
8869 +#define ETHER_ADDR_LEN 6
8870 +
8871 +/*
8872 + * The number of bytes in the type field.
8873 + */
8874 +#define ETHER_TYPE_LEN 2
8875 +
8876 +/*
8877 + * The number of bytes in the trailing CRC field.
8878 + */
8879 +#define ETHER_CRC_LEN 4
8880 +
8881 +/*
8882 + * The length of the combined header.
8883 + */
8884 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8885 +
8886 +/*
8887 + * The minimum packet length.
8888 + */
8889 +#define ETHER_MIN_LEN 64
8890 +
8891 +/*
8892 + * The minimum packet user data length.
8893 + */
8894 +#define ETHER_MIN_DATA 46
8895 +
8896 +/*
8897 + * The maximum packet length.
8898 + */
8899 +#define ETHER_MAX_LEN 1518
8900 +
8901 +/*
8902 + * The maximum packet user data length.
8903 + */
8904 +#define ETHER_MAX_DATA 1500
8905 +
8906 +/*
8907 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8908 + */
8909 +#define VLAN_TAG 0x8100
8910 +
8911 +/*
8912 + * Located after dest & src address in ether header.
8913 + */
8914 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8915 +
8916 +/*
8917 + * 4 bytes of vlan field info.
8918 + */
8919 +#define VLAN_FIELDS_SIZE 4
8920 +
8921 +/* location of pri bits in 16-bit vlan fields */
8922 +#define VLAN_PRI_SHIFT 13
8923 +
8924 +/* 3 bits of priority */
8925 +#define VLAN_PRI_MASK 7
8926 +
8927 +/* 802.1X ethertype */
8928 +#define ETHER_TYPE_802_1X 0x888e
8929 +
8930 +/*
8931 + * A macro to validate a length with
8932 + */
8933 +#define ETHER_IS_VALID_LEN(foo) \
8934 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8935 +
8936 +
8937 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8938 +/*
8939 + * Structure of a 10Mb/s Ethernet header.
8940 + */
8941 +struct ether_header {
8942 + uint8 ether_dhost[ETHER_ADDR_LEN];
8943 + uint8 ether_shost[ETHER_ADDR_LEN];
8944 + uint16 ether_type;
8945 +} PACKED ;
8946 +
8947 +/*
8948 + * Structure of a 48-bit Ethernet address.
8949 + */
8950 +struct ether_addr {
8951 + uint8 octet[ETHER_ADDR_LEN];
8952 +} PACKED ;
8953 +#endif
8954 +
8955 +/*
8956 + * Takes a pointer, returns true if a 48-bit multicast address
8957 + * (including broadcast, since it is all ones)
8958 + */
8959 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
8960 +
8961 +/*
8962 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
8963 + */
8964 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
8965 + ((uint8 *)(ea))[1] & \
8966 + ((uint8 *)(ea))[2] & \
8967 + ((uint8 *)(ea))[3] & \
8968 + ((uint8 *)(ea))[4] & \
8969 + ((uint8 *)(ea))[5]) == 0xff)
8970 +
8971 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
8972 +
8973 +/*
8974 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
8975 + */
8976 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
8977 + ((uint8 *)(ea))[1] | \
8978 + ((uint8 *)(ea))[2] | \
8979 + ((uint8 *)(ea))[3] | \
8980 + ((uint8 *)(ea))[4] | \
8981 + ((uint8 *)(ea))[5]) == 0)
8982 +
8983 +#undef PACKED
8984 +
8985 +#endif /* _NET_ETHERNET_H_ */
8986 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
8987 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
8988 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2005-12-15 12:57:27.869191250 +0100
8989 @@ -0,0 +1,103 @@
8990 +#ifndef _S5_H_
8991 +#define _S5_H_
8992 +/*
8993 + * Copyright 2003, Broadcom Corporation
8994 + * All Rights Reserved.
8995 + *
8996 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
8997 + * and MIPS3301 (R4K) System Address Space
8998 + *
8999 + * This program is free software; you can redistribute it and/or
9000 + * modify it under the terms of the GNU General Public License as
9001 + * published by the Free Software Foundation, located in the file
9002 + * LICENSE.
9003 + *
9004 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9005 + *
9006 + */
9007 +
9008 +/* BCM5365 Address map */
9009 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9010 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9011 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9012 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9013 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9014 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9015 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9016 +
9017 +/* BCM5365 Core register space */
9018 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9019 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9020 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9021 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9022 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9023 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9024 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9025 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9026 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9027 +
9028 +/* COM Ports 1/2 */
9029 +#define BCM5365_UART (BCM5365_REG_UARTS)
9030 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9031 +
9032 +/* Registers common to MIPS33 Core used in 5365 */
9033 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9034 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9035 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9036 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9037 +
9038 +/* Internal Core Sonics Backplane Devices */
9039 +#define INTERNAL_UART_COM1 BCM5365_UART
9040 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9041 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9042 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9043 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9044 +#define SB_REG_USB BCM5365_REG_USB
9045 +#define SB_REG_PCI BCM5365_REG_PCI
9046 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9047 +#define SB_REG_MEMC BCM5365_REG_MEMC
9048 +#define SB_REG_MEMC_OFF 0x6000
9049 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9050 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9051 +
9052 +/*
9053 + * XXX
9054 + * 5365-specific backplane interrupt flag numbers. This should be done
9055 + * dynamically instead.
9056 + */
9057 +#define SBFLAG_PCI 0
9058 +#define SBFLAG_ENET0 1
9059 +#define SBFLAG_ILINE20 2
9060 +#define SBFLAG_CODEC 3
9061 +#define SBFLAG_USB 4
9062 +#define SBFLAG_EXTIF 5
9063 +#define SBFLAG_ENET1 6
9064 +
9065 +/* BCM95365 Local Bus devices */
9066 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9067 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9068 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9069 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9070 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9071 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9072 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9073 +
9074 +/* Write to DLR2416 VFD Display character RAM */
9075 +#define LED_REG(x) \
9076 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9077 +
9078 +#ifdef CONFIG_VSIM
9079 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9080 + } while (0)
9081 +#else
9082 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9083 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9084 + *((int *)0xa0002ff8) = (trval); } while (0)
9085 +#endif
9086 +
9087 +/* BCM9536R Local Bus devices */
9088 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9089 +
9090 +
9091 +
9092 +#endif /*!_S5_H_ */
9093 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9094 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9095 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-12-15 15:35:20.458560250 +0100
9096 @@ -0,0 +1,440 @@
9097 +/*
9098 + * SiliconBackplane Chipcommon core hardware definitions.
9099 + *
9100 + * The chipcommon core provides chip identification, SB control,
9101 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9102 + * gpio interface, extbus, and support for serial and parallel flashes.
9103 + *
9104 + * $Id$
9105 + * Copyright 2005, Broadcom Corporation
9106 + * All Rights Reserved.
9107 + *
9108 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9109 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9110 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9111 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9112 + *
9113 + */
9114 +
9115 +#ifndef _SBCHIPC_H
9116 +#define _SBCHIPC_H
9117 +
9118 +
9119 +#ifndef _LANGUAGE_ASSEMBLY
9120 +
9121 +/* cpp contortions to concatenate w/arg prescan */
9122 +#ifndef PAD
9123 +#define _PADLINE(line) pad ## line
9124 +#define _XSTR(line) _PADLINE(line)
9125 +#define PAD _XSTR(__LINE__)
9126 +#endif /* PAD */
9127 +
9128 +typedef volatile struct {
9129 + uint32 chipid; /* 0x0 */
9130 + uint32 capabilities;
9131 + uint32 corecontrol; /* corerev >= 1 */
9132 + uint32 bist;
9133 +
9134 + /* OTP */
9135 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9136 + uint32 otpcontrol;
9137 + uint32 otpprog;
9138 + uint32 PAD;
9139 +
9140 + /* Interrupt control */
9141 + uint32 intstatus; /* 0x20 */
9142 + uint32 intmask;
9143 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9144 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9145 +
9146 + /* Jtag Master */
9147 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9148 + uint32 jtagir;
9149 + uint32 jtagdr;
9150 + uint32 jtagctrl;
9151 +
9152 + /* serial flash interface registers */
9153 + uint32 flashcontrol; /* 0x40 */
9154 + uint32 flashaddress;
9155 + uint32 flashdata;
9156 + uint32 PAD[1];
9157 +
9158 + /* Silicon backplane configuration broadcast control */
9159 + uint32 broadcastaddress; /* 0x50 */
9160 + uint32 broadcastdata;
9161 + uint32 PAD[2];
9162 +
9163 + /* gpio - cleared only by power-on-reset */
9164 + uint32 gpioin; /* 0x60 */
9165 + uint32 gpioout;
9166 + uint32 gpioouten;
9167 + uint32 gpiocontrol;
9168 + uint32 gpiointpolarity;
9169 + uint32 gpiointmask;
9170 + uint32 PAD[2];
9171 +
9172 + /* Watchdog timer */
9173 + uint32 watchdog; /* 0x80 */
9174 + uint32 PAD[1];
9175 +
9176 + /*GPIO based LED powersave registers corerev >= 16*/
9177 + uint32 gpiotimerval; /*0x88 */
9178 + uint32 gpiotimeroutmask;
9179 +
9180 + /* clock control */
9181 + uint32 clockcontrol_n; /* 0x90 */
9182 + uint32 clockcontrol_sb; /* aka m0 */
9183 + uint32 clockcontrol_pci; /* aka m1 */
9184 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9185 + uint32 clockcontrol_mips; /* aka m3 */
9186 + uint32 clkdiv; /* corerev >= 3 */
9187 + uint32 PAD[2];
9188 +
9189 + /* pll delay registers (corerev >= 4) */
9190 + uint32 pll_on_delay; /* 0xb0 */
9191 + uint32 fref_sel_delay;
9192 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9193 + uint32 PAD[1];
9194 +
9195 + /* Instaclock registers (corerev >= 10) */
9196 + uint32 system_clk_ctl; /* 0xc0 */
9197 + uint32 clkstatestretch;
9198 + uint32 PAD[14];
9199 +
9200 + /* ExtBus control registers (corerev >= 3) */
9201 + uint32 pcmcia_config; /* 0x100 */
9202 + uint32 pcmcia_memwait;
9203 + uint32 pcmcia_attrwait;
9204 + uint32 pcmcia_iowait;
9205 + uint32 ide_config;
9206 + uint32 ide_memwait;
9207 + uint32 ide_attrwait;
9208 + uint32 ide_iowait;
9209 + uint32 prog_config;
9210 + uint32 prog_waitcount;
9211 + uint32 flash_config;
9212 + uint32 flash_waitcount;
9213 + uint32 PAD[116];
9214 +
9215 + /* uarts */
9216 + uint8 uart0data; /* 0x300 */
9217 + uint8 uart0imr;
9218 + uint8 uart0fcr;
9219 + uint8 uart0lcr;
9220 + uint8 uart0mcr;
9221 + uint8 uart0lsr;
9222 + uint8 uart0msr;
9223 + uint8 uart0scratch;
9224 + uint8 PAD[248]; /* corerev >= 1 */
9225 +
9226 + uint8 uart1data; /* 0x400 */
9227 + uint8 uart1imr;
9228 + uint8 uart1fcr;
9229 + uint8 uart1lcr;
9230 + uint8 uart1mcr;
9231 + uint8 uart1lsr;
9232 + uint8 uart1msr;
9233 + uint8 uart1scratch;
9234 +} chipcregs_t;
9235 +
9236 +#endif /* _LANGUAGE_ASSEMBLY */
9237 +
9238 +#define CC_CHIPID 0
9239 +#define CC_CAPABILITIES 4
9240 +#define CC_JTAGCMD 0x30
9241 +#define CC_JTAGIR 0x34
9242 +#define CC_JTAGDR 0x38
9243 +#define CC_JTAGCTRL 0x3c
9244 +#define CC_WATCHDOG 0x80
9245 +#define CC_CLKC_N 0x90
9246 +#define CC_CLKC_M0 0x94
9247 +#define CC_CLKC_M1 0x98
9248 +#define CC_CLKC_M2 0x9c
9249 +#define CC_CLKC_M3 0xa0
9250 +#define CC_CLKDIV 0xa4
9251 +#define CC_SYS_CLK_CTL 0xc0
9252 +#define CC_OTP 0x800
9253 +
9254 +/* chipid */
9255 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9256 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9257 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9258 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9259 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9260 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9261 +#define CID_CC_SHIFT 24
9262 +
9263 +/* capabilities */
9264 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9265 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9266 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9267 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9268 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9269 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9270 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9271 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9272 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9273 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9274 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9275 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9276 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9277 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9278 +
9279 +/* PLL type */
9280 +#define PLL_NONE 0x00000000
9281 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9282 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9283 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9284 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9285 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9286 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9287 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9288 +
9289 +/* corecontrol */
9290 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9291 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9292 +
9293 +/* Fields in the otpstatus register */
9294 +#define OTPS_PROGFAIL 0x80000000
9295 +#define OTPS_PROTECT 0x00000007
9296 +#define OTPS_HW_PROTECT 0x00000001
9297 +#define OTPS_SW_PROTECT 0x00000002
9298 +#define OTPS_CID_PROTECT 0x00000004
9299 +
9300 +/* Fields in the otpcontrol register */
9301 +#define OTPC_RECWAIT 0xff000000
9302 +#define OTPC_PROGWAIT 0x00ffff00
9303 +#define OTPC_PRW_SHIFT 8
9304 +#define OTPC_MAXFAIL 0x00000038
9305 +#define OTPC_VSEL 0x00000006
9306 +#define OTPC_SELVL 0x00000001
9307 +
9308 +/* Fields in otpprog */
9309 +#define OTPP_COL_MASK 0x000000ff
9310 +#define OTPP_ROW_MASK 0x0000ff00
9311 +#define OTPP_ROW_SHIFT 8
9312 +#define OTPP_READERR 0x10000000
9313 +#define OTPP_VALUE 0x20000000
9314 +#define OTPP_VALUE_SHIFT 29
9315 +#define OTPP_READ 0x40000000
9316 +#define OTPP_START 0x80000000
9317 +#define OTPP_BUSY 0x80000000
9318 +
9319 +/* jtagcmd */
9320 +#define JCMD_START 0x80000000
9321 +#define JCMD_BUSY 0x80000000
9322 +#define JCMD_PAUSE 0x40000000
9323 +#define JCMD0_ACC_MASK 0x0000f000
9324 +#define JCMD0_ACC_IRDR 0x00000000
9325 +#define JCMD0_ACC_DR 0x00001000
9326 +#define JCMD0_ACC_IR 0x00002000
9327 +#define JCMD0_ACC_RESET 0x00003000
9328 +#define JCMD0_ACC_IRPDR 0x00004000
9329 +#define JCMD0_ACC_PDR 0x00005000
9330 +#define JCMD0_IRW_MASK 0x00000f00
9331 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9332 +#define JCMD_ACC_IRDR 0x00000000
9333 +#define JCMD_ACC_DR 0x00010000
9334 +#define JCMD_ACC_IR 0x00020000
9335 +#define JCMD_ACC_RESET 0x00030000
9336 +#define JCMD_ACC_IRPDR 0x00040000
9337 +#define JCMD_ACC_PDR 0x00050000
9338 +#define JCMD_IRW_MASK 0x00001f00
9339 +#define JCMD_IRW_SHIFT 8
9340 +#define JCMD_DRW_MASK 0x0000003f
9341 +
9342 +/* jtagctrl */
9343 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9344 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9345 +#define JCTRL_EN 1 /* Enable Jtag master */
9346 +
9347 +/* Fields in clkdiv */
9348 +#define CLKD_SFLASH 0x0f000000
9349 +#define CLKD_SFLASH_SHIFT 24
9350 +#define CLKD_OTP 0x000f0000
9351 +#define CLKD_OTP_SHIFT 16
9352 +#define CLKD_JTAG 0x00000f00
9353 +#define CLKD_JTAG_SHIFT 8
9354 +#define CLKD_UART 0x000000ff
9355 +
9356 +/* intstatus/intmask */
9357 +#define CI_GPIO 0x00000001 /* gpio intr */
9358 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9359 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9360 +
9361 +/* slow_clk_ctl */
9362 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9363 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9364 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9365 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9366 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9367 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9368 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9369 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9370 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9371 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9372 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9373 +#define SCC_CD_SHIFT 16
9374 +
9375 +/* system_clk_ctl */
9376 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9377 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9378 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9379 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9380 +#define SYCC_HR 0x00000010 /* Force HT */
9381 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9382 +#define SYCC_CD_SHIFT 16
9383 +
9384 +/* gpiotimerval*/
9385 +#define GPIO_ONTIME_SHIFT 16
9386 +
9387 +/* clockcontrol_n */
9388 +#define CN_N1_MASK 0x3f /* n1 control */
9389 +#define CN_N2_MASK 0x3f00 /* n2 control */
9390 +#define CN_N2_SHIFT 8
9391 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9392 +#define CN_PLLC_SHIFT 16
9393 +
9394 +/* clockcontrol_sb/pci/uart */
9395 +#define CC_M1_MASK 0x3f /* m1 control */
9396 +#define CC_M2_MASK 0x3f00 /* m2 control */
9397 +#define CC_M2_SHIFT 8
9398 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9399 +#define CC_M3_SHIFT 16
9400 +#define CC_MC_MASK 0x1f000000 /* mux control */
9401 +#define CC_MC_SHIFT 24
9402 +
9403 +/* N3M Clock control magic field values */
9404 +#define CC_F6_2 0x02 /* A factor of 2 in */
9405 +#define CC_F6_3 0x03 /* 6-bit fields like */
9406 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9407 +#define CC_F6_5 0x09
9408 +#define CC_F6_6 0x11
9409 +#define CC_F6_7 0x21
9410 +
9411 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9412 +
9413 +#define CC_MC_BYPASS 0x08
9414 +#define CC_MC_M1 0x04
9415 +#define CC_MC_M1M2 0x02
9416 +#define CC_MC_M1M2M3 0x01
9417 +#define CC_MC_M1M3 0x11
9418 +
9419 +/* Type 2 Clock control magic field values */
9420 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9421 +#define CC_T2M2_BIAS 3 /* m2 bias */
9422 +
9423 +#define CC_T2MC_M1BYP 1
9424 +#define CC_T2MC_M2BYP 2
9425 +#define CC_T2MC_M3BYP 4
9426 +
9427 +/* Type 6 Clock control magic field values */
9428 +#define CC_T6_MMASK 1 /* bits of interest in m */
9429 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9430 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9431 +#define SB2MIPS_T6(sb) (2 * (sb))
9432 +
9433 +/* Common clock base */
9434 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9435 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9436 +
9437 +/* Clock control values for 200Mhz in 5350 */
9438 +#define CLKC_5350_N 0x0311
9439 +#define CLKC_5350_M 0x04020009
9440 +
9441 +/* Flash types in the chipcommon capabilities register */
9442 +#define FLASH_NONE 0x000 /* No flash */
9443 +#define SFLASH_ST 0x100 /* ST serial flash */
9444 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9445 +#define PFLASH 0x700 /* Parallel flash */
9446 +
9447 +/* Bits in the config registers */
9448 +#define CC_CFG_EN 0x0001 /* Enable */
9449 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9450 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9451 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9452 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9453 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9454 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9455 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9456 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9457 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9458 +
9459 +/* Start/busy bit in flashcontrol */
9460 +#define SFLASH_START 0x80000000
9461 +#define SFLASH_BUSY SFLASH_START
9462 +
9463 +/* flashcontrol opcodes for ST flashes */
9464 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9465 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9466 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9467 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9468 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9469 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9470 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9471 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9472 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9473 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9474 +
9475 +/* Status register bits for ST flashes */
9476 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9477 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9478 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9479 +#define SFLASH_ST_BP_SHIFT 2
9480 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9481 +
9482 +/* flashcontrol opcodes for Atmel flashes */
9483 +#define SFLASH_AT_READ 0x07e8
9484 +#define SFLASH_AT_PAGE_READ 0x07d2
9485 +#define SFLASH_AT_BUF1_READ
9486 +#define SFLASH_AT_BUF2_READ
9487 +#define SFLASH_AT_STATUS 0x01d7
9488 +#define SFLASH_AT_BUF1_WRITE 0x0384
9489 +#define SFLASH_AT_BUF2_WRITE 0x0387
9490 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9491 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9492 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9493 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9494 +#define SFLASH_AT_PAGE_ERASE 0x0281
9495 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9496 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9497 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9498 +#define SFLASH_AT_BUF1_LOAD 0x0253
9499 +#define SFLASH_AT_BUF2_LOAD 0x0255
9500 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9501 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9502 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9503 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9504 +
9505 +/* Status register bits for Atmel flashes */
9506 +#define SFLASH_AT_READY 0x80
9507 +#define SFLASH_AT_MISMATCH 0x40
9508 +#define SFLASH_AT_ID_MASK 0x38
9509 +#define SFLASH_AT_ID_SHIFT 3
9510 +
9511 +/* OTP regions */
9512 +#define OTP_HW_REGION OTPS_HW_PROTECT
9513 +#define OTP_SW_REGION OTPS_SW_PROTECT
9514 +#define OTP_CID_REGION OTPS_CID_PROTECT
9515 +
9516 +/* OTP regions (Byte offsets from otp size) */
9517 +#define OTP_SWLIM_OFF (-8)
9518 +#define OTP_CIDBASE_OFF 0
9519 +#define OTP_CIDLIM_OFF 8
9520 +
9521 +/* Predefined OTP words (Word offset from otp size) */
9522 +#define OTP_BOUNDARY_OFF (-4)
9523 +#define OTP_HWSIGN_OFF (-3)
9524 +#define OTP_SWSIGN_OFF (-2)
9525 +#define OTP_CIDSIGN_OFF (-1)
9526 +
9527 +#define OTP_CID_OFF 0
9528 +#define OTP_PKG_OFF 1
9529 +#define OTP_FID_OFF 2
9530 +#define OTP_RSV_OFF 3
9531 +#define OTP_LIM_OFF 4
9532 +
9533 +#define OTP_SIGNATURE 0x578a
9534 +#define OTP_MAGIC 0x4e56
9535 +
9536 +#endif /* _SBCHIPC_H */
9537 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9538 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9539 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-12-15 15:35:24.538815250 +0100
9540 @@ -0,0 +1,342 @@
9541 +/*
9542 + * Broadcom SiliconBackplane hardware register definitions.
9543 + *
9544 + * Copyright 2005, Broadcom Corporation
9545 + * All Rights Reserved.
9546 + *
9547 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9548 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9549 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9550 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9551 + * $Id$
9552 + */
9553 +
9554 +#ifndef _SBCONFIG_H
9555 +#define _SBCONFIG_H
9556 +
9557 +/* cpp contortions to concatenate w/arg prescan */
9558 +#ifndef PAD
9559 +#define _PADLINE(line) pad ## line
9560 +#define _XSTR(line) _PADLINE(line)
9561 +#define PAD _XSTR(__LINE__)
9562 +#endif
9563 +
9564 +/*
9565 + * SiliconBackplane Address Map.
9566 + * All regions may not exist on all chips.
9567 + */
9568 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9569 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9570 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9571 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9572 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9573 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9574 +
9575 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9576 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9577 +
9578 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9579 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9580 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9581 +
9582 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9583 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9584 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9585 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9586 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9587 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9588 +
9589 +
9590 +/* enumeration space related defs */
9591 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9592 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9593 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9594 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9595 +
9596 +/* mips address */
9597 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9598 +
9599 +/*
9600 + * Sonics Configuration Space Registers.
9601 + */
9602 +#define SBIPSFLAG 0x08
9603 +#define SBTPSFLAG 0x18
9604 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9605 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9606 +#define SBADMATCH3 0x60
9607 +#define SBADMATCH2 0x68
9608 +#define SBADMATCH1 0x70
9609 +#define SBIMSTATE 0x90
9610 +#define SBINTVEC 0x94
9611 +#define SBTMSTATELOW 0x98
9612 +#define SBTMSTATEHIGH 0x9c
9613 +#define SBBWA0 0xa0
9614 +#define SBIMCONFIGLOW 0xa8
9615 +#define SBIMCONFIGHIGH 0xac
9616 +#define SBADMATCH0 0xb0
9617 +#define SBTMCONFIGLOW 0xb8
9618 +#define SBTMCONFIGHIGH 0xbc
9619 +#define SBBCONFIG 0xc0
9620 +#define SBBSTATE 0xc8
9621 +#define SBACTCNFG 0xd8
9622 +#define SBFLAGST 0xe8
9623 +#define SBIDLOW 0xf8
9624 +#define SBIDHIGH 0xfc
9625 +
9626 +#ifndef _LANGUAGE_ASSEMBLY
9627 +
9628 +typedef volatile struct _sbconfig {
9629 + uint32 PAD[2];
9630 + uint32 sbipsflag; /* initiator port ocp slave flag */
9631 + uint32 PAD[3];
9632 + uint32 sbtpsflag; /* target port ocp slave flag */
9633 + uint32 PAD[11];
9634 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9635 + uint32 PAD;
9636 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9637 + uint32 PAD[3];
9638 + uint32 sbadmatch3; /* address match3 */
9639 + uint32 PAD;
9640 + uint32 sbadmatch2; /* address match2 */
9641 + uint32 PAD;
9642 + uint32 sbadmatch1; /* address match1 */
9643 + uint32 PAD[7];
9644 + uint32 sbimstate; /* initiator agent state */
9645 + uint32 sbintvec; /* interrupt mask */
9646 + uint32 sbtmstatelow; /* target state */
9647 + uint32 sbtmstatehigh; /* target state */
9648 + uint32 sbbwa0; /* bandwidth allocation table0 */
9649 + uint32 PAD;
9650 + uint32 sbimconfiglow; /* initiator configuration */
9651 + uint32 sbimconfighigh; /* initiator configuration */
9652 + uint32 sbadmatch0; /* address match0 */
9653 + uint32 PAD;
9654 + uint32 sbtmconfiglow; /* target configuration */
9655 + uint32 sbtmconfighigh; /* target configuration */
9656 + uint32 sbbconfig; /* broadcast configuration */
9657 + uint32 PAD;
9658 + uint32 sbbstate; /* broadcast state */
9659 + uint32 PAD[3];
9660 + uint32 sbactcnfg; /* activate configuration */
9661 + uint32 PAD[3];
9662 + uint32 sbflagst; /* current sbflags */
9663 + uint32 PAD[3];
9664 + uint32 sbidlow; /* identification */
9665 + uint32 sbidhigh; /* identification */
9666 +} sbconfig_t;
9667 +
9668 +#endif /* _LANGUAGE_ASSEMBLY */
9669 +
9670 +/* sbipsflag */
9671 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9672 +#define SBIPS_INT1_SHIFT 0
9673 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9674 +#define SBIPS_INT2_SHIFT 8
9675 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9676 +#define SBIPS_INT3_SHIFT 16
9677 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9678 +#define SBIPS_INT4_SHIFT 24
9679 +
9680 +/* sbtpsflag */
9681 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9682 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9683 +
9684 +/* sbtmerrlog */
9685 +#define SBTMEL_CM 0x00000007 /* command */
9686 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9687 +#define SBTMEL_EC 0x0f000000 /* error code */
9688 +#define SBTMEL_ME 0x80000000 /* multiple error */
9689 +
9690 +/* sbimstate */
9691 +#define SBIM_PC 0xf /* pipecount */
9692 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9693 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9694 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9695 +#define SBIM_AP_TK 0x20 /* use token only */
9696 +#define SBIM_AP_RSV 0x30 /* reserved */
9697 +#define SBIM_IBE 0x20000 /* inbanderror */
9698 +#define SBIM_TO 0x40000 /* timeout */
9699 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9700 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9701 +
9702 +/* sbtmstatelow */
9703 +#define SBTML_RESET 0x1 /* reset */
9704 +#define SBTML_REJ_MASK 0x6 /* reject */
9705 +#define SBTML_REJ_SHIFT 1
9706 +#define SBTML_CLK 0x10000 /* clock enable */
9707 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9708 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9709 +#define SBTML_PE 0x40000000 /* pme enable */
9710 +#define SBTML_BE 0x80000000 /* bist enable */
9711 +
9712 +/* sbtmstatehigh */
9713 +#define SBTMH_SERR 0x1 /* serror */
9714 +#define SBTMH_INT 0x2 /* interrupt */
9715 +#define SBTMH_BUSY 0x4 /* busy */
9716 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9717 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9718 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9719 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9720 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9721 +#define SBTMH_BISTD 0x80000000 /* bist done */
9722 +
9723 +
9724 +/* sbbwa0 */
9725 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9726 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9727 +#define SBBWA_TAB1_SHIFT 16
9728 +
9729 +/* sbimconfiglow */
9730 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9731 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9732 +#define SBIMCL_RTO_SHIFT 4
9733 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9734 +#define SBIMCL_CID_SHIFT 16
9735 +
9736 +/* sbimconfighigh */
9737 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9738 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9739 +#define SBIMCH_TEM_SHIFT 4
9740 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9741 +#define SBIMCH_BEM_SHIFT 6
9742 +
9743 +/* sbadmatch0 */
9744 +#define SBAM_TYPE_MASK 0x3 /* address type */
9745 +#define SBAM_AD64 0x4 /* reserved */
9746 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9747 +#define SBAM_ADINT0_SHIFT 3
9748 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9749 +#define SBAM_ADINT1_SHIFT 3
9750 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9751 +#define SBAM_ADINT2_SHIFT 3
9752 +#define SBAM_ADEN 0x400 /* enable */
9753 +#define SBAM_ADNEG 0x800 /* negative decode */
9754 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9755 +#define SBAM_BASE0_SHIFT 8
9756 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9757 +#define SBAM_BASE1_SHIFT 12
9758 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9759 +#define SBAM_BASE2_SHIFT 16
9760 +
9761 +/* sbtmconfiglow */
9762 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9763 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9764 +#define SBTMCL_CO_SHIFT 11
9765 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9766 +#define SBTMCL_IF_SHIFT 18
9767 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9768 +#define SBTMCL_IM_SHIFT 24
9769 +
9770 +/* sbtmconfighigh */
9771 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9772 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9773 +#define SBTMCH_RM_SHIFT 2
9774 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9775 +#define SBTMCH_SM_SHIFT 4
9776 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9777 +#define SBTMCH_EM_SHIFT 8
9778 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9779 +#define SBTMCH_IM_SHIFT 10
9780 +
9781 +/* sbbconfig */
9782 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9783 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9784 +#define SBBC_MAX0_SHIFT 16
9785 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9786 +#define SBBC_MAX1_SHIFT 20
9787 +
9788 +/* sbbstate */
9789 +#define SBBS_SRD 0x1 /* st reg disable */
9790 +#define SBBS_HRD 0x2 /* hold reg disable */
9791 +
9792 +/* sbidlow */
9793 +#define SBIDL_CS_MASK 0x3 /* config space */
9794 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9795 +#define SBIDL_AR_SHIFT 3
9796 +#define SBIDL_SYNCH 0x40 /* sync */
9797 +#define SBIDL_INIT 0x80 /* initiator */
9798 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9799 +#define SBIDL_MINLAT_SHIFT 8
9800 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9801 +#define SBIDL_MAXLAT_SHIFT 12
9802 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9803 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9804 +#define SBIDL_CW_SHIFT 18
9805 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9806 +#define SBIDL_TP_SHIFT 20
9807 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9808 +#define SBIDL_IP_SHIFT 24
9809 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9810 +#define SBIDL_RV_SHIFT 28
9811 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9812 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9813 +
9814 +/* sbidhigh */
9815 +#define SBIDH_RC_MASK 0x000f /* revision code */
9816 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9817 +#define SBIDH_RCE_SHIFT 8
9818 +#define SBCOREREV(sbidh) \
9819 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9820 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9821 +#define SBIDH_CC_SHIFT 4
9822 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9823 +#define SBIDH_VC_SHIFT 16
9824 +
9825 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9826 +
9827 +/* vendor codes */
9828 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9829 +
9830 +/* core codes */
9831 +#define SB_CC 0x800 /* chipcommon core */
9832 +#define SB_ILINE20 0x801 /* iline20 core */
9833 +#define SB_SDRAM 0x803 /* sdram core */
9834 +#define SB_PCI 0x804 /* pci core */
9835 +#define SB_MIPS 0x805 /* mips core */
9836 +#define SB_ENET 0x806 /* enet mac core */
9837 +#define SB_CODEC 0x807 /* v90 codec core */
9838 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9839 +#define SB_ADSL 0x809 /* ADSL core */
9840 +#define SB_ILINE100 0x80a /* iline100 core */
9841 +#define SB_IPSEC 0x80b /* ipsec core */
9842 +#define SB_PCMCIA 0x80d /* pcmcia core */
9843 +#define SB_SOCRAM 0x80e /* internal memory core */
9844 +#define SB_MEMC 0x80f /* memc sdram core */
9845 +#define SB_EXTIF 0x811 /* external interface core */
9846 +#define SB_D11 0x812 /* 802.11 MAC core */
9847 +#define SB_MIPS33 0x816 /* mips3302 core */
9848 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9849 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9850 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9851 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9852 +#define SB_SDIOH 0x81b /* sdio host core */
9853 +#define SB_ROBO 0x81c /* roboswitch core */
9854 +#define SB_ATA100 0x81d /* parallel ATA core */
9855 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9856 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9857 +#define SB_PCIE 0x820 /* pci express core */
9858 +#define SB_SRAMC 0x822 /* SRAM controller core */
9859 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9860 +
9861 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9862 +
9863 +/* Not really related to Silicon Backplane, but a couple of software
9864 + * conventions for the use the flash space:
9865 + */
9866 +
9867 +/* Minumum amount of flash we support */
9868 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9869 +
9870 +/* A boot/binary may have an embedded block that describes its size */
9871 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9872 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9873 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9874 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9875 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9876 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9877 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9878 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9879 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9880 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9881 +
9882 +#endif /* _SBCONFIG_H */
9883 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9884 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9885 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-12-15 16:48:55.651993750 +0100
9886 @@ -0,0 +1,242 @@
9887 +/*
9888 + * Hardware-specific External Interface I/O core definitions
9889 + * for the BCM47xx family of SiliconBackplane-based chips.
9890 + *
9891 + * The External Interface core supports a total of three external chip selects
9892 + * supporting external interfaces. One of the external chip selects is
9893 + * used for Flash, one is used for PCMCIA, and the other may be
9894 + * programmed to support either a synchronous interface or an
9895 + * asynchronous interface. The asynchronous interface can be used to
9896 + * support external devices such as UARTs and the BCM2019 Bluetooth
9897 + * baseband processor.
9898 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9899 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9900 + *
9901 + * Copyright 2005, Broadcom Corporation
9902 + * All Rights Reserved.
9903 + *
9904 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9905 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9906 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9907 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9908 + * $Id$
9909 + */
9910 +
9911 +#ifndef _SBEXTIF_H
9912 +#define _SBEXTIF_H
9913 +
9914 +/* external interface address space */
9915 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9916 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9917 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9918 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9919 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9920 +
9921 +/* cpp contortions to concatenate w/arg prescan */
9922 +#ifndef PAD
9923 +#define _PADLINE(line) pad ## line
9924 +#define _XSTR(line) _PADLINE(line)
9925 +#define PAD _XSTR(__LINE__)
9926 +#endif /* PAD */
9927 +
9928 +/*
9929 + * The multiple instances of output and output enable registers
9930 + * are present to allow driver software for multiple cores to control
9931 + * gpio outputs without needing to share a single register pair.
9932 + */
9933 +struct gpiouser {
9934 + uint32 out;
9935 + uint32 outen;
9936 +};
9937 +#define NGPIOUSER 5
9938 +
9939 +typedef volatile struct {
9940 + uint32 corecontrol;
9941 + uint32 extstatus;
9942 + uint32 PAD[2];
9943 +
9944 + /* pcmcia control registers */
9945 + uint32 pcmcia_config;
9946 + uint32 pcmcia_memwait;
9947 + uint32 pcmcia_attrwait;
9948 + uint32 pcmcia_iowait;
9949 +
9950 + /* programmable interface control registers */
9951 + uint32 prog_config;
9952 + uint32 prog_waitcount;
9953 +
9954 + /* flash control registers */
9955 + uint32 flash_config;
9956 + uint32 flash_waitcount;
9957 + uint32 PAD[4];
9958 +
9959 + uint32 watchdog;
9960 +
9961 + /* clock control */
9962 + uint32 clockcontrol_n;
9963 + uint32 clockcontrol_sb;
9964 + uint32 clockcontrol_pci;
9965 + uint32 clockcontrol_mii;
9966 + uint32 PAD[3];
9967 +
9968 + /* gpio */
9969 + uint32 gpioin;
9970 + struct gpiouser gpio[NGPIOUSER];
9971 + uint32 PAD;
9972 + uint32 ejtagouten;
9973 + uint32 gpiointpolarity;
9974 + uint32 gpiointmask;
9975 + uint32 PAD[153];
9976 +
9977 + uint8 uartdata;
9978 + uint8 PAD[3];
9979 + uint8 uartimer;
9980 + uint8 PAD[3];
9981 + uint8 uartfcr;
9982 + uint8 PAD[3];
9983 + uint8 uartlcr;
9984 + uint8 PAD[3];
9985 + uint8 uartmcr;
9986 + uint8 PAD[3];
9987 + uint8 uartlsr;
9988 + uint8 PAD[3];
9989 + uint8 uartmsr;
9990 + uint8 PAD[3];
9991 + uint8 uartscratch;
9992 + uint8 PAD[3];
9993 +} extifregs_t;
9994 +
9995 +/* corecontrol */
9996 +#define CC_UE (1 << 0) /* uart enable */
9997 +
9998 +/* extstatus */
9999 +#define ES_EM (1 << 0) /* endian mode (ro) */
10000 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10001 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10002 +
10003 +/* gpio bit mask */
10004 +#define GPIO_BIT0 (1 << 0)
10005 +#define GPIO_BIT1 (1 << 1)
10006 +#define GPIO_BIT2 (1 << 2)
10007 +#define GPIO_BIT3 (1 << 3)
10008 +#define GPIO_BIT4 (1 << 4)
10009 +#define GPIO_BIT5 (1 << 5)
10010 +#define GPIO_BIT6 (1 << 6)
10011 +#define GPIO_BIT7 (1 << 7)
10012 +
10013 +
10014 +/* pcmcia/prog/flash_config */
10015 +#define CF_EN (1 << 0) /* enable */
10016 +#define CF_EM_MASK 0xe /* mode */
10017 +#define CF_EM_SHIFT 1
10018 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10019 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10020 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10021 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10022 +#define CF_BS (1 << 5) /* byteswap */
10023 +#define CF_CD_MASK 0xc0 /* clock divider */
10024 +#define CF_CD_SHIFT 6
10025 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10026 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10027 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10028 +#define CF_CE (1 << 8) /* clock enable */
10029 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10030 +
10031 +/* pcmcia_memwait */
10032 +#define PM_W0_MASK 0x3f /* waitcount0 */
10033 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10034 +#define PM_W1_SHIFT 8
10035 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10036 +#define PM_W2_SHIFT 16
10037 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10038 +#define PM_W3_SHIFT 24
10039 +
10040 +/* pcmcia_attrwait */
10041 +#define PA_W0_MASK 0x3f /* waitcount0 */
10042 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10043 +#define PA_W1_SHIFT 8
10044 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10045 +#define PA_W2_SHIFT 16
10046 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10047 +#define PA_W3_SHIFT 24
10048 +
10049 +/* pcmcia_iowait */
10050 +#define PI_W0_MASK 0x3f /* waitcount0 */
10051 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10052 +#define PI_W1_SHIFT 8
10053 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10054 +#define PI_W2_SHIFT 16
10055 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10056 +#define PI_W3_SHIFT 24
10057 +
10058 +/* prog_waitcount */
10059 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10060 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10061 +#define PW_W1_SHIFT 8
10062 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10063 +#define PW_W2_SHIFT 16
10064 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10065 +#define PW_W3_SHIFT 24
10066 +
10067 +#define PW_W0 0x0000000c
10068 +#define PW_W1 0x00000a00
10069 +#define PW_W2 0x00020000
10070 +#define PW_W3 0x01000000
10071 +
10072 +/* flash_waitcount */
10073 +#define FW_W0_MASK 0x1f /* waitcount0 */
10074 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10075 +#define FW_W1_SHIFT 8
10076 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10077 +#define FW_W2_SHIFT 16
10078 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10079 +#define FW_W3_SHIFT 24
10080 +
10081 +/* watchdog */
10082 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10083 +
10084 +/* clockcontrol_n */
10085 +#define CN_N1_MASK 0x3f /* n1 control */
10086 +#define CN_N2_MASK 0x3f00 /* n2 control */
10087 +#define CN_N2_SHIFT 8
10088 +
10089 +/* clockcontrol_sb/pci/mii */
10090 +#define CC_M1_MASK 0x3f /* m1 control */
10091 +#define CC_M2_MASK 0x3f00 /* m2 control */
10092 +#define CC_M2_SHIFT 8
10093 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10094 +#define CC_M3_SHIFT 16
10095 +#define CC_MC_MASK 0x1f000000 /* mux control */
10096 +#define CC_MC_SHIFT 24
10097 +
10098 +/* Clock control default values */
10099 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10100 +#define CC_DEF_100 0x04020011
10101 +#define CC_DEF_33 0x11030011
10102 +#define CC_DEF_25 0x11050011
10103 +
10104 +/* Clock control values for 125Mhz */
10105 +#define CC_125_N 0x0802
10106 +#define CC_125_M 0x04020009
10107 +#define CC_125_M25 0x11090009
10108 +#define CC_125_M33 0x11090005
10109 +
10110 +/* Clock control magic field values */
10111 +#define CC_F6_2 0x02 /* A factor of 2 in */
10112 +#define CC_F6_3 0x03 /* 6-bit fields like */
10113 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10114 +#define CC_F6_5 0x09
10115 +#define CC_F6_6 0x11
10116 +#define CC_F6_7 0x21
10117 +
10118 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10119 +
10120 +#define CC_MC_BYPASS 0x08
10121 +#define CC_MC_M1 0x04
10122 +#define CC_MC_M1M2 0x02
10123 +#define CC_MC_M1M2M3 0x01
10124 +#define CC_MC_M1M3 0x11
10125 +
10126 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10127 +
10128 +#endif /* _SBEXTIF_H */
10129 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10130 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10131 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-12-15 15:35:31.567254500 +0100
10132 @@ -0,0 +1,148 @@
10133 +/*
10134 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10135 + *
10136 + * Copyright 2005, Broadcom Corporation
10137 + * All Rights Reserved.
10138 + *
10139 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10140 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10141 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10142 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10143 + *
10144 + * $Id$
10145 + */
10146 +
10147 +#ifndef _SBMEMC_H
10148 +#define _SBMEMC_H
10149 +
10150 +#ifdef _LANGUAGE_ASSEMBLY
10151 +
10152 +#define MEMC_CONTROL 0x00
10153 +#define MEMC_CONFIG 0x04
10154 +#define MEMC_REFRESH 0x08
10155 +#define MEMC_BISTSTAT 0x0c
10156 +#define MEMC_MODEBUF 0x10
10157 +#define MEMC_BKCLS 0x14
10158 +#define MEMC_PRIORINV 0x18
10159 +#define MEMC_DRAMTIM 0x1c
10160 +#define MEMC_INTSTAT 0x20
10161 +#define MEMC_INTMASK 0x24
10162 +#define MEMC_INTINFO 0x28
10163 +#define MEMC_NCDLCTL 0x30
10164 +#define MEMC_RDNCDLCOR 0x34
10165 +#define MEMC_WRNCDLCOR 0x38
10166 +#define MEMC_MISCDLYCTL 0x3c
10167 +#define MEMC_DQSGATENCDL 0x40
10168 +#define MEMC_SPARE 0x44
10169 +#define MEMC_TPADDR 0x48
10170 +#define MEMC_TPDATA 0x4c
10171 +#define MEMC_BARRIER 0x50
10172 +#define MEMC_CORE 0x54
10173 +
10174 +
10175 +#else
10176 +
10177 +/* Sonics side: MEMC core registers */
10178 +typedef volatile struct sbmemcregs {
10179 + uint32 control;
10180 + uint32 config;
10181 + uint32 refresh;
10182 + uint32 biststat;
10183 + uint32 modebuf;
10184 + uint32 bkcls;
10185 + uint32 priorinv;
10186 + uint32 dramtim;
10187 + uint32 intstat;
10188 + uint32 intmask;
10189 + uint32 intinfo;
10190 + uint32 reserved1;
10191 + uint32 ncdlctl;
10192 + uint32 rdncdlcor;
10193 + uint32 wrncdlcor;
10194 + uint32 miscdlyctl;
10195 + uint32 dqsgatencdl;
10196 + uint32 spare;
10197 + uint32 tpaddr;
10198 + uint32 tpdata;
10199 + uint32 barrier;
10200 + uint32 core;
10201 +} sbmemcregs_t;
10202 +
10203 +#endif
10204 +
10205 +/* MEMC Core Init values (OCP ID 0x80f) */
10206 +
10207 +/* For sdr: */
10208 +#define MEMC_SD_CONFIG_INIT 0x00048000
10209 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10210 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10211 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10212 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10213 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10214 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10215 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10216 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10217 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10218 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10219 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10220 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10221 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10222 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10223 +
10224 +
10225 +/* This is for SDRM8X8X4 */
10226 +#define MEMC_SDR_INIT 0x0008
10227 +#define MEMC_SDR_MODE 0x32
10228 +#define MEMC_SDR_NCDL 0x00020032
10229 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10230 +
10231 +/* For ddr: */
10232 +#define MEMC_CONFIG_INIT 0x00048000
10233 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10234 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10235 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10236 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10237 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10238 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10239 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10240 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10241 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10242 +#define MEMC_NCDLCTL_INIT 0x00002001
10243 +#define MEMC_CONTROL_INIT0 0x00000002
10244 +#define MEMC_CONTROL_INIT1 0x00000008
10245 +#define MEMC_MODEBUF_INIT0 0x00004000
10246 +#define MEMC_CONTROL_INIT2 0x00000010
10247 +#define MEMC_MODEBUF_INIT1 0x00000100
10248 +#define MEMC_CONTROL_INIT3 0x00000010
10249 +#define MEMC_CONTROL_INIT4 0x00000008
10250 +#define MEMC_REFRESH_INIT 0x0000840f
10251 +#define MEMC_CONTROL_INIT5 0x00000004
10252 +#define MEMC_MODEBUF_INIT2 0x00000000
10253 +#define MEMC_CONTROL_INIT6 0x00000010
10254 +#define MEMC_CONTROL_INIT7 0x00000001
10255 +
10256 +
10257 +/* This is for DDRM16X16X2 */
10258 +#define MEMC_DDR_INIT 0x0009
10259 +#define MEMC_DDR_MODE 0x62
10260 +#define MEMC_DDR_NCDL 0x0005050a
10261 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10262 +
10263 +/* mask for sdr/ddr calibration registers */
10264 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10265 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10266 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10267 +
10268 +/* masks for miscdlyctl registers */
10269 +#define MEMC_MISC_SM_MASK 0x30000000
10270 +#define MEMC_MISC_SM_SHIFT 28
10271 +#define MEMC_MISC_SD_MASK 0x0f000000
10272 +#define MEMC_MISC_SD_SHIFT 24
10273 +
10274 +/* hw threshhold for calculating wr/rd for sdr memc */
10275 +#define MEMC_CD_THRESHOLD 128
10276 +
10277 +/* Low bit of init register says if memc is ddr or sdr */
10278 +#define MEMC_CONFIG_DDR 0x00000001
10279 +
10280 +#endif /* _SBMEMC_H */
10281 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10282 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10283 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-12-15 16:46:57.616617000 +0100
10284 @@ -0,0 +1,62 @@
10285 +/*
10286 + * Broadcom SiliconBackplane MIPS definitions
10287 + *
10288 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10289 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10290 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10291 + * interface. The core revision is stored in the SB ID register in SB
10292 + * configuration space.
10293 + *
10294 + * Copyright 2005, Broadcom Corporation
10295 + * All Rights Reserved.
10296 + *
10297 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10298 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10299 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10300 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10301 + *
10302 + * $Id$
10303 + */
10304 +
10305 +#ifndef _SBMIPS_H
10306 +#define _SBMIPS_H
10307 +
10308 +#include <mipsinc.h>
10309 +
10310 +#ifndef _LANGUAGE_ASSEMBLY
10311 +
10312 +/* cpp contortions to concatenate w/arg prescan */
10313 +#ifndef PAD
10314 +#define _PADLINE(line) pad ## line
10315 +#define _XSTR(line) _PADLINE(line)
10316 +#define PAD _XSTR(__LINE__)
10317 +#endif /* PAD */
10318 +
10319 +typedef volatile struct {
10320 + uint32 corecontrol;
10321 + uint32 PAD[2];
10322 + uint32 biststatus;
10323 + uint32 PAD[4];
10324 + uint32 intstatus;
10325 + uint32 intmask;
10326 + uint32 timer;
10327 +} mipsregs_t;
10328 +
10329 +extern uint32 sb_flag(sb_t *sbh);
10330 +extern uint sb_irq(sb_t *sbh);
10331 +
10332 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10333 +
10334 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10335 +extern void sb_jtagm_disable(void *h);
10336 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10337 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10338 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10339 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10340 +extern void BCMINIT(enable_pfc)(uint32 mode);
10341 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10342 +
10343 +
10344 +#endif /* _LANGUAGE_ASSEMBLY */
10345 +
10346 +#endif /* _SBMIPS_H */
10347 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10348 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10349 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-12-15 15:35:36.795581250 +0100
10350 @@ -0,0 +1,122 @@
10351 +/*
10352 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10353 + *
10354 + * $Id$
10355 + * Copyright 2005, Broadcom Corporation
10356 + * All Rights Reserved.
10357 + *
10358 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10359 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10360 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10361 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10362 + */
10363 +
10364 +#ifndef _SBPCI_H
10365 +#define _SBPCI_H
10366 +
10367 +/* cpp contortions to concatenate w/arg prescan */
10368 +#ifndef PAD
10369 +#define _PADLINE(line) pad ## line
10370 +#define _XSTR(line) _PADLINE(line)
10371 +#define PAD _XSTR(__LINE__)
10372 +#endif
10373 +
10374 +/* Sonics side: PCI core and host control registers */
10375 +typedef struct sbpciregs {
10376 + uint32 control; /* PCI control */
10377 + uint32 PAD[3];
10378 + uint32 arbcontrol; /* PCI arbiter control */
10379 + uint32 PAD[3];
10380 + uint32 intstatus; /* Interrupt status */
10381 + uint32 intmask; /* Interrupt mask */
10382 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10383 + uint32 PAD[9];
10384 + uint32 bcastaddr; /* Sonics broadcast address */
10385 + uint32 bcastdata; /* Sonics broadcast data */
10386 + uint32 PAD[2];
10387 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10388 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10389 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10390 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10391 + uint32 PAD[36];
10392 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10393 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10394 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10395 + uint32 PAD[445];
10396 + uint16 sprom[36]; /* SPROM shadow Area */
10397 + uint32 PAD[46];
10398 +} sbpciregs_t;
10399 +
10400 +/* PCI control */
10401 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10402 +#define PCI_RST 0x02 /* Value driven out to pin */
10403 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10404 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10405 +
10406 +/* PCI arbiter control */
10407 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10408 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10409 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10410 +#define PCI_PARKID_SHIFT 1
10411 +#define PCI_PARKID_LAST 0 /* Last requestor */
10412 +#define PCI_PARKID_4710 1 /* 4710 */
10413 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10414 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10415 +
10416 +/* Interrupt status/mask */
10417 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10418 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10419 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10420 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10421 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10422 +
10423 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10424 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10425 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10426 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10427 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10428 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10429 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10430 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10431 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10432 +
10433 +/* Sonics broadcast address */
10434 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10435 +
10436 +/* Sonics to PCI translation types */
10437 +#define SBTOPCI0_MASK 0xfc000000
10438 +#define SBTOPCI1_MASK 0xfc000000
10439 +#define SBTOPCI2_MASK 0xc0000000
10440 +#define SBTOPCI_MEM 0
10441 +#define SBTOPCI_IO 1
10442 +#define SBTOPCI_CFG0 2
10443 +#define SBTOPCI_CFG1 3
10444 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10445 +#define SBTOPCI_BURST 0x8 /* burst enable */
10446 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10447 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10448 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10449 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10450 +
10451 +/* PCI core index in SROM shadow area */
10452 +#define SRSH_PI_OFFSET 0 /* first word */
10453 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10454 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10455 +
10456 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10457 +#define cap_list rsvd_a[0]
10458 +#define bar0_window dev_dep[0x80 - 0x40]
10459 +#define bar1_window dev_dep[0x84 - 0x40]
10460 +#define sprom_control dev_dep[0x88 - 0x40]
10461 +
10462 +#ifndef _LANGUAGE_ASSEMBLY
10463 +
10464 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10465 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10466 +extern void sbpci_ban(uint16 core);
10467 +extern int sbpci_init(sb_t *sbh);
10468 +extern void sbpci_check(sb_t *sbh);
10469 +
10470 +#endif /* !_LANGUAGE_ASSEMBLY */
10471 +
10472 +#endif /* _SBPCI_H */
10473 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10474 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10475 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-12-15 15:35:40.175792500 +0100
10476 @@ -0,0 +1,75 @@
10477 +/*
10478 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10479 + *
10480 + * Copyright 2005, Broadcom Corporation
10481 + * All Rights Reserved.
10482 + *
10483 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10484 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10485 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10486 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10487 + * $Id$
10488 + */
10489 +
10490 +#ifndef _SBSDRAM_H
10491 +#define _SBSDRAM_H
10492 +
10493 +#ifndef _LANGUAGE_ASSEMBLY
10494 +
10495 +/* Sonics side: SDRAM core registers */
10496 +typedef volatile struct sbsdramregs {
10497 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10498 + uint32 config; /* Initializes external SDRAM mode register */
10499 + uint32 refresh; /* Controls external SDRAM refresh rate */
10500 + uint32 pad1;
10501 + uint32 pad2;
10502 +} sbsdramregs_t;
10503 +
10504 +#endif
10505 +
10506 +/* SDRAM initialization control (initcontrol) register bits */
10507 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10508 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10509 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10510 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10511 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10512 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10513 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10514 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10515 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10516 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10517 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10518 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10519 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10520 +
10521 +/* SDRAM configuration (config) register bits */
10522 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10523 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10524 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10525 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10526 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10527 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10528 +
10529 +/* SDRAM refresh control (refresh) register bits */
10530 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10531 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10532 +
10533 +/* SDRAM Core default Init values (OCP ID 0x803) */
10534 +#define SDRAM_INIT MEM4MX16X2
10535 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10536 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10537 +
10538 +#define MEM1MX16 0x009 /* 2 MB */
10539 +#define MEM1MX16X2 0x409 /* 4 MB */
10540 +#define MEM2MX8X2 0x809 /* 4 MB */
10541 +#define MEM2MX8X4 0xc09 /* 8 MB */
10542 +#define MEM2MX32 0x439 /* 8 MB */
10543 +#define MEM4MX16 0x019 /* 8 MB */
10544 +#define MEM4MX16X2 0x419 /* 16 MB */
10545 +#define MEM8MX8X2 0x819 /* 16 MB */
10546 +#define MEM8MX16 0x829 /* 16 MB */
10547 +#define MEM4MX32 0x429 /* 16 MB */
10548 +#define MEM8MX8X4 0xc19 /* 32 MB */
10549 +#define MEM8MX16X2 0xc29 /* 32 MB */
10550 +
10551 +#endif /* _SBSDRAM_H */
10552 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10553 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10554 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-12-15 16:00:47.404550500 +0100
10555 @@ -0,0 +1,136 @@
10556 +/*
10557 + * Misc utility routines for accessing chip-specific features
10558 + * of Broadcom HNBU SiliconBackplane-based chips.
10559 + *
10560 + * Copyright 2005, Broadcom Corporation
10561 + * All Rights Reserved.
10562 + *
10563 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10564 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10565 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10566 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10567 + *
10568 + * $Id$
10569 + */
10570 +
10571 +#ifndef _sbutils_h_
10572 +#define _sbutils_h_
10573 +
10574 +/*
10575 + * Datastructure to export all chip specific common variables
10576 + * public (read-only) portion of sbutils handle returned by
10577 + * sb_attach()/sb_kattach()
10578 +*/
10579 +
10580 +struct sb_pub {
10581 +
10582 + uint bustype; /* SB_BUS, PCI_BUS */
10583 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10584 + uint buscorerev; /* buscore rev */
10585 + uint buscoreidx; /* buscore index */
10586 + int ccrev; /* chip common core rev */
10587 + uint boardtype; /* board type */
10588 + uint boardvendor; /* board vendor */
10589 + uint chip; /* chip number */
10590 + uint chiprev; /* chip revision */
10591 + uint chippkg; /* chip package option */
10592 + uint sonicsrev; /* sonics backplane rev */
10593 +};
10594 +
10595 +typedef const struct sb_pub sb_t;
10596 +
10597 +/*
10598 + * Many of the routines below take an 'sbh' handle as their first arg.
10599 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10600 + * At any one time, the sbh is logically focused on one particular sb core
10601 + * (the "current core").
10602 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10603 + */
10604 +
10605 +/* exported externs */
10606 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10607 +extern sb_t * BCMINIT(sb_kattach)(void);
10608 +extern void sb_detach(sb_t *sbh);
10609 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10610 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10611 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10612 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10613 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10614 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10615 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10616 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10617 +extern uint sb_bus(sb_t *sbh);
10618 +extern uint sb_buscoretype(sb_t *sbh);
10619 +extern uint sb_buscorerev(sb_t *sbh);
10620 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10621 +extern uint sb_coreid(sb_t *sbh);
10622 +extern uint sb_coreidx(sb_t *sbh);
10623 +extern uint sb_coreunit(sb_t *sbh);
10624 +extern uint sb_corevendor(sb_t *sbh);
10625 +extern uint sb_corerev(sb_t *sbh);
10626 +extern void *sb_osh(sb_t *sbh);
10627 +extern void *sb_coreregs(sb_t *sbh);
10628 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10629 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10630 +extern bool sb_iscoreup(sb_t *sbh);
10631 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10632 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10633 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10634 +extern void sb_commit(sb_t *sbh);
10635 +extern uint32 sb_base(uint32 admatch);
10636 +extern uint32 sb_size(uint32 admatch);
10637 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10638 +extern void sb_core_tofixup(sb_t *sbh);
10639 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10640 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10641 +extern uint32 sb_clock(sb_t *sbh);
10642 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10643 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10644 +extern void *sb_gpiosetcore(sb_t *sbh);
10645 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10646 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10647 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10648 +extern uint32 sb_gpioin(sb_t *sbh);
10649 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10650 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10651 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10652 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10653 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10654 +
10655 +extern void sb_clkctl_init(sb_t *sbh);
10656 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10657 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10658 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10659 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10660 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10661 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10662 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10663 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10664 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10665 +
10666 +
10667 +
10668 +/*
10669 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10670 +* The returned path is NULL terminated and has trailing '/'.
10671 +* Return 0 on success, nonzero otherwise.
10672 +*/
10673 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10674 +
10675 +/* clkctl xtal what flags */
10676 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10677 +#define PLL 0x2 /* main chip pll */
10678 +
10679 +/* clkctl clk mode */
10680 +#define CLK_FAST 0 /* force fast (pll) clock */
10681 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10682 +
10683 +
10684 +/* GPIO usage priorities */
10685 +#define GPIO_DRV_PRIORITY 0
10686 +#define GPIO_APP_PRIORITY 1
10687 +
10688 +/* device path */
10689 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10690 +
10691 +#endif /* _sbutils_h_ */
10692 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10693 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10694 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-12-15 16:49:23.001703000 +0100
10695 @@ -0,0 +1,36 @@
10696 +/*
10697 + * Broadcom SiliconBackplane chipcommon serial flash interface
10698 + *
10699 + * Copyright 2005, Broadcom Corporation
10700 + * All Rights Reserved.
10701 + *
10702 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10703 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10704 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10705 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10706 + *
10707 + * $Id$
10708 + */
10709 +
10710 +#ifndef _sflash_h_
10711 +#define _sflash_h_
10712 +
10713 +#include <typedefs.h>
10714 +#include <sbchipc.h>
10715 +
10716 +struct sflash {
10717 + uint blocksize; /* Block size */
10718 + uint numblocks; /* Number of blocks */
10719 + uint32 type; /* Type */
10720 + uint size; /* Total size in bytes */
10721 +};
10722 +
10723 +/* Utility functions */
10724 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10725 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10726 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10727 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10728 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10729 +extern struct sflash * sflash_init(chipcregs_t *cc);
10730 +
10731 +#endif /* _sflash_h_ */
10732 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10733 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10734 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-12-15 15:35:49.220357750 +0100
10735 @@ -0,0 +1,33 @@
10736 +/*
10737 + * TRX image file header format.
10738 + *
10739 + * Copyright 2005, Broadcom Corporation
10740 + * All Rights Reserved.
10741 + *
10742 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10743 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10744 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10745 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10746 + *
10747 + * $Id$
10748 + */
10749 +
10750 +#include <typedefs.h>
10751 +
10752 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10753 +#define TRX_VERSION 1
10754 +#define TRX_MAX_LEN 0x3A0000
10755 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10756 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10757 +#define TRX_MAX_OFFSET 3
10758 +
10759 +struct trx_header {
10760 + uint32 magic; /* "HDR0" */
10761 + uint32 len; /* Length of file including header */
10762 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10763 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10764 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10765 +};
10766 +
10767 +/* Compatibility */
10768 +typedef struct trx_header TRXHDR, *PTRXHDR;
10769 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10770 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10771 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-12-15 15:35:52.436558750 +0100
10772 @@ -0,0 +1,326 @@
10773 +/*
10774 + * Copyright 2005, Broadcom Corporation
10775 + * All Rights Reserved.
10776 + *
10777 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10778 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10779 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10780 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10781 + * $Id$
10782 + */
10783 +
10784 +#ifndef _TYPEDEFS_H_
10785 +#define _TYPEDEFS_H_
10786 +
10787 +
10788 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10789 + * typedef file "site_typedefs.h".
10790 + *
10791 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10792 + * section of this file makes inferences about the compile environment
10793 + * based on defined symbols and possibly compiler pragmas.
10794 + *
10795 + * Following these two sections is the "Default Typedefs"
10796 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10797 + * defined. This section has a default set of typedefs and a few
10798 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10799 + */
10800 +
10801 +#ifdef SITE_TYPEDEFS
10802 +
10803 +/*******************************************************************************
10804 + * Site Specific Typedefs
10805 + *******************************************************************************/
10806 +
10807 +#include "site_typedefs.h"
10808 +
10809 +#else
10810 +
10811 +/*******************************************************************************
10812 + * Inferred Typedefs
10813 + *******************************************************************************/
10814 +
10815 +/* Infer the compile environment based on preprocessor symbols and pramas.
10816 + * Override type definitions as needed, and include configuration dependent
10817 + * header files to define types.
10818 + */
10819 +
10820 +#ifdef __cplusplus
10821 +
10822 +#define TYPEDEF_BOOL
10823 +#ifndef FALSE
10824 +#define FALSE false
10825 +#endif
10826 +#ifndef TRUE
10827 +#define TRUE true
10828 +#endif
10829 +
10830 +#else /* ! __cplusplus */
10831 +
10832 +#if defined(_WIN32)
10833 +
10834 +#define TYPEDEF_BOOL
10835 +typedef unsigned char bool; /* consistent w/BOOL */
10836 +
10837 +#endif /* _WIN32 */
10838 +
10839 +#endif /* ! __cplusplus */
10840 +
10841 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10842 +#if defined(_WIN64)
10843 +#include <basetsd.h>
10844 +#define TYPEDEF_UINTPTR
10845 +typedef ULONG_PTR uintptr;
10846 +#endif
10847 +
10848 +#ifdef _HNDRTE_
10849 +typedef long unsigned int size_t;
10850 +#endif
10851 +
10852 +#ifdef _MSC_VER /* Microsoft C */
10853 +#define TYPEDEF_INT64
10854 +#define TYPEDEF_UINT64
10855 +typedef signed __int64 int64;
10856 +typedef unsigned __int64 uint64;
10857 +#endif
10858 +
10859 +#if defined(MACOSX) && defined(KERNEL)
10860 +#define TYPEDEF_BOOL
10861 +#endif
10862 +
10863 +
10864 +#if defined(linux)
10865 +#define TYPEDEF_UINT
10866 +#define TYPEDEF_USHORT
10867 +#define TYPEDEF_ULONG
10868 +#endif
10869 +
10870 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10871 +#define TYPEDEF_UINT
10872 +#define TYPEDEF_USHORT
10873 +#endif
10874 +
10875 +
10876 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10877 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10878 +#define TYPEDEF_INT64
10879 +#define TYPEDEF_UINT64
10880 +#endif
10881 +
10882 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10883 + * for singned or unsigned */
10884 +#if defined(__ICL)
10885 +
10886 +#define TYPEDEF_INT64
10887 +
10888 +#if defined(__STDC__)
10889 +#define TYPEDEF_UINT64
10890 +#endif
10891 +
10892 +#endif /* __ICL */
10893 +
10894 +
10895 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10896 +
10897 +/* pick up ushort & uint from standard types.h */
10898 +#if defined(linux) && defined(__KERNEL__)
10899 +
10900 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10901 +
10902 +#else
10903 +
10904 +#include <sys/types.h>
10905 +
10906 +#endif
10907 +
10908 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10909 +
10910 +#if defined(MACOSX) && defined(KERNEL)
10911 +#include <IOKit/IOTypes.h>
10912 +#endif
10913 +
10914 +
10915 +/* use the default typedefs in the next section of this file */
10916 +#define USE_TYPEDEF_DEFAULTS
10917 +
10918 +#endif /* SITE_TYPEDEFS */
10919 +
10920 +
10921 +/*******************************************************************************
10922 + * Default Typedefs
10923 + *******************************************************************************/
10924 +
10925 +#ifdef USE_TYPEDEF_DEFAULTS
10926 +#undef USE_TYPEDEF_DEFAULTS
10927 +
10928 +#ifndef TYPEDEF_BOOL
10929 +typedef /*@abstract@*/ unsigned char bool;
10930 +#endif
10931 +
10932 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10933 +
10934 +#ifndef TYPEDEF_UCHAR
10935 +typedef unsigned char uchar;
10936 +#endif
10937 +
10938 +#ifndef TYPEDEF_USHORT
10939 +typedef unsigned short ushort;
10940 +#endif
10941 +
10942 +#ifndef TYPEDEF_UINT
10943 +typedef unsigned int uint;
10944 +#endif
10945 +
10946 +#ifndef TYPEDEF_ULONG
10947 +typedef unsigned long ulong;
10948 +#endif
10949 +
10950 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
10951 +
10952 +#ifndef TYPEDEF_UINT8
10953 +typedef unsigned char uint8;
10954 +#endif
10955 +
10956 +#ifndef TYPEDEF_UINT16
10957 +typedef unsigned short uint16;
10958 +#endif
10959 +
10960 +#ifndef TYPEDEF_UINT32
10961 +typedef unsigned int uint32;
10962 +#endif
10963 +
10964 +#ifndef TYPEDEF_UINT64
10965 +typedef unsigned long long uint64;
10966 +#endif
10967 +
10968 +#ifndef TYPEDEF_UINTPTR
10969 +typedef unsigned int uintptr;
10970 +#endif
10971 +
10972 +#ifndef TYPEDEF_INT8
10973 +typedef signed char int8;
10974 +#endif
10975 +
10976 +#ifndef TYPEDEF_INT16
10977 +typedef signed short int16;
10978 +#endif
10979 +
10980 +#ifndef TYPEDEF_INT32
10981 +typedef signed int int32;
10982 +#endif
10983 +
10984 +#ifndef TYPEDEF_INT64
10985 +typedef signed long long int64;
10986 +#endif
10987 +
10988 +/*----------------------- define float32/64, float_t -----------------------*/
10989 +
10990 +#ifndef TYPEDEF_FLOAT32
10991 +typedef float float32;
10992 +#endif
10993 +
10994 +#ifndef TYPEDEF_FLOAT64
10995 +typedef double float64;
10996 +#endif
10997 +
10998 +/*
10999 + * abstracted floating point type allows for compile time selection of
11000 + * single or double precision arithmetic. Compiling with -DFLOAT32
11001 + * selects single precision; the default is double precision.
11002 + */
11003 +
11004 +#ifndef TYPEDEF_FLOAT_T
11005 +
11006 +#if defined(FLOAT32)
11007 +typedef float32 float_t;
11008 +#else /* default to double precision floating point */
11009 +typedef float64 float_t;
11010 +#endif
11011 +
11012 +#endif /* TYPEDEF_FLOAT_T */
11013 +
11014 +/*----------------------- define macro values -----------------------------*/
11015 +
11016 +#ifndef FALSE
11017 +#define FALSE 0
11018 +#endif
11019 +
11020 +#ifndef TRUE
11021 +#define TRUE 1
11022 +#endif
11023 +
11024 +#ifndef NULL
11025 +#define NULL 0
11026 +#endif
11027 +
11028 +#ifndef OFF
11029 +#define OFF 0
11030 +#endif
11031 +
11032 +#ifndef ON
11033 +#define ON 1
11034 +#endif
11035 +
11036 +#define AUTO (-1)
11037 +
11038 +/* Reclaiming text and data :
11039 + The following macros specify special linker sections that can be reclaimed
11040 + after a system is considered 'up'.
11041 + */
11042 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11043 +extern bool bcmreclaimed;
11044 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11045 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11046 +#define BCMINIT(_id) _id##_ini
11047 +#else
11048 +#define BCMINITDATA(_data) _data
11049 +#define BCMINITFN(_fn) _fn
11050 +#define BCMINIT(_id) _id
11051 +#define bcmreclaimed 0
11052 +#endif
11053 +
11054 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11055 +
11056 +#ifndef PTRSZ
11057 +#define PTRSZ sizeof (char*)
11058 +#endif
11059 +
11060 +#ifndef INLINE
11061 +
11062 +#ifdef _MSC_VER
11063 +
11064 +#define INLINE __inline
11065 +
11066 +#elif __GNUC__
11067 +
11068 +#define INLINE __inline__
11069 +
11070 +#else
11071 +
11072 +#define INLINE
11073 +
11074 +#endif /* _MSC_VER */
11075 +
11076 +#endif /* INLINE */
11077 +
11078 +#undef TYPEDEF_BOOL
11079 +#undef TYPEDEF_UCHAR
11080 +#undef TYPEDEF_USHORT
11081 +#undef TYPEDEF_UINT
11082 +#undef TYPEDEF_ULONG
11083 +#undef TYPEDEF_UINT8
11084 +#undef TYPEDEF_UINT16
11085 +#undef TYPEDEF_UINT32
11086 +#undef TYPEDEF_UINT64
11087 +#undef TYPEDEF_UINTPTR
11088 +#undef TYPEDEF_INT8
11089 +#undef TYPEDEF_INT16
11090 +#undef TYPEDEF_INT32
11091 +#undef TYPEDEF_INT64
11092 +#undef TYPEDEF_FLOAT32
11093 +#undef TYPEDEF_FLOAT64
11094 +#undef TYPEDEF_FLOAT_T
11095 +
11096 +#endif /* USE_TYPEDEF_DEFAULTS */
11097 +
11098 +#endif /* _TYPEDEFS_H_ */
11099 diff -urN linux.old/arch/mips/bcm947xx/int-handler.S linux.dev/arch/mips/bcm947xx/int-handler.S
11100 --- linux.old/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
11101 +++ linux.dev/arch/mips/bcm947xx/int-handler.S 2005-12-15 12:57:27.877187750 +0100
11102 @@ -0,0 +1,48 @@
11103 +/*
11104 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11105 + *
11106 + * This program is free software; you can redistribute it and/or modify it
11107 + * under the terms of the GNU General Public License as published by the
11108 + * Free Software Foundation; either version 2 of the License, or (at your
11109 + * option) any later version.
11110 + *
11111 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11112 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11113 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11114 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11115 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11116 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11117 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11118 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11119 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11120 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11121 + *
11122 + * You should have received a copy of the GNU General Public License along
11123 + * with this program; if not, write to the Free Software Foundation, Inc.,
11124 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11125 + */
11126 +
11127 +#include <asm/asm.h>
11128 +#include <asm/mipsregs.h>
11129 +#include <asm/regdef.h>
11130 +#include <asm/stackframe.h>
11131 +
11132 + .text
11133 + .set noreorder
11134 + .set noat
11135 + .align 5
11136 +
11137 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
11138 + SAVE_ALL
11139 + CLI
11140 +
11141 + .set at
11142 + .set noreorder
11143 +
11144 + jal bcm47xx_irq_dispatch
11145 + move a0, sp
11146 +
11147 + j ret_from_irq
11148 + nop
11149 +
11150 + END(bcm47xx_irq_handler)
11151 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11152 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11153 +++ linux.dev/arch/mips/bcm947xx/irq.c 2005-12-15 12:57:27.877187750 +0100
11154 @@ -0,0 +1,67 @@
11155 +/*
11156 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11157 + *
11158 + * This program is free software; you can redistribute it and/or modify it
11159 + * under the terms of the GNU General Public License as published by the
11160 + * Free Software Foundation; either version 2 of the License, or (at your
11161 + * option) any later version.
11162 + *
11163 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11164 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11165 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11166 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11167 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11168 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11169 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11170 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11171 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11172 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11173 + *
11174 + * You should have received a copy of the GNU General Public License along
11175 + * with this program; if not, write to the Free Software Foundation, Inc.,
11176 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11177 + */
11178 +
11179 +#include <linux/config.h>
11180 +#include <linux/errno.h>
11181 +#include <linux/init.h>
11182 +#include <linux/interrupt.h>
11183 +#include <linux/irq.h>
11184 +#include <linux/module.h>
11185 +#include <linux/smp.h>
11186 +#include <linux/types.h>
11187 +
11188 +#include <asm/cpu.h>
11189 +#include <asm/io.h>
11190 +#include <asm/irq.h>
11191 +#include <asm/irq_cpu.h>
11192 +
11193 +extern asmlinkage void bcm47xx_irq_handler(void);
11194 +
11195 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
11196 +{
11197 + u32 cause;
11198 +
11199 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11200 +
11201 + clear_c0_status(cause);
11202 +
11203 + if (cause & CAUSEF_IP7)
11204 + do_IRQ(7, regs);
11205 + if (cause & CAUSEF_IP2)
11206 + do_IRQ(2, regs);
11207 + if (cause & CAUSEF_IP3)
11208 + do_IRQ(3, regs);
11209 + if (cause & CAUSEF_IP4)
11210 + do_IRQ(4, regs);
11211 + if (cause & CAUSEF_IP5)
11212 + do_IRQ(5, regs);
11213 + if (cause & CAUSEF_IP6)
11214 + do_IRQ(6, regs);
11215 +}
11216 +
11217 +void __init arch_init_irq(void)
11218 +{
11219 + set_except_vector(0, bcm47xx_irq_handler);
11220 + mips_cpu_irq_init(0);
11221 +}
11222 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11223 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11224 +++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-18 07:01:36.731635000 +0100
11225 @@ -0,0 +1,215 @@
11226 +#include <linux/kernel.h>
11227 +#include <linux/init.h>
11228 +#include <linux/pci.h>
11229 +#include <linux/types.h>
11230 +
11231 +#include <asm/cpu.h>
11232 +#include <asm/io.h>
11233 +
11234 +#include <typedefs.h>
11235 +#include <osl.h>
11236 +#include <sbutils.h>
11237 +#include <sbmips.h>
11238 +#include <sbconfig.h>
11239 +#include <sbpci.h>
11240 +#include <bcmdevs.h>
11241 +#include <pcicfg.h>
11242 +
11243 +extern sb_t *sbh;
11244 +extern spinlock_t sbh_lock;
11245 +
11246 +
11247 +static int
11248 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11249 + int reg, int size, u32 *val)
11250 +{
11251 + int ret;
11252 + unsigned long flags;
11253 +
11254 + spin_lock_irqsave(&sbh_lock, flags);
11255 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11256 + spin_unlock_irqrestore(&sbh_lock, flags);
11257 +
11258 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11259 +}
11260 +
11261 +static int
11262 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11263 + int reg, int size, u32 val)
11264 +{
11265 + int ret;
11266 + unsigned long flags;
11267 +
11268 + spin_lock_irqsave(&sbh_lock, flags);
11269 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11270 + spin_unlock_irqrestore(&sbh_lock, flags);
11271 +
11272 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11273 +}
11274 +
11275 +
11276 +static struct pci_ops sb_pci_ops = {
11277 + .read = sb_pci_read_config,
11278 + .write = sb_pci_write_config,
11279 +};
11280 +
11281 +static struct resource sb_pci_mem_resource = {
11282 + .name = "SB PCI Memory resources",
11283 + .start = SB_ENUM_BASE,
11284 + .end = SB_ENUM_LIM - 1,
11285 + .flags = IORESOURCE_MEM,
11286 +};
11287 +
11288 +static struct resource sb_pci_io_resource = {
11289 + .name = "SB PCI I/O resources",
11290 + .start = 0x000,
11291 + .end = 0x0FF,
11292 + .flags = IORESOURCE_IO,
11293 +};
11294 +
11295 +static struct pci_controller bcm47xx_sb_pci_controller = {
11296 + .pci_ops = &sb_pci_ops,
11297 + .mem_resource = &sb_pci_mem_resource,
11298 + .io_resource = &sb_pci_io_resource,
11299 +};
11300 +
11301 +static struct resource ext_pci_mem_resource = {
11302 + .name = "Ext PCI Memory resources",
11303 + .start = 0x40000000,
11304 + .end = 0x7fffffff,
11305 + .flags = IORESOURCE_MEM,
11306 +};
11307 +
11308 +static struct resource ext_pci_io_resource = {
11309 + .name = "Ext PCI I/O resources",
11310 + .start = 0x100,
11311 + .end = 0x1FF,
11312 + .flags = IORESOURCE_IO,
11313 +};
11314 +
11315 +static struct pci_controller bcm47xx_ext_pci_controller = {
11316 + .pci_ops = &sb_pci_ops,
11317 + .io_resource = &ext_pci_io_resource,
11318 + .mem_resource = &ext_pci_mem_resource,
11319 + .mem_offset = 0x24000000,
11320 +};
11321 +
11322 +void bcm47xx_pci_init(void)
11323 +{
11324 + unsigned long flags;
11325 +
11326 + spin_lock_irqsave(&sbh_lock, flags);
11327 + sbpci_init(sbh);
11328 + spin_unlock_irqrestore(&sbh_lock, flags);
11329 +
11330 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11331 +
11332 + register_pci_controller(&bcm47xx_sb_pci_controller);
11333 + register_pci_controller(&bcm47xx_ext_pci_controller);
11334 +}
11335 +
11336 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11337 +{
11338 + u8 irq;
11339 +
11340 + if (dev->bus->number == 1)
11341 + return 2;
11342 +
11343 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11344 + return irq + 2;
11345 +}
11346 +
11347 +u32 pci_iobase = 0x100;
11348 +u32 pci_membase = SB_PCI_DMA;
11349 +
11350 +static void bcm47xx_fixup_device(struct pci_dev *d)
11351 +{
11352 + struct resource *res;
11353 + int pos, size;
11354 + u32 *base;
11355 +
11356 + if (d->bus->number == 0)
11357 + return;
11358 +
11359 + printk("PCI: Fixing up device %s\n", pci_name(d));
11360 +
11361 + /* Fix up resource bases */
11362 + for (pos = 0; pos < 6; pos++) {
11363 + res = &d->resource[pos];
11364 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11365 + if (res->end) {
11366 + size = res->end - res->start + 1;
11367 + if (*base & (size - 1))
11368 + *base = (*base + size) & ~(size - 1);
11369 + res->start = *base;
11370 + res->end = res->start + size - 1;
11371 + *base += size;
11372 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11373 + }
11374 + /* Fix up PCI bridge BAR0 only */
11375 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11376 + break;
11377 + }
11378 + /* Fix up interrupt lines */
11379 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11380 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11381 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11382 +}
11383 +
11384 +
11385 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11386 +{
11387 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11388 + return;
11389 +
11390 + printk("PCI: fixing up bridge\n");
11391 +
11392 + /* Enable PCI bridge bus mastering and memory space */
11393 + pci_set_master(dev);
11394 + pcibios_enable_device(dev, ~0);
11395 +
11396 + /* Enable PCI bridge BAR1 prefetch and burst */
11397 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11398 +}
11399 +
11400 +/* Do platform specific device initialization at pci_enable_device() time */
11401 +int pcibios_plat_dev_init(struct pci_dev *dev)
11402 +{
11403 + uint coreidx;
11404 + unsigned long flags;
11405 +
11406 + bcm47xx_fixup_device(dev);
11407 +
11408 + /* These cores come out of reset enabled */
11409 + if ((dev->bus->number != 0) ||
11410 + (dev->device == SB_MIPS) ||
11411 + (dev->device == SB_MIPS33) ||
11412 + (dev->device == SB_EXTIF) ||
11413 + (dev->device == SB_CC))
11414 + return 0;
11415 +
11416 + /* Do a core reset */
11417 + spin_lock_irqsave(&sbh_lock, flags);
11418 + coreidx = sb_coreidx(sbh);
11419 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11420 + /*
11421 + * The USB core requires a special bit to be set during core
11422 + * reset to enable host (OHCI) mode. Resetting the SB core in
11423 + * pcibios_enable_device() is a hack for compatibility with
11424 + * vanilla usb-ohci so that it does not have to know about
11425 + * SB. A driver that wants to use the USB core in device mode
11426 + * should know about SB and should reset the bit back to 0
11427 + * after calling pcibios_enable_device().
11428 + */
11429 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11430 + sb_core_reset(sbh, 1 << 29);
11431 + } else {
11432 + sb_core_reset(sbh, 0);
11433 + }
11434 + sb_setcoreidx(sbh, coreidx);
11435 + spin_unlock_irqrestore(&sbh_lock, flags);
11436 +
11437 + return 0;
11438 +}
11439 +
11440 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11441 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11442 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11443 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-12-15 12:57:27.877187750 +0100
11444 @@ -0,0 +1,59 @@
11445 +/*
11446 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11447 + *
11448 + * This program is free software; you can redistribute it and/or modify it
11449 + * under the terms of the GNU General Public License as published by the
11450 + * Free Software Foundation; either version 2 of the License, or (at your
11451 + * option) any later version.
11452 + *
11453 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11454 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11455 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11456 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11457 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11458 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11459 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11460 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11461 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11462 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11463 + *
11464 + * You should have received a copy of the GNU General Public License along
11465 + * with this program; if not, write to the Free Software Foundation, Inc.,
11466 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11467 + */
11468 +
11469 +#include <linux/init.h>
11470 +#include <linux/mm.h>
11471 +#include <linux/sched.h>
11472 +#include <linux/bootmem.h>
11473 +
11474 +#include <asm/addrspace.h>
11475 +#include <asm/bootinfo.h>
11476 +#include <asm/pmon.h>
11477 +
11478 +const char *get_system_type(void)
11479 +{
11480 + return "Broadcom BCM47xx";
11481 +}
11482 +
11483 +void __init prom_init(void)
11484 +{
11485 + unsigned long mem;
11486 +
11487 + mips_machgroup = MACH_GROUP_BRCM;
11488 + mips_machtype = MACH_BCM47XX;
11489 +
11490 + /* Figure out memory size by finding aliases */
11491 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11492 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11493 + *(unsigned long *)(prom_init))
11494 + break;
11495 + }
11496 +
11497 + add_memory_region(0, mem, BOOT_MEM_RAM);
11498 +}
11499 +
11500 +unsigned long __init prom_free_prom_memory(void)
11501 +{
11502 + return 0;
11503 +}
11504 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11505 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11506 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-18 06:34:52.106215250 +0100
11507 @@ -0,0 +1,157 @@
11508 +/*
11509 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11510 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11511 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11512 + *
11513 + * This program is free software; you can redistribute it and/or modify it
11514 + * under the terms of the GNU General Public License as published by the
11515 + * Free Software Foundation; either version 2 of the License, or (at your
11516 + * option) any later version.
11517 + *
11518 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11519 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11520 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11521 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11522 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11523 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11524 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11525 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11526 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11527 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11528 + *
11529 + * You should have received a copy of the GNU General Public License along
11530 + * with this program; if not, write to the Free Software Foundation, Inc.,
11531 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11532 + */
11533 +
11534 +#include <linux/init.h>
11535 +#include <linux/types.h>
11536 +#include <linux/tty.h>
11537 +#include <linux/serial.h>
11538 +#include <linux/serial_core.h>
11539 +#include <linux/serial_reg.h>
11540 +#include <asm/bootinfo.h>
11541 +#include <asm/time.h>
11542 +#include <asm/reboot.h>
11543 +
11544 +#include <typedefs.h>
11545 +#include <osl.h>
11546 +#include <sbutils.h>
11547 +#include <sbmips.h>
11548 +#include <sbpci.h>
11549 +#include <sbconfig.h>
11550 +#include <bcmdevs.h>
11551 +#include <bcmutils.h>
11552 +#include <bcmnvram.h>
11553 +
11554 +extern void bcm47xx_pci_init(void);
11555 +extern void bcm47xx_time_init(void);
11556 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11557 +void *sbh;
11558 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11559 +int boardflags;
11560 +
11561 +static int ser_line = 0;
11562 +
11563 +typedef struct {
11564 + void *regs;
11565 + uint irq;
11566 + uint baud_base;
11567 + uint reg_shift;
11568 +} serial_port;
11569 +
11570 +static serial_port ports[4];
11571 +static int num_ports = 0;
11572 +
11573 +static void
11574 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11575 +{
11576 + ports[num_ports].regs = regs;
11577 + ports[num_ports].irq = irq;
11578 + ports[num_ports].baud_base = baud_base;
11579 + ports[num_ports].reg_shift = reg_shift;
11580 + num_ports++;
11581 +}
11582 +
11583 +static void
11584 +do_serial_add(serial_port *port)
11585 +{
11586 + void *regs;
11587 + uint irq;
11588 + uint baud_base;
11589 + uint reg_shift;
11590 + struct uart_port s;
11591 +
11592 + regs = port->regs;
11593 + irq = port->irq;
11594 + baud_base = port->baud_base;
11595 + reg_shift = port->reg_shift;
11596 +
11597 + memset(&s, 0, sizeof(s));
11598 +
11599 + s.line = ser_line++;
11600 + s.membase = regs;
11601 + s.irq = irq + 2;
11602 + s.uartclk = baud_base;
11603 + s.flags = ASYNC_BOOT_AUTOCONF;
11604 + s.iotype = SERIAL_IO_MEM;
11605 + s.regshift = reg_shift;
11606 +
11607 + if (early_serial_setup(&s) != 0) {
11608 + printk(KERN_ERR "Serial setup failed!\n");
11609 + }
11610 +}
11611 +
11612 +static void bcm47xx_machine_restart(char *command)
11613 +{
11614 + printk("Please stand by while rebooting the system...\n");
11615 +
11616 + /* Set the watchdog timer to reset immediately */
11617 + local_irq_disable();
11618 + sb_watchdog(sbh, 1);
11619 + while (1);
11620 +}
11621 +
11622 +static void bcm47xx_machine_halt(void)
11623 +{
11624 + /* Disable interrupts and watchdog and spin forever */
11625 + local_irq_disable();
11626 + sb_watchdog(sbh, 0);
11627 + while (1);
11628 +}
11629 +
11630 +void __init plat_setup(void)
11631 +{
11632 + char *s;
11633 + int i;
11634 +
11635 + sbh = (void *) sb_kattach();
11636 + sb_mips_init(sbh);
11637 +
11638 + bcm47xx_pci_init();
11639 +
11640 + sb_serial_init(sbh, serial_add);
11641 + boardflags = getintvar(NULL, "boardflags");
11642 +
11643 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11644 + s = nvram_get("kernel_args");
11645 + if (!s) s = "";
11646 + if (!strncmp(s, "console=ttyS1", 13)) {
11647 + for (i = num_ports; i; i--)
11648 + do_serial_add(&ports[i - 1]);
11649 + } else {
11650 + for (i = 0; i < num_ports; i++)
11651 + do_serial_add(&ports[i]);
11652 + }
11653 +
11654 + _machine_restart = bcm47xx_machine_restart;
11655 + _machine_halt = bcm47xx_machine_halt;
11656 + _machine_power_off = bcm47xx_machine_halt;
11657 +
11658 + board_time_init = bcm47xx_time_init;
11659 + board_timer_setup = bcm47xx_timer_setup;
11660 +}
11661 +
11662 +EXPORT_SYMBOL(sbh);
11663 +EXPORT_SYMBOL(sbh_lock);
11664 +EXPORT_SYMBOL(boardflags);
11665 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11666 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11667 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-12-15 12:57:27.877187750 +0100
11668 @@ -0,0 +1,59 @@
11669 +/*
11670 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11671 + *
11672 + * This program is free software; you can redistribute it and/or modify it
11673 + * under the terms of the GNU General Public License as published by the
11674 + * Free Software Foundation; either version 2 of the License, or (at your
11675 + * option) any later version.
11676 + *
11677 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11678 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11679 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11680 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11681 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11682 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11683 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11684 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11685 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11686 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11687 + *
11688 + * You should have received a copy of the GNU General Public License along
11689 + * with this program; if not, write to the Free Software Foundation, Inc.,
11690 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11691 + */
11692 +
11693 +#include <linux/config.h>
11694 +#include <linux/init.h>
11695 +#include <linux/kernel.h>
11696 +#include <linux/sched.h>
11697 +#include <linux/serial_reg.h>
11698 +#include <linux/interrupt.h>
11699 +#include <asm/addrspace.h>
11700 +#include <asm/io.h>
11701 +#include <asm/time.h>
11702 +
11703 +void __init
11704 +bcm47xx_time_init(void)
11705 +{
11706 + unsigned int hz;
11707 +
11708 + /*
11709 + * Use deterministic values for initial counter interrupt
11710 + * so that calibrate delay avoids encountering a counter wrap.
11711 + */
11712 + write_c0_count(0);
11713 + write_c0_compare(0xffff);
11714 +
11715 + hz = 200 * 1000 * 1000;
11716 +
11717 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11718 + mips_hpt_frequency = hz / 2;
11719 +
11720 +}
11721 +
11722 +void __init
11723 +bcm47xx_timer_setup(struct irqaction *irq)
11724 +{
11725 + /* Enable the timer interrupt */
11726 + setup_irq(7, irq);
11727 +}
11728 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11729 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-12-15 13:26:49.766024000 +0100
11730 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-12-15 12:57:27.901177250 +0100
11731 @@ -656,6 +656,28 @@
11732 }
11733
11734
11735 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11736 +{
11737 + decode_config1(c);
11738 + switch (c->processor_id & 0xff00) {
11739 + case PRID_IMP_BCM3302:
11740 + c->cputype = CPU_BCM3302;
11741 + c->isa_level = MIPS_CPU_ISA_M32;
11742 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11743 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11744 + break;
11745 + case PRID_IMP_BCM4710:
11746 + c->cputype = CPU_BCM4710;
11747 + c->isa_level = MIPS_CPU_ISA_M32;
11748 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11749 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11750 + break;
11751 + default:
11752 + c->cputype = CPU_UNKNOWN;
11753 + break;
11754 + }
11755 +}
11756 +
11757 __init void cpu_probe(void)
11758 {
11759 struct cpuinfo_mips *c = &current_cpu_data;
11760 @@ -678,6 +700,9 @@
11761 case PRID_COMP_SIBYTE:
11762 cpu_probe_sibyte(c);
11763 break;
11764 + case PRID_COMP_BROADCOM:
11765 + cpu_probe_broadcom(c);
11766 + break;
11767 case PRID_COMP_SANDCRAFT:
11768 cpu_probe_sandcraft(c);
11769 break;
11770 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11771 --- linux.old/arch/mips/kernel/head.S 2005-12-15 13:26:49.766024000 +0100
11772 +++ linux.dev/arch/mips/kernel/head.S 2005-12-15 12:57:27.901177250 +0100
11773 @@ -107,6 +107,14 @@
11774 #endif
11775 .endm
11776
11777 +#ifdef CONFIG_BCM4710
11778 +#undef eret
11779 +#define eret nop; nop; eret
11780 +#endif
11781 +
11782 + j kernel_entry
11783 + nop
11784 +
11785 /*
11786 * Reserved space for exception handlers.
11787 * Necessary for machines which link their kernels at KSEG0.
11788 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11789 --- linux.old/arch/mips/kernel/proc.c 2005-12-15 13:26:49.766024000 +0100
11790 +++ linux.dev/arch/mips/kernel/proc.c 2005-12-15 12:57:27.921168500 +0100
11791 @@ -82,6 +82,8 @@
11792 [CPU_VR4181] = "NEC VR4181",
11793 [CPU_VR4181A] = "NEC VR4181A",
11794 [CPU_SR71000] = "Sandcraft SR71000",
11795 + [CPU_BCM3302] = "Broadcom BCM3302",
11796 + [CPU_BCM4710] = "Broadcom BCM4710",
11797 [CPU_PR4450] = "Philips PR4450",
11798 };
11799
11800 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11801 --- linux.old/arch/mips/mm/tlbex.c 2005-12-15 13:26:49.794011750 +0100
11802 +++ linux.dev/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
11803 @@ -858,6 +858,8 @@
11804 case CPU_4KSC:
11805 case CPU_20KC:
11806 case CPU_25KF:
11807 + case CPU_BCM3302:
11808 + case CPU_BCM4710:
11809 tlbw(p);
11810 break;
11811
11812 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11813 --- linux.old/include/asm-mips/bootinfo.h 2005-12-15 13:26:49.818001250 +0100
11814 +++ linux.dev/include/asm-mips/bootinfo.h 2005-12-15 12:57:27.969147500 +0100
11815 @@ -218,6 +218,12 @@
11816 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11817 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11818
11819 +/*
11820 + * Valid machtype for group Broadcom
11821 + */
11822 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11823 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11824 +
11825 #define CL_SIZE COMMAND_LINE_SIZE
11826
11827 const char *get_system_type(void);
11828 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11829 --- linux.old/include/asm-mips/cpu.h 2005-12-15 13:26:49.818001250 +0100
11830 +++ linux.dev/include/asm-mips/cpu.h 2005-12-15 12:57:27.969147500 +0100
11831 @@ -102,6 +102,13 @@
11832 #define PRID_IMP_SR71000 0x0400
11833
11834 /*
11835 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11836 + */
11837 +
11838 +#define PRID_IMP_BCM4710 0x4000
11839 +#define PRID_IMP_BCM3302 0x9000
11840 +
11841 +/*
11842 * Definitions for 7:0 on legacy processors
11843 */
11844
11845 @@ -196,7 +203,9 @@
11846 #define CPU_34K 60
11847 #define CPU_PR4450 61
11848 #define CPU_SB1A 62
11849 -#define CPU_LAST 62
11850 +#define CPU_BCM3302 63
11851 +#define CPU_BCM4710 64
11852 +#define CPU_LAST 64
11853
11854 /*
11855 * ISA Level encodings
11856 diff -urN linux.old/include/linux/init.h linux.dev/include/linux/init.h
11857 --- linux.old/include/linux/init.h 2005-12-15 13:26:49.818001250 +0100
11858 +++ linux.dev/include/linux/init.h 2005-12-15 12:57:27.973145750 +0100
11859 @@ -86,6 +86,8 @@
11860 static initcall_t __initcall_##fn __attribute_used__ \
11861 __attribute__((__section__(".initcall" level ".init"))) = fn
11862
11863 +#define early_initcall(fn) __define_initcall(".early1",fn)
11864 +
11865 #define core_initcall(fn) __define_initcall("1",fn)
11866 #define postcore_initcall(fn) __define_initcall("2",fn)
11867 #define arch_initcall(fn) __define_initcall("3",fn)
11868 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11869 --- linux.old/include/linux/pci_ids.h 2005-12-15 13:26:49.818001250 +0100
11870 +++ linux.dev/include/linux/pci_ids.h 2005-12-15 12:57:27.977144000 +0100
11871 @@ -1835,6 +1835,7 @@
11872 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11873 #define PCI_DEVICE_ID_BCM4401 0x4401
11874 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11875 +#define PCI_DEVICE_ID_BCM4713 0x4713
11876
11877 #define PCI_VENDOR_ID_TOPIC 0x151f
11878 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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