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ar71xx: fix random wireless mac address on the TEW-632BRP/DIR-615 boards
[openwrt.git] / target / linux / ep93xx / patches-2.6.30 / 001-ep93xx-regs.patch
1 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
2 +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
3 @@ -57,6 +57,33 @@
4 #define EP93XX_APB_SIZE 0x00200000
5
6
7 +/* 8081_0000 - 8081_ffff: Timers */
8 +#define TIMERS_OFFSET 0x010000
9 +#define TIMERS_BASE (EP93XX_APB_VIRT_BASE|TIMERS_OFFSET)
10 +
11 +#define TIMER1LOAD (TIMERS_BASE+0x00)
12 +#define TIMER1VALUE (TIMERS_BASE+0x04)
13 +#define TIMER1CONTROL (TIMERS_BASE+0x08)
14 +#define TIMER1CLEAR (TIMERS_BASE+0x0C)
15 +#define TIMER1TEST (TIMERS_BASE+0x10)
16 +
17 +#define TIMER2LOAD (TIMERS_BASE+0x20)
18 +#define TIMER2VALUE (TIMERS_BASE+0x24)
19 +#define TIMER2CONTROL (TIMERS_BASE+0x28)
20 +#define TIMER2CLEAR (TIMERS_BASE+0x2C)
21 +#define TIMER2TEST (TIMERS_BASE+0x30)
22 +
23 +#define TIMER3LOAD (TIMERS_BASE+0x80)
24 +#define TIMER3VALUE (TIMERS_BASE+0x84)
25 +#define TIMER3CONTROL (TIMERS_BASE+0x88)
26 +#define TIMER3CLEAR (TIMERS_BASE+0x8C)
27 +#define TIMER3TEST (TIMERS_BASE+0x90)
28 +
29 +#define TTIMERBZCONT (TIMERS_BASE+0x40)
30 +
31 +#define TIMER4VALUELOW (TIMERS_BASE+0x60)
32 +#define TIMER4VALUEHIGH (TIMERS_BASE+0x64)
33 +
34 /* AHB peripherals */
35 #define EP93XX_DMA_BASE ((void __iomem *) \
36 (EP93XX_AHB_VIRT_BASE + 0x00000000))
37 @@ -105,6 +132,8 @@
38 #define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000)
39
40 #define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000)
41 +#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
42 +#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
43
44 #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000)
45 #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
46 @@ -127,6 +156,7 @@
47 #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000)
48
49 #define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000)
50 +#define EP93XX_SPI_BASE_PHYS (EP93XX_APB_PHYS_BASE + 0x000a0000)
51
52 #define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000)
53
54 @@ -164,8 +194,425 @@
55 #define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20)
56 #define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18)
57 #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
58 +#define EP93XX_SYSCON_CHIP_ID EP93XX_SYSCON_REG(0x94)
59 +#define EP93XX_SYSCON_BMAR EP93XX_SYSCON_REG(0x54)
60 +#define EP93XX_SYSCON_I2SDIV EP93XX_SYSCON_REG(0x8C)
61 +#define EP93XX_SYSCON_DEVCFG_CONFIG_Mong 0x02000000
62 +#define EP93XX_SYSCON_DEVCFG_CONFIG_Tong 0x04000000
63 +#define EP93XX_SYSCON_DEVCFG_CONFIG_I2SONSSP 0x00000080
64 +#define EP93XX_SYSCON_DEVCFG_CONFIG_I2SONAC97 0x00000040
65 +#define EP93XX_SYSCON_DEVCFG_RasOnP3 0x00000010
66 +#define EP93XX_SYSCON_DEVCFG_A1onG 0x00200000
67 +#define EP93XX_SYSCON_DEVCFG_A2onG 0x00400000
68 +#define EP93XX_SYSCON_DEVCFG_U1EN 0x00040000
69 +#define EP93XX_SYSCON_DEVCFG_TIN 0x00020000
70
71 #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000)
72
73
74 +#define SYSCON_PWRCNT (EP93XX_SYSCON_BASE+0x0004)
75 +#define SYSCON_VIDDIV (EP93XX_SYSCON_BASE+0x0084)
76 +#define SYSCON_MIRDIV (EP93XX_SYSCON_BASE+0x0088)
77 +#define SYSCON_KTDIV (EP93XX_SYSCON_BASE+0x0090)
78 +#define SYSCON_KTDIV_TSEN 0x80000000
79 +//-----------------------------------------------------------------------------
80 +// SYSCON_CLKSET1
81 +//-----------------------------------------------------------------------------
82 +#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0
83 +#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f
84 +#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5
85 +#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0
86 +#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11
87 +#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800
88 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
89 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
90 +#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18
91 +#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000
92 +#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20
93 +#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000
94 +#define SYSCON_CLKSET1_nBYP1 0x00800000
95 +#define SYSCON_CLKSET1_SMCROM 0x01000000
96 +#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25
97 +#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000
98 +
99 +#define SYSCON_CLKSET1_HSEL 0x00000001
100 +#define SYSCON_CLKSET1_PLL1_EXCLKSEL 0x00000002
101 +
102 +#define SYSCON_CLKSET1_PLL1_P_MASK 0x0000007C
103 +#define SYSCON_CLKSET1_PLL1_P_SHIFT 2
104 +
105 +#define SYSCON_CLKSET1_PLL1_M1_MASK 0x00000780
106 +#define SYSCON_CLKSET1_PLL1_M1_SHIFT 7
107 +#define SYSCON_CLKSET1_PLL1_M2_MASK 0x0000F800
108 +#define SYSCON_CLKSET1_PLL1_M2_SHIFT 11
109 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000
110 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16
111 +#define SYSCON_CLKSET1_PCLK_DIV_MASK 0x000C0000
112 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
113 +#define SYSCON_CLKSET1_HCLK_DIV_MASK 0x00700000
114 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
115 +#define SYSCON_CLKSET1_SMCROM 0x01000000
116 +#define SYSCON_CLKSET1_FCLK_DIV_MASK 0x0E000000
117 +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
118 +
119 +#define SYSCON_CLKSET2_PLL2_EN 0x00000001
120 +#define SYSCON_CLKSET2_PLL2EXCLKSEL 0x00000002
121 +#define SYSCON_CLKSET2_PLL2_P_MASK 0x0000007C
122 +#define SYSCON_CLKSET2_PLL2_P_SHIFT 2
123 +#define SYSCON_CLKSET2_PLL2_M2_MASK 0x00000F80
124 +#define SYSCON_CLKSET2_PLL2_M2_SHIFT 7
125 +#define SYSCON_CLKSET2_PLL2_M1_MASK 0x0001F000
126 +#define SYSCON_CLKSET2_PLL2_M1 12
127 +#define SYSCON_CLKSET2_PLL2_PS_MASK 0x000C0000
128 +#define SYSCON_CLKSET2_PLL2_PS_SHIFT 18
129 +#define SYSCON_CLKSET2_USBDIV_MASK 0xF0000000
130 +#define SYSCON_CLKSET2_USBDIV_SHIFT 28
131 +
132 +//-----------------------------------------------------------------------------
133 +// I2SDIV Register Defines
134 +//-----------------------------------------------------------------------------
135 +#define SYSCON_I2SDIV_MDIV_MASK 0x0000007f
136 +#define SYSCON_I2SDIV_MDIV_SHIFT 0
137 +#define SYSCON_I2SDIV_PDIV_MASK 0x00000300
138 +#define SYSCON_I2SDIV_PDIV_SHIFT 8
139 +#define SYSCON_I2SDIV_PSEL 0x00002000
140 +#define SYSCON_I2SDIV_ESEL 0x00004000
141 +#define SYSCON_I2SDIV_MENA 0x00008000
142 +#define SYSCON_I2SDIV_SDIV 0x00010000
143 +#define SYSCON_I2SDIV_LRDIV_MASK 0x00060000
144 +#define SYSCON_I2SDIV_LRDIV_SHIFT 17
145 +#define SYSCON_I2SDIV_SPOL 0x00080000
146 +#define SYSCON_I2SDIV_DROP 0x00100000
147 +#define SYSCON_I2SDIV_ORIDE 0x20000000
148 +#define SYSCON_I2SDIV_SLAVE 0x40000000
149 +#define SYSCON_I2SDIV_SENA 0x80000000
150 +
151 +#define SYSCON_I2SDIV_PDIV_OFF 0x00000000
152 +#define SYSCON_I2SDIV_PDIV_2 0x00000100
153 +#define SYSCON_I2SDIV_PDIV_25 0x00000200
154 +#define SYSCON_I2SDIV_PDIV_3 0x00000300
155 +
156 +#define SYSCON_I2SDIV_LRDIV_32 0x00000000
157 +#define SYSCON_I2SDIV_LRDIV_64 0x00020000
158 +#define SYSCON_I2SDIV_LRDIV_128 0x00040000
159 +
160 +//-----------------------------------------------------------------------------
161 +// VIDDIV Register Defines
162 +//-----------------------------------------------------------------------------
163 +#define SYSCON_VIDDIV_VDIV_MASK 0x0000007f
164 +#define SYSCON_VIDDIV_VDIV_SHIFT 0
165 +#define SYSCON_VIDDIV_PDIV_MASK 0x00000300
166 +#define SYSCON_VIDDIV_PDIV_SHIFT 8
167 +#define SYSCON_VIDDIV_PSEL 0x00002000
168 +#define SYSCON_VIDDIV_ESEL 0x00004000
169 +#define SYSCON_VIDDIV_VENA 0x00008000
170 +
171 +//-----------------------------------------------------------------------------
172 +// MIRDIV Register Defines
173 +//-----------------------------------------------------------------------------
174 +#define SYSCON_MIRDIV_MDIV_MASK 0x0000003f
175 +#define SYSCON_MIRDIV_MDIV_SHIFT 0
176 +#define SYSCON_MIRDIV_PDIV_MASK 0x00000300
177 +#define SYSCON_MIRDIV_PDIV_SHIFT 8
178 +#define SYSCON_MIRDIV_PSEL 0x00002000
179 +#define SYSCON_MIRDIV_ESEL 0x00004000
180 +#define SYSCON_MIRDIV_MENA 0x00008000
181 +
182 +/* 8082_0000 - 8082_ffff: I2S */
183 +#define I2S_OFFSET 0x020000
184 +#define I2S_BASE (EP93XX_APB_VIRT_BASE|I2S_OFFSET)
185 +#define I2S_PHYS_BASE (EP93XX_APB_PHYS_BASE + I2S_OFFSET)
186 +
187 +
188 +
189 +#define I2STxClkCfg (I2S_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */
190 +#define I2SRxClkCfg (I2S_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */
191 +#define I2SGlSts (I2S_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. */
192 +#define I2SGlCtrl (I2S_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */
193 +
194 +#define I2STX0Lft (I2S_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */
195 +#define I2STX0Rt (I2S_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */
196 +#define I2STX1Lft (I2S_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */
197 +#define I2STX1Rt (I2S_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */
198 +#define I2STX2Lft (I2S_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */
199 +#define I2STX2Rt (I2S_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */
200 +
201 +#define I2STXLinCtrlData (I2S_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */
202 +#define I2STXCtrl (I2S_BASE+0x2C) /* 8082.002C R/W TX Control register */
203 +#define I2STXWrdLen (I2S_BASE+0x30) /* 8082.0030 R/W TX Word Length */
204 +#define I2STX0En (I2S_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */
205 +#define I2STX1En (I2S_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */
206 +#define I2STX2En (I2S_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */
207 +
208 +#define I2SRX0Lft (I2S_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */
209 +#define I2SRX0Rt (I2S_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */
210 +#define I2SRX1Lft (I2S_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */
211 +#define I2SRX1Rt (I2S_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */
212 +#define I2SRX2Lft (I2S_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */
213 +#define I2SRX2Rt (I2S_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */
214 +
215 +#define I2SRXLinCtrlData (I2S_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */
216 +#define I2SRXCtrl (I2S_BASE+0x5C) /* 8082.005C R/W RX Control register */
217 +#define I2SRXWrdLen (I2S_BASE+0x60) /* 8082.0060 R/W RX Word Length */
218 +#define I2SRX0En (I2S_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */
219 +#define I2SRX1En (I2S_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */
220 +#define I2SRX2En (I2S_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */
221 +
222 +/* 8084_0000 - 8084_ffff: GPIO */
223 +#define GPIO_OFFSET 0x040000
224 +#define GPIO_BASE (EP93XX_APB_VIRT_BASE|GPIO_OFFSET)
225 +#define GPIO_PADR (GPIO_BASE+0x00)
226 +#define GPIO_PBDR (GPIO_BASE+0x04)
227 +#define GPIO_PCDR (GPIO_BASE+0x08)
228 +#define GPIO_PDDR (GPIO_BASE+0x0C)
229 +#define GPIO_PADDR (GPIO_BASE+0x10)
230 +#define GPIO_PBDDR (GPIO_BASE+0x14)
231 +#define GPIO_PCDDR (GPIO_BASE+0x18)
232 +#define GPIO_PDDDR (GPIO_BASE+0x1C)
233 +#define GPIO_PEDR (GPIO_BASE+0x20)
234 +#define GPIO_PEDDR (GPIO_BASE+0x24)
235 +// #define 0x8084.0028 Reserved
236 +// #define 0x8084.002C Reserved
237 +#define GPIO_PFDR (GPIO_BASE+0x30)
238 +#define GPIO_PFDDR (GPIO_BASE+0x34)
239 +#define GPIO_PGDR (GPIO_BASE+0x38)
240 +#define GPIO_PGDDR (GPIO_BASE+0x3C)
241 +#define GPIO_PHDR (GPIO_BASE+0x40)
242 +#define GPIO_PHDDR (GPIO_BASE+0x44)
243 +// #define 0x8084.0048 RAZ RAZ
244 +#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C)
245 +#define GPIO_FINTTYPE2 (GPIO_BASE+0x50)
246 +#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */
247 +#define GPIO_FINTEN (GPIO_BASE+0x58)
248 +#define GPIO_INTSTATUSF (GPIO_BASE+0x5C)
249 +#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60)
250 +#define GPIO_FDB (GPIO_BASE+0x64)
251 +#define GPIO_PAPINDR (GPIO_BASE+0x68)
252 +#define GPIO_PBPINDR (GPIO_BASE+0x6C)
253 +#define GPIO_PCPINDR (GPIO_BASE+0x70)
254 +#define GPIO_PDPINDR (GPIO_BASE+0x74)
255 +#define GPIO_PEPINDR (GPIO_BASE+0x78)
256 +#define GPIO_PFPINDR (GPIO_BASE+0x7C)
257 +#define GPIO_PGPINDR (GPIO_BASE+0x80)
258 +#define GPIO_PHPINDR (GPIO_BASE+0x84)
259 +#define GPIO_AINTTYPE1 (GPIO_BASE+0x90)
260 +#define GPIO_AINTTYPE2 (GPIO_BASE+0x94)
261 +#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */
262 +#define GPIO_AINTEN (GPIO_BASE+0x9C)
263 +#define GPIO_INTSTATUSA (GPIO_BASE+0xA0)
264 +#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4)
265 +#define GPIO_ADB (GPIO_BASE+0xA8)
266 +#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC)
267 +#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0)
268 +#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */
269 +#define GPIO_BINTEN (GPIO_BASE+0xB8)
270 +#define GPIO_INTSTATUSB (GPIO_BASE+0xBC)
271 +#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0)
272 +#define GPIO_BDB (GPIO_BASE+0xC4)
273 +#define GPIO_EEDRIVE (GPIO_BASE+0xC8)
274 +//#define Reserved (GPIO_BASE+0xCC)
275 +#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */
276 +#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */
277 +#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */
278 +#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */
279 +#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */
280 +#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */
281 +#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */
282 +#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */
283 +#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */
284 +#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */
285 +
286 +
287 +/* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */
288 +#define AC97_OFFSET 0x080000
289 +#define AC97_BASE (EP93XX_APB_VIRT_BASE|AC97_OFFSET)
290 +#define EP93XX_AC97_PHY_BASE (EP93XX_APB_PHYS_BASE|AC97_OFFSET)
291 +#define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */
292 +#define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */
293 +#define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */
294 +#define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */
295 +#define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */
296 +#define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */
297 +#define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */
298 + /* 8088.001C Reserved - RAZ */
299 +#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */
300 +#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */
301 +#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */
302 +#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */
303 +#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */
304 +#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */
305 +#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */
306 + /* 8088.003C Reserved - RAZ */
307 +#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */
308 +#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */
309 +#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */
310 +#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */
311 +#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */
312 +#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */
313 +#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */
314 + /* 8088.005C Reserved - RAZ */
315 +#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */
316 +#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */
317 +#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */
318 +#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */
319 +#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */
320 +#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */
321 +#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */
322 + /* 8088.003C Reserved - RAZ */
323 +#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */
324 +#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */
325 +#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */
326 +#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */
327 +#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */
328 +#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */
329 +#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */
330 + /* 8088.005C Reserved - RAZ */
331 +#define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */
332 +#define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */
333 +#define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */
334 +#define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */
335 +#define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */
336 +#define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */
337 +#define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */
338 + /* 8088.007C Reserved - RAZ */
339 +#define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */
340 +#define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */
341 +#define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */
342 +#define AC97RGIS (AC97_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/
343 +#define AC97GIS (AC97_BASE+0x90) /* 8088.0090 R Global interrupt status register */
344 +#define AC97IM (AC97_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */
345 +#define AC97EOI (AC97_BASE+0x98) /* 8088.0098 W Interrupt clear register */
346 +#define AC97GCR (AC97_BASE+0x9C) /* 8088.009C R/W Main Control register */
347 +#define AC97RESET (AC97_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */
348 +#define AC97SYNC (AC97_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */
349 +#define AC97GCIS (AC97_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register */
350 +
351 +
352 +/* 800B_0000 - 800B_FFFF: VIC 0 */
353 +#define VIC0_OFFSET 0x0B0000
354 +#define VIC0_BASE (EP93XX_AHB_VIRT_BASE|VIC0_OFFSET)
355 +#define VIC0 (VIC0_BASE+0x000)
356 +#define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */
357 +#define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */
358 +#define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */
359 +#define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */
360 +#define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */
361 +#define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */
362 +
363 +/* 8003_0000 - 8003_ffff: Raster */
364 +#define RASTER_OFFSET 0x030000
365 +#define RASTER_BASE (EP93XX_AHB_VIRT_BASE|RASTER_OFFSET)
366 +#define VLINESTOTAL (RASTER_BASE+0x00)
367 +#define VSYNCSTRTSTOP (RASTER_BASE+0x04)
368 +#define VACTIVESTRTSTOP (RASTER_BASE+0x08)
369 +#define VCLKSTRTSTOP (RASTER_BASE+0x0C)
370 +#define HCLKSTOTAL (RASTER_BASE+0x10)
371 +#define HSYNCSTRTSTOP (RASTER_BASE+0x14)
372 +#define HACTIVESTRTSTOP (RASTER_BASE+0x18)
373 +#define HCLKSTRTSTOP (RASTER_BASE+0x1C)
374 +#define BRIGHTNESS (RASTER_BASE+0x20)
375 +#define VIDEOATTRIBS (RASTER_BASE+0x24)
376 +#define VIDSCRNPAGE (RASTER_BASE+0x28)
377 +#define VIDSCRNHPG (RASTER_BASE+0x2C)
378 +#define SCRNLINES (RASTER_BASE+0x30)
379 +#define LINELENGTH (RASTER_BASE+0x34)
380 +#define VLINESTEP (RASTER_BASE+0x38)
381 +#define LINECARRY (RASTER_BASE+0x3C)
382 +#define BLINKRATE (RASTER_BASE+0x40)
383 +#define BLINKMASK (RASTER_BASE+0x44)
384 +#define BLINKPATTRN (RASTER_BASE+0x48)
385 +#define PATTRNMASK (RASTER_BASE+0x4C)
386 +#define BG_OFFSET (RASTER_BASE+0x50)
387 +#define PIXELMODE (RASTER_BASE+0x54)
388 +#define PARLLIFOUT (RASTER_BASE+0x58)
389 +#define PARLLIFIN (RASTER_BASE+0x5C)
390 +#define CURSOR_ADR_START (RASTER_BASE+0x60)
391 +#define CURSOR_ADR_RESET (RASTER_BASE+0x64)
392 +#define CURSORSIZE (RASTER_BASE+0x68)
393 +#define CURSORCOLOR1 (RASTER_BASE+0x6C)
394 +#define CURSORCOLOR2 (RASTER_BASE+0x70)
395 +#define CURSORXYLOC (RASTER_BASE+0x74)
396 +#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78)
397 +#define RASTER_SWLOCK (RASTER_BASE+0x7C)
398 +#define GS_LUT (RASTER_BASE+0x80)
399 +#define RASTER_TCR (RASTER_BASE+0x100)
400 +#define RASTER_TISRA (RASTER_BASE+0x104)
401 +#define RASTER_TISRB (RASTER_BASE+0x108)
402 +#define CURSOR_TISR (RASTER_BASE+0x10C)
403 +#define RASTER_TOCRA (RASTER_BASE+0x110)
404 +#define RASTER_TOCRB (RASTER_BASE+0x114)
405 +#define FIFO_TOCRA (RASTER_BASE+0x118)
406 +#define FIFO_TOCRB (RASTER_BASE+0x11C)
407 +#define BLINK_TISR (RASTER_BASE+0x120)
408 +#define DAC_TISRA (RASTER_BASE+0x124)
409 +#define DAC_TISRB (RASTER_BASE+0x128)
410 +#define SHIFT_TISR (RASTER_BASE+0x12C)
411 +#define DACMUX_TOCRA (RASTER_BASE+0x130)
412 +#define DACMUX_TOCRB (RASTER_BASE+0x134)
413 +#define PELMUX_TOCR (RASTER_BASE+0x138)
414 +#define VIDEO_TOCRA (RASTER_BASE+0x13C)
415 +#define VIDEO_TOCRB (RASTER_BASE+0x140)
416 +#define YCRCB_TOCR (RASTER_BASE+0x144)
417 +#define CURSOR_TOCR (RASTER_BASE+0x148)
418 +#define VIDEO_TOCRC (RASTER_BASE+0x14C)
419 +#define SHIFT_TOCR (RASTER_BASE+0x150)
420 +#define BLINK_TOCR (RASTER_BASE+0x154)
421 +#define RASTER_TCER (RASTER_BASE+0x180)
422 +#define SIGVAL (RASTER_BASE+0x200)
423 +#define SIGCTL (RASTER_BASE+0x204)
424 +#define VSIGSTRTSTOP (RASTER_BASE+0x208)
425 +#define HSIGSTRTSTOP (RASTER_BASE+0x20C)
426 +#define SIGCLR (RASTER_BASE+0x210)
427 +#define ACRATE (RASTER_BASE+0x214)
428 +#define LUTCONT (RASTER_BASE+0x218)
429 +#define VBLANKSTRTSTOP (RASTER_BASE+0x228)
430 +#define HBLANKSTRTSTOP (RASTER_BASE+0x22C)
431 +#define LUT (RASTER_BASE+0x400)
432 +#define CURSORBLINK1 (RASTER_BASE+0x21C)
433 +#define CURSORBLINK2 (RASTER_BASE+0x220)
434 +#define CURSORBLINK (RASTER_BASE+0x224)
435 +#define EOLOFFSET (RASTER_BASE+0x230)
436 +#define FIFOLEVEL (RASTER_BASE+0x234)
437 +#define GS_LUT2 (RASTER_BASE+0x280)
438 +#define GS_LUT3 (RASTER_BASE+0x300)
439 +#define COLOR_LUT (RASTER_BASE+0x400)
440 +
441 +/* 8004_0000 - 8004_ffff: Graphics */
442 +#define GRAPHICS_OFFSET 0x040000
443 +#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE|GRAPHICS_OFFSET)
444 +#define SRCPIXELSTRT (GRAPHICS_BASE+0x00)
445 +#define DESTPIXELSTRT (GRAPHICS_BASE+0x04)
446 +#define BLKSRCSTRT (GRAPHICS_BASE+0x08)
447 +#define BLKDSTSTRT (GRAPHICS_BASE+0x0C)
448 +#define BLKSRCWIDTH (GRAPHICS_BASE+0x10)
449 +#define SRCLINELENGTH (GRAPHICS_BASE+0x14)
450 +#define BLKDESTWIDTH (GRAPHICS_BASE+0x18)
451 +#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C)
452 +#define DESTLINELENGTH (GRAPHICS_BASE+0x20)
453 +#define BLOCKCTRL (GRAPHICS_BASE+0x24)
454 +#define TRANSPATTRN (GRAPHICS_BASE+0x28)
455 +#define BLOCKMASK (GRAPHICS_BASE+0x2C)
456 +#define BACKGROUND (GRAPHICS_BASE+0x30)
457 +#define LINEINC (GRAPHICS_BASE+0x34)
458 +#define LINEINIT (GRAPHICS_BASE+0x38)
459 +#define LINEPATTRN (GRAPHICS_BASE+0x3C)
460 +
461 +#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000)
462 +#define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000)
463 +
464 +#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000)
465 +#define EP93XX_GRAPHICS_ACCEL_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00040000)
466 +
467 +#ifndef __ASSEMBLY__
468 +
469 +#define SysconSetLocked(registername,value) \
470 + { \
471 + local_irq_disable(); \
472 + outl( 0xAA, EP93XX_SYSCON_SWLOCK); \
473 + outl( value, registername); \
474 + local_irq_enable(); \
475 + }
476 +
477 +#endif /* Not __ASSEMBLY__ */
478 +
479 #endif
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