projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Addd kernel modules for NTFS (#2181)
[openwrt.git] / target / linux / avr32-2.6 / patches / 100-git_sync.patch
1 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atngw100/Kconfig linux-avr32.git/arch/avr32/boards/atngw100/Kconfig
2 --- linux-2.6.22.1/arch/avr32/boards/atngw100/Kconfig 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-avr32.git/arch/avr32/boards/atngw100/Kconfig 2007-07-13 11:24:16.000000000 +0200
4 @@ -0,0 +1,12 @@
5 +# NGW100 customization
6 +
7 +config BOARD_ATNGW100_I2C_GPIO
8 + bool "Use GPIO for i2c instead of built-in TWI module"
9 + help
10 + The driver for the built-in TWI module has been plagued by
11 + various problems, while the i2c-gpio driver is based on the
12 + trusty old i2c-algo-bit bitbanging engine, making it work
13 + on pretty much any setup.
14 +
15 + Choose 'Y' here if you're having i2c-related problems and
16 + want to rule out the i2c bus driver.
17 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atngw100/setup.c linux-avr32.git/arch/avr32/boards/atngw100/setup.c
18 --- linux-2.6.22.1/arch/avr32/boards/atngw100/setup.c 2007-07-10 20:56:30.000000000 +0200
19 +++ linux-avr32.git/arch/avr32/boards/atngw100/setup.c 2007-07-13 11:24:16.000000000 +0200
20 @@ -9,10 +9,12 @@
21 */
22 #include <linux/clk.h>
23 #include <linux/etherdevice.h>
24 +#include <linux/i2c-gpio.h>
25 #include <linux/init.h>
26 #include <linux/linkage.h>
27 #include <linux/platform_device.h>
28 #include <linux/types.h>
29 +#include <linux/leds.h>
30 #include <linux/spi/spi.h>
31
32 #include <asm/io.h>
33 @@ -21,6 +23,7 @@
34 #include <asm/arch/at32ap7000.h>
35 #include <asm/arch/board.h>
36 #include <asm/arch/init.h>
37 +#include <asm/arch/portmux.h>
38
39 /* Initialized by bootloader-specific startup code. */
40 struct tag *bootloader_tags __initdata;
41 @@ -39,6 +42,11 @@
42 },
43 };
44
45 +static struct mci_platform_data __initdata mci0_data = {
46 + .detect_pin = GPIO_PIN_PC(25),
47 + .wp_pin = GPIO_PIN_PE(0),
48 +};
49 +
50 /*
51 * The next two functions should go away as the boot loader is
52 * supposed to initialize the macb address registers with a valid
53 @@ -100,8 +108,46 @@
54 at32_setup_serial_console(0);
55 }
56
57 +static const struct gpio_led ngw_leds[] = {
58 + { .name = "sys", .gpio = GPIO_PIN_PA(16), .active_low = 1,
59 + .default_trigger = "heartbeat",
60 + },
61 + { .name = "a", .gpio = GPIO_PIN_PA(19), .active_low = 1, },
62 + { .name = "b", .gpio = GPIO_PIN_PE(19), .active_low = 1, },
63 +};
64 +
65 +static const struct gpio_led_platform_data ngw_led_data = {
66 + .num_leds = ARRAY_SIZE(ngw_leds),
67 + .leds = (void *) ngw_leds,
68 +};
69 +
70 +static struct platform_device ngw_gpio_leds = {
71 + .name = "leds-gpio",
72 + .id = -1,
73 + .dev = {
74 + .platform_data = (void *) &ngw_led_data,
75 + }
76 +};
77 +
78 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
79 +static struct i2c_gpio_platform_data i2c_gpio_data = {
80 + .sda_pin = GPIO_PIN_PA(6),
81 + .scl_pin = GPIO_PIN_PA(7),
82 +};
83 +
84 +static struct platform_device i2c_gpio_device = {
85 + .name = "i2c-gpio",
86 + .id = 0,
87 + .dev = {
88 + .platform_data = &i2c_gpio_data,
89 + },
90 +};
91 +#endif
92 +
93 static int __init atngw100_init(void)
94 {
95 + unsigned i;
96 +
97 /*
98 * ATNGW100 uses 16-bit SDRAM interface, so we don't need to
99 * reserve any pins for it.
100 @@ -115,6 +161,22 @@
101 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
102
103 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
104 + at32_add_device_mci(0, &mci0_data);
105 + at32_add_device_usba(0, NULL);
106 +
107 + for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
108 + at32_select_gpio(ngw_leds[i].gpio,
109 + AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
110 + }
111 + platform_device_register(&ngw_gpio_leds);
112 +
113 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
114 + at32_select_gpio(i2c_gpio_data.sda_pin, 0);
115 + at32_select_gpio(i2c_gpio_data.scl_pin, 0);
116 + platform_device_register(&i2c_gpio_device);
117 +#else
118 + at32_add_device_twi(0);
119 +#endif
120
121 return 0;
122 }
123 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atstk1000/atstk1002.c linux-avr32.git/arch/avr32/boards/atstk1000/atstk1002.c
124 --- linux-2.6.22.1/arch/avr32/boards/atstk1000/atstk1002.c 2007-07-10 20:56:30.000000000 +0200
125 +++ linux-avr32.git/arch/avr32/boards/atstk1000/atstk1002.c 2007-07-12 13:59:49.000000000 +0200
126 @@ -11,6 +11,7 @@
127 #include <linux/etherdevice.h>
128 #include <linux/init.h>
129 #include <linux/kernel.h>
130 +#include <linux/leds.h>
131 #include <linux/platform_device.h>
132 #include <linux/string.h>
133 #include <linux/types.h>
134 @@ -27,7 +28,6 @@
135
136 #include "atstk1000.h"
137
138 -#define SW2_DEFAULT /* MMCI and UART_A available */
139
140 struct eth_addr {
141 u8 addr[6];
142 @@ -36,6 +36,7 @@
143 static struct eth_addr __initdata hw_addr[2];
144 static struct eth_platform_data __initdata eth_data[2];
145
146 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
147 static struct spi_board_info spi0_board_info[] __initdata = {
148 {
149 /* QVGA display */
150 @@ -45,6 +46,18 @@
151 .mode = SPI_MODE_3,
152 },
153 };
154 +#endif
155 +
156 +#ifdef CONFIG_BOARD_ATSTK1002_SPI1
157 +static struct spi_board_info spi1_board_info[] __initdata = { {
158 + /* patch in custom entries here */
159 +} };
160 +#endif
161 +
162 +static struct mci_platform_data __initdata mci0_data = {
163 + .detect_pin = GPIO_PIN_NONE,
164 + .wp_pin = GPIO_PIN_NONE,
165 +};
166
167 /*
168 * The next two functions should go away as the boot loader is
169 @@ -101,12 +114,71 @@
170 clk_put(pclk);
171 }
172
173 -void __init setup_board(void)
174 +#ifdef CONFIG_BOARD_ATSTK1002_J2_LED
175 +
176 +static struct gpio_led stk_j2_led[] = {
177 +#ifdef CONFIG_BOARD_ATSTK1002_J2_LED8
178 +#define LEDSTRING "J2 jumpered to LED8"
179 + { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
180 + { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
181 + { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
182 + { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
183 + { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
184 + { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
185 + { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
186 + { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
187 + .default_trigger = "heartbeat", },
188 +#else /* RGB */
189 +#define LEDSTRING "J2 jumpered to RGB LEDs"
190 + { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
191 + { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
192 + { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
193 +
194 + { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
195 + .default_trigger = "heartbeat", },
196 + { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
197 + { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
198 + .default_trigger = "heartbeat", },
199 + /* PB16, PB30 unused */
200 +#endif
201 +};
202 +
203 +static struct gpio_led_platform_data stk_j2_led_data = {
204 + .num_leds = ARRAY_SIZE(stk_j2_led),
205 + .leds = stk_j2_led,
206 +};
207 +
208 +static struct platform_device stk_j2_led_dev = {
209 + .name = "leds-gpio",
210 + .id = 2, /* gpio block J2 */
211 + .dev = {
212 + .platform_data = &stk_j2_led_data,
213 + },
214 +};
215 +
216 +static void setup_j2_leds(void)
217 {
218 -#ifdef SW2_DEFAULT
219 - at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
220 + unsigned i;
221 +
222 + for (i = 0; i < ARRAY_SIZE(stk_j2_led); i++)
223 + at32_select_gpio(stk_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
224 +
225 + printk("STK1002: " LEDSTRING "\n");
226 + platform_device_register(&stk_j2_led_dev);
227 +}
228 +
229 #else
230 +static void setup_j2_leds(void)
231 +{
232 +}
233 +#endif
234 +
235 +void __init setup_board(void)
236 +{
237 +#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
238 at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
239 +#else
240 + at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
241 #endif
242 /* USART 2/unused: expansion connector */
243 at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
244 @@ -140,18 +212,40 @@
245
246 at32_add_system_devices();
247
248 -#ifdef SW2_DEFAULT
249 - at32_add_device_usart(0);
250 -#else
251 +#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
252 at32_add_device_usart(1);
253 +#else
254 + at32_add_device_usart(0);
255 #endif
256 at32_add_device_usart(2);
257
258 +#ifndef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
259 set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
260 -
261 - at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
262 +#endif
263 +#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
264 + set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
265 +#else
266 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
267 fbmem_start, fbmem_size);
268 +#endif
269 +
270 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
271 + at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
272 +#endif
273 +#ifdef CONFIG_BOARD_ATSTK1002_SPI1
274 + at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
275 +#endif
276 + at32_add_device_twi(0);
277 +#ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
278 + at32_add_device_mci(0, &mci0_data);
279 +#endif
280 + at32_add_device_usba(0, NULL);
281 + at32_add_device_abdac(0);
282 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
283 + at32_add_device_ssc(0, ATMEL_SSC_TX);
284 +#endif
285 +
286 + setup_j2_leds();
287
288 return 0;
289 }
290 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atstk1000/Kconfig linux-avr32.git/arch/avr32/boards/atstk1000/Kconfig
291 --- linux-2.6.22.1/arch/avr32/boards/atstk1000/Kconfig 1970-01-01 01:00:00.000000000 +0100
292 +++ linux-avr32.git/arch/avr32/boards/atstk1000/Kconfig 2007-07-12 13:59:49.000000000 +0200
293 @@ -0,0 +1,79 @@
294 +# STK1000 customization
295 +
296 +if BOARD_ATSTK1002
297 +
298 +config BOARD_ATSTK1002_CUSTOM
299 + bool "Non-default STK-1002 jumper settings"
300 + help
301 + You will normally leave the jumpers on the CPU card at their
302 + default settings. If you need to use certain peripherals,
303 + you will need to change some of those jumpers.
304 +
305 +if BOARD_ATSTK1002_CUSTOM
306 +
307 +config BOARD_ATSTK1002_SW1_CUSTOM
308 + bool "SW1: use SSC1 (not SPI0)"
309 + help
310 + This also prevents using the external DAC as an audio interface,
311 + and means you can't initialize the on-board QVGA display.
312 +
313 +config BOARD_ATSTK1002_SW2_CUSTOM
314 + bool "SW2: use IRDA or TIMER0 (not UART-A, MMC/SD, and PS2-A)"
315 + help
316 + If you change this you'll want an updated boot loader putting
317 + the console on UART-C not UART-A.
318 +
319 +config BOARD_ATSTK1002_SW3_CUSTOM
320 + bool "SW3: use TIMER1 (not SSC0 and GCLK)"
321 + help
322 + This also prevents using the external DAC as an audio interface.
323 +
324 +config BOARD_ATSTK1002_SW4_CUSTOM
325 + bool "SW4: use ISI/Camera (not GPIOs, SPI1, and PS2-B)"
326 + help
327 + To use the camera interface you'll need a custom card (on the
328 + PCI-format connector) connect a video sensor.
329 +
330 +config BOARD_ATSTK1002_SW5_CUSTOM
331 + bool "SW5: use MACB1 (not LCDC)"
332 +
333 +config BOARD_ATSTK1002_SW6_CUSTOM
334 + bool "SW6: more GPIOs (not MACB0)"
335 +
336 +endif # custom
337 +
338 +config BOARD_ATSTK1002_SPI1
339 + bool "Configure SPI1 controller"
340 + depends on !BOARD_ATSTK1002_SW4_CUSTOM
341 + help
342 + All the signals for the second SPI controller are available on
343 + GPIO lines and accessed through the J1 jumper block. Say "y"
344 + here to configure that SPI controller.
345 +
346 +config BOARD_ATSTK1002_J2_LED
347 + bool
348 + default BOARD_ATSTK1002_J2_LED8 || BOARD_ATSTK1002_J2_RGB
349 +
350 +choice
351 + prompt "LEDs connected to J2:"
352 + depends on LEDS_GPIO && !BOARD_ATSTK1002_SW4_CUSTOM
353 + optional
354 + help
355 + Select this if you have jumpered the J2 jumper block to the
356 + LED0..LED7 amber leds, or to the RGB leds, using a ten-pin
357 + IDC cable. A default "heartbeat" trigger is provided, but
358 + you can of course override this.
359 +
360 +config BOARD_ATSTK1002_J2_LED8
361 + bool "LED0..LED7"
362 + help
363 + Select this if J2 is jumpered to LED0..LED7 amber leds.
364 +
365 +config BOARD_ATSTK1002_J2_RGB
366 + bool "RGB leds"
367 + help
368 + Select this if J2 is jumpered to the RGB leds.
369 +
370 +endchoice
371 +
372 +endif # stk 1002
373 diff -x .git -Nur linux-2.6.22.1/arch/avr32/configs/atngw100_defconfig linux-avr32.git/arch/avr32/configs/atngw100_defconfig
374 --- linux-2.6.22.1/arch/avr32/configs/atngw100_defconfig 2007-07-10 20:56:30.000000000 +0200
375 +++ linux-avr32.git/arch/avr32/configs/atngw100_defconfig 2007-07-13 11:24:16.000000000 +0200
376 @@ -1,7 +1,7 @@
377 #
378 # Automatically generated make config: don't edit
379 -# Linux kernel version: 2.6.22-rc5
380 -# Sat Jun 23 15:40:05 2007
381 +# Linux kernel version: 2.6.22.atmel.1
382 +# Thu Jul 12 17:49:20 2007
383 #
384 CONFIG_AVR32=y
385 CONFIG_GENERIC_GPIO=y
386 @@ -114,6 +114,7 @@
387 CONFIG_CPU_AT32AP7000=y
388 # CONFIG_BOARD_ATSTK1000 is not set
389 CONFIG_BOARD_ATNGW100=y
390 +# CONFIG_BOARD_ATNGW100_I2C_GPIO is not set
391 CONFIG_LOADER_U_BOOT=y
392
393 #
394 @@ -122,6 +123,7 @@
395 # CONFIG_AP7000_32_BIT_SMC is not set
396 CONFIG_AP7000_16_BIT_SMC=y
397 # CONFIG_AP7000_8_BIT_SMC is not set
398 +CONFIG_GPIO_DEV=y
399 CONFIG_LOAD_ADDRESS=0x10000000
400 CONFIG_ENTRY_ADDRESS=0x90000000
401 CONFIG_PHYS_OFFSET=0x10000000
402 @@ -145,6 +147,7 @@
403 # CONFIG_RESOURCES_64BIT is not set
404 CONFIG_ZONE_DMA_FLAG=0
405 # CONFIG_OWNERSHIP_TRACE is not set
406 +CONFIG_DW_DMAC=y
407 # CONFIG_HZ_100 is not set
408 CONFIG_HZ_250=y
409 # CONFIG_HZ_300 is not set
410 @@ -153,6 +156,27 @@
411 CONFIG_CMDLINE=""
412
413 #
414 +# Power managment options
415 +#
416 +
417 +#
418 +# CPU Frequency scaling
419 +#
420 +CONFIG_CPU_FREQ=y
421 +CONFIG_CPU_FREQ_TABLE=y
422 +# CONFIG_CPU_FREQ_DEBUG is not set
423 +CONFIG_CPU_FREQ_STAT=m
424 +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
425 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
426 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
427 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
428 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
429 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
430 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
431 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
432 +CONFIG_CPU_FREQ_AT32AP=y
433 +
434 +#
435 # Bus options
436 #
437 # CONFIG_ARCH_SUPPORTS_MSI is not set
438 @@ -187,13 +211,8 @@
439 # CONFIG_NET_KEY_MIGRATE is not set
440 CONFIG_INET=y
441 CONFIG_IP_MULTICAST=y
442 -CONFIG_IP_ADVANCED_ROUTER=y
443 -CONFIG_ASK_IP_FIB_HASH=y
444 -# CONFIG_IP_FIB_TRIE is not set
445 +# CONFIG_IP_ADVANCED_ROUTER is not set
446 CONFIG_IP_FIB_HASH=y
447 -# CONFIG_IP_MULTIPLE_TABLES is not set
448 -# CONFIG_IP_ROUTE_MULTIPATH is not set
449 -# CONFIG_IP_ROUTE_VERBOSE is not set
450 CONFIG_IP_PNP=y
451 CONFIG_IP_PNP_DHCP=y
452 # CONFIG_IP_PNP_BOOTP is not set
453 @@ -240,6 +259,7 @@
454 # CONFIG_NETWORK_SECMARK is not set
455 CONFIG_NETFILTER=y
456 # CONFIG_NETFILTER_DEBUG is not set
457 +CONFIG_BRIDGE_NETFILTER=y
458
459 #
460 # Core Netfilter Configuration
461 @@ -284,6 +304,7 @@
462 CONFIG_NETFILTER_XT_MATCH_MARK=m
463 CONFIG_NETFILTER_XT_MATCH_POLICY=m
464 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
465 +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
466 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
467 CONFIG_NETFILTER_XT_MATCH_QUOTA=m
468 CONFIG_NETFILTER_XT_MATCH_REALM=m
469 @@ -359,13 +380,19 @@
470 CONFIG_IP6_NF_MANGLE=m
471 CONFIG_IP6_NF_TARGET_HL=m
472 CONFIG_IP6_NF_RAW=m
473 +
474 +#
475 +# Bridge: Netfilter Configuration
476 +#
477 +# CONFIG_BRIDGE_NF_EBTABLES is not set
478 # CONFIG_IP_DCCP is not set
479 # CONFIG_IP_SCTP is not set
480 # CONFIG_TIPC is not set
481 # CONFIG_ATM is not set
482 -# CONFIG_BRIDGE is not set
483 +CONFIG_BRIDGE=m
484 CONFIG_VLAN_8021Q=m
485 # CONFIG_DECNET is not set
486 +CONFIG_LLC=m
487 # CONFIG_LLC2 is not set
488 # CONFIG_IPX is not set
489 # CONFIG_ATALK is not set
490 @@ -521,7 +548,6 @@
491 #
492 # Misc devices
493 #
494 -# CONFIG_BLINK is not set
495 # CONFIG_IDE is not set
496
497 #
498 @@ -545,13 +571,26 @@
499 # CONFIG_BONDING is not set
500 # CONFIG_EQUALIZER is not set
501 CONFIG_TUN=m
502 -# CONFIG_PHYLIB is not set
503 +CONFIG_PHYLIB=y
504 +
505 +#
506 +# MII PHY device drivers
507 +#
508 +# CONFIG_MARVELL_PHY is not set
509 +# CONFIG_DAVICOM_PHY is not set
510 +# CONFIG_QSEMI_PHY is not set
511 +# CONFIG_LXT_PHY is not set
512 +# CONFIG_CICADA_PHY is not set
513 +# CONFIG_VITESSE_PHY is not set
514 +# CONFIG_SMSC_PHY is not set
515 +# CONFIG_BROADCOM_PHY is not set
516 +# CONFIG_FIXED_PHY is not set
517
518 #
519 # Ethernet (10 or 100Mbit)
520 #
521 CONFIG_NET_ETHERNET=y
522 -CONFIG_MII=y
523 +# CONFIG_MII is not set
524 CONFIG_MACB=y
525 # CONFIG_NETDEV_1000 is not set
526 # CONFIG_NETDEV_10000 is not set
527 @@ -625,7 +664,15 @@
528 # IPMI
529 #
530 # CONFIG_IPMI_HANDLER is not set
531 -# CONFIG_WATCHDOG is not set
532 +CONFIG_WATCHDOG=y
533 +# CONFIG_WATCHDOG_NOWAYOUT is not set
534 +
535 +#
536 +# Watchdog Device Drivers
537 +#
538 +# CONFIG_SOFT_WATCHDOG is not set
539 +CONFIG_AT32AP700X_WDT=y
540 +CONFIG_AT32AP700X_WDT_TIMEOUT=2
541 # CONFIG_HW_RANDOM is not set
542 # CONFIG_RTC is not set
543 # CONFIG_GEN_RTC is not set
544 @@ -636,7 +683,42 @@
545 # TPM devices
546 #
547 # CONFIG_TCG_TPM is not set
548 -# CONFIG_I2C is not set
549 +CONFIG_I2C=m
550 +CONFIG_I2C_BOARDINFO=y
551 +CONFIG_I2C_CHARDEV=m
552 +
553 +#
554 +# I2C Algorithms
555 +#
556 +CONFIG_I2C_ALGOBIT=m
557 +# CONFIG_I2C_ALGOPCF is not set
558 +# CONFIG_I2C_ALGOPCA is not set
559 +
560 +#
561 +# I2C Hardware Bus support
562 +#
563 +CONFIG_I2C_ATMELTWI=m
564 +CONFIG_I2C_ATMELTWI_BAUDRATE=100000
565 +CONFIG_I2C_GPIO=m
566 +# CONFIG_I2C_OCORES is not set
567 +# CONFIG_I2C_PARPORT_LIGHT is not set
568 +# CONFIG_I2C_SIMTEC is not set
569 +# CONFIG_I2C_STUB is not set
570 +
571 +#
572 +# Miscellaneous I2C Chip support
573 +#
574 +# CONFIG_SENSORS_DS1337 is not set
575 +# CONFIG_SENSORS_DS1374 is not set
576 +# CONFIG_SENSORS_EEPROM is not set
577 +# CONFIG_SENSORS_PCF8574 is not set
578 +# CONFIG_SENSORS_PCA9539 is not set
579 +# CONFIG_SENSORS_PCF8591 is not set
580 +# CONFIG_SENSORS_MAX6875 is not set
581 +# CONFIG_I2C_DEBUG_CORE is not set
582 +# CONFIG_I2C_DEBUG_ALGO is not set
583 +# CONFIG_I2C_DEBUG_BUS is not set
584 +# CONFIG_I2C_DEBUG_CHIP is not set
585
586 #
587 # SPI support
588 @@ -655,7 +737,7 @@
589 # SPI Protocol Masters
590 #
591 # CONFIG_SPI_AT25 is not set
592 -# CONFIG_SPI_SPIDEV is not set
593 +CONFIG_SPI_SPIDEV=m
594
595 #
596 # Dallas's 1-wire bus
597 @@ -706,21 +788,59 @@
598 #
599 # USB Gadget Support
600 #
601 -# CONFIG_USB_GADGET is not set
602 -# CONFIG_MMC is not set
603 +CONFIG_USB_GADGET=y
604 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
605 +CONFIG_USB_GADGET_SELECTED=y
606 +# CONFIG_USB_GADGET_FSL_USB2 is not set
607 +# CONFIG_USB_GADGET_NET2280 is not set
608 +# CONFIG_USB_GADGET_PXA2XX is not set
609 +# CONFIG_USB_GADGET_GOKU is not set
610 +# CONFIG_USB_GADGET_LH7A40X is not set
611 +CONFIG_USB_GADGET_ATMEL_USBA=y
612 +CONFIG_USB_ATMEL_USBA=y
613 +# CONFIG_USB_GADGET_OMAP is not set
614 +# CONFIG_USB_GADGET_AT91 is not set
615 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
616 +CONFIG_USB_GADGET_DUALSPEED=y
617 +CONFIG_USB_ZERO=m
618 +CONFIG_USB_ETH=m
619 +CONFIG_USB_ETH_RNDIS=y
620 +CONFIG_USB_GADGETFS=m
621 +CONFIG_USB_FILE_STORAGE=m
622 +# CONFIG_USB_FILE_STORAGE_TEST is not set
623 +CONFIG_USB_G_SERIAL=m
624 +# CONFIG_USB_MIDI_GADGET is not set
625 +CONFIG_MMC=y
626 +# CONFIG_MMC_DEBUG is not set
627 +# CONFIG_MMC_UNSAFE_RESUME is not set
628 +
629 +#
630 +# MMC/SD Card Drivers
631 +#
632 +CONFIG_MMC_BLOCK=y
633 +
634 +#
635 +# MMC/SD Host Controller Drivers
636 +#
637 +CONFIG_MMC_ATMELMCI=y
638
639 #
640 # LED devices
641 #
642 -# CONFIG_NEW_LEDS is not set
643 +CONFIG_NEW_LEDS=y
644 +CONFIG_LEDS_CLASS=y
645
646 #
647 # LED drivers
648 #
649 +CONFIG_LEDS_GPIO=y
650
651 #
652 # LED Triggers
653 #
654 +CONFIG_LEDS_TRIGGERS=y
655 +CONFIG_LEDS_TRIGGER_TIMER=y
656 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
657
658 #
659 # InfiniBand support
660 @@ -733,7 +853,51 @@
661 #
662 # Real Time Clock
663 #
664 -# CONFIG_RTC_CLASS is not set
665 +CONFIG_RTC_LIB=y
666 +CONFIG_RTC_CLASS=y
667 +CONFIG_RTC_HCTOSYS=y
668 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
669 +# CONFIG_RTC_DEBUG is not set
670 +
671 +#
672 +# RTC interfaces
673 +#
674 +CONFIG_RTC_INTF_SYSFS=y
675 +CONFIG_RTC_INTF_PROC=y
676 +CONFIG_RTC_INTF_DEV=y
677 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
678 +# CONFIG_RTC_DRV_TEST is not set
679 +
680 +#
681 +# I2C RTC drivers
682 +#
683 +# CONFIG_RTC_DRV_DS1307 is not set
684 +# CONFIG_RTC_DRV_DS1672 is not set
685 +# CONFIG_RTC_DRV_MAX6900 is not set
686 +# CONFIG_RTC_DRV_RS5C372 is not set
687 +# CONFIG_RTC_DRV_ISL1208 is not set
688 +# CONFIG_RTC_DRV_X1205 is not set
689 +# CONFIG_RTC_DRV_PCF8563 is not set
690 +# CONFIG_RTC_DRV_PCF8583 is not set
691 +
692 +#
693 +# SPI RTC drivers
694 +#
695 +# CONFIG_RTC_DRV_RS5C348 is not set
696 +# CONFIG_RTC_DRV_MAX6902 is not set
697 +
698 +#
699 +# Platform RTC drivers
700 +#
701 +# CONFIG_RTC_DRV_DS1553 is not set
702 +# CONFIG_RTC_DRV_DS1742 is not set
703 +# CONFIG_RTC_DRV_M48T86 is not set
704 +# CONFIG_RTC_DRV_V3020 is not set
705 +
706 +#
707 +# on-CPU RTC drivers
708 +#
709 +CONFIG_RTC_DRV_AT32AP700X=y
710
711 #
712 # DMA Engine support
713 @@ -767,7 +931,8 @@
714 # CONFIG_OCFS2_FS is not set
715 # CONFIG_MINIX_FS is not set
716 # CONFIG_ROMFS_FS is not set
717 -# CONFIG_INOTIFY is not set
718 +CONFIG_INOTIFY=y
719 +CONFIG_INOTIFY_USER=y
720 # CONFIG_QUOTA is not set
721 # CONFIG_DNOTIFY is not set
722 # CONFIG_AUTOFS_FS is not set
723 @@ -922,7 +1087,7 @@
724 CONFIG_ENABLE_MUST_CHECK=y
725 CONFIG_MAGIC_SYSRQ=y
726 # CONFIG_UNUSED_SYMBOLS is not set
727 -# CONFIG_DEBUG_FS is not set
728 +CONFIG_DEBUG_FS=y
729 # CONFIG_HEADERS_CHECK is not set
730 CONFIG_DEBUG_KERNEL=y
731 # CONFIG_DEBUG_SHIRQ is not set
732 diff -x .git -Nur linux-2.6.22.1/arch/avr32/configs/atstk1002_defconfig linux-avr32.git/arch/avr32/configs/atstk1002_defconfig
733 --- linux-2.6.22.1/arch/avr32/configs/atstk1002_defconfig 2007-07-10 20:56:30.000000000 +0200
734 +++ linux-avr32.git/arch/avr32/configs/atstk1002_defconfig 2007-07-13 11:24:16.000000000 +0200
735 @@ -1,7 +1,7 @@
736 #
737 # Automatically generated make config: don't edit
738 -# Linux kernel version: 2.6.22-rc5
739 -# Sat Jun 23 15:32:08 2007
740 +# Linux kernel version: 2.6.22.atmel.1
741 +# Thu Jul 12 19:34:17 2007
742 #
743 CONFIG_AVR32=y
744 CONFIG_GENERIC_GPIO=y
745 @@ -80,10 +80,10 @@
746 #
747 CONFIG_MODULES=y
748 CONFIG_MODULE_UNLOAD=y
749 -# CONFIG_MODULE_FORCE_UNLOAD is not set
750 +CONFIG_MODULE_FORCE_UNLOAD=y
751 # CONFIG_MODVERSIONS is not set
752 # CONFIG_MODULE_SRCVERSION_ALL is not set
753 -# CONFIG_KMOD is not set
754 +CONFIG_KMOD=y
755
756 #
757 # Block layer
758 @@ -99,12 +99,12 @@
759 CONFIG_IOSCHED_NOOP=y
760 # CONFIG_IOSCHED_AS is not set
761 # CONFIG_IOSCHED_DEADLINE is not set
762 -# CONFIG_IOSCHED_CFQ is not set
763 +CONFIG_IOSCHED_CFQ=y
764 # CONFIG_DEFAULT_AS is not set
765 # CONFIG_DEFAULT_DEADLINE is not set
766 -# CONFIG_DEFAULT_CFQ is not set
767 -CONFIG_DEFAULT_NOOP=y
768 -CONFIG_DEFAULT_IOSCHED="noop"
769 +CONFIG_DEFAULT_CFQ=y
770 +# CONFIG_DEFAULT_NOOP is not set
771 +CONFIG_DEFAULT_IOSCHED="cfq"
772
773 #
774 # System Type and features
775 @@ -117,6 +117,11 @@
776 CONFIG_BOARD_ATSTK1002=y
777 CONFIG_BOARD_ATSTK1000=y
778 # CONFIG_BOARD_ATNGW100 is not set
779 +# CONFIG_BOARD_ATSTK1002_CUSTOM is not set
780 +# CONFIG_BOARD_ATSTK1002_SPI1 is not set
781 +# CONFIG_BOARD_ATSTK1002_J2_LED is not set
782 +# CONFIG_BOARD_ATSTK1002_J2_LED8 is not set
783 +# CONFIG_BOARD_ATSTK1002_J2_RGB is not set
784 CONFIG_LOADER_U_BOOT=y
785
786 #
787 @@ -125,6 +130,7 @@
788 # CONFIG_AP7000_32_BIT_SMC is not set
789 CONFIG_AP7000_16_BIT_SMC=y
790 # CONFIG_AP7000_8_BIT_SMC is not set
791 +CONFIG_GPIO_DEV=y
792 CONFIG_LOAD_ADDRESS=0x10000000
793 CONFIG_ENTRY_ADDRESS=0x90000000
794 CONFIG_PHYS_OFFSET=0x10000000
795 @@ -148,6 +154,7 @@
796 # CONFIG_RESOURCES_64BIT is not set
797 CONFIG_ZONE_DMA_FLAG=0
798 # CONFIG_OWNERSHIP_TRACE is not set
799 +CONFIG_DW_DMAC=y
800 # CONFIG_HZ_100 is not set
801 CONFIG_HZ_250=y
802 # CONFIG_HZ_300 is not set
803 @@ -156,6 +163,27 @@
804 CONFIG_CMDLINE=""
805
806 #
807 +# Power managment options
808 +#
809 +
810 +#
811 +# CPU Frequency scaling
812 +#
813 +CONFIG_CPU_FREQ=y
814 +CONFIG_CPU_FREQ_TABLE=y
815 +# CONFIG_CPU_FREQ_DEBUG is not set
816 +CONFIG_CPU_FREQ_STAT=m
817 +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
818 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
819 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
820 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
821 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
822 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
823 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
824 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
825 +CONFIG_CPU_FREQ_AT32AP=y
826 +
827 +#
828 # Bus options
829 #
830 # CONFIG_ARCH_SUPPORTS_MSI is not set
831 @@ -327,6 +355,8 @@
832 #
833 # Self-contained MTD device drivers
834 #
835 +CONFIG_MTD_DATAFLASH=m
836 +# CONFIG_MTD_M25P80 is not set
837 # CONFIG_MTD_SLRAM is not set
838 # CONFIG_MTD_PHRAM is not set
839 # CONFIG_MTD_MTDRAM is not set
840 @@ -373,7 +403,6 @@
841 #
842 # Misc devices
843 #
844 -# CONFIG_BLINK is not set
845 # CONFIG_IDE is not set
846
847 #
848 @@ -397,13 +426,26 @@
849 # CONFIG_BONDING is not set
850 # CONFIG_EQUALIZER is not set
851 CONFIG_TUN=m
852 -# CONFIG_PHYLIB is not set
853 +CONFIG_PHYLIB=y
854 +
855 +#
856 +# MII PHY device drivers
857 +#
858 +# CONFIG_MARVELL_PHY is not set
859 +# CONFIG_DAVICOM_PHY is not set
860 +# CONFIG_QSEMI_PHY is not set
861 +CONFIG_LXT_PHY=y
862 +# CONFIG_CICADA_PHY is not set
863 +# CONFIG_VITESSE_PHY is not set
864 +# CONFIG_SMSC_PHY is not set
865 +# CONFIG_BROADCOM_PHY is not set
866 +# CONFIG_FIXED_PHY is not set
867
868 #
869 # Ethernet (10 or 100Mbit)
870 #
871 CONFIG_NET_ETHERNET=y
872 -CONFIG_MII=y
873 +# CONFIG_MII is not set
874 CONFIG_MACB=y
875 # CONFIG_NETDEV_1000 is not set
876 # CONFIG_NETDEV_10000 is not set
877 @@ -443,7 +485,42 @@
878 #
879 # Input device support
880 #
881 -# CONFIG_INPUT is not set
882 +CONFIG_INPUT=m
883 +# CONFIG_INPUT_FF_MEMLESS is not set
884 +CONFIG_INPUT_POLLDEV=m
885 +
886 +#
887 +# Userland interfaces
888 +#
889 +CONFIG_INPUT_MOUSEDEV=m
890 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
891 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
892 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
893 +# CONFIG_INPUT_JOYDEV is not set
894 +# CONFIG_INPUT_TSDEV is not set
895 +# CONFIG_INPUT_EVDEV is not set
896 +# CONFIG_INPUT_EVBUG is not set
897 +
898 +#
899 +# Input Device Drivers
900 +#
901 +CONFIG_INPUT_KEYBOARD=y
902 +# CONFIG_KEYBOARD_ATKBD is not set
903 +# CONFIG_KEYBOARD_SUNKBD is not set
904 +# CONFIG_KEYBOARD_LKKBD is not set
905 +# CONFIG_KEYBOARD_XTKBD is not set
906 +# CONFIG_KEYBOARD_NEWTON is not set
907 +# CONFIG_KEYBOARD_STOWAWAY is not set
908 +CONFIG_KEYBOARD_GPIO=m
909 +CONFIG_INPUT_MOUSE=y
910 +# CONFIG_MOUSE_PS2 is not set
911 +# CONFIG_MOUSE_SERIAL is not set
912 +# CONFIG_MOUSE_VSXXXAA is not set
913 +CONFIG_MOUSE_GPIO=m
914 +# CONFIG_INPUT_JOYSTICK is not set
915 +# CONFIG_INPUT_TABLET is not set
916 +# CONFIG_INPUT_TOUCHSCREEN is not set
917 +# CONFIG_INPUT_MISC is not set
918
919 #
920 # Hardware I/O ports
921 @@ -477,7 +554,15 @@
922 # IPMI
923 #
924 # CONFIG_IPMI_HANDLER is not set
925 -# CONFIG_WATCHDOG is not set
926 +CONFIG_WATCHDOG=y
927 +# CONFIG_WATCHDOG_NOWAYOUT is not set
928 +
929 +#
930 +# Watchdog Device Drivers
931 +#
932 +# CONFIG_SOFT_WATCHDOG is not set
933 +CONFIG_AT32AP700X_WDT=y
934 +CONFIG_AT32AP700X_WDT_TIMEOUT=2
935 # CONFIG_HW_RANDOM is not set
936 # CONFIG_RTC is not set
937 # CONFIG_GEN_RTC is not set
938 @@ -488,13 +573,61 @@
939 # TPM devices
940 #
941 # CONFIG_TCG_TPM is not set
942 -# CONFIG_I2C is not set
943 +CONFIG_I2C=m
944 +CONFIG_I2C_BOARDINFO=y
945 +CONFIG_I2C_CHARDEV=m
946 +
947 +#
948 +# I2C Algorithms
949 +#
950 +CONFIG_I2C_ALGOBIT=m
951 +# CONFIG_I2C_ALGOPCF is not set
952 +# CONFIG_I2C_ALGOPCA is not set
953 +
954 +#
955 +# I2C Hardware Bus support
956 +#
957 +CONFIG_I2C_ATMELTWI=m
958 +CONFIG_I2C_ATMELTWI_BAUDRATE=100000
959 +CONFIG_I2C_GPIO=m
960 +# CONFIG_I2C_OCORES is not set
961 +# CONFIG_I2C_PARPORT_LIGHT is not set
962 +# CONFIG_I2C_SIMTEC is not set
963 +# CONFIG_I2C_STUB is not set
964 +
965 +#
966 +# Miscellaneous I2C Chip support
967 +#
968 +# CONFIG_SENSORS_DS1337 is not set
969 +# CONFIG_SENSORS_DS1374 is not set
970 +# CONFIG_SENSORS_EEPROM is not set
971 +# CONFIG_SENSORS_PCF8574 is not set
972 +# CONFIG_SENSORS_PCA9539 is not set
973 +# CONFIG_SENSORS_PCF8591 is not set
974 +# CONFIG_SENSORS_MAX6875 is not set
975 +# CONFIG_I2C_DEBUG_CORE is not set
976 +# CONFIG_I2C_DEBUG_ALGO is not set
977 +# CONFIG_I2C_DEBUG_BUS is not set
978 +# CONFIG_I2C_DEBUG_CHIP is not set
979
980 #
981 # SPI support
982 #
983 -# CONFIG_SPI is not set
984 -# CONFIG_SPI_MASTER is not set
985 +CONFIG_SPI=y
986 +# CONFIG_SPI_DEBUG is not set
987 +CONFIG_SPI_MASTER=y
988 +
989 +#
990 +# SPI Master Controller Drivers
991 +#
992 +CONFIG_SPI_ATMEL=y
993 +# CONFIG_SPI_BITBANG is not set
994 +
995 +#
996 +# SPI Protocol Masters
997 +#
998 +# CONFIG_SPI_AT25 is not set
999 +CONFIG_SPI_SPIDEV=m
1000
1001 #
1002 # Dallas's 1-wire bus
1003 @@ -517,14 +650,40 @@
1004 #
1005 # Graphics support
1006 #
1007 -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1008 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
1009 +CONFIG_LCD_CLASS_DEVICE=y
1010 +CONFIG_LCD_LTV350QV=y
1011 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
1012
1013 #
1014 # Display device support
1015 #
1016 # CONFIG_DISPLAY_SUPPORT is not set
1017 # CONFIG_VGASTATE is not set
1018 -# CONFIG_FB is not set
1019 +CONFIG_FB=y
1020 +# CONFIG_FIRMWARE_EDID is not set
1021 +# CONFIG_FB_DDC is not set
1022 +CONFIG_FB_CFB_FILLRECT=y
1023 +CONFIG_FB_CFB_COPYAREA=y
1024 +CONFIG_FB_CFB_IMAGEBLIT=y
1025 +# CONFIG_FB_SYS_FILLRECT is not set
1026 +# CONFIG_FB_SYS_COPYAREA is not set
1027 +# CONFIG_FB_SYS_IMAGEBLIT is not set
1028 +# CONFIG_FB_SYS_FOPS is not set
1029 +CONFIG_FB_DEFERRED_IO=y
1030 +# CONFIG_FB_SVGALIB is not set
1031 +# CONFIG_FB_MACMODES is not set
1032 +# CONFIG_FB_BACKLIGHT is not set
1033 +# CONFIG_FB_MODE_HELPERS is not set
1034 +# CONFIG_FB_TILEBLITTING is not set
1035 +
1036 +#
1037 +# Frame buffer hardware drivers
1038 +#
1039 +# CONFIG_FB_S1D13XXX is not set
1040 +CONFIG_FB_ATMEL=y
1041 +# CONFIG_FB_VIRTUAL is not set
1042 +# CONFIG_LOGO is not set
1043
1044 #
1045 # Sound
1046 @@ -532,6 +691,11 @@
1047 # CONFIG_SOUND is not set
1048
1049 #
1050 +# HID Devices
1051 +#
1052 +# CONFIG_HID is not set
1053 +
1054 +#
1055 # USB support
1056 #
1057 # CONFIG_USB_ARCH_HAS_HCD is not set
1058 @@ -545,21 +709,59 @@
1059 #
1060 # USB Gadget Support
1061 #
1062 -# CONFIG_USB_GADGET is not set
1063 -# CONFIG_MMC is not set
1064 +CONFIG_USB_GADGET=y
1065 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1066 +CONFIG_USB_GADGET_SELECTED=y
1067 +# CONFIG_USB_GADGET_FSL_USB2 is not set
1068 +# CONFIG_USB_GADGET_NET2280 is not set
1069 +# CONFIG_USB_GADGET_PXA2XX is not set
1070 +# CONFIG_USB_GADGET_GOKU is not set
1071 +# CONFIG_USB_GADGET_LH7A40X is not set
1072 +CONFIG_USB_GADGET_ATMEL_USBA=y
1073 +CONFIG_USB_ATMEL_USBA=y
1074 +# CONFIG_USB_GADGET_OMAP is not set
1075 +# CONFIG_USB_GADGET_AT91 is not set
1076 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1077 +CONFIG_USB_GADGET_DUALSPEED=y
1078 +CONFIG_USB_ZERO=m
1079 +CONFIG_USB_ETH=m
1080 +CONFIG_USB_ETH_RNDIS=y
1081 +CONFIG_USB_GADGETFS=m
1082 +CONFIG_USB_FILE_STORAGE=m
1083 +# CONFIG_USB_FILE_STORAGE_TEST is not set
1084 +CONFIG_USB_G_SERIAL=m
1085 +# CONFIG_USB_MIDI_GADGET is not set
1086 +CONFIG_MMC=y
1087 +# CONFIG_MMC_DEBUG is not set
1088 +# CONFIG_MMC_UNSAFE_RESUME is not set
1089 +
1090 +#
1091 +# MMC/SD Card Drivers
1092 +#
1093 +CONFIG_MMC_BLOCK=y
1094 +
1095 +#
1096 +# MMC/SD Host Controller Drivers
1097 +#
1098 +CONFIG_MMC_ATMELMCI=y
1099
1100 #
1101 # LED devices
1102 #
1103 -# CONFIG_NEW_LEDS is not set
1104 +CONFIG_NEW_LEDS=y
1105 +CONFIG_LEDS_CLASS=m
1106
1107 #
1108 # LED drivers
1109 #
1110 +CONFIG_LEDS_GPIO=m
1111
1112 #
1113 # LED Triggers
1114 #
1115 +CONFIG_LEDS_TRIGGERS=y
1116 +CONFIG_LEDS_TRIGGER_TIMER=m
1117 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1118
1119 #
1120 # InfiniBand support
1121 @@ -572,7 +774,50 @@
1122 #
1123 # Real Time Clock
1124 #
1125 -# CONFIG_RTC_CLASS is not set
1126 +CONFIG_RTC_LIB=y
1127 +CONFIG_RTC_CLASS=y
1128 +# CONFIG_RTC_HCTOSYS is not set
1129 +# CONFIG_RTC_DEBUG is not set
1130 +
1131 +#
1132 +# RTC interfaces
1133 +#
1134 +CONFIG_RTC_INTF_SYSFS=y
1135 +CONFIG_RTC_INTF_PROC=y
1136 +CONFIG_RTC_INTF_DEV=y
1137 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1138 +# CONFIG_RTC_DRV_TEST is not set
1139 +
1140 +#
1141 +# I2C RTC drivers
1142 +#
1143 +# CONFIG_RTC_DRV_DS1307 is not set
1144 +# CONFIG_RTC_DRV_DS1672 is not set
1145 +# CONFIG_RTC_DRV_MAX6900 is not set
1146 +# CONFIG_RTC_DRV_RS5C372 is not set
1147 +# CONFIG_RTC_DRV_ISL1208 is not set
1148 +# CONFIG_RTC_DRV_X1205 is not set
1149 +# CONFIG_RTC_DRV_PCF8563 is not set
1150 +# CONFIG_RTC_DRV_PCF8583 is not set
1151 +
1152 +#
1153 +# SPI RTC drivers
1154 +#
1155 +# CONFIG_RTC_DRV_RS5C348 is not set
1156 +# CONFIG_RTC_DRV_MAX6902 is not set
1157 +
1158 +#
1159 +# Platform RTC drivers
1160 +#
1161 +# CONFIG_RTC_DRV_DS1553 is not set
1162 +# CONFIG_RTC_DRV_DS1742 is not set
1163 +# CONFIG_RTC_DRV_M48T86 is not set
1164 +# CONFIG_RTC_DRV_V3020 is not set
1165 +
1166 +#
1167 +# on-CPU RTC drivers
1168 +#
1169 +CONFIG_RTC_DRV_AT32AP700X=y
1170
1171 #
1172 # DMA Engine support
1173 @@ -590,11 +835,14 @@
1174 #
1175 # File systems
1176 #
1177 -CONFIG_EXT2_FS=m
1178 +CONFIG_EXT2_FS=y
1179 # CONFIG_EXT2_FS_XATTR is not set
1180 # CONFIG_EXT2_FS_XIP is not set
1181 -# CONFIG_EXT3_FS is not set
1182 +CONFIG_EXT3_FS=y
1183 +# CONFIG_EXT3_FS_XATTR is not set
1184 # CONFIG_EXT4DEV_FS is not set
1185 +CONFIG_JBD=y
1186 +# CONFIG_JBD_DEBUG is not set
1187 # CONFIG_REISERFS_FS is not set
1188 # CONFIG_JFS_FS is not set
1189 # CONFIG_FS_POSIX_ACL is not set
1190 @@ -609,7 +857,7 @@
1191 # CONFIG_DNOTIFY is not set
1192 # CONFIG_AUTOFS_FS is not set
1193 # CONFIG_AUTOFS4_FS is not set
1194 -# CONFIG_FUSE_FS is not set
1195 +CONFIG_FUSE_FS=m
1196
1197 #
1198 # CD-ROM/DVD Filesystems
1199 @@ -638,7 +886,7 @@
1200 # CONFIG_TMPFS_POSIX_ACL is not set
1201 # CONFIG_HUGETLB_PAGE is not set
1202 CONFIG_RAMFS=y
1203 -CONFIG_CONFIGFS_FS=m
1204 +CONFIG_CONFIGFS_FS=y
1205
1206 #
1207 # Miscellaneous filesystems
1208 @@ -683,8 +931,14 @@
1209 # CONFIG_SUNRPC_BIND34 is not set
1210 # CONFIG_RPCSEC_GSS_KRB5 is not set
1211 # CONFIG_RPCSEC_GSS_SPKM3 is not set
1212 -# CONFIG_SMB_FS is not set
1213 -# CONFIG_CIFS is not set
1214 +CONFIG_SMB_FS=m
1215 +# CONFIG_SMB_NLS_DEFAULT is not set
1216 +CONFIG_CIFS=m
1217 +# CONFIG_CIFS_STATS is not set
1218 +# CONFIG_CIFS_WEAK_PW_HASH is not set
1219 +# CONFIG_CIFS_XATTR is not set
1220 +# CONFIG_CIFS_DEBUG2 is not set
1221 +# CONFIG_CIFS_EXPERIMENTAL is not set
1222 # CONFIG_NCP_FS is not set
1223 # CONFIG_CODA_FS is not set
1224 # CONFIG_AFS_FS is not set
1225 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/dw-dmac.c linux-avr32.git/arch/avr32/drivers/dw-dmac.c
1226 --- linux-2.6.22.1/arch/avr32/drivers/dw-dmac.c 1970-01-01 01:00:00.000000000 +0100
1227 +++ linux-avr32.git/arch/avr32/drivers/dw-dmac.c 2007-07-13 11:24:16.000000000 +0200
1228 @@ -0,0 +1,761 @@
1229 +/*
1230 + * Driver for the Synopsys DesignWare DMA Controller
1231 + *
1232 + * Copyright (C) 2005-2006 Atmel Corporation
1233 + *
1234 + * This program is free software; you can redistribute it and/or modify
1235 + * it under the terms of the GNU General Public License version 2 as
1236 + * published by the Free Software Foundation.
1237 + */
1238 +#include <linux/clk.h>
1239 +#include <linux/device.h>
1240 +#include <linux/dma-mapping.h>
1241 +#include <linux/dmapool.h>
1242 +#include <linux/init.h>
1243 +#include <linux/interrupt.h>
1244 +#include <linux/module.h>
1245 +#include <linux/platform_device.h>
1246 +
1247 +#include <asm/dma-controller.h>
1248 +#include <asm/io.h>
1249 +
1250 +#include "dw-dmac.h"
1251 +
1252 +#define DMAC_NR_CHANNELS 3
1253 +#define DMAC_MAX_BLOCKSIZE 4095
1254 +
1255 +enum {
1256 + CH_STATE_FREE = 0,
1257 + CH_STATE_ALLOCATED,
1258 + CH_STATE_BUSY,
1259 +};
1260 +
1261 +struct dw_dma_lli {
1262 + dma_addr_t sar;
1263 + dma_addr_t dar;
1264 + dma_addr_t llp;
1265 + u32 ctllo;
1266 + u32 ctlhi;
1267 + u32 sstat;
1268 + u32 dstat;
1269 +};
1270 +
1271 +struct dw_dma_block {
1272 + struct dw_dma_lli *lli_vaddr;
1273 + dma_addr_t lli_dma_addr;
1274 +};
1275 +
1276 +struct dw_dma_channel {
1277 + unsigned int state;
1278 + int is_cyclic;
1279 + struct dma_request_sg *req_sg;
1280 + struct dma_request_cyclic *req_cyclic;
1281 + unsigned int nr_blocks;
1282 + int direction;
1283 + struct dw_dma_block *block;
1284 +};
1285 +
1286 +struct dw_dma_controller {
1287 + spinlock_t lock;
1288 + void * __iomem regs;
1289 + struct dma_pool *lli_pool;
1290 + struct clk *hclk;
1291 + struct dma_controller dma;
1292 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
1293 +};
1294 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
1295 +
1296 +#define dmac_writel_hi(dmac, reg, value) \
1297 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
1298 +#define dmac_readl_hi(dmac, reg) \
1299 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
1300 +#define dmac_writel_lo(dmac, reg, value) \
1301 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
1302 +#define dmac_readl_lo(dmac, reg) \
1303 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
1304 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
1305 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
1306 + + DW_DMAC_CHAN_##reg + 4))
1307 +#define dmac_chan_readl_hi(dmac, chan, reg) \
1308 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
1309 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
1310 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
1311 +#define dmac_chan_readl_lo(dmac, chan, reg) \
1312 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
1313 +#define set_channel_bit(dmac, reg, chan) \
1314 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
1315 +#define clear_channel_bit(dmac, reg, chan) \
1316 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
1317 +
1318 +static int dmac_alloc_channel(struct dma_controller *_dmac)
1319 +{
1320 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1321 + struct dw_dma_channel *chan;
1322 + unsigned long flags;
1323 + int i;
1324 +
1325 + spin_lock_irqsave(&dmac->lock, flags);
1326 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
1327 + if (dmac->channel[i].state == CH_STATE_FREE)
1328 + break;
1329 +
1330 + if (i < DMAC_NR_CHANNELS) {
1331 + chan = &dmac->channel[i];
1332 + chan->state = CH_STATE_ALLOCATED;
1333 + } else {
1334 + i = -EBUSY;
1335 + }
1336 +
1337 + spin_unlock_irqrestore(&dmac->lock, flags);
1338 +
1339 + return i;
1340 +}
1341 +
1342 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
1343 +{
1344 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1345 +
1346 + BUG_ON(channel >= DMAC_NR_CHANNELS
1347 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
1348 +
1349 + dmac->channel[channel].state = CH_STATE_FREE;
1350 +}
1351 +
1352 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
1353 + unsigned int nr_blocks)
1354 +{
1355 + struct dw_dma_block *block;
1356 + void *p;
1357 + unsigned int i;
1358 +
1359 + block = kmalloc(nr_blocks * sizeof(*block),
1360 + GFP_KERNEL);
1361 + if (unlikely(!block))
1362 + return NULL;
1363 +
1364 + for (i = 0; i < nr_blocks; i++) {
1365 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
1366 + &block[i].lli_dma_addr);
1367 + block[i].lli_vaddr = p;
1368 + if (unlikely(!p))
1369 + goto fail;
1370 + }
1371 +
1372 + return block;
1373 +
1374 +fail:
1375 + for (i = 0; i < nr_blocks; i++) {
1376 + if (!block[i].lli_vaddr)
1377 + break;
1378 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
1379 + block[i].lli_dma_addr);
1380 + }
1381 + kfree(block);
1382 + return NULL;
1383 +}
1384 +
1385 +static void cleanup_channel(struct dw_dma_controller *dmac,
1386 + struct dw_dma_channel *chan)
1387 +{
1388 + unsigned int i;
1389 +
1390 + if (chan->nr_blocks > 1) {
1391 + for (i = 0; i < chan->nr_blocks; i++)
1392 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
1393 + chan->block[i].lli_dma_addr);
1394 + kfree(chan->block);
1395 + }
1396 +
1397 + chan->state = CH_STATE_ALLOCATED;
1398 +}
1399 +
1400 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
1401 + struct dma_request_sg *req)
1402 +{
1403 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1404 + struct dw_dma_channel *chan;
1405 + unsigned long ctlhi, ctllo, cfghi, cfglo;
1406 + unsigned long block_size;
1407 + unsigned int nr_blocks;
1408 + int ret, i, direction;
1409 + unsigned long flags;
1410 +
1411 + spin_lock_irqsave(&dmac->lock, flags);
1412 +
1413 + ret = -EINVAL;
1414 + if (req->req.channel >= DMAC_NR_CHANNELS
1415 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
1416 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
1417 + spin_unlock_irqrestore(&dmac->lock, flags);
1418 + return -EINVAL;
1419 + }
1420 +
1421 + chan = &dmac->channel[req->req.channel];
1422 + chan->state = CH_STATE_BUSY;
1423 + chan->req_sg = req;
1424 + chan->is_cyclic = 0;
1425 +
1426 + /*
1427 + * We have marked the channel as busy, so no need to keep the
1428 + * lock as long as we only touch the channel-specific
1429 + * registers
1430 + */
1431 + spin_unlock_irqrestore(&dmac->lock, flags);
1432 +
1433 + /*
1434 + * There may be limitations in the driver and/or the DMA
1435 + * controller that prevents us from sending a whole
1436 + * scatterlist item in one go. Taking this into account,
1437 + * calculate the number of block transfers we need to set up.
1438 + *
1439 + * FIXME: Let the peripheral driver know about the maximum
1440 + * block size we support. We really don't want to use a
1441 + * different block size than what was suggested by the
1442 + * peripheral.
1443 + *
1444 + * Each block will get its own Linked List Item (LLI) below.
1445 + */
1446 + block_size = req->block_size;
1447 + nr_blocks = req->nr_blocks;
1448 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
1449 + block_size, nr_blocks, req->nr_sg);
1450 +
1451 + BUG_ON(nr_blocks == 0);
1452 + chan->nr_blocks = nr_blocks;
1453 +
1454 + ret = -EINVAL;
1455 + cfglo = cfghi = 0;
1456 + switch (req->direction) {
1457 + case DMA_DIR_MEM_TO_PERIPH:
1458 + direction = DMA_TO_DEVICE;
1459 + cfghi = req->periph_id << (43 - 32);
1460 + break;
1461 +
1462 + case DMA_DIR_PERIPH_TO_MEM:
1463 + direction = DMA_FROM_DEVICE;
1464 + cfghi = req->periph_id << (39 - 32);
1465 + break;
1466 + default:
1467 + goto out_unclaim_channel;
1468 + }
1469 +
1470 + chan->direction = direction;
1471 +
1472 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
1473 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
1474 +
1475 + ctlhi = block_size >> req->width;
1476 + ctllo = ((req->direction << 20)
1477 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
1478 + | (req->width << 4) | (req->width << 1)
1479 + | (1 << 0)); // interrupt enable
1480 +
1481 + if (nr_blocks == 1) {
1482 + /* Only one block: No need to use block chaining */
1483 + if (direction == DMA_TO_DEVICE) {
1484 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
1485 + req->sg->dma_address);
1486 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
1487 + req->data_reg);
1488 + ctllo |= 2 << 7; // no dst increment
1489 + } else {
1490 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
1491 + req->data_reg);
1492 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
1493 + req->sg->dma_address);
1494 + ctllo |= 2 << 9; // no src increment
1495 + }
1496 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
1497 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
1498 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
1499 + } else {
1500 + struct dw_dma_lli *lli, *lli_prev = NULL;
1501 + int j = 0, offset = 0;
1502 +
1503 + ret = -ENOMEM;
1504 + chan->block = allocate_blocks(dmac, nr_blocks);
1505 + if (!chan->block)
1506 + goto out_unclaim_channel;
1507 +
1508 + if (direction == DMA_TO_DEVICE)
1509 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
1510 + else
1511 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
1512 +
1513 + /*
1514 + * Map scatterlist items to blocks. One scatterlist
1515 + * item may need more than one block for the reasons
1516 + * mentioned above.
1517 + */
1518 + for (i = 0; i < nr_blocks; i++) {
1519 + lli = chan->block[i].lli_vaddr;
1520 + if (lli_prev) {
1521 + lli_prev->llp = chan->block[i].lli_dma_addr;
1522 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1523 + i - 1, chan->block[i - 1].lli_vaddr,
1524 + chan->block[i - 1].lli_dma_addr,
1525 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
1526 + lli_prev->ctllo, lli_prev->ctlhi);
1527 + }
1528 + lli->llp = 0;
1529 + lli->ctllo = ctllo;
1530 + lli->ctlhi = ctlhi;
1531 + if (direction == DMA_TO_DEVICE) {
1532 + lli->sar = req->sg[j].dma_address + offset;
1533 + lli->dar = req->data_reg;
1534 + } else {
1535 + lli->sar = req->data_reg;
1536 + lli->dar = req->sg[j].dma_address + offset;
1537 + }
1538 + lli_prev = lli;
1539 +
1540 + offset += block_size;
1541 + if (offset > req->sg[j].length) {
1542 + j++;
1543 + offset = 0;
1544 + }
1545 + }
1546 +
1547 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1548 + i - 1, chan->block[i - 1].lli_vaddr,
1549 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
1550 + lli_prev->dar, lli_prev->llp,
1551 + lli_prev->ctllo, lli_prev->ctlhi);
1552 +
1553 + /*
1554 + * SAR, DAR and CTL are initialized from the LLI. We
1555 + * only have to enable the LLI bits in CTL.
1556 + */
1557 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
1558 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
1559 + chan->block[0].lli_dma_addr);
1560 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
1561 + }
1562 +
1563 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
1564 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
1565 + if (req->req.block_complete)
1566 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1567 + else
1568 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1569 +
1570 + return 0;
1571 +
1572 +out_unclaim_channel:
1573 + chan->state = CH_STATE_ALLOCATED;
1574 + return ret;
1575 +}
1576 +
1577 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
1578 + struct dma_request_cyclic *req)
1579 +{
1580 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1581 + struct dw_dma_channel *chan;
1582 + unsigned long ctlhi, ctllo, cfghi, cfglo;
1583 + unsigned long block_size;
1584 + int ret, i, direction;
1585 + unsigned long flags;
1586 +
1587 + spin_lock_irqsave(&dmac->lock, flags);
1588 +
1589 + block_size = (req->buffer_size/req->periods) >> req->width;
1590 +
1591 + ret = -EINVAL;
1592 + if (req->req.channel >= DMAC_NR_CHANNELS
1593 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
1594 + || (req->periods == 0)
1595 + || block_size > DMAC_MAX_BLOCKSIZE) {
1596 + spin_unlock_irqrestore(&dmac->lock, flags);
1597 + return -EINVAL;
1598 + }
1599 +
1600 + chan = &dmac->channel[req->req.channel];
1601 + chan->state = CH_STATE_BUSY;
1602 + chan->is_cyclic = 1;
1603 + chan->req_cyclic = req;
1604 +
1605 + /*
1606 + * We have marked the channel as busy, so no need to keep the
1607 + * lock as long as we only touch the channel-specific
1608 + * registers
1609 + */
1610 + spin_unlock_irqrestore(&dmac->lock, flags);
1611 +
1612 + /*
1613 + Setup
1614 + */
1615 + BUG_ON(req->buffer_size % req->periods);
1616 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
1617 +
1618 + chan->nr_blocks = req->periods;
1619 +
1620 + ret = -EINVAL;
1621 + cfglo = cfghi = 0;
1622 + switch (req->direction) {
1623 + case DMA_DIR_MEM_TO_PERIPH:
1624 + direction = DMA_TO_DEVICE;
1625 + cfghi = req->periph_id << (43 - 32);
1626 + break;
1627 +
1628 + case DMA_DIR_PERIPH_TO_MEM:
1629 + direction = DMA_FROM_DEVICE;
1630 + cfghi = req->periph_id << (39 - 32);
1631 + break;
1632 + default:
1633 + goto out_unclaim_channel;
1634 + }
1635 +
1636 + chan->direction = direction;
1637 +
1638 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
1639 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
1640 +
1641 + ctlhi = block_size;
1642 + ctllo = ((req->direction << 20)
1643 + | (req->width << 4) | (req->width << 1)
1644 + | (1 << 0)); // interrupt enable
1645 +
1646 + {
1647 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
1648 +
1649 + ret = -ENOMEM;
1650 + chan->block = allocate_blocks(dmac, req->periods);
1651 + if (!chan->block)
1652 + goto out_unclaim_channel;
1653 +
1654 + if (direction == DMA_TO_DEVICE)
1655 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
1656 + else
1657 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
1658 +
1659 + /*
1660 + * Set up a linked list items where each period gets
1661 + * an item. The linked list item for the last period
1662 + * points back to the star of the buffer making a
1663 + * cyclic buffer.
1664 + */
1665 + for (i = 0; i < req->periods; i++) {
1666 + lli = chan->block[i].lli_vaddr;
1667 + if (lli_prev) {
1668 + lli_prev->llp = chan->block[i].lli_dma_addr;
1669 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1670 + i - 1, chan->block[i - 1].lli_vaddr,
1671 + chan->block[i - 1].lli_dma_addr,
1672 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
1673 + lli_prev->ctllo, lli_prev->ctlhi);*/
1674 + }
1675 + lli->llp = 0;
1676 + lli->ctllo = ctllo;
1677 + lli->ctlhi = ctlhi;
1678 + if (direction == DMA_TO_DEVICE) {
1679 + lli->sar = req->buffer_start + i*(block_size << req->width);
1680 + lli->dar = req->data_reg;
1681 + } else {
1682 + lli->sar = req->data_reg;
1683 + lli->dar = req->buffer_start + i*(block_size << req->width);
1684 + }
1685 + lli_prev = lli;
1686 + }
1687 + lli->llp = chan->block[0].lli_dma_addr;
1688 +
1689 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1690 + i - 1, chan->block[i - 1].lli_vaddr,
1691 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
1692 + lli_prev->dar, lli_prev->llp,
1693 + lli_prev->ctllo, lli_prev->ctlhi); */
1694 +
1695 + /*
1696 + * SAR, DAR and CTL are initialized from the LLI. We
1697 + * only have to enable the LLI bits in CTL.
1698 + */
1699 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
1700 + chan->block[0].lli_dma_addr);
1701 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
1702 + }
1703 +
1704 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
1705 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
1706 + if (req->req.block_complete)
1707 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1708 + else
1709 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1710 +
1711 + return 0;
1712 +
1713 +out_unclaim_channel:
1714 + chan->state = CH_STATE_ALLOCATED;
1715 + return ret;
1716 +}
1717 +
1718 +static int dmac_start_request(struct dma_controller *_dmac,
1719 + unsigned int channel)
1720 +{
1721 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1722 +
1723 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1724 +
1725 + set_channel_bit(dmac, CH_EN, channel);
1726 +
1727 + return 0;
1728 +}
1729 +
1730 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
1731 + unsigned int channel)
1732 +{
1733 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1734 + struct dw_dma_channel *chan;
1735 + dma_addr_t current_pos;
1736 +
1737 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1738 +
1739 + chan = &dmac->channel[channel];
1740 +
1741 + switch (chan->direction) {
1742 + case DMA_TO_DEVICE:
1743 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
1744 + break;
1745 + case DMA_FROM_DEVICE:
1746 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
1747 + break;
1748 + default:
1749 + return 0;
1750 + }
1751 +
1752 +
1753 + if (!current_pos) {
1754 + if (chan->is_cyclic) {
1755 + current_pos = chan->req_cyclic->buffer_start;
1756 + } else {
1757 + current_pos = chan->req_sg->sg->dma_address;
1758 + }
1759 + }
1760 +
1761 + return current_pos;
1762 +}
1763 +
1764 +
1765 +static int dmac_stop_request(struct dma_controller *_dmac,
1766 + unsigned int channel)
1767 +{
1768 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1769 + struct dw_dma_channel *chan;
1770 +
1771 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1772 +
1773 + chan = &dmac->channel[channel];
1774 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
1775 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
1776 + dmac_chan_readl_lo(dmac, channel, DAR),
1777 + dmac_chan_readl_lo(dmac, channel, LLP),
1778 + dmac_chan_readl_hi(dmac, channel, CTL),
1779 + dmac_chan_readl_lo(dmac, channel, CTL));
1780 +
1781 + if (chan->state == CH_STATE_BUSY) {
1782 + clear_channel_bit(dmac, CH_EN, channel);
1783 + cleanup_channel(dmac, &dmac->channel[channel]);
1784 + }
1785 +
1786 + return 0;
1787 +}
1788 +
1789 +
1790 +static void dmac_block_complete(struct dw_dma_controller *dmac)
1791 +{
1792 + struct dw_dma_channel *chan;
1793 + unsigned long status, chanid;
1794 +
1795 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
1796 +
1797 + while (status) {
1798 + struct dma_request *req;
1799 + chanid = __ffs(status);
1800 + chan = &dmac->channel[chanid];
1801 +
1802 + if (chan->is_cyclic) {
1803 + BUG_ON(!chan->req_cyclic
1804 + || !chan->req_cyclic->req.block_complete);
1805 + req = &chan->req_cyclic->req;
1806 + } else {
1807 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
1808 + req = &chan->req_sg->req;
1809 + }
1810 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
1811 + req->block_complete(req);
1812 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
1813 + }
1814 +}
1815 +
1816 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
1817 +{
1818 + struct dw_dma_channel *chan;
1819 + struct dma_request *req;
1820 + unsigned long status, chanid;
1821 +
1822 + status = dmac_readl_lo(dmac, STATUS_XFER);
1823 +
1824 + while (status) {
1825 + chanid = __ffs(status);
1826 + chan = &dmac->channel[chanid];
1827 +
1828 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
1829 +
1830 + req = &chan->req_sg->req;
1831 + BUG_ON(!req);
1832 + cleanup_channel(dmac, chan);
1833 + if (req->xfer_complete)
1834 + req->xfer_complete(req);
1835 +
1836 + status = dmac_readl_lo(dmac, STATUS_XFER);
1837 + }
1838 +}
1839 +
1840 +static void dmac_error(struct dw_dma_controller *dmac)
1841 +{
1842 + struct dw_dma_channel *chan;
1843 + unsigned long status, chanid;
1844 +
1845 + status = dmac_readl_lo(dmac, STATUS_ERROR);
1846 +
1847 + while (status) {
1848 + struct dma_request *req;
1849 +
1850 + chanid = __ffs(status);
1851 + chan = &dmac->channel[chanid];
1852 +
1853 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
1854 + clear_channel_bit(dmac, CH_EN, chanid);
1855 +
1856 + if (chan->is_cyclic) {
1857 + BUG_ON(!chan->req_cyclic);
1858 + req = &chan->req_cyclic->req;
1859 + } else {
1860 + BUG_ON(!chan->req_sg);
1861 + req = &chan->req_sg->req;
1862 + }
1863 +
1864 + cleanup_channel(dmac, chan);
1865 + if (req->error)
1866 + req->error(req);
1867 +
1868 + status = dmac_readl_lo(dmac, STATUS_XFER);
1869 + }
1870 +}
1871 +
1872 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
1873 +{
1874 + struct dw_dma_controller *dmac = dev_id;
1875 + unsigned long status;
1876 + int ret = IRQ_NONE;
1877 +
1878 + spin_lock(&dmac->lock);
1879 +
1880 + status = dmac_readl_lo(dmac, STATUS_INT);
1881 +
1882 + while (status) {
1883 + ret = IRQ_HANDLED;
1884 + if (status & 0x10)
1885 + dmac_error(dmac);
1886 + if (status & 0x02)
1887 + dmac_block_complete(dmac);
1888 + if (status & 0x01)
1889 + dmac_xfer_complete(dmac);
1890 +
1891 + status = dmac_readl_lo(dmac, STATUS_INT);
1892 + }
1893 +
1894 + spin_unlock(&dmac->lock);
1895 + return ret;
1896 +}
1897 +
1898 +static int __devinit dmac_probe(struct platform_device *pdev)
1899 +{
1900 + struct dw_dma_controller *dmac;
1901 + struct resource *regs;
1902 + int ret;
1903 +
1904 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1905 + if (!regs)
1906 + return -ENXIO;
1907 +
1908 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
1909 + if (!dmac)
1910 + return -ENOMEM;
1911 + memset(dmac, 0, sizeof(*dmac));
1912 +
1913 + dmac->hclk = clk_get(&pdev->dev, "hclk");
1914 + if (IS_ERR(dmac->hclk)) {
1915 + ret = PTR_ERR(dmac->hclk);
1916 + goto out_free_dmac;
1917 + }
1918 + clk_enable(dmac->hclk);
1919 +
1920 + ret = -ENOMEM;
1921 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
1922 + sizeof(struct dw_dma_lli), 4, 0);
1923 + if (!dmac->lli_pool)
1924 + goto out_disable_clk;
1925 +
1926 + spin_lock_init(&dmac->lock);
1927 + dmac->dma.dev = &pdev->dev;
1928 + dmac->dma.alloc_channel = dmac_alloc_channel;
1929 + dmac->dma.release_channel = dmac_release_channel;
1930 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
1931 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
1932 + dmac->dma.start_request = dmac_start_request;
1933 + dmac->dma.stop_request = dmac_stop_request;
1934 + dmac->dma.get_current_pos = dmac_get_current_pos;
1935 +
1936 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
1937 + if (!dmac->regs)
1938 + goto out_free_pool;
1939 +
1940 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
1941 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
1942 + if (ret)
1943 + goto out_unmap_regs;
1944 +
1945 + /* Enable the DMA controller */
1946 + dmac_writel_lo(dmac, CFG, 1);
1947 +
1948 + register_dma_controller(&dmac->dma);
1949 +
1950 + printk(KERN_INFO
1951 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
1952 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
1953 +
1954 + return 0;
1955 +
1956 +out_unmap_regs:
1957 + iounmap(dmac->regs);
1958 +out_free_pool:
1959 + dma_pool_destroy(dmac->lli_pool);
1960 +out_disable_clk:
1961 + clk_disable(dmac->hclk);
1962 + clk_put(dmac->hclk);
1963 +out_free_dmac:
1964 + kfree(dmac);
1965 + return ret;
1966 +}
1967 +
1968 +static struct platform_driver dmac_driver = {
1969 + .probe = dmac_probe,
1970 + .driver = {
1971 + .name = "dmaca",
1972 + },
1973 +};
1974 +
1975 +static int __init dmac_init(void)
1976 +{
1977 + return platform_driver_register(&dmac_driver);
1978 +}
1979 +subsys_initcall(dmac_init);
1980 +
1981 +static void __exit dmac_exit(void)
1982 +{
1983 + platform_driver_unregister(&dmac_driver);
1984 +}
1985 +module_exit(dmac_exit);
1986 +
1987 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1988 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
1989 +MODULE_LICENSE("GPL");
1990 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/dw-dmac.h linux-avr32.git/arch/avr32/drivers/dw-dmac.h
1991 --- linux-2.6.22.1/arch/avr32/drivers/dw-dmac.h 1970-01-01 01:00:00.000000000 +0100
1992 +++ linux-avr32.git/arch/avr32/drivers/dw-dmac.h 2007-06-06 11:33:46.000000000 +0200
1993 @@ -0,0 +1,42 @@
1994 +/*
1995 + * Driver for the Synopsys DesignWare DMA Controller
1996 + *
1997 + * Copyright (C) 2005-2006 Atmel Corporation
1998 + *
1999 + * This program is free software; you can redistribute it and/or modify
2000 + * it under the terms of the GNU General Public License version 2 as
2001 + * published by the Free Software Foundation.
2002 + */
2003 +#ifndef __AVR32_DW_DMAC_H__
2004 +#define __AVR32_DW_DMAC_H__
2005 +
2006 +#define DW_DMAC_CFG 0x398
2007 +#define DW_DMAC_CH_EN 0x3a0
2008 +
2009 +#define DW_DMAC_STATUS_XFER 0x2e8
2010 +#define DW_DMAC_STATUS_BLOCK 0x2f0
2011 +#define DW_DMAC_STATUS_ERROR 0x308
2012 +
2013 +#define DW_DMAC_MASK_XFER 0x310
2014 +#define DW_DMAC_MASK_BLOCK 0x318
2015 +#define DW_DMAC_MASK_ERROR 0x330
2016 +
2017 +#define DW_DMAC_CLEAR_XFER 0x338
2018 +#define DW_DMAC_CLEAR_BLOCK 0x340
2019 +#define DW_DMAC_CLEAR_ERROR 0x358
2020 +
2021 +#define DW_DMAC_STATUS_INT 0x360
2022 +
2023 +#define DW_DMAC_CHAN_SAR 0x000
2024 +#define DW_DMAC_CHAN_DAR 0x008
2025 +#define DW_DMAC_CHAN_LLP 0x010
2026 +#define DW_DMAC_CHAN_CTL 0x018
2027 +#define DW_DMAC_CHAN_SSTAT 0x020
2028 +#define DW_DMAC_CHAN_DSTAT 0x028
2029 +#define DW_DMAC_CHAN_SSTATAR 0x030
2030 +#define DW_DMAC_CHAN_DSTATAR 0x038
2031 +#define DW_DMAC_CHAN_CFG 0x040
2032 +#define DW_DMAC_CHAN_SGR 0x048
2033 +#define DW_DMAC_CHAN_DSR 0x050
2034 +
2035 +#endif /* __AVR32_DW_DMAC_H__ */
2036 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/Makefile linux-avr32.git/arch/avr32/drivers/Makefile
2037 --- linux-2.6.22.1/arch/avr32/drivers/Makefile 1970-01-01 01:00:00.000000000 +0100
2038 +++ linux-avr32.git/arch/avr32/drivers/Makefile 2007-06-06 11:33:46.000000000 +0200
2039 @@ -0,0 +1 @@
2040 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
2041 diff -x .git -Nur linux-2.6.22.1/arch/avr32/Kconfig linux-avr32.git/arch/avr32/Kconfig
2042 --- linux-2.6.22.1/arch/avr32/Kconfig 2007-07-10 20:56:30.000000000 +0200
2043 +++ linux-avr32.git/arch/avr32/Kconfig 2007-07-13 11:24:16.000000000 +0200
2044 @@ -113,6 +113,13 @@
2045 bool "ATNGW100 Network Gateway"
2046 endchoice
2047
2048 +if BOARD_ATSTK1000
2049 +source "arch/avr32/boards/atstk1000/Kconfig"
2050 +endif
2051 +if BOARD_ATNGW100
2052 +source "arch/avr32/boards/atngw100/Kconfig"
2053 +endif
2054 +
2055 choice
2056 prompt "Boot loader type"
2057 default LOADER_U_BOOT
2058 @@ -171,6 +178,10 @@
2059 enabling Nexus-compliant debuggers to keep track of the PID of the
2060 currently executing task.
2061
2062 +config DW_DMAC
2063 + tristate "Synopsys DesignWare DMA Controller support"
2064 + default y if CPU_AT32AP7000
2065 +
2066 # FPU emulation goes here
2067
2068 source "kernel/Kconfig.hz"
2069 @@ -185,6 +196,27 @@
2070
2071 endmenu
2072
2073 +menu "Power managment options"
2074 +
2075 +menu "CPU Frequency scaling"
2076 +
2077 +source "drivers/cpufreq/Kconfig"
2078 +
2079 +config CPU_FREQ_AT32AP
2080 + bool "CPU frequency driver for AT32AP"
2081 + depends on CPU_FREQ && PLATFORM_AT32AP
2082 + default n
2083 + help
2084 + This enables the CPU frequency driver for AT32AP processors.
2085 +
2086 + For details, take a look in <file:Documentation/cpu-freq>.
2087 +
2088 + If in doubt, say N.
2089 +
2090 +endmenu
2091 +
2092 +endmenu
2093 +
2094 menu "Bus options"
2095
2096 config PCI
2097 diff -x .git -Nur linux-2.6.22.1/arch/avr32/kernel/dma-controller.c linux-avr32.git/arch/avr32/kernel/dma-controller.c
2098 --- linux-2.6.22.1/arch/avr32/kernel/dma-controller.c 1970-01-01 01:00:00.000000000 +0100
2099 +++ linux-avr32.git/arch/avr32/kernel/dma-controller.c 2007-06-06 11:33:46.000000000 +0200
2100 @@ -0,0 +1,34 @@
2101 +/*
2102 + * Preliminary DMA controller framework for AVR32
2103 + *
2104 + * Copyright (C) 2005-2006 Atmel Corporation
2105 + *
2106 + * This program is free software; you can redistribute it and/or modify
2107 + * it under the terms of the GNU General Public License version 2 as
2108 + * published by the Free Software Foundation.
2109 + */
2110 +#include <asm/dma-controller.h>
2111 +
2112 +static LIST_HEAD(controllers);
2113 +
2114 +int register_dma_controller(struct dma_controller *dmac)
2115 +{
2116 + static int next_id;
2117 +
2118 + dmac->id = next_id++;
2119 + list_add_tail(&dmac->list, &controllers);
2120 +
2121 + return 0;
2122 +}
2123 +EXPORT_SYMBOL(register_dma_controller);
2124 +
2125 +struct dma_controller *find_dma_controller(int id)
2126 +{
2127 + struct dma_controller *dmac;
2128 +
2129 + list_for_each_entry(dmac, &controllers, list)
2130 + if (dmac->id == id)
2131 + return dmac;
2132 + return NULL;
2133 +}
2134 +EXPORT_SYMBOL(find_dma_controller);
2135 diff -x .git -Nur linux-2.6.22.1/arch/avr32/kernel/Makefile linux-avr32.git/arch/avr32/kernel/Makefile
2136 --- linux-2.6.22.1/arch/avr32/kernel/Makefile 2007-07-10 20:56:30.000000000 +0200
2137 +++ linux-avr32.git/arch/avr32/kernel/Makefile 2007-06-06 11:33:46.000000000 +0200
2138 @@ -9,6 +9,7 @@
2139 obj-y += setup.o traps.o semaphore.o ptrace.o
2140 obj-y += signal.o sys_avr32.o process.o time.o
2141 obj-y += init_task.o switch_to.o cpu.o
2142 +obj-y += dma-controller.o
2143 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
2144 obj-$(CONFIG_KPROBES) += kprobes.o
2145
2146 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap7000.c linux-avr32.git/arch/avr32/mach-at32ap/at32ap7000.c
2147 --- linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap7000.c 2007-07-10 20:56:30.000000000 +0200
2148 +++ linux-avr32.git/arch/avr32/mach-at32ap/at32ap7000.c 2007-07-12 13:59:49.000000000 +0200
2149 @@ -17,14 +17,20 @@
2150 #include <asm/arch/at32ap7000.h>
2151 #include <asm/arch/board.h>
2152 #include <asm/arch/portmux.h>
2153 -#include <asm/arch/sm.h>
2154
2155 #include <video/atmel_lcdc.h>
2156
2157 #include "clock.h"
2158 #include "hmatrix.h"
2159 #include "pio.h"
2160 -#include "sm.h"
2161 +#include "pm.h"
2162 +
2163 +/*
2164 + * We can reduce the code size a bit by using a constant here. Since
2165 + * this file is completely chip-specific, it's safe to not use
2166 + * ioremap. Generic drivers should of course never do this.
2167 + */
2168 +#define AT32_PM_BASE 0xfff00000
2169
2170 #define PBMEM(base) \
2171 { \
2172 @@ -88,6 +94,8 @@
2173 .index = _index, \
2174 }
2175
2176 +static DEFINE_SPINLOCK(pm_lock);
2177 +
2178 unsigned long at32ap7000_osc_rates[3] = {
2179 [0] = 32768,
2180 /* FIXME: these are ATSTK1002-specific */
2181 @@ -104,11 +112,11 @@
2182 {
2183 unsigned long div, mul, rate;
2184
2185 - if (!(control & SM_BIT(PLLEN)))
2186 + if (!(control & PM_BIT(PLLEN)))
2187 return 0;
2188
2189 - div = SM_BFEXT(PLLDIV, control) + 1;
2190 - mul = SM_BFEXT(PLLMUL, control) + 1;
2191 + div = PM_BFEXT(PLLDIV, control) + 1;
2192 + mul = PM_BFEXT(PLLMUL, control) + 1;
2193
2194 rate = clk->parent->get_rate(clk->parent);
2195 rate = (rate + div / 2) / div;
2196 @@ -121,7 +129,7 @@
2197 {
2198 u32 control;
2199
2200 - control = sm_readl(&system_manager, PM_PLL0);
2201 + control = pm_readl(PLL0);
2202
2203 return pll_get_rate(clk, control);
2204 }
2205 @@ -130,7 +138,7 @@
2206 {
2207 u32 control;
2208
2209 - control = sm_readl(&system_manager, PM_PLL1);
2210 + control = pm_readl(PLL1);
2211
2212 return pll_get_rate(clk, control);
2213 }
2214 @@ -187,108 +195,139 @@
2215
2216 static void cpu_clk_mode(struct clk *clk, int enabled)
2217 {
2218 - struct at32_sm *sm = &system_manager;
2219 unsigned long flags;
2220 u32 mask;
2221
2222 - spin_lock_irqsave(&sm->lock, flags);
2223 - mask = sm_readl(sm, PM_CPU_MASK);
2224 + spin_lock_irqsave(&pm_lock, flags);
2225 + mask = pm_readl(CPU_MASK);
2226 if (enabled)
2227 mask |= 1 << clk->index;
2228 else
2229 mask &= ~(1 << clk->index);
2230 - sm_writel(sm, PM_CPU_MASK, mask);
2231 - spin_unlock_irqrestore(&sm->lock, flags);
2232 + pm_writel(CPU_MASK, mask);
2233 + spin_unlock_irqrestore(&pm_lock, flags);
2234 }
2235
2236 static unsigned long cpu_clk_get_rate(struct clk *clk)
2237 {
2238 unsigned long cksel, shift = 0;
2239
2240 - cksel = sm_readl(&system_manager, PM_CKSEL);
2241 - if (cksel & SM_BIT(CPUDIV))
2242 - shift = SM_BFEXT(CPUSEL, cksel) + 1;
2243 + cksel = pm_readl(CKSEL);
2244 + if (cksel & PM_BIT(CPUDIV))
2245 + shift = PM_BFEXT(CPUSEL, cksel) + 1;
2246
2247 return bus_clk_get_rate(clk, shift);
2248 }
2249
2250 +static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
2251 +{
2252 + u32 control;
2253 + unsigned long parent_rate, child_div, actual_rate, div;
2254 +
2255 + parent_rate = clk->parent->get_rate(clk->parent);
2256 + control = pm_readl(CKSEL);
2257 +
2258 + if (control & PM_BIT(HSBDIV))
2259 + child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
2260 + else
2261 + child_div = 1;
2262 +
2263 + if (rate > 3 * (parent_rate / 4) || child_div == 1) {
2264 + actual_rate = parent_rate;
2265 + control &= ~PM_BIT(CPUDIV);
2266 + } else {
2267 + unsigned int cpusel;
2268 + div = (parent_rate + rate / 2) / rate;
2269 + if (div > child_div)
2270 + div = child_div;
2271 + cpusel = (div > 1) ? (fls(div) - 2) : 0;
2272 + control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
2273 + actual_rate = parent_rate / (1 << (cpusel + 1));
2274 + }
2275 +
2276 + pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
2277 + clk->name, rate, actual_rate);
2278 +
2279 + if (apply)
2280 + pm_writel(CKSEL, control);
2281 +
2282 + return actual_rate;
2283 +}
2284 +
2285 static void hsb_clk_mode(struct clk *clk, int enabled)
2286 {
2287 - struct at32_sm *sm = &system_manager;
2288 unsigned long flags;
2289 u32 mask;
2290
2291 - spin_lock_irqsave(&sm->lock, flags);
2292 - mask = sm_readl(sm, PM_HSB_MASK);
2293 + spin_lock_irqsave(&pm_lock, flags);
2294 + mask = pm_readl(HSB_MASK);
2295 if (enabled)
2296 mask |= 1 << clk->index;
2297 else
2298 mask &= ~(1 << clk->index);
2299 - sm_writel(sm, PM_HSB_MASK, mask);
2300 - spin_unlock_irqrestore(&sm->lock, flags);
2301 + pm_writel(HSB_MASK, mask);
2302 + spin_unlock_irqrestore(&pm_lock, flags);
2303 }
2304
2305 static unsigned long hsb_clk_get_rate(struct clk *clk)
2306 {
2307 unsigned long cksel, shift = 0;
2308
2309 - cksel = sm_readl(&system_manager, PM_CKSEL);
2310 - if (cksel & SM_BIT(HSBDIV))
2311 - shift = SM_BFEXT(HSBSEL, cksel) + 1;
2312 + cksel = pm_readl(CKSEL);
2313 + if (cksel & PM_BIT(HSBDIV))
2314 + shift = PM_BFEXT(HSBSEL, cksel) + 1;
2315
2316 return bus_clk_get_rate(clk, shift);
2317 }
2318
2319 static void pba_clk_mode(struct clk *clk, int enabled)
2320 {
2321 - struct at32_sm *sm = &system_manager;
2322 unsigned long flags;
2323 u32 mask;
2324
2325 - spin_lock_irqsave(&sm->lock, flags);
2326 - mask = sm_readl(sm, PM_PBA_MASK);
2327 + spin_lock_irqsave(&pm_lock, flags);
2328 + mask = pm_readl(PBA_MASK);
2329 if (enabled)
2330 mask |= 1 << clk->index;
2331 else
2332 mask &= ~(1 << clk->index);
2333 - sm_writel(sm, PM_PBA_MASK, mask);
2334 - spin_unlock_irqrestore(&sm->lock, flags);
2335 + pm_writel(PBA_MASK, mask);
2336 + spin_unlock_irqrestore(&pm_lock, flags);
2337 }
2338
2339 static unsigned long pba_clk_get_rate(struct clk *clk)
2340 {
2341 unsigned long cksel, shift = 0;
2342
2343 - cksel = sm_readl(&system_manager, PM_CKSEL);
2344 - if (cksel & SM_BIT(PBADIV))
2345 - shift = SM_BFEXT(PBASEL, cksel) + 1;
2346 + cksel = pm_readl(CKSEL);
2347 + if (cksel & PM_BIT(PBADIV))
2348 + shift = PM_BFEXT(PBASEL, cksel) + 1;
2349
2350 return bus_clk_get_rate(clk, shift);
2351 }
2352
2353 static void pbb_clk_mode(struct clk *clk, int enabled)
2354 {
2355 - struct at32_sm *sm = &system_manager;
2356 unsigned long flags;
2357 u32 mask;
2358
2359 - spin_lock_irqsave(&sm->lock, flags);
2360 - mask = sm_readl(sm, PM_PBB_MASK);
2361 + spin_lock_irqsave(&pm_lock, flags);
2362 + mask = pm_readl(PBB_MASK);
2363 if (enabled)
2364 mask |= 1 << clk->index;
2365 else
2366 mask &= ~(1 << clk->index);
2367 - sm_writel(sm, PM_PBB_MASK, mask);
2368 - spin_unlock_irqrestore(&sm->lock, flags);
2369 + pm_writel(PBB_MASK, mask);
2370 + spin_unlock_irqrestore(&pm_lock, flags);
2371 }
2372
2373 static unsigned long pbb_clk_get_rate(struct clk *clk)
2374 {
2375 unsigned long cksel, shift = 0;
2376
2377 - cksel = sm_readl(&system_manager, PM_CKSEL);
2378 - if (cksel & SM_BIT(PBBDIV))
2379 - shift = SM_BFEXT(PBBSEL, cksel) + 1;
2380 + cksel = pm_readl(CKSEL);
2381 + if (cksel & PM_BIT(PBBDIV))
2382 + shift = PM_BFEXT(PBBSEL, cksel) + 1;
2383
2384 return bus_clk_get_rate(clk, shift);
2385 }
2386 @@ -296,6 +335,7 @@
2387 static struct clk cpu_clk = {
2388 .name = "cpu",
2389 .get_rate = cpu_clk_get_rate,
2390 + .set_rate = cpu_clk_set_rate,
2391 .users = 1,
2392 };
2393 static struct clk hsb_clk = {
2394 @@ -327,12 +367,12 @@
2395 {
2396 u32 control;
2397
2398 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
2399 + control = pm_readl(GCCTRL(clk->index));
2400 if (enabled)
2401 - control |= SM_BIT(CEN);
2402 + control |= PM_BIT(CEN);
2403 else
2404 - control &= ~SM_BIT(CEN);
2405 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
2406 + control &= ~PM_BIT(CEN);
2407 + pm_writel(GCCTRL(clk->index), control);
2408 }
2409
2410 static unsigned long genclk_get_rate(struct clk *clk)
2411 @@ -340,9 +380,9 @@
2412 u32 control;
2413 unsigned long div = 1;
2414
2415 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
2416 - if (control & SM_BIT(DIVEN))
2417 - div = 2 * (SM_BFEXT(DIV, control) + 1);
2418 + control = pm_readl(GCCTRL(clk->index));
2419 + if (control & PM_BIT(DIVEN))
2420 + div = 2 * (PM_BFEXT(DIV, control) + 1);
2421
2422 return clk->parent->get_rate(clk->parent) / div;
2423 }
2424 @@ -353,23 +393,22 @@
2425 unsigned long parent_rate, actual_rate, div;
2426
2427 parent_rate = clk->parent->get_rate(clk->parent);
2428 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
2429 + control = pm_readl(GCCTRL(clk->index));
2430
2431 if (rate > 3 * parent_rate / 4) {
2432 actual_rate = parent_rate;
2433 - control &= ~SM_BIT(DIVEN);
2434 + control &= ~PM_BIT(DIVEN);
2435 } else {
2436 div = (parent_rate + rate) / (2 * rate) - 1;
2437 - control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
2438 + control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
2439 actual_rate = parent_rate / (2 * (div + 1));
2440 }
2441
2442 - printk("clk %s: new rate %lu (actual rate %lu)\n",
2443 - clk->name, rate, actual_rate);
2444 + dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
2445 + clk->name, rate, actual_rate);
2446
2447 if (apply)
2448 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
2449 - control);
2450 + pm_writel(GCCTRL(clk->index), control);
2451
2452 return actual_rate;
2453 }
2454 @@ -378,24 +417,24 @@
2455 {
2456 u32 control;
2457
2458 - printk("clk %s: new parent %s (was %s)\n",
2459 - clk->name, parent->name, clk->parent->name);
2460 + dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
2461 + clk->name, parent->name, clk->parent->name);
2462
2463 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
2464 + control = pm_readl(GCCTRL(clk->index));
2465
2466 if (parent == &osc1 || parent == &pll1)
2467 - control |= SM_BIT(OSCSEL);
2468 + control |= PM_BIT(OSCSEL);
2469 else if (parent == &osc0 || parent == &pll0)
2470 - control &= ~SM_BIT(OSCSEL);
2471 + control &= ~PM_BIT(OSCSEL);
2472 else
2473 return -EINVAL;
2474
2475 if (parent == &pll0 || parent == &pll1)
2476 - control |= SM_BIT(PLLSEL);
2477 + control |= PM_BIT(PLLSEL);
2478 else
2479 - control &= ~SM_BIT(PLLSEL);
2480 + control &= ~PM_BIT(PLLSEL);
2481
2482 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
2483 + pm_writel(GCCTRL(clk->index), control);
2484 clk->parent = parent;
2485
2486 return 0;
2487 @@ -408,11 +447,11 @@
2488
2489 BUG_ON(clk->index > 7);
2490
2491 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
2492 - if (control & SM_BIT(OSCSEL))
2493 - parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
2494 + control = pm_readl(GCCTRL(clk->index));
2495 + if (control & PM_BIT(OSCSEL))
2496 + parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
2497 else
2498 - parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
2499 + parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
2500
2501 clk->parent = parent;
2502 }
2503 @@ -420,21 +459,53 @@
2504 /* --------------------------------------------------------------------
2505 * System peripherals
2506 * -------------------------------------------------------------------- */
2507 -static struct resource sm_resource[] = {
2508 - PBMEM(0xfff00000),
2509 - NAMED_IRQ(19, "eim"),
2510 - NAMED_IRQ(20, "pm"),
2511 - NAMED_IRQ(21, "rtc"),
2512 +static struct resource at32_pm0_resource[] = {
2513 + {
2514 + .start = 0xfff00000,
2515 + .end = 0xfff0007f,
2516 + .flags = IORESOURCE_MEM,
2517 + },
2518 + IRQ(20),
2519 };
2520 -struct platform_device at32_sm_device = {
2521 - .name = "sm",
2522 - .id = 0,
2523 - .resource = sm_resource,
2524 - .num_resources = ARRAY_SIZE(sm_resource),
2525 +
2526 +static struct resource at32ap700x_rtc0_resource[] = {
2527 + {
2528 + .start = 0xfff00080,
2529 + .end = 0xfff000af,
2530 + .flags = IORESOURCE_MEM,
2531 + },
2532 + IRQ(21),
2533 +};
2534 +
2535 +static struct resource at32_wdt0_resource[] = {
2536 + {
2537 + .start = 0xfff000b0,
2538 + .end = 0xfff000bf,
2539 + .flags = IORESOURCE_MEM,
2540 + },
2541 +};
2542 +
2543 +static struct resource at32_eic0_resource[] = {
2544 + {
2545 + .start = 0xfff00100,
2546 + .end = 0xfff0013f,
2547 + .flags = IORESOURCE_MEM,
2548 + },
2549 + IRQ(19),
2550 };
2551 -static struct clk at32_sm_pclk = {
2552 +
2553 +DEFINE_DEV(at32_pm, 0);
2554 +DEFINE_DEV(at32ap700x_rtc, 0);
2555 +DEFINE_DEV(at32_wdt, 0);
2556 +DEFINE_DEV(at32_eic, 0);
2557 +
2558 +/*
2559 + * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
2560 + * is always running.
2561 + */
2562 +static struct clk at32_pm_pclk = {
2563 .name = "pclk",
2564 - .dev = &at32_sm_device.dev,
2565 + .dev = &at32_pm0_device.dev,
2566 .parent = &pbb_clk,
2567 .mode = pbb_clk_mode,
2568 .get_rate = pbb_clk_get_rate,
2569 @@ -491,6 +562,17 @@
2570 .users = 1,
2571 };
2572
2573 +static struct resource dmaca0_resource[] = {
2574 + {
2575 + .start = 0xff200000,
2576 + .end = 0xff20ffff,
2577 + .flags = IORESOURCE_MEM,
2578 + },
2579 + IRQ(2),
2580 +};
2581 +DEFINE_DEV(dmaca, 0);
2582 +DEV_CLK(hclk, dmaca0, hsb, 10);
2583 +
2584 /* --------------------------------------------------------------------
2585 * HMATRIX
2586 * -------------------------------------------------------------------- */
2587 @@ -583,12 +665,14 @@
2588
2589 void __init at32_add_system_devices(void)
2590 {
2591 - system_manager.eim_first_irq = EIM_IRQ_BASE;
2592 -
2593 - platform_device_register(&at32_sm_device);
2594 + platform_device_register(&at32_pm0_device);
2595 platform_device_register(&at32_intc0_device);
2596 + platform_device_register(&at32ap700x_rtc0_device);
2597 + platform_device_register(&at32_wdt0_device);
2598 + platform_device_register(&at32_eic0_device);
2599 platform_device_register(&smc0_device);
2600 platform_device_register(&pdc_device);
2601 + platform_device_register(&dmaca0_device);
2602
2603 platform_device_register(&at32_systc0_device);
2604
2605 @@ -894,6 +978,83 @@
2606 }
2607
2608 /* --------------------------------------------------------------------
2609 + * TWI
2610 + * -------------------------------------------------------------------- */
2611 +
2612 +static struct resource atmel_twi0_resource[] = {
2613 + PBMEM(0xffe00800),
2614 + IRQ(5),
2615 +};
2616 +DEFINE_DEV(atmel_twi, 0);
2617 +DEV_CLK(pclk,atmel_twi0,pba,2);
2618 +
2619 +struct platform_device *__init
2620 +at32_add_device_twi(unsigned int id)
2621 +{
2622 + struct platform_device *pdev;
2623 +
2624 + switch (id) {
2625 + case 0:
2626 + pdev = &atmel_twi0_device;
2627 + select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
2628 + select_peripheral(PA(7), PERIPH_A, 0); /* SCL */
2629 + break;
2630 +
2631 + default:
2632 + return NULL;
2633 + }
2634 +
2635 + platform_device_register(pdev);
2636 + return pdev;
2637 +}
2638 +
2639 +/* --------------------------------------------------------------------
2640 + * MMC
2641 + * -------------------------------------------------------------------- */
2642 +static struct mci_platform_data atmel_mci0_data = {
2643 + .detect_pin = GPIO_PIN_NONE,
2644 + .wp_pin = GPIO_PIN_NONE,
2645 +};
2646 +static struct resource atmel_mci0_resource[] = {
2647 + PBMEM(0xfff02400),
2648 + IRQ(28),
2649 +};
2650 +DEFINE_DEV_DATA(atmel_mci, 0);
2651 +DEV_CLK(mci_clk, atmel_mci0, pbb, 9);
2652 +
2653 +struct platform_device *__init
2654 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
2655 +{
2656 + struct platform_device *pdev;
2657 +
2658 + switch (id) {
2659 + case 0:
2660 + pdev = &atmel_mci0_device;
2661 + select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
2662 + select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
2663 + select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
2664 + select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
2665 + select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
2666 + select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
2667 + break;
2668 + default:
2669 + return NULL;
2670 + }
2671 +
2672 + if (data) {
2673 + if (data->detect_pin != GPIO_PIN_NONE)
2674 + at32_select_gpio(data->detect_pin, 0);
2675 + if (data->wp_pin != GPIO_PIN_NONE)
2676 + at32_select_gpio(data->wp_pin, 0);
2677 + memcpy(pdev->dev.platform_data, data,
2678 + sizeof(struct mci_platform_data));
2679 + }
2680 +
2681 + platform_device_register(pdev);
2682 + return pdev;
2683 +}
2684 +
2685 +/* --------------------------------------------------------------------
2686 * LCDC
2687 * -------------------------------------------------------------------- */
2688 static struct atmel_lcdfb_info atmel_lcdfb0_data;
2689 @@ -1013,6 +1174,228 @@
2690 }
2691
2692 /* --------------------------------------------------------------------
2693 + * USB Device Controller
2694 + * -------------------------------------------------------------------- */
2695 +static struct resource usba0_resource[] __initdata = {
2696 + {
2697 + .name = "fifo",
2698 + .start = 0xff300000,
2699 + .end = 0xff3fffff,
2700 + .flags = IORESOURCE_MEM,
2701 + }, {
2702 + .name = "regs",
2703 + .start = 0xfff03000,
2704 + .end = 0xfff033ff,
2705 + .flags = IORESOURCE_MEM,
2706 + },
2707 + IRQ(31),
2708 +};
2709 +static struct clk usba0_pclk = {
2710 + .name = "pclk",
2711 + .parent = &pbb_clk,
2712 + .mode = pbb_clk_mode,
2713 + .get_rate = pbb_clk_get_rate,
2714 + .index = 12,
2715 +};
2716 +static struct clk usba0_hclk = {
2717 + .name = "hclk",
2718 + .parent = &hsb_clk,
2719 + .mode = hsb_clk_mode,
2720 + .get_rate = hsb_clk_get_rate,
2721 + .index = 6,
2722 +};
2723 +
2724 +struct platform_device *__init
2725 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
2726 +{
2727 + struct platform_device *pdev;
2728 +
2729 + if (id != 0)
2730 + return NULL;
2731 +
2732 + pdev = platform_device_alloc("atmel_usba_udc", 0);
2733 + if (!pdev)
2734 + return NULL;
2735 +
2736 + if (platform_device_add_resources(pdev, usba0_resource,
2737 + ARRAY_SIZE(usba0_resource)))
2738 + goto out_free_pdev;
2739 +
2740 + if (data) {
2741 + if (platform_device_add_data(pdev, data, sizeof(*data)))
2742 + goto out_free_pdev;
2743 +
2744 + if (data->vbus_pin != GPIO_PIN_NONE)
2745 + at32_select_gpio(data->vbus_pin, 0);
2746 + }
2747 +
2748 + usba0_pclk.dev = &pdev->dev;
2749 + usba0_hclk.dev = &pdev->dev;
2750 +
2751 + platform_device_add(pdev);
2752 +
2753 + return pdev;
2754 +
2755 +out_free_pdev:
2756 + platform_device_put(pdev);
2757 + return NULL;
2758 +}
2759 +
2760 +/* --------------------------------------------------------------------
2761 + * SSC
2762 + * -------------------------------------------------------------------- */
2763 +static struct resource ssc0_resource[] = {
2764 + PBMEM(0xffe01c00),
2765 + IRQ(10),
2766 +};
2767 +DEFINE_DEV(ssc, 0);
2768 +DEV_CLK(pclk, ssc0, pba, 7);
2769 +
2770 +static struct resource ssc1_resource[] = {
2771 + PBMEM(0xffe02000),
2772 + IRQ(11),
2773 +};
2774 +DEFINE_DEV(ssc, 1);
2775 +DEV_CLK(pclk, ssc1, pba, 8);
2776 +
2777 +static struct resource ssc2_resource[] = {
2778 + PBMEM(0xffe02400),
2779 + IRQ(12),
2780 +};
2781 +DEFINE_DEV(ssc, 2);
2782 +DEV_CLK(pclk, ssc2, pba, 9);
2783 +
2784 +struct platform_device *__init
2785 +at32_add_device_ssc(unsigned int id, unsigned int flags)
2786 +{
2787 + struct platform_device *pdev;
2788 +
2789 + switch (id) {
2790 + case 0:
2791 + pdev = &ssc0_device;
2792 + if (flags & ATMEL_SSC_RF)
2793 + select_peripheral(PA(21), PERIPH_A, 0); /* RF */
2794 + if (flags & ATMEL_SSC_RK)
2795 + select_peripheral(PA(22), PERIPH_A, 0); /* RK */
2796 + if (flags & ATMEL_SSC_TK)
2797 + select_peripheral(PA(23), PERIPH_A, 0); /* TK */
2798 + if (flags & ATMEL_SSC_TF)
2799 + select_peripheral(PA(24), PERIPH_A, 0); /* TF */
2800 + if (flags & ATMEL_SSC_TD)
2801 + select_peripheral(PA(25), PERIPH_A, 0); /* TD */
2802 + if (flags & ATMEL_SSC_RD)
2803 + select_peripheral(PA(26), PERIPH_A, 0); /* RD */
2804 + break;
2805 + case 1:
2806 + pdev = &ssc1_device;
2807 + if (flags & ATMEL_SSC_RF)
2808 + select_peripheral(PA(0), PERIPH_B, 0); /* RF */
2809 + if (flags & ATMEL_SSC_RK)
2810 + select_peripheral(PA(1), PERIPH_B, 0); /* RK */
2811 + if (flags & ATMEL_SSC_TK)
2812 + select_peripheral(PA(2), PERIPH_B, 0); /* TK */
2813 + if (flags & ATMEL_SSC_TF)
2814 + select_peripheral(PA(3), PERIPH_B, 0); /* TF */
2815 + if (flags & ATMEL_SSC_TD)
2816 + select_peripheral(PA(4), PERIPH_B, 0); /* TD */
2817 + if (flags & ATMEL_SSC_RD)
2818 + select_peripheral(PA(5), PERIPH_B, 0); /* RD */
2819 + break;
2820 + case 2:
2821 + pdev = &ssc2_device;
2822 + if (flags & ATMEL_SSC_TD)
2823 + select_peripheral(PB(13), PERIPH_A, 0); /* TD */
2824 + if (flags & ATMEL_SSC_RD)
2825 + select_peripheral(PB(14), PERIPH_A, 0); /* RD */
2826 + if (flags & ATMEL_SSC_TK)
2827 + select_peripheral(PB(15), PERIPH_A, 0); /* TK */
2828 + if (flags & ATMEL_SSC_TF)
2829 + select_peripheral(PB(16), PERIPH_A, 0); /* TF */
2830 + if (flags & ATMEL_SSC_RF)
2831 + select_peripheral(PB(17), PERIPH_A, 0); /* RF */
2832 + if (flags & ATMEL_SSC_RK)
2833 + select_peripheral(PB(18), PERIPH_A, 0); /* RK */
2834 + break;
2835 + default:
2836 + return NULL;
2837 + }
2838 +
2839 + platform_device_register(pdev);
2840 + return pdev;
2841 +}
2842 +
2843 +/* --------------------------------------------------------------------
2844 + * AC97C
2845 + * -------------------------------------------------------------------- */
2846 +static struct resource atmel_ac97c0_resource[] = {
2847 + PBMEM(0xfff02800),
2848 + IRQ(29),
2849 +};
2850 +DEFINE_DEV(atmel_ac97c, 0);
2851 +DEV_CLK(pclk, atmel_ac97c0, pbb, 10);
2852 +
2853 +struct platform_device *__init
2854 +at32_add_device_ac97c(unsigned int id)
2855 +{
2856 + struct platform_device *pdev;
2857 +
2858 + switch (id) {
2859 + case 0:
2860 + pdev = &atmel_ac97c0_device;
2861 + select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
2862 + select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
2863 + select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
2864 + select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
2865 + break;
2866 + default:
2867 + return NULL;
2868 + }
2869 +
2870 + platform_device_register(pdev);
2871 + return pdev;
2872 +}
2873 +
2874 +/* --------------------------------------------------------------------
2875 + * DAC
2876 + * -------------------------------------------------------------------- */
2877 +static struct resource abdac0_resource[] = {
2878 + PBMEM(0xfff02000),
2879 + IRQ(27),
2880 +};
2881 +DEFINE_DEV(abdac, 0);
2882 +DEV_CLK(pclk, abdac0, pbb, 8);
2883 +static struct clk abdac0_sample_clk = {
2884 + .name = "sample_clk",
2885 + .dev = &abdac0_device.dev,
2886 + .mode = genclk_mode,
2887 + .get_rate = genclk_get_rate,
2888 + .set_rate = genclk_set_rate,
2889 + .set_parent = genclk_set_parent,
2890 + .index = 6,
2891 +};
2892 +
2893 +struct platform_device *__init
2894 +at32_add_device_abdac(unsigned int id)
2895 +{
2896 + struct platform_device *pdev;
2897 +
2898 + switch (id) {
2899 + case 0:
2900 + pdev = &abdac0_device;
2901 + select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
2902 + select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
2903 + select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
2904 + select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
2905 + break;
2906 + default:
2907 + return NULL;
2908 + }
2909 +
2910 + platform_device_register(pdev);
2911 + return pdev;
2912 +}
2913 +
2914 +/* --------------------------------------------------------------------
2915 * GCLK
2916 * -------------------------------------------------------------------- */
2917 static struct clk gclk0 = {
2918 @@ -1066,7 +1449,7 @@
2919 &hsb_clk,
2920 &pba_clk,
2921 &pbb_clk,
2922 - &at32_sm_pclk,
2923 + &at32_pm_pclk,
2924 &at32_intc0_pclk,
2925 &hmatrix_clk,
2926 &ebi_clk,
2927 @@ -1075,6 +1458,7 @@
2928 &smc0_mck,
2929 &pdc_hclk,
2930 &pdc_pclk,
2931 + &dmaca0_hclk,
2932 &pico_clk,
2933 &pio0_mck,
2934 &pio1_mck,
2935 @@ -1092,8 +1476,18 @@
2936 &macb1_pclk,
2937 &atmel_spi0_spi_clk,
2938 &atmel_spi1_spi_clk,
2939 + &atmel_twi0_pclk,
2940 + &atmel_mci0_mci_clk,
2941 &atmel_lcdfb0_hck1,
2942 &atmel_lcdfb0_pixclk,
2943 + &usba0_pclk,
2944 + &usba0_hclk,
2945 + &ssc0_pclk,
2946 + &ssc1_pclk,
2947 + &ssc2_pclk,
2948 + &atmel_ac97c0_pclk,
2949 + &abdac0_pclk,
2950 + &abdac0_sample_clk,
2951 &gclk0,
2952 &gclk1,
2953 &gclk2,
2954 @@ -1113,18 +1507,20 @@
2955
2956 void __init at32_clock_init(void)
2957 {
2958 - struct at32_sm *sm = &system_manager;
2959 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2960 int i;
2961
2962 - if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
2963 + if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2964 main_clock = &pll0;
2965 - else
2966 + cpu_clk.parent = &pll0;
2967 + } else {
2968 main_clock = &osc0;
2969 + cpu_clk.parent = &osc0;
2970 + }
2971
2972 - if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
2973 + if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2974 pll0.parent = &osc1;
2975 - if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
2976 + if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2977 pll1.parent = &osc1;
2978
2979 genclk_init_parent(&gclk0);
2980 @@ -1133,6 +1529,7 @@
2981 genclk_init_parent(&gclk3);
2982 genclk_init_parent(&gclk4);
2983 genclk_init_parent(&atmel_lcdfb0_pixclk);
2984 + genclk_init_parent(&abdac0_sample_clk);
2985
2986 /*
2987 * Turn on all clocks that have at least one user already, and
2988 @@ -1157,8 +1554,8 @@
2989 pbb_mask |= 1 << clk->index;
2990 }
2991
2992 - sm_writel(sm, PM_CPU_MASK, cpu_mask);
2993 - sm_writel(sm, PM_HSB_MASK, hsb_mask);
2994 - sm_writel(sm, PM_PBA_MASK, pba_mask);
2995 - sm_writel(sm, PM_PBB_MASK, pbb_mask);
2996 + pm_writel(CPU_MASK, cpu_mask);
2997 + pm_writel(HSB_MASK, hsb_mask);
2998 + pm_writel(PBA_MASK, pba_mask);
2999 + pm_writel(PBB_MASK, pbb_mask);
3000 }
3001 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap.c linux-avr32.git/arch/avr32/mach-at32ap/at32ap.c
3002 --- linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap.c 2007-07-10 20:56:30.000000000 +0200
3003 +++ linux-avr32.git/arch/avr32/mach-at32ap/at32ap.c 2007-07-12 13:59:49.000000000 +0200
3004 @@ -11,41 +11,10 @@
3005 #include <linux/init.h>
3006 #include <linux/platform_device.h>
3007
3008 -#include <asm/io.h>
3009 -
3010 #include <asm/arch/init.h>
3011 -#include <asm/arch/sm.h>
3012 -
3013 -struct at32_sm system_manager;
3014 -
3015 -static int __init at32_sm_init(void)
3016 -{
3017 - struct resource *regs;
3018 - struct at32_sm *sm = &system_manager;
3019 - int ret = -ENXIO;
3020 -
3021 - regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
3022 - if (!regs)
3023 - goto fail;
3024 -
3025 - spin_lock_init(&sm->lock);
3026 - sm->pdev = &at32_sm_device;
3027 -
3028 - ret = -ENOMEM;
3029 - sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
3030 - if (!sm->regs)
3031 - goto fail;
3032 -
3033 - return 0;
3034 -
3035 -fail:
3036 - printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
3037 - return ret;
3038 -}
3039
3040 void __init setup_platform(void)
3041 {
3042 - at32_sm_init();
3043 at32_clock_init();
3044 at32_portmux_init();
3045 }
3046 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/cpufreq.c linux-avr32.git/arch/avr32/mach-at32ap/cpufreq.c
3047 --- linux-2.6.22.1/arch/avr32/mach-at32ap/cpufreq.c 1970-01-01 01:00:00.000000000 +0100
3048 +++ linux-avr32.git/arch/avr32/mach-at32ap/cpufreq.c 2007-07-12 13:59:49.000000000 +0200
3049 @@ -0,0 +1,112 @@
3050 +/*
3051 + * Copyright (C) 2004-2007 Atmel Corporation
3052 + *
3053 + * Based on MIPS implementation arch/mips/kernel/time.c
3054 + * Copyright 2001 MontaVista Software Inc.
3055 + *
3056 + * This program is free software; you can redistribute it and/or modify
3057 + * it under the terms of the GNU General Public License version 2 as
3058 + * published by the Free Software Foundation.
3059 + */
3060 +
3061 +/*#define DEBUG*/
3062 +
3063 +#include <linux/kernel.h>
3064 +#include <linux/types.h>
3065 +#include <linux/init.h>
3066 +#include <linux/cpufreq.h>
3067 +#include <linux/io.h>
3068 +#include <linux/clk.h>
3069 +#include <linux/err.h>
3070 +#include <asm/system.h>
3071 +
3072 +static struct clk *cpuclk;
3073 +
3074 +static int at32_verify_speed(struct cpufreq_policy *policy)
3075 +{
3076 + if (policy->cpu != 0)
3077 + return -EINVAL;
3078 +
3079 + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
3080 + policy->cpuinfo.max_freq);
3081 + return 0;
3082 +}
3083 +
3084 +static unsigned int at32_get_speed(unsigned int cpu)
3085 +{
3086 + /* No SMP support */
3087 + if (cpu)
3088 + return 0;
3089 + return (unsigned int)((clk_get_rate(cpuclk) + 500) / 1000);
3090 +}
3091 +
3092 +static int at32_set_target(struct cpufreq_policy *policy,
3093 + unsigned int target_freq,
3094 + unsigned int relation)
3095 +{
3096 + struct cpufreq_freqs freqs;
3097 + long freq;
3098 +
3099 + /* Convert target_freq from kHz to Hz */
3100 + freq = clk_round_rate(cpuclk, target_freq * 1000);
3101 +
3102 + /* Check if policy->min <= new_freq <= policy->max */
3103 + if(freq < (policy->min * 1000) || freq > (policy->max * 1000))
3104 + return -EINVAL;
3105 +
3106 + pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
3107 +
3108 + freqs.old = at32_get_speed(0);
3109 + freqs.new = (freq + 500) / 1000;
3110 + freqs.cpu = 0;
3111 + freqs.flags = 0;
3112 +
3113 + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
3114 + clk_set_rate(cpuclk, freq);
3115 + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
3116 +
3117 + pr_debug("cpufreq: set frequency %lu Hz\n", freq);
3118 +
3119 + return 0;
3120 +}
3121 +
3122 +static int __init at32_cpufreq_driver_init(struct cpufreq_policy *policy)
3123 +{
3124 + if (policy->cpu != 0)
3125 + return -EINVAL;
3126 +
3127 + cpuclk = clk_get(NULL, "cpu");
3128 + if (IS_ERR(cpuclk)) {
3129 + pr_debug("cpufreq: could not get CPU clk\n");
3130 + return PTR_ERR(cpuclk);
3131 + }
3132 +
3133 + policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000;
3134 + policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
3135 + policy->cpuinfo.transition_latency = 0;
3136 + policy->cur = at32_get_speed(0);
3137 + policy->min = policy->cpuinfo.min_freq;
3138 + policy->max = policy->cpuinfo.max_freq;
3139 + policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
3140 +
3141 + printk("cpufreq: AT32AP CPU frequency driver\n");
3142 +
3143 + return 0;
3144 +}
3145 +
3146 +static struct cpufreq_driver at32_driver = {
3147 + .name = "at32ap",
3148 + .owner = THIS_MODULE,
3149 + .init = at32_cpufreq_driver_init,
3150 + .verify = at32_verify_speed,
3151 + .target = at32_set_target,
3152 + .get = at32_get_speed,
3153 + .flags = CPUFREQ_STICKY,
3154 +};
3155 +
3156 +static int __init at32_cpufreq_init(void)
3157 +{
3158 + return cpufreq_register_driver(&at32_driver);
3159 +}
3160 +
3161 +arch_initcall(at32_cpufreq_init);
3162 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/extint.c linux-avr32.git/arch/avr32/mach-at32ap/extint.c
3163 --- linux-2.6.22.1/arch/avr32/mach-at32ap/extint.c 2007-07-10 20:56:30.000000000 +0200
3164 +++ linux-avr32.git/arch/avr32/mach-at32ap/extint.c 2007-07-12 13:59:49.000000000 +0200
3165 @@ -17,42 +17,83 @@
3166
3167 #include <asm/io.h>
3168
3169 -#include <asm/arch/sm.h>
3170 -
3171 -#include "sm.h"
3172 +/* EIC register offsets */
3173 +#define EIC_IER 0x0000
3174 +#define EIC_IDR 0x0004
3175 +#define EIC_IMR 0x0008
3176 +#define EIC_ISR 0x000c
3177 +#define EIC_ICR 0x0010
3178 +#define EIC_MODE 0x0014
3179 +#define EIC_EDGE 0x0018
3180 +#define EIC_LEVEL 0x001c
3181 +#define EIC_TEST 0x0020
3182 +#define EIC_NMIC 0x0024
3183 +
3184 +/* Bitfields in TEST */
3185 +#define EIC_TESTEN_OFFSET 31
3186 +#define EIC_TESTEN_SIZE 1
3187 +
3188 +/* Bitfields in NMIC */
3189 +#define EIC_EN_OFFSET 0
3190 +#define EIC_EN_SIZE 1
3191 +
3192 +/* Bit manipulation macros */
3193 +#define EIC_BIT(name) \
3194 + (1 << EIC_##name##_OFFSET)
3195 +#define EIC_BF(name,value) \
3196 + (((value) & ((1 << EIC_##name##_SIZE) - 1)) \
3197 + << EIC_##name##_OFFSET)
3198 +#define EIC_BFEXT(name,value) \
3199 + (((value) >> EIC_##name##_OFFSET) \
3200 + & ((1 << EIC_##name##_SIZE) - 1))
3201 +#define EIC_BFINS(name,value,old) \
3202 + (((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
3203 + << EIC_##name##_OFFSET)) \
3204 + | EIC_BF(name,value))
3205 +
3206 +/* Register access macros */
3207 +#define eic_readl(port,reg) \
3208 + __raw_readl((port)->regs + EIC_##reg)
3209 +#define eic_writel(port,reg,value) \
3210 + __raw_writel((value), (port)->regs + EIC_##reg)
3211 +
3212 +struct eic {
3213 + void __iomem *regs;
3214 + struct irq_chip *chip;
3215 + unsigned int first_irq;
3216 +};
3217
3218 -static void eim_ack_irq(unsigned int irq)
3219 +static void eic_ack_irq(unsigned int irq)
3220 {
3221 - struct at32_sm *sm = get_irq_chip_data(irq);
3222 - sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
3223 + struct eic *eic = get_irq_chip_data(irq);
3224 + eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
3225 }
3226
3227 -static void eim_mask_irq(unsigned int irq)
3228 +static void eic_mask_irq(unsigned int irq)
3229 {
3230 - struct at32_sm *sm = get_irq_chip_data(irq);
3231 - sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
3232 + struct eic *eic = get_irq_chip_data(irq);
3233 + eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
3234 }
3235
3236 -static void eim_mask_ack_irq(unsigned int irq)
3237 +static void eic_mask_ack_irq(unsigned int irq)
3238 {
3239 - struct at32_sm *sm = get_irq_chip_data(irq);
3240 - sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
3241 - sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
3242 + struct eic *eic = get_irq_chip_data(irq);
3243 + eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
3244 + eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
3245 }
3246
3247 -static void eim_unmask_irq(unsigned int irq)
3248 +static void eic_unmask_irq(unsigned int irq)
3249 {
3250 - struct at32_sm *sm = get_irq_chip_data(irq);
3251 - sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
3252 + struct eic *eic = get_irq_chip_data(irq);
3253 + eic_writel(eic, IER, 1 << (irq - eic->first_irq));
3254 }
3255
3256 -static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
3257 +static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
3258 {
3259 - struct at32_sm *sm = get_irq_chip_data(irq);
3260 + struct eic *eic = get_irq_chip_data(irq);
3261 struct irq_desc *desc;
3262 - unsigned int i = irq - sm->eim_first_irq;
3263 + unsigned int i = irq - eic->first_irq;
3264 u32 mode, edge, level;
3265 - unsigned long flags;
3266 int ret = 0;
3267
3268 flow_type &= IRQ_TYPE_SENSE_MASK;
3269 @@ -60,11 +101,10 @@
3270 flow_type = IRQ_TYPE_LEVEL_LOW;
3271
3272 desc = &irq_desc[irq];
3273 - spin_lock_irqsave(&sm->lock, flags);
3274
3275 - mode = sm_readl(sm, EIM_MODE);
3276 - edge = sm_readl(sm, EIM_EDGE);
3277 - level = sm_readl(sm, EIM_LEVEL);
3278 + mode = eic_readl(eic, MODE);
3279 + edge = eic_readl(eic, EDGE);
3280 + level = eic_readl(eic, LEVEL);
3281
3282 switch (flow_type) {
3283 case IRQ_TYPE_LEVEL_LOW:
3284 @@ -89,9 +129,9 @@
3285 }
3286
3287 if (ret == 0) {
3288 - sm_writel(sm, EIM_MODE, mode);
3289 - sm_writel(sm, EIM_EDGE, edge);
3290 - sm_writel(sm, EIM_LEVEL, level);
3291 + eic_writel(eic, MODE, mode);
3292 + eic_writel(eic, EDGE, edge);
3293 + eic_writel(eic, LEVEL, level);
3294
3295 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
3296 flow_type |= IRQ_LEVEL;
3297 @@ -99,35 +139,33 @@
3298 desc->status |= flow_type;
3299 }
3300
3301 - spin_unlock_irqrestore(&sm->lock, flags);
3302 -
3303 return ret;
3304 }
3305
3306 -struct irq_chip eim_chip = {
3307 - .name = "eim",
3308 - .ack = eim_ack_irq,
3309 - .mask = eim_mask_irq,
3310 - .mask_ack = eim_mask_ack_irq,
3311 - .unmask = eim_unmask_irq,
3312 - .set_type = eim_set_irq_type,
3313 +struct irq_chip eic_chip = {
3314 + .name = "eic",
3315 + .ack = eic_ack_irq,
3316 + .mask = eic_mask_irq,
3317 + .mask_ack = eic_mask_ack_irq,
3318 + .unmask = eic_unmask_irq,
3319 + .set_type = eic_set_irq_type,
3320 };
3321
3322 -static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
3323 +static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
3324 {
3325 - struct at32_sm *sm = desc->handler_data;
3326 + struct eic *eic = desc->handler_data;
3327 struct irq_desc *ext_desc;
3328 unsigned long status, pending;
3329 unsigned int i, ext_irq;
3330
3331 - status = sm_readl(sm, EIM_ISR);
3332 - pending = status & sm_readl(sm, EIM_IMR);
3333 + status = eic_readl(eic, ISR);
3334 + pending = status & eic_readl(eic, IMR);
3335
3336 while (pending) {
3337 i = fls(pending) - 1;
3338 pending &= ~(1 << i);
3339
3340 - ext_irq = i + sm->eim_first_irq;
3341 + ext_irq = i + eic->first_irq;
3342 ext_desc = irq_desc + ext_irq;
3343 if (ext_desc->status & IRQ_LEVEL)
3344 handle_level_irq(ext_irq, ext_desc);
3345 @@ -136,51 +174,85 @@
3346 }
3347 }
3348
3349 -static int __init eim_init(void)
3350 +static int __init eic_probe(struct platform_device *pdev)
3351 {
3352 - struct at32_sm *sm = &system_manager;
3353 + struct eic *eic;
3354 + struct resource *regs;
3355 unsigned int i;
3356 unsigned int nr_irqs;
3357 unsigned int int_irq;
3358 + int ret;
3359 u32 pattern;
3360
3361 - /*
3362 - * The EIM is really the same module as SM, so register
3363 - * mapping, etc. has been taken care of already.
3364 - */
3365 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3366 + int_irq = platform_get_irq(pdev, 0);
3367 + if (!regs || !int_irq) {
3368 + dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
3369 + return -ENXIO;
3370 + }
3371 +
3372 + ret = -ENOMEM;
3373 + eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
3374 + if (!eic) {
3375 + dev_dbg(&pdev->dev, "no memory for eic structure\n");
3376 + goto err_kzalloc;
3377 + }
3378 +
3379 + eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
3380 + eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
3381 + if (!eic->regs) {
3382 + dev_dbg(&pdev->dev, "failed to map regs\n");
3383 + goto err_ioremap;
3384 + }
3385
3386 /*
3387 * Find out how many interrupt lines that are actually
3388 * implemented in hardware.
3389 */
3390 - sm_writel(sm, EIM_IDR, ~0UL);
3391 - sm_writel(sm, EIM_MODE, ~0UL);
3392 - pattern = sm_readl(sm, EIM_MODE);
3393 + eic_writel(eic, IDR, ~0UL);
3394 + eic_writel(eic, MODE, ~0UL);
3395 + pattern = eic_readl(eic, MODE);
3396 nr_irqs = fls(pattern);
3397
3398 /* Trigger on falling edge unless overridden by driver */
3399 - sm_writel(sm, EIM_MODE, 0UL);
3400 - sm_writel(sm, EIM_EDGE, 0UL);
3401 + eic_writel(eic, MODE, 0UL);
3402 + eic_writel(eic, EDGE, 0UL);
3403
3404 - sm->eim_chip = &eim_chip;
3405 + eic->chip = &eic_chip;
3406
3407 for (i = 0; i < nr_irqs; i++) {
3408 /* NOTE the handler we set here is ignored by the demux */
3409 - set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
3410 + set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
3411 handle_level_irq);
3412 - set_irq_chip_data(sm->eim_first_irq + i, sm);
3413 + set_irq_chip_data(eic->first_irq + i, eic);
3414 }
3415
3416 - int_irq = platform_get_irq_byname(sm->pdev, "eim");
3417 -
3418 - set_irq_chained_handler(int_irq, demux_eim_irq);
3419 - set_irq_data(int_irq, sm);
3420 + set_irq_chained_handler(int_irq, demux_eic_irq);
3421 + set_irq_data(int_irq, eic);
3422
3423 - printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
3424 - sm->regs, int_irq);
3425 - printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
3426 - nr_irqs, sm->eim_first_irq);
3427 + dev_info(&pdev->dev,
3428 + "External Interrupt Controller at 0x%p, IRQ %u\n",
3429 + eic->regs, int_irq);
3430 + dev_info(&pdev->dev,
3431 + "Handling %u external IRQs, starting with IRQ %u\n",
3432 + nr_irqs, eic->first_irq);
3433
3434 return 0;
3435 +
3436 +err_ioremap:
3437 + kfree(eic);
3438 +err_kzalloc:
3439 + return ret;
3440 +}
3441 +
3442 +static struct platform_driver eic_driver = {
3443 + .driver = {
3444 + .name = "at32_eic",
3445 + },
3446 +};
3447 +
3448 +static int __init eic_init(void)
3449 +{
3450 + return platform_driver_probe(&eic_driver, eic_probe);
3451 }
3452 -arch_initcall(eim_init);
3453 +arch_initcall(eic_init);
3454 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/gpio-dev.c linux-avr32.git/arch/avr32/mach-at32ap/gpio-dev.c
3455 --- linux-2.6.22.1/arch/avr32/mach-at32ap/gpio-dev.c 1970-01-01 01:00:00.000000000 +0100
3456 +++ linux-avr32.git/arch/avr32/mach-at32ap/gpio-dev.c 2007-07-12 13:59:49.000000000 +0200
3457 @@ -0,0 +1,570 @@
3458 +/*
3459 + * GPIO /dev and configfs interface
3460 + *
3461 + * Copyright (C) 2006-2007 Atmel Corporation
3462 + *
3463 + * This program is free software; you can redistribute it and/or modify
3464 + * it under the terms of the GNU General Public License version 2 as
3465 + * published by the Free Software Foundation.
3466 + */
3467 +#include <linux/configfs.h>
3468 +#include <linux/cdev.h>
3469 +#include <linux/fs.h>
3470 +#include <linux/interrupt.h>
3471 +#include <linux/poll.h>
3472 +#include <linux/uaccess.h>
3473 +#include <linux/wait.h>
3474 +
3475 +#include <asm/gpio.h>
3476 +#include <asm/arch/portmux.h>
3477 +
3478 +#define GPIO_DEV_MAX 8
3479 +
3480 +static struct class *gpio_dev_class;
3481 +static dev_t gpio_devt;
3482 +
3483 +struct gpio_item {
3484 + spinlock_t lock;
3485 +
3486 + int enabled;
3487 + int initialized;
3488 + int port;
3489 + u32 pin_mask;
3490 + u32 oe_mask;
3491 +
3492 + /* Pin state last time we read it (for blocking reads) */
3493 + u32 pin_state;
3494 + int changed;
3495 +
3496 + wait_queue_head_t change_wq;
3497 + struct fasync_struct *async_queue;
3498 +
3499 + int id;
3500 + struct class_device *gpio_dev;
3501 + struct cdev char_dev;
3502 + struct config_item item;
3503 +};
3504 +
3505 +struct gpio_attribute {
3506 + struct configfs_attribute attr;
3507 + ssize_t (*show)(struct gpio_item *, char *);
3508 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
3509 +};
3510 +
3511 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
3512 +{
3513 + struct gpio_item *gpio = dev_id;
3514 + u32 old_state, new_state;
3515 +
3516 + old_state = gpio->pin_state;
3517 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
3518 + gpio->pin_state = new_state;
3519 +
3520 + if (new_state != old_state) {
3521 + gpio->changed = 1;
3522 + wake_up_interruptible(&gpio->change_wq);
3523 +
3524 + if (gpio->async_queue)
3525 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
3526 + }
3527 +
3528 + return IRQ_HANDLED;
3529 +}
3530 +
3531 +static int gpio_dev_open(struct inode *inode, struct file *file)
3532 +{
3533 + struct gpio_item *gpio = container_of(inode->i_cdev,
3534 + struct gpio_item,
3535 + char_dev);
3536 + unsigned int irq;
3537 + unsigned int i;
3538 + int ret;
3539 +
3540 + nonseekable_open(inode, file);
3541 + config_item_get(&gpio->item);
3542 + file->private_data = gpio;
3543 +
3544 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
3545 + gpio->pin_mask);
3546 + gpio->changed = 1;
3547 +
3548 + for (i = 0; i < 32; i++) {
3549 + if (gpio->pin_mask & (1 << i)) {
3550 + irq = gpio_to_irq(32 * gpio->port + i);
3551 + ret = request_irq(irq, gpio_dev_interrupt, 0,
3552 + "gpio-dev", gpio);
3553 + if (ret)
3554 + goto err_irq;
3555 + }
3556 + }
3557 +
3558 + return 0;
3559 +
3560 +err_irq:
3561 + while (i--) {
3562 + if (gpio->pin_mask & (1 << i)) {
3563 + irq = gpio_to_irq(32 * gpio->port + i);
3564 + free_irq(irq, gpio);
3565 + }
3566 + }
3567 +
3568 + config_item_put(&gpio->item);
3569 +
3570 + return ret;
3571 +}
3572 +
3573 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
3574 +{
3575 + struct gpio_item *gpio = file->private_data;
3576 +
3577 + return fasync_helper(fd, file, mode, &gpio->async_queue);
3578 +}
3579 +
3580 +static int gpio_dev_release(struct inode *inode, struct file *file)
3581 +{
3582 + struct gpio_item *gpio = file->private_data;
3583 + unsigned int irq;
3584 + unsigned int i;
3585 +
3586 + gpio_dev_fasync(-1, file, 0);
3587 +
3588 + for (i = 0; i < 32; i++) {
3589 + if (gpio->pin_mask & (1 << i)) {
3590 + irq = gpio_to_irq(32 * gpio->port + i);
3591 + free_irq(irq, gpio);
3592 + }
3593 + }
3594 +
3595 + config_item_put(&gpio->item);
3596 +
3597 + return 0;
3598 +}
3599 +
3600 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
3601 +{
3602 + struct gpio_item *gpio = file->private_data;
3603 + unsigned int mask = 0;
3604 +
3605 + poll_wait(file, &gpio->change_wq, wait);
3606 + if (gpio->changed)
3607 + mask |= POLLIN | POLLRDNORM;
3608 +
3609 + return mask;
3610 +}
3611 +
3612 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
3613 + size_t count, loff_t *offset)
3614 +{
3615 + struct gpio_item *gpio = file->private_data;
3616 + u32 value;
3617 +
3618 + spin_lock_irq(&gpio->lock);
3619 + while (!gpio->changed) {
3620 + spin_unlock_irq(&gpio->lock);
3621 +
3622 + if (file->f_flags & O_NONBLOCK)
3623 + return -EAGAIN;
3624 +
3625 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
3626 + return -ERESTARTSYS;
3627 +
3628 + spin_lock_irq(&gpio->lock);
3629 + }
3630 +
3631 + gpio->changed = 0;
3632 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
3633 +
3634 + spin_unlock_irq(&gpio->lock);
3635 +
3636 + count = min(count, (size_t)4);
3637 + if (copy_to_user(buf, &value, count))
3638 + return -EFAULT;
3639 +
3640 + return count;
3641 +}
3642 +
3643 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
3644 + size_t count, loff_t *offset)
3645 +{
3646 + struct gpio_item *gpio = file->private_data;
3647 + u32 value = 0;
3648 + u32 mask = ~0UL;
3649 +
3650 + count = min(count, (size_t)4);
3651 + if (copy_from_user(&value, buf, count))
3652 + return -EFAULT;
3653 +
3654 + /* Assuming big endian */
3655 + mask <<= (4 - count) * 8;
3656 + mask &= gpio->pin_mask;
3657 +
3658 + at32_gpio_set_value_multiple(gpio->port, value, mask);
3659 +
3660 + return count;
3661 +}
3662 +
3663 +static struct file_operations gpio_dev_fops = {
3664 + .owner = THIS_MODULE,
3665 + .llseek = no_llseek,
3666 + .open = gpio_dev_open,
3667 + .release = gpio_dev_release,
3668 + .fasync = gpio_dev_fasync,
3669 + .poll = gpio_dev_poll,
3670 + .read = gpio_dev_read,
3671 + .write = gpio_dev_write,
3672 +};
3673 +
3674 +static struct gpio_item *to_gpio_item(struct config_item *item)
3675 +{
3676 + return item ? container_of(item, struct gpio_item, item) : NULL;
3677 +}
3678 +
3679 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
3680 +{
3681 + return sprintf(page, "%d\n", gpio->port);
3682 +}
3683 +
3684 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
3685 + const char *page, size_t count)
3686 +{
3687 + unsigned long id;
3688 + char *p = (char *)page;
3689 + ssize_t ret = -EINVAL;
3690 +
3691 + id = simple_strtoul(p, &p, 0);
3692 + if (!p || (*p && (*p != '\n')))
3693 + return -EINVAL;
3694 +
3695 + /* Switching PIO is not allowed when live... */
3696 + spin_lock(&gpio->lock);
3697 + if (!gpio->enabled) {
3698 + ret = -ENXIO;
3699 + if (at32_gpio_port_is_valid(id)) {
3700 + gpio->port = id;
3701 + ret = count;
3702 + }
3703 + }
3704 + spin_unlock(&gpio->lock);
3705 +
3706 + return ret;
3707 +}
3708 +
3709 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
3710 +{
3711 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
3712 +}
3713 +
3714 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
3715 + const char *page, size_t count)
3716 +{
3717 + u32 new_mask;
3718 + char *p = (char *)page;
3719 + ssize_t ret = -EINVAL;
3720 +
3721 + new_mask = simple_strtoul(p, &p, 0);
3722 + if (!p || (*p && (*p != '\n')))
3723 + return -EINVAL;
3724 +
3725 + /* Can't update the pin mask while live. */
3726 + spin_lock(&gpio->lock);
3727 + if (!gpio->enabled) {
3728 + gpio->oe_mask &= new_mask;
3729 + gpio->pin_mask = new_mask;
3730 + ret = count;
3731 + }
3732 + spin_unlock(&gpio->lock);
3733 +
3734 + return ret;
3735 +}
3736 +
3737 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
3738 +{
3739 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
3740 +}
3741 +
3742 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
3743 + const char *page, size_t count)
3744 +{
3745 + u32 mask;
3746 + char *p = (char *)page;
3747 + ssize_t ret = -EINVAL;
3748 +
3749 + mask = simple_strtoul(p, &p, 0);
3750 + if (!p || (*p && (*p != '\n')))
3751 + return -EINVAL;
3752 +
3753 + spin_lock(&gpio->lock);
3754 + if (!gpio->enabled) {
3755 + gpio->oe_mask = mask & gpio->pin_mask;
3756 + ret = count;
3757 + }
3758 + spin_unlock(&gpio->lock);
3759 +
3760 + return ret;
3761 +}
3762 +
3763 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
3764 +{
3765 + return sprintf(page, "%d\n", gpio->enabled);
3766 +}
3767 +
3768 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
3769 + const char *page, size_t count)
3770 +{
3771 + char *p = (char *)page;
3772 + int enabled;
3773 + int ret;
3774 +
3775 + enabled = simple_strtoul(p, &p, 0);
3776 + if (!p || (*p && (*p != '\n')))
3777 + return -EINVAL;
3778 +
3779 + /* make it a boolean value */
3780 + enabled = !!enabled;
3781 +
3782 + if (gpio->enabled == enabled)
3783 + /* No change; do nothing. */
3784 + return count;
3785 +
3786 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
3787 +
3788 + if (!enabled) {
3789 + class_device_unregister(gpio->gpio_dev);
3790 + cdev_del(&gpio->char_dev);
3791 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3792 + gpio->initialized = 0;
3793 + } else {
3794 + if (gpio->port < 0 || !gpio->pin_mask)
3795 + return -ENODEV;
3796 + }
3797 +
3798 + /* Disallow any updates to gpio_id or pin_mask */
3799 + spin_lock(&gpio->lock);
3800 + gpio->enabled = enabled;
3801 + spin_unlock(&gpio->lock);
3802 +
3803 + if (!enabled)
3804 + return count;
3805 +
3806 + /* Now, try to allocate the pins */
3807 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
3808 + if (ret)
3809 + goto err_alloc_pins;
3810 +
3811 + gpio->initialized = 1;
3812 +
3813 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
3814 + gpio->char_dev.owner = THIS_MODULE;
3815 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
3816 + if (ret < 0)
3817 + goto err_cdev_add;
3818 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
3819 + MKDEV(MAJOR(gpio_devt), gpio->id),
3820 + NULL,
3821 + "gpio%d", gpio->id);
3822 + if (IS_ERR(gpio->gpio_dev)) {
3823 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
3824 + ret = PTR_ERR(gpio->gpio_dev);
3825 + goto err_class_dev;
3826 + }
3827 +
3828 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
3829 + gpio->id, gpio->port, gpio->pin_mask,
3830 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
3831 +
3832 + return 0;
3833 +
3834 +err_class_dev:
3835 + cdev_del(&gpio->char_dev);
3836 +err_cdev_add:
3837 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3838 + gpio->initialized = 0;
3839 +err_alloc_pins:
3840 + spin_lock(&gpio->lock);
3841 + gpio->enabled = 0;
3842 + spin_unlock(&gpio->lock);
3843 +
3844 + return ret;
3845 +}
3846 +
3847 +static struct gpio_attribute gpio_item_attr_gpio_id = {
3848 + .attr = {
3849 + .ca_owner = THIS_MODULE,
3850 + .ca_name = "gpio_id",
3851 + .ca_mode = S_IRUGO | S_IWUSR,
3852 + },
3853 + .show = gpio_show_gpio_id,
3854 + .store = gpio_store_gpio_id,
3855 +};
3856 +static struct gpio_attribute gpio_item_attr_pin_mask = {
3857 + .attr = {
3858 + .ca_owner = THIS_MODULE,
3859 + .ca_name = "pin_mask",
3860 + .ca_mode = S_IRUGO | S_IWUSR,
3861 + },
3862 + .show = gpio_show_pin_mask,
3863 + .store = gpio_store_pin_mask,
3864 +};
3865 +static struct gpio_attribute gpio_item_attr_oe_mask = {
3866 + .attr = {
3867 + .ca_owner = THIS_MODULE,
3868 + .ca_name = "oe_mask",
3869 + .ca_mode = S_IRUGO | S_IWUSR,
3870 + },
3871 + .show = gpio_show_oe_mask,
3872 + .store = gpio_store_oe_mask,
3873 +};
3874 +static struct gpio_attribute gpio_item_attr_enabled = {
3875 + .attr = {
3876 + .ca_owner = THIS_MODULE,
3877 + .ca_name = "enabled",
3878 + .ca_mode = S_IRUGO | S_IWUSR,
3879 + },
3880 + .show = gpio_show_enabled,
3881 + .store = gpio_store_enabled,
3882 +};
3883 +
3884 +static struct configfs_attribute *gpio_item_attrs[] = {
3885 + &gpio_item_attr_gpio_id.attr,
3886 + &gpio_item_attr_pin_mask.attr,
3887 + &gpio_item_attr_oe_mask.attr,
3888 + &gpio_item_attr_enabled.attr,
3889 + NULL,
3890 +};
3891 +
3892 +static ssize_t gpio_show_attr(struct config_item *item,
3893 + struct configfs_attribute *attr,
3894 + char *page)
3895 +{
3896 + struct gpio_item *gpio_item = to_gpio_item(item);
3897 + struct gpio_attribute *gpio_attr
3898 + = container_of(attr, struct gpio_attribute, attr);
3899 + ssize_t ret = 0;
3900 +
3901 + if (gpio_attr->show)
3902 + ret = gpio_attr->show(gpio_item, page);
3903 + return ret;
3904 +}
3905 +
3906 +static ssize_t gpio_store_attr(struct config_item *item,
3907 + struct configfs_attribute *attr,
3908 + const char *page, size_t count)
3909 +{
3910 + struct gpio_item *gpio_item = to_gpio_item(item);
3911 + struct gpio_attribute *gpio_attr
3912 + = container_of(attr, struct gpio_attribute, attr);
3913 + ssize_t ret = -EINVAL;
3914 +
3915 + if (gpio_attr->store)
3916 + ret = gpio_attr->store(gpio_item, page, count);
3917 + return ret;
3918 +}
3919 +
3920 +static void gpio_release(struct config_item *item)
3921 +{
3922 + kfree(to_gpio_item(item));
3923 +}
3924 +
3925 +static struct configfs_item_operations gpio_item_ops = {
3926 + .release = gpio_release,
3927 + .show_attribute = gpio_show_attr,
3928 + .store_attribute = gpio_store_attr,
3929 +};
3930 +
3931 +static struct config_item_type gpio_item_type = {
3932 + .ct_item_ops = &gpio_item_ops,
3933 + .ct_attrs = gpio_item_attrs,
3934 + .ct_owner = THIS_MODULE,
3935 +};
3936 +
3937 +static struct config_item *gpio_make_item(struct config_group *group,
3938 + const char *name)
3939 +{
3940 + static int next_id;
3941 + struct gpio_item *gpio;
3942 +
3943 + if (next_id >= GPIO_DEV_MAX)
3944 + return NULL;
3945 +
3946 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
3947 + if (!gpio)
3948 + return NULL;
3949 +
3950 + gpio->id = next_id++;
3951 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
3952 + spin_lock_init(&gpio->lock);
3953 + init_waitqueue_head(&gpio->change_wq);
3954 +
3955 + return &gpio->item;
3956 +}
3957 +
3958 +static void gpio_drop_item(struct config_group *group,
3959 + struct config_item *item)
3960 +{
3961 + struct gpio_item *gpio = to_gpio_item(item);
3962 +
3963 + spin_lock(&gpio->lock);
3964 + if (gpio->enabled) {
3965 + class_device_unregister(gpio->gpio_dev);
3966 + cdev_del(&gpio->char_dev);
3967 + }
3968 +
3969 + if (gpio->initialized) {
3970 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3971 + gpio->initialized = 0;
3972 + gpio->enabled = 0;
3973 + }
3974 + spin_unlock(&gpio->lock);
3975 +}
3976 +
3977 +static struct configfs_group_operations gpio_group_ops = {
3978 + .make_item = gpio_make_item,
3979 + .drop_item = gpio_drop_item,
3980 +};
3981 +
3982 +static struct config_item_type gpio_group_type = {
3983 + .ct_group_ops = &gpio_group_ops,
3984 + .ct_owner = THIS_MODULE,
3985 +};
3986 +
3987 +static struct configfs_subsystem gpio_subsys = {
3988 + .su_group = {
3989 + .cg_item = {
3990 + .ci_namebuf = "gpio",
3991 + .ci_type = &gpio_group_type,
3992 + },
3993 + },
3994 +};
3995 +
3996 +static int __init gpio_dev_init(void)
3997 +{
3998 + int err;
3999 +
4000 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
4001 + if (IS_ERR(gpio_dev_class)) {
4002 + err = PTR_ERR(gpio_dev_class);
4003 + goto err_class_create;
4004 + }
4005 +
4006 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
4007 + if (err < 0)
4008 + goto err_alloc_chrdev;
4009 +
4010 + /* Configfs initialization */
4011 + config_group_init(&gpio_subsys.su_group);
4012 + init_MUTEX(&gpio_subsys.su_sem);
4013 + err = configfs_register_subsystem(&gpio_subsys);
4014 + if (err)
4015 + goto err_register_subsys;
4016 +
4017 + return 0;
4018 +
4019 +err_register_subsys:
4020 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
4021 +err_alloc_chrdev:
4022 + class_destroy(gpio_dev_class);
4023 +err_class_create:
4024 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
4025 + return err;
4026 +}
4027 +late_initcall(gpio_dev_init);
4028 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/Kconfig linux-avr32.git/arch/avr32/mach-at32ap/Kconfig
4029 --- linux-2.6.22.1/arch/avr32/mach-at32ap/Kconfig 2007-07-10 20:56:30.000000000 +0200
4030 +++ linux-avr32.git/arch/avr32/mach-at32ap/Kconfig 2007-07-12 13:59:49.000000000 +0200
4031 @@ -26,6 +26,13 @@
4032
4033 endchoice
4034
4035 +config GPIO_DEV
4036 + bool "GPIO /dev interface"
4037 + select CONFIGFS_FS
4038 + default n
4039 + help
4040 + Say `Y' to enable a /dev interface to the GPIO pins.
4041 +
4042 endmenu
4043
4044 endif # PLATFORM_AT32AP
4045 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/Makefile linux-avr32.git/arch/avr32/mach-at32ap/Makefile
4046 --- linux-2.6.22.1/arch/avr32/mach-at32ap/Makefile 2007-07-10 20:56:30.000000000 +0200
4047 +++ linux-avr32.git/arch/avr32/mach-at32ap/Makefile 2007-07-12 13:59:49.000000000 +0200
4048 @@ -1,3 +1,5 @@
4049 obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
4050 obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
4051 obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
4052 +obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
4053 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
4054 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/pio.c linux-avr32.git/arch/avr32/mach-at32ap/pio.c
4055 --- linux-2.6.22.1/arch/avr32/mach-at32ap/pio.c 2007-07-10 20:56:30.000000000 +0200
4056 +++ linux-avr32.git/arch/avr32/mach-at32ap/pio.c 2007-07-12 13:59:49.000000000 +0200
4057 @@ -158,6 +158,82 @@
4058 dump_stack();
4059 }
4060
4061 +#ifdef CONFIG_GPIO_DEV
4062 +
4063 +/* Gang allocators and accessors; used by the GPIO /dev driver */
4064 +int at32_gpio_port_is_valid(unsigned int port)
4065 +{
4066 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
4067 +}
4068 +
4069 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
4070 +{
4071 + struct pio_device *pio;
4072 + u32 old, new;
4073 +
4074 + pio = &pio_dev[port];
4075 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
4076 +
4077 + /* Try to allocate the pins */
4078 + do {
4079 + old = pio->pinmux_mask;
4080 + if (old & pins)
4081 + return -EBUSY;
4082 +
4083 + new = old | pins;
4084 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
4085 +
4086 + /* That went well, now configure the port */
4087 + pio_writel(pio, OER, oe_mask);
4088 + pio_writel(pio, PER, pins);
4089 +
4090 + return 0;
4091 +}
4092 +
4093 +void at32_deselect_pins(unsigned int port, u32 pins)
4094 +{
4095 + struct pio_device *pio;
4096 + u32 old, new;
4097 +
4098 + pio = &pio_dev[port];
4099 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
4100 +
4101 + /* Return to a "safe" mux configuration */
4102 + pio_writel(pio, PUER, pins);
4103 + pio_writel(pio, ODR, pins);
4104 +
4105 + /* Deallocate the pins */
4106 + do {
4107 + old = pio->pinmux_mask;
4108 + new = old & ~pins;
4109 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
4110 +}
4111 +
4112 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
4113 +{
4114 + struct pio_device *pio;
4115 +
4116 + pio = &pio_dev[port];
4117 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
4118 +
4119 + return pio_readl(pio, PDSR) & pins;
4120 +}
4121 +
4122 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
4123 +{
4124 + struct pio_device *pio;
4125 +
4126 + pio = &pio_dev[port];
4127 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
4128 +
4129 + /* No atomic updates for now... */
4130 + pio_writel(pio, CODR, ~value & mask);
4131 + pio_writel(pio, SODR, value & mask);
4132 +}
4133 +
4134 +#endif /* CONFIG_GPIO_DEV */
4135 +
4136 +
4137 /*--------------------------------------------------------------------------*/
4138
4139 /* GPIO API */
4140 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/pm.h linux-avr32.git/arch/avr32/mach-at32ap/pm.h
4141 --- linux-2.6.22.1/arch/avr32/mach-at32ap/pm.h 1970-01-01 01:00:00.000000000 +0100
4142 +++ linux-avr32.git/arch/avr32/mach-at32ap/pm.h 2007-07-12 13:59:49.000000000 +0200
4143 @@ -0,0 +1,112 @@
4144 +/*
4145 + * Register definitions for the Power Manager (PM)
4146 + */
4147 +#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
4148 +#define __ARCH_AVR32_MACH_AT32AP_PM_H__
4149 +
4150 +/* PM register offsets */
4151 +#define PM_MCCTRL 0x0000
4152 +#define PM_CKSEL 0x0004
4153 +#define PM_CPU_MASK 0x0008
4154 +#define PM_HSB_MASK 0x000c
4155 +#define PM_PBA_MASK 0x0010
4156 +#define PM_PBB_MASK 0x0014
4157 +#define PM_PLL0 0x0020
4158 +#define PM_PLL1 0x0024
4159 +#define PM_IER 0x0040
4160 +#define PM_IDR 0x0044
4161 +#define PM_IMR 0x0048
4162 +#define PM_ISR 0x004c
4163 +#define PM_ICR 0x0050
4164 +#define PM_GCCTRL(x) (0x0060 + 4 * (x))
4165 +#define PM_RCAUSE 0x00c0
4166 +
4167 +/* Bitfields in CKSEL */
4168 +#define PM_CPUSEL_OFFSET 0
4169 +#define PM_CPUSEL_SIZE 3
4170 +#define PM_CPUDIV_OFFSET 7
4171 +#define PM_CPUDIV_SIZE 1
4172 +#define PM_HSBSEL_OFFSET 8
4173 +#define PM_HSBSEL_SIZE 3
4174 +#define PM_HSBDIV_OFFSET 15
4175 +#define PM_HSBDIV_SIZE 1
4176 +#define PM_PBASEL_OFFSET 16
4177 +#define PM_PBASEL_SIZE 3
4178 +#define PM_PBADIV_OFFSET 23
4179 +#define PM_PBADIV_SIZE 1
4180 +#define PM_PBBSEL_OFFSET 24
4181 +#define PM_PBBSEL_SIZE 3
4182 +#define PM_PBBDIV_OFFSET 31
4183 +#define PM_PBBDIV_SIZE 1
4184 +
4185 +/* Bitfields in PLL0 */
4186 +#define PM_PLLEN_OFFSET 0
4187 +#define PM_PLLEN_SIZE 1
4188 +#define PM_PLLOSC_OFFSET 1
4189 +#define PM_PLLOSC_SIZE 1
4190 +#define PM_PLLOPT_OFFSET 2
4191 +#define PM_PLLOPT_SIZE 3
4192 +#define PM_PLLDIV_OFFSET 8
4193 +#define PM_PLLDIV_SIZE 8
4194 +#define PM_PLLMUL_OFFSET 16
4195 +#define PM_PLLMUL_SIZE 8
4196 +#define PM_PLLCOUNT_OFFSET 24
4197 +#define PM_PLLCOUNT_SIZE 6
4198 +#define PM_PLLTEST_OFFSET 31
4199 +#define PM_PLLTEST_SIZE 1
4200 +
4201 +/* Bitfields in ICR */
4202 +#define PM_LOCK0_OFFSET 0
4203 +#define PM_LOCK0_SIZE 1
4204 +#define PM_LOCK1_OFFSET 1
4205 +#define PM_LOCK1_SIZE 1
4206 +#define PM_WAKE_OFFSET 2
4207 +#define PM_WAKE_SIZE 1
4208 +#define PM_CKRDY_OFFSET 5
4209 +#define PM_CKRDY_SIZE 1
4210 +#define PM_MSKRDY_OFFSET 6
4211 +#define PM_MSKRDY_SIZE 1
4212 +
4213 +/* Bitfields in GCCTRL0 */
4214 +#define PM_OSCSEL_OFFSET 0
4215 +#define PM_OSCSEL_SIZE 1
4216 +#define PM_PLLSEL_OFFSET 1
4217 +#define PM_PLLSEL_SIZE 1
4218 +#define PM_CEN_OFFSET 2
4219 +#define PM_CEN_SIZE 1
4220 +#define PM_DIVEN_OFFSET 4
4221 +#define PM_DIVEN_SIZE 1
4222 +#define PM_DIV_OFFSET 8
4223 +#define PM_DIV_SIZE 8
4224 +
4225 +/* Bitfields in RCAUSE */
4226 +#define PM_POR_OFFSET 0
4227 +#define PM_POR_SIZE 1
4228 +#define PM_EXT_OFFSET 2
4229 +#define PM_EXT_SIZE 1
4230 +#define PM_WDT_OFFSET 3
4231 +#define PM_WDT_SIZE 1
4232 +#define PM_NTAE_OFFSET 4
4233 +#define PM_NTAE_SIZE 1
4234 +
4235 +/* Bit manipulation macros */
4236 +#define PM_BIT(name) \
4237 + (1 << PM_##name##_OFFSET)
4238 +#define PM_BF(name,value) \
4239 + (((value) & ((1 << PM_##name##_SIZE) - 1)) \
4240 + << PM_##name##_OFFSET)
4241 +#define PM_BFEXT(name,value) \
4242 + (((value) >> PM_##name##_OFFSET) \
4243 + & ((1 << PM_##name##_SIZE) - 1))
4244 +#define PM_BFINS(name,value,old)\
4245 + (((old) & ~(((1 << PM_##name##_SIZE) - 1) \
4246 + << PM_##name##_OFFSET)) \
4247 + | PM_BF(name,value))
4248 +
4249 +/* Register access macros */
4250 +#define pm_readl(reg) \
4251 + __raw_readl((void __iomem *)AT32_PM_BASE + PM_##reg)
4252 +#define pm_writel(reg,value) \
4253 + __raw_writel((value), (void __iomem *)AT32_PM_BASE + PM_##reg)
4254 +
4255 +#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
4256 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/sm.h linux-avr32.git/arch/avr32/mach-at32ap/sm.h
4257 --- linux-2.6.22.1/arch/avr32/mach-at32ap/sm.h 2007-07-10 20:56:30.000000000 +0200
4258 +++ linux-avr32.git/arch/avr32/mach-at32ap/sm.h 1970-01-01 01:00:00.000000000 +0100
4259 @@ -1,242 +0,0 @@
4260 -/*
4261 - * Register definitions for SM
4262 - *
4263 - * System Manager
4264 - */
4265 -#ifndef __ASM_AVR32_SM_H__
4266 -#define __ASM_AVR32_SM_H__
4267 -
4268 -/* SM register offsets */
4269 -#define SM_PM_MCCTRL 0x0000
4270 -#define SM_PM_CKSEL 0x0004
4271 -#define SM_PM_CPU_MASK 0x0008
4272 -#define SM_PM_HSB_MASK 0x000c
4273 -#define SM_PM_PBA_MASK 0x0010
4274 -#define SM_PM_PBB_MASK 0x0014
4275 -#define SM_PM_PLL0 0x0020
4276 -#define SM_PM_PLL1 0x0024
4277 -#define SM_PM_VCTRL 0x0030
4278 -#define SM_PM_VMREF 0x0034
4279 -#define SM_PM_VMV 0x0038
4280 -#define SM_PM_IER 0x0040
4281 -#define SM_PM_IDR 0x0044
4282 -#define SM_PM_IMR 0x0048
4283 -#define SM_PM_ISR 0x004c
4284 -#define SM_PM_ICR 0x0050
4285 -#define SM_PM_GCCTRL 0x0060
4286 -#define SM_RTC_CTRL 0x0080
4287 -#define SM_RTC_VAL 0x0084
4288 -#define SM_RTC_TOP 0x0088
4289 -#define SM_RTC_IER 0x0090
4290 -#define SM_RTC_IDR 0x0094
4291 -#define SM_RTC_IMR 0x0098
4292 -#define SM_RTC_ISR 0x009c
4293 -#define SM_RTC_ICR 0x00a0
4294 -#define SM_WDT_CTRL 0x00b0
4295 -#define SM_WDT_CLR 0x00b4
4296 -#define SM_WDT_EXT 0x00b8
4297 -#define SM_RC_RCAUSE 0x00c0
4298 -#define SM_EIM_IER 0x0100
4299 -#define SM_EIM_IDR 0x0104
4300 -#define SM_EIM_IMR 0x0108
4301 -#define SM_EIM_ISR 0x010c
4302 -#define SM_EIM_ICR 0x0110
4303 -#define SM_EIM_MODE 0x0114
4304 -#define SM_EIM_EDGE 0x0118
4305 -#define SM_EIM_LEVEL 0x011c
4306 -#define SM_EIM_TEST 0x0120
4307 -#define SM_EIM_NMIC 0x0124
4308 -
4309 -/* Bitfields in PM_MCCTRL */
4310 -
4311 -/* Bitfields in PM_CKSEL */
4312 -#define SM_CPUSEL_OFFSET 0
4313 -#define SM_CPUSEL_SIZE 3
4314 -#define SM_CPUDIV_OFFSET 7
4315 -#define SM_CPUDIV_SIZE 1
4316 -#define SM_HSBSEL_OFFSET 8
4317 -#define SM_HSBSEL_SIZE 3
4318 -#define SM_HSBDIV_OFFSET 15
4319 -#define SM_HSBDIV_SIZE 1
4320 -#define SM_PBASEL_OFFSET 16
4321 -#define SM_PBASEL_SIZE 3
4322 -#define SM_PBADIV_OFFSET 23
4323 -#define SM_PBADIV_SIZE 1
4324 -#define SM_PBBSEL_OFFSET 24
4325 -#define SM_PBBSEL_SIZE 3
4326 -#define SM_PBBDIV_OFFSET 31
4327 -#define SM_PBBDIV_SIZE 1
4328 -
4329 -/* Bitfields in PM_CPU_MASK */
4330 -
4331 -/* Bitfields in PM_HSB_MASK */
4332 -
4333 -/* Bitfields in PM_PBA_MASK */
4334 -
4335 -/* Bitfields in PM_PBB_MASK */
4336 -
4337 -/* Bitfields in PM_PLL0 */
4338 -#define SM_PLLEN_OFFSET 0
4339 -#define SM_PLLEN_SIZE 1
4340 -#define SM_PLLOSC_OFFSET 1
4341 -#define SM_PLLOSC_SIZE 1
4342 -#define SM_PLLOPT_OFFSET 2
4343 -#define SM_PLLOPT_SIZE 3
4344 -#define SM_PLLDIV_OFFSET 8
4345 -#define SM_PLLDIV_SIZE 8
4346 -#define SM_PLLMUL_OFFSET 16
4347 -#define SM_PLLMUL_SIZE 8
4348 -#define SM_PLLCOUNT_OFFSET 24
4349 -#define SM_PLLCOUNT_SIZE 6
4350 -#define SM_PLLTEST_OFFSET 31
4351 -#define SM_PLLTEST_SIZE 1
4352 -
4353 -/* Bitfields in PM_PLL1 */
4354 -
4355 -/* Bitfields in PM_VCTRL */
4356 -#define SM_VAUTO_OFFSET 0
4357 -#define SM_VAUTO_SIZE 1
4358 -#define SM_PM_VCTRL_VAL_OFFSET 8
4359 -#define SM_PM_VCTRL_VAL_SIZE 7
4360 -
4361 -/* Bitfields in PM_VMREF */
4362 -#define SM_REFSEL_OFFSET 0
4363 -#define SM_REFSEL_SIZE 4
4364 -
4365 -/* Bitfields in PM_VMV */
4366 -#define SM_PM_VMV_VAL_OFFSET 0
4367 -#define SM_PM_VMV_VAL_SIZE 8
4368 -
4369 -/* Bitfields in PM_IER */
4370 -
4371 -/* Bitfields in PM_IDR */
4372 -
4373 -/* Bitfields in PM_IMR */
4374 -
4375 -/* Bitfields in PM_ISR */
4376 -
4377 -/* Bitfields in PM_ICR */
4378 -#define SM_LOCK0_OFFSET 0
4379 -#define SM_LOCK0_SIZE 1
4380 -#define SM_LOCK1_OFFSET 1
4381 -#define SM_LOCK1_SIZE 1
4382 -#define SM_WAKE_OFFSET 2
4383 -#define SM_WAKE_SIZE 1
4384 -#define SM_VOK_OFFSET 3
4385 -#define SM_VOK_SIZE 1
4386 -#define SM_VMRDY_OFFSET 4
4387 -#define SM_VMRDY_SIZE 1
4388 -#define SM_CKRDY_OFFSET 5
4389 -#define SM_CKRDY_SIZE 1
4390 -
4391 -/* Bitfields in PM_GCCTRL */
4392 -#define SM_OSCSEL_OFFSET 0
4393 -#define SM_OSCSEL_SIZE 1
4394 -#define SM_PLLSEL_OFFSET 1
4395 -#define SM_PLLSEL_SIZE 1
4396 -#define SM_CEN_OFFSET 2
4397 -#define SM_CEN_SIZE 1
4398 -#define SM_CPC_OFFSET 3
4399 -#define SM_CPC_SIZE 1
4400 -#define SM_DIVEN_OFFSET 4
4401 -#define SM_DIVEN_SIZE 1
4402 -#define SM_DIV_OFFSET 8
4403 -#define SM_DIV_SIZE 8
4404 -
4405 -/* Bitfields in RTC_CTRL */
4406 -#define SM_PCLR_OFFSET 1
4407 -#define SM_PCLR_SIZE 1
4408 -#define SM_TOPEN_OFFSET 2
4409 -#define SM_TOPEN_SIZE 1
4410 -#define SM_CLKEN_OFFSET 3
4411 -#define SM_CLKEN_SIZE 1
4412 -#define SM_PSEL_OFFSET 8
4413 -#define SM_PSEL_SIZE 16
4414 -
4415 -/* Bitfields in RTC_VAL */
4416 -#define SM_RTC_VAL_VAL_OFFSET 0
4417 -#define SM_RTC_VAL_VAL_SIZE 31
4418 -
4419 -/* Bitfields in RTC_TOP */
4420 -#define SM_RTC_TOP_VAL_OFFSET 0
4421 -#define SM_RTC_TOP_VAL_SIZE 32
4422 -
4423 -/* Bitfields in RTC_IER */
4424 -
4425 -/* Bitfields in RTC_IDR */
4426 -
4427 -/* Bitfields in RTC_IMR */
4428 -
4429 -/* Bitfields in RTC_ISR */
4430 -
4431 -/* Bitfields in RTC_ICR */
4432 -#define SM_TOPI_OFFSET 0
4433 -#define SM_TOPI_SIZE 1
4434 -
4435 -/* Bitfields in WDT_CTRL */
4436 -#define SM_KEY_OFFSET 24
4437 -#define SM_KEY_SIZE 8
4438 -
4439 -/* Bitfields in WDT_CLR */
4440 -
4441 -/* Bitfields in WDT_EXT */
4442 -
4443 -/* Bitfields in RC_RCAUSE */
4444 -#define SM_POR_OFFSET 0
4445 -#define SM_POR_SIZE 1
4446 -#define SM_BOD_OFFSET 1
4447 -#define SM_BOD_SIZE 1
4448 -#define SM_EXT_OFFSET 2
4449 -#define SM_EXT_SIZE 1
4450 -#define SM_WDT_OFFSET 3
4451 -#define SM_WDT_SIZE 1
4452 -#define SM_NTAE_OFFSET 4
4453 -#define SM_NTAE_SIZE 1
4454 -#define SM_SERP_OFFSET 5
4455 -#define SM_SERP_SIZE 1
4456 -
4457 -/* Bitfields in EIM_IER */
4458 -
4459 -/* Bitfields in EIM_IDR */
4460 -
4461 -/* Bitfields in EIM_IMR */
4462 -
4463 -/* Bitfields in EIM_ISR */
4464 -
4465 -/* Bitfields in EIM_ICR */
4466 -
4467 -/* Bitfields in EIM_MODE */
4468 -
4469 -/* Bitfields in EIM_EDGE */
4470 -#define SM_INT0_OFFSET 0
4471 -#define SM_INT0_SIZE 1
4472 -#define SM_INT1_OFFSET 1
4473 -#define SM_INT1_SIZE 1
4474 -#define SM_INT2_OFFSET 2
4475 -#define SM_INT2_SIZE 1
4476 -#define SM_INT3_OFFSET 3
4477 -#define SM_INT3_SIZE 1
4478 -
4479 -/* Bitfields in EIM_LEVEL */
4480 -
4481 -/* Bitfields in EIM_TEST */
4482 -#define SM_TESTEN_OFFSET 31
4483 -#define SM_TESTEN_SIZE 1
4484 -
4485 -/* Bitfields in EIM_NMIC */
4486 -#define SM_EN_OFFSET 0
4487 -#define SM_EN_SIZE 1
4488 -
4489 -/* Bit manipulation macros */
4490 -#define SM_BIT(name) (1 << SM_##name##_OFFSET)
4491 -#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
4492 -#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
4493 -#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
4494 -
4495 -/* Register access macros */
4496 -#define sm_readl(port,reg) \
4497 - __raw_readl((port)->regs + SM_##reg)
4498 -#define sm_writel(port,reg,value) \
4499 - __raw_writel((value), (port)->regs + SM_##reg)
4500 -
4501 -#endif /* __ASM_AVR32_SM_H__ */
4502 diff -x .git -Nur linux-2.6.22.1/arch/avr32/Makefile linux-avr32.git/arch/avr32/Makefile
4503 --- linux-2.6.22.1/arch/avr32/Makefile 2007-07-10 20:56:30.000000000 +0200
4504 +++ linux-avr32.git/arch/avr32/Makefile 2007-06-06 11:33:46.000000000 +0200
4505 @@ -31,6 +31,7 @@
4506 core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
4507 core-y += arch/avr32/kernel/
4508 core-y += arch/avr32/mm/
4509 +drivers-y += arch/avr32/drivers/
4510 libs-y += arch/avr32/lib/
4511
4512 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
4513 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mm/dma-coherent.c linux-avr32.git/arch/avr32/mm/dma-coherent.c
4514 --- linux-2.6.22.1/arch/avr32/mm/dma-coherent.c 2007-07-10 20:56:30.000000000 +0200
4515 +++ linux-avr32.git/arch/avr32/mm/dma-coherent.c 2007-07-12 13:59:49.000000000 +0200
4516 @@ -41,6 +41,13 @@
4517 struct page *page, *free, *end;
4518 int order;
4519
4520 + /* Following is a work-around (a.k.a. hack) to prevent pages
4521 + * with __GFP_COMP being passed to split_page() which cannot
4522 + * handle them. The real problem is that this flag probably
4523 + * should be 0 on AVR32 as it is not supported on this
4524 + * platform--see CONFIG_HUGETLB_PAGE. */
4525 + gfp &= ~(__GFP_COMP);
4526 +
4527 size = PAGE_ALIGN(size);
4528 order = get_order(size);
4529
4530 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/at32ap700x_wdt.c linux-avr32.git/drivers/char/watchdog/at32ap700x_wdt.c
4531 --- linux-2.6.22.1/drivers/char/watchdog/at32ap700x_wdt.c 1970-01-01 01:00:00.000000000 +0100
4532 +++ linux-avr32.git/drivers/char/watchdog/at32ap700x_wdt.c 2007-07-12 13:59:59.000000000 +0200
4533 @@ -0,0 +1,325 @@
4534 +/*
4535 + * Watchdog driver for Atmel AT32AP700X devices
4536 + *
4537 + * Copyright (C) 2005-2006 Atmel Corporation
4538 + *
4539 + * This program is free software; you can redistribute it and/or modify
4540 + * it under the terms of the GNU General Public License version 2 as
4541 + * published by the Free Software Foundation.
4542 + */
4543 +
4544 +#include <linux/init.h>
4545 +#include <linux/kernel.h>
4546 +#include <linux/module.h>
4547 +#include <linux/moduleparam.h>
4548 +#include <linux/miscdevice.h>
4549 +#include <linux/fs.h>
4550 +#include <linux/platform_device.h>
4551 +#include <linux/watchdog.h>
4552 +#include <linux/uaccess.h>
4553 +#include <linux/io.h>
4554 +
4555 +#define TIMEOUT_MIN 1
4556 +#define TIMEOUT_DEFAULT CONFIG_AT32AP700X_WDT_TIMEOUT
4557 +#define TIMEOUT_MAX 2
4558 +
4559 +/* Watchdog registers and write/read macro */
4560 +#define WDT_CTRL 0x00
4561 +#define WDT_CTRL_EN 0
4562 +#define WDT_CTRL_PSEL 8
4563 +#define WDT_CTRL_KEY 24
4564 +
4565 +#define WDT_CLR 0x04
4566 +
4567 +#define WDT_BIT(name) (1 << WDT_##name)
4568 +#define WDT_BF(name,value) ((value) << WDT_##name)
4569 +
4570 +#define wdt_readl(dev,reg) \
4571 + __raw_readl((dev)->regs + WDT_##reg)
4572 +#define wdt_writel(dev,reg,value) \
4573 + __raw_writel((value), (dev)->regs + WDT_##reg)
4574 +
4575 +struct wdt_at32ap700x {
4576 + void __iomem *regs;
4577 + int timeout;
4578 + int users;
4579 + struct miscdevice miscdev;
4580 +};
4581 +
4582 +static struct wdt_at32ap700x *wdt;
4583 +
4584 +/*
4585 + * Disable the watchdog.
4586 + */
4587 +static void inline at32_wdt_stop(void)
4588 +{
4589 + unsigned long psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
4590 + wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
4591 + wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
4592 +}
4593 +
4594 +/*
4595 + * Enable and reset the watchdog.
4596 + */
4597 +static void inline at32_wdt_start(void)
4598 +{
4599 + /* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
4600 + unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
4601 +
4602 + wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
4603 + | WDT_BF(CTRL_PSEL, psel)
4604 + | WDT_BF(CTRL_KEY, 0x55));
4605 + wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
4606 + | WDT_BF(CTRL_PSEL, psel)
4607 + | WDT_BF(CTRL_KEY, 0xaa));
4608 +}
4609 +
4610 +/*
4611 + * Pat the watchdog timer.
4612 + */
4613 +static void inline at32_wdt_pat(void)
4614 +{
4615 + wdt_writel(wdt, CLR, 0x42);
4616 +}
4617 +
4618 +/*
4619 + * Watchdog device is opened, and watchdog starts running.
4620 + */
4621 +static int at32_wdt_open(struct inode *inode, struct file *file)
4622 +{
4623 + if (test_and_set_bit(1, &wdt->users))
4624 + return -EBUSY;
4625 +
4626 + at32_wdt_start();
4627 + return nonseekable_open(inode, file);
4628 +}
4629 +
4630 +/*
4631 + * Close the watchdog device. If CONFIG_WATCHDOG_NOWAYOUT is _not_ defined then
4632 + * the watchdog is also disabled.
4633 + */
4634 +static int at32_wdt_close(struct inode *inode, struct file *file)
4635 +{
4636 +#ifndef CONFIG_WATCHDOG_NOWAYOUT
4637 + at32_wdt_stop();
4638 +#endif
4639 + clear_bit(1, &wdt->users);
4640 + return 0;
4641 +}
4642 +
4643 +/*
4644 + * Change the watchdog time interval.
4645 + */
4646 +static int at32_wdt_settimeout(int time)
4647 +{
4648 + /*
4649 + * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
4650 + * 2 ^ 16 allowing up to 2 seconds timeout.
4651 + */
4652 + if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
4653 + return -EINVAL;
4654 +
4655 + /*
4656 + * Set new watchdog time. It will be used when at32_wdt_start() is
4657 + * called.
4658 + */
4659 + wdt->timeout = time;
4660 + return 0;
4661 +}
4662 +
4663 +static struct watchdog_info at32_wdt_info = {
4664 + .identity = "at32ap700x watchdog",
4665 + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
4666 +};
4667 +
4668 +/*
4669 + * Handle commands from user-space.
4670 + */
4671 +static int at32_wdt_ioctl(struct inode *inode, struct file *file,
4672 + unsigned int cmd, unsigned long arg)
4673 +{
4674 + int ret = -ENOTTY;
4675 + int time;
4676 + void __user *argp = (void __user *)arg;
4677 + int __user *p = argp;
4678 +
4679 + switch (cmd) {
4680 + case WDIOC_KEEPALIVE:
4681 + at32_wdt_pat();
4682 + ret = 0;
4683 + break;
4684 + case WDIOC_GETSUPPORT:
4685 + ret = copy_to_user(argp, &at32_wdt_info,
4686 + sizeof(at32_wdt_info)) ? -EFAULT : 0;
4687 + break;
4688 + case WDIOC_SETTIMEOUT:
4689 + ret = get_user(time, p);
4690 + if (ret)
4691 + break;
4692 + ret = at32_wdt_settimeout(time);
4693 + if (ret)
4694 + break;
4695 + /* Enable new time value */
4696 + at32_wdt_start();
4697 + /* fall through */
4698 + case WDIOC_GETTIMEOUT:
4699 + ret = put_user(wdt->timeout, p);
4700 + break;
4701 + case WDIOC_GETSTATUS: /* fall through */
4702 + case WDIOC_GETBOOTSTATUS:
4703 + ret = put_user(0, p);
4704 + break;
4705 + case WDIOC_SETOPTIONS:
4706 + ret = get_user(time, p);
4707 + if (ret)
4708 + break;
4709 + if (time & WDIOS_DISABLECARD)
4710 + at32_wdt_stop();
4711 + if (time & WDIOS_ENABLECARD)
4712 + at32_wdt_start();
4713 + ret = 0;
4714 + break;
4715 + }
4716 +
4717 + return ret;
4718 +}
4719 +
4720 +static ssize_t at32_wdt_write(struct file *file, const char *data, size_t len,
4721 + loff_t *ppos)
4722 +{
4723 + at32_wdt_pat();
4724 + return len;
4725 +}
4726 +
4727 +static const struct file_operations at32_wdt_fops = {
4728 + .owner = THIS_MODULE,
4729 + .llseek = no_llseek,
4730 + .ioctl = at32_wdt_ioctl,
4731 + .open = at32_wdt_open,
4732 + .release = at32_wdt_close,
4733 + .write = at32_wdt_write,
4734 +};
4735 +
4736 +static int __init at32_wdt_probe(struct platform_device *pdev)
4737 +{
4738 + struct resource *regs;
4739 + int ret;
4740 +
4741 + if (wdt) {
4742 + dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
4743 + return -EBUSY;
4744 + }
4745 +
4746 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4747 + if (!regs) {
4748 + dev_dbg(&pdev->dev, "missing mmio resource\n");
4749 + return -ENXIO;
4750 + }
4751 +
4752 + wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
4753 + if (!wdt) {
4754 + dev_dbg(&pdev->dev, "no memory for wdt structure\n");
4755 + return -ENOMEM;
4756 + }
4757 +
4758 + wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
4759 + if (!wdt->regs) {
4760 + ret = -ENOMEM;
4761 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
4762 + goto err_free;
4763 + }
4764 + wdt->users = 0;
4765 + wdt->miscdev.minor = WATCHDOG_MINOR;
4766 + wdt->miscdev.name = "watchdog";
4767 + wdt->miscdev.fops = &at32_wdt_fops;
4768 +
4769 + if (at32_wdt_settimeout(TIMEOUT_DEFAULT)) {
4770 + at32_wdt_settimeout(TIMEOUT_MAX);
4771 + dev_dbg(&pdev->dev,
4772 + "default timeout invalid, set to %d sec.\n",
4773 + TIMEOUT_MAX);
4774 + }
4775 +
4776 + ret = misc_register(&wdt->miscdev);
4777 + if (ret) {
4778 + dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
4779 + goto err_iounmap;
4780 + }
4781 +
4782 + platform_set_drvdata(pdev, wdt);
4783 + wdt->miscdev.parent = &pdev->dev;
4784 + dev_info(&pdev->dev, "AT32AP700X WDT at 0x%p\n", wdt->regs);
4785 +
4786 + return 0;
4787 +
4788 +err_iounmap:
4789 + iounmap(wdt->regs);
4790 +err_free:
4791 + kfree(wdt);
4792 + wdt = NULL;
4793 + return ret;
4794 +}
4795 +
4796 +static int __exit at32_wdt_remove(struct platform_device *pdev)
4797 +{
4798 + if (wdt && platform_get_drvdata(pdev) == wdt) {
4799 + misc_deregister(&wdt->miscdev);
4800 + iounmap(wdt->regs);
4801 + kfree(wdt);
4802 + wdt = NULL;
4803 + platform_set_drvdata(pdev, NULL);
4804 + }
4805 +
4806 + return 0;
4807 +}
4808 +
4809 +static void at32_wdt_shutdown(struct platform_device *pdev)
4810 +{
4811 + at32_wdt_stop();
4812 +}
4813 +
4814 +#ifdef CONFIG_PM
4815 +static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
4816 +{
4817 + at32_wdt_stop();
4818 + return 0;
4819 +}
4820 +
4821 +static int at32_wdt_resume(struct platform_device *pdev)
4822 +{
4823 + if (wdt->users)
4824 + at32_wdt_start();
4825 + return 0;
4826 +}
4827 +#else
4828 +#define at32_wdt_suspend NULL
4829 +#define at32_wdt_resume NULL
4830 +#endif
4831 +
4832 +static struct platform_driver at32_wdt_driver = {
4833 + .remove = __exit_p(at32_wdt_remove),
4834 + .suspend = at32_wdt_suspend,
4835 + .resume = at32_wdt_resume,
4836 + .driver = {
4837 + .name = "at32_wdt",
4838 + .owner = THIS_MODULE,
4839 + },
4840 + .shutdown = at32_wdt_shutdown,
4841 +};
4842 +
4843 +static int __init at32_wdt_init(void)
4844 +{
4845 + return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
4846 +}
4847 +module_init(at32_wdt_init);
4848 +
4849 +static void __exit at32_wdt_exit(void)
4850 +{
4851 + platform_driver_unregister(&at32_wdt_driver);
4852 +}
4853 +module_exit(at32_wdt_exit);
4854 +
4855 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
4856 +MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
4857 +MODULE_LICENSE("GPL");
4858 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
4859 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/Kconfig linux-avr32.git/drivers/char/watchdog/Kconfig
4860 --- linux-2.6.22.1/drivers/char/watchdog/Kconfig 2007-07-10 20:56:30.000000000 +0200
4861 +++ linux-avr32.git/drivers/char/watchdog/Kconfig 2007-07-12 13:59:59.000000000 +0200
4862 @@ -187,6 +187,26 @@
4863
4864 Say N if you are unsure.
4865
4866 +# AVR32 Architecture
4867 +
4868 +config AT32AP700X_WDT
4869 + tristate "AT32AP700x watchdog"
4870 + depends on WATCHDOG && CPU_AT32AP7000
4871 + help
4872 + Watchdog timer embedded into AT32AP700x devices. This will reboot
4873 + your system when the timeout is reached.
4874 +
4875 +config AT32AP700X_WDT_TIMEOUT
4876 + int "Timeout value for AT32AP700x watchdog"
4877 + depends on AT32AP700X_WDT
4878 + default "2"
4879 + range 1 2
4880 + help
4881 + Sets the timeout value for the watchdog in AT32AP700x devices.
4882 + Limited by hardware to be 1 or 2 seconds.
4883 +
4884 + Set to 2 seconds by default.
4885 +
4886 # X86 (i386 + ia64 + x86_64) Architecture
4887
4888 config ACQUIRE_WDT
4889 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/Makefile linux-avr32.git/drivers/char/watchdog/Makefile
4890 --- linux-2.6.22.1/drivers/char/watchdog/Makefile 2007-07-10 20:56:30.000000000 +0200
4891 +++ linux-avr32.git/drivers/char/watchdog/Makefile 2007-07-12 13:59:59.000000000 +0200
4892 @@ -36,6 +36,9 @@
4893 obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
4894 obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
4895
4896 +# AVR32 Architecture
4897 +obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
4898 +
4899 # X86 (i386 + ia64 + x86_64) Architecture
4900 obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4901 obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4902 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/atmeltwi.h linux-avr32.git/drivers/i2c/busses/atmeltwi.h
4903 --- linux-2.6.22.1/drivers/i2c/busses/atmeltwi.h 1970-01-01 01:00:00.000000000 +0100
4904 +++ linux-avr32.git/drivers/i2c/busses/atmeltwi.h 2007-06-06 11:33:51.000000000 +0200
4905 @@ -0,0 +1,117 @@
4906 +/*
4907 + * Register definitions for the Atmel Two-Wire Interface
4908 + */
4909 +
4910 +#ifndef __ASM_AVR32_TWI_H__
4911 +#define __ASM_AVR32_TWI_H__
4912 +
4913 +/* TWI register offsets */
4914 +#define TWI_CR 0x0000
4915 +#define TWI_MMR 0x0004
4916 +#define TWI_SMR 0x0008
4917 +#define TWI_IADR 0x000c
4918 +#define TWI_CWGR 0x0010
4919 +#define TWI_SR 0x0020
4920 +#define TWI_IER 0x0024
4921 +#define TWI_IDR 0x0028
4922 +#define TWI_IMR 0x002c
4923 +#define TWI_RHR 0x0030
4924 +#define TWI_THR 0x0034
4925 +
4926 +/* Bitfields in CR */
4927 +#define TWI_START_OFFSET 0
4928 +#define TWI_START_SIZE 1
4929 +#define TWI_STOP_OFFSET 1
4930 +#define TWI_STOP_SIZE 1
4931 +#define TWI_MSEN_OFFSET 2
4932 +#define TWI_MSEN_SIZE 1
4933 +#define TWI_MSDIS_OFFSET 3
4934 +#define TWI_MSDIS_SIZE 1
4935 +#define TWI_SVEN_OFFSET 4
4936 +#define TWI_SVEN_SIZE 1
4937 +#define TWI_SVDIS_OFFSET 5
4938 +#define TWI_SVDIS_SIZE 1
4939 +#define TWI_SWRST_OFFSET 7
4940 +#define TWI_SWRST_SIZE 1
4941 +
4942 +/* Bitfields in MMR */
4943 +#define TWI_IADRSZ_OFFSET 8
4944 +#define TWI_IADRSZ_SIZE 2
4945 +#define TWI_MREAD_OFFSET 12
4946 +#define TWI_MREAD_SIZE 1
4947 +#define TWI_DADR_OFFSET 16
4948 +#define TWI_DADR_SIZE 7
4949 +
4950 +/* Bitfields in SMR */
4951 +#define TWI_SADR_OFFSET 16
4952 +#define TWI_SADR_SIZE 7
4953 +
4954 +/* Bitfields in IADR */
4955 +#define TWI_IADR_OFFSET 0
4956 +#define TWI_IADR_SIZE 24
4957 +
4958 +/* Bitfields in CWGR */
4959 +#define TWI_CLDIV_OFFSET 0
4960 +#define TWI_CLDIV_SIZE 8
4961 +#define TWI_CHDIV_OFFSET 8
4962 +#define TWI_CHDIV_SIZE 8
4963 +#define TWI_CKDIV_OFFSET 16
4964 +#define TWI_CKDIV_SIZE 3
4965 +
4966 +/* Bitfields in SR */
4967 +#define TWI_TXCOMP_OFFSET 0
4968 +#define TWI_TXCOMP_SIZE 1
4969 +#define TWI_RXRDY_OFFSET 1
4970 +#define TWI_RXRDY_SIZE 1
4971 +#define TWI_TXRDY_OFFSET 2
4972 +#define TWI_TXRDY_SIZE 1
4973 +#define TWI_SVDIR_OFFSET 3
4974 +#define TWI_SVDIR_SIZE 1
4975 +#define TWI_SVACC_OFFSET 4
4976 +#define TWI_SVACC_SIZE 1
4977 +#define TWI_GCACC_OFFSET 5
4978 +#define TWI_GCACC_SIZE 1
4979 +#define TWI_OVRE_OFFSET 6
4980 +#define TWI_OVRE_SIZE 1
4981 +#define TWI_UNRE_OFFSET 7
4982 +#define TWI_UNRE_SIZE 1
4983 +#define TWI_NACK_OFFSET 8
4984 +#define TWI_NACK_SIZE 1
4985 +#define TWI_ARBLST_OFFSET 9
4986 +#define TWI_ARBLST_SIZE 1
4987 +
4988 +/* Bitfields in RHR */
4989 +#define TWI_RXDATA_OFFSET 0
4990 +#define TWI_RXDATA_SIZE 8
4991 +
4992 +/* Bitfields in THR */
4993 +#define TWI_TXDATA_OFFSET 0
4994 +#define TWI_TXDATA_SIZE 8
4995 +
4996 +/* Constants for IADRSZ */
4997 +#define TWI_IADRSZ_NO_ADDR 0
4998 +#define TWI_IADRSZ_ONE_BYTE 1
4999 +#define TWI_IADRSZ_TWO_BYTES 2
5000 +#define TWI_IADRSZ_THREE_BYTES 3
5001 +
5002 +/* Bit manipulation macros */
5003 +#define TWI_BIT(name) \
5004 + (1 << TWI_##name##_OFFSET)
5005 +#define TWI_BF(name,value) \
5006 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
5007 + << TWI_##name##_OFFSET)
5008 +#define TWI_BFEXT(name,value) \
5009 + (((value) >> TWI_##name##_OFFSET) \
5010 + & ((1 << TWI_##name##_SIZE) - 1))
5011 +#define TWI_BFINS(name,value,old) \
5012 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
5013 + << TWI_##name##_OFFSET)) \
5014 + | TWI_BF(name,value))
5015 +
5016 +/* Register access macros */
5017 +#define twi_readl(port,reg) \
5018 + __raw_readl((port)->regs + TWI_##reg)
5019 +#define twi_writel(port,reg,value) \
5020 + __raw_writel((value), (port)->regs + TWI_##reg)
5021 +
5022 +#endif /* __ASM_AVR32_TWI_H__ */
5023 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/i2c-atmeltwi.c linux-avr32.git/drivers/i2c/busses/i2c-atmeltwi.c
5024 --- linux-2.6.22.1/drivers/i2c/busses/i2c-atmeltwi.c 1970-01-01 01:00:00.000000000 +0100
5025 +++ linux-avr32.git/drivers/i2c/busses/i2c-atmeltwi.c 2007-07-13 11:24:16.000000000 +0200
5026 @@ -0,0 +1,383 @@
5027 +/*
5028 + * i2c Support for Atmel's Two-Wire Interface (TWI)
5029 + *
5030 + * Based on the work of Copyright (C) 2004 Rick Bronson
5031 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
5032 + * Ported to AVR32 and heavily modified by Espen Krangnes
5033 + * <ekrangnes at atmel.com>
5034 + *
5035 + * Copyright (C) 2006 Atmel Corporation
5036 + *
5037 + * Borrowed heavily from the original work by:
5038 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
5039 + *
5040 + * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
5041 + * bugs removed, interrupt routine markedly rewritten
5042 + *
5043 + * This program is free software; you can redistribute it and/or modify
5044 + * it under the terms of the GNU General Public License as published by
5045 + * the Free Software Foundation; either version 2 of the License, or
5046 + * (at your option) any later version.
5047 + */
5048 +
5049 +
5050 +#include <linux/err.h>
5051 +#include <linux/module.h>
5052 +#include <linux/kernel.h>
5053 +#include <linux/slab.h>
5054 +#include <linux/types.h>
5055 +#include <linux/delay.h>
5056 +#include <linux/i2c.h>
5057 +#include <linux/init.h>
5058 +#include <linux/clk.h>
5059 +#include <linux/interrupt.h>
5060 +#include <linux/irq.h>
5061 +#include <linux/platform_device.h>
5062 +#include <linux/completion.h>
5063 +#include <asm/io.h>
5064 +#include <linux/time.h>
5065 +#include "atmeltwi.h"
5066 +
5067 +static unsigned int baudrate = CONFIG_I2C_ATMELTWI_BAUDRATE;
5068 +module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
5069 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
5070 +
5071 +
5072 +struct atmel_twi {
5073 + void __iomem *regs;
5074 + struct i2c_adapter adapter;
5075 + struct clk *pclk;
5076 + spinlock_t lock;
5077 + struct completion comp;
5078 + u32 intmask;
5079 + u8 *buf;
5080 + u8 len;
5081 + u8 acks_left;
5082 + u8 nack;
5083 + unsigned int irq;
5084 +
5085 +};
5086 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
5087 +
5088 +/*
5089 + * Initialize the TWI hardware registers.
5090 + */
5091 +static int __devinit twi_hwinit(struct atmel_twi *twi)
5092 +{
5093 + unsigned long cdiv, ckdiv=0;
5094 +
5095 + twi_writel(twi, IDR, ~0UL);
5096 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
5097 + twi_readl(twi, SR);
5098 +
5099 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
5100 +
5101 + while (cdiv > 255) {
5102 + ckdiv++;
5103 + cdiv = cdiv >> 1;
5104 + }
5105 +
5106 + if (ckdiv > 7)
5107 + return -EINVAL;
5108 + else
5109 + twi_writel(twi, CWGR, (TWI_BF(CKDIV, ckdiv)
5110 + | TWI_BF(CHDIV, cdiv)
5111 + | TWI_BF(CLDIV, cdiv)));
5112 + return 0;
5113 +}
5114 +
5115 +/*
5116 + * Waits for the i2c status register to set the specified bitmask
5117 + * Returns 0 if timed out (~100ms).
5118 + */
5119 +static short twi_complete(struct atmel_twi *twi, u32 mask)
5120 +{
5121 + int timeout = msecs_to_jiffies(100);
5122 +
5123 + twi->intmask = mask;
5124 + init_completion(&twi->comp);
5125 +
5126 + twi_writel(twi, IER, mask);
5127 +
5128 + if (!wait_for_completion_timeout(&twi->comp, timeout)) {
5129 + /* RESET TWI interface */
5130 + twi_writel(twi, CR, TWI_BIT(SWRST));
5131 +
5132 + /* Reinitialize TWI */
5133 + twi_hwinit(twi);
5134 +
5135 + return -ETIMEDOUT;
5136 + }
5137 + return 0;
5138 +}
5139 +
5140 +/*
5141 + * Generic i2c master transfer entrypoint.
5142 + */
5143 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
5144 +{
5145 + struct atmel_twi *twi = to_atmel_twi(adap);
5146 + struct i2c_msg *pmsg;
5147 + int i;
5148 +
5149 + /* get first message */
5150 + pmsg = msgs;
5151 +
5152 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
5153 +
5154 + twi->nack = 0;
5155 + for (i = 0; i < num; i++, pmsg++) {
5156 + twi->len = pmsg->len;
5157 + twi->buf = pmsg->buf;
5158 + twi->acks_left = pmsg->len;
5159 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
5160 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
5161 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
5162 +
5163 + dev_dbg(&adap->dev,"#%d: internal addr %d %s byte%s %s 0x%02x\n",
5164 + i,pmsg->len, pmsg->flags & I2C_M_RD ? "reading" : "writing",
5165 + pmsg->len > 1 ? "s" : "",
5166 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
5167 +
5168 + /* enable */
5169 + twi_writel(twi, CR, TWI_BIT(MSEN));
5170 +
5171 + if (pmsg->flags & I2C_M_RD) {
5172 + if (twi->len == 1)
5173 + twi_writel(twi, CR,
5174 + TWI_BIT(START) | TWI_BIT(STOP));
5175 + else
5176 + twi_writel(twi, CR, TWI_BIT(START));
5177 +
5178 + if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
5179 + dev_dbg(&adap->dev, "RXRDY timeout. Stopped with %d bytes left\n",
5180 + twi->acks_left);
5181 + return -ETIMEDOUT;
5182 + }
5183 + } else {
5184 + twi_writel(twi, THR, twi->buf[0]);
5185 + if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
5186 + dev_dbg(&adap->dev, "TXRDY timeout. Stopped with %d bytes left\n",
5187 + twi->acks_left);
5188 + return -ETIMEDOUT;
5189 + }
5190 +
5191 + if (twi->nack)
5192 + return -ENODEV;
5193 + }
5194 +
5195 + /* Disable TWI interface */
5196 + twi_writel(twi, CR, TWI_BIT(MSDIS));
5197 +
5198 + } /* end cur msg */
5199 +
5200 + return i;
5201 +}
5202 +
5203 +
5204 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
5205 +{
5206 + struct atmel_twi *twi = dev_id;
5207 + int status = twi_readl(twi, SR);
5208 +
5209 + /* Save state for later debug prints */
5210 + int old_mask = twi->intmask;
5211 + int old_status = status;
5212 +
5213 + if (twi->intmask & status) {
5214 + if (status & TWI_BIT(NACK))
5215 + goto nack;
5216 +
5217 + status &= twi->intmask;
5218 +
5219 + if (status & TWI_BIT(TXCOMP))
5220 + goto complete;
5221 +
5222 + else if (status & TWI_BIT(RXRDY)) {
5223 + if ( twi->acks_left > 0 ) {
5224 + twi->buf[twi->len - twi->acks_left] =
5225 + twi_readl(twi, RHR);
5226 + twi->acks_left--;
5227 + }
5228 + if ( twi->acks_left == 1 )
5229 + twi_writel(twi, CR, TWI_BIT(STOP));
5230 +
5231 + if (twi->acks_left == 0 ) {
5232 + twi->intmask = TWI_BIT(TXCOMP);
5233 + twi_writel(twi, IER, TWI_BIT(TXCOMP));
5234 + }
5235 + } else if (status & TWI_BIT(TXRDY)) {
5236 + twi->acks_left--;
5237 + if ( twi->acks_left == 0 ) {
5238 + twi->intmask = TWI_BIT(TXCOMP);
5239 + twi_writel(twi, IER, TWI_BIT(TXCOMP));
5240 + } else if (twi->acks_left > 0)
5241 + twi_writel(twi, THR, twi->buf[twi->len - twi->acks_left]);
5242 + }
5243 + }
5244 +
5245 + dev_dbg(&twi->adapter.dev,
5246 + "TWI ISR, SR 0x%08X, intmask 0x%08X, acks_left %i.\n",
5247 + old_status, old_mask, twi->acks_left);
5248 +
5249 + return IRQ_HANDLED;
5250 +
5251 +nack:
5252 + dev_dbg(&twi->adapter.dev, "NACK received!\n");
5253 + twi->nack = 1;
5254 +
5255 +complete:
5256 + twi_writel(twi, IDR, ~0UL);
5257 + complete(&twi->comp);
5258 +
5259 + dev_dbg(&twi->adapter.dev,
5260 + "TWI ISR, SR 0x%08X, intmask 0x%08X, \
5261 + acks_left %i - completed.\n",
5262 + old_status, old_mask, twi->acks_left);
5263 +
5264 + return IRQ_HANDLED;
5265 +}
5266 +
5267 +
5268 +/*
5269 + * Return list of supported functionality.
5270 + */
5271 +static u32 twi_func(struct i2c_adapter *adapter)
5272 +{
5273 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5274 +}
5275 +
5276 +/* For now, we only handle combined mode (smbus) */
5277 +static struct i2c_algorithm twi_algorithm = {
5278 + .master_xfer = twi_xfer,
5279 + .functionality = twi_func,
5280 +};
5281 +
5282 +/*
5283 + * Main initialization routine.
5284 + */
5285 +static int __devinit twi_probe(struct platform_device *pdev)
5286 +{
5287 + struct atmel_twi *twi;
5288 + struct resource *regs;
5289 + struct clk *pclk;
5290 + struct i2c_adapter *adapter;
5291 + int rc, irq;
5292 +
5293 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5294 + if (!regs)
5295 + return -ENXIO;
5296 +
5297 + pclk = clk_get(&pdev->dev, "pclk");
5298 + if (IS_ERR(pclk))
5299 + return PTR_ERR(pclk);
5300 + clk_enable(pclk);
5301 +
5302 + rc = -ENOMEM;
5303 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
5304 + if (!twi) {
5305 + dev_err(&pdev->dev, "can't allocate interface!\n");
5306 + goto err_alloc_twi;
5307 + }
5308 +
5309 + twi->pclk = pclk;
5310 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
5311 + if (!twi->regs)
5312 + goto err_ioremap;
5313 +
5314 + irq = platform_get_irq(pdev,0);
5315 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
5316 + if (rc) {
5317 + dev_err(&pdev->dev, "can't bind irq!\n");
5318 + goto err_irq;
5319 + }
5320 + twi->irq = irq;
5321 +
5322 + rc = twi_hwinit(twi);
5323 + if (rc) {
5324 + dev_err(&pdev->dev, "Unable to set baudrate\n");
5325 + goto err_hw_init;
5326 + }
5327 +
5328 + adapter = &twi->adapter;
5329 + sprintf(adapter->name, "TWI");
5330 + adapter->algo = &twi_algorithm;
5331 + adapter->class = I2C_CLASS_HWMON;
5332 + adapter->dev.parent = &pdev->dev;
5333 +
5334 + platform_set_drvdata(pdev, twi);
5335 +
5336 + rc = i2c_add_adapter(adapter);
5337 + if (rc) {
5338 + dev_err(&pdev->dev, "Adapter %s registration failed\n",
5339 + adapter->name);
5340 + goto err_register;
5341 + }
5342 +
5343 + dev_info(&pdev->dev, "Atmel TWI i2c bus device (baudrate %dk) at 0x%08lx.\n",
5344 + baudrate/1000, (unsigned long)regs->start);
5345 +
5346 + return 0;
5347 +
5348 +
5349 +err_register:
5350 + platform_set_drvdata(pdev, NULL);
5351 +
5352 +err_hw_init:
5353 + free_irq(irq, twi);
5354 +
5355 +err_irq:
5356 + iounmap(twi->regs);
5357 +
5358 +err_ioremap:
5359 + kfree(twi);
5360 +
5361 +err_alloc_twi:
5362 + clk_disable(pclk);
5363 + clk_put(pclk);
5364 +
5365 + return rc;
5366 +}
5367 +
5368 +static int __devexit twi_remove(struct platform_device *pdev)
5369 +{
5370 + struct atmel_twi *twi = platform_get_drvdata(pdev);
5371 + int res;
5372 +
5373 + platform_set_drvdata(pdev, NULL);
5374 + res = i2c_del_adapter(&twi->adapter);
5375 + twi_writel(twi, CR, TWI_BIT(MSDIS));
5376 + iounmap(twi->regs);
5377 + clk_disable(twi->pclk);
5378 + clk_put(twi->pclk);
5379 + free_irq(twi->irq, twi);
5380 + kfree(twi);
5381 +
5382 + return res;
5383 +}
5384 +
5385 +static struct platform_driver twi_driver = {
5386 + .probe = twi_probe,
5387 + .remove = __devexit_p(twi_remove),
5388 + .driver = {
5389 + .name = "atmel_twi",
5390 + .owner = THIS_MODULE,
5391 + },
5392 +};
5393 +
5394 +static int __init atmel_twi_init(void)
5395 +{
5396 + return platform_driver_register(&twi_driver);
5397 +}
5398 +
5399 +static void __exit atmel_twi_exit(void)
5400 +{
5401 + platform_driver_unregister(&twi_driver);
5402 +}
5403 +
5404 +module_init(atmel_twi_init);
5405 +module_exit(atmel_twi_exit);
5406 +
5407 +MODULE_AUTHOR("Espen Krangnes");
5408 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
5409 +MODULE_LICENSE("GPL");
5410 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/Kconfig linux-avr32.git/drivers/i2c/busses/Kconfig
5411 --- linux-2.6.22.1/drivers/i2c/busses/Kconfig 2007-07-10 20:56:30.000000000 +0200
5412 +++ linux-avr32.git/drivers/i2c/busses/Kconfig 2007-07-12 13:59:59.000000000 +0200
5413 @@ -4,6 +4,26 @@
5414
5415 menu "I2C Hardware Bus support"
5416
5417 +config I2C_ATMELTWI
5418 + tristate "Atmel TWI/I2C"
5419 + depends on I2C
5420 + help
5421 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
5422 + AT91-based device and want to use its built-in TWI
5423 + functionality. Atmel's TWI is compatible with Philips' I2C
5424 + protocol. If in doubt, say NO
5425 +
5426 +config I2C_ATMELTWI_BAUDRATE
5427 + prompt "Atmel TWI baudrate"
5428 + depends on I2C_ATMELTWI
5429 + int
5430 + default 100000
5431 + help
5432 + Set the TWI/I2C baudrate. This will alter the default value. A
5433 + different baudrate can be set by using a module parameter as well. If
5434 + no parameter is provided when loading, this is the value that will be
5435 + used.
5436 +
5437 config I2C_ALI1535
5438 tristate "ALI 1535"
5439 depends on PCI
5440 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/Makefile linux-avr32.git/drivers/i2c/busses/Makefile
5441 --- linux-2.6.22.1/drivers/i2c/busses/Makefile 2007-07-10 20:56:30.000000000 +0200
5442 +++ linux-avr32.git/drivers/i2c/busses/Makefile 2007-07-12 13:59:59.000000000 +0200
5443 @@ -52,6 +52,7 @@
5444 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
5445 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
5446 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
5447 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
5448
5449 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
5450 EXTRA_CFLAGS += -DDEBUG
5451 diff -x .git -Nur linux-2.6.22.1/drivers/input/mouse/gpio_mouse.c linux-avr32.git/drivers/input/mouse/gpio_mouse.c
5452 --- linux-2.6.22.1/drivers/input/mouse/gpio_mouse.c 1970-01-01 01:00:00.000000000 +0100
5453 +++ linux-avr32.git/drivers/input/mouse/gpio_mouse.c 2007-07-13 11:24:16.000000000 +0200
5454 @@ -0,0 +1,196 @@
5455 +/*
5456 + * Driver for simulating a mouse on GPIO lines.
5457 + *
5458 + * Copyright (C) 2007 Atmel Corporation
5459 + *
5460 + * This program is free software; you can redistribute it and/or modify
5461 + * it under the terms of the GNU General Public License version 2 as
5462 + * published by the Free Software Foundation.
5463 + */
5464 +
5465 +#include <linux/init.h>
5466 +#include <linux/version.h>
5467 +#include <linux/module.h>
5468 +#include <linux/platform_device.h>
5469 +#include <linux/input-polldev.h>
5470 +#include <linux/gpio_mouse.h>
5471 +
5472 +#include <asm/gpio.h>
5473 +
5474 +/*
5475 + * Timer function which is run every scan_ms ms when the device is opened.
5476 + * The dev input varaible is set to the the input_dev pointer.
5477 + */
5478 +static void gpio_mouse_scan(struct input_polled_dev *dev)
5479 +{
5480 + struct gpio_mouse_platform_data *gpio = dev->private;
5481 + struct input_dev *input = dev->input;
5482 + int x, y;
5483 +
5484 + if (gpio->bleft >= 0)
5485 + input_report_key(input, BTN_LEFT,
5486 + gpio_get_value(gpio->bleft) ^ gpio->polarity);
5487 + if (gpio->bmiddle >= 0)
5488 + input_report_key(input, BTN_MIDDLE,
5489 + gpio_get_value(gpio->bmiddle) ^ gpio->polarity);
5490 + if (gpio->bright >= 0)
5491 + input_report_key(input, BTN_RIGHT,
5492 + gpio_get_value(gpio->bright) ^ gpio->polarity);
5493 +
5494 + x = (gpio_get_value(gpio->right) ^ gpio->polarity)
5495 + - (gpio_get_value(gpio->left) ^ gpio->polarity);
5496 + y = (gpio_get_value(gpio->down) ^ gpio->polarity)
5497 + - (gpio_get_value(gpio->up) ^ gpio->polarity);
5498 +
5499 + input_report_rel(input, REL_X, x);
5500 + input_report_rel(input, REL_Y, y);
5501 + input_sync(input);
5502 +}
5503 +
5504 +static int __init gpio_mouse_probe(struct platform_device *pdev)
5505 +{
5506 + struct gpio_mouse_platform_data *pdata = pdev->dev.platform_data;
5507 + struct input_polled_dev *input_poll;
5508 + struct input_dev *input;
5509 + int pin, i;
5510 + int error;
5511 +
5512 + if (!pdata) {
5513 + dev_err(&pdev->dev, "no platform data\n");
5514 + error = -ENXIO;
5515 + goto out;
5516 + }
5517 +
5518 + if (pdata->scan_ms < 0) {
5519 + dev_err(&pdev->dev, "invalid scan time\n");
5520 + error = -EINVAL;
5521 + goto out;
5522 + }
5523 +
5524 + for (i = 0; i < GPIO_MOUSE_PIN_MAX; i++) {
5525 + pin = pdata->pins[i];
5526 +
5527 + if (pin < 0) {
5528 +
5529 + if (i <= GPIO_MOUSE_PIN_RIGHT) {
5530 + /* Mouse direction is required. */
5531 + dev_err(&pdev->dev,
5532 + "missing GPIO for directions\n");
5533 + error = -EINVAL;
5534 + goto out_free_gpios;
5535 + }
5536 +
5537 + if (i == GPIO_MOUSE_PIN_BLEFT)
5538 + dev_dbg(&pdev->dev, "no left button defined\n");
5539 +
5540 + } else {
5541 + error = gpio_request(pin, "gpio_mouse");
5542 + if (error) {
5543 + dev_err(&pdev->dev, "fail %d pin (%d idx)\n",
5544 + pin, i);
5545 + goto out_free_gpios;
5546 + }
5547 +
5548 + gpio_direction_input(pin);
5549 + }
5550 + }
5551 +
5552 + input_poll = input_allocate_polled_device();
5553 + if (!input_poll) {
5554 + dev_err(&pdev->dev, "not enough memory for input device\n");
5555 + error = -ENOMEM;
5556 + goto out_free_gpios;
5557 + }
5558 +
5559 + platform_set_drvdata(pdev, input_poll);
5560 +
5561 + /* set input-polldev handlers */
5562 + input_poll->private = pdata;
5563 + input_poll->poll = gpio_mouse_scan;
5564 + input_poll->poll_interval = pdata->scan_ms;
5565 +
5566 + input = input_poll->input;
5567 + input->name = pdev->name;
5568 + input->id.bustype = BUS_HOST;
5569 + input->dev.parent = &pdev->dev;
5570 +
5571 + input_set_capability(input, EV_REL, REL_X);
5572 + input_set_capability(input, EV_REL, REL_Y);
5573 + if (pdata->bleft >= 0)
5574 + input_set_capability(input, EV_KEY, BTN_LEFT);
5575 + if (pdata->bmiddle >= 0)
5576 + input_set_capability(input, EV_KEY, BTN_MIDDLE);
5577 + if (pdata->bright >= 0)
5578 + input_set_capability(input, EV_KEY, BTN_RIGHT);
5579 +
5580 + error = input_register_polled_device(input_poll);
5581 + if (error) {
5582 + dev_err(&pdev->dev, "could not register input device\n");
5583 + goto out_free_polldev;
5584 + }
5585 +
5586 + dev_dbg(&pdev->dev, "%d ms scan time, buttons: %s%s%s\n",
5587 + pdata->scan_ms,
5588 + pdata->bleft < 0 ? "" : "left ",
5589 + pdata->bmiddle < 0 ? "" : "middle ",
5590 + pdata->bright < 0 ? "" : "right");
5591 +
5592 + return 0;
5593 +
5594 + out_free_polldev:
5595 + input_free_polled_device(input_poll);
5596 + platform_set_drvdata(pdev, NULL);
5597 +
5598 + out_free_gpios:
5599 + while (--i >= 0) {
5600 + pin = pdata->pins[i];
5601 + if (pin)
5602 + gpio_free(pin);
5603 + }
5604 + out:
5605 + return error;
5606 +}
5607 +
5608 +static int __devexit gpio_mouse_remove(struct platform_device *pdev)
5609 +{
5610 + struct input_polled_dev *input = platform_get_drvdata(pdev);
5611 + struct gpio_mouse_platform_data *pdata = input->private;
5612 + int pin, i;
5613 +
5614 + input_unregister_polled_device(input);
5615 + input_free_polled_device(input);
5616 +
5617 + for (i = 0; i < GPIO_MOUSE_PIN_MAX; i++) {
5618 + pin = pdata->pins[i];
5619 + if (pin >= 0)
5620 + gpio_free(pin);
5621 + }
5622 +
5623 + platform_set_drvdata(pdev, NULL);
5624 +
5625 + return 0;
5626 +}
5627 +
5628 +struct platform_driver gpio_mouse_device_driver = {
5629 + .remove = __devexit_p(gpio_mouse_remove),
5630 + .driver = {
5631 + .name = "gpio_mouse",
5632 + }
5633 +};
5634 +
5635 +static int __init gpio_mouse_init(void)
5636 +{
5637 + return platform_driver_probe(&gpio_mouse_device_driver,
5638 + gpio_mouse_probe);
5639 +}
5640 +module_init(gpio_mouse_init);
5641 +
5642 +static void __exit gpio_mouse_exit(void)
5643 +{
5644 + platform_driver_unregister(&gpio_mouse_device_driver);
5645 +}
5646 +module_exit(gpio_mouse_exit);
5647 +
5648 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
5649 +MODULE_DESCRIPTION("GPIO mouse driver");
5650 +MODULE_LICENSE("GPL");
5651 diff -x .git -Nur linux-2.6.22.1/drivers/input/mouse/Kconfig linux-avr32.git/drivers/input/mouse/Kconfig
5652 --- linux-2.6.22.1/drivers/input/mouse/Kconfig 2007-07-10 20:56:30.000000000 +0200
5653 +++ linux-avr32.git/drivers/input/mouse/Kconfig 2007-07-13 11:24:16.000000000 +0200
5654 @@ -216,4 +216,20 @@
5655 help
5656 Say Y here to support HIL pointers.
5657
5658 +config MOUSE_GPIO
5659 + tristate "GPIO mouse"
5660 + depends on GENERIC_GPIO
5661 + select INPUT_POLLDEV
5662 + help
5663 + This driver simulates a mouse on GPIO lines of various CPUs (and some
5664 + other chips).
5665 +
5666 + Say Y here if your device has buttons or a simple joystick connected
5667 + directly to GPIO lines. Your board-specific setup logic must also
5668 + provide a platform device and platform data saying which GPIOs are
5669 + used.
5670 +
5671 + To compile this driver as a module, choose M here: the
5672 + module will be called gpio_mouse.
5673 +
5674 endif
5675 diff -x .git -Nur linux-2.6.22.1/drivers/input/mouse/Makefile linux-avr32.git/drivers/input/mouse/Makefile
5676 --- linux-2.6.22.1/drivers/input/mouse/Makefile 2007-07-10 20:56:30.000000000 +0200
5677 +++ linux-avr32.git/drivers/input/mouse/Makefile 2007-07-13 11:24:16.000000000 +0200
5678 @@ -15,6 +15,7 @@
5679 obj-$(CONFIG_MOUSE_SERIAL) += sermouse.o
5680 obj-$(CONFIG_MOUSE_HIL) += hil_ptr.o
5681 obj-$(CONFIG_MOUSE_VSXXXAA) += vsxxxaa.o
5682 +obj-$(CONFIG_MOUSE_GPIO) += gpio_mouse.o
5683
5684 psmouse-objs := psmouse-base.o synaptics.o
5685
5686 diff -x .git -Nur linux-2.6.22.1/drivers/leds/Kconfig linux-avr32.git/drivers/leds/Kconfig
5687 --- linux-2.6.22.1/drivers/leds/Kconfig 2007-07-10 20:56:30.000000000 +0200
5688 +++ linux-avr32.git/drivers/leds/Kconfig 2007-07-12 14:00:02.000000000 +0200
5689 @@ -95,6 +95,14 @@
5690 help
5691 This option enables support for the front LED on Cobalt Server
5692
5693 +config LEDS_GPIO
5694 + tristate "LED Support for GPIO connected LEDs"
5695 + depends on LEDS_CLASS && GENERIC_GPIO
5696 + help
5697 + This option enables support for the LEDs connected to GPIO
5698 + outputs. To be useful the particular board must have LEDs
5699 + and they must be connected to the GPIO lines.
5700 +
5701 comment "LED Triggers"
5702
5703 config LEDS_TRIGGERS
5704 diff -x .git -Nur linux-2.6.22.1/drivers/leds/leds-gpio.c linux-avr32.git/drivers/leds/leds-gpio.c
5705 --- linux-2.6.22.1/drivers/leds/leds-gpio.c 1970-01-01 01:00:00.000000000 +0100
5706 +++ linux-avr32.git/drivers/leds/leds-gpio.c 2007-07-12 14:00:02.000000000 +0200
5707 @@ -0,0 +1,199 @@
5708 +/*
5709 + * LEDs driver for GPIOs
5710 + *
5711 + * Copyright (C) 2007 8D Technologies inc.
5712 + * Raphael Assenat <raph@8d.com>
5713 + *
5714 + * This program is free software; you can redistribute it and/or modify
5715 + * it under the terms of the GNU General Public License version 2 as
5716 + * published by the Free Software Foundation.
5717 + *
5718 + */
5719 +#include <linux/kernel.h>
5720 +#include <linux/init.h>
5721 +#include <linux/platform_device.h>
5722 +#include <linux/leds.h>
5723 +#include <linux/workqueue.h>
5724 +
5725 +#include <asm/gpio.h>
5726 +
5727 +struct gpio_led_data {
5728 + struct led_classdev cdev;
5729 + unsigned gpio;
5730 + struct work_struct work;
5731 + u8 new_level;
5732 + u8 can_sleep;
5733 + u8 active_low;
5734 +};
5735 +
5736 +static void gpio_led_work(struct work_struct *work)
5737 +{
5738 + struct gpio_led_data *led_dat =
5739 + container_of(work, struct gpio_led_data, work);
5740 +
5741 + gpio_set_value_cansleep(led_dat->gpio, led_dat->new_level);
5742 +}
5743 +
5744 +static void gpio_led_set(struct led_classdev *led_cdev,
5745 + enum led_brightness value)
5746 +{
5747 + struct gpio_led_data *led_dat =
5748 + container_of(led_cdev, struct gpio_led_data, cdev);
5749 + int level;
5750 +
5751 + if (value == LED_OFF)
5752 + level = 0;
5753 + else
5754 + level = 1;
5755 +
5756 + if (led_dat->active_low)
5757 + level = !level;
5758 +
5759 + /* setting GPIOs with I2C/etc requires a preemptible task context */
5760 + if (led_dat->can_sleep) {
5761 + if (preempt_count()) {
5762 + led_dat->new_level = level;
5763 + schedule_work(&led_dat->work);
5764 + } else
5765 + gpio_set_value_cansleep(led_dat->gpio, level);
5766 + } else
5767 + gpio_set_value(led_dat->gpio, level);
5768 +}
5769 +
5770 +static int __init gpio_led_probe(struct platform_device *pdev)
5771 +{
5772 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
5773 + struct gpio_led *cur_led;
5774 + struct gpio_led_data *leds_data, *led_dat;
5775 + int i, ret = 0;
5776 +
5777 + if (!pdata)
5778 + return -EBUSY;
5779 +
5780 + leds_data = kzalloc(sizeof(struct gpio_led_data) * pdata->num_leds,
5781 + GFP_KERNEL);
5782 + if (!leds_data)
5783 + return -ENOMEM;
5784 +
5785 + for (i = 0; i < pdata->num_leds; i++) {
5786 + cur_led = &pdata->leds[i];
5787 + led_dat = &leds_data[i];
5788 +
5789 + led_dat->cdev.name = cur_led->name;
5790 + led_dat->cdev.default_trigger = cur_led->default_trigger;
5791 + led_dat->gpio = cur_led->gpio;
5792 + led_dat->can_sleep = gpio_cansleep(cur_led->gpio);
5793 + led_dat->active_low = cur_led->active_low;
5794 + led_dat->cdev.brightness_set = gpio_led_set;
5795 + led_dat->cdev.brightness = cur_led->active_low ? LED_FULL : LED_OFF;
5796 +
5797 + ret = gpio_request(led_dat->gpio, led_dat->cdev.name);
5798 + if (ret < 0)
5799 + goto err;
5800 +
5801 + gpio_direction_output(led_dat->gpio, led_dat->active_low);
5802 +
5803 + ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
5804 + if (ret < 0) {
5805 + gpio_free(led_dat->gpio);
5806 + goto err;
5807 + }
5808 +
5809 + INIT_WORK(&led_dat->work, gpio_led_work);
5810 + }
5811 +
5812 + platform_set_drvdata(pdev, leds_data);
5813 +
5814 + return 0;
5815 +
5816 +err:
5817 + if (i > 0) {
5818 + for (i = i - 1; i >= 0; i--) {
5819 + led_classdev_unregister(&leds_data[i].cdev);
5820 + gpio_free(leds_data[i].gpio);
5821 + }
5822 + }
5823 +
5824 + flush_scheduled_work();
5825 + kfree(leds_data);
5826 +
5827 + return ret;
5828 +}
5829 +
5830 +static int __exit gpio_led_remove(struct platform_device *pdev)
5831 +{
5832 + int i;
5833 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
5834 + struct gpio_led_data *leds_data;
5835 +
5836 + leds_data = platform_get_drvdata(pdev);
5837 +
5838 + for (i = 0; i < pdata->num_leds; i++) {
5839 + led_classdev_unregister(&leds_data[i].cdev);
5840 + gpio_free(leds_data[i].gpio);
5841 + }
5842 +
5843 + kfree(leds_data);
5844 +
5845 + return 0;
5846 +}
5847 +
5848 +#ifdef CONFIG_PM
5849 +static int gpio_led_suspend(struct platform_device *pdev, pm_message_t state)
5850 +{
5851 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
5852 + struct gpio_led_data *leds_data;
5853 + int i;
5854 +
5855 + leds_data = platform_get_drvdata(pdev);
5856 +
5857 + for (i = 0; i < pdata->num_leds; i++)
5858 + led_classdev_suspend(&leds_data[i].cdev);
5859 +
5860 + return 0;
5861 +}
5862 +
5863 +static int gpio_led_resume(struct platform_device *pdev)
5864 +{
5865 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
5866 + struct gpio_led_data *leds_data;
5867 + int i;
5868 +
5869 + leds_data = platform_get_drvdata(pdev);
5870 +
5871 + for (i = 0; i < pdata->num_leds; i++)
5872 + led_classdev_resume(&leds_data[i].cdev);
5873 +
5874 + return 0;
5875 +}
5876 +#else
5877 +#define gpio_led_suspend NULL
5878 +#define gpio_led_resume NULL
5879 +#endif
5880 +
5881 +static struct platform_driver gpio_led_driver = {
5882 + .remove = __exit_p(gpio_led_remove),
5883 + .suspend = gpio_led_suspend,
5884 + .resume = gpio_led_resume,
5885 + .driver = {
5886 + .name = "leds-gpio",
5887 + .owner = THIS_MODULE,
5888 + },
5889 +};
5890 +
5891 +static int __init gpio_led_init(void)
5892 +{
5893 + return platform_driver_probe(&gpio_led_driver, gpio_led_probe);
5894 +}
5895 +
5896 +static void __exit gpio_led_exit(void)
5897 +{
5898 + platform_driver_unregister(&gpio_led_driver);
5899 +}
5900 +
5901 +module_init(gpio_led_init);
5902 +module_exit(gpio_led_exit);
5903 +
5904 +MODULE_AUTHOR("Raphael Assenat <raph@8d.com>");
5905 +MODULE_DESCRIPTION("GPIO LED driver");
5906 +MODULE_LICENSE("GPL");
5907 diff -x .git -Nur linux-2.6.22.1/drivers/leds/Makefile linux-avr32.git/drivers/leds/Makefile
5908 --- linux-2.6.22.1/drivers/leds/Makefile 2007-07-10 20:56:30.000000000 +0200
5909 +++ linux-avr32.git/drivers/leds/Makefile 2007-07-12 14:00:02.000000000 +0200
5910 @@ -16,6 +16,7 @@
5911 obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
5912 obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
5913 obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o
5914 +obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
5915
5916 # LED Triggers
5917 obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
5918 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/atmel-mci.c linux-avr32.git/drivers/mmc/host/atmel-mci.c
5919 --- linux-2.6.22.1/drivers/mmc/host/atmel-mci.c 1970-01-01 01:00:00.000000000 +0100
5920 +++ linux-avr32.git/drivers/mmc/host/atmel-mci.c 2007-07-12 14:00:03.000000000 +0200
5921 @@ -0,0 +1,1217 @@
5922 +/*
5923 + * Atmel MultiMedia Card Interface driver
5924 + *
5925 + * Copyright (C) 2004-2006 Atmel Corporation
5926 + *
5927 + * This program is free software; you can redistribute it and/or modify
5928 + * it under the terms of the GNU General Public License version 2 as
5929 + * published by the Free Software Foundation.
5930 + */
5931 +#include <linux/blkdev.h>
5932 +#include <linux/clk.h>
5933 +#include <linux/device.h>
5934 +#include <linux/dma-mapping.h>
5935 +#include <linux/init.h>
5936 +#include <linux/interrupt.h>
5937 +#include <linux/ioport.h>
5938 +#include <linux/module.h>
5939 +#include <linux/platform_device.h>
5940 +
5941 +#include <linux/mmc/host.h>
5942 +
5943 +#include <asm/dma-controller.h>
5944 +#include <asm/io.h>
5945 +#include <asm/arch/board.h>
5946 +#include <asm/arch/gpio.h>
5947 +
5948 +#include "atmel-mci.h"
5949 +
5950 +#define DRIVER_NAME "atmel_mci"
5951 +
5952 +#define MCI_CMD_ERROR_FLAGS (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | \
5953 + MCI_BIT(RCRCE) | MCI_BIT(RENDE) | \
5954 + MCI_BIT(RTOE))
5955 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
5956 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
5957 +
5958 +enum {
5959 + EVENT_CMD_COMPLETE = 0,
5960 + EVENT_CMD_ERROR,
5961 + EVENT_DATA_COMPLETE,
5962 + EVENT_DATA_ERROR,
5963 + EVENT_STOP_SENT,
5964 + EVENT_STOP_COMPLETE,
5965 + EVENT_STOP_ERROR,
5966 + EVENT_DMA_ERROR,
5967 + EVENT_CARD_DETECT,
5968 +};
5969 +
5970 +struct atmel_mci_dma {
5971 + struct dma_request_sg req;
5972 + unsigned short rx_periph_id;
5973 + unsigned short tx_periph_id;
5974 +};
5975 +
5976 +struct atmel_mci {
5977 + struct mmc_host *mmc;
5978 + void __iomem *regs;
5979 + struct atmel_mci_dma dma;
5980 +
5981 + struct mmc_request *mrq;
5982 + struct mmc_command *cmd;
5983 + struct mmc_data *data;
5984 +
5985 + u32 stop_cmdr;
5986 + u32 stop_iflags;
5987 +
5988 + struct tasklet_struct tasklet;
5989 + unsigned long pending_events;
5990 + unsigned long completed_events;
5991 + u32 error_status;
5992 +
5993 + int present;
5994 + int detect_pin;
5995 + int wp_pin;
5996 +
5997 + unsigned long bus_hz;
5998 + unsigned long mapbase;
5999 + struct clk *mck;
6000 + struct platform_device *pdev;
6001 +
6002 +#ifdef CONFIG_DEBUG_FS
6003 + struct dentry *debugfs_root;
6004 + struct dentry *debugfs_regs;
6005 + struct dentry *debugfs_req;
6006 + struct dentry *debugfs_pending_events;
6007 + struct dentry *debugfs_completed_events;
6008 +#endif
6009 +};
6010 +
6011 +/* Those printks take an awful lot of time... */
6012 +#ifndef DEBUG
6013 +static unsigned int fmax = 15000000U;
6014 +#else
6015 +static unsigned int fmax = 1000000U;
6016 +#endif
6017 +module_param(fmax, uint, 0444);
6018 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
6019 +
6020 +/* Test bit macros for completed events */
6021 +#define mci_cmd_is_complete(host) \
6022 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
6023 +#define mci_cmd_error_is_complete(host) \
6024 + test_bit(EVENT_CMD_ERROR, &host->completed_events)
6025 +#define mci_data_is_complete(host) \
6026 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
6027 +#define mci_data_error_is_complete(host) \
6028 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
6029 +#define mci_stop_sent_is_complete(host) \
6030 + test_bit(EVENT_STOP_SENT, &host->completed_events)
6031 +#define mci_stop_is_complete(host) \
6032 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
6033 +#define mci_stop_error_is_complete(host) \
6034 + test_bit(EVENT_STOP_ERROR, &host->completed_events)
6035 +#define mci_dma_error_is_complete(host) \
6036 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
6037 +#define mci_card_detect_is_complete(host) \
6038 + test_bit(EVENT_CARD_DETECT, &host->completed_events)
6039 +
6040 +/* Test and clear bit macros for pending events */
6041 +#define mci_clear_cmd_is_pending(host) \
6042 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
6043 +#define mci_clear_cmd_error_is_pending(host) \
6044 + test_and_clear_bit(EVENT_CMD_ERROR, &host->pending_events)
6045 +#define mci_clear_data_is_pending(host) \
6046 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
6047 +#define mci_clear_data_error_is_pending(host) \
6048 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
6049 +#define mci_clear_stop_sent_is_pending(host) \
6050 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
6051 +#define mci_clear_stop_is_pending(host) \
6052 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
6053 +#define mci_clear_stop_error_is_pending(host) \
6054 + test_and_clear_bit(EVENT_STOP_ERROR, &host->pending_events)
6055 +#define mci_clear_dma_error_is_pending(host) \
6056 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
6057 +#define mci_clear_card_detect_is_pending(host) \
6058 + test_and_clear_bit(EVENT_CARD_DETECT, &host->pending_events)
6059 +
6060 +/* Test and set bit macros for completed events */
6061 +#define mci_set_cmd_is_completed(host) \
6062 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
6063 +#define mci_set_cmd_error_is_completed(host) \
6064 + test_and_set_bit(EVENT_CMD_ERROR, &host->completed_events)
6065 +#define mci_set_data_is_completed(host) \
6066 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
6067 +#define mci_set_data_error_is_completed(host) \
6068 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
6069 +#define mci_set_stop_sent_is_completed(host) \
6070 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
6071 +#define mci_set_stop_is_completed(host) \
6072 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
6073 +#define mci_set_stop_error_is_completed(host) \
6074 + test_and_set_bit(EVENT_STOP_ERROR, &host->completed_events)
6075 +#define mci_set_dma_error_is_completed(host) \
6076 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
6077 +#define mci_set_card_detect_is_completed(host) \
6078 + test_and_set_bit(EVENT_CARD_DETECT, &host->completed_events)
6079 +
6080 +/* Set bit macros for completed events */
6081 +#define mci_set_cmd_complete(host) \
6082 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
6083 +#define mci_set_cmd_error_complete(host) \
6084 + set_bit(EVENT_CMD_ERROR, &host->completed_events)
6085 +#define mci_set_data_complete(host) \
6086 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
6087 +#define mci_set_data_error_complete(host) \
6088 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
6089 +#define mci_set_stop_sent_complete(host) \
6090 + set_bit(EVENT_STOP_SENT, &host->completed_events)
6091 +#define mci_set_stop_complete(host) \
6092 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
6093 +#define mci_set_stop_error_complete(host) \
6094 + set_bit(EVENT_STOP_ERROR, &host->completed_events)
6095 +#define mci_set_dma_error_complete(host) \
6096 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
6097 +#define mci_set_card_detect_complete(host) \
6098 + set_bit(EVENT_CARD_DETECT, &host->completed_events)
6099 +
6100 +/* Set bit macros for pending events */
6101 +#define mci_set_cmd_pending(host) \
6102 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
6103 +#define mci_set_cmd_error_pending(host) \
6104 + set_bit(EVENT_CMD_ERROR, &host->pending_events)
6105 +#define mci_set_data_pending(host) \
6106 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
6107 +#define mci_set_data_error_pending(host) \
6108 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
6109 +#define mci_set_stop_sent_pending(host) \
6110 + set_bit(EVENT_STOP_SENT, &host->pending_events)
6111 +#define mci_set_stop_pending(host) \
6112 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
6113 +#define mci_set_stop_error_pending(host) \
6114 + set_bit(EVENT_STOP_ERROR, &host->pending_events)
6115 +#define mci_set_dma_error_pending(host) \
6116 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
6117 +#define mci_set_card_detect_pending(host) \
6118 + set_bit(EVENT_CARD_DETECT, &host->pending_events)
6119 +
6120 +/* Clear bit macros for pending events */
6121 +#define mci_clear_cmd_pending(host) \
6122 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
6123 +#define mci_clear_cmd_error_pending(host) \
6124 + clear_bit(EVENT_CMD_ERROR, &host->pending_events)
6125 +#define mci_clear_data_pending(host) \
6126 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
6127 +#define mci_clear_data_error_pending(host) \
6128 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
6129 +#define mci_clear_stop_sent_pending(host) \
6130 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
6131 +#define mci_clear_stop_pending(host) \
6132 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
6133 +#define mci_clear_stop_error_pending(host) \
6134 + clear_bit(EVENT_STOP_ERROR, &host->pending_events)
6135 +#define mci_clear_dma_error_pending(host) \
6136 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
6137 +#define mci_clear_card_detect_pending(host) \
6138 + clear_bit(EVENT_CARD_DETECT, &host->pending_events)
6139 +
6140 +
6141 +#ifdef CONFIG_DEBUG_FS
6142 +#include <linux/debugfs.h>
6143 +
6144 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
6145 +
6146 +struct req_dbg_data {
6147 + unsigned int nbytes;
6148 + char str[DBG_REQ_BUF_SIZE];
6149 +};
6150 +
6151 +static int req_dbg_open(struct inode *inode, struct file *file)
6152 +{
6153 + struct atmel_mci *host;
6154 + struct mmc_request *mrq;
6155 + struct mmc_command *cmd, *stop;
6156 + struct mmc_data *data;
6157 + struct req_dbg_data *priv;
6158 + char *str;
6159 + unsigned long n = 0;
6160 +
6161 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
6162 + if (!priv)
6163 + return -ENOMEM;
6164 + str = priv->str;
6165 +
6166 + mutex_lock(&inode->i_mutex);
6167 + host = inode->i_private;
6168 +
6169 + spin_lock_irq(&host->mmc->lock);
6170 + mrq = host->mrq;
6171 + if (mrq) {
6172 + cmd = mrq->cmd;
6173 + data = mrq->data;
6174 + stop = mrq->stop;
6175 + n = snprintf(str, DBG_REQ_BUF_SIZE,
6176 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
6177 + cmd->opcode, cmd->arg, cmd->flags,
6178 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
6179 + cmd->resp[3], cmd->error);
6180 + if (n < DBG_REQ_BUF_SIZE && data)
6181 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
6182 + "DATA %u * %u (%u) %x (err %u)\n",
6183 + data->blocks, data->blksz,
6184 + data->bytes_xfered, data->flags,
6185 + data->error);
6186 + if (n < DBG_REQ_BUF_SIZE && stop)
6187 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
6188 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
6189 + stop->opcode, stop->arg, stop->flags,
6190 + stop->resp[0], stop->resp[1],
6191 + stop->resp[2], stop->resp[3],
6192 + stop->error);
6193 + }
6194 + spin_unlock_irq(&host->mmc->lock);
6195 + mutex_unlock(&inode->i_mutex);
6196 +
6197 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
6198 + file->private_data = priv;
6199 +
6200 + return 0;
6201 +}
6202 +
6203 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
6204 + size_t nbytes, loff_t *ppos)
6205 +{
6206 + struct req_dbg_data *priv = file->private_data;
6207 +
6208 + return simple_read_from_buffer(buf, nbytes, ppos,
6209 + priv->str, priv->nbytes);
6210 +}
6211 +
6212 +static int req_dbg_release(struct inode *inode, struct file *file)
6213 +{
6214 + kfree(file->private_data);
6215 + return 0;
6216 +}
6217 +
6218 +static const struct file_operations req_dbg_fops = {
6219 + .owner = THIS_MODULE,
6220 + .open = req_dbg_open,
6221 + .llseek = no_llseek,
6222 + .read = req_dbg_read,
6223 + .release = req_dbg_release,
6224 +};
6225 +
6226 +static int regs_dbg_open(struct inode *inode, struct file *file)
6227 +{
6228 + struct atmel_mci *host;
6229 + unsigned int i;
6230 + u32 *data;
6231 + int ret = -ENOMEM;
6232 +
6233 + mutex_lock(&inode->i_mutex);
6234 + host = inode->i_private;
6235 + data = kmalloc(inode->i_size, GFP_KERNEL);
6236 + if (!data)
6237 + goto out;
6238 +
6239 + spin_lock_irq(&host->mmc->lock);
6240 + for (i = 0; i < inode->i_size / 4; i++)
6241 + data[i] = __raw_readl(host->regs + i * 4);
6242 + spin_unlock_irq(&host->mmc->lock);
6243 +
6244 + file->private_data = data;
6245 + ret = 0;
6246 +
6247 +out:
6248 + mutex_unlock(&inode->i_mutex);
6249 +
6250 + return ret;
6251 +}
6252 +
6253 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
6254 + size_t nbytes, loff_t *ppos)
6255 +{
6256 + struct inode *inode = file->f_dentry->d_inode;
6257 + int ret;
6258 +
6259 + mutex_lock(&inode->i_mutex);
6260 + ret = simple_read_from_buffer(buf, nbytes, ppos,
6261 + file->private_data,
6262 + file->f_dentry->d_inode->i_size);
6263 + mutex_unlock(&inode->i_mutex);
6264 +
6265 + return ret;
6266 +}
6267 +
6268 +static int regs_dbg_release(struct inode *inode, struct file *file)
6269 +{
6270 + kfree(file->private_data);
6271 + return 0;
6272 +}
6273 +
6274 +static const struct file_operations regs_dbg_fops = {
6275 + .owner = THIS_MODULE,
6276 + .open = regs_dbg_open,
6277 + .llseek = generic_file_llseek,
6278 + .read = regs_dbg_read,
6279 + .release = regs_dbg_release,
6280 +};
6281 +
6282 +static void atmci_init_debugfs(struct atmel_mci *host)
6283 +{
6284 + struct mmc_host *mmc;
6285 + struct dentry *root, *regs;
6286 + struct resource *res;
6287 +
6288 + mmc = host->mmc;
6289 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
6290 + if (IS_ERR(root) || !root)
6291 + goto err_root;
6292 + host->debugfs_root = root;
6293 +
6294 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
6295 + if (!regs)
6296 + goto err_regs;
6297 +
6298 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
6299 + regs->d_inode->i_size = res->end - res->start + 1;
6300 + host->debugfs_regs = regs;
6301 +
6302 + host->debugfs_req = debugfs_create_file("req", 0400, root,
6303 + host, &req_dbg_fops);
6304 + if (!host->debugfs_req)
6305 + goto err_req;
6306 +
6307 + host->debugfs_pending_events
6308 + = debugfs_create_u32("pending_events", 0400, root,
6309 + (u32 *)&host->pending_events);
6310 + if (!host->debugfs_pending_events)
6311 + goto err_pending_events;
6312 +
6313 + host->debugfs_completed_events
6314 + = debugfs_create_u32("completed_events", 0400, root,
6315 + (u32 *)&host->completed_events);
6316 + if (!host->debugfs_completed_events)
6317 + goto err_completed_events;
6318 +
6319 + return;
6320 +
6321 +err_completed_events:
6322 + debugfs_remove(host->debugfs_pending_events);
6323 +err_pending_events:
6324 + debugfs_remove(host->debugfs_req);
6325 +err_req:
6326 + debugfs_remove(host->debugfs_regs);
6327 +err_regs:
6328 + debugfs_remove(host->debugfs_root);
6329 +err_root:
6330 + host->debugfs_root = NULL;
6331 + dev_err(&host->pdev->dev,
6332 + "failed to initialize debugfs for %s\n",
6333 + mmc_hostname(mmc));
6334 +}
6335 +
6336 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
6337 +{
6338 + if (host->debugfs_root) {
6339 + debugfs_remove(host->debugfs_completed_events);
6340 + debugfs_remove(host->debugfs_pending_events);
6341 + debugfs_remove(host->debugfs_req);
6342 + debugfs_remove(host->debugfs_regs);
6343 + debugfs_remove(host->debugfs_root);
6344 + host->debugfs_root = NULL;
6345 + }
6346 +}
6347 +#else
6348 +static inline void atmci_init_debugfs(struct atmel_mci *host)
6349 +{
6350 +
6351 +}
6352 +
6353 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
6354 +{
6355 +
6356 +}
6357 +#endif /* CONFIG_DEBUG_FS */
6358 +
6359 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
6360 + unsigned int ns)
6361 +{
6362 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
6363 +}
6364 +
6365 +static void atmci_set_timeout(struct atmel_mci *host,
6366 + struct mmc_data *data)
6367 +{
6368 + static unsigned dtomul_to_shift[] = {
6369 + 0, 4, 7, 8, 10, 12, 16, 20
6370 + };
6371 + unsigned timeout;
6372 + unsigned dtocyc, dtomul;
6373 +
6374 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
6375 +
6376 + for (dtomul = 0; dtomul < 8; dtomul++) {
6377 + unsigned shift = dtomul_to_shift[dtomul];
6378 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
6379 + if (dtocyc < 15)
6380 + break;
6381 + }
6382 +
6383 + if (dtomul >= 8) {
6384 + dtomul = 7;
6385 + dtocyc = 15;
6386 + }
6387 +
6388 + pr_debug("%s: setting timeout to %u cycles\n",
6389 + mmc_hostname(host->mmc),
6390 + dtocyc << dtomul_to_shift[dtomul]);
6391 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
6392 + | MCI_BF(DTOCYC, dtocyc)));
6393 +}
6394 +
6395 +/*
6396 + * Return mask with interrupt flags to be handled for this command.
6397 + */
6398 +static u32 atmci_prepare_command(struct mmc_host *mmc,
6399 + struct mmc_command *cmd,
6400 + u32 *cmd_flags)
6401 +{
6402 + u32 cmdr;
6403 + u32 iflags;
6404 +
6405 + cmd->error = MMC_ERR_NONE;
6406 +
6407 + cmdr = 0;
6408 + BUG_ON(MCI_BFEXT(CMDNB, cmdr) != 0);
6409 + cmdr = MCI_BFINS(CMDNB, cmd->opcode, cmdr);
6410 +
6411 + if (cmd->flags & MMC_RSP_PRESENT) {
6412 + if (cmd->flags & MMC_RSP_136)
6413 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
6414 + else
6415 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
6416 + }
6417 +
6418 + /*
6419 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
6420 + * it's too difficult to determine whether this is an ACMD or
6421 + * not. Better make it 64.
6422 + */
6423 + cmdr |= MCI_BIT(MAXLAT);
6424 +
6425 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
6426 + cmdr |= MCI_BIT(OPDCMD);
6427 +
6428 + iflags = MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS;
6429 + if (!(cmd->flags & MMC_RSP_CRC))
6430 + iflags &= ~MCI_BIT(RCRCE);
6431 +
6432 + pr_debug("%s: cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
6433 + mmc_hostname(mmc), cmd->opcode, cmd->arg, cmd->flags,
6434 + (unsigned long)cmdr);
6435 +
6436 + *cmd_flags = cmdr;
6437 + return iflags;
6438 +}
6439 +
6440 +static void atmci_start_command(struct atmel_mci *host,
6441 + struct mmc_command *cmd,
6442 + u32 cmd_flags)
6443 +{
6444 + WARN_ON(host->cmd);
6445 + host->cmd = cmd;
6446 +
6447 + mci_writel(host, ARGR, cmd->arg);
6448 + mci_writel(host, CMDR, cmd_flags);
6449 +
6450 + if (cmd->data)
6451 + dma_start_request(host->dma.req.req.dmac,
6452 + host->dma.req.req.channel);
6453 +}
6454 +
6455 +/*
6456 + * Returns a mask of flags to be set in the command register when the
6457 + * command to start the transfer is to be sent.
6458 + */
6459 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
6460 +{
6461 + struct atmel_mci *host = mmc_priv(mmc);
6462 + u32 cmd_flags;
6463 +
6464 + WARN_ON(host->data);
6465 + host->data = data;
6466 +
6467 + atmci_set_timeout(host, data);
6468 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
6469 + | MCI_BF(BLKLEN, data->blksz)));
6470 + host->dma.req.block_size = data->blksz;
6471 + host->dma.req.nr_blocks = data->blocks;
6472 +
6473 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
6474 + if (data->flags & MMC_DATA_STREAM)
6475 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
6476 + else if (data->blocks > 1)
6477 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
6478 + else
6479 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
6480 +
6481 + if (data->flags & MMC_DATA_READ) {
6482 + cmd_flags |= MCI_BIT(TRDIR);
6483 + host->dma.req.nr_sg
6484 + = dma_map_sg(&host->pdev->dev, data->sg,
6485 + data->sg_len, DMA_FROM_DEVICE);
6486 + host->dma.req.periph_id = host->dma.rx_periph_id;
6487 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
6488 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
6489 + } else {
6490 + host->dma.req.nr_sg
6491 + = dma_map_sg(&host->pdev->dev, data->sg,
6492 + data->sg_len, DMA_TO_DEVICE);
6493 + host->dma.req.periph_id = host->dma.tx_periph_id;
6494 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
6495 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
6496 + }
6497 + host->dma.req.sg = data->sg;
6498 +
6499 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
6500 +
6501 + return cmd_flags;
6502 +}
6503 +
6504 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
6505 +{
6506 + struct atmel_mci *host = mmc_priv(mmc);
6507 + struct mmc_data *data = mrq->data;
6508 + u32 iflags;
6509 + u32 cmdflags = 0;
6510 +
6511 + iflags = mci_readl(host, IMR);
6512 + if (iflags)
6513 + printk("WARNING: IMR=0x%08x\n", mci_readl(host, IMR));
6514 +
6515 + WARN_ON(host->mrq != NULL);
6516 + host->mrq = mrq;
6517 + host->pending_events = 0;
6518 + host->completed_events = 0;
6519 +
6520 + iflags = atmci_prepare_command(mmc, mrq->cmd, &cmdflags);
6521 +
6522 + if (mrq->stop) {
6523 + BUG_ON(!data);
6524 +
6525 + host->stop_iflags = atmci_prepare_command(mmc, mrq->stop,
6526 + &host->stop_cmdr);
6527 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
6528 + if (!(data->flags & MMC_DATA_WRITE))
6529 + host->stop_cmdr |= MCI_BIT(TRDIR);
6530 + if (data->flags & MMC_DATA_STREAM)
6531 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
6532 + else
6533 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
6534 + }
6535 + if (data) {
6536 + cmdflags |= atmci_prepare_data(mmc, data);
6537 + iflags |= MCI_DATA_ERROR_FLAGS;
6538 + }
6539 +
6540 + atmci_start_command(host, mrq->cmd, cmdflags);
6541 + mci_writel(host, IER, iflags);
6542 +}
6543 +
6544 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
6545 +{
6546 + struct atmel_mci *host = mmc_priv(mmc);
6547 +
6548 + if (ios->clock) {
6549 + u32 clkdiv;
6550 +
6551 + clkdiv = host->bus_hz / (2 * ios->clock) - 1;
6552 + if (clkdiv > 255)
6553 + clkdiv = 255;
6554 + mci_writel(host, MR, (clkdiv
6555 + | MCI_BIT(WRPROOF)
6556 + | MCI_BIT(RDPROOF)));
6557 + }
6558 +
6559 + switch (ios->bus_width) {
6560 + case MMC_BUS_WIDTH_1:
6561 + mci_writel(host, SDCR, 0);
6562 + break;
6563 + case MMC_BUS_WIDTH_4:
6564 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
6565 + break;
6566 + }
6567 +
6568 + switch (ios->power_mode) {
6569 + case MMC_POWER_OFF:
6570 + mci_writel(host, CR, MCI_BIT(MCIDIS));
6571 + break;
6572 + case MMC_POWER_UP:
6573 + mci_writel(host, CR, MCI_BIT(SWRST));
6574 + break;
6575 + case MMC_POWER_ON:
6576 + mci_writel(host, CR, MCI_BIT(MCIEN));
6577 + break;
6578 + }
6579 +}
6580 +
6581 +static int atmci_get_ro(struct mmc_host *mmc)
6582 +{
6583 + int read_only = 0;
6584 + struct atmel_mci *host = mmc_priv(mmc);
6585 +
6586 + if (host->wp_pin >= 0) {
6587 + read_only = gpio_get_value(host->wp_pin);
6588 + pr_debug("%s: card is %s\n", mmc_hostname(mmc),
6589 + read_only ? "read-only" : "read-write");
6590 + } else {
6591 + pr_debug("%s: no pin for checking read-only switch."
6592 + " Assuming write-enable.\n", mmc_hostname(mmc));
6593 + }
6594 +
6595 + return read_only;
6596 +}
6597 +
6598 +static struct mmc_host_ops atmci_ops = {
6599 + .request = atmci_request,
6600 + .set_ios = atmci_set_ios,
6601 + .get_ro = atmci_get_ro,
6602 +};
6603 +
6604 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
6605 +{
6606 + struct atmel_mci *host = mmc_priv(mmc);
6607 +
6608 + WARN_ON(host->cmd || host->data);
6609 + host->mrq = NULL;
6610 +
6611 + mmc_request_done(mmc, mrq);
6612 +}
6613 +
6614 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
6615 + u32 flags)
6616 +{
6617 + struct atmel_mci *host = mmc_priv(mmc);
6618 +
6619 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
6620 + mci_writel(host, IER, host->stop_iflags);
6621 +}
6622 +
6623 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
6624 +{
6625 + host->data = NULL;
6626 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
6627 + ((data->flags & MMC_DATA_WRITE)
6628 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
6629 +
6630 + /*
6631 + * Data might complete before command for very short transfers
6632 + * (like READ_SCR)
6633 + */
6634 + if (mci_cmd_is_complete(host)
6635 + && (!data->stop || mci_stop_is_complete(host)))
6636 + atmci_request_end(host->mmc, data->mrq);
6637 +}
6638 +
6639 +static void atmci_command_error(struct mmc_host *mmc,
6640 + struct mmc_command *cmd,
6641 + u32 status)
6642 +{
6643 + pr_debug("%s: command error: status=0x%08x\n",
6644 + mmc_hostname(mmc), status);
6645 +
6646 + if (status & MCI_BIT(RTOE))
6647 + cmd->error = MMC_ERR_TIMEOUT;
6648 + else if (status & MCI_BIT(RCRCE))
6649 + cmd->error = MMC_ERR_BADCRC;
6650 + else
6651 + cmd->error = MMC_ERR_FAILED;
6652 +}
6653 +
6654 +static void atmci_tasklet_func(unsigned long priv)
6655 +{
6656 + struct mmc_host *mmc = (struct mmc_host *)priv;
6657 + struct atmel_mci *host = mmc_priv(mmc);
6658 + struct mmc_request *mrq = host->mrq;
6659 + struct mmc_data *data = host->data;
6660 +
6661 + pr_debug("atmci_tasklet: pending/completed/mask %lx/%lx/%x\n",
6662 + host->pending_events, host->completed_events,
6663 + mci_readl(host, IMR));
6664 +
6665 + if (mci_clear_cmd_error_is_pending(host)) {
6666 + struct mmc_command *cmd;
6667 +
6668 + mci_set_cmd_error_complete(host);
6669 + mci_clear_cmd_pending(host);
6670 + cmd = host->mrq->cmd;
6671 +
6672 + if (cmd->data) {
6673 + dma_stop_request(host->dma.req.req.dmac,
6674 + host->dma.req.req.channel);
6675 + host->data = NULL;
6676 + }
6677 +
6678 + atmci_command_error(mmc, cmd, host->error_status);
6679 + atmci_request_end(mmc, cmd->mrq);
6680 + }
6681 + if (mci_clear_stop_error_is_pending(host)) {
6682 + mci_set_stop_error_complete(host);
6683 + mci_clear_stop_pending(host);
6684 + atmci_command_error(mmc, host->mrq->stop,
6685 + host->error_status);
6686 + if (!host->data)
6687 + atmci_request_end(mmc, host->mrq);
6688 + }
6689 + if (mci_clear_cmd_is_pending(host)) {
6690 + mci_set_cmd_complete(host);
6691 + if (!mrq->data || mci_data_is_complete(host)
6692 + || mci_data_error_is_complete(host))
6693 + atmci_request_end(mmc, mrq);
6694 + }
6695 + if (mci_clear_stop_is_pending(host)) {
6696 + mci_set_stop_complete(host);
6697 + if (mci_data_is_complete(host)
6698 + || mci_data_error_is_complete(host))
6699 + atmci_request_end(mmc, mrq);
6700 + }
6701 + if (mci_clear_dma_error_is_pending(host)) {
6702 + mci_set_dma_error_complete(host);
6703 + mci_clear_data_pending(host);
6704 +
6705 + /* DMA controller got bus error => invalid address */
6706 + data->error = MMC_ERR_INVALID;
6707 +
6708 + printk(KERN_DEBUG "%s: dma error after %u bytes xfered\n",
6709 + mmc_hostname(mmc), host->data->bytes_xfered);
6710 +
6711 + if (data->stop
6712 + && !mci_set_stop_sent_is_completed(host))
6713 + /* TODO: Check if card is still present */
6714 + send_stop_cmd(host->mmc, data, 0);
6715 +
6716 + atmci_data_complete(host, data);
6717 + }
6718 + if (mci_clear_data_error_is_pending(host)) {
6719 + u32 status = host->error_status;
6720 +
6721 + mci_set_data_error_complete(host);
6722 + mci_clear_data_pending(host);
6723 +
6724 + dma_stop_request(host->dma.req.req.dmac,
6725 + host->dma.req.req.channel);
6726 +
6727 + printk(KERN_DEBUG "%s: data error: status=0x%08x\n",
6728 + mmc_hostname(host->mmc), status);
6729 +
6730 + if (status & MCI_BIT(DCRCE)) {
6731 + printk(KERN_DEBUG "%s: Data CRC error\n",
6732 + mmc_hostname(host->mmc));
6733 + data->error = MMC_ERR_BADCRC;
6734 + } else if (status & MCI_BIT(DTOE)) {
6735 + printk(KERN_DEBUG "%s: Data Timeout error\n",
6736 + mmc_hostname(host->mmc));
6737 + data->error = MMC_ERR_TIMEOUT;
6738 + } else {
6739 + printk(KERN_DEBUG "%s: Data FIFO error\n",
6740 + mmc_hostname(host->mmc));
6741 + data->error = MMC_ERR_FIFO;
6742 + }
6743 + printk(KERN_DEBUG "%s: Bytes xfered: %u\n",
6744 + mmc_hostname(host->mmc), data->bytes_xfered);
6745 +
6746 + if (data->stop
6747 + && !mci_set_stop_sent_is_completed(host))
6748 + /* TODO: Check if card is still present */
6749 + send_stop_cmd(host->mmc, data, 0);
6750 +
6751 + atmci_data_complete(host, data);
6752 + }
6753 + if (mci_clear_data_is_pending(host)) {
6754 + mci_set_data_complete(host);
6755 + data->bytes_xfered = data->blocks * data->blksz;
6756 + atmci_data_complete(host, data);
6757 + }
6758 + if (mci_clear_card_detect_is_pending(host)) {
6759 + /* Reset controller if card is gone */
6760 + if (!host->present) {
6761 + mci_writel(host, CR, MCI_BIT(SWRST));
6762 + mci_writel(host, IDR, ~0UL);
6763 + mci_writel(host, CR, MCI_BIT(MCIEN));
6764 + }
6765 +
6766 + /* Clean up queue if present */
6767 + if (mrq) {
6768 + if (!mci_cmd_is_complete(host)
6769 + && !mci_cmd_error_is_complete(host)) {
6770 + mrq->cmd->error = MMC_ERR_TIMEOUT;
6771 + }
6772 + if (mrq->data && !mci_data_is_complete(host)
6773 + && !mci_data_error_is_complete(host)) {
6774 + dma_stop_request(host->dma.req.req.dmac,
6775 + host->dma.req.req.channel);
6776 + host->data->error = MMC_ERR_TIMEOUT;
6777 + atmci_data_complete(host, data);
6778 + }
6779 + if (mrq->stop && !mci_stop_is_complete(host)
6780 + && !mci_stop_error_is_complete(host)) {
6781 + mrq->stop->error = MMC_ERR_TIMEOUT;
6782 + }
6783 +
6784 + host->cmd = NULL;
6785 + atmci_request_end(mmc, mrq);
6786 + }
6787 + mmc_detect_change(host->mmc, msecs_to_jiffies(100));
6788 + }
6789 +}
6790 +
6791 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
6792 +{
6793 + struct atmel_mci *host = mmc_priv(mmc);
6794 + struct mmc_command *cmd = host->cmd;
6795 +
6796 + /*
6797 + * Read the response now so that we're free to send a new
6798 + * command immediately.
6799 + */
6800 + cmd->resp[0] = mci_readl(host, RSPR);
6801 + cmd->resp[1] = mci_readl(host, RSPR);
6802 + cmd->resp[2] = mci_readl(host, RSPR);
6803 + cmd->resp[3] = mci_readl(host, RSPR);
6804 +
6805 + mci_writel(host, IDR, MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS);
6806 + host->cmd = NULL;
6807 +
6808 + if (mci_stop_sent_is_complete(host))
6809 + mci_set_stop_pending(host);
6810 + else
6811 + mci_set_cmd_pending(host);
6812 +
6813 + tasklet_schedule(&host->tasklet);
6814 +}
6815 +
6816 +static void atmci_xfer_complete(struct dma_request *_req)
6817 +{
6818 + struct dma_request_sg *req = to_dma_request_sg(_req);
6819 + struct atmel_mci_dma *dma;
6820 + struct atmel_mci *host;
6821 + struct mmc_data *data;
6822 +
6823 + dma = container_of(req, struct atmel_mci_dma, req);
6824 + host = container_of(dma, struct atmel_mci, dma);
6825 + data = host->data;
6826 +
6827 + if (data->stop && !mci_set_stop_sent_is_completed(host))
6828 + send_stop_cmd(host->mmc, data, 0);
6829 +
6830 + if (data->flags & MMC_DATA_READ) {
6831 + mci_writel(host, IDR, MCI_DATA_ERROR_FLAGS);
6832 + mci_set_data_pending(host);
6833 + tasklet_schedule(&host->tasklet);
6834 + } else {
6835 + /*
6836 + * For the WRITE case, wait for NOTBUSY. This function
6837 + * is called when everything has been written to the
6838 + * controller, not when the card is done programming.
6839 + */
6840 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
6841 + }
6842 +}
6843 +
6844 +static void atmci_dma_error(struct dma_request *_req)
6845 +{
6846 + struct dma_request_sg *req = to_dma_request_sg(_req);
6847 + struct atmel_mci_dma *dma;
6848 + struct atmel_mci *host;
6849 +
6850 + dma = container_of(req, struct atmel_mci_dma, req);
6851 + host = container_of(dma, struct atmel_mci, dma);
6852 +
6853 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
6854 + | MCI_DATA_ERROR_FLAGS));
6855 +
6856 + mci_set_dma_error_pending(host);
6857 + tasklet_schedule(&host->tasklet);
6858 +}
6859 +
6860 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
6861 +{
6862 + struct mmc_host *mmc = dev_id;
6863 + struct atmel_mci *host = mmc_priv(mmc);
6864 + u32 status, mask, pending;
6865 +
6866 + spin_lock(&mmc->lock);
6867 +
6868 + status = mci_readl(host, SR);
6869 + mask = mci_readl(host, IMR);
6870 + pending = status & mask;
6871 +
6872 + do {
6873 + if (pending & MCI_CMD_ERROR_FLAGS) {
6874 + mci_writel(host, IDR, (MCI_BIT(CMDRDY)
6875 + | MCI_BIT(NOTBUSY)
6876 + | MCI_CMD_ERROR_FLAGS
6877 + | MCI_DATA_ERROR_FLAGS));
6878 + host->error_status = status;
6879 + host->cmd = NULL;
6880 + if (mci_stop_sent_is_complete(host))
6881 + mci_set_stop_error_pending(host);
6882 + else
6883 + mci_set_cmd_error_pending(host);
6884 + tasklet_schedule(&host->tasklet);
6885 + break;
6886 + }
6887 + if (pending & MCI_DATA_ERROR_FLAGS) {
6888 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
6889 + | MCI_DATA_ERROR_FLAGS));
6890 + host->error_status = status;
6891 + mci_set_data_error_pending(host);
6892 + tasklet_schedule(&host->tasklet);
6893 + break;
6894 + }
6895 + if (pending & MCI_BIT(CMDRDY))
6896 + atmci_cmd_interrupt(mmc, status);
6897 + if (pending & MCI_BIT(NOTBUSY)) {
6898 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
6899 + | MCI_DATA_ERROR_FLAGS));
6900 + mci_set_data_pending(host);
6901 + tasklet_schedule(&host->tasklet);
6902 + }
6903 +
6904 + status = mci_readl(host, SR);
6905 + mask = mci_readl(host, IMR);
6906 + pending = status & mask;
6907 + } while (pending);
6908 +
6909 + spin_unlock(&mmc->lock);
6910 +
6911 + return IRQ_HANDLED;
6912 +}
6913 +
6914 +static irqreturn_t atmci_detect_change(int irq, void *dev_id)
6915 +{
6916 + struct mmc_host *mmc = dev_id;
6917 + struct atmel_mci *host = mmc_priv(mmc);
6918 +
6919 + int present = !gpio_get_value(irq_to_gpio(irq));
6920 +
6921 + if (present != host->present) {
6922 + pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
6923 + present ? "inserted" : "removed");
6924 + host->present = present;
6925 + mci_set_card_detect_pending(host);
6926 + tasklet_schedule(&host->tasklet);
6927 + }
6928 + return IRQ_HANDLED;
6929 +}
6930 +
6931 +static int __devinit atmci_probe(struct platform_device *pdev)
6932 +{
6933 + struct mci_platform_data *board;
6934 + struct atmel_mci *host;
6935 + struct mmc_host *mmc;
6936 + struct resource *regs;
6937 + int irq;
6938 + int ret;
6939 +
6940 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6941 + if (!regs)
6942 + return -ENXIO;
6943 + irq = platform_get_irq(pdev, 0);
6944 + if (irq < 0)
6945 + return irq;
6946 +
6947 + board = pdev->dev.platform_data;
6948 +
6949 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
6950 + if (!mmc)
6951 + return -ENOMEM;
6952 +
6953 + host = mmc_priv(mmc);
6954 + host->pdev = pdev;
6955 + host->mmc = mmc;
6956 + if (board) {
6957 + host->detect_pin = board->detect_pin;
6958 + host->wp_pin = board->wp_pin;
6959 + } else {
6960 + host->detect_pin = -1;
6961 + host->detect_pin = -1;
6962 + }
6963 +
6964 + host->mck = clk_get(&pdev->dev, "mci_clk");
6965 + if (IS_ERR(host->mck)) {
6966 + ret = PTR_ERR(host->mck);
6967 + goto out_free_host;
6968 + }
6969 + clk_enable(host->mck);
6970 +
6971 + ret = -ENOMEM;
6972 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
6973 + if (!host->regs)
6974 + goto out_disable_clk;
6975 +
6976 + host->bus_hz = clk_get_rate(host->mck);
6977 + host->mapbase = regs->start;
6978 +
6979 + mmc->ops = &atmci_ops;
6980 + mmc->f_min = (host->bus_hz + 511) / 512;
6981 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
6982 + mmc->ocr_avail = 0x00100000;
6983 + mmc->caps |= MMC_CAP_4_BIT_DATA;
6984 +
6985 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
6986 +
6987 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
6988 + if (ret)
6989 + goto out_unmap;
6990 +
6991 + /* Assume card is present if we don't have a detect pin */
6992 + host->present = 1;
6993 + if (host->detect_pin >= 0) {
6994 + if (gpio_request(host->detect_pin, "mmc_detect")) {
6995 + printk(KERN_WARNING "%s: no detect pin available\n",
6996 + mmc_hostname(host->mmc));
6997 + host->detect_pin = -1;
6998 + } else {
6999 + host->present = !gpio_get_value(host->detect_pin);
7000 + }
7001 + }
7002 + if (host->wp_pin >= 0) {
7003 + if (gpio_request(host->wp_pin, "mmc_wp")) {
7004 + printk(KERN_WARNING "%s: no WP pin available\n",
7005 + mmc_hostname(host->mmc));
7006 + host->wp_pin = -1;
7007 + }
7008 + }
7009 +
7010 + /* TODO: Get this information from platform data */
7011 + ret = -ENOMEM;
7012 + host->dma.req.req.dmac = find_dma_controller(0);
7013 + if (!host->dma.req.req.dmac) {
7014 + printk(KERN_ERR
7015 + "mmci: No DMA controller available, aborting\n");
7016 + goto out_free_irq;
7017 + }
7018 + ret = dma_alloc_channel(host->dma.req.req.dmac);
7019 + if (ret < 0) {
7020 + printk(KERN_ERR
7021 + "mmci: Unable to allocate DMA channel, aborting\n");
7022 + goto out_free_irq;
7023 + }
7024 + host->dma.req.req.channel = ret;
7025 + host->dma.req.width = DMA_WIDTH_32BIT;
7026 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
7027 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
7028 + host->dma.req.req.error = atmci_dma_error;
7029 + host->dma.rx_periph_id = 0;
7030 + host->dma.tx_periph_id = 1;
7031 +
7032 + mci_writel(host, CR, MCI_BIT(SWRST));
7033 + mci_writel(host, IDR, ~0UL);
7034 + mci_writel(host, CR, MCI_BIT(MCIEN));
7035 +
7036 + platform_set_drvdata(pdev, host);
7037 +
7038 + mmc_add_host(mmc);
7039 +
7040 + if (host->detect_pin >= 0) {
7041 + ret = request_irq(gpio_to_irq(host->detect_pin),
7042 + atmci_detect_change,
7043 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
7044 + DRIVER_NAME, mmc);
7045 + if (ret) {
7046 + printk(KERN_ERR
7047 + "%s: could not request IRQ %d for detect pin\n",
7048 + mmc_hostname(mmc),
7049 + gpio_to_irq(host->detect_pin));
7050 + gpio_free(host->detect_pin);
7051 + host->detect_pin = -1;
7052 + }
7053 + }
7054 +
7055 + printk(KERN_INFO "%s: Atmel MCI controller at 0x%08lx irq %d\n",
7056 + mmc_hostname(mmc), host->mapbase, irq);
7057 +
7058 + atmci_init_debugfs(host);
7059 +
7060 + return 0;
7061 +
7062 +out_free_irq:
7063 + if (host->detect_pin >= 0)
7064 + gpio_free(host->detect_pin);
7065 + if (host->wp_pin >= 0)
7066 + gpio_free(host->wp_pin);
7067 + free_irq(irq, mmc);
7068 +out_unmap:
7069 + iounmap(host->regs);
7070 +out_disable_clk:
7071 + clk_disable(host->mck);
7072 + clk_put(host->mck);
7073 +out_free_host:
7074 + mmc_free_host(mmc);
7075 + return ret;
7076 +}
7077 +
7078 +static int __devexit atmci_remove(struct platform_device *pdev)
7079 +{
7080 + struct atmel_mci *host = platform_get_drvdata(pdev);
7081 +
7082 + platform_set_drvdata(pdev, NULL);
7083 +
7084 + if (host) {
7085 + atmci_cleanup_debugfs(host);
7086 +
7087 + if (host->detect_pin >= 0) {
7088 + free_irq(gpio_to_irq(host->detect_pin), host->mmc);
7089 + cancel_delayed_work(&host->mmc->detect);
7090 + gpio_free(host->detect_pin);
7091 + }
7092 +
7093 + mmc_remove_host(host->mmc);
7094 +
7095 + mci_writel(host, IDR, ~0UL);
7096 + mci_writel(host, CR, MCI_BIT(MCIDIS));
7097 + mci_readl(host, SR);
7098 +
7099 + dma_release_channel(host->dma.req.req.dmac,
7100 + host->dma.req.req.channel);
7101 +
7102 + if (host->wp_pin >= 0)
7103 + gpio_free(host->wp_pin);
7104 +
7105 + free_irq(platform_get_irq(pdev, 0), host->mmc);
7106 + iounmap(host->regs);
7107 +
7108 + clk_disable(host->mck);
7109 + clk_put(host->mck);
7110 +
7111 + mmc_free_host(host->mmc);
7112 + }
7113 + return 0;
7114 +}
7115 +
7116 +static struct platform_driver atmci_driver = {
7117 + .probe = atmci_probe,
7118 + .remove = __devexit_p(atmci_remove),
7119 + .driver = {
7120 + .name = DRIVER_NAME,
7121 + },
7122 +};
7123 +
7124 +static int __init atmci_init(void)
7125 +{
7126 + return platform_driver_register(&atmci_driver);
7127 +}
7128 +
7129 +static void __exit atmci_exit(void)
7130 +{
7131 + platform_driver_unregister(&atmci_driver);
7132 +}
7133 +
7134 +module_init(atmci_init);
7135 +module_exit(atmci_exit);
7136 +
7137 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
7138 +MODULE_LICENSE("GPL");
7139 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/atmel-mci.h linux-avr32.git/drivers/mmc/host/atmel-mci.h
7140 --- linux-2.6.22.1/drivers/mmc/host/atmel-mci.h 1970-01-01 01:00:00.000000000 +0100
7141 +++ linux-avr32.git/drivers/mmc/host/atmel-mci.h 2007-07-12 14:00:03.000000000 +0200
7142 @@ -0,0 +1,192 @@
7143 +/*
7144 + * Atmel MultiMedia Card Interface driver
7145 + *
7146 + * Copyright (C) 2004-2006 Atmel Corporation
7147 + *
7148 + * This program is free software; you can redistribute it and/or modify
7149 + * it under the terms of the GNU General Public License version 2 as
7150 + * published by the Free Software Foundation.
7151 + */
7152 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
7153 +#define __DRIVERS_MMC_ATMEL_MCI_H__
7154 +
7155 +/* MCI register offsets */
7156 +#define MCI_CR 0x0000
7157 +#define MCI_MR 0x0004
7158 +#define MCI_DTOR 0x0008
7159 +#define MCI_SDCR 0x000c
7160 +#define MCI_ARGR 0x0010
7161 +#define MCI_CMDR 0x0014
7162 +#define MCI_BLKR 0x0018
7163 +#define MCI_RSPR 0x0020
7164 +#define MCI_RSPR1 0x0024
7165 +#define MCI_RSPR2 0x0028
7166 +#define MCI_RSPR3 0x002c
7167 +#define MCI_RDR 0x0030
7168 +#define MCI_TDR 0x0034
7169 +#define MCI_SR 0x0040
7170 +#define MCI_IER 0x0044
7171 +#define MCI_IDR 0x0048
7172 +#define MCI_IMR 0x004c
7173 +
7174 +/* Bitfields in CR */
7175 +#define MCI_MCIEN_OFFSET 0
7176 +#define MCI_MCIEN_SIZE 1
7177 +#define MCI_MCIDIS_OFFSET 1
7178 +#define MCI_MCIDIS_SIZE 1
7179 +#define MCI_PWSEN_OFFSET 2
7180 +#define MCI_PWSEN_SIZE 1
7181 +#define MCI_PWSDIS_OFFSET 3
7182 +#define MCI_PWSDIS_SIZE 1
7183 +#define MCI_SWRST_OFFSET 7
7184 +#define MCI_SWRST_SIZE 1
7185 +
7186 +/* Bitfields in MR */
7187 +#define MCI_CLKDIV_OFFSET 0
7188 +#define MCI_CLKDIV_SIZE 8
7189 +#define MCI_PWSDIV_OFFSET 8
7190 +#define MCI_PWSDIV_SIZE 3
7191 +#define MCI_RDPROOF_OFFSET 11
7192 +#define MCI_RDPROOF_SIZE 1
7193 +#define MCI_WRPROOF_OFFSET 12
7194 +#define MCI_WRPROOF_SIZE 1
7195 +#define MCI_DMAPADV_OFFSET 14
7196 +#define MCI_DMAPADV_SIZE 1
7197 +#define MCI_BLKLEN_OFFSET 16
7198 +#define MCI_BLKLEN_SIZE 16
7199 +
7200 +/* Bitfields in DTOR */
7201 +#define MCI_DTOCYC_OFFSET 0
7202 +#define MCI_DTOCYC_SIZE 4
7203 +#define MCI_DTOMUL_OFFSET 4
7204 +#define MCI_DTOMUL_SIZE 3
7205 +
7206 +/* Bitfields in SDCR */
7207 +#define MCI_SDCSEL_OFFSET 0
7208 +#define MCI_SDCSEL_SIZE 4
7209 +#define MCI_SDCBUS_OFFSET 7
7210 +#define MCI_SDCBUS_SIZE 1
7211 +
7212 +/* Bitfields in ARGR */
7213 +#define MCI_ARG_OFFSET 0
7214 +#define MCI_ARG_SIZE 32
7215 +
7216 +/* Bitfields in CMDR */
7217 +#define MCI_CMDNB_OFFSET 0
7218 +#define MCI_CMDNB_SIZE 6
7219 +#define MCI_RSPTYP_OFFSET 6
7220 +#define MCI_RSPTYP_SIZE 2
7221 +#define MCI_SPCMD_OFFSET 8
7222 +#define MCI_SPCMD_SIZE 3
7223 +#define MCI_OPDCMD_OFFSET 11
7224 +#define MCI_OPDCMD_SIZE 1
7225 +#define MCI_MAXLAT_OFFSET 12
7226 +#define MCI_MAXLAT_SIZE 1
7227 +#define MCI_TRCMD_OFFSET 16
7228 +#define MCI_TRCMD_SIZE 2
7229 +#define MCI_TRDIR_OFFSET 18
7230 +#define MCI_TRDIR_SIZE 1
7231 +#define MCI_TRTYP_OFFSET 19
7232 +#define MCI_TRTYP_SIZE 2
7233 +
7234 +/* Bitfields in BLKR */
7235 +#define MCI_BCNT_OFFSET 0
7236 +#define MCI_BCNT_SIZE 16
7237 +
7238 +/* Bitfields in RSPRn */
7239 +#define MCI_RSP_OFFSET 0
7240 +#define MCI_RSP_SIZE 32
7241 +
7242 +/* Bitfields in SR/IER/IDR/IMR */
7243 +#define MCI_CMDRDY_OFFSET 0
7244 +#define MCI_CMDRDY_SIZE 1
7245 +#define MCI_RXRDY_OFFSET 1
7246 +#define MCI_RXRDY_SIZE 1
7247 +#define MCI_TXRDY_OFFSET 2
7248 +#define MCI_TXRDY_SIZE 1
7249 +#define MCI_BLKE_OFFSET 3
7250 +#define MCI_BLKE_SIZE 1
7251 +#define MCI_DTIP_OFFSET 4
7252 +#define MCI_DTIP_SIZE 1
7253 +#define MCI_NOTBUSY_OFFSET 5
7254 +#define MCI_NOTBUSY_SIZE 1
7255 +#define MCI_ENDRX_OFFSET 6
7256 +#define MCI_ENDRX_SIZE 1
7257 +#define MCI_ENDTX_OFFSET 7
7258 +#define MCI_ENDTX_SIZE 1
7259 +#define MCI_RXBUFF_OFFSET 14
7260 +#define MCI_RXBUFF_SIZE 1
7261 +#define MCI_TXBUFE_OFFSET 15
7262 +#define MCI_TXBUFE_SIZE 1
7263 +#define MCI_RINDE_OFFSET 16
7264 +#define MCI_RINDE_SIZE 1
7265 +#define MCI_RDIRE_OFFSET 17
7266 +#define MCI_RDIRE_SIZE 1
7267 +#define MCI_RCRCE_OFFSET 18
7268 +#define MCI_RCRCE_SIZE 1
7269 +#define MCI_RENDE_OFFSET 19
7270 +#define MCI_RENDE_SIZE 1
7271 +#define MCI_RTOE_OFFSET 20
7272 +#define MCI_RTOE_SIZE 1
7273 +#define MCI_DCRCE_OFFSET 21
7274 +#define MCI_DCRCE_SIZE 1
7275 +#define MCI_DTOE_OFFSET 22
7276 +#define MCI_DTOE_SIZE 1
7277 +#define MCI_OVRE_OFFSET 30
7278 +#define MCI_OVRE_SIZE 1
7279 +#define MCI_UNRE_OFFSET 31
7280 +#define MCI_UNRE_SIZE 1
7281 +
7282 +/* Constants for DTOMUL */
7283 +#define MCI_DTOMUL_1_CYCLE 0
7284 +#define MCI_DTOMUL_16_CYCLES 1
7285 +#define MCI_DTOMUL_128_CYCLES 2
7286 +#define MCI_DTOMUL_256_CYCLES 3
7287 +#define MCI_DTOMUL_1024_CYCLES 4
7288 +#define MCI_DTOMUL_4096_CYCLES 5
7289 +#define MCI_DTOMUL_65536_CYCLES 6
7290 +#define MCI_DTOMUL_1048576_CYCLES 7
7291 +
7292 +/* Constants for RSPTYP */
7293 +#define MCI_RSPTYP_NO_RESP 0
7294 +#define MCI_RSPTYP_48_BIT 1
7295 +#define MCI_RSPTYP_136_BIT 2
7296 +
7297 +/* Constants for SPCMD */
7298 +#define MCI_SPCMD_NO_SPEC_CMD 0
7299 +#define MCI_SPCMD_INIT_CMD 1
7300 +#define MCI_SPCMD_SYNC_CMD 2
7301 +#define MCI_SPCMD_INT_CMD 4
7302 +#define MCI_SPCMD_INT_RESP 5
7303 +
7304 +/* Constants for TRCMD */
7305 +#define MCI_TRCMD_NO_TRANS 0
7306 +#define MCI_TRCMD_START_TRANS 1
7307 +#define MCI_TRCMD_STOP_TRANS 2
7308 +
7309 +/* Constants for TRTYP */
7310 +#define MCI_TRTYP_BLOCK 0
7311 +#define MCI_TRTYP_MULTI_BLOCK 1
7312 +#define MCI_TRTYP_STREAM 2
7313 +
7314 +/* Bit manipulation macros */
7315 +#define MCI_BIT(name) \
7316 + (1 << MCI_##name##_OFFSET)
7317 +#define MCI_BF(name,value) \
7318 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
7319 + << MCI_##name##_OFFSET)
7320 +#define MCI_BFEXT(name,value) \
7321 + (((value) >> MCI_##name##_OFFSET) \
7322 + & ((1 << MCI_##name##_SIZE) - 1))
7323 +#define MCI_BFINS(name,value,old) \
7324 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
7325 + << MCI_##name##_OFFSET)) \
7326 + | MCI_BF(name,value))
7327 +
7328 +/* Register access macros */
7329 +#define mci_readl(port,reg) \
7330 + __raw_readl((port)->regs + MCI_##reg)
7331 +#define mci_writel(port,reg,value) \
7332 + __raw_writel((value), (port)->regs + MCI_##reg)
7333 +
7334 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
7335 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/Kconfig linux-avr32.git/drivers/mmc/host/Kconfig
7336 --- linux-2.6.22.1/drivers/mmc/host/Kconfig 2007-07-10 20:56:30.000000000 +0200
7337 +++ linux-avr32.git/drivers/mmc/host/Kconfig 2007-07-12 14:00:03.000000000 +0200
7338 @@ -74,6 +74,16 @@
7339
7340 If unsure, say N.
7341
7342 +config MMC_ATMELMCI
7343 + tristate "Atmel Multimedia Card Interface support"
7344 + depends on AVR32 && MMC
7345 + help
7346 + This selects the Atmel Multimedia Card Interface. If you have
7347 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
7348 + slot, say Y or M here.
7349 +
7350 + If unsure, say N.
7351 +
7352 config MMC_IMX
7353 tristate "Motorola i.MX Multimedia Card Interface support"
7354 depends on ARCH_IMX
7355 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/Makefile linux-avr32.git/drivers/mmc/host/Makefile
7356 --- linux-2.6.22.1/drivers/mmc/host/Makefile 2007-07-10 20:56:30.000000000 +0200
7357 +++ linux-avr32.git/drivers/mmc/host/Makefile 2007-07-12 14:00:03.000000000 +0200
7358 @@ -14,5 +14,6 @@
7359 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
7360 obj-$(CONFIG_MMC_OMAP) += omap.o
7361 obj-$(CONFIG_MMC_AT91) += at91_mci.o
7362 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
7363 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
7364
7365 diff -x .git -Nur linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0001.c linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0001.c
7366 --- linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0001.c 2007-07-10 20:56:30.000000000 +0200
7367 +++ linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0001.c 2007-07-12 14:00:03.000000000 +0200
7368 @@ -50,6 +50,7 @@
7369 #define I82802AC 0x00ac
7370 #define MANUFACTURER_ST 0x0020
7371 #define M50LPW080 0x002F
7372 +#define AT49BV640D 0x02de
7373
7374 static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
7375 static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
7376 @@ -156,6 +157,47 @@
7377 }
7378 #endif
7379
7380 +/* Atmel chips don't use the same PRI format as Intel chips */
7381 +static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
7382 +{
7383 + struct map_info *map = mtd->priv;
7384 + struct cfi_private *cfi = map->fldrv_priv;
7385 + struct cfi_pri_intelext *extp = cfi->cmdset_priv;
7386 + struct cfi_pri_atmel atmel_pri;
7387 + uint32_t features = 0;
7388 +
7389 + /* Reverse byteswapping */
7390 + extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
7391 + extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
7392 + extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
7393 +
7394 + memcpy(&atmel_pri, extp, sizeof(atmel_pri));
7395 + memset((char *)extp + 5, 0, sizeof(*extp) - 5);
7396 +
7397 + printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
7398 +
7399 + if (atmel_pri.Features & 0x01) /* chip erase supported */
7400 + features |= (1<<0);
7401 + if (atmel_pri.Features & 0x02) /* erase suspend supported */
7402 + features |= (1<<1);
7403 + if (atmel_pri.Features & 0x04) /* program suspend supported */
7404 + features |= (1<<2);
7405 + if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
7406 + features |= (1<<9);
7407 + if (atmel_pri.Features & 0x20) /* page mode read supported */
7408 + features |= (1<<7);
7409 + if (atmel_pri.Features & 0x40) /* queued erase supported */
7410 + features |= (1<<4);
7411 + if (atmel_pri.Features & 0x80) /* Protection bits supported */
7412 + features |= (1<<6);
7413 +
7414 + extp->FeatureSupport = features;
7415 +
7416 + /* burst write mode not supported */
7417 + cfi->cfiq->BufWriteTimeoutTyp = 0;
7418 + cfi->cfiq->BufWriteTimeoutMax = 0;
7419 +}
7420 +
7421 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
7422 /* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
7423 static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
7424 @@ -233,6 +275,7 @@
7425 }
7426
7427 static struct cfi_fixup cfi_fixup_table[] = {
7428 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
7429 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
7430 { CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
7431 #endif
7432 diff -x .git -Nur linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0002.c linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0002.c
7433 --- linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0002.c 2007-07-10 20:56:30.000000000 +0200
7434 +++ linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0002.c 2007-06-06 11:33:56.000000000 +0200
7435 @@ -186,6 +186,10 @@
7436 extp->TopBottom = 2;
7437 else
7438 extp->TopBottom = 3;
7439 +
7440 + /* burst write mode not supported */
7441 + cfi->cfiq->BufWriteTimeoutTyp = 0;
7442 + cfi->cfiq->BufWriteTimeoutMax = 0;
7443 }
7444
7445 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
7446 @@ -218,6 +222,7 @@
7447 }
7448
7449 static struct cfi_fixup cfi_fixup_table[] = {
7450 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
7451 #ifdef AMD_BOOTLOC_BUG
7452 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
7453 #endif
7454 @@ -230,7 +235,6 @@
7455 #if !FORCE_WORD_WRITE
7456 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
7457 #endif
7458 - { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
7459 { 0, 0, NULL, NULL }
7460 };
7461 static struct cfi_fixup jedec_fixup_table[] = {
7462 diff -x .git -Nur linux-2.6.22.1/drivers/net/Kconfig linux-avr32.git/drivers/net/Kconfig
7463 --- linux-2.6.22.1/drivers/net/Kconfig 2007-07-10 20:56:30.000000000 +0200
7464 +++ linux-avr32.git/drivers/net/Kconfig 2007-07-12 14:00:03.000000000 +0200
7465 @@ -314,7 +314,7 @@
7466 config MACB
7467 tristate "Atmel MACB support"
7468 depends on NET_ETHERNET && (AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263)
7469 - select MII
7470 + select PHYLIB
7471 help
7472 The Atmel MACB ethernet interface is found on many AT32 and AT91
7473 parts. Say Y to include support for the MACB chip.
7474 diff -x .git -Nur linux-2.6.22.1/drivers/net/macb.c linux-avr32.git/drivers/net/macb.c
7475 --- linux-2.6.22.1/drivers/net/macb.c 2007-07-10 20:56:30.000000000 +0200
7476 +++ linux-avr32.git/drivers/net/macb.c 2007-07-13 11:24:16.000000000 +0200
7477 @@ -17,13 +17,14 @@
7478 #include <linux/init.h>
7479 #include <linux/netdevice.h>
7480 #include <linux/etherdevice.h>
7481 -#include <linux/mii.h>
7482 -#include <linux/mutex.h>
7483 #include <linux/dma-mapping.h>
7484 -#include <linux/ethtool.h>
7485 #include <linux/platform_device.h>
7486 +#include <linux/phy.h>
7487
7488 #include <asm/arch/board.h>
7489 +#if defined(CONFIG_ARCH_AT91)
7490 +#include <asm/arch/cpu.h>
7491 +#endif
7492
7493 #include "macb.h"
7494
7495 @@ -85,172 +86,202 @@
7496 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
7497 }
7498
7499 -static void macb_enable_mdio(struct macb *bp)
7500 -{
7501 - unsigned long flags;
7502 - u32 reg;
7503 -
7504 - spin_lock_irqsave(&bp->lock, flags);
7505 - reg = macb_readl(bp, NCR);
7506 - reg |= MACB_BIT(MPE);
7507 - macb_writel(bp, NCR, reg);
7508 - macb_writel(bp, IER, MACB_BIT(MFD));
7509 - spin_unlock_irqrestore(&bp->lock, flags);
7510 -}
7511 -
7512 -static void macb_disable_mdio(struct macb *bp)
7513 +static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
7514 {
7515 - unsigned long flags;
7516 - u32 reg;
7517 -
7518 - spin_lock_irqsave(&bp->lock, flags);
7519 - reg = macb_readl(bp, NCR);
7520 - reg &= ~MACB_BIT(MPE);
7521 - macb_writel(bp, NCR, reg);
7522 - macb_writel(bp, IDR, MACB_BIT(MFD));
7523 - spin_unlock_irqrestore(&bp->lock, flags);
7524 -}
7525 -
7526 -static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
7527 -{
7528 - struct macb *bp = netdev_priv(dev);
7529 + struct macb *bp = bus->priv;
7530 int value;
7531
7532 - mutex_lock(&bp->mdio_mutex);
7533 -
7534 - macb_enable_mdio(bp);
7535 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
7536 | MACB_BF(RW, MACB_MAN_READ)
7537 - | MACB_BF(PHYA, phy_id)
7538 - | MACB_BF(REGA, location)
7539 + | MACB_BF(PHYA, mii_id)
7540 + | MACB_BF(REGA, regnum)
7541 | MACB_BF(CODE, MACB_MAN_CODE)));
7542
7543 - wait_for_completion(&bp->mdio_complete);
7544 + /* wait for end of transfer */
7545 + while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
7546 + cpu_relax();
7547
7548 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
7549 - macb_disable_mdio(bp);
7550 - mutex_unlock(&bp->mdio_mutex);
7551
7552 return value;
7553 }
7554
7555 -static void macb_mdio_write(struct net_device *dev, int phy_id,
7556 - int location, int val)
7557 +static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
7558 + u16 value)
7559 {
7560 - struct macb *bp = netdev_priv(dev);
7561 -
7562 - dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
7563 - phy_id, location, val);
7564 -
7565 - mutex_lock(&bp->mdio_mutex);
7566 - macb_enable_mdio(bp);
7567 + struct macb *bp = bus->priv;
7568
7569 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
7570 | MACB_BF(RW, MACB_MAN_WRITE)
7571 - | MACB_BF(PHYA, phy_id)
7572 - | MACB_BF(REGA, location)
7573 + | MACB_BF(PHYA, mii_id)
7574 + | MACB_BF(REGA, regnum)
7575 | MACB_BF(CODE, MACB_MAN_CODE)
7576 - | MACB_BF(DATA, val)));
7577 + | MACB_BF(DATA, value)));
7578
7579 - wait_for_completion(&bp->mdio_complete);
7580 + /* wait for end of transfer */
7581 + while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
7582 + cpu_relax();
7583
7584 - macb_disable_mdio(bp);
7585 - mutex_unlock(&bp->mdio_mutex);
7586 + return 0;
7587 }
7588
7589 -static int macb_phy_probe(struct macb *bp)
7590 +static int macb_mdio_reset(struct mii_bus *bus)
7591 {
7592 - int phy_address;
7593 - u16 phyid1, phyid2;
7594 + return 0;
7595 +}
7596
7597 - for (phy_address = 0; phy_address < 32; phy_address++) {
7598 - phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
7599 - phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
7600 +static void macb_handle_link_change(struct net_device *dev)
7601 +{
7602 + struct macb *bp = netdev_priv(dev);
7603 + struct phy_device *phydev = bp->phy_dev;
7604 + unsigned long flags;
7605
7606 - if (phyid1 != 0xffff && phyid1 != 0x0000
7607 - && phyid2 != 0xffff && phyid2 != 0x0000)
7608 - break;
7609 + int status_change = 0;
7610 +
7611 + spin_lock_irqsave(&bp->lock, flags);
7612 +
7613 + if (phydev->link) {
7614 + if ((bp->speed != phydev->speed) ||
7615 + (bp->duplex != phydev->duplex)) {
7616 + u32 reg;
7617 +
7618 + reg = macb_readl(bp, NCFGR);
7619 + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
7620 +
7621 + if (phydev->duplex)
7622 + reg |= MACB_BIT(FD);
7623 + if (phydev->speed)
7624 + reg |= MACB_BIT(SPD);
7625 +
7626 + macb_writel(bp, NCFGR, reg);
7627 +
7628 + bp->speed = phydev->speed;
7629 + bp->duplex = phydev->duplex;
7630 + status_change = 1;
7631 + }
7632 }
7633
7634 - if (phy_address == 32)
7635 - return -ENODEV;
7636 + if (phydev->link != bp->link) {
7637 + if (phydev->link)
7638 + netif_schedule(dev);
7639 + else {
7640 + bp->speed = 0;
7641 + bp->duplex = -1;
7642 + }
7643 + bp->link = phydev->link;
7644
7645 - dev_info(&bp->pdev->dev,
7646 - "detected PHY at address %d (ID %04x:%04x)\n",
7647 - phy_address, phyid1, phyid2);
7648 + status_change = 1;
7649 + }
7650
7651 - bp->mii.phy_id = phy_address;
7652 - return 0;
7653 + spin_unlock_irqrestore(&bp->lock, flags);
7654 +
7655 + if (status_change) {
7656 + if (phydev->link)
7657 + printk(KERN_INFO "%s: link up (%d/%s)\n",
7658 + dev->name, phydev->speed,
7659 + DUPLEX_FULL == phydev->duplex ? "Full":"Half");
7660 + else
7661 + printk(KERN_INFO "%s: link down\n", dev->name);
7662 + }
7663 }
7664
7665 -static void macb_set_media(struct macb *bp, int media)
7666 +/* based on au1000_eth. c*/
7667 +static int macb_mii_probe(struct net_device *dev)
7668 {
7669 - u32 reg;
7670 + struct macb *bp = netdev_priv(dev);
7671 + struct phy_device *phydev = NULL;
7672 + struct eth_platform_data *pdata;
7673 + int phy_addr;
7674
7675 - spin_lock_irq(&bp->lock);
7676 - reg = macb_readl(bp, NCFGR);
7677 - reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
7678 - if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
7679 - reg |= MACB_BIT(SPD);
7680 - if (media & ADVERTISE_FULL)
7681 - reg |= MACB_BIT(FD);
7682 - macb_writel(bp, NCFGR, reg);
7683 - spin_unlock_irq(&bp->lock);
7684 + /* find the first phy */
7685 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
7686 + if (bp->mii_bus.phy_map[phy_addr]) {
7687 + phydev = bp->mii_bus.phy_map[phy_addr];
7688 + break;
7689 + }
7690 + }
7691 +
7692 + if (!phydev) {
7693 + printk (KERN_ERR "%s: no PHY found\n", dev->name);
7694 + return -1;
7695 + }
7696 +
7697 + pdata = bp->pdev->dev.platform_data;
7698 + /* TODO : add pin_irq */
7699 +
7700 + /* attach the mac to the phy */
7701 + if (pdata && pdata->is_rmii) {
7702 + phydev = phy_connect(dev, phydev->dev.bus_id,
7703 + &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
7704 + } else {
7705 + phydev = phy_connect(dev, phydev->dev.bus_id,
7706 + &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
7707 + }
7708 +
7709 + if (IS_ERR(phydev)) {
7710 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
7711 + return PTR_ERR(phydev);
7712 + }
7713 +
7714 + /* mask with MAC supported features */
7715 + phydev->supported &= PHY_BASIC_FEATURES;
7716 +
7717 + phydev->advertising = phydev->supported;
7718 +
7719 + bp->link = 0;
7720 + bp->speed = 0;
7721 + bp->duplex = -1;
7722 + bp->phy_dev = phydev;
7723 +
7724 + return 0;
7725 }
7726
7727 -static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
7728 +static int macb_mii_init(struct macb *bp)
7729 {
7730 - struct mii_if_info *mii = &bp->mii;
7731 - unsigned int old_carrier, new_carrier;
7732 - int advertise, lpa, media, duplex;
7733 + struct eth_platform_data *pdata;
7734 + int err = -ENXIO, i;
7735
7736 - /* if forced media, go no further */
7737 - if (mii->force_media)
7738 - return;
7739 + /* Enable managment port */
7740 + macb_writel(bp, NCR, MACB_BIT(MPE));
7741
7742 - /* check current and old link status */
7743 - old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
7744 - new_carrier = (unsigned int) mii_link_ok(mii);
7745 + bp->mii_bus.name = "MACB_mii_bus",
7746 + bp->mii_bus.read = &macb_mdio_read,
7747 + bp->mii_bus.write = &macb_mdio_write,
7748 + bp->mii_bus.reset = &macb_mdio_reset,
7749 + bp->mii_bus.id = bp->pdev->id,
7750 + bp->mii_bus.priv = bp,
7751 + bp->mii_bus.dev = &bp->dev->dev;
7752 + pdata = bp->pdev->dev.platform_data;
7753
7754 - /* if carrier state did not change, assume nothing else did */
7755 - if (!init_media && old_carrier == new_carrier)
7756 - return;
7757 + if (pdata)
7758 + bp->mii_bus.phy_mask = pdata->phy_mask;
7759
7760 - /* no carrier, nothing much to do */
7761 - if (!new_carrier) {
7762 - netif_carrier_off(mii->dev);
7763 - printk(KERN_INFO "%s: link down\n", mii->dev->name);
7764 - return;
7765 + bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
7766 + if (!bp->mii_bus.irq) {
7767 + err = -ENOMEM;
7768 + goto err_out;
7769 }
7770
7771 - /*
7772 - * we have carrier, see who's on the other end
7773 - */
7774 - netif_carrier_on(mii->dev);
7775 + for (i = 0; i < PHY_MAX_ADDR; i++)
7776 + bp->mii_bus.irq[i] = PHY_POLL;
7777
7778 - /* get MII advertise and LPA values */
7779 - if (!init_media && mii->advertising) {
7780 - advertise = mii->advertising;
7781 - } else {
7782 - advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
7783 - mii->advertising = advertise;
7784 - }
7785 - lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
7786 + platform_set_drvdata(bp->dev, &bp->mii_bus);
7787
7788 - /* figure out media and duplex from advertise and LPA values */
7789 - media = mii_nway_result(lpa & advertise);
7790 - duplex = (media & ADVERTISE_FULL) ? 1 : 0;
7791 + if (mdiobus_register(&bp->mii_bus))
7792 + goto err_out_free_mdio_irq;
7793
7794 - if (ok_to_print)
7795 - printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
7796 - mii->dev->name,
7797 - media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
7798 - duplex ? "full" : "half", lpa);
7799 + if (macb_mii_probe(bp->dev) != 0) {
7800 + goto err_out_unregister_bus;
7801 + }
7802
7803 - mii->full_duplex = duplex;
7804 + return 0;
7805
7806 - /* Let the MAC know about the new link state */
7807 - macb_set_media(bp, media);
7808 +err_out_unregister_bus:
7809 + mdiobus_unregister(&bp->mii_bus);
7810 +err_out_free_mdio_irq:
7811 + kfree(bp->mii_bus.irq);
7812 +err_out:
7813 + return err;
7814 }
7815
7816 static void macb_update_stats(struct macb *bp)
7817 @@ -265,16 +296,6 @@
7818 *p += __raw_readl(reg);
7819 }
7820
7821 -static void macb_periodic_task(struct work_struct *work)
7822 -{
7823 - struct macb *bp = container_of(work, struct macb, periodic_task.work);
7824 -
7825 - macb_update_stats(bp);
7826 - macb_check_media(bp, 1, 0);
7827 -
7828 - schedule_delayed_work(&bp->periodic_task, HZ);
7829 -}
7830 -
7831 static void macb_tx(struct macb *bp)
7832 {
7833 unsigned int tail;
7834 @@ -519,9 +540,6 @@
7835 spin_lock(&bp->lock);
7836
7837 while (status) {
7838 - if (status & MACB_BIT(MFD))
7839 - complete(&bp->mdio_complete);
7840 -
7841 /* close possible race with dev_close */
7842 if (unlikely(!netif_running(dev))) {
7843 macb_writel(bp, IDR, ~0UL);
7844 @@ -535,7 +553,8 @@
7845 * until we have processed the buffers
7846 */
7847 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
7848 - dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
7849 + dev_dbg(&bp->pdev->dev,
7850 + "scheduling RX softirq\n");
7851 __netif_rx_schedule(dev);
7852 }
7853 }
7854 @@ -765,7 +784,7 @@
7855 macb_writel(bp, TBQP, bp->tx_ring_dma);
7856
7857 /* Enable TX and RX */
7858 - macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
7859 + macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
7860
7861 /* Enable interrupts */
7862 macb_writel(bp, IER, (MACB_BIT(RCOMP)
7863 @@ -776,18 +795,126 @@
7864 | MACB_BIT(TCOMP)
7865 | MACB_BIT(ISR_ROVR)
7866 | MACB_BIT(HRESP)));
7867 +
7868 +}
7869 +
7870 +/*
7871 + * The hash address register is 64 bits long and takes up two
7872 + * locations in the memory map. The least significant bits are stored
7873 + * in EMAC_HSL and the most significant bits in EMAC_HSH.
7874 + *
7875 + * The unicast hash enable and the multicast hash enable bits in the
7876 + * network configuration register enable the reception of hash matched
7877 + * frames. The destination address is reduced to a 6 bit index into
7878 + * the 64 bit hash register using the following hash function. The
7879 + * hash function is an exclusive or of every sixth bit of the
7880 + * destination address.
7881 + *
7882 + * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
7883 + * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
7884 + * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
7885 + * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
7886 + * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
7887 + * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
7888 + *
7889 + * da[0] represents the least significant bit of the first byte
7890 + * received, that is, the multicast/unicast indicator, and da[47]
7891 + * represents the most significant bit of the last byte received. If
7892 + * the hash index, hi[n], points to a bit that is set in the hash
7893 + * register then the frame will be matched according to whether the
7894 + * frame is multicast or unicast. A multicast match will be signalled
7895 + * if the multicast hash enable bit is set, da[0] is 1 and the hash
7896 + * index points to a bit set in the hash register. A unicast match
7897 + * will be signalled if the unicast hash enable bit is set, da[0] is 0
7898 + * and the hash index points to a bit set in the hash register. To
7899 + * receive all multicast frames, the hash register should be set with
7900 + * all ones and the multicast hash enable bit should be set in the
7901 + * network configuration register.
7902 + */
7903 +
7904 +static inline int hash_bit_value(int bitnr, __u8 *addr)
7905 +{
7906 + if (addr[bitnr / 8] & (1 << (bitnr % 8)))
7907 + return 1;
7908 + return 0;
7909 +}
7910 +
7911 +/*
7912 + * Return the hash index value for the specified address.
7913 + */
7914 +static int hash_get_index(__u8 *addr)
7915 +{
7916 + int i, j, bitval;
7917 + int hash_index = 0;
7918 +
7919 + for (j = 0; j < 6; j++) {
7920 + for (i = 0, bitval = 0; i < 8; i++)
7921 + bitval ^= hash_bit_value(i*6 + j, addr);
7922 +
7923 + hash_index |= (bitval << j);
7924 + }
7925 +
7926 + return hash_index;
7927 }
7928
7929 -static void macb_init_phy(struct net_device *dev)
7930 +/*
7931 + * Add multicast addresses to the internal multicast-hash table.
7932 + */
7933 +static void macb_sethashtable(struct net_device *dev)
7934 {
7935 + struct dev_mc_list *curr;
7936 + unsigned long mc_filter[2];
7937 + unsigned int i, bitnr;
7938 struct macb *bp = netdev_priv(dev);
7939
7940 - /* Set some reasonable default settings */
7941 - macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
7942 - ADVERTISE_CSMA | ADVERTISE_ALL);
7943 - macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
7944 - (BMCR_SPEED100 | BMCR_ANENABLE
7945 - | BMCR_ANRESTART | BMCR_FULLDPLX));
7946 + mc_filter[0] = mc_filter[1] = 0;
7947 +
7948 + curr = dev->mc_list;
7949 + for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
7950 + if (!curr) break; /* unexpected end of list */
7951 +
7952 + bitnr = hash_get_index(curr->dmi_addr);
7953 + mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
7954 + }
7955 +
7956 + macb_writel(bp, HRB, mc_filter[0]);
7957 + macb_writel(bp, HRT, mc_filter[1]);
7958 +}
7959 +
7960 +/*
7961 + * Enable/Disable promiscuous and multicast modes.
7962 + */
7963 +static void macb_set_rx_mode(struct net_device *dev)
7964 +{
7965 + unsigned long cfg;
7966 + struct macb *bp = netdev_priv(dev);
7967 +
7968 + cfg = macb_readl(bp, NCFGR);
7969 +
7970 + if (dev->flags & IFF_PROMISC)
7971 + /* Enable promiscuous mode */
7972 + cfg |= MACB_BIT(CAF);
7973 + else if (dev->flags & (~IFF_PROMISC))
7974 + /* Disable promiscuous mode */
7975 + cfg &= ~MACB_BIT(CAF);
7976 +
7977 + if (dev->flags & IFF_ALLMULTI) {
7978 + /* Enable all multicast mode */
7979 + macb_writel(bp, HRB, -1);
7980 + macb_writel(bp, HRT, -1);
7981 + cfg |= MACB_BIT(NCFGR_MTI);
7982 + } else if (dev->mc_count > 0) {
7983 + /* Enable specific multicasts */
7984 + macb_sethashtable(dev);
7985 + cfg |= MACB_BIT(NCFGR_MTI);
7986 + } else if (dev->flags & (~IFF_ALLMULTI)) {
7987 + /* Disable all multicast mode */
7988 + macb_writel(bp, HRB, 0);
7989 + macb_writel(bp, HRT, 0);
7990 + cfg &= ~MACB_BIT(NCFGR_MTI);
7991 + }
7992 +
7993 + macb_writel(bp, NCFGR, cfg);
7994 }
7995
7996 static int macb_open(struct net_device *dev)
7997 @@ -797,6 +924,10 @@
7998
7999 dev_dbg(&bp->pdev->dev, "open\n");
8000
8001 + /* if the phy is not yet register, retry later*/
8002 + if (!bp->phy_dev)
8003 + return -EAGAIN;
8004 +
8005 if (!is_valid_ether_addr(dev->dev_addr))
8006 return -EADDRNOTAVAIL;
8007
8008 @@ -810,12 +941,11 @@
8009
8010 macb_init_rings(bp);
8011 macb_init_hw(bp);
8012 - macb_init_phy(dev);
8013
8014 - macb_check_media(bp, 1, 1);
8015 - netif_start_queue(dev);
8016 + /* schedule a link state check */
8017 + phy_start(bp->phy_dev);
8018
8019 - schedule_delayed_work(&bp->periodic_task, HZ);
8020 + netif_start_queue(dev);
8021
8022 return 0;
8023 }
8024 @@ -825,10 +955,11 @@
8025 struct macb *bp = netdev_priv(dev);
8026 unsigned long flags;
8027
8028 - cancel_rearming_delayed_work(&bp->periodic_task);
8029 -
8030 netif_stop_queue(dev);
8031
8032 + if (bp->phy_dev)
8033 + phy_stop(bp->phy_dev);
8034 +
8035 spin_lock_irqsave(&bp->lock, flags);
8036 macb_reset_hw(bp);
8037 netif_carrier_off(dev);
8038 @@ -845,6 +976,9 @@
8039 struct net_device_stats *nstat = &bp->stats;
8040 struct macb_stats *hwstat = &bp->hw_stats;
8041
8042 + /* read stats from hardware */
8043 + macb_update_stats(bp);
8044 +
8045 /* Convert HW stats into netdevice stats */
8046 nstat->rx_errors = (hwstat->rx_fcs_errors +
8047 hwstat->rx_align_errors +
8048 @@ -882,18 +1016,27 @@
8049 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8050 {
8051 struct macb *bp = netdev_priv(dev);
8052 + struct phy_device *phydev = bp->phy_dev;
8053 +
8054 + if (!phydev)
8055 + return -ENODEV;
8056
8057 - return mii_ethtool_gset(&bp->mii, cmd);
8058 + return phy_ethtool_gset(phydev, cmd);
8059 }
8060
8061 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8062 {
8063 struct macb *bp = netdev_priv(dev);
8064 + struct phy_device *phydev = bp->phy_dev;
8065 +
8066 + if (!phydev)
8067 + return -ENODEV;
8068
8069 - return mii_ethtool_sset(&bp->mii, cmd);
8070 + return phy_ethtool_sset(phydev, cmd);
8071 }
8072
8073 -static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8074 +static void macb_get_drvinfo(struct net_device *dev,
8075 + struct ethtool_drvinfo *info)
8076 {
8077 struct macb *bp = netdev_priv(dev);
8078
8079 @@ -902,104 +1045,34 @@
8080 strcpy(info->bus_info, bp->pdev->dev.bus_id);
8081 }
8082
8083 -static int macb_nway_reset(struct net_device *dev)
8084 -{
8085 - struct macb *bp = netdev_priv(dev);
8086 - return mii_nway_restart(&bp->mii);
8087 -}
8088 -
8089 static struct ethtool_ops macb_ethtool_ops = {
8090 .get_settings = macb_get_settings,
8091 .set_settings = macb_set_settings,
8092 .get_drvinfo = macb_get_drvinfo,
8093 - .nway_reset = macb_nway_reset,
8094 .get_link = ethtool_op_get_link,
8095 };
8096
8097 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
8098 {
8099 struct macb *bp = netdev_priv(dev);
8100 + struct phy_device *phydev = bp->phy_dev;
8101
8102 if (!netif_running(dev))
8103 return -EINVAL;
8104
8105 - return generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
8106 -}
8107 -
8108 -static ssize_t macb_mii_show(const struct device *_dev, char *buf,
8109 - unsigned long addr)
8110 -{
8111 - struct net_device *dev = to_net_dev(_dev);
8112 - struct macb *bp = netdev_priv(dev);
8113 - ssize_t ret = -EINVAL;
8114 -
8115 - if (netif_running(dev)) {
8116 - int value;
8117 - value = macb_mdio_read(dev, bp->mii.phy_id, addr);
8118 - ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
8119 - }
8120 -
8121 - return ret;
8122 -}
8123 -
8124 -#define MII_ENTRY(name, addr) \
8125 -static ssize_t show_##name(struct device *_dev, \
8126 - struct device_attribute *attr, \
8127 - char *buf) \
8128 -{ \
8129 - return macb_mii_show(_dev, buf, addr); \
8130 -} \
8131 -static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
8132 -
8133 -MII_ENTRY(bmcr, MII_BMCR);
8134 -MII_ENTRY(bmsr, MII_BMSR);
8135 -MII_ENTRY(physid1, MII_PHYSID1);
8136 -MII_ENTRY(physid2, MII_PHYSID2);
8137 -MII_ENTRY(advertise, MII_ADVERTISE);
8138 -MII_ENTRY(lpa, MII_LPA);
8139 -MII_ENTRY(expansion, MII_EXPANSION);
8140 -
8141 -static struct attribute *macb_mii_attrs[] = {
8142 - &dev_attr_bmcr.attr,
8143 - &dev_attr_bmsr.attr,
8144 - &dev_attr_physid1.attr,
8145 - &dev_attr_physid2.attr,
8146 - &dev_attr_advertise.attr,
8147 - &dev_attr_lpa.attr,
8148 - &dev_attr_expansion.attr,
8149 - NULL,
8150 -};
8151 -
8152 -static struct attribute_group macb_mii_group = {
8153 - .name = "mii",
8154 - .attrs = macb_mii_attrs,
8155 -};
8156 -
8157 -static void macb_unregister_sysfs(struct net_device *net)
8158 -{
8159 - struct device *_dev = &net->dev;
8160 + if (!phydev)
8161 + return -ENODEV;
8162
8163 - sysfs_remove_group(&_dev->kobj, &macb_mii_group);
8164 + return phy_mii_ioctl(phydev, if_mii(rq), cmd);
8165 }
8166
8167 -static int macb_register_sysfs(struct net_device *net)
8168 -{
8169 - struct device *_dev = &net->dev;
8170 - int ret;
8171 -
8172 - ret = sysfs_create_group(&_dev->kobj, &macb_mii_group);
8173 - if (ret)
8174 - printk(KERN_WARNING
8175 - "%s: sysfs mii attribute registration failed: %d\n",
8176 - net->name, ret);
8177 - return ret;
8178 -}
8179 static int __devinit macb_probe(struct platform_device *pdev)
8180 {
8181 struct eth_platform_data *pdata;
8182 struct resource *regs;
8183 struct net_device *dev;
8184 struct macb *bp;
8185 + struct phy_device *phydev;
8186 unsigned long pclk_hz;
8187 u32 config;
8188 int err = -ENXIO;
8189 @@ -1073,6 +1146,7 @@
8190 dev->stop = macb_close;
8191 dev->hard_start_xmit = macb_start_xmit;
8192 dev->get_stats = macb_get_stats;
8193 + dev->set_multicast_list = macb_set_rx_mode;
8194 dev->do_ioctl = macb_ioctl;
8195 dev->poll = macb_poll;
8196 dev->weight = 64;
8197 @@ -1080,10 +1154,6 @@
8198
8199 dev->base_addr = regs->start;
8200
8201 - INIT_DELAYED_WORK(&bp->periodic_task, macb_periodic_task);
8202 - mutex_init(&bp->mdio_mutex);
8203 - init_completion(&bp->mdio_complete);
8204 -
8205 /* Set MII management clock divider */
8206 pclk_hz = clk_get_rate(bp->pclk);
8207 if (pclk_hz <= 20000000)
8208 @@ -1096,20 +1166,9 @@
8209 config = MACB_BF(CLK, MACB_CLK_DIV64);
8210 macb_writel(bp, NCFGR, config);
8211
8212 - bp->mii.dev = dev;
8213 - bp->mii.mdio_read = macb_mdio_read;
8214 - bp->mii.mdio_write = macb_mdio_write;
8215 - bp->mii.phy_id_mask = 0x1f;
8216 - bp->mii.reg_num_mask = 0x1f;
8217 -
8218 macb_get_hwaddr(bp);
8219 - err = macb_phy_probe(bp);
8220 - if (err) {
8221 - dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
8222 - goto err_out_free_irq;
8223 - }
8224 -
8225 pdata = pdev->dev.platform_data;
8226 +
8227 if (pdata && pdata->is_rmii)
8228 #if defined(CONFIG_ARCH_AT91)
8229 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
8230 @@ -1131,9 +1190,11 @@
8231 goto err_out_free_irq;
8232 }
8233
8234 - platform_set_drvdata(pdev, dev);
8235 + if (macb_mii_init(bp) != 0) {
8236 + goto err_out_unregister_netdev;
8237 + }
8238
8239 - macb_register_sysfs(dev);
8240 + platform_set_drvdata(pdev, dev);
8241
8242 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
8243 "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
8244 @@ -1141,8 +1202,15 @@
8245 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
8246 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
8247
8248 + phydev = bp->phy_dev;
8249 + printk(KERN_INFO "%s: attached PHY driver [%s] "
8250 + "(mii_bus:phy_addr=%s, irq=%d)\n",
8251 + dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
8252 +
8253 return 0;
8254
8255 +err_out_unregister_netdev:
8256 + unregister_netdev(dev);
8257 err_out_free_irq:
8258 free_irq(dev->irq, dev);
8259 err_out_iounmap:
8260 @@ -1153,7 +1221,9 @@
8261 clk_put(bp->hclk);
8262 #endif
8263 clk_disable(bp->pclk);
8264 +#ifndef CONFIG_ARCH_AT91
8265 err_out_put_pclk:
8266 +#endif
8267 clk_put(bp->pclk);
8268 err_out_free_dev:
8269 free_netdev(dev);
8270 @@ -1171,7 +1241,8 @@
8271
8272 if (dev) {
8273 bp = netdev_priv(dev);
8274 - macb_unregister_sysfs(dev);
8275 + mdiobus_unregister(&bp->mii_bus);
8276 + kfree(bp->mii_bus.irq);
8277 unregister_netdev(dev);
8278 free_irq(dev->irq, dev);
8279 iounmap(bp->regs);
8280 diff -x .git -Nur linux-2.6.22.1/drivers/net/macb.h linux-avr32.git/drivers/net/macb.h
8281 --- linux-2.6.22.1/drivers/net/macb.h 2007-07-10 20:56:30.000000000 +0200
8282 +++ linux-avr32.git/drivers/net/macb.h 2007-07-12 14:00:04.000000000 +0200
8283 @@ -383,11 +383,11 @@
8284
8285 unsigned int rx_pending, tx_pending;
8286
8287 - struct delayed_work periodic_task;
8288 -
8289 - struct mutex mdio_mutex;
8290 - struct completion mdio_complete;
8291 - struct mii_if_info mii;
8292 + struct mii_bus mii_bus;
8293 + struct phy_device *phy_dev;
8294 + unsigned int link;
8295 + unsigned int speed;
8296 + unsigned int duplex;
8297 };
8298
8299 #endif /* _MACB_H */
8300 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/Kconfig linux-avr32.git/drivers/rtc/Kconfig
8301 --- linux-2.6.22.1/drivers/rtc/Kconfig 2007-07-10 20:56:30.000000000 +0200
8302 +++ linux-avr32.git/drivers/rtc/Kconfig 2007-07-12 14:00:13.000000000 +0200
8303 @@ -379,6 +379,13 @@
8304 To compile this driver as a module, choose M here: the
8305 module will be called rtc-pl031.
8306
8307 +config RTC_DRV_AT32AP700X
8308 + tristate "AT32AP700X series RTC"
8309 + depends on RTC_CLASS && PLATFORM_AT32AP
8310 + help
8311 + Driver for the internal RTC (Realtime Clock) on Atmel AVR32
8312 + AT32AP700x family processors.
8313 +
8314 config RTC_DRV_AT91RM9200
8315 tristate "AT91RM9200"
8316 depends on RTC_CLASS && ARCH_AT91RM9200
8317 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/Makefile linux-avr32.git/drivers/rtc/Makefile
8318 --- linux-2.6.22.1/drivers/rtc/Makefile 2007-07-10 20:56:30.000000000 +0200
8319 +++ linux-avr32.git/drivers/rtc/Makefile 2007-07-12 14:00:13.000000000 +0200
8320 @@ -19,6 +19,7 @@
8321 obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
8322 obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
8323 obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
8324 +obj-$(CONFIG_RTC_DRV_AT32AP700X) += rtc-at32ap700x.o
8325 obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o
8326 obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
8327 obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
8328 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/rtc-at32ap700x.c linux-avr32.git/drivers/rtc/rtc-at32ap700x.c
8329 --- linux-2.6.22.1/drivers/rtc/rtc-at32ap700x.c 1970-01-01 01:00:00.000000000 +0100
8330 +++ linux-avr32.git/drivers/rtc/rtc-at32ap700x.c 2007-07-12 14:00:13.000000000 +0200
8331 @@ -0,0 +1,337 @@
8332 +/*
8333 + * An RTC driver for the AVR32 AT32AP700x processor series.
8334 + *
8335 + * Copyright (C) 2007 Atmel Corporation
8336 + *
8337 + * This program is free software; you can redistribute it and/or modify it
8338 + * under the terms of the GNU General Public License version 2 as published
8339 + * by the Free Software Foundation.
8340 + */
8341 +
8342 +#include <linux/module.h>
8343 +#include <linux/kernel.h>
8344 +#include <linux/platform_device.h>
8345 +#include <linux/rtc.h>
8346 +#include <linux/io.h>
8347 +
8348 +/*
8349 + * This is a bare-bones RTC. It runs during most system sleep states, but has
8350 + * no battery backup and gets reset during system restart. It must be
8351 + * initialized from an external clock (network, I2C, etc) before it can be of
8352 + * much use.
8353 + *
8354 + * The alarm functionality is limited by the hardware, not supporting
8355 + * periodic interrupts.
8356 + */
8357 +
8358 +#define RTC_CTRL 0x00
8359 +#define RTC_CTRL_EN 0
8360 +#define RTC_CTRL_PCLR 1
8361 +#define RTC_CTRL_TOPEN 2
8362 +#define RTC_CTRL_PSEL 8
8363 +
8364 +#define RTC_VAL 0x04
8365 +
8366 +#define RTC_TOP 0x08
8367 +
8368 +#define RTC_IER 0x10
8369 +#define RTC_IER_TOPI 0
8370 +
8371 +#define RTC_IDR 0x14
8372 +#define RTC_IDR_TOPI 0
8373 +
8374 +#define RTC_IMR 0x18
8375 +#define RTC_IMR_TOPI 0
8376 +
8377 +#define RTC_ISR 0x1c
8378 +#define RTC_ISR_TOPI 0
8379 +
8380 +#define RTC_ICR 0x20
8381 +#define RTC_ICR_TOPI 0
8382 +
8383 +#define RTC_BIT(name) (1 << RTC_##name)
8384 +#define RTC_BF(name, value) ((value) << RTC_##name)
8385 +
8386 +#define rtc_readl(dev, reg) \
8387 + __raw_readl((dev)->regs + RTC_##reg)
8388 +#define rtc_writel(dev, reg, value) \
8389 + __raw_writel((value), (dev)->regs + RTC_##reg)
8390 +
8391 +struct rtc_at32ap700x {
8392 + struct rtc_device *rtc;
8393 + void __iomem *regs;
8394 + unsigned long alarm_time;
8395 + unsigned long irq;
8396 + /* Protect against concurrent register access. */
8397 + spinlock_t lock;
8398 +};
8399 +
8400 +static int at32_rtc_readtime(struct device *dev, struct rtc_time *tm)
8401 +{
8402 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
8403 + unsigned long now;
8404 +
8405 + now = rtc_readl(rtc, VAL);
8406 + rtc_time_to_tm(now, tm);
8407 +
8408 + return 0;
8409 +}
8410 +
8411 +static int at32_rtc_settime(struct device *dev, struct rtc_time *tm)
8412 +{
8413 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
8414 + unsigned long now;
8415 + int ret;
8416 +
8417 + ret = rtc_tm_to_time(tm, &now);
8418 + if (ret == 0)
8419 + rtc_writel(rtc, VAL, now);
8420 +
8421 + return ret;
8422 +}
8423 +
8424 +static int at32_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
8425 +{
8426 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
8427 +
8428 + rtc_time_to_tm(rtc->alarm_time, &alrm->time);
8429 + alrm->pending = rtc_readl(rtc, IMR) & RTC_BIT(IMR_TOPI) ? 1 : 0;
8430 +
8431 + return 0;
8432 +}
8433 +
8434 +static int at32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
8435 +{
8436 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
8437 + unsigned long rtc_unix_time;
8438 + unsigned long alarm_unix_time;
8439 + int ret;
8440 +
8441 + rtc_unix_time = rtc_readl(rtc, VAL);
8442 +
8443 + /* RTC does only support one alarm time, not periodic */
8444 + if (alrm->time.tm_mday <= 0) {
8445 + struct rtc_time tm;
8446 + unsigned long then;
8447 +
8448 + rtc_time_to_tm(rtc_unix_time, &tm);
8449 +
8450 + alrm->time.tm_mday = tm.tm_mday;
8451 + alrm->time.tm_mon = tm.tm_mon;
8452 + alrm->time.tm_year = tm.tm_year;
8453 +
8454 + rtc_tm_to_time(&alrm->time, &then);
8455 +
8456 + /* check if the alarm wraps into tomorrow */
8457 + if (then < rtc_unix_time) {
8458 + rtc_time_to_tm(rtc_unix_time + 24 * 60 * 60, &tm);
8459 + alrm->time.tm_mday = tm.tm_mday;
8460 + alrm->time.tm_mon = tm.tm_mon;
8461 + alrm->time.tm_year = tm.tm_year;
8462 + }
8463 + }
8464 +
8465 + ret = rtc_tm_to_time(&alrm->time, &alarm_unix_time);
8466 + if (ret)
8467 + return ret;
8468 +
8469 + if (alarm_unix_time < rtc_unix_time)
8470 + return -EINVAL;
8471 +
8472 + spin_lock_irq(&rtc->lock);
8473 + rtc->alarm_time = alarm_unix_time;
8474 + rtc_writel(rtc, TOP, rtc->alarm_time);
8475 + if (alrm->pending)
8476 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
8477 + | RTC_BIT(CTRL_TOPEN));
8478 + else
8479 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
8480 + & ~RTC_BIT(CTRL_TOPEN));
8481 + spin_unlock_irq(&rtc->lock);
8482 +
8483 + return ret;
8484 +}
8485 +
8486 +static int at32_rtc_ioctl(struct device *dev, unsigned int cmd,
8487 + unsigned long arg)
8488 +{
8489 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
8490 + int ret = 0;
8491 +
8492 + spin_lock_irq(&rtc->lock);
8493 +
8494 + switch (cmd) {
8495 + case RTC_AIE_ON:
8496 + if (rtc_readl(rtc, VAL) > rtc->alarm_time) {
8497 + ret = -EINVAL;
8498 + break;
8499 + }
8500 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
8501 + | RTC_BIT(CTRL_TOPEN));
8502 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
8503 + rtc_writel(rtc, IER, RTC_BIT(IER_TOPI));
8504 + break;
8505 + case RTC_AIE_OFF:
8506 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
8507 + & ~RTC_BIT(CTRL_TOPEN));
8508 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
8509 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
8510 + break;
8511 + default:
8512 + ret = -ENOIOCTLCMD;
8513 + break;
8514 + }
8515 +
8516 + spin_unlock_irq(&rtc->lock);
8517 +
8518 + return ret;
8519 +}
8520 +
8521 +static irqreturn_t at32_rtc_interrupt(int irq, void *dev_id)
8522 +{
8523 + struct rtc_at32ap700x *rtc = (struct rtc_at32ap700x *)dev_id;
8524 + unsigned long isr = rtc_readl(rtc, ISR);
8525 + unsigned long events = 0;
8526 + int ret = IRQ_NONE;
8527 +
8528 + spin_lock(&rtc->lock);
8529 +
8530 + if (isr & RTC_BIT(ISR_TOPI)) {
8531 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
8532 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
8533 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
8534 + & ~RTC_BIT(CTRL_TOPEN));
8535 + rtc_writel(rtc, VAL, rtc->alarm_time);
8536 + events = RTC_AF | RTC_IRQF;
8537 + rtc_update_irq(rtc->rtc, 1, events);
8538 + ret = IRQ_HANDLED;
8539 + }
8540 +
8541 + spin_unlock(&rtc->lock);
8542 +
8543 + return ret;
8544 +}
8545 +
8546 +static struct rtc_class_ops at32_rtc_ops = {
8547 + .ioctl = at32_rtc_ioctl,
8548 + .read_time = at32_rtc_readtime,
8549 + .set_time = at32_rtc_settime,
8550 + .read_alarm = at32_rtc_readalarm,
8551 + .set_alarm = at32_rtc_setalarm,
8552 +};
8553 +
8554 +static int __init at32_rtc_probe(struct platform_device *pdev)
8555 +{
8556 + struct resource *regs;
8557 + struct rtc_at32ap700x *rtc;
8558 + int irq = -1;
8559 + int ret;
8560 +
8561 + rtc = kzalloc(sizeof(struct rtc_at32ap700x), GFP_KERNEL);
8562 + if (!rtc) {
8563 + dev_dbg(&pdev->dev, "out of memory\n");
8564 + return -ENOMEM;
8565 + }
8566 +
8567 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8568 + if (!regs) {
8569 + dev_dbg(&pdev->dev, "no mmio resource defined\n");
8570 + ret = -ENXIO;
8571 + goto out;
8572 + }
8573 +
8574 + irq = platform_get_irq(pdev, 0);
8575 + if (irq < 0) {
8576 + dev_dbg(&pdev->dev, "could not get irq\n");
8577 + ret = -ENXIO;
8578 + goto out;
8579 + }
8580 +
8581 + ret = request_irq(irq, at32_rtc_interrupt, IRQF_SHARED, "rtc", rtc);
8582 + if (ret) {
8583 + dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
8584 + goto out;
8585 + }
8586 +
8587 + rtc->irq = irq;
8588 + rtc->regs = ioremap(regs->start, regs->end - regs->start + 1);
8589 + if (!rtc->regs) {
8590 + ret = -ENOMEM;
8591 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
8592 + goto out_free_irq;
8593 + }
8594 + spin_lock_init(&rtc->lock);
8595 +
8596 + /*
8597 + * Maybe init RTC: count from zero at 1 Hz, disable wrap irq.
8598 + *
8599 + * Do not reset VAL register, as it can hold an old time
8600 + * from last JTAG reset.
8601 + */
8602 + if (!(rtc_readl(rtc, CTRL) & RTC_BIT(CTRL_EN))) {
8603 + rtc_writel(rtc, CTRL, RTC_BIT(CTRL_PCLR));
8604 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
8605 + rtc_writel(rtc, CTRL, RTC_BF(CTRL_PSEL, 0xe)
8606 + | RTC_BIT(CTRL_EN));
8607 + }
8608 +
8609 + rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
8610 + &at32_rtc_ops, THIS_MODULE);
8611 + if (IS_ERR(rtc->rtc)) {
8612 + dev_dbg(&pdev->dev, "could not register rtc device\n");
8613 + ret = PTR_ERR(rtc->rtc);
8614 + goto out_iounmap;
8615 + }
8616 +
8617 + platform_set_drvdata(pdev, rtc);
8618 +
8619 + dev_info(&pdev->dev, "Atmel RTC for AT32AP700x at %08lx irq %ld\n",
8620 + (unsigned long)rtc->regs, rtc->irq);
8621 +
8622 + return 0;
8623 +
8624 +out_iounmap:
8625 + iounmap(rtc->regs);
8626 +out_free_irq:
8627 + free_irq(irq, rtc);
8628 +out:
8629 + kfree(rtc);
8630 + return ret;
8631 +}
8632 +
8633 +static int __exit at32_rtc_remove(struct platform_device *pdev)
8634 +{
8635 + struct rtc_at32ap700x *rtc = platform_get_drvdata(pdev);
8636 +
8637 + free_irq(rtc->irq, rtc);
8638 + iounmap(rtc->regs);
8639 + rtc_device_unregister(rtc->rtc);
8640 + kfree(rtc);
8641 + platform_set_drvdata(pdev, NULL);
8642 +
8643 + return 0;
8644 +}
8645 +
8646 +static struct platform_driver at32_rtc_driver = {
8647 + .remove = __exit_p(at32_rtc_remove),
8648 + .driver = {
8649 + .name = "rtc-at32ap700x",
8650 + .owner = THIS_MODULE,
8651 + },
8652 +};
8653 +
8654 +static int __init at32_rtc_init(void)
8655 +{
8656 + return platform_driver_probe(&at32_rtc_driver, at32_rtc_probe);
8657 +}
8658 +module_init(at32_rtc_init);
8659 +
8660 +static void __exit at32_rtc_exit(void)
8661 +{
8662 + platform_driver_unregister(&at32_rtc_driver);
8663 +}
8664 +module_exit(at32_rtc_exit);
8665 +
8666 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
8667 +MODULE_DESCRIPTION("Real time clock for AVR32 AT32AP700x");
8668 +MODULE_LICENSE("GPL");
8669 diff -x .git -Nur linux-2.6.22.1/drivers/serial/atmel_serial.c linux-avr32.git/drivers/serial/atmel_serial.c
8670 --- linux-2.6.22.1/drivers/serial/atmel_serial.c 2007-07-10 20:56:30.000000000 +0200
8671 +++ linux-avr32.git/drivers/serial/atmel_serial.c 2007-06-06 11:33:59.000000000 +0200
8672 @@ -114,6 +114,7 @@
8673 struct uart_port uart; /* uart */
8674 struct clk *clk; /* uart clock */
8675 unsigned short suspended; /* is port suspended? */
8676 + int break_active; /* break being received */
8677 };
8678
8679 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
8680 @@ -252,6 +253,7 @@
8681 */
8682 static void atmel_rx_chars(struct uart_port *port)
8683 {
8684 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
8685 struct tty_struct *tty = port->info->tty;
8686 unsigned int status, ch, flg;
8687
8688 @@ -267,13 +269,29 @@
8689 * note that the error handling code is
8690 * out of the main execution path
8691 */
8692 - if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
8693 + if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
8694 + | ATMEL_US_OVRE | ATMEL_US_RXBRK)
8695 + || atmel_port->break_active)) {
8696 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
8697 - if (status & ATMEL_US_RXBRK) {
8698 + if (status & ATMEL_US_RXBRK
8699 + && !atmel_port->break_active) {
8700 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
8701 port->icount.brk++;
8702 + atmel_port->break_active = 1;
8703 + UART_PUT_IER(port, ATMEL_US_RXBRK);
8704 if (uart_handle_break(port))
8705 goto ignore_char;
8706 + } else {
8707 + /*
8708 + * This is either the end-of-break
8709 + * condition or we've received at
8710 + * least one character without RXBRK
8711 + * being set. In both cases, the next
8712 + * RXBRK will indicate start-of-break.
8713 + */
8714 + UART_PUT_IDR(port, ATMEL_US_RXBRK);
8715 + status &= ~ATMEL_US_RXBRK;
8716 + atmel_port->break_active = 0;
8717 }
8718 if (status & ATMEL_US_PARE)
8719 port->icount.parity++;
8720 @@ -352,6 +370,16 @@
8721 /* Interrupt receive */
8722 if (pending & ATMEL_US_RXRDY)
8723 atmel_rx_chars(port);
8724 + else if (pending & ATMEL_US_RXBRK) {
8725 + /*
8726 + * End of break detected. If it came along
8727 + * with a character, atmel_rx_chars will
8728 + * handle it.
8729 + */
8730 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
8731 + UART_PUT_IDR(port, ATMEL_US_RXBRK);
8732 + atmel_port->break_active = 0;
8733 + }
8734
8735 // TODO: All reads to CSR will clear these interrupts!
8736 if (pending & ATMEL_US_RIIC) port->icount.rng++;
8737 diff -x .git -Nur linux-2.6.22.1/drivers/spi/atmel_spi.c linux-avr32.git/drivers/spi/atmel_spi.c
8738 --- linux-2.6.22.1/drivers/spi/atmel_spi.c 2007-07-10 20:56:30.000000000 +0200
8739 +++ linux-avr32.git/drivers/spi/atmel_spi.c 2007-06-06 11:33:59.000000000 +0200
8740 @@ -412,8 +412,8 @@
8741 csr |= SPI_BIT(NCPHA);
8742
8743 /* TODO: DLYBS and DLYBCT */
8744 - csr |= SPI_BF(DLYBS, 10);
8745 - csr |= SPI_BF(DLYBCT, 10);
8746 + csr |= SPI_BF(DLYBS, 0);
8747 + csr |= SPI_BF(DLYBCT, 0);
8748
8749 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
8750 npcs_pin = (unsigned int)spi->controller_data;
8751 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.c linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.c
8752 --- linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.c 1970-01-01 01:00:00.000000000 +0100
8753 +++ linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.c 2007-07-12 14:00:19.000000000 +0200
8754 @@ -0,0 +1,2072 @@
8755 +/*
8756 + * Driver for the Atmel USBA high speed USB device controller
8757 + *
8758 + * Copyright (C) 2005-2007 Atmel Corporation
8759 + *
8760 + * This program is free software; you can redistribute it and/or modify
8761 + * it under the terms of the GNU General Public License version 2 as
8762 + * published by the Free Software Foundation.
8763 + */
8764 +/* #define DEBUG */
8765 +
8766 +#include <linux/clk.h>
8767 +#include <linux/module.h>
8768 +#include <linux/init.h>
8769 +#include <linux/interrupt.h>
8770 +#include <linux/io.h>
8771 +#include <linux/device.h>
8772 +#include <linux/dma-mapping.h>
8773 +#include <linux/list.h>
8774 +#include <linux/platform_device.h>
8775 +#include <linux/usb/ch9.h>
8776 +#include <linux/usb_gadget.h>
8777 +#include <linux/delay.h>
8778 +
8779 +#include <asm/gpio.h>
8780 +#include <asm/arch/board.h>
8781 +
8782 +#include "atmel_usba_udc.h"
8783 +
8784 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
8785 +
8786 +#define FIFO_IOMEM_ID 0
8787 +#define CTRL_IOMEM_ID 1
8788 +
8789 +#ifdef DEBUG
8790 +#define DBG_ERR 0x0001 /* report all error returns */
8791 +#define DBG_HW 0x0002 /* debug hardware initialization */
8792 +#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
8793 +#define DBG_INT 0x0008 /* interrupts */
8794 +#define DBG_BUS 0x0010 /* report changes in bus state */
8795 +#define DBG_QUEUE 0x0020 /* debug request queue processing */
8796 +#define DBG_FIFO 0x0040 /* debug FIFO contents */
8797 +#define DBG_DMA 0x0080 /* debug DMA handling */
8798 +#define DBG_REQ 0x0100 /* print out queued request length */
8799 +#define DBG_ALL 0xffff
8800 +#define DBG_NONE 0x0000
8801 +
8802 +#define DEBUG_LEVEL (DBG_ERR)
8803 +#define DBG(level, fmt, ...) \
8804 + do { \
8805 + if ((level) & DEBUG_LEVEL) \
8806 + printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
8807 + } while (0)
8808 +#else
8809 +#define DBG(level, fmt...)
8810 +#endif
8811 +
8812 +static struct usba_udc the_udc;
8813 +
8814 +#ifdef CONFIG_DEBUG_FS
8815 +#include <linux/debugfs.h>
8816 +#include <linux/uaccess.h>
8817 +
8818 +static int queue_dbg_open(struct inode *inode, struct file *file)
8819 +{
8820 + struct usba_ep *ep = inode->i_private;
8821 + struct usba_request *req, *req_copy;
8822 + struct list_head *queue_data;
8823 +
8824 + queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
8825 + if (!queue_data)
8826 + return -ENOMEM;
8827 + INIT_LIST_HEAD(queue_data);
8828 +
8829 + spin_lock_irq(&ep->udc->lock);
8830 + list_for_each_entry(req, &ep->queue, queue) {
8831 + req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
8832 + if (!req_copy)
8833 + goto fail;
8834 + memcpy(req_copy, req, sizeof(*req_copy));
8835 + list_add_tail(&req_copy->queue, queue_data);
8836 + }
8837 + spin_unlock_irq(&ep->udc->lock);
8838 +
8839 + file->private_data = queue_data;
8840 + return 0;
8841 +
8842 +fail:
8843 + spin_unlock_irq(&ep->udc->lock);
8844 + list_for_each_entry_safe(req, req_copy, queue_data, queue) {
8845 + list_del(&req->queue);
8846 + kfree(req);
8847 + }
8848 + kfree(queue_data);
8849 + return -ENOMEM;
8850 +}
8851 +
8852 +/*
8853 + * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
8854 + *
8855 + * b: buffer address
8856 + * l: buffer length
8857 + * I/i: interrupt/no interrupt
8858 + * Z/z: zero/no zero
8859 + * S/s: short ok/short not ok
8860 + * s: status
8861 + * n: nr_packets
8862 + * F/f: submitted/not submitted to FIFO
8863 + * D/d: using/not using DMA
8864 + * L/l: last transaction/not last transaction
8865 + */
8866 +static ssize_t queue_dbg_read(struct file *file, char __user *buf,
8867 + size_t nbytes, loff_t *ppos)
8868 +{
8869 + struct list_head *queue = file->private_data;
8870 + struct usba_request *req, *tmp_req;
8871 + size_t len, remaining, actual = 0;
8872 + char tmpbuf[38];
8873 +
8874 + if (!access_ok(VERIFY_WRITE, buf, nbytes))
8875 + return -EFAULT;
8876 +
8877 + mutex_lock(&file->f_dentry->d_inode->i_mutex);
8878 + list_for_each_entry_safe(req, tmp_req, queue, queue) {
8879 + len = snprintf(tmpbuf, sizeof(tmpbuf),
8880 + "%8p %08x %c%c%c %5d %c%c%c\n",
8881 + req->req.buf, req->req.length,
8882 + req->req.no_interrupt ? 'i' : 'I',
8883 + req->req.zero ? 'Z' : 'z',
8884 + req->req.short_not_ok ? 's' : 'S',
8885 + req->req.status,
8886 + req->submitted ? 'F' : 'f',
8887 + req->using_dma ? 'D' : 'd',
8888 + req->last_transaction ? 'L' : 'l');
8889 + len = min(len, sizeof(tmpbuf));
8890 + if (len > nbytes)
8891 + break;
8892 +
8893 + list_del(&req->queue);
8894 + kfree(req);
8895 +
8896 + remaining = __copy_to_user(buf, tmpbuf, len);
8897 + actual += len - remaining;
8898 + if (remaining)
8899 + break;
8900 +
8901 + nbytes -= len;
8902 + buf += len;
8903 + }
8904 + mutex_unlock(&file->f_dentry->d_inode->i_mutex);
8905 +
8906 + return actual;
8907 +}
8908 +
8909 +static int queue_dbg_release(struct inode *inode, struct file *file)
8910 +{
8911 + struct list_head *queue_data = file->private_data;
8912 + struct usba_request *req, *tmp_req;
8913 +
8914 + list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
8915 + list_del(&req->queue);
8916 + kfree(req);
8917 + }
8918 + kfree(queue_data);
8919 + return 0;
8920 +}
8921 +
8922 +static int regs_dbg_open(struct inode *inode, struct file *file)
8923 +{
8924 + struct usba_udc *udc;
8925 + unsigned int i;
8926 + u32 *data;
8927 + int ret = -ENOMEM;
8928 +
8929 + mutex_lock(&inode->i_mutex);
8930 + udc = inode->i_private;
8931 + data = kmalloc(inode->i_size, GFP_KERNEL);
8932 + if (!data)
8933 + goto out;
8934 +
8935 + spin_lock_irq(&udc->lock);
8936 + for (i = 0; i < inode->i_size / 4; i++)
8937 + data[i] = __raw_readl(udc->regs + i * 4);
8938 + spin_unlock_irq(&udc->lock);
8939 +
8940 + file->private_data = data;
8941 + ret = 0;
8942 +
8943 +out:
8944 + mutex_unlock(&inode->i_mutex);
8945 +
8946 + return ret;
8947 +}
8948 +
8949 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
8950 + size_t nbytes, loff_t *ppos)
8951 +{
8952 + struct inode *inode = file->f_dentry->d_inode;
8953 + int ret;
8954 +
8955 + mutex_lock(&inode->i_mutex);
8956 + ret = simple_read_from_buffer(buf, nbytes, ppos,
8957 + file->private_data,
8958 + file->f_dentry->d_inode->i_size);
8959 + mutex_unlock(&inode->i_mutex);
8960 +
8961 + return ret;
8962 +}
8963 +
8964 +static int regs_dbg_release(struct inode *inode, struct file *file)
8965 +{
8966 + kfree(file->private_data);
8967 + return 0;
8968 +}
8969 +
8970 +const struct file_operations queue_dbg_fops = {
8971 + .owner = THIS_MODULE,
8972 + .open = queue_dbg_open,
8973 + .llseek = no_llseek,
8974 + .read = queue_dbg_read,
8975 + .release = queue_dbg_release,
8976 +};
8977 +
8978 +const struct file_operations regs_dbg_fops = {
8979 + .owner = THIS_MODULE,
8980 + .open = regs_dbg_open,
8981 + .llseek = generic_file_llseek,
8982 + .read = regs_dbg_read,
8983 + .release = regs_dbg_release,
8984 +};
8985 +
8986 +static void usba_ep_init_debugfs(struct usba_udc *udc,
8987 + struct usba_ep *ep)
8988 +{
8989 + struct dentry *ep_root;
8990 +
8991 + ep_root = debugfs_create_dir(ep_name(ep), udc->debugfs_root);
8992 + if (!ep_root)
8993 + goto err_root;
8994 + ep->debugfs_dir = ep_root;
8995 +
8996 + ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
8997 + ep, &queue_dbg_fops);
8998 + if (!ep->debugfs_queue)
8999 + goto err_queue;
9000 +
9001 + if (ep_can_dma(ep)) {
9002 + ep->debugfs_dma_status
9003 + = debugfs_create_u32("dma_status", 0400, ep_root,
9004 + &ep->last_dma_status);
9005 + if (!ep->debugfs_dma_status)
9006 + goto err_dma_status;
9007 + }
9008 + if (ep_is_control(ep)) {
9009 + ep->debugfs_state
9010 + = debugfs_create_u32("state", 0400, ep_root,
9011 + &ep->state);
9012 + if (!ep->debugfs_state)
9013 + goto err_state;
9014 + }
9015 +
9016 + return;
9017 +
9018 +err_state:
9019 + if (ep_can_dma(ep))
9020 + debugfs_remove(ep->debugfs_dma_status);
9021 +err_dma_status:
9022 + debugfs_remove(ep->debugfs_queue);
9023 +err_queue:
9024 + debugfs_remove(ep_root);
9025 +err_root:
9026 + dev_err(&ep->udc->pdev->dev,
9027 + "failed to create debugfs directory for %s\n", ep_name(ep));
9028 +}
9029 +
9030 +static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
9031 +{
9032 + debugfs_remove(ep->debugfs_queue);
9033 + debugfs_remove(ep->debugfs_dma_status);
9034 + debugfs_remove(ep->debugfs_state);
9035 + debugfs_remove(ep->debugfs_dir);
9036 + ep->debugfs_dma_status = NULL;
9037 + ep->debugfs_dir = NULL;
9038 +}
9039 +
9040 +static void usba_init_debugfs(struct usba_udc *udc)
9041 +{
9042 + struct dentry *root, *regs;
9043 + struct resource *regs_resource;
9044 +
9045 + root = debugfs_create_dir(udc->gadget.name, NULL);
9046 + if (IS_ERR(root) || !root)
9047 + goto err_root;
9048 + udc->debugfs_root = root;
9049 +
9050 + regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
9051 + if (!regs)
9052 + goto err_regs;
9053 +
9054 + regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
9055 + CTRL_IOMEM_ID);
9056 + regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
9057 + udc->debugfs_regs = regs;
9058 +
9059 + usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
9060 +
9061 + return;
9062 +
9063 +err_regs:
9064 + debugfs_remove(root);
9065 +err_root:
9066 + udc->debugfs_root = NULL;
9067 + dev_err(&udc->pdev->dev, "debugfs is not available\n");
9068 +}
9069 +
9070 +static void usba_cleanup_debugfs(struct usba_udc *udc)
9071 +{
9072 + usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
9073 + debugfs_remove(udc->debugfs_regs);
9074 + debugfs_remove(udc->debugfs_root);
9075 + udc->debugfs_regs = NULL;
9076 + udc->debugfs_root = NULL;
9077 +}
9078 +#else
9079 +static inline void usba_ep_init_debugfs(struct usba_udc *udc,
9080 + struct usba_ep *ep)
9081 +{
9082 +
9083 +}
9084 +
9085 +static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
9086 +{
9087 +
9088 +}
9089 +
9090 +static inline void usba_init_debugfs(struct usba_udc *udc)
9091 +{
9092 +
9093 +}
9094 +
9095 +static inline void usba_cleanup_debugfs(struct usba_udc *udc)
9096 +{
9097 +
9098 +}
9099 +#endif
9100 +
9101 +static int vbus_is_present(struct usba_udc *udc)
9102 +{
9103 + if (udc->vbus_pin != -1)
9104 + return gpio_get_value(udc->vbus_pin);
9105 +
9106 + /* No Vbus detection: Assume always present */
9107 + return 1;
9108 +}
9109 +
9110 +static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
9111 +{
9112 + unsigned long tmp;
9113 +
9114 + DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
9115 + for (; len > 0; len -= 4, buf += 4, fifo += 4) {
9116 + tmp = *(unsigned long *)buf;
9117 + if (len >= 4) {
9118 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
9119 + __raw_writel(tmp, fifo);
9120 + } else {
9121 + do {
9122 + DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
9123 + __raw_writeb(tmp >> 24, fifo);
9124 + fifo++;
9125 + tmp <<= 8;
9126 + } while (--len);
9127 + break;
9128 + }
9129 + }
9130 +}
9131 +
9132 +static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
9133 +{
9134 + union {
9135 + unsigned long *w;
9136 + unsigned char *b;
9137 + } p;
9138 + unsigned long tmp;
9139 +
9140 + DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
9141 + for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
9142 + if (len >= 4) {
9143 + tmp = __raw_readl(fifo);
9144 + *p.w = tmp;
9145 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
9146 + } else {
9147 + do {
9148 + tmp = __raw_readb(fifo);
9149 + *p.b = tmp;
9150 + DBG(DBG_FIFO, " -> %02lx\n", tmp);
9151 + fifo++, p.b++;
9152 + } while (--len);
9153 + }
9154 + }
9155 +}
9156 +
9157 +static void next_fifo_transaction(struct usba_ep *ep,
9158 + struct usba_request *req)
9159 +{
9160 + unsigned int transaction_len;
9161 +
9162 + transaction_len = req->req.length - req->req.actual;
9163 + req->last_transaction = 1;
9164 + if (transaction_len > ep->ep.maxpacket) {
9165 + transaction_len = ep->ep.maxpacket;
9166 + req->last_transaction = 0;
9167 + } else if (transaction_len == ep->ep.maxpacket
9168 + && req->req.zero) {
9169 + req->last_transaction = 0;
9170 + }
9171 + DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
9172 + ep_name(ep), req, transaction_len,
9173 + req->last_transaction ? ", done" : "");
9174 +
9175 + copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
9176 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
9177 + req->req.actual += transaction_len;
9178 +}
9179 +
9180 +static void submit_request(struct usba_ep *ep, struct usba_request *req)
9181 +{
9182 + DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
9183 + ep_name(ep), req, req->req.length);
9184 +
9185 + req->req.actual = 0;
9186 + req->submitted = 1;
9187 +
9188 + if (req->using_dma) {
9189 + if (req->req.length == 0) {
9190 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
9191 + return;
9192 + }
9193 +
9194 + if (req->req.zero)
9195 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(SHORT_PACKET));
9196 + else
9197 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(SHORT_PACKET));
9198 +
9199 + usba_dma_writel(ep, ADDRESS, req->req.dma);
9200 + usba_dma_writel(ep, CONTROL, req->ctrl);
9201 + } else {
9202 + next_fifo_transaction(ep, req);
9203 + if (req->last_transaction) {
9204 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
9205 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
9206 + } else {
9207 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
9208 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
9209 + }
9210 + }
9211 +}
9212 +
9213 +static void submit_next_request(struct usba_ep *ep)
9214 +{
9215 + struct usba_request *req;
9216 +
9217 + if (list_empty(&ep->queue)) {
9218 + usba_ep_writel(ep, CTL_DIS, (USBA_BIT(TX_PK_RDY)
9219 + | USBA_BIT(RX_BK_RDY)));
9220 + return;
9221 + }
9222 +
9223 + req = list_entry(ep->queue.next, struct usba_request, queue);
9224 + if (!req->submitted)
9225 + submit_request(ep, req);
9226 +}
9227 +
9228 +static void send_status(struct usba_udc *udc, struct usba_ep *ep)
9229 +{
9230 + ep->state = STATUS_STAGE_IN;
9231 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
9232 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
9233 +}
9234 +
9235 +static void receive_data(struct usba_ep *ep)
9236 +{
9237 + struct usba_udc *udc = ep->udc;
9238 + struct usba_request *req;
9239 + unsigned long status;
9240 + unsigned int bytecount, nr_busy;
9241 + int is_complete = 0;
9242 +
9243 + status = usba_ep_readl(ep, STA);
9244 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
9245 +
9246 + DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
9247 +
9248 + while (nr_busy > 0) {
9249 + if (list_empty(&ep->queue)) {
9250 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
9251 + break;
9252 + }
9253 + req = list_entry(ep->queue.next,
9254 + struct usba_request, queue);
9255 +
9256 + bytecount = USBA_BFEXT(BYTE_COUNT, status);
9257 +
9258 + if (status & (1 << 31))
9259 + is_complete = 1;
9260 + if (req->req.actual + bytecount >= req->req.length) {
9261 + is_complete = 1;
9262 + bytecount = req->req.length - req->req.actual;
9263 + }
9264 +
9265 + copy_from_fifo(req->req.buf + req->req.actual,
9266 + ep->fifo, bytecount);
9267 + req->req.actual += bytecount;
9268 +
9269 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
9270 +
9271 + if (is_complete) {
9272 + DBG(DBG_QUEUE, "%s: request done\n", ep_name(ep));
9273 + req->req.status = 0;
9274 + list_del_init(&req->queue);
9275 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
9276 + req->req.complete(&ep->ep, &req->req);
9277 + }
9278 +
9279 + status = usba_ep_readl(ep, STA);
9280 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
9281 +
9282 + if (is_complete && ep_is_control(ep)) {
9283 + send_status(udc, ep);
9284 + break;
9285 + }
9286 + }
9287 +}
9288 +
9289 +static void request_complete(struct usba_ep *ep,
9290 + struct usba_request *req,
9291 + int status)
9292 +{
9293 + struct usba_udc *udc = ep->udc;
9294 +
9295 + WARN_ON(!list_empty(&req->queue));
9296 +
9297 + if (req->req.status == -EINPROGRESS)
9298 + req->req.status = status;
9299 +
9300 + if (req->mapped) {
9301 + dma_unmap_single(
9302 + &udc->pdev->dev, req->req.dma, req->req.length,
9303 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9304 + req->req.dma = DMA_ADDR_INVALID;
9305 + req->mapped = 0;
9306 + }
9307 +
9308 + DBG(DBG_GADGET | DBG_REQ,
9309 + "%s: req %p complete: status %d, actual %u\n",
9310 + ep_name(ep), req, req->req.status, req->req.actual);
9311 + req->req.complete(&ep->ep, &req->req);
9312 +}
9313 +
9314 +static void request_complete_list(struct usba_ep *ep,
9315 + struct list_head *list,
9316 + int status)
9317 +{
9318 + struct usba_request *req, *tmp_req;
9319 +
9320 + list_for_each_entry_safe(req, tmp_req, list, queue) {
9321 + list_del_init(&req->queue);
9322 + request_complete(ep, req, status);
9323 + }
9324 +}
9325 +
9326 +static int usba_ep_enable(struct usb_ep *_ep,
9327 + const struct usb_endpoint_descriptor *desc)
9328 +{
9329 + struct usba_ep *ep = to_usba_ep(_ep);
9330 + struct usba_udc *udc = ep->udc;
9331 + unsigned long flags, ept_cfg, maxpacket;
9332 +
9333 + DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep_name(ep), desc);
9334 +
9335 + maxpacket = le16_to_cpu(desc->wMaxPacketSize);
9336 +
9337 + if (ep->index == 0
9338 + || desc->bDescriptorType != USB_DT_ENDPOINT
9339 + || ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
9340 + != ep->index)
9341 + || maxpacket == 0
9342 + || maxpacket > ep->fifo_size) {
9343 + DBG(DBG_ERR, "ep_enable: Invalid argument");
9344 + return -EINVAL;
9345 + }
9346 +
9347 + ep->is_isoc = 0;
9348 + ep->is_in = 0;
9349 +
9350 + if ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
9351 + == USB_ENDPOINT_XFER_ISOC) {
9352 + if (!ep->can_isoc) {
9353 + DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
9354 + ep_name(ep));
9355 + return -EINVAL;
9356 + }
9357 + ep->is_isoc = 1;
9358 + }
9359 +
9360 + if (maxpacket <= 8)
9361 + ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
9362 + else
9363 + /* LSB is bit 1, not 0 */
9364 + ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
9365 + DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
9366 + ep_name(ep), ept_cfg, maxpacket);
9367 +
9368 + if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
9369 + ep->is_in = 1;
9370 + ept_cfg |= USBA_BIT(EPT_DIR);
9371 + }
9372 +
9373 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
9374 + case USB_ENDPOINT_XFER_CONTROL:
9375 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
9376 + break;
9377 + case USB_ENDPOINT_XFER_ISOC:
9378 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
9379 + break;
9380 + case USB_ENDPOINT_XFER_BULK:
9381 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
9382 + break;
9383 + case USB_ENDPOINT_XFER_INT:
9384 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
9385 + break;
9386 + }
9387 + ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
9388 +
9389 + spin_lock_irqsave(&ep->udc->lock, flags);
9390 +
9391 + if (ep->desc) {
9392 + spin_unlock_irqrestore(&ep->udc->lock, flags);
9393 + DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
9394 + return -EBUSY;
9395 + }
9396 +
9397 + ep->desc = desc;
9398 + ep->ep.maxpacket = maxpacket;
9399 +
9400 + usba_ep_writel(ep, CFG, ept_cfg);
9401 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
9402 +
9403 + if (ep_can_dma(ep)) {
9404 + u32 ctrl;
9405 +
9406 + usba_writel(udc, INT_ENB,
9407 + (usba_readl(udc, INT_ENB)
9408 + | USBA_BF(EPT_INT, 1 << ep->index)
9409 + | USBA_BF(DMA_INT, 1 << ep->index)));
9410 + ctrl = USBA_BIT(AUTO_VALID) | USBA_BIT(INTDIS_DMA);
9411 + usba_ep_writel(ep, CTL_ENB, ctrl);
9412 + } else {
9413 + usba_writel(udc, INT_ENB,
9414 + (usba_readl(udc, INT_ENB)
9415 + | USBA_BF(EPT_INT, 1 << ep->index)));
9416 + }
9417 +
9418 + spin_unlock_irqrestore(&udc->lock, flags);
9419 +
9420 + DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
9421 + (unsigned long)usba_ep_readl(ep, CFG));
9422 + DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
9423 + (unsigned long)usba_readl(udc, INT_ENB));
9424 +
9425 + return 0;
9426 +}
9427 +
9428 +static int usba_ep_disable(struct usb_ep *_ep)
9429 +{
9430 + struct usba_ep *ep = to_usba_ep(_ep);
9431 + struct usba_udc *udc = ep->udc;
9432 + LIST_HEAD(req_list);
9433 + unsigned long flags;
9434 +
9435 + DBG(DBG_GADGET, "ep_disable: %s\n", ep_name(ep));
9436 +
9437 + spin_lock_irqsave(&udc->lock, flags);
9438 +
9439 + if (!ep->desc) {
9440 + spin_unlock_irqrestore(&udc->lock, flags);
9441 + DBG(DBG_ERR, "ep_disable: %s not enabled\n",
9442 + ep_name(ep));
9443 + return -EINVAL;
9444 + }
9445 + ep->desc = NULL;
9446 +
9447 + list_splice_init(&ep->queue, &req_list);
9448 + if (ep_can_dma(ep)) {
9449 + usba_dma_writel(ep, CONTROL, 0);
9450 + usba_dma_writel(ep, ADDRESS, 0);
9451 + usba_dma_readl(ep, STATUS);
9452 + }
9453 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(EPT_ENABLE));
9454 + usba_writel(udc, INT_ENB, (usba_readl(udc, INT_ENB)
9455 + & ~USBA_BF(EPT_INT, 1 << ep->index)));
9456 +
9457 + spin_unlock_irqrestore(&udc->lock, flags);
9458 +
9459 + request_complete_list(ep, &req_list, -ESHUTDOWN);
9460 +
9461 + return 0;
9462 +}
9463 +
9464 +static struct usb_request *
9465 +usba_ep_alloc_request(struct usb_ep *_ep, unsigned gfp_flags)
9466 +{
9467 + struct usba_request *req;
9468 +
9469 + DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
9470 +
9471 + req = kzalloc(sizeof(*req), gfp_flags);
9472 + if (!req)
9473 + return NULL;
9474 +
9475 + INIT_LIST_HEAD(&req->queue);
9476 + req->req.dma = DMA_ADDR_INVALID;
9477 +
9478 + return &req->req;
9479 +}
9480 +
9481 +static void
9482 +usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
9483 +{
9484 + struct usba_request *req = to_usba_req(_req);
9485 +
9486 + DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
9487 +
9488 + kfree(req);
9489 +}
9490 +
9491 +static void *usba_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
9492 + dma_addr_t *dma, unsigned gfp_flags)
9493 +{
9494 + void *buf;
9495 +
9496 + if (bytes < L1_CACHE_BYTES)
9497 + bytes = L1_CACHE_BYTES;
9498 +
9499 + buf = kmalloc(bytes, gfp_flags);
9500 +
9501 + /*
9502 + * Seems like we have to map the buffer any chance we get.
9503 + * ether.c wants us to initialize the dma member of a
9504 + * different request than the one receiving the buffer, so one
9505 + * never knows...
9506 + *
9507 + * Ah, screw it. The ether driver is probably wrong, and this
9508 + * is not the right place to do the mapping. The driver
9509 + * shouldn't mess with our DMA mappings anyway.
9510 + */
9511 + *dma = DMA_ADDR_INVALID;
9512 +
9513 + return buf;
9514 +}
9515 +
9516 +static void usba_ep_free_buffer(struct usb_ep *_ep, void *buf,
9517 + dma_addr_t dma, unsigned bytes)
9518 +{
9519 + DBG(DBG_GADGET, "ep_free_buffer: %s, buf %p (size %u)\n",
9520 + _ep->name, buf, bytes);
9521 + kfree(buf);
9522 +}
9523 +
9524 +static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
9525 + struct usba_request *req, gfp_t gfp_flags)
9526 +{
9527 + unsigned long flags;
9528 + int ret;
9529 +
9530 + DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
9531 + ep_name(ep), req->req.length, req->req.dma,
9532 + req->req.zero ? 'Z' : 'z',
9533 + req->req.short_not_ok ? 'S' : 's',
9534 + req->req.no_interrupt ? 'I' : 'i');
9535 +
9536 + if (req->req.length > 0x10000) {
9537 + /* Lengths from 0 to 65536 (inclusive) are supported */
9538 + DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
9539 + return -EINVAL;
9540 + }
9541 +
9542 + req->using_dma = 1;
9543 +
9544 + if (req->req.dma == DMA_ADDR_INVALID) {
9545 + req->req.dma = dma_map_single(
9546 + &udc->pdev->dev, req->req.buf, req->req.length,
9547 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9548 + req->mapped = 1;
9549 + } else {
9550 + dma_sync_single_for_device(
9551 + &udc->pdev->dev, req->req.dma, req->req.length,
9552 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9553 + req->mapped = 0;
9554 + }
9555 +
9556 + req->ctrl = (USBA_BF(DMA_BUF_LEN, req->req.length)
9557 + | USBA_BIT(DMA_CH_EN) | USBA_BIT(DMA_END_BUF_IE)
9558 + | USBA_BIT(DMA_END_TR_EN) | USBA_BIT(DMA_END_TR_IE));
9559 +
9560 + if (ep_is_in(ep))
9561 + req->ctrl |= USBA_BIT(DMA_END_BUF_EN);
9562 +
9563 + /*
9564 + * Add this request to the queue and submit for DMA if
9565 + * possible. Check if we're still alive first -- we may have
9566 + * received a reset since last time we checked.
9567 + */
9568 + ret = -ESHUTDOWN;
9569 + spin_lock_irqsave(&udc->lock, flags);
9570 + if (ep->desc) {
9571 + if (list_empty(&ep->queue))
9572 + submit_request(ep, req);
9573 +
9574 + list_add_tail(&req->queue, &ep->queue);
9575 + ret = 0;
9576 + }
9577 + spin_unlock_irqrestore(&udc->lock, flags);
9578 +
9579 + return ret;
9580 +}
9581 +
9582 +static int usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
9583 + gfp_t gfp_flags)
9584 +{
9585 + struct usba_request *req = to_usba_req(_req);
9586 + struct usba_ep *ep = to_usba_ep(_ep);
9587 + struct usba_udc *udc = ep->udc;
9588 + unsigned long flags;
9589 + int ret;
9590 +
9591 + DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ,
9592 + "%s: queue req %p, len %u\n", ep_name(ep), req, _req->length);
9593 +
9594 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN
9595 + || !ep->desc)
9596 + return -ESHUTDOWN;
9597 +
9598 + req->submitted = 0;
9599 + req->using_dma = 0;
9600 + req->last_transaction = 0;
9601 +
9602 + _req->status = -EINPROGRESS;
9603 + _req->actual = 0;
9604 +
9605 + if (ep_can_dma(ep))
9606 + return queue_dma(udc, ep, req, gfp_flags);
9607 +
9608 + /* May have received a reset since last time we checked */
9609 + ret = -ESHUTDOWN;
9610 + spin_lock_irqsave(&udc->lock, flags);
9611 + if (ep->desc) {
9612 + list_add_tail(&req->queue, &ep->queue);
9613 +
9614 + if (ep_is_in(ep)
9615 + || (ep_is_control(ep)
9616 + && (ep->state == DATA_STAGE_IN
9617 + || ep->state == STATUS_STAGE_IN)))
9618 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
9619 + else
9620 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(RX_BK_RDY));
9621 + ret = 0;
9622 + }
9623 + spin_unlock_irqrestore(&udc->lock, flags);
9624 +
9625 + return ret;
9626 +}
9627 +
9628 +static void usba_update_req(struct usba_ep *ep, struct usba_request *req,
9629 + u32 status)
9630 +{
9631 + req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
9632 +}
9633 +
9634 +static int stop_dma(struct usba_ep *ep, u32 *pstatus)
9635 +{
9636 + unsigned int timeout;
9637 + u32 status;
9638 +
9639 + /*
9640 + * Stop the DMA controller. When writing both CH_EN
9641 + * and LINK to 0, the other bits are not affected.
9642 + */
9643 + usba_dma_writel(ep, CONTROL, 0);
9644 +
9645 + /* Wait for the FIFO to empty */
9646 + for (timeout = 40; timeout; --timeout) {
9647 + status = usba_dma_readl(ep, STATUS);
9648 + if (!(status & USBA_BIT(DMA_CH_EN)))
9649 + break;
9650 + udelay(1);
9651 + }
9652 +
9653 + if (pstatus)
9654 + *pstatus = status;
9655 +
9656 + if (timeout == 0) {
9657 + dev_err(&ep->udc->pdev->dev,
9658 + "%s: timed out waiting for DMA FIFO to empty\n",
9659 + ep_name(ep));
9660 + return -ETIMEDOUT;
9661 + }
9662 +
9663 + return 0;
9664 +}
9665 +
9666 +static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
9667 +{
9668 + struct usba_ep *ep = to_usba_ep(_ep);
9669 + struct usba_udc *udc = ep->udc;
9670 + struct usba_request *req = to_usba_req(_req);
9671 + unsigned long flags;
9672 + u32 status;
9673 +
9674 + DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
9675 + ep_name(ep), req);
9676 +
9677 + spin_lock_irqsave(&udc->lock, flags);
9678 +
9679 + if (req->using_dma) {
9680 + /*
9681 + * If this request is currently being transferred,
9682 + * stop the DMA controller and reset the FIFO.
9683 + */
9684 + if (ep->queue.next == &req->queue) {
9685 + status = usba_dma_readl(ep, STATUS);
9686 + if (status & USBA_BIT(DMA_CH_EN))
9687 + stop_dma(ep, &status);
9688 +
9689 +#ifdef CONFIG_DEBUG_FS
9690 + ep->last_dma_status = status;
9691 +#endif
9692 +
9693 + usba_writel(udc, EPT_RST,
9694 + 1 << ep_index(ep));
9695 +
9696 + usba_update_req(ep, req, status);
9697 + }
9698 + }
9699 +
9700 + /*
9701 + * Errors should stop the queue from advancing until the
9702 + * completion function returns.
9703 + */
9704 + list_del_init(&req->queue);
9705 + spin_unlock_irqrestore(&udc->lock, flags);
9706 +
9707 + request_complete(ep, req, -ECONNRESET);
9708 +
9709 + /* Process the next request if any */
9710 + spin_lock_irqsave(&udc->lock, flags);
9711 + submit_next_request(ep);
9712 + spin_unlock_irqrestore(&udc->lock, flags);
9713 +
9714 + return 0;
9715 +}
9716 +
9717 +static int usba_ep_set_halt(struct usb_ep *_ep, int value)
9718 +{
9719 + struct usba_ep *ep = to_usba_ep(_ep);
9720 + struct usba_udc *udc = ep->udc;
9721 + unsigned long flags;
9722 + int ret = 0;
9723 +
9724 + DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep_name(ep),
9725 + value ? "set" : "clear");
9726 +
9727 + if (!ep->desc) {
9728 + DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
9729 + ep_name(ep));
9730 + return -ENODEV;
9731 + }
9732 + if (ep_is_isochronous(ep)) {
9733 + DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
9734 + ep_name(ep));
9735 + return -ENOTTY;
9736 + }
9737 +
9738 + spin_lock_irqsave(&udc->lock, flags);
9739 +
9740 + /*
9741 + * We can't halt IN endpoints while there are still data to be
9742 + * transferred
9743 + */
9744 + if (!list_empty(&ep->queue)
9745 + || ((value && ep_is_in(ep)
9746 + && (usba_ep_readl(ep, STA)
9747 + & USBA_BF(BUSY_BANKS, -1L))))) {
9748 + ret = -EAGAIN;
9749 + } else {
9750 + if (value)
9751 + usba_ep_writel(ep, SET_STA, USBA_BIT(FORCE_STALL));
9752 + else
9753 + usba_ep_writel(ep, CLR_STA, (USBA_BIT(FORCE_STALL)
9754 + | USBA_BIT(TOGGLE_SEQ)));
9755 + usba_ep_readl(ep, STA);
9756 + }
9757 +
9758 + spin_unlock_irqrestore(&udc->lock, flags);
9759 +
9760 + return ret;
9761 +}
9762 +
9763 +static int usba_ep_fifo_status(struct usb_ep *_ep)
9764 +{
9765 + struct usba_ep *ep = to_usba_ep(_ep);
9766 +
9767 + return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
9768 +}
9769 +
9770 +static void usba_ep_fifo_flush(struct usb_ep *_ep)
9771 +{
9772 + struct usba_ep *ep = to_usba_ep(_ep);
9773 + struct usba_udc *udc = ep->udc;
9774 +
9775 + usba_writel(udc, EPT_RST, 1 << ep->index);
9776 +}
9777 +
9778 +struct usb_ep_ops usba_ep_ops = {
9779 + .enable = usba_ep_enable,
9780 + .disable = usba_ep_disable,
9781 + .alloc_request = usba_ep_alloc_request,
9782 + .free_request = usba_ep_free_request,
9783 + .alloc_buffer = usba_ep_alloc_buffer,
9784 + .free_buffer = usba_ep_free_buffer,
9785 + .queue = usba_ep_queue,
9786 + .dequeue = usba_ep_dequeue,
9787 + .set_halt = usba_ep_set_halt,
9788 + .fifo_status = usba_ep_fifo_status,
9789 + .fifo_flush = usba_ep_fifo_flush,
9790 +};
9791 +
9792 +static int usba_udc_get_frame(struct usb_gadget *gadget)
9793 +{
9794 + struct usba_udc *udc = to_usba_udc(gadget);
9795 +
9796 + return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
9797 +}
9798 +
9799 +struct usb_gadget_ops usba_udc_ops = {
9800 + .get_frame = usba_udc_get_frame,
9801 +};
9802 +
9803 +#define EP(nam, type, idx, dma, isoc) \
9804 +{ \
9805 + .ep = { \
9806 + .ops = &usba_ep_ops, \
9807 + .name = nam, \
9808 + .maxpacket = type##_FIFO_SIZE, \
9809 + }, \
9810 + .udc = &the_udc, \
9811 + .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
9812 + .fifo_size = type##_FIFO_SIZE, \
9813 + .nr_banks = type##_NR_BANKS, \
9814 + .index = idx, \
9815 + .can_dma = dma, \
9816 + .can_isoc = isoc, \
9817 +}
9818 +
9819 +static struct usba_ep usba_ep[] = {
9820 + EP("ep0", EP0, 0, 0, 0),
9821 + EP("ep1in-bulk", BULK, 1, 1, 0),
9822 + EP("ep2out-bulk", BULK, 2, 1, 0),
9823 + EP("ep3in-iso", ISO, 3, 1, 1),
9824 + EP("ep4out-iso", ISO, 4, 1, 1),
9825 + EP("ep5in-int", INT, 5, 1, 0),
9826 + EP("ep6out-int", INT, 6, 1, 0),
9827 +};
9828 +#undef EP
9829 +
9830 +static struct usb_endpoint_descriptor usba_ep0_desc = {
9831 + .bLength = USB_DT_ENDPOINT_SIZE,
9832 + .bDescriptorType = USB_DT_ENDPOINT,
9833 + .bEndpointAddress = 0,
9834 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
9835 + .wMaxPacketSize = __constant_cpu_to_le16(64),
9836 + /* FIXME: I have no idea what to put here */
9837 + .bInterval = 1,
9838 +};
9839 +
9840 +static void nop_release(struct device *dev)
9841 +{
9842 +
9843 +}
9844 +
9845 +static struct usba_udc the_udc = {
9846 + .gadget = {
9847 + .ops = &usba_udc_ops,
9848 + .ep0 = &usba_ep[0].ep,
9849 + .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
9850 + .is_dualspeed = 1,
9851 + .name = "atmel_usba_udc",
9852 + .dev = {
9853 + .bus_id = "gadget",
9854 + .release = nop_release,
9855 + },
9856 + },
9857 +
9858 + .lock = SPIN_LOCK_UNLOCKED,
9859 +};
9860 +
9861 +/*
9862 + * Called with interrupts disabled and udc->lock held.
9863 + */
9864 +static void reset_all_endpoints(struct usba_udc *udc)
9865 +{
9866 + struct usba_ep *ep;
9867 + struct usba_request *req, *tmp_req;
9868 +
9869 + usba_writel(udc, EPT_RST, ~0UL);
9870 +
9871 + ep = to_usba_ep(udc->gadget.ep0);
9872 + list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
9873 + list_del_init(&req->queue);
9874 + request_complete(ep, req, -ECONNRESET);
9875 + }
9876 +
9877 + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
9878 + if (ep->desc)
9879 + usba_ep_disable(&ep->ep);
9880 + }
9881 +}
9882 +
9883 +static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
9884 +{
9885 + struct usba_ep *ep;
9886 +
9887 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
9888 + return to_usba_ep(udc->gadget.ep0);
9889 +
9890 + list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
9891 + u8 bEndpointAddress;
9892 +
9893 + if (!ep->desc)
9894 + continue;
9895 + bEndpointAddress = ep->desc->bEndpointAddress;
9896 + if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
9897 + continue;
9898 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
9899 + == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
9900 + return ep;
9901 + }
9902 +
9903 + return NULL;
9904 +}
9905 +
9906 +/* Called with interrupts disabled and udc->lock held */
9907 +static inline void set_protocol_stall(struct usba_udc *udc,
9908 + struct usba_ep *ep)
9909 +{
9910 + usba_ep_writel(ep, SET_STA, USBA_BIT(FORCE_STALL));
9911 + ep->state = WAIT_FOR_SETUP;
9912 +}
9913 +
9914 +static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
9915 +{
9916 + if (usba_ep_readl(ep, STA) & USBA_BIT(FORCE_STALL))
9917 + return 1;
9918 + return 0;
9919 +}
9920 +
9921 +static inline void set_address(struct usba_udc *udc, unsigned int addr)
9922 +{
9923 + u32 regval;
9924 +
9925 + DBG(DBG_BUS, "setting address %u...\n", addr);
9926 + regval = usba_readl(udc, CTRL);
9927 + regval = USBA_BFINS(DEV_ADDR, addr, regval);
9928 + usba_writel(udc, CTRL, regval);
9929 +}
9930 +
9931 +static int do_test_mode(struct usba_udc *udc)
9932 +{
9933 + static const char test_packet_buffer[] = {
9934 + /* JKJKJKJK * 9 */
9935 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9936 + /* JJKKJJKK * 8 */
9937 + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
9938 + /* JJKKJJKK * 8 */
9939 + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
9940 + /* JJJJJJJKKKKKKK * 8 */
9941 + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
9942 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
9943 + /* JJJJJJJK * 8 */
9944 + 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
9945 + /* {JKKKKKKK * 10}, JK */
9946 + 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
9947 + };
9948 + struct device *dev = &udc->pdev->dev;
9949 + struct usba_ep *ep;
9950 + int test_mode;
9951 +
9952 + test_mode = udc->test_mode;
9953 +
9954 + /* Start from a clean slate */
9955 + reset_all_endpoints(udc);
9956 +
9957 + switch (test_mode) {
9958 + case 0x0100:
9959 + /* Test_J */
9960 + usba_writel(udc, TST, USBA_BIT(TST_J_MODE));
9961 + dev_info(dev, "Entering Test_J mode...\n");
9962 + break;
9963 + case 0x0200:
9964 + /* Test_K */
9965 + usba_writel(udc, TST, USBA_BIT(TST_K_MODE));
9966 + dev_info(dev, "Entering Test_K mode...\n");
9967 + break;
9968 + case 0x0300:
9969 + /*
9970 + * Test_SE0_NAK: Force high-speed mode and set up ep0
9971 + * for Bulk IN transfers
9972 + */
9973 + ep = &usba_ep[0];
9974 + usba_writel(udc, TST,
9975 + USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
9976 + usba_ep_writel(ep, CFG,
9977 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
9978 + | USBA_BIT(EPT_DIR)
9979 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
9980 + | USBA_BF(BK_NUMBER, 1));
9981 + if (!(usba_ep_readl(ep, CFG) & USBA_BIT(EPT_MAPPED))) {
9982 + set_protocol_stall(udc, ep);
9983 + dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
9984 + } else {
9985 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
9986 + dev_info(dev, "Entering Test_SE0_NAK mode...\n");
9987 + }
9988 + break;
9989 + case 0x0400:
9990 + /* Test_Packet */
9991 + ep = &usba_ep[0];
9992 + usba_ep_writel(ep, CFG,
9993 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
9994 + | USBA_BIT(EPT_DIR)
9995 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
9996 + | USBA_BF(BK_NUMBER, 1));
9997 + if (!(usba_ep_readl(ep, CFG) & USBA_BIT(EPT_MAPPED))) {
9998 + set_protocol_stall(udc, ep);
9999 + dev_err(dev, "Test_Packet: ep0 not mapped\n");
10000 + } else {
10001 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
10002 + usba_writel(udc, TST, USBA_BIT(TST_PKT_MODE));
10003 + copy_to_fifo(ep->fifo, test_packet_buffer,
10004 + sizeof(test_packet_buffer));
10005 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
10006 + dev_info(dev, "Entering Test_Packet mode...\n");
10007 + }
10008 + break;
10009 + default:
10010 + dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
10011 + return -EINVAL;
10012 + }
10013 +
10014 + return 0;
10015 +}
10016 +
10017 +/* Avoid overly long expressions */
10018 +static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
10019 +{
10020 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
10021 + return true;
10022 + return false;
10023 +}
10024 +
10025 +static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
10026 +{
10027 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
10028 + return true;
10029 + return false;
10030 +}
10031 +
10032 +static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
10033 +{
10034 + if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
10035 + return true;
10036 + return false;
10037 +}
10038 +
10039 +static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
10040 + struct usb_ctrlrequest *crq)
10041 +{
10042 + switch (crq->bRequest) {
10043 + case USB_REQ_GET_STATUS: {
10044 + u16 status;
10045 +
10046 + if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
10047 + /* Self-powered, no remote wakeup */
10048 + status = __constant_cpu_to_le16(1 << 0);
10049 + } else if (crq->bRequestType
10050 + == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
10051 + status = __constant_cpu_to_le16(0);
10052 + } else if (crq->bRequestType
10053 + == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
10054 + struct usba_ep *target;
10055 +
10056 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
10057 + if (!target)
10058 + goto stall;
10059 +
10060 + status = 0;
10061 + if (is_stalled(udc, target))
10062 + status |= __constant_cpu_to_le16(1);
10063 + } else {
10064 + goto delegate;
10065 + }
10066 +
10067 + /* Write directly to the FIFO. No queueing is done. */
10068 + if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
10069 + goto stall;
10070 + ep->state = DATA_STAGE_IN;
10071 + __raw_writew(status, ep->fifo);
10072 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
10073 + break;
10074 + }
10075 +
10076 + case USB_REQ_CLEAR_FEATURE: {
10077 + if (crq->bRequestType == USB_RECIP_DEVICE) {
10078 + if (feature_is_dev_remote_wakeup(crq)) {
10079 + /* TODO: Handle REMOTE_WAKEUP */
10080 + } else {
10081 + /* Can't CLEAR_FEATURE TEST_MODE */
10082 + goto stall;
10083 + }
10084 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
10085 + struct usba_ep *target;
10086 +
10087 + if (!feature_is_ep_halt(crq)
10088 + || crq->wLength != __constant_cpu_to_le16(0))
10089 + goto stall;
10090 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
10091 + if (!target)
10092 + goto stall;
10093 +
10094 + usba_ep_writel(target, CLR_STA,
10095 + (USBA_BIT(FORCE_STALL)
10096 + | USBA_BIT(TOGGLE_SEQ)));
10097 + } else {
10098 + goto delegate;
10099 + }
10100 +
10101 + send_status(udc, ep);
10102 + break;
10103 + }
10104 +
10105 + case USB_REQ_SET_FEATURE: {
10106 + if (crq->bRequestType == USB_RECIP_DEVICE) {
10107 + if (feature_is_dev_test_mode(crq)) {
10108 + send_status(udc, ep);
10109 + ep->state = STATUS_STAGE_TEST;
10110 + udc->test_mode = le16_to_cpu(crq->wIndex);
10111 + return 0;
10112 + } else if (feature_is_dev_remote_wakeup(crq)) {
10113 + /* TODO: Handle REMOTE_WAKEUP */
10114 + } else {
10115 + goto stall;
10116 + }
10117 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
10118 + struct usba_ep *target;
10119 +
10120 + if (!feature_is_ep_halt(crq)
10121 + || crq->wLength != __constant_cpu_to_le16(0))
10122 + goto stall;
10123 +
10124 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
10125 + if (!target)
10126 + goto stall;
10127 +
10128 + usba_ep_writel(target, SET_STA, USBA_BIT(FORCE_STALL));
10129 + } else
10130 + goto delegate;
10131 +
10132 + send_status(udc, ep);
10133 + break;
10134 + }
10135 +
10136 + case USB_REQ_SET_ADDRESS:
10137 + if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
10138 + goto delegate;
10139 +
10140 + set_address(udc, le16_to_cpu(crq->wValue));
10141 + send_status(udc, ep);
10142 + ep->state = STATUS_STAGE_ADDR;
10143 + break;
10144 +
10145 + default:
10146 +delegate:
10147 + return udc->driver->setup(&udc->gadget, crq);
10148 + }
10149 +
10150 + return 0;
10151 +
10152 +stall:
10153 + printk(KERN_ERR
10154 + "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
10155 + "halting endpoint...\n",
10156 + ep_name(ep), crq->bRequestType, crq->bRequest,
10157 + le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
10158 + le16_to_cpu(crq->wLength));
10159 + set_protocol_stall(udc, ep);
10160 + return -1;
10161 +}
10162 +
10163 +static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
10164 +{
10165 + struct usba_request *req;
10166 + u32 epstatus;
10167 + u32 epctrl;
10168 +
10169 +restart:
10170 + epstatus = usba_ep_readl(ep, STA);
10171 + epctrl = usba_ep_readl(ep, CTL);
10172 +
10173 + DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
10174 + ep_name(ep), ep->state, epstatus, epctrl);
10175 +
10176 + req = NULL;
10177 + if (!list_empty(&ep->queue))
10178 + req = list_entry(ep->queue.next,
10179 + struct usba_request, queue);
10180 +
10181 + if ((epctrl & USBA_BIT(TX_PK_RDY))
10182 + && !(epstatus & USBA_BIT(TX_PK_RDY))) {
10183 + if (req->submitted)
10184 + next_fifo_transaction(ep, req);
10185 + else
10186 + submit_request(ep, req);
10187 +
10188 + if (req->last_transaction) {
10189 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
10190 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
10191 + }
10192 + goto restart;
10193 + }
10194 + if ((epstatus & epctrl) & USBA_BIT(TX_COMPLETE)) {
10195 + usba_ep_writel(ep, CLR_STA, USBA_BIT(TX_COMPLETE));
10196 +
10197 + switch (ep->state) {
10198 + case DATA_STAGE_IN:
10199 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(RX_BK_RDY));
10200 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
10201 + ep->state = STATUS_STAGE_OUT;
10202 + break;
10203 + case STATUS_STAGE_ADDR:
10204 + /* Activate our new address */
10205 + usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
10206 + | USBA_BIT(FADDR_EN)));
10207 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
10208 + ep->state = WAIT_FOR_SETUP;
10209 + break;
10210 + case STATUS_STAGE_IN:
10211 + if (req) {
10212 + list_del_init(&req->queue);
10213 + request_complete(ep, req, 0);
10214 + submit_next_request(ep);
10215 + }
10216 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
10217 + ep->state = WAIT_FOR_SETUP;
10218 + break;
10219 + case STATUS_STAGE_TEST:
10220 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
10221 + ep->state = WAIT_FOR_SETUP;
10222 + if (do_test_mode(udc))
10223 + set_protocol_stall(udc, ep);
10224 + break;
10225 + default:
10226 + printk(KERN_ERR
10227 + "udc: %s: TXCOMP: Invalid endpoint state %d, "
10228 + "halting endpoint...\n",
10229 + ep_name(ep), ep->state);
10230 + set_protocol_stall(udc, ep);
10231 + break;
10232 + }
10233 +
10234 + goto restart;
10235 + }
10236 + if ((epstatus & epctrl) & USBA_BIT(RX_BK_RDY)) {
10237 + switch (ep->state) {
10238 + case STATUS_STAGE_OUT:
10239 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
10240 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
10241 +
10242 + if (req) {
10243 + list_del_init(&req->queue);
10244 + request_complete(ep, req, 0);
10245 + }
10246 + ep->state = WAIT_FOR_SETUP;
10247 + break;
10248 +
10249 + case DATA_STAGE_OUT:
10250 + receive_data(ep);
10251 + break;
10252 +
10253 + default:
10254 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
10255 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
10256 + printk(KERN_ERR
10257 + "udc: %s: RXRDY: Invalid endpoint state %d, "
10258 + "halting endpoint...\n",
10259 + ep_name(ep), ep->state);
10260 + set_protocol_stall(udc, ep);
10261 + break;
10262 + }
10263 +
10264 + goto restart;
10265 + }
10266 + if (epstatus & USBA_BIT(RX_SETUP)) {
10267 + union {
10268 + struct usb_ctrlrequest crq;
10269 + unsigned long data[2];
10270 + } crq;
10271 + unsigned int pkt_len;
10272 + int ret;
10273 +
10274 + if (ep->state != WAIT_FOR_SETUP) {
10275 + /*
10276 + * Didn't expect a SETUP packet at this
10277 + * point. Clean up any pending requests (which
10278 + * may be successful).
10279 + */
10280 + int status = -EPROTO;
10281 +
10282 + /*
10283 + * RXRDY and TXCOMP are dropped when SETUP
10284 + * packets arrive. Just pretend we received
10285 + * the status packet.
10286 + */
10287 + if (ep->state == STATUS_STAGE_OUT
10288 + || ep->state == STATUS_STAGE_IN) {
10289 + usba_ep_writel(ep, CTL_DIS,
10290 + USBA_BIT(RX_BK_RDY));
10291 + status = 0;
10292 + }
10293 +
10294 + if (req) {
10295 + list_del_init(&req->queue);
10296 + request_complete(ep, req, status);
10297 + }
10298 + }
10299 +
10300 + pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
10301 + DBG(DBG_HW, "Packet length: %u\n", pkt_len);
10302 + if (pkt_len != sizeof(crq)) {
10303 + printk(KERN_WARNING
10304 + "udc: Invalid packet length %u (expected %lu)\n",
10305 + pkt_len, sizeof(crq));
10306 + set_protocol_stall(udc, ep);
10307 + return;
10308 + }
10309 +
10310 + DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
10311 + copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
10312 +
10313 + /* Free up one bank in the FIFO so that we can
10314 + * generate or receive a reply right away. */
10315 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_SETUP));
10316 +
10317 + /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
10318 + ep->state, crq.crq.bRequestType,
10319 + crq.crq.bRequest); */
10320 +
10321 + if (crq.crq.bRequestType & USB_DIR_IN) {
10322 + /*
10323 + * The USB 2.0 spec states that "if wLength is
10324 + * zero, there is no data transfer phase."
10325 + * However, testusb #14 seems to actually
10326 + * expect a data phase even if wLength = 0...
10327 + */
10328 + ep->state = DATA_STAGE_IN;
10329 + } else {
10330 + if (crq.crq.wLength != __constant_cpu_to_le16(0))
10331 + ep->state = DATA_STAGE_OUT;
10332 + else
10333 + ep->state = STATUS_STAGE_IN;
10334 + }
10335 +
10336 + ret = -1;
10337 + if (ep->index == 0)
10338 + ret = handle_ep0_setup(udc, ep, &crq.crq);
10339 + else
10340 + ret = udc->driver->setup(&udc->gadget, &crq.crq);
10341 +
10342 + DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
10343 + crq.crq.bRequestType, crq.crq.bRequest,
10344 + le16_to_cpu(crq.crq.wLength), ep->state, ret);
10345 +
10346 + if (ret < 0) {
10347 + /* Let the host know that we failed */
10348 + set_protocol_stall(udc, ep);
10349 + }
10350 + }
10351 +}
10352 +
10353 +static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
10354 +{
10355 + struct usba_request *req;
10356 + u32 epstatus;
10357 + u32 epctrl;
10358 +
10359 + epstatus = usba_ep_readl(ep, STA);
10360 + epctrl = usba_ep_readl(ep, CTL);
10361 +
10362 + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
10363 + ep_name(ep), epstatus);
10364 +
10365 + while ((epctrl & USBA_BIT(TX_PK_RDY))
10366 + && !(epstatus & USBA_BIT(TX_PK_RDY))) {
10367 + DBG(DBG_BUS, "%s: TX PK ready\n", ep_name(ep));
10368 +
10369 + if (list_empty(&ep->queue)) {
10370 + dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
10371 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
10372 + return;
10373 + }
10374 +
10375 + req = list_entry(ep->queue.next, struct usba_request, queue);
10376 +
10377 + if (req->using_dma) {
10378 + /* Send a zero-length packet */
10379 + usba_ep_writel(ep, SET_STA,
10380 + USBA_BIT(TX_PK_RDY));
10381 + usba_ep_writel(ep, CTL_DIS,
10382 + USBA_BIT(TX_PK_RDY));
10383 + list_del_init(&req->queue);
10384 + submit_next_request(ep);
10385 + request_complete(ep, req, 0);
10386 + } else {
10387 + if (req->submitted)
10388 + next_fifo_transaction(ep, req);
10389 + else
10390 + submit_request(ep, req);
10391 +
10392 + if (req->last_transaction) {
10393 + list_del_init(&req->queue);
10394 + submit_next_request(ep);
10395 + request_complete(ep, req, 0);
10396 + }
10397 + }
10398 +
10399 + epstatus = usba_ep_readl(ep, STA);
10400 + epctrl = usba_ep_readl(ep, CTL);
10401 + }
10402 + if ((epstatus & epctrl) & USBA_BIT(RX_BK_RDY)) {
10403 + DBG(DBG_BUS, "%s: RX data ready\n", ep_name(ep));
10404 + receive_data(ep);
10405 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
10406 + }
10407 +}
10408 +
10409 +static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
10410 +{
10411 + struct usba_request *req;
10412 + u32 status, control, pending;
10413 +
10414 + status = usba_dma_readl(ep, STATUS);
10415 + control = usba_dma_readl(ep, CONTROL);
10416 +#ifdef CONFIG_DEBUG_FS
10417 + ep->last_dma_status = status;
10418 +#endif
10419 + pending = status & control;
10420 + DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n",
10421 + status, control);
10422 +
10423 + if (status & USBA_BIT(DMA_CH_EN)) {
10424 + dev_err(&udc->pdev->dev,
10425 + "DMA_CH_EN is set after transfer is finished!\n");
10426 + dev_err(&udc->pdev->dev,
10427 + "status=%#08x, pending=%#08x, control=%#08x\n",
10428 + status, pending, control);
10429 +
10430 + /*
10431 + * try to pretend nothing happened. We might have to
10432 + * do something here...
10433 + */
10434 + }
10435 +
10436 + if (list_empty(&ep->queue))
10437 + /* Might happen if a reset comes along at the right moment */
10438 + return;
10439 +
10440 + if (pending & (USBA_BIT(DMA_END_TR_ST) | USBA_BIT(DMA_END_BUF_ST))) {
10441 + req = list_entry(ep->queue.next, struct usba_request, queue);
10442 + usba_update_req(ep, req, status);
10443 +
10444 + list_del_init(&req->queue);
10445 + submit_next_request(ep);
10446 + request_complete(ep, req, 0);
10447 + }
10448 +}
10449 +
10450 +static irqreturn_t usba_udc_irq(int irq, void *devid)
10451 +{
10452 + struct usba_udc *udc = devid;
10453 + u32 status;
10454 + u32 dma_status;
10455 + u32 ep_status;
10456 +
10457 + spin_lock(&udc->lock);
10458 +
10459 + status = usba_readl(udc, INT_STA);
10460 + DBG(DBG_INT, "irq, status=%#08x\n", status);
10461 +
10462 + if (status & USBA_BIT(DET_SUSPEND)) {
10463 + usba_writel(udc, INT_CLR, USBA_BIT(DET_SUSPEND));
10464 + DBG(DBG_BUS, "Suspend detected\n");
10465 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
10466 + && udc->driver && udc->driver->suspend)
10467 + udc->driver->suspend(&udc->gadget);
10468 + }
10469 +
10470 + if (status & USBA_BIT(WAKE_UP)) {
10471 + usba_writel(udc, INT_CLR, USBA_BIT(WAKE_UP));
10472 + DBG(DBG_BUS, "Wake Up CPU detected\n");
10473 + }
10474 +
10475 + if (status & USBA_BIT(END_OF_RESUME)) {
10476 + usba_writel(udc, INT_CLR, USBA_BIT(END_OF_RESUME));
10477 + DBG(DBG_BUS, "Resume detected\n");
10478 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
10479 + && udc->driver && udc->driver->resume)
10480 + udc->driver->resume(&udc->gadget);
10481 + }
10482 +
10483 + dma_status = USBA_BFEXT(DMA_INT, status);
10484 + if (dma_status) {
10485 + int i;
10486 +
10487 + for (i = 1; i < USBA_NR_ENDPOINTS; i++)
10488 + if (dma_status & (1 << i))
10489 + usba_dma_irq(udc, &usba_ep[i]);
10490 + }
10491 +
10492 + ep_status = USBA_BFEXT(EPT_INT, status);
10493 + if (ep_status) {
10494 + int i;
10495 +
10496 + for (i = 0; i < USBA_NR_ENDPOINTS; i++)
10497 + if (ep_status & (1 << i)) {
10498 + if (ep_is_control(&usba_ep[i]))
10499 + usba_control_irq(udc, &usba_ep[i]);
10500 + else
10501 + usba_ep_irq(udc, &usba_ep[i]);
10502 + }
10503 + }
10504 +
10505 + if (status & USBA_BIT(END_OF_RESET)) {
10506 + struct usba_ep *ep0;
10507 +
10508 + usba_writel(udc, INT_CLR, USBA_BIT(END_OF_RESET));
10509 + reset_all_endpoints(udc);
10510 +
10511 + if (status & USBA_BIT(HIGH_SPEED)) {
10512 + DBG(DBG_BUS, "High-speed bus reset detected\n");
10513 + udc->gadget.speed = USB_SPEED_HIGH;
10514 + } else {
10515 + DBG(DBG_BUS, "Full-speed bus reset detected\n");
10516 + udc->gadget.speed = USB_SPEED_FULL;
10517 + }
10518 +
10519 + ep0 = &usba_ep[0];
10520 + ep0->desc = &usba_ep0_desc;
10521 + ep0->state = WAIT_FOR_SETUP;
10522 + usba_ep_writel(ep0, CFG,
10523 + (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
10524 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
10525 + | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
10526 + usba_ep_writel(ep0, CTL_ENB,
10527 + USBA_BIT(EPT_ENABLE) | USBA_BIT(RX_SETUP));
10528 + usba_writel(udc, INT_ENB, (usba_readl(udc, INT_ENB)
10529 + | USBA_BF(EPT_INT, 1)
10530 + | USBA_BIT(DET_SUSPEND)
10531 + | USBA_BIT(END_OF_RESUME)));
10532 +
10533 + if (!(usba_ep_readl(ep0, CFG) & USBA_BIT(EPT_MAPPED)))
10534 + dev_warn(&udc->pdev->dev,
10535 + "WARNING: EP0 configuration is invalid!\n");
10536 + }
10537 +
10538 + spin_unlock(&udc->lock);
10539 +
10540 + return IRQ_HANDLED;
10541 +}
10542 +
10543 +static irqreturn_t usba_vbus_irq(int irq, void *devid)
10544 +{
10545 + struct usba_udc *udc = devid;
10546 + int vbus;
10547 +
10548 + /* debounce */
10549 + udelay(10);
10550 +
10551 + spin_lock(&udc->lock);
10552 + vbus = gpio_get_value(udc->vbus_pin);
10553 + if (vbus != udc->vbus_prev) {
10554 + if (vbus) {
10555 + usba_writel(udc, CTRL, USBA_BIT(EN_USBA));
10556 + usba_writel(udc, INT_ENB, USBA_BIT(END_OF_RESET));
10557 + } else {
10558 + udc->gadget.speed = USB_SPEED_UNKNOWN;
10559 + reset_all_endpoints(udc);
10560 + usba_writel(udc, CTRL, 0);
10561 + if (udc->driver)
10562 + udc->driver->disconnect(&udc->gadget);
10563 + }
10564 + udc->vbus_prev = vbus;
10565 + }
10566 + spin_unlock(&udc->lock);
10567 +
10568 + return IRQ_HANDLED;
10569 +}
10570 +
10571 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
10572 +{
10573 + struct usba_udc *udc = &the_udc;
10574 + unsigned long flags;
10575 + int ret;
10576 +
10577 + if (!udc->pdev)
10578 + return -ENODEV;
10579 +
10580 + spin_lock_irqsave(&udc->lock, flags);
10581 + if (udc->driver) {
10582 + spin_unlock_irqrestore(&udc->lock, flags);
10583 + return -EBUSY;
10584 + }
10585 +
10586 + udc->driver = driver;
10587 + udc->gadget.dev.driver = &driver->driver;
10588 + spin_unlock_irqrestore(&udc->lock, flags);
10589 +
10590 + clk_enable(udc->pclk);
10591 + clk_enable(udc->hclk);
10592 +
10593 + ret = driver->bind(&udc->gadget);
10594 + if (ret) {
10595 + DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
10596 + driver->driver.name, ret);
10597 + goto err_driver_bind;
10598 + }
10599 +
10600 + DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
10601 +
10602 + udc->vbus_prev = 0;
10603 + if (udc->vbus_pin != -1) {
10604 + ret = request_irq(gpio_to_irq(udc->vbus_pin),
10605 + usba_vbus_irq, 0, "atmel_usba_udc", udc);
10606 + if (ret) {
10607 + gpio_free(udc->vbus_pin);
10608 + udc->vbus_pin = -1;
10609 + dev_warn(&udc->pdev->dev,
10610 + "failed to request vbus irq; "
10611 + "assuming always on\n");
10612 + }
10613 + }
10614 +
10615 + /* If Vbus is present, enable the controller and wait for reset */
10616 + spin_lock_irqsave(&udc->lock, flags);
10617 + if (vbus_is_present(udc) && udc->vbus_prev == 0) {
10618 + usba_writel(udc, CTRL, USBA_BIT(EN_USBA));
10619 + usba_writel(udc, INT_ENB, USBA_BIT(END_OF_RESET));
10620 + }
10621 + spin_unlock_irqrestore(&udc->lock, flags);
10622 +
10623 + return 0;
10624 +
10625 +err_driver_bind:
10626 + udc->driver = NULL;
10627 + udc->gadget.dev.driver = NULL;
10628 + return ret;
10629 +}
10630 +EXPORT_SYMBOL(usb_gadget_register_driver);
10631 +
10632 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
10633 +{
10634 + struct usba_udc *udc = &the_udc;
10635 + unsigned long flags;
10636 +
10637 + if (!udc->pdev)
10638 + return -ENODEV;
10639 + if (driver != udc->driver)
10640 + return -EINVAL;
10641 +
10642 + if (udc->vbus_pin != -1)
10643 + free_irq(gpio_to_irq(udc->vbus_pin), udc);
10644 +
10645 + spin_lock_irqsave(&udc->lock, flags);
10646 + udc->gadget.speed = USB_SPEED_UNKNOWN;
10647 + reset_all_endpoints(udc);
10648 + spin_unlock_irqrestore(&udc->lock, flags);
10649 +
10650 + /* This will also disable the DP pullup */
10651 + usba_writel(udc, CTRL, 0);
10652 +
10653 + driver->unbind(&udc->gadget);
10654 + udc->gadget.dev.driver = NULL;
10655 + udc->driver = NULL;
10656 +
10657 + clk_disable(udc->hclk);
10658 + clk_disable(udc->pclk);
10659 +
10660 + DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
10661 +
10662 + return 0;
10663 +}
10664 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
10665 +
10666 +static int __devinit usba_udc_probe(struct platform_device *pdev)
10667 +{
10668 + struct usba_platform_data *pdata = pdev->dev.platform_data;
10669 + struct resource *regs, *fifo;
10670 + struct clk *pclk, *hclk;
10671 + struct usba_udc *udc = &the_udc;
10672 + int irq, ret, i;
10673 +
10674 + regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
10675 + fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
10676 + if (!regs || !fifo)
10677 + return -ENXIO;
10678 +
10679 + irq = platform_get_irq(pdev, 0);
10680 + if (irq < 0)
10681 + return irq;
10682 +
10683 + pclk = clk_get(&pdev->dev, "pclk");
10684 + if (IS_ERR(pclk))
10685 + return PTR_ERR(pclk);
10686 + hclk = clk_get(&pdev->dev, "hclk");
10687 + if (IS_ERR(hclk)) {
10688 + ret = PTR_ERR(hclk);
10689 + goto err_get_hclk;
10690 + }
10691 +
10692 + udc->pdev = pdev;
10693 + udc->pclk = pclk;
10694 + udc->hclk = hclk;
10695 + udc->vbus_pin = -1;
10696 +
10697 + ret = -ENOMEM;
10698 + udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
10699 + if (!udc->regs) {
10700 + dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
10701 + goto err_map_regs;
10702 + }
10703 + dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
10704 + (unsigned long)regs->start, udc->regs);
10705 + udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
10706 + if (!udc->fifo) {
10707 + dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
10708 + goto err_map_fifo;
10709 + }
10710 + dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
10711 + (unsigned long)fifo->start, udc->fifo);
10712 +
10713 + device_initialize(&udc->gadget.dev);
10714 + udc->gadget.dev.parent = &pdev->dev;
10715 + udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
10716 +
10717 + platform_set_drvdata(pdev, udc);
10718 +
10719 + /* Make sure we start from a clean slate */
10720 + clk_enable(pclk);
10721 + usba_writel(udc, CTRL, 0);
10722 + clk_disable(pclk);
10723 +
10724 + INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
10725 + usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
10726 + usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
10727 + usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
10728 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
10729 + struct usba_ep *ep = &usba_ep[i];
10730 +
10731 + ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
10732 + ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
10733 + ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
10734 +
10735 + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
10736 + }
10737 +
10738 + ret = request_irq(irq, usba_udc_irq, IRQF_SAMPLE_RANDOM,
10739 + "atmel_usba_udc", udc);
10740 + if (ret) {
10741 + dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
10742 + irq, ret);
10743 + goto err_request_irq;
10744 + }
10745 + udc->irq = irq;
10746 +
10747 + ret = device_add(&udc->gadget.dev);
10748 + if (ret) {
10749 + dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
10750 + goto err_device_add;
10751 + }
10752 +
10753 + if (pdata && pdata->vbus_pin != GPIO_PIN_NONE)
10754 + if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc"))
10755 + udc->vbus_pin = pdata->vbus_pin;
10756 +
10757 + usba_init_debugfs(udc);
10758 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
10759 + usba_ep_init_debugfs(udc, &usba_ep[i]);
10760 +
10761 + return 0;
10762 +
10763 +err_device_add:
10764 + free_irq(irq, udc);
10765 +err_request_irq:
10766 + iounmap(udc->fifo);
10767 +err_map_fifo:
10768 + iounmap(udc->regs);
10769 +err_map_regs:
10770 + clk_put(hclk);
10771 +err_get_hclk:
10772 + clk_put(pclk);
10773 +
10774 + platform_set_drvdata(pdev, NULL);
10775 +
10776 + return ret;
10777 +}
10778 +
10779 +static int __devexit usba_udc_remove(struct platform_device *pdev)
10780 +{
10781 + struct usba_udc *udc;
10782 + int i;
10783 +
10784 + udc = platform_get_drvdata(pdev);
10785 +
10786 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
10787 + usba_ep_cleanup_debugfs(&usba_ep[i]);
10788 + usba_cleanup_debugfs(udc);
10789 +
10790 + if (udc->vbus_pin != -1)
10791 + gpio_free(udc->vbus_pin);
10792 +
10793 + free_irq(udc->irq, udc);
10794 + iounmap(udc->fifo);
10795 + iounmap(udc->regs);
10796 + clk_put(udc->hclk);
10797 + clk_put(udc->pclk);
10798 +
10799 + device_unregister(&udc->gadget.dev);
10800 +
10801 + return 0;
10802 +}
10803 +
10804 +static struct platform_driver udc_driver = {
10805 + .probe = usba_udc_probe,
10806 + .remove = __devexit_p(usba_udc_remove),
10807 + .driver = {
10808 + .name = "atmel_usba_udc",
10809 + },
10810 +};
10811 +
10812 +static int __init udc_init(void)
10813 +{
10814 + return platform_driver_register(&udc_driver);
10815 +}
10816 +module_init(udc_init);
10817 +
10818 +static void __exit udc_exit(void)
10819 +{
10820 + platform_driver_unregister(&udc_driver);
10821 +}
10822 +module_exit(udc_exit);
10823 +
10824 +MODULE_DESCRIPTION("Atmel USBA UDC driver");
10825 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
10826 +MODULE_LICENSE("GPL");
10827 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.h linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.h
10828 --- linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.h 1970-01-01 01:00:00.000000000 +0100
10829 +++ linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.h 2007-07-12 14:00:19.000000000 +0200
10830 @@ -0,0 +1,402 @@
10831 +/*
10832 + * Driver for the Atmel USBA high speed USB device controller
10833 + *
10834 + * Copyright (C) 2005-2007 Atmel Corporation
10835 + *
10836 + * This program is free software; you can redistribute it and/or modify
10837 + * it under the terms of the GNU General Public License version 2 as
10838 + * published by the Free Software Foundation.
10839 + */
10840 +#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
10841 +#define __LINUX_USB_GADGET_USBA_UDC_H__
10842 +
10843 +/* USB register offsets */
10844 +#define USBA_CTRL 0x0000
10845 +#define USBA_FNUM 0x0004
10846 +#define USBA_INT_ENB 0x0010
10847 +#define USBA_INT_STA 0x0014
10848 +#define USBA_INT_CLR 0x0018
10849 +#define USBA_EPT_RST 0x001c
10850 +#define USBA_TST_SOF_CNT 0x00d0
10851 +#define USBA_TST_CNT_A 0x00d4
10852 +#define USBA_TST_CNT_B 0x00d8
10853 +#define USBA_TST_MODE_REG 0x00dc
10854 +#define USBA_TST 0x00e0
10855 +
10856 +/* USB endpoint register offsets */
10857 +#define USBA_EPT_CFG 0x0000
10858 +#define USBA_EPT_CTL_ENB 0x0004
10859 +#define USBA_EPT_CTL_DIS 0x0008
10860 +#define USBA_EPT_CTL 0x000c
10861 +#define USBA_EPT_SET_STA 0x0014
10862 +#define USBA_EPT_CLR_STA 0x0018
10863 +#define USBA_EPT_STA 0x001c
10864 +
10865 +/* USB DMA register offsets */
10866 +#define USBA_DMA_NXT_DSC 0x0000
10867 +#define USBA_DMA_ADDRESS 0x0004
10868 +#define USBA_DMA_CONTROL 0x0008
10869 +#define USBA_DMA_STATUS 0x000c
10870 +
10871 +/* Bitfields in CTRL */
10872 +#define USBA_DEV_ADDR_OFFSET 0
10873 +#define USBA_DEV_ADDR_SIZE 7
10874 +#define USBA_FADDR_EN_OFFSET 7
10875 +#define USBA_FADDR_EN_SIZE 1
10876 +#define USBA_EN_USBA_OFFSET 8
10877 +#define USBA_EN_USBA_SIZE 1
10878 +#define USBA_DETACH_OFFSET 9
10879 +#define USBA_DETACH_SIZE 1
10880 +#define USBA_REMOTE_WAKE_UP_OFFSET 10
10881 +#define USBA_REMOTE_WAKE_UP_SIZE 1
10882 +
10883 +/* Bitfields in FNUM */
10884 +#define USBA_MICRO_FRAME_NUM_OFFSET 0
10885 +#define USBA_MICRO_FRAME_NUM_SIZE 3
10886 +#define USBA_FRAME_NUMBER_OFFSET 3
10887 +#define USBA_FRAME_NUMBER_SIZE 11
10888 +#define USBA_FRAME_NUM_ERROR_OFFSET 31
10889 +#define USBA_FRAME_NUM_ERROR_SIZE 1
10890 +
10891 +/* Bitfields in INT_ENB/INT_STA/INT_CLR */
10892 +#define USBA_HIGH_SPEED_OFFSET 0
10893 +#define USBA_HIGH_SPEED_SIZE 1
10894 +#define USBA_DET_SUSPEND_OFFSET 1
10895 +#define USBA_DET_SUSPEND_SIZE 1
10896 +#define USBA_MICRO_SOF_OFFSET 2
10897 +#define USBA_MICRO_SOF_SIZE 1
10898 +#define USBA_SOF_OFFSET 3
10899 +#define USBA_SOF_SIZE 1
10900 +#define USBA_END_OF_RESET_OFFSET 4
10901 +#define USBA_END_OF_RESET_SIZE 1
10902 +#define USBA_WAKE_UP_OFFSET 5
10903 +#define USBA_WAKE_UP_SIZE 1
10904 +#define USBA_END_OF_RESUME_OFFSET 6
10905 +#define USBA_END_OF_RESUME_SIZE 1
10906 +#define USBA_UPSTREAM_RESUME_OFFSET 7
10907 +#define USBA_UPSTREAM_RESUME_SIZE 1
10908 +#define USBA_EPT_INT_OFFSET 8
10909 +#define USBA_EPT_INT_SIZE 16
10910 +#define USBA_DMA_INT_OFFSET 24
10911 +#define USBA_DMA_INT_SIZE 8
10912 +
10913 +/* Bitfields in EPT_RST */
10914 +#define USBA_RST_OFFSET 0
10915 +#define USBA_RST_SIZE 16
10916 +
10917 +/* Bitfields in TST_SOF_CNT */
10918 +#define USBA_SOF_CNT_MAX_OFFSET 0
10919 +#define USBA_SOF_CNT_MAX_SIZE 7
10920 +#define USBA_SOF_CNT_LOAD_OFFSET 7
10921 +#define USBA_SOF_CNT_LOAD_SIZE 1
10922 +
10923 +/* Bitfields in TST_CNT_A */
10924 +#define USBA_CNT_A_MAX_OFFSET 0
10925 +#define USBA_CNT_A_MAX_SIZE 7
10926 +#define USBA_CNT_A_LOAD_OFFSET 7
10927 +#define USBA_CNT_A_LOAD_SIZE 1
10928 +
10929 +/* Bitfields in TST_CNT_B */
10930 +#define USBA_CNT_B_MAX_OFFSET 0
10931 +#define USBA_CNT_B_MAX_SIZE 7
10932 +#define USBA_CNT_B_LOAD_OFFSET 7
10933 +#define USBA_CNT_B_LOAD_SIZE 1
10934 +
10935 +/* Bitfields in TST_MODE_REG */
10936 +#define USBA_TST_MODE_OFFSET 0
10937 +#define USBA_TST_MODE_SIZE 6
10938 +
10939 +/* Bitfields in USBA_TST */
10940 +#define USBA_SPEED_CFG_OFFSET 0
10941 +#define USBA_SPEED_CFG_SIZE 2
10942 +#define USBA_TST_J_MODE_OFFSET 2
10943 +#define USBA_TST_J_MODE_SIZE 1
10944 +#define USBA_TST_K_MODE_OFFSET 3
10945 +#define USBA_TST_K_MODE_SIZE 1
10946 +#define USBA_TST_PKT_MODE_OFFSET 4
10947 +#define USBA_TST_PKT_MODE_SIZE 1
10948 +#define USBA_OPMODE2_OFFSET 5
10949 +#define USBA_OPMODE2_SIZE 1
10950 +
10951 +/* Bitfields in EPT_CFG */
10952 +#define USBA_EPT_SIZE_OFFSET 0
10953 +#define USBA_EPT_SIZE_SIZE 3
10954 +#define USBA_EPT_DIR_OFFSET 3
10955 +#define USBA_EPT_DIR_SIZE 1
10956 +#define USBA_EPT_TYPE_OFFSET 4
10957 +#define USBA_EPT_TYPE_SIZE 2
10958 +#define USBA_BK_NUMBER_OFFSET 6
10959 +#define USBA_BK_NUMBER_SIZE 2
10960 +#define USBA_NB_TRANS_OFFSET 8
10961 +#define USBA_NB_TRANS_SIZE 2
10962 +#define USBA_EPT_MAPPED_OFFSET 31
10963 +#define USBA_EPT_MAPPED_SIZE 1
10964 +
10965 +/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
10966 +#define USBA_EPT_ENABLE_OFFSET 0
10967 +#define USBA_EPT_ENABLE_SIZE 1
10968 +#define USBA_AUTO_VALID_OFFSET 1
10969 +#define USBA_AUTO_VALID_SIZE 1
10970 +#define USBA_INTDIS_DMA_OFFSET 3
10971 +#define USBA_INTDIS_DMA_SIZE 1
10972 +#define USBA_NYET_DIS_OFFSET 4
10973 +#define USBA_NYET_DIS_SIZE 1
10974 +#define USBA_DATAX_RX_OFFSET 6
10975 +#define USBA_DATAX_RX_SIZE 1
10976 +#define USBA_MDATA_RX_OFFSET 7
10977 +#define USBA_MDATA_RX_SIZE 1
10978 +/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
10979 +#define USBA_BUSY_BANK_IE_OFFSET 18
10980 +#define USBA_BUSY_BANK_IE_SIZE 1
10981 +
10982 +/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
10983 +#define USBA_FORCE_STALL_OFFSET 5
10984 +#define USBA_FORCE_STALL_SIZE 1
10985 +#define USBA_TOGGLE_SEQ_OFFSET 6
10986 +#define USBA_TOGGLE_SEQ_SIZE 2
10987 +#define USBA_ERR_OVFLW_OFFSET 8
10988 +#define USBA_ERR_OVFLW_SIZE 1
10989 +#define USBA_RX_BK_RDY_OFFSET 9
10990 +#define USBA_RX_BK_RDY_SIZE 1
10991 +#define USBA_KILL_BANK_OFFSET 9
10992 +#define USBA_KILL_BANK_SIZE 1
10993 +#define USBA_TX_COMPLETE_OFFSET 10
10994 +#define USBA_TX_COMPLETE_SIZE 1
10995 +#define USBA_TX_PK_RDY_OFFSET 11
10996 +#define USBA_TX_PK_RDY_SIZE 1
10997 +#define USBA_ISO_ERR_TRANS_OFFSET 11
10998 +#define USBA_ISO_ERR_TRANS_SIZE 1
10999 +#define USBA_RX_SETUP_OFFSET 12
11000 +#define USBA_RX_SETUP_SIZE 1
11001 +#define USBA_ISO_ERR_FLOW_OFFSET 12
11002 +#define USBA_ISO_ERR_FLOW_SIZE 1
11003 +#define USBA_STALL_SENT_OFFSET 13
11004 +#define USBA_STALL_SENT_SIZE 1
11005 +#define USBA_ISO_ERR_CRC_OFFSET 13
11006 +#define USBA_ISO_ERR_CRC_SIZE 1
11007 +#define USBA_ISO_ERR_NBTRANS_OFFSET 13
11008 +#define USBA_ISO_ERR_NBTRANS_SIZE 1
11009 +#define USBA_NAK_IN_OFFSET 14
11010 +#define USBA_NAK_IN_SIZE 1
11011 +#define USBA_ISO_ERR_FLUSH_OFFSET 14
11012 +#define USBA_ISO_ERR_FLUSH_SIZE 1
11013 +#define USBA_NAK_OUT_OFFSET 15
11014 +#define USBA_NAK_OUT_SIZE 1
11015 +#define USBA_CURRENT_BANK_OFFSET 16
11016 +#define USBA_CURRENT_BANK_SIZE 2
11017 +#define USBA_BUSY_BANKS_OFFSET 18
11018 +#define USBA_BUSY_BANKS_SIZE 2
11019 +#define USBA_BYTE_COUNT_OFFSET 20
11020 +#define USBA_BYTE_COUNT_SIZE 11
11021 +#define USBA_SHORT_PACKET_OFFSET 31
11022 +#define USBA_SHORT_PACKET_SIZE 1
11023 +
11024 +/* Bitfields in DMA_CONTROL */
11025 +#define USBA_DMA_CH_EN_OFFSET 0
11026 +#define USBA_DMA_CH_EN_SIZE 1
11027 +#define USBA_DMA_LINK_OFFSET 1
11028 +#define USBA_DMA_LINK_SIZE 1
11029 +#define USBA_DMA_END_TR_EN_OFFSET 2
11030 +#define USBA_DMA_END_TR_EN_SIZE 1
11031 +#define USBA_DMA_END_BUF_EN_OFFSET 3
11032 +#define USBA_DMA_END_BUF_EN_SIZE 1
11033 +#define USBA_DMA_END_TR_IE_OFFSET 4
11034 +#define USBA_DMA_END_TR_IE_SIZE 1
11035 +#define USBA_DMA_END_BUF_IE_OFFSET 5
11036 +#define USBA_DMA_END_BUF_IE_SIZE 1
11037 +#define USBA_DMA_DESC_LOAD_IE_OFFSET 6
11038 +#define USBA_DMA_DESC_LOAD_IE_SIZE 1
11039 +#define USBA_DMA_BURST_LOCK_OFFSET 7
11040 +#define USBA_DMA_BURST_LOCK_SIZE 1
11041 +#define USBA_DMA_BUF_LEN_OFFSET 16
11042 +#define USBA_DMA_BUF_LEN_SIZE 16
11043 +
11044 +/* Bitfields in DMA_STATUS */
11045 +#define USBA_DMA_CH_ACTIVE_OFFSET 1
11046 +#define USBA_DMA_CH_ACTIVE_SIZE 1
11047 +#define USBA_DMA_END_TR_ST_OFFSET 4
11048 +#define USBA_DMA_END_TR_ST_SIZE 1
11049 +#define USBA_DMA_END_BUF_ST_OFFSET 5
11050 +#define USBA_DMA_END_BUF_ST_SIZE 1
11051 +#define USBA_DMA_DESC_LOAD_ST_OFFSET 6
11052 +#define USBA_DMA_DESC_LOAD_ST_SIZE 1
11053 +
11054 +/* Constants for SPEED_CFG */
11055 +#define USBA_SPEED_CFG_NORMAL 0
11056 +#define USBA_SPEED_CFG_FORCE_HIGH 2
11057 +#define USBA_SPEED_CFG_FORCE_FULL 3
11058 +
11059 +/* Constants for EPT_SIZE */
11060 +#define USBA_EPT_SIZE_8 0
11061 +#define USBA_EPT_SIZE_16 1
11062 +#define USBA_EPT_SIZE_32 2
11063 +#define USBA_EPT_SIZE_64 3
11064 +#define USBA_EPT_SIZE_128 4
11065 +#define USBA_EPT_SIZE_256 5
11066 +#define USBA_EPT_SIZE_512 6
11067 +#define USBA_EPT_SIZE_1024 7
11068 +
11069 +/* Constants for EPT_TYPE */
11070 +#define USBA_EPT_TYPE_CONTROL 0
11071 +#define USBA_EPT_TYPE_ISO 1
11072 +#define USBA_EPT_TYPE_BULK 2
11073 +#define USBA_EPT_TYPE_INT 3
11074 +
11075 +/* Constants for BK_NUMBER */
11076 +#define USBA_BK_NUMBER_ZERO 0
11077 +#define USBA_BK_NUMBER_ONE 1
11078 +#define USBA_BK_NUMBER_DOUBLE 2
11079 +#define USBA_BK_NUMBER_TRIPLE 3
11080 +
11081 +/* Bit manipulation macros */
11082 +#define USBA_BIT(name) \
11083 + (1 << USBA_##name##_OFFSET)
11084 +#define USBA_BF(name, value) \
11085 + (((value) & ((1 << USBA_##name##_SIZE) - 1)) \
11086 + << USBA_##name##_OFFSET)
11087 +#define USBA_BFEXT(name, value) \
11088 + (((value) >> USBA_##name##_OFFSET) \
11089 + & ((1 << USBA_##name##_SIZE) - 1))
11090 +#define USBA_BFINS(name, value, old) \
11091 + (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
11092 + << USBA_##name##_OFFSET)) \
11093 + | USBA_BF(name, value))
11094 +
11095 +/* Register access macros */
11096 +#define usba_readl(udc, reg) \
11097 + __raw_readl((udc)->regs + USBA_##reg)
11098 +#define usba_writel(udc, reg, value) \
11099 + __raw_writel((value), (udc)->regs + USBA_##reg)
11100 +#define usba_ep_readl(ep, reg) \
11101 + __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
11102 +#define usba_ep_writel(ep, reg, value) \
11103 + __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
11104 +#define usba_dma_readl(ep, reg) \
11105 + __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
11106 +#define usba_dma_writel(ep, reg, value) \
11107 + __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
11108 +
11109 +/* Calculate base address for a given endpoint or DMA controller */
11110 +#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
11111 +#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
11112 +#define USBA_FIFO_BASE(x) ((x) << 16)
11113 +
11114 +/* Synth parameters */
11115 +#define USBA_NR_ENDPOINTS 7
11116 +
11117 +#define EP0_FIFO_SIZE 64
11118 +#define EP0_EPT_SIZE USBA_EPT_SIZE_64
11119 +#define EP0_NR_BANKS 1
11120 +#define BULK_FIFO_SIZE 512
11121 +#define BULK_EPT_SIZE USBA_EPT_SIZE_512
11122 +#define BULK_NR_BANKS 2
11123 +#define ISO_FIFO_SIZE 1024
11124 +#define ISO_EPT_SIZE USBA_EPT_SIZE_1024
11125 +#define ISO_NR_BANKS 3
11126 +#define INT_FIFO_SIZE 64
11127 +#define INT_EPT_SIZE USBA_EPT_SIZE_64
11128 +#define INT_NR_BANKS 3
11129 +
11130 +enum usba_ctrl_state {
11131 + WAIT_FOR_SETUP,
11132 + DATA_STAGE_IN,
11133 + DATA_STAGE_OUT,
11134 + STATUS_STAGE_IN,
11135 + STATUS_STAGE_OUT,
11136 + STATUS_STAGE_ADDR,
11137 + STATUS_STAGE_TEST,
11138 +};
11139 +/*
11140 + EP_STATE_IDLE,
11141 + EP_STATE_SETUP,
11142 + EP_STATE_IN_DATA,
11143 + EP_STATE_OUT_DATA,
11144 + EP_STATE_SET_ADDR_STATUS,
11145 + EP_STATE_RX_STATUS,
11146 + EP_STATE_TX_STATUS,
11147 + EP_STATE_HALT,
11148 +*/
11149 +
11150 +struct usba_dma_desc {
11151 + dma_addr_t next;
11152 + dma_addr_t addr;
11153 + u32 ctrl;
11154 +};
11155 +
11156 +struct usba_ep {
11157 + int state;
11158 + void __iomem *ep_regs;
11159 + void __iomem *dma_regs;
11160 + void __iomem *fifo;
11161 + struct usb_ep ep;
11162 + struct usba_udc *udc;
11163 +
11164 + struct list_head queue;
11165 + const struct usb_endpoint_descriptor *desc;
11166 +
11167 + u16 fifo_size;
11168 + u8 nr_banks;
11169 + u8 index;
11170 + unsigned int can_dma:1;
11171 + unsigned int can_isoc:1;
11172 + unsigned int is_isoc:1;
11173 + unsigned int is_in:1;
11174 +
11175 +#ifdef CONFIG_DEBUG_FS
11176 + u32 last_dma_status;
11177 + struct dentry *debugfs_dir;
11178 + struct dentry *debugfs_queue;
11179 + struct dentry *debugfs_dma_status;
11180 + struct dentry *debugfs_state;
11181 +#endif
11182 +};
11183 +
11184 +struct usba_request {
11185 + struct usb_request req;
11186 + struct list_head queue;
11187 +
11188 + u32 ctrl;
11189 +
11190 + unsigned int submitted:1;
11191 + unsigned int last_transaction:1;
11192 + unsigned int using_dma:1;
11193 + unsigned int mapped:1;
11194 +};
11195 +
11196 +struct usba_udc {
11197 + /* Protect hw registers from concurrent modifications */
11198 + spinlock_t lock;
11199 +
11200 + void __iomem *regs;
11201 + void __iomem *fifo;
11202 +
11203 + struct usb_gadget gadget;
11204 + struct usb_gadget_driver *driver;
11205 + struct platform_device *pdev;
11206 + int irq;
11207 + int vbus_pin;
11208 + struct clk *pclk;
11209 + struct clk *hclk;
11210 +
11211 + int test_mode;
11212 + int vbus_prev;
11213 +
11214 +#ifdef CONFIG_DEBUG_FS
11215 + struct dentry *debugfs_root;
11216 + struct dentry *debugfs_regs;
11217 +#endif
11218 +};
11219 +
11220 +#define to_usba_ep(x) container_of((x), struct usba_ep, ep)
11221 +#define to_usba_req(x) container_of((x), struct usba_request, req)
11222 +#define to_usba_udc(x) container_of((x), struct usba_udc, gadget)
11223 +
11224 +#define ep_index(ep) ((ep)->index)
11225 +#define ep_can_dma(ep) ((ep)->can_dma)
11226 +#define ep_is_in(ep) ((ep)->is_in)
11227 +#define ep_is_isochronous(ep) ((ep)->is_isoc)
11228 +#define ep_is_control(ep) (ep_index(ep) == 0)
11229 +#define ep_name(ep) ((ep)->ep.name)
11230 +#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
11231 +
11232 +#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
11233 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/ether.c linux-avr32.git/drivers/usb/gadget/ether.c
11234 --- linux-2.6.22.1/drivers/usb/gadget/ether.c 2007-07-10 20:56:30.000000000 +0200
11235 +++ linux-avr32.git/drivers/usb/gadget/ether.c 2007-07-12 14:00:19.000000000 +0200
11236 @@ -277,7 +277,7 @@
11237 #define DEV_CONFIG_CDC
11238 #endif
11239
11240 -#ifdef CONFIG_USB_GADGET_HUSB2DEV
11241 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
11242 #define DEV_CONFIG_CDC
11243 #endif
11244
11245 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/gadget_chips.h linux-avr32.git/drivers/usb/gadget/gadget_chips.h
11246 --- linux-2.6.22.1/drivers/usb/gadget/gadget_chips.h 2007-07-10 20:56:30.000000000 +0200
11247 +++ linux-avr32.git/drivers/usb/gadget/gadget_chips.h 2007-07-12 14:00:19.000000000 +0200
11248 @@ -75,10 +75,10 @@
11249 #define gadget_is_pxa27x(g) 0
11250 #endif
11251
11252 -#ifdef CONFIG_USB_GADGET_HUSB2DEV
11253 -#define gadget_is_husb2dev(g) !strcmp("husb2_udc", (g)->name)
11254 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
11255 +#define gadget_is_atmel_usba(g) !strcmp("atmel_usba_udc", (g)->name)
11256 #else
11257 -#define gadget_is_husb2dev(g) 0
11258 +#define gadget_is_atmel_usba(g) 0
11259 #endif
11260
11261 #ifdef CONFIG_USB_GADGET_S3C2410
11262 @@ -181,7 +181,7 @@
11263 return 0x16;
11264 else if (gadget_is_mpc8272(gadget))
11265 return 0x17;
11266 - else if (gadget_is_husb2dev(gadget))
11267 + else if (gadget_is_atmel_usba(gadget))
11268 return 0x18;
11269 else if (gadget_is_fsl_usb2(gadget))
11270 return 0x19;
11271 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/inode.c linux-avr32.git/drivers/usb/gadget/inode.c
11272 --- linux-2.6.22.1/drivers/usb/gadget/inode.c 2007-07-10 20:56:30.000000000 +0200
11273 +++ linux-avr32.git/drivers/usb/gadget/inode.c 2007-07-12 14:00:19.000000000 +0200
11274 @@ -37,7 +37,7 @@
11275 #include <linux/device.h>
11276 #include <linux/moduleparam.h>
11277
11278 -#include <linux/usb_gadgetfs.h>
11279 +#include <linux/usb/gadgetfs.h>
11280 #include <linux/usb_gadget.h>
11281
11282
11283 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/Kconfig linux-avr32.git/drivers/usb/gadget/Kconfig
11284 --- linux-2.6.22.1/drivers/usb/gadget/Kconfig 2007-07-10 20:56:30.000000000 +0200
11285 +++ linux-avr32.git/drivers/usb/gadget/Kconfig 2007-07-12 14:00:19.000000000 +0200
11286 @@ -175,6 +175,19 @@
11287 default USB_GADGET
11288 select USB_GADGET_SELECTED
11289
11290 +config USB_GADGET_ATMEL_USBA
11291 + boolean "Atmel USBA"
11292 + select USB_GADGET_DUALSPEED
11293 + depends on AVR32
11294 + help
11295 + USBA is the integrated high-speed USB Device controller on
11296 + the AT32AP700x processors from Atmel.
11297 +
11298 +config USB_ATMEL_USBA
11299 + tristate
11300 + depends on USB_GADGET_ATMEL_USBA
11301 + default USB_GADGET
11302 + select USB_GADGET_SELECTED
11303
11304 config USB_GADGET_OMAP
11305 boolean "OMAP USB Device Controller"
11306 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/Makefile linux-avr32.git/drivers/usb/gadget/Makefile
11307 --- linux-2.6.22.1/drivers/usb/gadget/Makefile 2007-07-10 20:56:30.000000000 +0200
11308 +++ linux-avr32.git/drivers/usb/gadget/Makefile 2007-07-12 14:00:19.000000000 +0200
11309 @@ -8,6 +8,7 @@
11310 obj-$(CONFIG_USB_OMAP) += omap_udc.o
11311 obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
11312 obj-$(CONFIG_USB_AT91) += at91_udc.o
11313 +obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
11314 obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
11315
11316 #
11317 diff -x .git -Nur linux-2.6.22.1/drivers/video/atmel_lcdfb.c linux-avr32.git/drivers/video/atmel_lcdfb.c
11318 --- linux-2.6.22.1/drivers/video/atmel_lcdfb.c 2007-07-10 20:56:30.000000000 +0200
11319 +++ linux-avr32.git/drivers/video/atmel_lcdfb.c 2007-07-12 14:00:20.000000000 +0200
11320 @@ -37,7 +37,9 @@
11321 #endif
11322
11323 #if defined(CONFIG_ARCH_AT91)
11324 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
11325 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
11326 + | FBINFO_PARTIAL_PAN_OK \
11327 + | FBINFO_HWACCEL_YPAN)
11328
11329 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
11330 struct fb_var_screeninfo *var)
11331 @@ -74,11 +76,34 @@
11332 .type = FB_TYPE_PACKED_PIXELS,
11333 .visual = FB_VISUAL_TRUECOLOR,
11334 .xpanstep = 0,
11335 - .ypanstep = 0,
11336 + .ypanstep = 1,
11337 .ywrapstep = 0,
11338 .accel = FB_ACCEL_NONE,
11339 };
11340
11341 +static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
11342 +{
11343 + unsigned long value;
11344 +
11345 + if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
11346 + return xres;
11347 +
11348 + value = xres;
11349 + if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
11350 + /* STN display */
11351 + if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
11352 + value *= 3;
11353 + }
11354 + if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
11355 + || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
11356 + && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
11357 + value = DIV_ROUND_UP(value, 4);
11358 + else
11359 + value = DIV_ROUND_UP(value, 8);
11360 + }
11361 +
11362 + return value;
11363 +}
11364
11365 static void atmel_lcdfb_update_dma(struct fb_info *info,
11366 struct fb_var_screeninfo *var)
11367 @@ -181,6 +206,7 @@
11368 var->xoffset = var->yoffset = 0;
11369
11370 switch (var->bits_per_pixel) {
11371 + case 1:
11372 case 2:
11373 case 4:
11374 case 8:
11375 @@ -195,8 +221,11 @@
11376 var->blue.offset = 10;
11377 var->red.length = var->green.length = var->blue.length = 5;
11378 break;
11379 - case 24:
11380 case 32:
11381 + var->transp.offset = 24;
11382 + var->transp.length = 8;
11383 + /* fall through */
11384 + case 24:
11385 var->red.offset = 0;
11386 var->green.offset = 8;
11387 var->blue.offset = 16;
11388 @@ -228,8 +257,10 @@
11389 static int atmel_lcdfb_set_par(struct fb_info *info)
11390 {
11391 struct atmel_lcdfb_info *sinfo = info->par;
11392 + unsigned long hozval_linesz;
11393 unsigned long value;
11394 unsigned long clk_value_khz;
11395 + unsigned long bits_per_line;
11396
11397 dev_dbg(info->device, "%s:\n", __func__);
11398 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
11399 @@ -241,12 +272,15 @@
11400
11401 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
11402
11403 - if (info->var.bits_per_pixel <= 8)
11404 + if (info->var.bits_per_pixel == 1)
11405 + info->fix.visual = FB_VISUAL_MONO01;
11406 + else if (info->var.bits_per_pixel <= 8)
11407 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
11408 else
11409 info->fix.visual = FB_VISUAL_TRUECOLOR;
11410
11411 - info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8);
11412 + bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
11413 + info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
11414
11415 /* Re-initialize the DMA engine... */
11416 dev_dbg(info->device, " * update DMA engine\n");
11417 @@ -262,18 +296,21 @@
11418 /* Set pixel clock */
11419 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
11420
11421 - value = clk_value_khz / PICOS2KHZ(info->var.pixclock);
11422 -
11423 - if (clk_value_khz % PICOS2KHZ(info->var.pixclock))
11424 - value++;
11425 + value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
11426
11427 value = (value / 2) - 1;
11428 + dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value);
11429
11430 if (value <= 0) {
11431 dev_notice(info->device, "Bypassing pixel clock divider\n");
11432 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
11433 - } else
11434 + } else {
11435 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
11436 + info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
11437 + dev_dbg(info->device, " updated pixclk: %lu KHz\n",
11438 + PICOS2KHZ(info->var.pixclock));
11439 + }
11440 +
11441
11442 /* Initialize control register 2 */
11443 value = sinfo->default_lcdcon2;
11444 @@ -311,9 +348,14 @@
11445 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
11446 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
11447
11448 + /* Horizontal value (aka line size) */
11449 + hozval_linesz = compute_hozval(info->var.xres,
11450 + lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
11451 +
11452 /* Display size */
11453 - value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
11454 + value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
11455 value |= info->var.yres - 1;
11456 + dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
11457 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
11458
11459 /* FIFO Threshold: Use formula from data sheet */
11460 @@ -421,6 +463,15 @@
11461 ret = 0;
11462 }
11463 break;
11464 +
11465 + case FB_VISUAL_MONO01:
11466 + if (regno < 2) {
11467 + val = (regno == 0) ? 0x00 : 0x1F;
11468 + lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
11469 + ret = 0;
11470 + }
11471 + break;
11472 +
11473 }
11474
11475 return ret;
11476 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/Kconfig linux-avr32.git/drivers/video/backlight/Kconfig
11477 --- linux-2.6.22.1/drivers/video/backlight/Kconfig 2007-07-10 20:56:30.000000000 +0200
11478 +++ linux-avr32.git/drivers/video/backlight/Kconfig 2007-07-12 14:00:20.000000000 +0200
11479 @@ -8,26 +8,44 @@
11480 Enable this to be able to choose the drivers for controlling the
11481 backlight and the LCD panel on some platforms, for example on PDAs.
11482
11483 -config BACKLIGHT_CLASS_DEVICE
11484 - tristate "Lowlevel Backlight controls"
11485 +#
11486 +# LCD
11487 +#
11488 +config LCD_CLASS_DEVICE
11489 + tristate "Lowlevel LCD controls"
11490 depends on BACKLIGHT_LCD_SUPPORT
11491 default m
11492 help
11493 - This framework adds support for low-level control of the LCD
11494 - backlight. This includes support for brightness and power.
11495 + This framework adds support for low-level control of LCD.
11496 + Some framebuffer devices connect to platform-specific LCD modules
11497 + in order to have a platform-specific way to control the flat panel
11498 + (contrast and applying power to the LCD (not to the backlight!)).
11499
11500 To have support for your specific LCD panel you will have to
11501 select the proper drivers which depend on this option.
11502
11503 -config LCD_CLASS_DEVICE
11504 - tristate "Lowlevel LCD controls"
11505 +config LCD_LTV350QV
11506 + tristate "Samsung LTV350QV LCD Panel"
11507 + depends on LCD_CLASS_DEVICE && SPI_MASTER
11508 + default n
11509 + help
11510 + If you have a Samsung LTV350QV LCD panel, say y to include a
11511 + power control driver for it. The panel starts up in power
11512 + off state, so you need this driver in order to see any
11513 + output.
11514 +
11515 + The LTV350QV panel is present on all ATSTK1000 boards.
11516 +
11517 +#
11518 +# Backlight
11519 +#
11520 +config BACKLIGHT_CLASS_DEVICE
11521 + tristate "Lowlevel Backlight controls"
11522 depends on BACKLIGHT_LCD_SUPPORT
11523 default m
11524 help
11525 - This framework adds support for low-level control of LCD.
11526 - Some framebuffer devices connect to platform-specific LCD modules
11527 - in order to have a platform-specific way to control the flat panel
11528 - (contrast and applying power to the LCD (not to the backlight!)).
11529 + This framework adds support for low-level control of the LCD
11530 + backlight. This includes support for brightness and power.
11531
11532 To have support for your specific LCD panel you will have to
11533 select the proper drivers which depend on this option.
11534 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/ltv350qv.c linux-avr32.git/drivers/video/backlight/ltv350qv.c
11535 --- linux-2.6.22.1/drivers/video/backlight/ltv350qv.c 1970-01-01 01:00:00.000000000 +0100
11536 +++ linux-avr32.git/drivers/video/backlight/ltv350qv.c 2007-06-06 11:34:00.000000000 +0200
11537 @@ -0,0 +1,340 @@
11538 +/*
11539 + * Power control for Samsung LTV350QV Quarter VGA LCD Panel
11540 + *
11541 + * Copyright (C) 2006, 2007 Atmel Corporation
11542 + *
11543 + * This program is free software; you can redistribute it and/or modify
11544 + * it under the terms of the GNU General Public License version 2 as
11545 + * published by the Free Software Foundation.
11546 + */
11547 +#include <linux/delay.h>
11548 +#include <linux/err.h>
11549 +#include <linux/fb.h>
11550 +#include <linux/init.h>
11551 +#include <linux/lcd.h>
11552 +#include <linux/module.h>
11553 +#include <linux/spi/spi.h>
11554 +
11555 +#include "ltv350qv.h"
11556 +
11557 +#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
11558 +
11559 +struct ltv350qv {
11560 + struct spi_device *spi;
11561 + u8 *buffer;
11562 + int power;
11563 + struct lcd_device *ld;
11564 +};
11565 +
11566 +/*
11567 + * The power-on and power-off sequences are taken from the
11568 + * LTV350QV-F04 data sheet from Samsung. The register definitions are
11569 + * taken from the S6F2002 command list also from Samsung. Both
11570 + * documents are distributed with the AVR32 Linux BSP CD from Atmel.
11571 + *
11572 + * There's still some voodoo going on here, but it's a lot better than
11573 + * in the first incarnation of the driver where all we had was the raw
11574 + * numbers from the initialization sequence.
11575 + */
11576 +static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val)
11577 +{
11578 + struct spi_message msg;
11579 + struct spi_transfer index_xfer = {
11580 + .len = 3,
11581 + .cs_change = 1,
11582 + };
11583 + struct spi_transfer value_xfer = {
11584 + .len = 3,
11585 + .cs_change = 1,
11586 + };
11587 +
11588 + spi_message_init(&msg);
11589 +
11590 + /* register index */
11591 + lcd->buffer[0] = LTV_OPC_INDEX;
11592 + lcd->buffer[1] = 0x00;
11593 + lcd->buffer[2] = reg & 0x7f;
11594 + index_xfer.tx_buf = lcd->buffer;
11595 + spi_message_add_tail(&index_xfer, &msg);
11596 +
11597 + /* register value */
11598 + lcd->buffer[4] = LTV_OPC_DATA;
11599 + lcd->buffer[5] = val >> 8;
11600 + lcd->buffer[6] = val;
11601 + value_xfer.tx_buf = lcd->buffer + 4;
11602 + spi_message_add_tail(&value_xfer, &msg);
11603 +
11604 + return spi_sync(lcd->spi, &msg);
11605 +}
11606 +
11607 +/* The comments are taken straight from the data sheet */
11608 +static int ltv350qv_power_on(struct ltv350qv *lcd)
11609 +{
11610 + int ret;
11611 +
11612 + /* Power On Reset Display off State */
11613 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, 0x0000))
11614 + goto err;
11615 + msleep(15);
11616 +
11617 + /* Power Setting Function 1 */
11618 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE))
11619 + goto err;
11620 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL2, LTV_VCOML_ENABLE))
11621 + goto err_power1;
11622 +
11623 + /* Power Setting Function 2 */
11624 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1,
11625 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
11626 + | LTV_SUPPLY_CURRENT(5)))
11627 + goto err_power2;
11628 +
11629 + msleep(55);
11630 +
11631 + /* Instruction Setting */
11632 + ret = ltv350qv_write_reg(lcd, LTV_IFCTL,
11633 + LTV_NMD | LTV_REV | LTV_NL(0x1d));
11634 + ret |= ltv350qv_write_reg(lcd, LTV_DATACTL,
11635 + LTV_DS_SAME | LTV_CHS_480
11636 + | LTV_DF_RGB | LTV_RGB_BGR);
11637 + ret |= ltv350qv_write_reg(lcd, LTV_ENTRY_MODE,
11638 + LTV_VSPL_ACTIVE_LOW
11639 + | LTV_HSPL_ACTIVE_LOW
11640 + | LTV_DPL_SAMPLE_RISING
11641 + | LTV_EPL_ACTIVE_LOW
11642 + | LTV_SS_RIGHT_TO_LEFT);
11643 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL1, LTV_CLW(3));
11644 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
11645 + LTV_NW_INV_1LINE | LTV_FWI(3));
11646 + ret |= ltv350qv_write_reg(lcd, LTV_VBP, 0x000a);
11647 + ret |= ltv350qv_write_reg(lcd, LTV_HBP, 0x0021);
11648 + ret |= ltv350qv_write_reg(lcd, LTV_SOTCTL, LTV_SDT(3) | LTV_EQ(0));
11649 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(0), 0x0103);
11650 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(1), 0x0301);
11651 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(2), 0x1f0f);
11652 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(3), 0x1f0f);
11653 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(4), 0x0707);
11654 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(5), 0x0307);
11655 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(6), 0x0707);
11656 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(7), 0x0000);
11657 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(8), 0x0004);
11658 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(9), 0x0000);
11659 + if (ret)
11660 + goto err_settings;
11661 +
11662 + /* Wait more than 2 frames */
11663 + msleep(20);
11664 +
11665 + /* Display On Sequence */
11666 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
11667 + LTV_VCOM_DISABLE | LTV_VCOMOUT_ENABLE
11668 + | LTV_POWER_ON | LTV_DRIVE_CURRENT(5)
11669 + | LTV_SUPPLY_CURRENT(5));
11670 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
11671 + LTV_NW_INV_1LINE | LTV_DSC | LTV_FWI(3));
11672 + if (ret)
11673 + goto err_disp_on;
11674 +
11675 + /* Display should now be ON. Phew. */
11676 + return 0;
11677 +
11678 +err_disp_on:
11679 + /*
11680 + * Try to recover. Error handling probably isn't very useful
11681 + * at this point, just make a best effort to switch the panel
11682 + * off.
11683 + */
11684 + ltv350qv_write_reg(lcd, LTV_PWRCTL1,
11685 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
11686 + | LTV_SUPPLY_CURRENT(5));
11687 + ltv350qv_write_reg(lcd, LTV_GATECTL2,
11688 + LTV_NW_INV_1LINE | LTV_FWI(3));
11689 +err_settings:
11690 +err_power2:
11691 +err_power1:
11692 + ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
11693 + msleep(1);
11694 +err:
11695 + ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
11696 + return -EIO;
11697 +}
11698 +
11699 +static int ltv350qv_power_off(struct ltv350qv *lcd)
11700 +{
11701 + int ret;
11702 +
11703 + /* Display Off Sequence */
11704 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
11705 + LTV_VCOM_DISABLE
11706 + | LTV_DRIVE_CURRENT(5)
11707 + | LTV_SUPPLY_CURRENT(5));
11708 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
11709 + LTV_NW_INV_1LINE | LTV_FWI(3));
11710 +
11711 + /* Power down setting 1 */
11712 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
11713 +
11714 + /* Wait at least 1 ms */
11715 + msleep(1);
11716 +
11717 + /* Power down setting 2 */
11718 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
11719 +
11720 + /*
11721 + * No point in trying to recover here. If we can't switch the
11722 + * panel off, what are we supposed to do other than inform the
11723 + * user about the failure?
11724 + */
11725 + if (ret)
11726 + return -EIO;
11727 +
11728 + /* Display power should now be OFF */
11729 + return 0;
11730 +}
11731 +
11732 +static int ltv350qv_power(struct ltv350qv *lcd, int power)
11733 +{
11734 + int ret = 0;
11735 +
11736 + if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
11737 + ret = ltv350qv_power_on(lcd);
11738 + else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
11739 + ret = ltv350qv_power_off(lcd);
11740 +
11741 + if (!ret)
11742 + lcd->power = power;
11743 +
11744 + return ret;
11745 +}
11746 +
11747 +static int ltv350qv_set_power(struct lcd_device *ld, int power)
11748 +{
11749 + struct ltv350qv *lcd;
11750 +
11751 + lcd = class_get_devdata(&ld->class_dev);
11752 + return ltv350qv_power(lcd, power);
11753 +}
11754 +
11755 +static int ltv350qv_get_power(struct lcd_device *ld)
11756 +{
11757 + struct ltv350qv *lcd;
11758 +
11759 + lcd = class_get_devdata(&ld->class_dev);
11760 + return lcd->power;
11761 +}
11762 +
11763 +static struct lcd_ops ltv_ops = {
11764 + .get_power = ltv350qv_get_power,
11765 + .set_power = ltv350qv_set_power,
11766 +};
11767 +
11768 +static int __devinit ltv350qv_probe(struct spi_device *spi)
11769 +{
11770 + struct ltv350qv *lcd;
11771 + struct lcd_device *ld;
11772 + int ret;
11773 +
11774 + lcd = kzalloc(sizeof(struct ltv350qv), GFP_KERNEL);
11775 + if (!lcd)
11776 + return -ENOMEM;
11777 +
11778 + lcd->spi = spi;
11779 + lcd->power = FB_BLANK_POWERDOWN;
11780 + lcd->buffer = kzalloc(8, GFP_KERNEL);
11781 +
11782 + ld = lcd_device_register("ltv350qv", lcd, &ltv_ops);
11783 + if (IS_ERR(ld)) {
11784 + ret = PTR_ERR(ld);
11785 + goto out_free_lcd;
11786 + }
11787 + lcd->ld = ld;
11788 +
11789 + ret = ltv350qv_power(lcd, FB_BLANK_UNBLANK);
11790 + if (ret)
11791 + goto out_unregister;
11792 +
11793 + dev_set_drvdata(&spi->dev, lcd);
11794 +
11795 + return 0;
11796 +
11797 +out_unregister:
11798 + lcd_device_unregister(ld);
11799 +out_free_lcd:
11800 + kfree(lcd);
11801 + return ret;
11802 +}
11803 +
11804 +static int __devexit ltv350qv_remove(struct spi_device *spi)
11805 +{
11806 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
11807 +
11808 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
11809 + lcd_device_unregister(lcd->ld);
11810 + kfree(lcd);
11811 +
11812 + return 0;
11813 +}
11814 +
11815 +#ifdef CONFIG_PM
11816 +static int ltv350qv_suspend(struct spi_device *spi,
11817 + pm_message_t state, u32 level)
11818 +{
11819 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
11820 +
11821 + if (level == SUSPEND_POWER_DOWN)
11822 + return ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
11823 +
11824 + return 0;
11825 +}
11826 +
11827 +static int ltv350qv_resume(struct spi_device *spi, u32 level)
11828 +{
11829 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
11830 +
11831 + if (level == RESUME_POWER_ON)
11832 + return ltv350qv_power(lcd, FB_BLANK_UNBLANK);
11833 +
11834 + return 0;
11835 +}
11836 +#else
11837 +#define ltv350qv_suspend NULL
11838 +#define ltv350qv_resume NULL
11839 +#endif
11840 +
11841 +/* Power down all displays on reboot, poweroff or halt */
11842 +static void ltv350qv_shutdown(struct spi_device *spi)
11843 +{
11844 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
11845 +
11846 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
11847 +}
11848 +
11849 +static struct spi_driver ltv350qv_driver = {
11850 + .driver = {
11851 + .name = "ltv350qv",
11852 + .bus = &spi_bus_type,
11853 + .owner = THIS_MODULE,
11854 + },
11855 +
11856 + .probe = ltv350qv_probe,
11857 + .remove = __devexit_p(ltv350qv_remove),
11858 + .shutdown = ltv350qv_shutdown,
11859 + .suspend = ltv350qv_suspend,
11860 + .resume = ltv350qv_resume,
11861 +};
11862 +
11863 +static int __init ltv350qv_init(void)
11864 +{
11865 + return spi_register_driver(&ltv350qv_driver);
11866 +}
11867 +
11868 +static void __exit ltv350qv_exit(void)
11869 +{
11870 + spi_unregister_driver(&ltv350qv_driver);
11871 +}
11872 +module_init(ltv350qv_init);
11873 +module_exit(ltv350qv_exit);
11874 +
11875 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
11876 +MODULE_DESCRIPTION("Samsung LTV350QV LCD Driver");
11877 +MODULE_LICENSE("GPL");
11878 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/ltv350qv.h linux-avr32.git/drivers/video/backlight/ltv350qv.h
11879 --- linux-2.6.22.1/drivers/video/backlight/ltv350qv.h 1970-01-01 01:00:00.000000000 +0100
11880 +++ linux-avr32.git/drivers/video/backlight/ltv350qv.h 2007-06-06 11:34:00.000000000 +0200
11881 @@ -0,0 +1,95 @@
11882 +/*
11883 + * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel
11884 + *
11885 + * Copyright (C) 2006, 2007 Atmel Corporation
11886 + *
11887 + * This program is free software; you can redistribute it and/or modify
11888 + * it under the terms of the GNU General Public License version 2 as
11889 + * published by the Free Software Foundation.
11890 + */
11891 +#ifndef __LTV350QV_H
11892 +#define __LTV350QV_H
11893 +
11894 +#define LTV_OPC_INDEX 0x74
11895 +#define LTV_OPC_DATA 0x76
11896 +
11897 +#define LTV_ID 0x00 /* ID Read */
11898 +#define LTV_IFCTL 0x01 /* Display Interface Control */
11899 +#define LTV_DATACTL 0x02 /* Display Data Control */
11900 +#define LTV_ENTRY_MODE 0x03 /* Entry Mode */
11901 +#define LTV_GATECTL1 0x04 /* Gate Control 1 */
11902 +#define LTV_GATECTL2 0x05 /* Gate Control 2 */
11903 +#define LTV_VBP 0x06 /* Vertical Back Porch */
11904 +#define LTV_HBP 0x07 /* Horizontal Back Porch */
11905 +#define LTV_SOTCTL 0x08 /* Source Output Timing Control */
11906 +#define LTV_PWRCTL1 0x09 /* Power Control 1 */
11907 +#define LTV_PWRCTL2 0x0a /* Power Control 2 */
11908 +#define LTV_GAMMA(x) (0x10 + (x)) /* Gamma control */
11909 +
11910 +/* Bit definitions for LTV_IFCTL */
11911 +#define LTV_IM (1 << 15)
11912 +#define LTV_NMD (1 << 14)
11913 +#define LTV_SSMD (1 << 13)
11914 +#define LTV_REV (1 << 7)
11915 +#define LTV_NL(x) (((x) & 0x001f) << 0)
11916 +
11917 +/* Bit definitions for LTV_DATACTL */
11918 +#define LTV_DS_SAME (0 << 12)
11919 +#define LTV_DS_D_TO_S (1 << 12)
11920 +#define LTV_DS_S_TO_D (2 << 12)
11921 +#define LTV_CHS_384 (0 << 9)
11922 +#define LTV_CHS_480 (1 << 9)
11923 +#define LTV_CHS_492 (2 << 9)
11924 +#define LTV_DF_RGB (0 << 6)
11925 +#define LTV_DF_RGBX (1 << 6)
11926 +#define LTV_DF_XRGB (2 << 6)
11927 +#define LTV_RGB_RGB (0 << 2)
11928 +#define LTV_RGB_BGR (1 << 2)
11929 +#define LTV_RGB_GRB (2 << 2)
11930 +#define LTV_RGB_RBG (3 << 2)
11931 +
11932 +/* Bit definitions for LTV_ENTRY_MODE */
11933 +#define LTV_VSPL_ACTIVE_LOW (0 << 15)
11934 +#define LTV_VSPL_ACTIVE_HIGH (1 << 15)
11935 +#define LTV_HSPL_ACTIVE_LOW (0 << 14)
11936 +#define LTV_HSPL_ACTIVE_HIGH (1 << 14)
11937 +#define LTV_DPL_SAMPLE_RISING (0 << 13)
11938 +#define LTV_DPL_SAMPLE_FALLING (1 << 13)
11939 +#define LTV_EPL_ACTIVE_LOW (0 << 12)
11940 +#define LTV_EPL_ACTIVE_HIGH (1 << 12)
11941 +#define LTV_SS_LEFT_TO_RIGHT (0 << 8)
11942 +#define LTV_SS_RIGHT_TO_LEFT (1 << 8)
11943 +#define LTV_STB (1 << 1)
11944 +
11945 +/* Bit definitions for LTV_GATECTL1 */
11946 +#define LTV_CLW(x) (((x) & 0x0007) << 12)
11947 +#define LTV_GAON (1 << 5)
11948 +#define LTV_SDR (1 << 3)
11949 +
11950 +/* Bit definitions for LTV_GATECTL2 */
11951 +#define LTV_NW_INV_FRAME (0 << 14)
11952 +#define LTV_NW_INV_1LINE (1 << 14)
11953 +#define LTV_NW_INV_2LINE (2 << 14)
11954 +#define LTV_DSC (1 << 12)
11955 +#define LTV_GIF (1 << 8)
11956 +#define LTV_FHN (1 << 7)
11957 +#define LTV_FTI(x) (((x) & 0x0003) << 4)
11958 +#define LTV_FWI(x) (((x) & 0x0003) << 0)
11959 +
11960 +/* Bit definitions for LTV_SOTCTL */
11961 +#define LTV_SDT(x) (((x) & 0x0007) << 10)
11962 +#define LTV_EQ(x) (((x) & 0x0007) << 2)
11963 +
11964 +/* Bit definitions for LTV_PWRCTL1 */
11965 +#define LTV_VCOM_DISABLE (1 << 14)
11966 +#define LTV_VCOMOUT_ENABLE (1 << 11)
11967 +#define LTV_POWER_ON (1 << 9)
11968 +#define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */
11969 +#define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */
11970 +
11971 +/* Bit definitions for LTV_PWRCTL2 */
11972 +#define LTV_VCOML_ENABLE (1 << 13)
11973 +#define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */
11974 +#define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */
11975 +
11976 +#endif /* __LTV350QV_H */
11977 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/Makefile linux-avr32.git/drivers/video/backlight/Makefile
11978 --- linux-2.6.22.1/drivers/video/backlight/Makefile 2007-07-10 20:56:30.000000000 +0200
11979 +++ linux-avr32.git/drivers/video/backlight/Makefile 2007-07-12 14:00:20.000000000 +0200
11980 @@ -1,6 +1,8 @@
11981 # Backlight & LCD drivers
11982
11983 obj-$(CONFIG_LCD_CLASS_DEVICE) += lcd.o
11984 +obj-$(CONFIG_LCD_LTV350QV) += ltv350qv.o
11985 +
11986 obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
11987 obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
11988 obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
11989 diff -x .git -Nur linux-2.6.22.1/drivers/video/Kconfig linux-avr32.git/drivers/video/Kconfig
11990 --- linux-2.6.22.1/drivers/video/Kconfig 2007-07-10 20:56:30.000000000 +0200
11991 +++ linux-avr32.git/drivers/video/Kconfig 2007-07-12 14:00:20.000000000 +0200
11992 @@ -849,6 +849,16 @@
11993 Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
11994 to let frame buffer in external SDRAM.
11995
11996 +config FB_ATMEL_STN
11997 + bool "Use a STN display with AT91/AT32 LCD Controller"
11998 + depends on FB_ATMEL && ARCH_AT91SAM9261
11999 + default n
12000 + help
12001 + Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
12002 + Controller. Say N if you want to connect a TFT.
12003 +
12004 + If unsure, say N.
12005 +
12006 config FB_NVIDIA
12007 tristate "nVidia Framebuffer Support"
12008 depends on FB && PCI
12009 diff -x .git -Nur linux-2.6.22.1/include/asm-arm/arch-at91/board.h linux-avr32.git/include/asm-arm/arch-at91/board.h
12010 --- linux-2.6.22.1/include/asm-arm/arch-at91/board.h 2007-07-10 20:56:30.000000000 +0200
12011 +++ linux-avr32.git/include/asm-arm/arch-at91/board.h 2007-07-12 14:00:26.000000000 +0200
12012 @@ -64,6 +64,7 @@
12013
12014 /* Ethernet (EMAC & MACB) */
12015 struct at91_eth_data {
12016 + u32 phy_mask;
12017 u8 phy_irq_pin; /* PHY IRQ */
12018 u8 is_rmii; /* using RMII interface? */
12019 };
12020 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/board.h linux-avr32.git/include/asm-avr32/arch-at32ap/board.h
12021 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/board.h 2007-07-10 20:56:30.000000000 +0200
12022 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/board.h 2007-07-12 14:00:26.000000000 +0200
12023 @@ -6,6 +6,8 @@
12024
12025 #include <linux/types.h>
12026
12027 +#define GPIO_PIN_NONE (-1)
12028 +
12029 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
12030 void at32_add_system_devices(void);
12031
12032 @@ -21,6 +23,7 @@
12033 struct platform_device *at32_add_device_usart(unsigned int id);
12034
12035 struct eth_platform_data {
12036 + u32 phy_mask;
12037 u8 is_rmii;
12038 };
12039 struct platform_device *
12040 @@ -30,9 +33,41 @@
12041 struct platform_device *
12042 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
12043
12044 +struct platform_device *at32_add_device_twi(unsigned int id);
12045 +
12046 +struct mci_platform_data {
12047 + int detect_pin;
12048 + int wp_pin;
12049 +};
12050 +struct platform_device *
12051 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
12052 +
12053 +struct usba_platform_data {
12054 + int vbus_pin;
12055 +};
12056 +struct platform_device *
12057 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
12058 +
12059 struct atmel_lcdfb_info;
12060 struct platform_device *
12061 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
12062 unsigned long fbmem_start, unsigned long fbmem_len);
12063
12064 +struct platform_device *at32_add_device_ac97c(unsigned int id);
12065 +struct platform_device *at32_add_device_abdac(unsigned int id);
12066 +
12067 +/* depending on what's hooked up, not all SSC pins will be used */
12068 +#define ATMEL_SSC_TK 0x01
12069 +#define ATMEL_SSC_TF 0x02
12070 +#define ATMEL_SSC_TD 0x04
12071 +#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
12072 +
12073 +#define ATMEL_SSC_RK 0x10
12074 +#define ATMEL_SSC_RF 0x20
12075 +#define ATMEL_SSC_RD 0x40
12076 +#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
12077 +
12078 +struct platform_device *
12079 +at32_add_device_ssc(unsigned int id, unsigned int flags);
12080 +
12081 #endif /* __ASM_ARCH_BOARD_H */
12082 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/portmux.h linux-avr32.git/include/asm-avr32/arch-at32ap/portmux.h
12083 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/portmux.h 2007-07-10 20:56:30.000000000 +0200
12084 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/portmux.h 2007-07-12 14:00:26.000000000 +0200
12085 @@ -25,4 +25,16 @@
12086 void at32_select_gpio(unsigned int pin, unsigned long flags);
12087 void at32_reserve_pin(unsigned int pin);
12088
12089 +#ifdef CONFIG_GPIO_DEV
12090 +
12091 +/* Gang allocators and accessors; used by the GPIO /dev driver */
12092 +int at32_gpio_port_is_valid(unsigned int port);
12093 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
12094 +void at32_deselect_pins(unsigned int port, u32 pins);
12095 +
12096 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
12097 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
12098 +
12099 +#endif /* CONFIG_GPIO_DEV */
12100 +
12101 #endif /* __ASM_ARCH_PORTMUX_H__ */
12102 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/sm.h linux-avr32.git/include/asm-avr32/arch-at32ap/sm.h
12103 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/sm.h 2007-07-10 20:56:30.000000000 +0200
12104 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/sm.h 1970-01-01 01:00:00.000000000 +0100
12105 @@ -1,27 +0,0 @@
12106 -/*
12107 - * AT32 System Manager interface.
12108 - *
12109 - * Copyright (C) 2006 Atmel Corporation
12110 - *
12111 - * This program is free software; you can redistribute it and/or modify
12112 - * it under the terms of the GNU General Public License version 2 as
12113 - * published by the Free Software Foundation.
12114 - */
12115 -#ifndef __ASM_AVR32_AT32_SM_H__
12116 -#define __ASM_AVR32_AT32_SM_H__
12117 -
12118 -struct irq_chip;
12119 -struct platform_device;
12120 -
12121 -struct at32_sm {
12122 - spinlock_t lock;
12123 - void __iomem *regs;
12124 - struct irq_chip *eim_chip;
12125 - unsigned int eim_first_irq;
12126 - struct platform_device *pdev;
12127 -};
12128 -
12129 -extern struct platform_device at32_sm_device;
12130 -extern struct at32_sm system_manager;
12131 -
12132 -#endif /* __ASM_AVR32_AT32_SM_H__ */
12133 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/dma-controller.h linux-avr32.git/include/asm-avr32/dma-controller.h
12134 --- linux-2.6.22.1/include/asm-avr32/dma-controller.h 1970-01-01 01:00:00.000000000 +0100
12135 +++ linux-avr32.git/include/asm-avr32/dma-controller.h 2007-06-06 11:34:11.000000000 +0200
12136 @@ -0,0 +1,166 @@
12137 +/*
12138 + * Copyright (C) 2005-2006 Atmel Corporation
12139 + *
12140 + * This program is free software; you can redistribute it and/or modify
12141 + * it under the terms of the GNU General Public License version 2 as
12142 + * published by the Free Software Foundation.
12143 + */
12144 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
12145 +#define __ASM_AVR32_DMA_CONTROLLER_H
12146 +
12147 +#include <linux/device.h>
12148 +
12149 +#define DMA_DIR_MEM_TO_MEM 0x0000
12150 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
12151 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
12152 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
12153 +
12154 +#define DMA_WIDTH_8BIT 0
12155 +#define DMA_WIDTH_16BIT 1
12156 +#define DMA_WIDTH_32BIT 2
12157 +
12158 +struct dma_request {
12159 + struct dma_controller *dmac;
12160 + struct list_head list;
12161 +
12162 + unsigned short channel;
12163 +
12164 + void (*xfer_complete)(struct dma_request *req);
12165 + void (*block_complete)(struct dma_request *req);
12166 + void (*error)(struct dma_request *req);
12167 +};
12168 +
12169 +struct dma_request_sg {
12170 + struct dma_request req;
12171 +
12172 + int nr_sg;
12173 + struct scatterlist *sg;
12174 + unsigned long block_size;
12175 + unsigned int nr_blocks;
12176 +
12177 + dma_addr_t data_reg;
12178 + unsigned short periph_id;
12179 +
12180 + unsigned char direction;
12181 + unsigned char width;
12182 +};
12183 +#define to_dma_request_sg(_req) \
12184 + container_of(_req, struct dma_request_sg, req)
12185 +
12186 +struct dma_request_cyclic {
12187 + struct dma_request req;
12188 +
12189 + int periods;
12190 + unsigned long buffer_size;
12191 +
12192 + dma_addr_t buffer_start;
12193 + dma_addr_t data_reg;
12194 +
12195 + unsigned short periph_id;
12196 + unsigned char direction;
12197 + unsigned char width;
12198 +
12199 + void *dev_id;
12200 +};
12201 +#define to_dma_request_cyclic(_req) \
12202 + container_of(_req, struct dma_request_cyclic, req)
12203 +
12204 +struct dma_request_memcpy {
12205 + struct dma_request req;
12206 +
12207 + dma_addr_t src_addr;
12208 + unsigned int src_width;
12209 + unsigned int src_stride;
12210 +
12211 + dma_addr_t dst_addr;
12212 + unsigned int dst_width;
12213 + unsigned int dst_stride;
12214 +
12215 + size_t length;
12216 +
12217 + unsigned short src_reverse:1;
12218 + unsigned short dst_reverse:1;
12219 +};
12220 +#define to_dma_request_memcpy(_req) \
12221 + container_of(_req, struct dma_request_memcpy, req)
12222 +
12223 +struct dma_controller {
12224 + struct list_head list;
12225 + int id;
12226 + struct device *dev;
12227 +
12228 + int (*alloc_channel)(struct dma_controller *dmac);
12229 + void (*release_channel)(struct dma_controller *dmac,
12230 + int channel);
12231 + int (*prepare_request_sg)(struct dma_controller *dmac,
12232 + struct dma_request_sg *req);
12233 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
12234 + struct dma_request_cyclic *req);
12235 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
12236 + struct dma_request_memcpy *req);
12237 + int (*start_request)(struct dma_controller *dmac,
12238 + unsigned int channel);
12239 + int (*stop_request)(struct dma_controller *dmac,
12240 + unsigned int channel);
12241 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
12242 + unsigned int channel);
12243 +};
12244 +
12245 +static inline int
12246 +dma_alloc_channel(struct dma_controller *dmac)
12247 +{
12248 + return dmac->alloc_channel(dmac);
12249 +}
12250 +
12251 +static inline void
12252 +dma_release_channel(struct dma_controller *dmac, int chan)
12253 +{
12254 + dmac->release_channel(dmac, chan);
12255 +}
12256 +
12257 +static inline int
12258 +dma_prepare_request_sg(struct dma_controller *dmac,
12259 + struct dma_request_sg *req)
12260 +{
12261 + return dmac->prepare_request_sg(dmac, req);
12262 +}
12263 +
12264 +static inline int
12265 +dma_prepare_request_cyclic(struct dma_controller *dmac,
12266 + struct dma_request_cyclic *req)
12267 +{
12268 + return dmac->prepare_request_cyclic(dmac, req);
12269 +}
12270 +
12271 +static inline int
12272 +dma_prepare_request_memcpy(struct dma_controller *dmac,
12273 + struct dma_request_memcpy *req)
12274 +{
12275 + return dmac->prepare_request_memcpy(dmac, req);
12276 +}
12277 +
12278 +static inline int
12279 +dma_start_request(struct dma_controller *dmac,
12280 + unsigned int channel)
12281 +{
12282 + return dmac->start_request(dmac, channel);
12283 +}
12284 +
12285 +static inline int
12286 +dma_stop_request(struct dma_controller *dmac,
12287 + unsigned int channel)
12288 +{
12289 + return dmac->stop_request(dmac, channel);
12290 +}
12291 +
12292 +static inline dma_addr_t
12293 +dma_get_current_pos(struct dma_controller *dmac,
12294 + unsigned int channel)
12295 +{
12296 + return dmac->get_current_pos(dmac, channel);
12297 +}
12298 +
12299 +extern int register_dma_controller(struct dma_controller *dmac);
12300 +extern struct dma_controller *find_dma_controller(int id);
12301 +
12302 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
12303 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/unaligned.h linux-avr32.git/include/asm-avr32/unaligned.h
12304 --- linux-2.6.22.1/include/asm-avr32/unaligned.h 2007-07-10 20:56:30.000000000 +0200
12305 +++ linux-avr32.git/include/asm-avr32/unaligned.h 2007-07-12 14:00:26.000000000 +0200
12306 @@ -7,19 +7,10 @@
12307 * words, but halfwords must be halfword-aligned, and doublewords must
12308 * be word-aligned.
12309 *
12310 - * TODO: Make all this CPU-specific and optimize.
12311 + * However, swapped word loads must be word-aligned so we can't
12312 + * optimize word loads in general.
12313 */
12314
12315 -#include <linux/string.h>
12316 -
12317 -/* Use memmove here, so gcc does not insert a __builtin_memcpy. */
12318 -
12319 -#define get_unaligned(ptr) \
12320 - ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; })
12321 -
12322 -#define put_unaligned(val, ptr) \
12323 - ({ __typeof__(*(ptr)) __tmp = (val); \
12324 - memmove((ptr), &__tmp, sizeof(*(ptr))); \
12325 - (void)0; })
12326 +#include <asm-generic/unaligned.h>
12327
12328 #endif /* __ASM_AVR32_UNALIGNED_H */
12329 diff -x .git -Nur linux-2.6.22.1/include/linux/gpio_mouse.h linux-avr32.git/include/linux/gpio_mouse.h
12330 --- linux-2.6.22.1/include/linux/gpio_mouse.h 1970-01-01 01:00:00.000000000 +0100
12331 +++ linux-avr32.git/include/linux/gpio_mouse.h 2007-07-13 11:24:16.000000000 +0200
12332 @@ -0,0 +1,61 @@
12333 +/*
12334 + * Driver for simulating a mouse on GPIO lines.
12335 + *
12336 + * Copyright (C) 2007 Atmel Corporation
12337 + *
12338 + * This program is free software; you can redistribute it and/or modify
12339 + * it under the terms of the GNU General Public License version 2 as
12340 + * published by the Free Software Foundation.
12341 + */
12342 +
12343 +#ifndef _GPIO_MOUSE_H
12344 +#define _GPIO_MOUSE_H
12345 +
12346 +#define GPIO_MOUSE_POLARITY_ACT_HIGH 0x00
12347 +#define GPIO_MOUSE_POLARITY_ACT_LOW 0x01
12348 +
12349 +#define GPIO_MOUSE_PIN_UP 0
12350 +#define GPIO_MOUSE_PIN_DOWN 1
12351 +#define GPIO_MOUSE_PIN_LEFT 2
12352 +#define GPIO_MOUSE_PIN_RIGHT 3
12353 +#define GPIO_MOUSE_PIN_BLEFT 4
12354 +#define GPIO_MOUSE_PIN_BMIDDLE 5
12355 +#define GPIO_MOUSE_PIN_BRIGHT 6
12356 +#define GPIO_MOUSE_PIN_MAX 7
12357 +
12358 +/**
12359 + * struct gpio_mouse_platform_data
12360 + * @scan_ms: integer in ms specifying the scan periode.
12361 + * @polarity: Pin polarity, active high or low.
12362 + * @up: GPIO line for up value.
12363 + * @down: GPIO line for down value.
12364 + * @left: GPIO line for left value.
12365 + * @right: GPIO line for right value.
12366 + * @bleft: GPIO line for left button.
12367 + * @bmiddle: GPIO line for middle button.
12368 + * @bright: GPIO line for right button.
12369 + *
12370 + * This struct must be added to the platform_device in the board code.
12371 + * It is used by the gpio_mouse driver to setup GPIO lines and to
12372 + * calculate mouse movement.
12373 + */
12374 +struct gpio_mouse_platform_data {
12375 + int scan_ms;
12376 + int polarity;
12377 +
12378 + union {
12379 + struct {
12380 + int up;
12381 + int down;
12382 + int left;
12383 + int right;
12384 +
12385 + int bleft;
12386 + int bmiddle;
12387 + int bright;
12388 + };
12389 + int pins[GPIO_MOUSE_PIN_MAX];
12390 + };
12391 +};
12392 +
12393 +#endif /* _GPIO_MOUSE_H */
12394 diff -x .git -Nur linux-2.6.22.1/include/linux/leds.h linux-avr32.git/include/linux/leds.h
12395 --- linux-2.6.22.1/include/linux/leds.h 2007-07-10 20:56:30.000000000 +0200
12396 +++ linux-avr32.git/include/linux/leds.h 2007-07-12 14:00:30.000000000 +0200
12397 @@ -110,4 +110,18 @@
12398 #define ledtrig_ide_activity() do {} while(0)
12399 #endif
12400
12401 +/* For the leds-gpio driver */
12402 +struct gpio_led {
12403 + const char *name;
12404 + char *default_trigger;
12405 + unsigned gpio;
12406 + u8 active_low;
12407 +};
12408 +
12409 +struct gpio_led_platform_data {
12410 + int num_leds;
12411 + struct gpio_led *leds;
12412 +};
12413 +
12414 +
12415 #endif /* __LINUX_LEDS_H_INCLUDED */
12416 diff -x .git -Nur linux-2.6.22.1/include/linux/usb/gadgetfs.h linux-avr32.git/include/linux/usb/gadgetfs.h
12417 --- linux-2.6.22.1/include/linux/usb/gadgetfs.h 1970-01-01 01:00:00.000000000 +0100
12418 +++ linux-avr32.git/include/linux/usb/gadgetfs.h 2007-07-12 14:00:31.000000000 +0200
12419 @@ -0,0 +1,81 @@
12420 +#ifndef __LINUX_USB_GADGETFS_H
12421 +#define __LINUX_USB_GADGETFS_H
12422 +
12423 +#include <asm/types.h>
12424 +#include <asm/ioctl.h>
12425 +
12426 +#include <linux/usb/ch9.h>
12427 +
12428 +/*
12429 + * Filesystem based user-mode API to USB Gadget controller hardware
12430 + *
12431 + * Other than ep0 operations, most things are done by read() and write()
12432 + * on endpoint files found in one directory. They are configured by
12433 + * writing descriptors, and then may be used for normal stream style
12434 + * i/o requests. When ep0 is configured, the device can enumerate;
12435 + * when it's closed, the device disconnects from usb. Operations on
12436 + * ep0 require ioctl() operations.
12437 + *
12438 + * Configuration and device descriptors get written to /dev/gadget/$CHIP,
12439 + * which may then be used to read usb_gadgetfs_event structs. The driver
12440 + * may activate endpoints as it handles SET_CONFIGURATION setup events,
12441 + * or earlier; writing endpoint descriptors to /dev/gadget/$ENDPOINT
12442 + * then performing data transfers by reading or writing.
12443 + */
12444 +
12445 +/*
12446 + * Events are delivered on the ep0 file descriptor, when the user mode driver
12447 + * reads from this file descriptor after writing the descriptors. Don't
12448 + * stop polling this descriptor.
12449 + */
12450 +
12451 +enum usb_gadgetfs_event_type {
12452 + GADGETFS_NOP = 0,
12453 +
12454 + GADGETFS_CONNECT,
12455 + GADGETFS_DISCONNECT,
12456 + GADGETFS_SETUP,
12457 + GADGETFS_SUSPEND,
12458 + // and likely more !
12459 +};
12460 +
12461 +/* NOTE: this structure must stay the same size and layout on
12462 + * both 32-bit and 64-bit kernels.
12463 + */
12464 +struct usb_gadgetfs_event {
12465 + union {
12466 + // NOP, DISCONNECT, SUSPEND: nothing
12467 + // ... some hardware can't report disconnection
12468 +
12469 + // CONNECT: just the speed
12470 + enum usb_device_speed speed;
12471 +
12472 + // SETUP: packet; DATA phase i/o precedes next event
12473 + // (setup.bmRequestType & USB_DIR_IN) flags direction
12474 + // ... includes SET_CONFIGURATION, SET_INTERFACE
12475 + struct usb_ctrlrequest setup;
12476 + } u;
12477 + enum usb_gadgetfs_event_type type;
12478 +};
12479 +
12480 +
12481 +/* endpoint ioctls */
12482 +
12483 +/* IN transfers may be reported to the gadget driver as complete
12484 + * when the fifo is loaded, before the host reads the data;
12485 + * OUT transfers may be reported to the host's "client" driver as
12486 + * complete when they're sitting in the FIFO unread.
12487 + * THIS returns how many bytes are "unclaimed" in the endpoint fifo
12488 + * (needed for precise fault handling, when the hardware allows it)
12489 + */
12490 +#define GADGETFS_FIFO_STATUS _IO('g',1)
12491 +
12492 +/* discards any unclaimed data in the fifo. */
12493 +#define GADGETFS_FIFO_FLUSH _IO('g',2)
12494 +
12495 +/* resets endpoint halt+toggle; used to implement set_interface.
12496 + * some hardware (like pxa2xx) can't support this.
12497 + */
12498 +#define GADGETFS_CLEAR_HALT _IO('g',3)
12499 +
12500 +#endif /* __LINUX_USB_GADGETFS_H */
12501 diff -x .git -Nur linux-2.6.22.1/include/linux/usb/Kbuild linux-avr32.git/include/linux/usb/Kbuild
12502 --- linux-2.6.22.1/include/linux/usb/Kbuild 2007-07-10 20:56:30.000000000 +0200
12503 +++ linux-avr32.git/include/linux/usb/Kbuild 2007-07-12 14:00:31.000000000 +0200
12504 @@ -1,5 +1,6 @@
12505 unifdef-y += audio.h
12506 unifdef-y += cdc.h
12507 unifdef-y += ch9.h
12508 +unifdef-y += gadgetfs.h
12509 unifdef-y += midi.h
12510
12511 diff -x .git -Nur linux-2.6.22.1/include/linux/usb_gadgetfs.h linux-avr32.git/include/linux/usb_gadgetfs.h
12512 --- linux-2.6.22.1/include/linux/usb_gadgetfs.h 2007-07-10 20:56:30.000000000 +0200
12513 +++ linux-avr32.git/include/linux/usb_gadgetfs.h 1970-01-01 01:00:00.000000000 +0100
12514 @@ -1,75 +0,0 @@
12515 -
12516 -#include <asm/types.h>
12517 -#include <asm/ioctl.h>
12518 -
12519 -#include <linux/usb/ch9.h>
12520 -
12521 -/*
12522 - * Filesystem based user-mode API to USB Gadget controller hardware
12523 - *
12524 - * Almost everything can be done with only read and write operations,
12525 - * on endpoint files found in one directory. They are configured by
12526 - * writing descriptors, and then may be used for normal stream style
12527 - * i/o requests. When ep0 is configured, the device can enumerate;
12528 - * when it's closed, the device disconnects from usb.
12529 - *
12530 - * Configuration and device descriptors get written to /dev/gadget/$CHIP,
12531 - * which may then be used to read usb_gadgetfs_event structs. The driver
12532 - * may activate endpoints as it handles SET_CONFIGURATION setup events,
12533 - * or earlier; writing endpoint descriptors to /dev/gadget/$ENDPOINT
12534 - * then performing data transfers by reading or writing.
12535 - */
12536 -
12537 -/*
12538 - * Events are delivered on the ep0 file descriptor, if the user mode driver
12539 - * reads from this file descriptor after writing the descriptors. Don't
12540 - * stop polling this descriptor, if you write that kind of driver.
12541 - */
12542 -
12543 -enum usb_gadgetfs_event_type {
12544 - GADGETFS_NOP = 0,
12545 -
12546 - GADGETFS_CONNECT,
12547 - GADGETFS_DISCONNECT,
12548 - GADGETFS_SETUP,
12549 - GADGETFS_SUSPEND,
12550 - // and likely more !
12551 -};
12552 -
12553 -struct usb_gadgetfs_event {
12554 - enum usb_gadgetfs_event_type type;
12555 - union {
12556 - // NOP, DISCONNECT, SUSPEND: nothing
12557 - // ... some hardware can't report disconnection
12558 -
12559 - // CONNECT: just the speed
12560 - enum usb_device_speed speed;
12561 -
12562 - // SETUP: packet; DATA phase i/o precedes next event
12563 - // (setup.bmRequestType & USB_DIR_IN) flags direction
12564 - // ... includes SET_CONFIGURATION, SET_INTERFACE
12565 - struct usb_ctrlrequest setup;
12566 - } u;
12567 -};
12568 -
12569 -
12570 -/* endpoint ioctls */
12571 -
12572 -/* IN transfers may be reported to the gadget driver as complete
12573 - * when the fifo is loaded, before the host reads the data;
12574 - * OUT transfers may be reported to the host's "client" driver as
12575 - * complete when they're sitting in the FIFO unread.
12576 - * THIS returns how many bytes are "unclaimed" in the endpoint fifo
12577 - * (needed for precise fault handling, when the hardware allows it)
12578 - */
12579 -#define GADGETFS_FIFO_STATUS _IO('g',1)
12580 -
12581 -/* discards any unclaimed data in the fifo. */
12582 -#define GADGETFS_FIFO_FLUSH _IO('g',2)
12583 -
12584 -/* resets endpoint halt+toggle; used to implement set_interface.
12585 - * some hardware (like pxa2xx) can't support this.
12586 - */
12587 -#define GADGETFS_CLEAR_HALT _IO('g',3)
12588 -
12589 -
12590 diff -x .git -Nur linux-2.6.22.1/init/do_mounts.c linux-avr32.git/init/do_mounts.c
12591 --- linux-2.6.22.1/init/do_mounts.c 2007-07-10 20:56:30.000000000 +0200
12592 +++ linux-avr32.git/init/do_mounts.c 2007-07-12 14:00:31.000000000 +0200
12593 @@ -25,6 +25,7 @@
12594 int root_mountflags = MS_RDONLY | MS_SILENT;
12595 char * __initdata root_device_name;
12596 static char __initdata saved_root_name[64];
12597 +int __initdata root_wait;
12598
12599 dev_t ROOT_DEV;
12600
12601 @@ -216,6 +217,14 @@
12602
12603 __setup("root=", root_dev_setup);
12604
12605 +static int __init rootwait_setup(char *line)
12606 +{
12607 + root_wait = simple_strtol(line,NULL,0);
12608 + return 1;
12609 +}
12610 +
12611 +__setup("rootwait=", rootwait_setup);
12612 +
12613 static char * __initdata root_mount_data;
12614 static int __init root_data_setup(char *str)
12615 {
12616 @@ -438,11 +447,24 @@
12617 root_device_name += 5;
12618 }
12619
12620 - is_floppy = MAJOR(ROOT_DEV) == FLOPPY_MAJOR;
12621 -
12622 if (initrd_load())
12623 goto out;
12624
12625 + /* wait for any asynchronous scanning to complete */
12626 + if ((ROOT_DEV == 0) && root_wait) {
12627 + printk(KERN_INFO "Waiting for root device %s...\n",
12628 + saved_root_name);
12629 + do {
12630 + while (driver_probe_done() != 0)
12631 + msleep(100);
12632 + ROOT_DEV = name_to_dev_t(saved_root_name);
12633 + if (ROOT_DEV == 0)
12634 + msleep(100);
12635 + } while (ROOT_DEV == 0);
12636 + }
12637 +
12638 + is_floppy = MAJOR(ROOT_DEV) == FLOPPY_MAJOR;
12639 +
12640 if (is_floppy && rd_doload && rd_load_disk(0))
12641 ROOT_DEV = Root_RAM0;
12642
12643 diff -x .git -Nur linux-2.6.22.1/MAINTAINERS linux-avr32.git/MAINTAINERS
12644 --- linux-2.6.22.1/MAINTAINERS 2007-07-10 20:56:30.000000000 +0200
12645 +++ linux-avr32.git/MAINTAINERS 2007-07-12 13:59:48.000000000 +0200
12646 @@ -674,6 +674,13 @@
12647 M: hskinnemoen@atmel.com
12648 S: Supported
12649
12650 +ATMEL USBA UDC DRIVER
12651 +P: Haavard Skinnemoen
12652 +M: hskinnemoen@atmel.com
12653 +L: kernel@avr32linux.org
12654 +W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
12655 +S: Supported
12656 +
12657 ATMEL WIRELESS DRIVER
12658 P: Simon Kelley
12659 M: simon@thekelleys.org.uk
12660 diff -x .git -Nur linux-2.6.22.1/scripts/checkstack.pl linux-avr32.git/scripts/checkstack.pl
12661 --- linux-2.6.22.1/scripts/checkstack.pl 2007-07-10 20:56:30.000000000 +0200
12662 +++ linux-avr32.git/scripts/checkstack.pl 2007-06-06 11:34:14.000000000 +0200
12663 @@ -12,6 +12,7 @@
12664 # sh64 port by Paul Mundt
12665 # Random bits by Matt Mackall <mpm@selenic.com>
12666 # M68k port by Geert Uytterhoeven and Andreas Schwab
12667 +# AVR32 port by Haavard Skinnemoen <hskinnemoen@atmel.com>
12668 #
12669 # Usage:
12670 # objdump -d vmlinux | stackcheck.pl [arch]
12671 @@ -37,6 +38,10 @@
12672 if ($arch eq 'arm') {
12673 #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
12674 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
12675 + } elsif ($arch eq 'avr32') {
12676 + #8000008a: 20 1d sub sp,4
12677 + #80000ca8: fa cd 05 b0 sub sp,sp,1456
12678 + $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
12679 } elsif ($arch =~ /^i[3456]86$/) {
12680 #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
12681 $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
Personal OpenWRT clone
This page took 0.575899 seconds and 5 git commands to generate.