target/linux/xburst/patches-2.6.35/050-nand.patch

   1 From c09d9002953c1182843050df1d4c639dea4af7f6 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 17 Jul 2010 11:15:29 +0000
   4 Subject: [PATCH] MTD: Nand: Add JZ4740 NAND driver
   5
   6 Add support for the NAND controller on JZ4740 SoCs.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Cc: David Woodhouse <dwmw2@infradead.org>
  10 Cc: linux-mtd@lists.infradead.org
  11 Cc: linux-mips@linux-mips.org
  12 Cc: linux-kernel@vger.kernel.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/1470/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/include/asm/mach-jz4740/jz4740_nand.h |   34 ++
  17  drivers/mtd/nand/Kconfig                        |    6 +
  18  drivers/mtd/nand/Makefile                       |    1 +
  19  drivers/mtd/nand/jz4740_nand.c                  |  516 +++++++++++++++++++++++
  20  4 files changed, 557 insertions(+), 0 deletions(-)
  21  create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_nand.h
  22  create mode 100644 drivers/mtd/nand/jz4740_nand.c
  23
  24 --- /dev/null
  25 +++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
  26 @@ -0,0 +1,34 @@
  27 +/*
  28 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  29 + *  JZ4740 SoC NAND controller driver
  30 + *
  31 + *  This program is free software; you can redistribute         it and/or modify it
  32 + *  under  the terms of         the GNU General  Public License as published by the
  33 + *  Free Software Foundation;  either version 2 of the License, or (at your
  34 + *  option) any later version.
  35 + *
  36 + *  You should have received a copy of the  GNU General Public License along
  37 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  38 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  39 + *
  40 + */
  41 +
  42 +#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
  43 +#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
  44 +
  45 +#include <linux/mtd/nand.h>
  46 +#include <linux/mtd/partitions.h>
  47 +
  48 +struct jz_nand_platform_data {
  49 +       int                     num_partitions;
  50 +       struct mtd_partition    *partitions;
  51 +
  52 +       struct nand_ecclayout   *ecc_layout;
  53 +
  54 +       unsigned int busy_gpio;
  55 +
  56 +       void (*ident_callback)(struct platform_device *, struct nand_chip *,
  57 +                               struct mtd_partition **, int *num_partitions);
  58 +};
  59 +
  60 +#endif
  61 --- a/drivers/mtd/nand/Kconfig
  62 +++ b/drivers/mtd/nand/Kconfig
  63 @@ -526,4 +526,10 @@ config MTD_NAND_NUC900
  64           This enables the driver for the NAND Flash on evaluation board based
  65           on w90p910 / NUC9xx.
  66
  67 +config MTD_NAND_JZ4740
  68 +       tristate "Support for JZ4740 SoC NAND controller"
  69 +       depends on MACH_JZ4740
  70 +       help
  71 +               Enables support for NAND Flash on JZ4740 SoC based boards.
  72 +
  73  endif # MTD_NAND
  74 --- a/drivers/mtd/nand/Makefile
  75 +++ b/drivers/mtd/nand/Makefile
  76 @@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK)                += nomad
  77  obj-$(CONFIG_MTD_NAND_BCM_UMI)         += bcm_umi_nand.o nand_bcm_umi.o
  78  obj-$(CONFIG_MTD_NAND_MPC5121_NFC)     += mpc5121_nfc.o
  79  obj-$(CONFIG_MTD_NAND_RICOH)           += r852.o
  80 +obj-$(CONFIG_MTD_NAND_JZ4740)          += jz4740_nand.o
  81
  82  nand-objs := nand_base.o nand_bbt.o
  83 --- /dev/null
  84 +++ b/drivers/mtd/nand/jz4740_nand.c
  85 @@ -0,0 +1,516 @@
  86 +/*
  87 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  88 + *  JZ4740 SoC NAND controller driver
  89 + *
  90 + *  This program is free software; you can redistribute it and/or modify it
  91 + *  under  the terms of the GNU General  Public License as published by the
  92 + *  Free Software Foundation;  either version 2 of the License, or (at your
  93 + *  option) any later version.
  94 + *
  95 + *  You should have received a copy of the GNU General Public License along
  96 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  97 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  98 + *
  99 + */
 100 +
 101 +#include <linux/ioport.h>
 102 +#include <linux/kernel.h>
 103 +#include <linux/module.h>
 104 +#include <linux/platform_device.h>
 105 +#include <linux/slab.h>
 106 +
 107 +#include <linux/mtd/mtd.h>
 108 +#include <linux/mtd/nand.h>
 109 +#include <linux/mtd/partitions.h>
 110 +
 111 +#include <linux/gpio.h>
 112 +
 113 +#include <asm/mach-jz4740/jz4740_nand.h>
 114 +
 115 +#define JZ_REG_NAND_CTRL       0x50
 116 +#define JZ_REG_NAND_ECC_CTRL   0x100
 117 +#define JZ_REG_NAND_DATA       0x104
 118 +#define JZ_REG_NAND_PAR0       0x108
 119 +#define JZ_REG_NAND_PAR1       0x10C
 120 +#define JZ_REG_NAND_PAR2       0x110
 121 +#define JZ_REG_NAND_IRQ_STAT   0x114
 122 +#define JZ_REG_NAND_IRQ_CTRL   0x118
 123 +#define JZ_REG_NAND_ERR(x)     (0x11C + ((x) << 2))
 124 +
 125 +#define JZ_NAND_ECC_CTRL_PAR_READY     BIT(4)
 126 +#define JZ_NAND_ECC_CTRL_ENCODING      BIT(3)
 127 +#define JZ_NAND_ECC_CTRL_RS            BIT(2)
 128 +#define JZ_NAND_ECC_CTRL_RESET         BIT(1)
 129 +#define JZ_NAND_ECC_CTRL_ENABLE                BIT(0)
 130 +
 131 +#define JZ_NAND_STATUS_ERR_COUNT       (BIT(31) | BIT(30) | BIT(29))
 132 +#define JZ_NAND_STATUS_PAD_FINISH      BIT(4)
 133 +#define JZ_NAND_STATUS_DEC_FINISH      BIT(3)
 134 +#define JZ_NAND_STATUS_ENC_FINISH      BIT(2)
 135 +#define JZ_NAND_STATUS_UNCOR_ERROR     BIT(1)
 136 +#define JZ_NAND_STATUS_ERROR           BIT(0)
 137 +
 138 +#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
 139 +#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
 140 +
 141 +#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
 142 +#define JZ_NAND_MEM_CMD_OFFSET 0x08000
 143 +
 144 +struct jz_nand {
 145 +       struct mtd_info mtd;
 146 +       struct nand_chip chip;
 147 +       void __iomem *base;
 148 +       struct resource *mem;
 149 +
 150 +       void __iomem *bank_base;
 151 +       struct resource *bank_mem;
 152 +
 153 +       struct jz_nand_platform_data *pdata;
 154 +       bool is_reading;
 155 +};
 156 +
 157 +static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
 158 +{
 159 +       return container_of(mtd, struct jz_nand, mtd);
 160 +}
 161 +
 162 +static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
 163 +{
 164 +       struct jz_nand *nand = mtd_to_jz_nand(mtd);
 165 +       struct nand_chip *chip = mtd->priv;
 166 +       uint32_t reg;
 167 +
 168 +       if (ctrl & NAND_CTRL_CHANGE) {
 169 +               BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
 170 +               if (ctrl & NAND_ALE)
 171 +                       chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
 172 +               else if (ctrl & NAND_CLE)
 173 +                       chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
 174 +               else
 175 +                       chip->IO_ADDR_W = nand->bank_base;
 176 +
 177 +               reg = readl(nand->base + JZ_REG_NAND_CTRL);
 178 +               if (ctrl & NAND_NCE)
 179 +                       reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
 180 +               else
 181 +                       reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
 182 +               writel(reg, nand->base + JZ_REG_NAND_CTRL);
 183 +       }
 184 +       if (dat != NAND_CMD_NONE)
 185 +               writeb(dat, chip->IO_ADDR_W);
 186 +}
 187 +
 188 +static int jz_nand_dev_ready(struct mtd_info *mtd)
 189 +{
 190 +       struct jz_nand *nand = mtd_to_jz_nand(mtd);
 191 +       return gpio_get_value_cansleep(nand->pdata->busy_gpio);
 192 +}
 193 +
 194 +static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
 195 +{
 196 +       struct jz_nand *nand = mtd_to_jz_nand(mtd);
 197 +       uint32_t reg;
 198 +
 199 +       writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
 200 +       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 201 +
 202 +       reg |= JZ_NAND_ECC_CTRL_RESET;
 203 +       reg |= JZ_NAND_ECC_CTRL_ENABLE;
 204 +       reg |= JZ_NAND_ECC_CTRL_RS;
 205 +
 206 +       switch (mode) {
 207 +       case NAND_ECC_READ:
 208 +               reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
 209 +               nand->is_reading = true;
 210 +               break;
 211 +       case NAND_ECC_WRITE:
 212 +               reg |= JZ_NAND_ECC_CTRL_ENCODING;
 213 +               nand->is_reading = false;
 214 +               break;
 215 +       default:
 216 +               break;
 217 +       }
 218 +
 219 +       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 220 +}
 221 +
 222 +static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
 223 +       uint8_t *ecc_code)
 224 +{
 225 +       struct jz_nand *nand = mtd_to_jz_nand(mtd);
 226 +       uint32_t reg, status;
 227 +       int i;
 228 +       unsigned int timeout = 1000;
 229 +       static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
 230 +                                               0x8b, 0xff, 0xb7, 0x6f};
 231 +
 232 +       if (nand->is_reading)
 233 +               return 0;
 234 +
 235 +       do {
 236 +               status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 237 +       } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
 238 +
 239 +       if (timeout == 0)
 240 +           return -1;
 241 +
 242 +       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 243 +       reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 244 +       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 245 +
 246 +       for (i = 0; i < 9; ++i)
 247 +               ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
 248 +
 249 +       /* If the written data is completly 0xff, we also want to write 0xff as
 250 +        * ecc, otherwise we will get in trouble when doing subpage writes. */
 251 +       if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
 252 +               memset(ecc_code, 0xff, 9);
 253 +
 254 +       return 0;
 255 +}
 256 +
 257 +static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
 258 +{
 259 +       int offset = index & 0x7;
 260 +       uint16_t data;
 261 +
 262 +       index += (index >> 3);
 263 +
 264 +       data = dat[index];
 265 +       data |= dat[index+1] << 8;
 266 +
 267 +       mask ^= (data >> offset) & 0x1ff;
 268 +       data &= ~(0x1ff << offset);
 269 +       data |= (mask << offset);
 270 +
 271 +       dat[index] = data & 0xff;
 272 +       dat[index+1] = (data >> 8) & 0xff;
 273 +}
 274 +
 275 +static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
 276 +       uint8_t *read_ecc, uint8_t *calc_ecc)
 277 +{
 278 +       struct jz_nand *nand = mtd_to_jz_nand(mtd);
 279 +       int i, error_count, index;
 280 +       uint32_t reg, status, error;
 281 +       uint32_t t;
 282 +       unsigned int timeout = 1000;
 283 +
 284 +       t = read_ecc[0];
 285 +
 286 +       if (t == 0xff) {
 287 +               for (i = 1; i < 9; ++i)
 288 +                       t &= read_ecc[i];
 289 +
 290 +               t &= dat[0];
 291 +               t &= dat[nand->chip.ecc.size / 2];
 292 +               t &= dat[nand->chip.ecc.size - 1];
 293 +
 294 +               if (t == 0xff) {
 295 +                       for (i = 1; i < nand->chip.ecc.size - 1; ++i)
 296 +                               t &= dat[i];
 297 +                       if (t == 0xff)
 298 +                               return 0;
 299 +               }
 300 +       }
 301 +
 302 +       for (i = 0; i < 9; ++i)
 303 +               writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
 304 +
 305 +       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 306 +       reg |= JZ_NAND_ECC_CTRL_PAR_READY;
 307 +       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 308 +
 309 +       do {
 310 +               status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
 311 +       } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
 312 +
 313 +       if (timeout == 0)
 314 +           return -1;
 315 +
 316 +       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
 317 +       reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
 318 +       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
 319 +
 320 +       if (status & JZ_NAND_STATUS_ERROR) {
 321 +               if (status & JZ_NAND_STATUS_UNCOR_ERROR)
 322 +                       return -1;
 323 +
 324 +               error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
 325 +
 326 +               for (i = 0; i < error_count; ++i) {
 327 +                       error = readl(nand->base + JZ_REG_NAND_ERR(i));
 328 +                       index = ((error >> 16) & 0x1ff) - 1;
 329 +                       if (index >= 0 && index < 512)
 330 +                               jz_nand_correct_data(dat, index, error & 0x1ff);
 331 +               }
 332 +
 333 +               return error_count;
 334 +       }
 335 +
 336 +       return 0;
 337 +}
 338 +
 339 +
 340 +/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos
 341 + * handling. The ecc area is for 4k chips 72 bytes long and thus does not fit
 342 + * into the eccpos array. */
 343 +static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 344 +       struct nand_chip *chip, uint8_t *buf, int page)
 345 +{
 346 +       int i, eccsize = chip->ecc.size;
 347 +       int eccbytes = chip->ecc.bytes;
 348 +       int eccsteps = chip->ecc.steps;
 349 +       uint8_t *p = buf;
 350 +       unsigned int ecc_offset = chip->page_shift;
 351 +
 352 +       /* Read the OOB area first */
 353 +       chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 354 +       chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 355 +       chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 356 +
 357 +       for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 358 +               int stat;
 359 +
 360 +               chip->ecc.hwctl(mtd, NAND_ECC_READ);
 361 +               chip->read_buf(mtd, p, eccsize);
 362 +
 363 +               stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL);
 364 +               if (stat < 0)
 365 +                       mtd->ecc_stats.failed++;
 366 +               else
 367 +                       mtd->ecc_stats.corrected += stat;
 368 +       }
 369 +       return 0;
 370 +}
 371 +
 372 +/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */
 373 +static void jz_nand_write_page_hwecc(struct mtd_info *mtd,
 374 +       struct nand_chip *chip, const uint8_t *buf)
 375 +{
 376 +       int i, eccsize = chip->ecc.size;
 377 +       int eccbytes = chip->ecc.bytes;
 378 +       int eccsteps = chip->ecc.steps;
 379 +       const uint8_t *p = buf;
 380 +       unsigned int ecc_offset = chip->page_shift;
 381 +
 382 +       for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 383 +               chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 384 +               chip->write_buf(mtd, p, eccsize);
 385 +               chip->ecc.calculate(mtd, p, &chip->oob_poi[i]);
 386 +       }
 387 +
 388 +       chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 389 +}
 390 +
 391 +#ifdef CONFIG_MTD_CMDLINE_PARTS
 392 +static const char *part_probes[] = {"cmdline", NULL};
 393 +#endif
 394 +
 395 +static int jz_nand_ioremap_resource(struct platform_device *pdev,
 396 +       const char *name, struct resource **res, void __iomem **base)
 397 +{
 398 +       int ret;
 399 +
 400 +       *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 401 +       if (!*res) {
 402 +               dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
 403 +               ret = -ENXIO;
 404 +               goto err;
 405 +       }
 406 +
 407 +       *res = request_mem_region((*res)->start, resource_size(*res),
 408 +                               pdev->name);
 409 +       if (!*res) {
 410 +               dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
 411 +               ret = -EBUSY;
 412 +               goto err;
 413 +       }
 414 +
 415 +       *base = ioremap((*res)->start, resource_size(*res));
 416 +       if (!*base) {
 417 +               dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
 418 +               ret = -EBUSY;
 419 +               goto err_release_mem;
 420 +       }
 421 +
 422 +       return 0;
 423 +
 424 +err_release_mem:
 425 +       release_mem_region((*res)->start, resource_size(*res));
 426 +err:
 427 +       *res = NULL;
 428 +       *base = NULL;
 429 +       return ret;
 430 +}
 431 +
 432 +static int __devinit jz_nand_probe(struct platform_device *pdev)
 433 +{
 434 +       int ret;
 435 +       struct jz_nand *nand;
 436 +       struct nand_chip *chip;
 437 +       struct mtd_info *mtd;
 438 +       struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
 439 +#ifdef CONFIG_MTD_PARTITIONS
 440 +       struct mtd_partition *partition_info;
 441 +       int num_partitions = 0;
 442 +#endif
 443 +
 444 +       nand = kzalloc(sizeof(*nand), GFP_KERNEL);
 445 +       if (!nand) {
 446 +               dev_err(&pdev->dev, "Failed to allocate device structure.\n");
 447 +               return -ENOMEM;
 448 +       }
 449 +
 450 +       ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
 451 +       if (ret)
 452 +               goto err_free;
 453 +       ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
 454 +                       &nand->bank_base);
 455 +       if (ret)
 456 +               goto err_iounmap_mmio;
 457 +
 458 +       if (pdata && gpio_is_valid(pdata->busy_gpio)) {
 459 +               ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
 460 +               if (ret) {
 461 +                       dev_err(&pdev->dev,
 462 +                               "Failed to request busy gpio %d: %d\n",
 463 +                               pdata->busy_gpio, ret);
 464 +                       goto err_iounmap_mem;
 465 +               }
 466 +       }
 467 +
 468 +       mtd             = &nand->mtd;
 469 +       chip            = &nand->chip;
 470 +       mtd->priv       = chip;
 471 +       mtd->owner      = THIS_MODULE;
 472 +       mtd->name       = "jz4740-nand";
 473 +
 474 +       chip->ecc.hwctl         = jz_nand_hwctl;
 475 +       chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
 476 +       chip->ecc.correct       = jz_nand_correct_ecc_rs;
 477 +       chip->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
 478 +       chip->ecc.size          = 512;
 479 +       chip->ecc.bytes         = 9;
 480 +
 481 +       chip->ecc.read_page     = jz_nand_read_page_hwecc_oob_first;
 482 +       chip->ecc.write_page    = jz_nand_write_page_hwecc;
 483 +
 484 +       if (pdata)
 485 +               chip->ecc.layout = pdata->ecc_layout;
 486 +
 487 +       chip->chip_delay = 50;
 488 +       chip->cmd_ctrl = jz_nand_cmd_ctrl;
 489 +
 490 +       if (pdata && gpio_is_valid(pdata->busy_gpio))
 491 +               chip->dev_ready = jz_nand_dev_ready;
 492 +
 493 +       chip->IO_ADDR_R = nand->bank_base;
 494 +       chip->IO_ADDR_W = nand->bank_base;
 495 +
 496 +       nand->pdata = pdata;
 497 +       platform_set_drvdata(pdev, nand);
 498 +
 499 +       writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
 500 +
 501 +       ret = nand_scan_ident(mtd, 1, NULL);
 502 +       if (ret) {
 503 +               dev_err(&pdev->dev,  "Failed to scan nand\n");
 504 +               goto err_gpio_free;
 505 +       }
 506 +
 507 +       if (pdata && pdata->ident_callback) {
 508 +               pdata->ident_callback(pdev, chip, &pdata->partitions,
 509 +                                       &pdata->num_partitions);
 510 +       }
 511 +
 512 +       ret = nand_scan_tail(mtd);
 513 +       if (ret) {
 514 +               dev_err(&pdev->dev,  "Failed to scan nand\n");
 515 +               goto err_gpio_free;
 516 +       }
 517 +
 518 +#ifdef CONFIG_MTD_PARTITIONS
 519 +#ifdef CONFIG_MTD_CMDLINE_PARTS
 520 +       num_partitions = parse_mtd_partitions(mtd, part_probes,
 521 +                                               &partition_info, 0);
 522 +#endif
 523 +       if (num_partitions <= 0 && pdata) {
 524 +               num_partitions = pdata->num_partitions;
 525 +               partition_info = pdata->partitions;
 526 +       }
 527 +
 528 +       if (num_partitions > 0)
 529 +               ret = add_mtd_partitions(mtd, partition_info, num_partitions);
 530 +       else
 531 +#endif
 532 +       ret = add_mtd_device(mtd);
 533 +
 534 +       if (ret) {
 535 +               dev_err(&pdev->dev, "Failed to add mtd device\n");
 536 +               goto err_nand_release;
 537 +       }
 538 +
 539 +       dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
 540 +
 541 +       return 0;
 542 +
 543 +err_nand_release:
 544 +       nand_release(&nand->mtd);
 545 +err_gpio_free:
 546 +       platform_set_drvdata(pdev, NULL);
 547 +       gpio_free(pdata->busy_gpio);
 548 +err_iounmap_mem:
 549 +       iounmap(nand->bank_base);
 550 +err_iounmap_mmio:
 551 +       iounmap(nand->base);
 552 +err_free:
 553 +       kfree(nand);
 554 +       return ret;
 555 +}
 556 +
 557 +static int __devexit jz_nand_remove(struct platform_device *pdev)
 558 +{
 559 +       struct jz_nand *nand = platform_get_drvdata(pdev);
 560 +
 561 +       nand_release(&nand->mtd);
 562 +
 563 +       /* Deassert and disable all chips */
 564 +       writel(0, nand->base + JZ_REG_NAND_CTRL);
 565 +
 566 +       iounmap(nand->bank_base);
 567 +       release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
 568 +       iounmap(nand->base);
 569 +       release_mem_region(nand->mem->start, resource_size(nand->mem));
 570 +
 571 +       platform_set_drvdata(pdev, NULL);
 572 +       kfree(nand);
 573 +
 574 +       return 0;
 575 +}
 576 +
 577 +struct platform_driver jz_nand_driver = {
 578 +       .probe = jz_nand_probe,
 579 +       .remove = __devexit_p(jz_nand_remove),
 580 +       .driver = {
 581 +               .name = "jz4740-nand",
 582 +               .owner = THIS_MODULE,
 583 +       },
 584 +};
 585 +
 586 +static int __init jz_nand_init(void)
 587 +{
 588 +       return platform_driver_register(&jz_nand_driver);
 589 +}
 590 +module_init(jz_nand_init);
 591 +
 592 +static void __exit jz_nand_exit(void)
 593 +{
 594 +       platform_driver_unregister(&jz_nand_driver);
 595 +}
 596 +module_exit(jz_nand_exit);
 597 +
 598 +MODULE_LICENSE("GPL");
 599 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 600 +MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
 601 +MODULE_ALIAS("platform:jz4740-nand");