package/mac80211/patches/466-ath5k_optimize_tx_status.patch

   1 --- a/drivers/net/wireless/ath/ath5k/desc.c
   2 +++ b/drivers/net/wireless/ath/ath5k/desc.c
   3 @@ -401,32 +401,38 @@ static int ath5k_hw_proc_4word_tx_status
   4  {
   5         struct ath5k_hw_4w_tx_ctl *tx_ctl;
   6         struct ath5k_hw_tx_status *tx_status;
   7 +       u32 txstat0, txstat1, txctl2;
   8
   9         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  10         tx_status = &desc->ud.ds_tx5212.tx_stat;
  11
  12 +       txstat1 = ACCESS_ONCE(tx_status->tx_status_1);
  13 +
  14         /* No frame has been send or error */
  15 -       if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
  16 +       if (unlikely(!(txstat1 & AR5K_DESC_TX_STATUS1_DONE)))
  17                 return -EINPROGRESS;
  18
  19 +       txstat0 = ACCESS_ONCE(tx_status->tx_status_0);
  20 +       txctl2 = ACCESS_ONCE(tx_ctl->tx_control_2);
  21 +
  22         /*
  23          * Get descriptor status
  24          */
  25 -       ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
  26 +       ts->ts_tstamp = AR5K_REG_MS(txstat0,
  27                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
  28 -       ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
  29 +       ts->ts_shortretry = AR5K_REG_MS(txstat0,
  30                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
  31 -       ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
  32 +       ts->ts_longretry = AR5K_REG_MS(txstat0,
  33                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
  34 -       ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
  35 +       ts->ts_seqnum = AR5K_REG_MS(txstat1,
  36                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
  37 -       ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
  38 +       ts->ts_rssi = AR5K_REG_MS(txstat1,
  39                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
  40 -       ts->ts_antenna = (tx_status->tx_status_1 &
  41 +       ts->ts_antenna = (txstat1 &
  42                 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
  43         ts->ts_status = 0;
  44
  45 -       ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
  46 +       ts->ts_final_idx = AR5K_REG_MS(txstat1,
  47                         AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
  48
  49         /* The longretry counter has the number of un-acked retries
  50 @@ -437,17 +443,17 @@ static int ath5k_hw_proc_4word_tx_status
  51         ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
  52         switch (ts->ts_final_idx) {
  53         case 3:
  54 -               ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
  55 +               ts->ts_retry[2] = AR5K_REG_MS(txctl2,
  56                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
  57                 ts->ts_longretry += ts->ts_retry[2];
  58                 /* fall through */
  59         case 2:
  60 -               ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
  61 +               ts->ts_retry[1] = AR5K_REG_MS(txctl2,
  62                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
  63                 ts->ts_longretry += ts->ts_retry[1];
  64                 /* fall through */
  65         case 1:
  66 -               ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
  67 +               ts->ts_retry[0] = AR5K_REG_MS(txctl2,
  68                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
  69                 ts->ts_longretry += ts->ts_retry[0];
  70                 /* fall through */
  71 @@ -456,15 +462,14 @@ static int ath5k_hw_proc_4word_tx_status
  72         }
  73
  74         /* TX error */
  75 -       if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  76 -               if (tx_status->tx_status_0 &
  77 -                               AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  78 +       if (!(txstat0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  79 +               if (txstat0 & AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  80                         ts->ts_status |= AR5K_TXERR_XRETRY;
  81
  82 -               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  83 +               if (txstat0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  84                         ts->ts_status |= AR5K_TXERR_FIFO;
  85
  86 -               if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
  87 +               if (txstat0 & AR5K_DESC_TX_STATUS0_FILTERED)
  88                         ts->ts_status |= AR5K_TXERR_FILT;
  89         }
  90