target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_ar7240.c

   1 /*
   2  *  Driver for the built-in ethernet switch of the Atheros AR7240 SoC
   3  *  Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
   4  *  Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/etherdevice.h>
  13 #include <linux/list.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/phy.h>
  16 #include <linux/mii.h>
  17 #include <linux/bitops.h>
  18 #include <linux/switch.h>
  19 #include "ag71xx.h"
  20
  21 #define BITM(_count)    (BIT(_count) - 1)
  22 #define BITS(_shift, _count)    (BITM(_count) << _shift)
  23
  24 #define AR7240_REG_MASK_CTRL            0x00
  25 #define AR7240_MASK_CTRL_REVISION_M     BITM(8)
  26 #define AR7240_MASK_CTRL_VERSION_M      BITM(8)
  27 #define AR7240_MASK_CTRL_VERSION_S      8
  28 #define AR7240_MASK_CTRL_SOFT_RESET     BIT(31)
  29
  30 #define AR7240_REG_MAC_ADDR0            0x20
  31 #define AR7240_REG_MAC_ADDR1            0x24
  32
  33 #define AR7240_REG_FLOOD_MASK           0x2c
  34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU  BIT(26)
  35
  36 #define AR7240_REG_GLOBAL_CTRL          0x30
  37 #define AR7240_GLOBAL_CTRL_MTU_M        BITM(12)
  38
  39 #define AR7240_REG_VTU                  0x0040
  40 #define   AR7240_VTU_OP                 BITM(3)
  41 #define   AR7240_VTU_OP_NOOP            0x0
  42 #define   AR7240_VTU_OP_FLUSH           0x1
  43 #define   AR7240_VTU_OP_LOAD            0x2
  44 #define   AR7240_VTU_OP_PURGE           0x3
  45 #define   AR7240_VTU_OP_REMOVE_PORT     0x4
  46 #define   AR7240_VTU_ACTIVE             BIT(3)
  47 #define   AR7240_VTU_FULL               BIT(4)
  48 #define   AR7240_VTU_PORT               BITS(8, 4)
  49 #define   AR7240_VTU_PORT_S             8
  50 #define   AR7240_VTU_VID                BITS(16, 12)
  51 #define   AR7240_VTU_VID_S              16
  52 #define   AR7240_VTU_PRIO               BITS(28, 3)
  53 #define   AR7240_VTU_PRIO_S             28
  54 #define   AR7240_VTU_PRIO_EN            BIT(31)
  55
  56 #define AR7240_REG_VTU_DATA             0x0044
  57 #define   AR7240_VTUDATA_MEMBER         BITS(0, 10)
  58 #define   AR7240_VTUDATA_VALID          BIT(11)
  59
  60 #define AR7240_REG_AT_CTRL              0x5c
  61 #define AR7240_AT_CTRL_ARP_EN           BIT(20)
  62
  63 #define AR7240_REG_TAG_PRIORITY         0x70
  64
  65 #define AR7240_REG_SERVICE_TAG          0x74
  66 #define AR7240_SERVICE_TAG_M            BITM(16)
  67
  68 #define AR7240_REG_CPU_PORT             0x78
  69 #define AR7240_MIRROR_PORT_S            4
  70 #define AR7240_CPU_PORT_EN              BIT(8)
  71
  72 #define AR7240_REG_MIB_FUNCTION0        0x80
  73 #define AR7240_MIB_TIMER_M              BITM(16)
  74 #define AR7240_MIB_AT_HALF_EN           BIT(16)
  75 #define AR7240_MIB_BUSY                 BIT(17)
  76 #define AR7240_MIB_FUNC_S               24
  77 #define AR7240_MIB_FUNC_NO_OP           0x0
  78 #define AR7240_MIB_FUNC_FLUSH           0x1
  79 #define AR7240_MIB_FUNC_CAPTURE         0x3
  80
  81 #define AR7240_REG_MDIO_CTRL            0x98
  82 #define AR7240_MDIO_CTRL_DATA_M         BITM(16)
  83 #define AR7240_MDIO_CTRL_REG_ADDR_S     16
  84 #define AR7240_MDIO_CTRL_PHY_ADDR_S     21
  85 #define AR7240_MDIO_CTRL_CMD_WRITE      0
  86 #define AR7240_MDIO_CTRL_CMD_READ       BIT(27)
  87 #define AR7240_MDIO_CTRL_MASTER_EN      BIT(30)
  88 #define AR7240_MDIO_CTRL_BUSY           BIT(31)
  89
  90 #define AR7240_REG_PORT_BASE(_port)     (0x100 + (_port) * 0x100)
  91
  92 #define AR7240_REG_PORT_STATUS(_port)   (AR7240_REG_PORT_BASE((_port)) + 0x00)
  93 #define AR7240_PORT_STATUS_SPEED_M      BITM(2)
  94 #define AR7240_PORT_STATUS_SPEED_10     0
  95 #define AR7240_PORT_STATUS_SPEED_100    1
  96 #define AR7240_PORT_STATUS_SPEED_1000   2
  97 #define AR7240_PORT_STATUS_TXMAC        BIT(2)
  98 #define AR7240_PORT_STATUS_RXMAC        BIT(3)
  99 #define AR7240_PORT_STATUS_TXFLOW       BIT(4)
 100 #define AR7240_PORT_STATUS_RXFLOW       BIT(5)
 101 #define AR7240_PORT_STATUS_DUPLEX       BIT(6)
 102 #define AR7240_PORT_STATUS_LINK_UP      BIT(8)
 103 #define AR7240_PORT_STATUS_LINK_AUTO    BIT(9)
 104 #define AR7240_PORT_STATUS_LINK_PAUSE   BIT(10)
 105
 106 #define AR7240_REG_PORT_CTRL(_port)     (AR7240_REG_PORT_BASE((_port)) + 0x04)
 107 #define AR7240_PORT_CTRL_STATE_M        BITM(3)
 108 #define AR7240_PORT_CTRL_STATE_DISABLED 0
 109 #define AR7240_PORT_CTRL_STATE_BLOCK    1
 110 #define AR7240_PORT_CTRL_STATE_LISTEN   2
 111 #define AR7240_PORT_CTRL_STATE_LEARN    3
 112 #define AR7240_PORT_CTRL_STATE_FORWARD  4
 113 #define AR7240_PORT_CTRL_LEARN_LOCK     BIT(7)
 114 #define AR7240_PORT_CTRL_VLAN_MODE_S    8
 115 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
 116 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
 117 #define AR7240_PORT_CTRL_VLAN_MODE_ADD  2
 118 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
 119 #define AR7240_PORT_CTRL_IGMP_SNOOP     BIT(10)
 120 #define AR7240_PORT_CTRL_HEADER         BIT(11)
 121 #define AR7240_PORT_CTRL_MAC_LOOP       BIT(12)
 122 #define AR7240_PORT_CTRL_SINGLE_VLAN    BIT(13)
 123 #define AR7240_PORT_CTRL_LEARN          BIT(14)
 124 #define AR7240_PORT_CTRL_DOUBLE_TAG     BIT(15)
 125 #define AR7240_PORT_CTRL_MIRROR_TX      BIT(16)
 126 #define AR7240_PORT_CTRL_MIRROR_RX      BIT(17)
 127
 128 #define AR7240_REG_PORT_VLAN(_port)     (AR7240_REG_PORT_BASE((_port)) + 0x08)
 129
 130 #define AR7240_PORT_VLAN_DEFAULT_ID_S   0
 131 #define AR7240_PORT_VLAN_DEST_PORTS_S   16
 132 #define AR7240_PORT_VLAN_MODE_S         30
 133 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
 134 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK     1
 135 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
 136 #define AR7240_PORT_VLAN_MODE_SECURE    3
 137
 138
 139 #define AR7240_REG_STATS_BASE(_port)    (0x20000 + (_port) * 0x100)
 140
 141 #define AR7240_STATS_RXBROAD            0x00
 142 #define AR7240_STATS_RXPAUSE            0x04
 143 #define AR7240_STATS_RXMULTI            0x08
 144 #define AR7240_STATS_RXFCSERR           0x0c
 145 #define AR7240_STATS_RXALIGNERR         0x10
 146 #define AR7240_STATS_RXRUNT             0x14
 147 #define AR7240_STATS_RXFRAGMENT         0x18
 148 #define AR7240_STATS_RX64BYTE           0x1c
 149 #define AR7240_STATS_RX128BYTE          0x20
 150 #define AR7240_STATS_RX256BYTE          0x24
 151 #define AR7240_STATS_RX512BYTE          0x28
 152 #define AR7240_STATS_RX1024BYTE         0x2c
 153 #define AR7240_STATS_RX1518BYTE         0x30
 154 #define AR7240_STATS_RXMAXBYTE          0x34
 155 #define AR7240_STATS_RXTOOLONG          0x38
 156 #define AR7240_STATS_RXGOODBYTE         0x3c
 157 #define AR7240_STATS_RXBADBYTE          0x44
 158 #define AR7240_STATS_RXOVERFLOW         0x4c
 159 #define AR7240_STATS_FILTERED           0x50
 160 #define AR7240_STATS_TXBROAD            0x54
 161 #define AR7240_STATS_TXPAUSE            0x58
 162 #define AR7240_STATS_TXMULTI            0x5c
 163 #define AR7240_STATS_TXUNDERRUN         0x60
 164 #define AR7240_STATS_TX64BYTE           0x64
 165 #define AR7240_STATS_TX128BYTE          0x68
 166 #define AR7240_STATS_TX256BYTE          0x6c
 167 #define AR7240_STATS_TX512BYTE          0x70
 168 #define AR7240_STATS_TX1024BYTE         0x74
 169 #define AR7240_STATS_TX1518BYTE         0x78
 170 #define AR7240_STATS_TXMAXBYTE          0x7c
 171 #define AR7240_STATS_TXOVERSIZE         0x80
 172 #define AR7240_STATS_TXBYTE             0x84
 173 #define AR7240_STATS_TXCOLLISION        0x8c
 174 #define AR7240_STATS_TXABORTCOL         0x90
 175 #define AR7240_STATS_TXMULTICOL         0x94
 176 #define AR7240_STATS_TXSINGLECOL        0x98
 177 #define AR7240_STATS_TXEXCDEFER         0x9c
 178 #define AR7240_STATS_TXDEFER            0xa0
 179 #define AR7240_STATS_TXLATECOL          0xa4
 180
 181 #define AR7240_PORT_CPU         0
 182 #define AR7240_NUM_PORTS        6
 183 #define AR7240_NUM_PHYS         5
 184
 185 #define AR7240_PHY_ID1          0x004d
 186 #define AR7240_PHY_ID2          0xd041
 187
 188 #define AR7240_PORT_MASK(_port)         BIT((_port))
 189 #define AR7240_PORT_MASK_ALL            BITM(AR7240_NUM_PORTS)
 190 #define AR7240_PORT_MASK_BUT(_port)     (AR7240_PORT_MASK_ALL & ~BIT((_port)))
 191
 192 #define AR7240_MAX_VLANS        16
 193
 194 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
 195
 196 struct ar7240sw {
 197         struct mii_bus  *mii_bus;
 198         struct mutex    reg_mutex;
 199         struct switch_dev swdev;
 200         bool vlan;
 201         u16 vlan_id[AR7240_MAX_VLANS];
 202         u8 vlan_table[AR7240_MAX_VLANS];
 203         u8 vlan_tagged;
 204         u16 pvid[AR7240_NUM_PORTS];
 205 };
 206
 207 struct ar7240sw_hw_stat {
 208         char string[ETH_GSTRING_LEN];
 209         int sizeof_stat;
 210         int reg;
 211 };
 212
 213
 214 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
 215 {
 216         as->mii_bus = mii;
 217         mutex_init(&as->reg_mutex);
 218 }
 219
 220 static inline u16 mk_phy_addr(u32 reg)
 221 {
 222         return (0x17 & ((reg >> 4) | 0x10));
 223 }
 224
 225 static inline u16 mk_phy_reg(u32 reg)
 226 {
 227         return ((reg << 1) & 0x1e);
 228 }
 229
 230 static inline u16 mk_high_addr(u32 reg)
 231 {
 232         return ((reg >> 7) & 0x1ff);
 233 }
 234
 235 static u32 __ar7240sw_reg_read(struct ar7240sw *as, u32 reg)
 236 {
 237         struct mii_bus *mii = as->mii_bus;
 238         u16 phy_addr;
 239         u16 phy_reg;
 240         u32 hi, lo;
 241
 242         reg = (reg & 0xfffffffc) >> 2;
 243
 244         mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg));
 245
 246         phy_addr = mk_phy_addr(reg);
 247         phy_reg = mk_phy_reg(reg);
 248
 249         lo = (u32) mdiobus_read(mii, phy_addr, phy_reg);
 250         hi = (u32) mdiobus_read(mii, phy_addr, phy_reg + 1);
 251
 252         return ((hi << 16) | lo);
 253 }
 254
 255 static void __ar7240sw_reg_write(struct ar7240sw *as, u32 reg, u32 val)
 256 {
 257         struct mii_bus *mii = as->mii_bus;
 258         u16 phy_addr;
 259         u16 phy_reg;
 260
 261         reg = (reg & 0xfffffffc) >> 2;
 262
 263         mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg));
 264
 265         phy_addr = mk_phy_addr(reg);
 266         phy_reg = mk_phy_reg(reg);
 267
 268         mdiobus_write(mii, phy_addr, phy_reg + 1, (val >> 16));
 269         mdiobus_write(mii, phy_addr, phy_reg, (val & 0xffff));
 270 }
 271
 272 static u32 ar7240sw_reg_read(struct ar7240sw *as, u32 reg_addr)
 273 {
 274         u32 ret;
 275
 276         mutex_lock(&as->reg_mutex);
 277         ret = __ar7240sw_reg_read(as, reg_addr);
 278         mutex_unlock(&as->reg_mutex);
 279
 280         return ret;
 281 }
 282
 283 static void ar7240sw_reg_write(struct ar7240sw *as, u32 reg_addr, u32 reg_val)
 284 {
 285         mutex_lock(&as->reg_mutex);
 286         __ar7240sw_reg_write(as, reg_addr, reg_val);
 287         mutex_unlock(&as->reg_mutex);
 288 }
 289
 290 static u32 ar7240sw_reg_rmw(struct ar7240sw *as, u32 reg, u32 mask, u32 val)
 291 {
 292         u32 t;
 293
 294         mutex_lock(&as->reg_mutex);
 295         t = __ar7240sw_reg_read(as, reg);
 296         t &= ~mask;
 297         t |= val;
 298         __ar7240sw_reg_write(as, reg, t);
 299         mutex_unlock(&as->reg_mutex);
 300
 301         return t;
 302 }
 303
 304 static void ar7240sw_reg_set(struct ar7240sw *as, u32 reg, u32 val)
 305 {
 306         u32 t;
 307
 308         mutex_lock(&as->reg_mutex);
 309         t = __ar7240sw_reg_read(as, reg);
 310         t |= val;
 311         __ar7240sw_reg_write(as, reg, t);
 312         mutex_unlock(&as->reg_mutex);
 313 }
 314
 315 static int ar7240sw_reg_wait(struct ar7240sw *as, u32 reg, u32 mask, u32 val,
 316                              unsigned timeout)
 317 {
 318         int i;
 319
 320         for (i = 0; i < timeout; i++) {
 321                 u32 t;
 322
 323                 t = ar7240sw_reg_read(as, reg);
 324                 if ((t & mask) == val)
 325                         return 0;
 326
 327                 msleep(1);
 328         }
 329
 330         return -ETIMEDOUT;
 331 }
 332
 333 static u16 ar7240sw_phy_read(struct ar7240sw *as, unsigned phy_addr,
 334                              unsigned reg_addr)
 335 {
 336         u32 t;
 337         int err;
 338
 339         if (phy_addr >= AR7240_NUM_PHYS)
 340                 return 0xffff;
 341
 342         t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
 343             (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
 344             AR7240_MDIO_CTRL_MASTER_EN |
 345             AR7240_MDIO_CTRL_BUSY |
 346             AR7240_MDIO_CTRL_CMD_READ;
 347
 348         ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t);
 349         err = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL,
 350                                 AR7240_MDIO_CTRL_BUSY, 0, 5);
 351         if (err)
 352                 return 0xffff;
 353
 354         t = ar7240sw_reg_read(as, AR7240_REG_MDIO_CTRL);
 355         return (t & AR7240_MDIO_CTRL_DATA_M);
 356 }
 357
 358 static int ar7240sw_phy_write(struct ar7240sw *as, unsigned phy_addr,
 359                               unsigned reg_addr, u16 reg_val)
 360 {
 361         u32 t;
 362         int ret;
 363
 364         if (phy_addr >= AR7240_NUM_PHYS)
 365                 return -EINVAL;
 366
 367         t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
 368             (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
 369             AR7240_MDIO_CTRL_MASTER_EN |
 370             AR7240_MDIO_CTRL_BUSY |
 371             AR7240_MDIO_CTRL_CMD_WRITE |
 372             reg_val;
 373
 374         ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t);
 375         ret = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL,
 376                                 AR7240_MDIO_CTRL_BUSY, 0, 5);
 377         return ret;
 378 }
 379
 380 static int ar7240sw_capture_stats(struct ar7240sw *as)
 381 {
 382         int ret;
 383
 384         /* Capture the hardware statistics for all ports */
 385         ar7240sw_reg_write(as, AR7240_REG_MIB_FUNCTION0,
 386                            (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
 387
 388         /* Wait for the capturing to complete. */
 389         ret = ar7240sw_reg_wait(as, AR7240_REG_MIB_FUNCTION0,
 390                                 AR7240_MIB_BUSY, 0, 10);
 391         return ret;
 392 }
 393
 394 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
 395 {
 396         ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port),
 397                            AR7240_PORT_CTRL_STATE_DISABLED);
 398 }
 399
 400 static int ar7240sw_reset(struct ar7240sw *as)
 401 {
 402         int ret;
 403         int i;
 404
 405         /* Set all ports to disabled state. */
 406         for (i = 0; i < AR7240_NUM_PORTS; i++)
 407                 ar7240sw_disable_port(as, i);
 408
 409         /* Wait for transmit queues to drain. */
 410         msleep(2);
 411
 412         /* Reset the switch. */
 413         ar7240sw_reg_write(as, AR7240_REG_MASK_CTRL,
 414                            AR7240_MASK_CTRL_SOFT_RESET);
 415
 416         ret = ar7240sw_reg_wait(as, AR7240_REG_MASK_CTRL,
 417                                 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
 418         return ret;
 419 }
 420
 421 static void ar7240sw_setup(struct ar7240sw *as)
 422 {
 423         /* Enable CPU port, and disable mirror port */
 424         ar7240sw_reg_write(as, AR7240_REG_CPU_PORT,
 425                            AR7240_CPU_PORT_EN |
 426                            (15 << AR7240_MIRROR_PORT_S));
 427
 428         /* Setup TAG priority mapping */
 429         ar7240sw_reg_write(as, AR7240_REG_TAG_PRIORITY, 0xfa50);
 430
 431         /* Enable ARP frame acknowledge */
 432         ar7240sw_reg_set(as, AR7240_REG_AT_CTRL, AR7240_AT_CTRL_ARP_EN);
 433
 434         /* Enable Broadcast frames transmitted to the CPU */
 435         ar7240sw_reg_set(as, AR7240_REG_FLOOD_MASK,
 436                          AR7240_FLOOD_MASK_BROAD_TO_CPU);
 437
 438         /* setup MTU */
 439         ar7240sw_reg_rmw(as, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
 440                          1536);
 441
 442         /* setup Service TAG */
 443         ar7240sw_reg_rmw(as, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
 444 }
 445
 446 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
 447 {
 448         u32 ctrl;
 449         u32 dest_ports;
 450         u32 vlan;
 451
 452         ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
 453                 AR7240_PORT_CTRL_SINGLE_VLAN;
 454
 455         if (port == AR7240_PORT_CPU) {
 456                 ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port),
 457                                    AR7240_PORT_STATUS_SPEED_1000 |
 458                                    AR7240_PORT_STATUS_TXFLOW |
 459                                    AR7240_PORT_STATUS_RXFLOW |
 460                                    AR7240_PORT_STATUS_TXMAC |
 461                                    AR7240_PORT_STATUS_RXMAC |
 462                                    AR7240_PORT_STATUS_DUPLEX);
 463         } else {
 464                 ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port),
 465                                    AR7240_PORT_STATUS_LINK_AUTO);
 466         }
 467
 468         /* Set the default VID for this port */
 469         if (as->vlan) {
 470                 vlan = as->vlan_id[as->pvid[port]];
 471                 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
 472                         AR7240_PORT_VLAN_MODE_S;
 473         } else {
 474                 vlan = port;
 475                 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
 476                         AR7240_PORT_VLAN_MODE_S;
 477         }
 478
 479         if (as->vlan && (as->vlan_tagged & BIT(port))) {
 480                 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
 481                         AR7240_PORT_CTRL_VLAN_MODE_S;
 482         } else {
 483                 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
 484                         AR7240_PORT_CTRL_VLAN_MODE_S;
 485         }
 486
 487         if (!portmask) {
 488                 if (port == AR7240_PORT_CPU)
 489                         portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
 490                 else
 491                         portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
 492         }
 493
 494         /* allow the port to talk to all other ports, but exclude its
 495          * own ID to prevent frames from being reflected back to the
 496          * port that they came from */
 497         dest_ports = AR7240_PORT_MASK_BUT(port);
 498
 499         /* set default VID and and destination ports for this VLAN */
 500         vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
 501
 502         ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port), ctrl);
 503         ar7240sw_reg_write(as, AR7240_REG_PORT_VLAN(port), vlan);
 504 }
 505
 506 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
 507 {
 508         u32 t;
 509
 510         t = (addr[4] << 8) | addr[5];
 511         ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR0, t);
 512
 513         t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
 514         ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR1, t);
 515
 516         return 0;
 517 }
 518
 519 static int
 520 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
 521                 struct switch_val *val)
 522 {
 523         struct ar7240sw *as = sw_to_ar7240(dev);
 524         as->vlan_id[val->port_vlan] = val->value.i;
 525         return 0;
 526 }
 527
 528 static int
 529 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
 530                 struct switch_val *val)
 531 {
 532         struct ar7240sw *as = sw_to_ar7240(dev);
 533         val->value.i = as->vlan_id[val->port_vlan];
 534         return 0;
 535 }
 536
 537 static int
 538 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
 539 {
 540         struct ar7240sw *as = sw_to_ar7240(dev);
 541
 542         /* make sure no invalid PVIDs get set */
 543
 544         if (vlan >= dev->vlans)
 545                 return -EINVAL;
 546
 547         as->pvid[port] = vlan;
 548         return 0;
 549 }
 550
 551 static int
 552 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
 553 {
 554         struct ar7240sw *as = sw_to_ar7240(dev);
 555         *vlan = as->pvid[port];
 556         return 0;
 557 }
 558
 559 static int
 560 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
 561 {
 562         struct ar7240sw *as = sw_to_ar7240(dev);
 563         u8 ports = as->vlan_table[val->port_vlan];
 564         int i;
 565
 566         val->len = 0;
 567         for (i = 0; i < AR7240_NUM_PORTS; i++) {
 568                 struct switch_port *p;
 569
 570                 if (!(ports & (1 << i)))
 571                         continue;
 572
 573                 p = &val->value.ports[val->len++];
 574                 p->id = i;
 575                 if (as->vlan_tagged & (1 << i))
 576                         p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
 577                 else
 578                         p->flags = 0;
 579         }
 580         return 0;
 581 }
 582
 583 static int
 584 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
 585 {
 586         struct ar7240sw *as = sw_to_ar7240(dev);
 587         u8 *vt = &as->vlan_table[val->port_vlan];
 588         int i, j;
 589
 590         *vt = 0;
 591         for (i = 0; i < val->len; i++) {
 592                 struct switch_port *p = &val->value.ports[i];
 593
 594                 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
 595                         as->vlan_tagged |= (1 << p->id);
 596                 else {
 597                         as->vlan_tagged &= ~(1 << p->id);
 598                         as->pvid[p->id] = val->port_vlan;
 599
 600                         /* make sure that an untagged port does not
 601                          * appear in other vlans */
 602                         for (j = 0; j < AR7240_MAX_VLANS; j++) {
 603                                 if (j == val->port_vlan)
 604                                         continue;
 605                                 as->vlan_table[j] &= ~(1 << p->id);
 606                         }
 607                 }
 608
 609                 *vt |= 1 << p->id;
 610         }
 611         return 0;
 612 }
 613
 614 static int
 615 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 616                 struct switch_val *val)
 617 {
 618         struct ar7240sw *as = sw_to_ar7240(dev);
 619         as->vlan = !!val->value.i;
 620         return 0;
 621 }
 622
 623 static int
 624 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
 625                 struct switch_val *val)
 626 {
 627         struct ar7240sw *as = sw_to_ar7240(dev);
 628         val->value.i = as->vlan;
 629         return 0;
 630 }
 631
 632
 633 static void
 634 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
 635 {
 636         if (ar7240sw_reg_wait(as, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
 637                 return;
 638
 639         if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
 640                 val &= AR7240_VTUDATA_MEMBER;
 641                 val |= AR7240_VTUDATA_VALID;
 642                 ar7240sw_reg_write(as, AR7240_REG_VTU_DATA, val);
 643         }
 644         op |= AR7240_VTU_ACTIVE;
 645         ar7240sw_reg_write(as, AR7240_REG_VTU, op);
 646 }
 647
 648 static int
 649 ar7240_hw_apply(struct switch_dev *dev)
 650 {
 651         struct ar7240sw *as = sw_to_ar7240(dev);
 652         u8 portmask[AR7240_NUM_PORTS];
 653         int i, j;
 654
 655         /* flush all vlan translation unit entries */
 656         ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
 657
 658         memset(portmask, 0, sizeof(portmask));
 659         if (as->vlan) {
 660                 /* calculate the port destination masks and load vlans
 661                  * into the vlan translation unit */
 662                 for (j = 0; j < AR7240_MAX_VLANS; j++) {
 663                         u8 vp = as->vlan_table[j];
 664
 665                         if (!vp)
 666                                 continue;
 667
 668                         for (i = 0; i < AR7240_NUM_PORTS; i++) {
 669                                 u8 mask = (1 << i);
 670                                 if (vp & mask)
 671                                         portmask[i] |= vp & ~mask;
 672                         }
 673
 674                         ar7240_vtu_op(as,
 675                                 AR7240_VTU_OP_LOAD |
 676                                 (as->vlan_id[j] << AR7240_VTU_VID_S),
 677                                 as->vlan_table[j]);
 678                 }
 679         } else {
 680                 /* vlan disabled:
 681                  * isolate all ports, but connect them to the cpu port */
 682                 for (i = 0; i < AR7240_NUM_PORTS; i++) {
 683                         if (i == AR7240_PORT_CPU)
 684                                 continue;
 685
 686                         portmask[i] = 1 << AR7240_PORT_CPU;
 687                         portmask[AR7240_PORT_CPU] |= (1 << i);
 688                 }
 689         }
 690
 691         /* update the port destination mask registers and tag settings */
 692         for (i = 0; i < AR7240_NUM_PORTS; i++)
 693                 ar7240sw_setup_port(as, i, portmask[i]);
 694
 695         return 0;
 696 }
 697
 698 static int
 699 ar7240_reset_switch(struct switch_dev *dev)
 700 {
 701         struct ar7240sw *as = sw_to_ar7240(dev);
 702         ar7240sw_reset(as);
 703         return 0;
 704 }
 705
 706 static struct switch_attr ar7240_globals[] = {
 707         {
 708                 .type = SWITCH_TYPE_INT,
 709                 .name = "enable_vlan",
 710                 .description = "Enable VLAN mode",
 711                 .set = ar7240_set_vlan,
 712                 .get = ar7240_get_vlan,
 713                 .max = 1
 714         },
 715 };
 716
 717 static struct switch_attr ar7240_port[] = {
 718 };
 719
 720 static struct switch_attr ar7240_vlan[] = {
 721         {
 722                 .type = SWITCH_TYPE_INT,
 723                 .name = "vid",
 724                 .description = "VLAN ID",
 725                 .set = ar7240_set_vid,
 726                 .get = ar7240_get_vid,
 727                 .max = 4094,
 728         },
 729 };
 730
 731 static const struct switch_dev_ops ar7240_ops = {
 732         .attr_global = {
 733                 .attr = ar7240_globals,
 734                 .n_attr = ARRAY_SIZE(ar7240_globals),
 735         },
 736         .attr_port = {
 737                 .attr = ar7240_port,
 738                 .n_attr = ARRAY_SIZE(ar7240_port),
 739         },
 740         .attr_vlan = {
 741                 .attr = ar7240_vlan,
 742                 .n_attr = ARRAY_SIZE(ar7240_vlan),
 743         },
 744         .get_port_pvid = ar7240_get_pvid,
 745         .set_port_pvid = ar7240_set_pvid,
 746         .get_vlan_ports = ar7240_get_ports,
 747         .set_vlan_ports = ar7240_set_ports,
 748         .apply_config = ar7240_hw_apply,
 749         .reset_switch = ar7240_reset_switch,
 750 };
 751
 752 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
 753 {
 754         struct mii_bus *mii = ag->mii_bus;
 755         struct ar7240sw *as;
 756         struct switch_dev *swdev;
 757         u32 ctrl;
 758         u16 phy_id1;
 759         u16 phy_id2;
 760         u8 ver;
 761         int i;
 762
 763         as = kzalloc(sizeof(*as), GFP_KERNEL);
 764         if (!as)
 765                 return NULL;
 766
 767         ar7240sw_init(as, mii);
 768
 769         ctrl = ar7240sw_reg_read(as, AR7240_REG_MASK_CTRL);
 770
 771         ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
 772         if (ver != 1) {
 773                 pr_err("%s: unsupported chip, ctrl=%08x\n",
 774                         ag->dev->name, ctrl);
 775                 return NULL;
 776         }
 777
 778         phy_id1 = ar7240sw_phy_read(as, 0, MII_PHYSID1);
 779         phy_id2 = ar7240sw_phy_read(as, 0, MII_PHYSID2);
 780         if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
 781                 pr_err("%s: unknown phy id '%04x:%04x'\n",
 782                        ag->dev->name, phy_id1, phy_id2);
 783                 return NULL;
 784         }
 785
 786         swdev = &as->swdev;
 787         swdev->name = "AR7240 built-in switch";
 788         swdev->ports = AR7240_NUM_PORTS;
 789         swdev->cpu_port = AR7240_PORT_CPU;
 790         swdev->vlans = AR7240_MAX_VLANS;
 791         swdev->ops = &ar7240_ops;
 792
 793         if (register_switch(&as->swdev, ag->dev) < 0) {
 794                 kfree(as);
 795                 return NULL;
 796         }
 797
 798         printk("%s: Found an AR7240 built-in switch\n", ag->dev->name);
 799
 800         /* initialize defaults */
 801         for (i = 0; i < AR7240_MAX_VLANS; i++)
 802                 as->vlan_id[i] = i;
 803
 804         as->vlan_table[0] = AR7240_PORT_MASK_ALL;
 805
 806         return as;
 807 }
 808
 809 void ag71xx_ar7240_start(struct ag71xx *ag)
 810 {
 811         struct ar7240sw *as = ag->phy_priv;
 812
 813         ar7240sw_reset(as);
 814         ar7240sw_setup(as);
 815
 816         ag->speed = SPEED_1000;
 817         ag->link = 1;
 818         ag->duplex = 1;
 819
 820         ar7240_set_addr(as, ag->dev->dev_addr);
 821         ar7240_hw_apply(&as->swdev);
 822 }
 823
 824 void ag71xx_ar7240_stop(struct ag71xx *ag)
 825 {
 826 }
 827
 828 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
 829 {
 830         struct ar7240sw *as;
 831
 832         as = ar7240_probe(ag);
 833         if (!as)
 834                 return -ENODEV;
 835
 836         ag->phy_priv = as;
 837         ar7240sw_reset(as);
 838
 839         return 0;
 840 }
 841
 842 void __devexit ag71xx_ar7240_cleanup(struct ag71xx *ag)
 843 {
 844         struct ar7240sw *as = ag->phy_priv;
 845
 846         if (!as)
 847                 return;
 848
 849         unregister_switch(&as->swdev);
 850         kfree(as);
 851         ag->phy_priv = NULL;
 852 }