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disable minix, separate flash-map driver patch
[openwrt.git] / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -Nur linux-2.6.12.5/arch/mips/Kconfig linux-2.6.12.5-brcm/arch/mips/Kconfig
2 --- linux-2.6.12.5/arch/mips/Kconfig 2005-08-15 02:20:18.000000000 +0200
3 +++ linux-2.6.12.5-brcm/arch/mips/Kconfig 2005-09-16 10:29:18.135597872 +0200
4 @@ -40,6 +40,15 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select CPU_LITTLE_ENDIAN
14 + help
15 + Support for BCM947xx based boards
16 +
17 config ACER_PICA_61
18 bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
19 depends on MACH_JAZZ && EXPERIMENTAL
20 @@ -974,7 +983,7 @@
21
22 config CPU_LITTLE_ENDIAN
23 bool "Generate little endian code"
24 - default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
25 + default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA || BCM947XX
26 default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
27 help
28 Some MIPS machines can be configured for either little or big endian
29 diff -Nur linux-2.6.12.5/arch/mips/Makefile linux-2.6.12.5-brcm/arch/mips/Makefile
30 --- linux-2.6.12.5/arch/mips/Makefile 2005-08-15 02:20:18.000000000 +0200
31 +++ linux-2.6.12.5-brcm/arch/mips/Makefile 2005-09-16 10:29:18.137597568 +0200
32 @@ -79,7 +79,7 @@
33 cflags-y += -I $(TOPDIR)/include/asm/gcc
34 cflags-y += -G 0 -mno-abicalls -fno-pic -pipe
35 cflags-y += $(call cc-option, -finline-limit=100000)
36 -LDFLAGS_vmlinux += -G 0 -static -n
37 +LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
38 MODFLAGS += -mlong-calls
39
40 cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
41 @@ -170,6 +170,7 @@
42 cflags-$(CONFIG_CPU_MIPS32) += \
43 $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \
44 -Wa,--trap
45 +cflags-$(CONFIG_CPU_MIPS32) += -Wa,--trap
46
47 cflags-$(CONFIG_CPU_MIPS64) += \
48 $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \
49 @@ -618,6 +619,14 @@
50 load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
51
52 #
53 +# Broadcom BCM47XX boards
54 +#
55 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
56 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
57 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
58 +
59 +
60 +#
61 # SNI RM200 PCI
62 #
63 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
64 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/Makefile linux-2.6.12.5-brcm/arch/mips/bcm947xx/Makefile
65 --- linux-2.6.12.5/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
66 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/Makefile 2005-09-16 10:29:18.149595744 +0200
67 @@ -0,0 +1,6 @@
68 +#
69 +# Makefile for the BCM47xx specific kernel interface routines
70 +# under Linux.
71 +#
72 +
73 +obj-y := irq.o int-handler.o prom.o setup.o time.o
74 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/Makefile linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/Makefile
75 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
76 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/Makefile 2005-09-16 10:29:18.149595744 +0200
77 @@ -0,0 +1,6 @@
78 +#
79 +# Makefile for the BCM47xx specific kernel interface routines
80 +# under Linux.
81 +#
82 +
83 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o hnddma.o
84 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmsrom.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmsrom.c
85 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
86 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-09-16 10:29:18.150595592 +0200
87 @@ -0,0 +1,685 @@
88 +/*
89 + * Misc useful routines to access NIC SROM
90 + *
91 + * Copyright 2001-2003, Broadcom Corporation
92 + * All Rights Reserved.
93 + *
94 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
95 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
96 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
97 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
98 + * $Id: bcmsrom.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
99 + */
100 +
101 +#include <typedefs.h>
102 +#include <osl.h>
103 +#include <bcmutils.h>
104 +#include <bcmsrom.h>
105 +#include <bcmdevs.h>
106 +#include <bcmendian.h>
107 +#include <sbpcmcia.h>
108 +#include <pcicfg.h>
109 +
110 +#include <proto/ethernet.h> /* for sprom content groking */
111 +
112 +#define VARS_MAX 4096 /* should be reduced */
113 +
114 +static int initvars_srom_pci(void *curmap, char **vars, int *count);
115 +static int initvars_cis_pcmcia(void *osh, char **vars, int *count);
116 +static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
117 +static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
118 +static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
119 +static int sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc);
120 +
121 +/*
122 + * Initialize the vars from the right source for this platform.
123 + * Return 0 on success, nonzero on error.
124 + */
125 +int
126 +srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count)
127 +{
128 + if (vars == NULL)
129 + return (0);
130 +
131 + switch (bus) {
132 + case SB_BUS:
133 + /* These two could be asserts ... */
134 + *vars = NULL;
135 + *count = 0;
136 + return(0);
137 +
138 + case PCI_BUS:
139 + ASSERT(curmap); /* can not be NULL */
140 + return(initvars_srom_pci(curmap, vars, count));
141 +
142 + case PCMCIA_BUS:
143 + return(initvars_cis_pcmcia(osh, vars, count));
144 +
145 +
146 + default:
147 + ASSERT(0);
148 + }
149 + return (-1);
150 +}
151 +
152 +
153 +/* support only 16-bit word read from srom */
154 +int
155 +srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
156 +{
157 + void *srom;
158 + uint i, off, nw;
159 +
160 + /* check input - 16-bit access only */
161 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
162 + return 1;
163 +
164 + if (bus == PCI_BUS) {
165 + if (!curmap)
166 + return 1;
167 + srom = (void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
168 + if (sprom_read_pci(srom, byteoff, buf, nbytes, FALSE))
169 + return 1;
170 + } else if (bus == PCMCIA_BUS) {
171 + off = byteoff / 2;
172 + nw = nbytes / 2;
173 + for (i = 0; i < nw; i++) {
174 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
175 + return 1;
176 + }
177 + } else {
178 + return 1;
179 + }
180 +
181 + return 0;
182 +}
183 +
184 +/* support only 16-bit word write into srom */
185 +int
186 +srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
187 +{
188 + uint16 *srom;
189 + uint i, off, nw, crc_range;
190 + uint16 image[SPROM_SIZE], *p;
191 + uint8 crc;
192 + volatile uint32 val32;
193 +
194 + /* check input - 16-bit access only */
195 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
196 + return 1;
197 +
198 + crc_range = ((bus == PCMCIA_BUS) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
199 +
200 + /* if changes made inside crc cover range */
201 + if (byteoff < crc_range) {
202 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
203 + /* read data including entire first 64 words from srom */
204 + if (srom_read(bus, curmap, osh, 0, nw * 2, image))
205 + return 1;
206 + /* make changes */
207 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
208 + /* calculate crc */
209 + htol16_buf(image, crc_range);
210 + crc = ~crc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
211 + ltoh16_buf(image, crc_range);
212 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
213 + p = image;
214 + off = 0;
215 + } else {
216 + p = buf;
217 + off = byteoff / 2;
218 + nw = nbytes / 2;
219 + }
220 +
221 + if (bus == PCI_BUS) {
222 + srom = (uint16*)((uint)curmap + PCI_BAR0_SPROM_OFFSET);
223 + /* enable writes to the SPROM */
224 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
225 + val32 |= SPROM_WRITEEN;
226 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
227 + bcm_mdelay(500);
228 + /* write srom */
229 + for (i = 0; i < nw; i++) {
230 + W_REG(&srom[off + i], p[i]);
231 + bcm_mdelay(20);
232 + }
233 + /* disable writes to the SPROM */
234 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
235 + } else if (bus == PCMCIA_BUS) {
236 + /* enable writes to the SPROM */
237 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
238 + return 1;
239 + bcm_mdelay(500);
240 + /* write srom */
241 + for (i = 0; i < nw; i++) {
242 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
243 + bcm_mdelay(20);
244 + }
245 + /* disable writes to the SPROM */
246 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
247 + return 1;
248 + } else {
249 + return 1;
250 + }
251 +
252 + bcm_mdelay(500);
253 + return 0;
254 +}
255 +
256 +
257 +int
258 +srom_parsecis(uint8 *cis, char **vars, int *count)
259 +{
260 + char eabuf[32];
261 + char *vp, *base;
262 + uint8 tup, tlen, sromrev = 1;
263 + int i, j;
264 + uint varsize;
265 + bool ag_init = FALSE;
266 + uint16 w;
267 +
268 + ASSERT(vars);
269 + ASSERT(count);
270 +
271 + base = vp = MALLOC(VARS_MAX);
272 + ASSERT(vp);
273 +
274 + i = 0;
275 + do {
276 + tup = cis[i++];
277 + tlen = cis[i++];
278 +
279 + switch (tup) {
280 + case CISTPL_MANFID:
281 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
282 + vp++;
283 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
284 + vp++;
285 + break;
286 +
287 + case CISTPL_FUNCE:
288 + if (cis[i] == LAN_NID) {
289 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
290 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
291 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
292 + vp++;
293 + }
294 + break;
295 +
296 + case CISTPL_CFTABLE:
297 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
298 + vp++;
299 + break;
300 +
301 + case CISTPL_BRCM_HNBU:
302 + switch (cis[i]) {
303 + case HNBU_CHIPID:
304 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
305 + vp++;
306 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
307 + vp++;
308 + if (tlen == 7) {
309 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
310 + vp++;
311 + }
312 + break;
313 +
314 + case HNBU_BOARDREV:
315 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
316 + vp++;
317 + break;
318 +
319 + case HNBU_AA:
320 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
321 + vp++;
322 + break;
323 +
324 + case HNBU_AG:
325 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
326 + vp++;
327 + ag_init = TRUE;
328 + break;
329 +
330 + case HNBU_CC:
331 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
332 + vp++;
333 + break;
334 +
335 + case HNBU_PAPARMS:
336 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
337 + vp++;
338 + if (tlen == 9) {
339 + /* New version */
340 + for (j = 0; j < 3; j++) {
341 + vp += sprintf(vp, "pa0b%d=%d", j,
342 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
343 + vp++;
344 + }
345 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
346 + vp++;
347 + }
348 + break;
349 +
350 + case HNBU_OEM:
351 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
352 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
353 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
354 + vp++;
355 + break;
356 + case HNBU_BOARDFLAGS:
357 + w = (cis[i + 2] << 8) + cis[i + 1];
358 + if (w == 0xffff) w = 0;
359 + vp += sprintf(vp, "boardflags=%d", w);
360 + vp++;
361 + break;
362 + case HNBU_LED:
363 + if (cis[i + 1] != 0xff) {
364 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
365 + vp++;
366 + }
367 + if (cis[i + 2] != 0xff) {
368 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
369 + vp++;
370 + }
371 + if (cis[i + 3] != 0xff) {
372 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
373 + vp++;
374 + }
375 + if (cis[i + 4] != 0xff) {
376 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
377 + vp++;
378 + }
379 + break;
380 + }
381 + break;
382 +
383 + }
384 + i += tlen;
385 + } while (tup != 0xff);
386 +
387 + /* Set the srom version */
388 + vp += sprintf(vp, "sromrev=%d", sromrev);
389 + vp++;
390 +
391 + /* For now just set boardflags2 to zero */
392 + vp += sprintf(vp, "boardflags2=0");
393 + vp++;
394 +
395 + /* if there is no antenna gain field, set default */
396 + if (ag_init == FALSE) {
397 + vp += sprintf(vp, "ag0=%d", 0xff);
398 + vp++;
399 + }
400 +
401 + /* final nullbyte terminator */
402 + *vp++ = '\0';
403 + varsize = (uint)vp - (uint)base;
404 +
405 + ASSERT(varsize < VARS_MAX);
406 +
407 + if (varsize == VARS_MAX) {
408 + *vars = base;
409 + } else {
410 + vp = MALLOC(varsize);
411 + ASSERT(vp);
412 + bcopy(base, vp, varsize);
413 + MFREE(base, VARS_MAX);
414 + *vars = vp;
415 + }
416 + *count = varsize;
417 +
418 + return (0);
419 +}
420 +
421 +
422 +/* set PCMCIA sprom command register */
423 +static int
424 +sprom_cmd_pcmcia(void *osh, uint8 cmd)
425 +{
426 + uint8 status;
427 + uint wait_cnt = 1000;
428 +
429 + /* write sprom command register */
430 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
431 +
432 + /* wait status */
433 + while (wait_cnt--) {
434 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
435 + if (status & SROM_DONE)
436 + return 0;
437 + }
438 + return 1;
439 +}
440 +
441 +/* read a word from the PCMCIA srom */
442 +static int
443 +sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
444 +{
445 + uint8 addr_l, addr_h, data_l, data_h;
446 +
447 + addr_l = (uint8)((addr * 2) & 0xff);
448 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
449 +
450 + /* set address */
451 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
453 +
454 + /* do read */
455 + if (sprom_cmd_pcmcia(osh, SROM_READ))
456 + return 1;
457 +
458 + /* read data */
459 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
460 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
461 +
462 + *data = (data_h << 8) | data_l;
463 + return 0;
464 +}
465 +
466 +/* write a word to the PCMCIA srom */
467 +static int
468 +sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
469 +{
470 + uint8 addr_l, addr_h, data_l, data_h;
471 +
472 + addr_l = (uint8)((addr * 2) & 0xff);
473 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
474 + data_l = (uint8)(data & 0xff);
475 + data_h = (uint8)((data >> 8) & 0xff);
476 +
477 + /* set address */
478 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
479 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
480 +
481 + /* write data */
482 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
483 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
484 +
485 + /* do write */
486 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
487 +}
488 +
489 +/*
490 + * Read in and validate sprom.
491 + * Return 0 on success, nonzero on error.
492 + */
493 +static int
494 +sprom_read_pci(uint16 *sprom, uint byteoff, uint16 *buf, uint nbytes, bool check_crc)
495 +{
496 + int off, nw;
497 + uint8 chk8;
498 + int i;
499 +
500 + off = byteoff / 2;
501 + nw = ROUNDUP(nbytes, 2) / 2;
502 +
503 + /* read the sprom */
504 + for (i = 0; i < nw; i++)
505 + buf[i] = R_REG(&sprom[off + i]);
506 +
507 + if (check_crc) {
508 + /* fixup the endianness so crc8 will pass */
509 + htol16_buf(buf, nw * 2);
510 + if ((chk8 = crc8((uchar*)buf, nbytes, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
511 + return (1);
512 + /* now correct the endianness of the byte array */
513 + ltoh16_buf(buf, nw * 2);
514 + }
515 +
516 + return (0);
517 +}
518 +
519 +/*
520 + * Initialize nonvolatile variable table from sprom.
521 + * Return 0 on success, nonzero on error.
522 + */
523 +
524 +static int
525 +initvars_srom_pci(void *curmap, char **vars, int *count)
526 +{
527 + uint16 w, b[64];
528 + uint8 sromrev;
529 + struct ether_addr ea;
530 + char eabuf[32];
531 + int c, woff, i;
532 + char *vp, *base;
533 +
534 + if (sprom_read_pci((void *)((uint)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof (b), TRUE))
535 + return (-1);
536 +
537 + /* top word of sprom contains version and crc8 */
538 + sromrev = b[63] & 0xff;
539 + if ((sromrev != 1) && (sromrev != 2)) {
540 + return (-2);
541 + }
542 +
543 + ASSERT(vars);
544 + ASSERT(count);
545 +
546 + base = vp = MALLOC(VARS_MAX);
547 + ASSERT(vp);
548 +
549 + vp += sprintf(vp, "sromrev=%d", sromrev);
550 + vp++;
551 +
552 + if (sromrev >= 2) {
553 + /* New section takes over the 4th hardware function space */
554 +
555 + /* Word 28 is boardflags2 */
556 + vp += sprintf(vp, "boardflags2=%d", b[28]);
557 + vp++;
558 +
559 + /* Word 29 is max power 11a high/low */
560 + w = b[29];
561 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
562 + vp++;
563 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
564 + vp++;
565 +
566 + /* Words 30-32 set the 11alow pa settings,
567 + * 33-35 are the 11ahigh ones.
568 + */
569 + for (i = 0; i < 3; i++) {
570 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
571 + vp++;
572 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
573 + vp++;
574 + }
575 + w = b[59];
576 + if (w == 0)
577 + vp += sprintf(vp, "ccode=");
578 + else
579 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
580 + vp++;
581 +
582 + }
583 +
584 + /* parameter section of sprom starts at byte offset 72 */
585 + woff = 72/2;
586 +
587 + /* first 6 bytes are il0macaddr */
588 + ea.octet[0] = (b[woff] >> 8) & 0xff;
589 + ea.octet[1] = b[woff] & 0xff;
590 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
591 + ea.octet[3] = b[woff+1] & 0xff;
592 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
593 + ea.octet[5] = b[woff+2] & 0xff;
594 + woff += ETHER_ADDR_LEN/2 ;
595 + bcm_ether_ntoa((uchar*)&ea, eabuf);
596 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
597 + vp++;
598 +
599 + /* next 6 bytes are et0macaddr */
600 + ea.octet[0] = (b[woff] >> 8) & 0xff;
601 + ea.octet[1] = b[woff] & 0xff;
602 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
603 + ea.octet[3] = b[woff+1] & 0xff;
604 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
605 + ea.octet[5] = b[woff+2] & 0xff;
606 + woff += ETHER_ADDR_LEN/2 ;
607 + bcm_ether_ntoa((uchar*)&ea, eabuf);
608 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
609 + vp++;
610 +
611 + /* next 6 bytes are et1macaddr */
612 + ea.octet[0] = (b[woff] >> 8) & 0xff;
613 + ea.octet[1] = b[woff] & 0xff;
614 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
615 + ea.octet[3] = b[woff+1] & 0xff;
616 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
617 + ea.octet[5] = b[woff+2] & 0xff;
618 + woff += ETHER_ADDR_LEN/2 ;
619 + bcm_ether_ntoa((uchar*)&ea, eabuf);
620 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
621 + vp++;
622 +
623 + /*
624 + * Enet phy settings one or two singles or a dual
625 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
626 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
627 + * Bit 14 : Mdio for enet0
628 + * Bit 15 : Mdio for enet1
629 + */
630 + w = b[woff];
631 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
632 + vp++;
633 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
634 + vp++;
635 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
636 + vp++;
637 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
638 + vp++;
639 +
640 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
641 + w = b[46];
642 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
643 + vp++;
644 +
645 + if (sromrev > 1)
646 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
647 + else
648 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
649 + vp++;
650 +
651 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
652 + vp++;
653 +
654 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
655 + vp++;
656 +
657 + /* Words 47-49 set the (wl) pa settings */
658 + woff = 47;
659 +
660 + for (i = 0; i < 3; i++) {
661 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
662 + vp++;
663 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
664 + vp++;
665 + }
666 +
667 + /*
668 + * Words 50-51 set the customer-configured wl led behavior.
669 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
670 + * LED behavior values defined in wlioctl.h .
671 + */
672 + w = b[50];
673 + if ((w != 0) && (w != 0xffff)) {
674 + /* gpio0 */
675 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
676 + vp++;
677 +
678 + /* gpio1 */
679 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
680 + vp++;
681 + }
682 + w = b[51];
683 + if ((w != 0) && (w != 0xffff)) {
684 + /* gpio2 */
685 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
686 + vp++;
687 +
688 + /* gpio3 */
689 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
690 + vp++;
691 + }
692 +
693 + /* Word 52 is max power 0/1 */
694 + w = b[52];
695 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
696 + vp++;
697 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
698 + vp++;
699 +
700 + /* Word 56 is idle tssi target 0/1 */
701 + w = b[56];
702 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
703 + vp++;
704 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
705 + vp++;
706 +
707 + /* Word 57 is boardflags, if not programmed make it zero */
708 + w = b[57];
709 + if (w == 0xffff) w = 0;
710 + vp += sprintf(vp, "boardflags=%d", w);
711 + vp++;
712 +
713 + /* Word 58 is antenna gain 0/1 */
714 + w = b[58];
715 + vp += sprintf(vp, "ag0=%d", w & 0xff);
716 + vp++;
717 +
718 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
719 + vp++;
720 +
721 + if (sromrev == 1) {
722 + /* set the oem string */
723 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
724 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
725 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
726 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
727 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
728 + vp++;
729 + }
730 +
731 + /* final nullbyte terminator */
732 + *vp++ = '\0';
733 +
734 + c = vp - base;
735 + ASSERT(c <= VARS_MAX);
736 +
737 + if (c == VARS_MAX) {
738 + *vars = base;
739 + } else {
740 + vp = MALLOC(c);
741 + ASSERT(vp);
742 + bcopy(base, vp, c);
743 + MFREE(base, VARS_MAX);
744 + *vars = vp;
745 + }
746 + *count = c;
747 +
748 + return (0);
749 +}
750 +
751 +/*
752 + * Read the cis and call parsecis to initialize the vars.
753 + * Return 0 on success, nonzero on error.
754 + */
755 +static int
756 +initvars_cis_pcmcia(void *osh, char **vars, int *count)
757 +{
758 + uint8 *cis = NULL;
759 + int rc;
760 +
761 + if ((cis = MALLOC(CIS_SIZE)) == NULL)
762 + return (-1);
763 +
764 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, CIS_SIZE);
765 +
766 + rc = srom_parsecis(cis, vars, count);
767 +
768 + MFREE(cis, CIS_SIZE);
769 +
770 + return (rc);
771 +}
772 +
773 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmutils.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmutils.c
774 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
775 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-09-16 10:29:18.164593464 +0200
776 @@ -0,0 +1,691 @@
777 +/*
778 + * Misc useful OS-independent routines.
779 + *
780 + * Copyright 2001-2003, Broadcom Corporation
781 + * All Rights Reserved.
782 + *
783 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
784 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
785 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
786 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
787 + * $Id: bcmutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
788 + */
789 +
790 +#include <typedefs.h>
791 +#include <osl.h>
792 +#include <bcmutils.h>
793 +#include <bcmendian.h>
794 +#include <bcmnvram.h>
795 +
796 +unsigned char bcm_ctype[] = {
797 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
798 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
799 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
800 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
801 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
802 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
803 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
804 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
805 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
806 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
807 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
808 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
809 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
810 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
811 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
812 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
813 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
814 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
815 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
816 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
817 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
818 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
819 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
820 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
821 +};
822 +
823 +uchar
824 +bcm_toupper(uchar c)
825 +{
826 + if (bcm_islower(c))
827 + c -= 'a'-'A';
828 + return (c);
829 +}
830 +
831 +ulong
832 +bcm_strtoul(char *cp, char **endp, uint base)
833 +{
834 + ulong result, value;
835 + bool minus;
836 +
837 + minus = FALSE;
838 +
839 + while (bcm_isspace(*cp))
840 + cp++;
841 +
842 + if (cp[0] == '+')
843 + cp++;
844 + else if (cp[0] == '-') {
845 + minus = TRUE;
846 + cp++;
847 + }
848 +
849 + if (base == 0) {
850 + if (cp[0] == '0') {
851 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
852 + base = 16;
853 + cp = &cp[2];
854 + } else {
855 + base = 8;
856 + cp = &cp[1];
857 + }
858 + } else
859 + base = 10;
860 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
861 + cp = &cp[2];
862 + }
863 +
864 + result = 0;
865 +
866 + while (bcm_isxdigit(*cp) &&
867 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
868 + result = result*base + value;
869 + cp++;
870 + }
871 +
872 + if (minus)
873 + result = (ulong)(result * -1);
874 +
875 + if (endp)
876 + *endp = (char *)cp;
877 +
878 + return (result);
879 +}
880 +
881 +uint
882 +bcm_atoi(char *s)
883 +{
884 + uint n;
885 +
886 + n = 0;
887 +
888 + while (bcm_isdigit(*s))
889 + n = (n * 10) + *s++ - '0';
890 + return (n);
891 +}
892 +
893 +void
894 +deadbeef(char *p, uint len)
895 +{
896 + static uchar meat[] = { 0xde, 0xad, 0xbe, 0xef };
897 +
898 + while (len-- > 0) {
899 + *p = meat[((uint)p) & 3];
900 + p++;
901 + }
902 +}
903 +
904 +/* pretty hex print a contiguous buffer */
905 +void
906 +prhex(char *msg, uchar *buf, uint nbytes)
907 +{
908 + char line[256];
909 + char* p;
910 + uint i;
911 +
912 + if (msg && (msg[0] != '\0'))
913 + printf("%s: ", msg);
914 +
915 + p = line;
916 + for (i = 0; i < nbytes; i++) {
917 + if (i % 16 == 0) {
918 + p += sprintf(p, "%04d: ", i); /* line prefix */
919 + }
920 + p += sprintf(p, "%02x ", buf[i]);
921 + if (i % 16 == 15) {
922 + printf("%s\n", line); /* flush line */
923 + p = line;
924 + }
925 + }
926 +
927 + /* flush last partial line */
928 + if (p != line)
929 + printf("%s\n", line);
930 +}
931 +
932 +/* pretty hex print a pkt buffer chain */
933 +void
934 +prpkt(char *msg, void *drv, void *p0)
935 +{
936 + void *p;
937 +
938 + if (msg && (msg[0] != '\0'))
939 + printf("%s: ", msg);
940 +
941 + for (p = p0; p; p = PKTNEXT(drv, p))
942 + prhex(NULL, PKTDATA(drv, p), PKTLEN(drv, p));
943 +}
944 +
945 +/* copy a pkt buffer chain into a buffer */
946 +uint
947 +pktcopy(void *drv, void *p, uint offset, int len, uchar *buf)
948 +{
949 + uint n, ret = 0;
950 +
951 + if (len < 0)
952 + len = 4096; /* "infinite" */
953 +
954 + /* skip 'offset' bytes */
955 + for (; p && offset; p = PKTNEXT(drv, p)) {
956 + if (offset < (uint)PKTLEN(drv, p))
957 + break;
958 + offset -= PKTLEN(drv, p);
959 + }
960 +
961 + if (!p)
962 + return 0;
963 +
964 + /* copy the data */
965 + for (; p && len; p = PKTNEXT(drv, p)) {
966 + n = MIN((uint)PKTLEN(drv, p) - offset, (uint)len);
967 + bcopy(PKTDATA(drv, p) + offset, buf, n);
968 + buf += n;
969 + len -= n;
970 + ret += n;
971 + offset = 0;
972 + }
973 +
974 + return ret;
975 +}
976 +
977 +/* return total length of buffer chain */
978 +uint
979 +pkttotlen(void *drv, void *p)
980 +{
981 + uint total;
982 +
983 + total = 0;
984 + for (; p; p = PKTNEXT(drv, p))
985 + total += PKTLEN(drv, p);
986 + return (total);
987 +}
988 +
989 +
990 +uchar*
991 +bcm_ether_ntoa(char *ea, char *buf)
992 +{
993 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
994 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
995 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
996 + return (buf);
997 +}
998 +
999 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
1000 +int
1001 +bcm_ether_atoe(char *p, char *ea)
1002 +{
1003 + int i = 0;
1004 +
1005 + for (;;) {
1006 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
1007 + if (!*p++ || i == 6)
1008 + break;
1009 + }
1010 +
1011 + return (i == 6);
1012 +}
1013 +
1014 +/*
1015 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
1016 + * triples, returning a pointer to the substring whose first element
1017 + * matches tag. Stop parsing when we see an element whose ID is greater
1018 + * than the target key.
1019 + */
1020 +bcm_tlv_t *
1021 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
1022 +{
1023 + bcm_tlv_t *elt;
1024 + int totlen;
1025 +
1026 + elt = (bcm_tlv_t*)buf;
1027 + totlen = buflen;
1028 +
1029 + /* find tagged parameter */
1030 + while (totlen >= 2) {
1031 + uint id = elt->id;
1032 + int len = elt->len;
1033 +
1034 + /* Punt if we start seeing IDs > than target key */
1035 + if (id > key)
1036 + return(NULL);
1037 +
1038 + /* validate remaining totlen */
1039 + if ((id == key) && (totlen >= (len + 2)))
1040 + return (elt);
1041 +
1042 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
1043 + totlen -= (len + 2);
1044 + }
1045 + return NULL;
1046 +}
1047 +
1048 +
1049 +/*
1050 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
1051 + * triples, returning a pointer to the substring whose first element
1052 + * matches tag
1053 + */
1054 +bcm_tlv_t *
1055 +bcm_parse_tlvs(void *buf, int buflen, uint key)
1056 +{
1057 + bcm_tlv_t *elt;
1058 + int totlen;
1059 +
1060 + elt = (bcm_tlv_t*)buf;
1061 + totlen = buflen;
1062 +
1063 + /* find tagged parameter */
1064 + while (totlen >= 2) {
1065 + int len = elt->len;
1066 +
1067 + /* validate remaining totlen */
1068 + if ((elt->id == key) && (totlen >= (len + 2)))
1069 + return (elt);
1070 +
1071 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
1072 + totlen -= (len + 2);
1073 + }
1074 +
1075 + return NULL;
1076 +}
1077 +
1078 +void
1079 +pktqinit(struct pktq *q, int maxlen)
1080 +{
1081 + q->head = q->tail = NULL;
1082 + q->maxlen = maxlen;
1083 + q->len = 0;
1084 +}
1085 +
1086 +void
1087 +pktenq(struct pktq *q, void *p, bool lifo)
1088 +{
1089 + ASSERT(PKTLINK(p) == NULL);
1090 +
1091 + PKTSETLINK(p, NULL);
1092 +
1093 + if (q->tail == NULL) {
1094 + ASSERT(q->head == NULL);
1095 + q->head = q->tail = p;
1096 + }
1097 + else {
1098 + ASSERT(q->head);
1099 + ASSERT(PKTLINK(q->tail) == NULL);
1100 + if (lifo) {
1101 + PKTSETLINK(p, q->head);
1102 + q->head = p;
1103 + } else {
1104 + PKTSETLINK(q->tail, p);
1105 + q->tail = p;
1106 + }
1107 + }
1108 + q->len++;
1109 +}
1110 +
1111 +void*
1112 +pktdeq(struct pktq *q)
1113 +{
1114 + void *p;
1115 +
1116 + if ((p = q->head)) {
1117 + ASSERT(q->tail);
1118 + q->head = PKTLINK(p);
1119 + PKTSETLINK(p, NULL);
1120 + q->len--;
1121 + if (q->head == NULL)
1122 + q->tail = NULL;
1123 + }
1124 + else {
1125 + ASSERT(q->tail == NULL);
1126 + }
1127 +
1128 + return (p);
1129 +}
1130 +
1131 +/*******************************************************************************
1132 + * crc8
1133 + *
1134 + * Computes a crc8 over the input data using the polynomial:
1135 + *
1136 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1137 + *
1138 + * The caller provides the initial value (either CRC8_INIT_VALUE
1139 + * or the previous returned value) to allow for processing of
1140 + * discontiguous blocks of data. When generating the CRC the
1141 + * caller is responsible for complementing the final return value
1142 + * and inserting it into the byte stream. When checking, a final
1143 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1144 + *
1145 + * Reference: Dallas Semiconductor Application Note 27
1146 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1147 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1148 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1149 + *
1150 + ******************************************************************************/
1151 +
1152 +static uint8 crc8_table[256] = {
1153 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1154 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1155 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1156 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1157 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1158 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1159 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1160 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1161 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1162 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1163 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1164 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1165 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1166 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1167 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1168 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1169 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1170 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1171 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1172 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1173 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1174 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1175 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1176 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1177 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1178 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1179 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1180 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1181 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1182 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1183 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1184 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1185 +};
1186 +
1187 +/*
1188 + * Search the name=value vars for a specific one and return its value.
1189 + * Returns NULL if not found.
1190 + */
1191 +char*
1192 +getvar(char *vars, char *name)
1193 +{
1194 + char *s;
1195 + int len;
1196 +
1197 + len = strlen(name);
1198 +
1199 + /* first look in vars[] */
1200 + for (s = vars; s && *s; ) {
1201 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
1202 + return (&s[len+1]);
1203 +
1204 + while (*s++)
1205 + ;
1206 + }
1207 +
1208 + /* then query nvram */
1209 + return (nvram_get(name));
1210 +}
1211 +
1212 +/*
1213 + * Search the vars for a specific one and return its value as
1214 + * an integer. Returns 0 if not found.
1215 + */
1216 +int
1217 +getintvar(char *vars, char *name)
1218 +{
1219 + char *val;
1220 +
1221 + if ((val = getvar(vars, name)) == NULL)
1222 + return (0);
1223 +
1224 + return (bcm_strtoul(val, NULL, 0));
1225 +}
1226 +
1227 +void
1228 +bcm_mdelay(uint ms)
1229 +{
1230 + uint i;
1231 +
1232 + for (i = 0; i < ms; i++) {
1233 + OSL_DELAY(1000);
1234 + }
1235 +}
1236 +
1237 +#define CRC_INNER_LOOP(n, c, x) \
1238 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1239 +
1240 +uint8
1241 +crc8(
1242 + uint8 *pdata, /* pointer to array of data to process */
1243 + uint nbytes, /* number of input data bytes to process */
1244 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1245 +)
1246 +{
1247 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1248 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
1249 + while (nbytes-- > 0)
1250 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1251 +
1252 + return crc;
1253 +}
1254 +
1255 +/*******************************************************************************
1256 + * crc16
1257 + *
1258 + * Computes a crc16 over the input data using the polynomial:
1259 + *
1260 + * x^16 + x^12 +x^5 + 1
1261 + *
1262 + * The caller provides the initial value (either CRC16_INIT_VALUE
1263 + * or the previous returned value) to allow for processing of
1264 + * discontiguous blocks of data. When generating the CRC the
1265 + * caller is responsible for complementing the final return value
1266 + * and inserting it into the byte stream. When checking, a final
1267 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
1268 + *
1269 + * Reference: Dallas Semiconductor Application Note 27
1270 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1271 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1272 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1273 + *
1274 + ******************************************************************************/
1275 +
1276 +static uint16 crc16_table[256] = {
1277 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
1278 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
1279 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
1280 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
1281 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
1282 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
1283 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
1284 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
1285 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
1286 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
1287 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
1288 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
1289 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
1290 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
1291 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
1292 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
1293 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
1294 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
1295 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
1296 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
1297 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
1298 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
1299 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
1300 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
1301 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
1302 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
1303 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
1304 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
1305 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
1306 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
1307 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
1308 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
1309 +};
1310 +
1311 +uint16
1312 +crc16(
1313 + uint8 *pdata, /* pointer to array of data to process */
1314 + uint nbytes, /* number of input data bytes to process */
1315 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
1316 +)
1317 +{
1318 + while (nbytes-- > 0)
1319 + CRC_INNER_LOOP(16, crc, *pdata++);
1320 + return crc;
1321 +}
1322 +
1323 +static uint32 crc32_table[256] = {
1324 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
1325 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
1326 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
1327 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
1328 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
1329 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
1330 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
1331 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
1332 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
1333 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
1334 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
1335 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
1336 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
1337 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
1338 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
1339 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
1340 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
1341 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
1342 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
1343 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
1344 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
1345 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
1346 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
1347 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
1348 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
1349 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
1350 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
1351 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
1352 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
1353 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
1354 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
1355 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
1356 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
1357 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
1358 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
1359 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
1360 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
1361 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
1362 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
1363 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
1364 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
1365 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
1366 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
1367 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
1368 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
1369 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
1370 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
1371 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
1372 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
1373 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
1374 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
1375 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
1376 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
1377 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
1378 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
1379 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
1380 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
1381 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
1382 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
1383 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
1384 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
1385 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
1386 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
1387 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
1388 +};
1389 +
1390 +uint32
1391 +crc32(
1392 + uint8 *pdata, /* pointer to array of data to process */
1393 + uint nbytes, /* number of input data bytes to process */
1394 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
1395 +)
1396 +{
1397 + uint8 *pend;
1398 +#ifdef __mips__
1399 + uint8 tmp[4];
1400 + ulong *tptr = (ulong *)tmp;
1401 +
1402 + /* in case the beginning of the buffer isn't aligned */
1403 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
1404 + nbytes -= (pend - pdata);
1405 + while (pdata < pend)
1406 + CRC_INNER_LOOP(32, crc, *pdata++);
1407 +
1408 + /* handle bulk of data as 32-bit words */
1409 + pend = pdata + (nbytes & 0xfffffffc);
1410 + while (pdata < pend) {
1411 + *tptr = *((ulong *)pdata)++;
1412 + CRC_INNER_LOOP(32, crc, tmp[0]);
1413 + CRC_INNER_LOOP(32, crc, tmp[1]);
1414 + CRC_INNER_LOOP(32, crc, tmp[2]);
1415 + CRC_INNER_LOOP(32, crc, tmp[3]);
1416 + }
1417 +
1418 + /* 1-3 bytes at end of buffer */
1419 + pend = pdata + (nbytes & 0x03);
1420 + while (pdata < pend)
1421 + CRC_INNER_LOOP(32, crc, *pdata++);
1422 +#else
1423 + pend = pdata + nbytes;
1424 + while (pdata < pend)
1425 + CRC_INNER_LOOP(32, crc, *pdata++);
1426 +#endif
1427 +
1428 + return crc;
1429 +}
1430 +
1431 +#ifdef notdef
1432 +#define CLEN 1499
1433 +#define CBUFSIZ (CLEN+4)
1434 +#define CNBUFS 5
1435 +
1436 +void testcrc32(void)
1437 +{
1438 + uint j,k,l;
1439 + uint8 *buf;
1440 + uint len[CNBUFS];
1441 + uint32 crcr;
1442 + uint32 crc32tv[CNBUFS] =
1443 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
1444 +
1445 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
1446 +
1447 + /* step through all possible alignments */
1448 + for (l=0;l<=4;l++) {
1449 + for (j=0; j<CNBUFS; j++) {
1450 + len[j] = CLEN;
1451 + for (k=0; k<len[j]; k++)
1452 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
1453 + }
1454 +
1455 + for (j=0; j<CNBUFS; j++) {
1456 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
1457 + ASSERT(crcr == crc32tv[j]);
1458 + }
1459 + }
1460 +
1461 + MFREE(buf, CBUFSIZ*CNBUFS);
1462 + return;
1463 +}
1464 +#endif
1465 +
1466 +
1467 +
1468 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/hnddma.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/hnddma.c
1469 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/hnddma.c 1970-01-01 01:00:00.000000000 +0100
1470 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/hnddma.c 2005-09-16 10:29:18.165593312 +0200
1471 @@ -0,0 +1,763 @@
1472 +/*
1473 + * Generic Broadcom Home Networking Division (HND) DMA module.
1474 + * This supports the following chips: BCM42xx, 44xx, 47xx .
1475 + *
1476 + * Copyright 2001-2003, Broadcom Corporation
1477 + * All Rights Reserved.
1478 + *
1479 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1480 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1481 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1482 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1483 + *
1484 + * $Id: hnddma.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
1485 + */
1486 +
1487 +#include <typedefs.h>
1488 +#include <osl.h>
1489 +#include <bcmendian.h>
1490 +#include <bcmutils.h>
1491 +
1492 +struct dma_info; /* forward declaration */
1493 +#define di_t struct dma_info
1494 +#include <hnddma.h>
1495 +
1496 +/* debug/trace */
1497 +#define DMA_ERROR(args)
1498 +#define DMA_TRACE(args)
1499 +
1500 +/* default dma message level(if input msg_level pointer is null in dma_attach()) */
1501 +static uint dma_msg_level = 0;
1502 +
1503 +#define MAXNAMEL 8
1504 +#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
1505 +
1506 +/* dma engine software state */
1507 +typedef struct dma_info {
1508 + hnddma_t hnddma; /* exported structure */
1509 + uint *msg_level; /* message level pointer */
1510 +
1511 + char name[MAXNAMEL]; /* callers name for diag msgs */
1512 + void *drv; /* driver handle */
1513 + void *dev; /* device handle */
1514 + dmaregs_t *regs; /* dma engine registers */
1515 +
1516 + dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
1517 + uint txin; /* index of next descriptor to reclaim */
1518 + uint txout; /* index of next descriptor to post */
1519 + uint txavail; /* # free tx descriptors */
1520 + void *txp[MAXDD]; /* parallel array of pointers to packets */
1521 + ulong txdpa; /* physical address of descriptor ring */
1522 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
1523 +
1524 + dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
1525 + uint rxin; /* index of next descriptor to reclaim */
1526 + uint rxout; /* index of next descriptor to post */
1527 + void *rxp[MAXDD]; /* parallel array of pointers to packets */
1528 + ulong rxdpa; /* physical address of descriptor ring */
1529 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
1530 +
1531 + /* tunables */
1532 + uint ntxd; /* # tx descriptors */
1533 + uint nrxd; /* # rx descriptors */
1534 + uint rxbufsize; /* rx buffer size in bytes */
1535 + uint nrxpost; /* # rx buffers to keep posted */
1536 + uint rxoffset; /* rxcontrol offset */
1537 + uint ddoffset; /* add to get dma address of descriptor ring */
1538 + uint dataoffset; /* add to get dma address of data buffer */
1539 +} dma_info_t;
1540 +
1541 +/* descriptor bumping macros */
1542 +#define NEXTTXD(i) ((i + 1) & (di->ntxd - 1))
1543 +#define PREVTXD(i) ((i - 1) & (di->ntxd - 1))
1544 +#define NEXTRXD(i) ((i + 1) & (di->nrxd - 1))
1545 +#define NTXDACTIVE(h, t) ((t - h) & (di->ntxd - 1))
1546 +#define NRXDACTIVE(h, t) ((t - h) & (di->nrxd - 1))
1547 +
1548 +/* macros to convert between byte offsets and indexes */
1549 +#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
1550 +#define I2B(index) ((index) * sizeof (dmadd_t))
1551 +
1552 +void*
1553 +dma_attach(void *drv, void *dev, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
1554 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
1555 +{
1556 + dma_info_t *di;
1557 + void *va;
1558 +
1559 + ASSERT(ntxd <= MAXDD);
1560 + ASSERT(nrxd <= MAXDD);
1561 +
1562 + /* allocate private info structure */
1563 + if ((di = MALLOC(sizeof (dma_info_t))) == NULL)
1564 + return (NULL);
1565 + bzero((char*)di, sizeof (dma_info_t));
1566 +
1567 + /* set message level */
1568 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
1569 +
1570 + DMA_TRACE(("%s: dma_attach: drv 0x%x dev 0x%x regs 0x%x ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, (uint)drv, (uint)dev, (uint)regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
1571 +
1572 + /* make a private copy of our callers name */
1573 + strncpy(di->name, name, MAXNAMEL);
1574 + di->name[MAXNAMEL-1] = '\0';
1575 +
1576 + di->drv = drv;
1577 + di->dev = dev;
1578 + di->regs = regs;
1579 +
1580 + /* allocate transmit descriptor ring */
1581 + if (ntxd) {
1582 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->txdpa)) == NULL)
1583 + goto fail;
1584 + di->txd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1585 + di->txdalign = ((uint)di->txd - (uint)va);
1586 + di->txdpa = di->txdpa + di->txdalign;
1587 + ASSERT(ISALIGNED(di->txd, DMARINGALIGN));
1588 + }
1589 +
1590 + /* allocate receive descriptor ring */
1591 + if (nrxd) {
1592 + if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->rxdpa)) == NULL)
1593 + goto fail;
1594 + di->rxd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
1595 + di->rxdalign = ((uint)di->rxd - (uint)va);
1596 + di->rxdpa = di->rxdpa + di->rxdalign;
1597 + ASSERT(ISALIGNED(di->rxd, DMARINGALIGN));
1598 + }
1599 +
1600 + /* save tunables */
1601 + di->ntxd = ntxd;
1602 + di->nrxd = nrxd;
1603 + di->rxbufsize = rxbufsize;
1604 + di->nrxpost = nrxpost;
1605 + di->rxoffset = rxoffset;
1606 + di->ddoffset = ddoffset;
1607 + di->dataoffset = dataoffset;
1608 +
1609 + return ((void*)di);
1610 +
1611 +fail:
1612 + dma_detach((void*)di);
1613 + return (NULL);
1614 +}
1615 +
1616 +/* may be called with core in reset */
1617 +void
1618 +dma_detach(dma_info_t *di)
1619 +{
1620 + if (di == NULL)
1621 + return;
1622 +
1623 + DMA_TRACE(("%s: dma_detach\n", di->name));
1624 +
1625 + /* shouldn't be here if descriptors are unreclaimed */
1626 + ASSERT(di->txin == di->txout);
1627 + ASSERT(di->rxin == di->rxout);
1628 +
1629 + /* free dma descriptor rings */
1630 + if (di->txd)
1631 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->txd - di->txdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->txdpa);
1632 + if (di->rxd)
1633 + DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->rxd - di->rxdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->rxdpa);
1634 +
1635 + /* free our private info structure */
1636 + MFREE((void*)di, sizeof (dma_info_t));
1637 +}
1638 +
1639 +
1640 +void
1641 +dma_txreset(dma_info_t *di)
1642 +{
1643 + uint32 status;
1644 +
1645 + DMA_TRACE(("%s: dma_txreset\n", di->name));
1646 +
1647 + /* suspend tx DMA first */
1648 + W_REG(&di->regs->xmtcontrol, XC_SE);
1649 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
1650 + status != XS_XS_IDLE &&
1651 + status != XS_XS_STOPPED,
1652 + 10000);
1653 +
1654 + W_REG(&di->regs->xmtcontrol, 0);
1655 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
1656 + 10000);
1657 +
1658 + if (status != XS_XS_DISABLED) {
1659 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
1660 + }
1661 +
1662 + /* wait for the last transaction to complete */
1663 + OSL_DELAY(300);
1664 +}
1665 +
1666 +void
1667 +dma_rxreset(dma_info_t *di)
1668 +{
1669 + uint32 status;
1670 +
1671 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
1672 +
1673 + W_REG(&di->regs->rcvcontrol, 0);
1674 + SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
1675 + 10000);
1676 +
1677 + if (status != RS_RS_DISABLED) {
1678 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
1679 + }
1680 +}
1681 +
1682 +void
1683 +dma_txinit(dma_info_t *di)
1684 +{
1685 + DMA_TRACE(("%s: dma_txinit\n", di->name));
1686 +
1687 + di->txin = di->txout = 0;
1688 + di->txavail = di->ntxd - 1;
1689 +
1690 + /* clear tx descriptor ring */
1691 + BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
1692 +
1693 + W_REG(&di->regs->xmtcontrol, XC_XE);
1694 + W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
1695 +}
1696 +
1697 +bool
1698 +dma_txenabled(dma_info_t *di)
1699 +{
1700 + uint32 xc;
1701 +
1702 + /* If the chip is dead, it is not enabled :-) */
1703 + xc = R_REG(&di->regs->xmtcontrol);
1704 + return ((xc != 0xffffffff) && (xc & XC_XE));
1705 +}
1706 +
1707 +void
1708 +dma_txsuspend(dma_info_t *di)
1709 +{
1710 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1711 + OR_REG(&di->regs->xmtcontrol, XC_SE);
1712 +}
1713 +
1714 +void
1715 +dma_txresume(dma_info_t *di)
1716 +{
1717 + DMA_TRACE(("%s: dma_txresume\n", di->name));
1718 + AND_REG(&di->regs->xmtcontrol, ~XC_SE);
1719 +}
1720 +
1721 +bool
1722 +dma_txsuspended(dma_info_t *di)
1723 +{
1724 + uint32 xc;
1725 + uint32 xs;
1726 +
1727 + xc = R_REG(&di->regs->xmtcontrol);
1728 + if (xc & XC_SE) {
1729 + xs = R_REG(&di->regs->xmtstatus);
1730 + return ((xs & XS_XS_MASK) == XS_XS_IDLE);
1731 + }
1732 + return 0;
1733 +}
1734 +
1735 +bool
1736 +dma_txstopped(dma_info_t *di)
1737 +{
1738 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
1739 +}
1740 +
1741 +bool
1742 +dma_rxstopped(dma_info_t *di)
1743 +{
1744 + return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
1745 +}
1746 +
1747 +void
1748 +dma_fifoloopbackenable(dma_info_t *di)
1749 +{
1750 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
1751 + OR_REG(&di->regs->xmtcontrol, XC_LE);
1752 +}
1753 +
1754 +void
1755 +dma_rxinit(dma_info_t *di)
1756 +{
1757 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
1758 +
1759 + di->rxin = di->rxout = 0;
1760 +
1761 + /* clear rx descriptor ring */
1762 + BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
1763 +
1764 + dma_rxenable(di);
1765 + W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
1766 +}
1767 +
1768 +void
1769 +dma_rxenable(dma_info_t *di)
1770 +{
1771 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
1772 + W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
1773 +}
1774 +
1775 +bool
1776 +dma_rxenabled(dma_info_t *di)
1777 +{
1778 + uint32 rc;
1779 +
1780 + rc = R_REG(&di->regs->rcvcontrol);
1781 + return ((rc != 0xffffffff) && (rc & RC_RE));
1782 +}
1783 +
1784 +/*
1785 + * The BCM47XX family supports full 32bit dma engine buffer addressing so
1786 + * dma buffers can cross 4 Kbyte page boundaries.
1787 + */
1788 +int
1789 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
1790 +{
1791 + void *p, *next;
1792 + uchar *data;
1793 + uint len;
1794 + uint txout;
1795 + uint32 ctrl;
1796 + uint32 pa;
1797 +
1798 + DMA_TRACE(("%s: dma_txfast\n", di->name));
1799 +
1800 + txout = di->txout;
1801 + ctrl = 0;
1802 +
1803 + /*
1804 + * Walk the chain of packet buffers
1805 + * allocating and initializing transmit descriptor entries.
1806 + */
1807 + for (p = p0; p; p = next) {
1808 + data = PKTDATA(di->drv, p);
1809 + len = PKTLEN(di->drv, p);
1810 + next = PKTNEXT(di->drv, p);
1811 +
1812 + /* return nonzero if out of tx descriptors */
1813 + if (NEXTTXD(txout) == di->txin)
1814 + goto outoftxd;
1815 +
1816 + if (len == 0)
1817 + continue;
1818 +
1819 + /* get physical address of buffer start */
1820 + pa = (uint32) DMA_MAP(di->dev, data, len, DMA_TX, p);
1821 +
1822 + /* build the descriptor control value */
1823 + ctrl = len & CTRL_BC_MASK;
1824 +
1825 + ctrl |= coreflags;
1826 +
1827 + if (p == p0)
1828 + ctrl |= CTRL_SOF;
1829 + if (next == NULL)
1830 + ctrl |= (CTRL_IOC | CTRL_EOF);
1831 + if (txout == (di->ntxd - 1))
1832 + ctrl |= CTRL_EOT;
1833 +
1834 + /* init the tx descriptor */
1835 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1836 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1837 +
1838 + ASSERT(di->txp[txout] == NULL);
1839 +
1840 + txout = NEXTTXD(txout);
1841 + }
1842 +
1843 + /* if last txd eof not set, fix it */
1844 + if (!(ctrl & CTRL_EOF))
1845 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1846 +
1847 + /* save the packet */
1848 + di->txp[PREVTXD(txout)] = p0;
1849 +
1850 + /* bump the tx descriptor index */
1851 + di->txout = txout;
1852 +
1853 + /* kick the chip */
1854 + W_REG(&di->regs->xmtptr, I2B(txout));
1855 +
1856 + /* tx flow control */
1857 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1858 +
1859 + return (0);
1860 +
1861 +outoftxd:
1862 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
1863 + PKTFREE(di->drv, p0, TRUE);
1864 + di->txavail = 0;
1865 + di->hnddma.txnobuf++;
1866 + return (-1);
1867 +}
1868 +
1869 +#define PAGESZ 4096
1870 +#define PAGEBASE(x) ((uint)(x) & ~4095)
1871 +
1872 +/*
1873 + * Just like above except go through the extra effort of splitting
1874 + * buffers that cross 4Kbyte boundaries into multiple tx descriptors.
1875 + */
1876 +int
1877 +dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
1878 +{
1879 + void *p, *next;
1880 + uchar *data;
1881 + uint plen, len;
1882 + uchar *page, *start, *end;
1883 + uint txout;
1884 + uint32 ctrl;
1885 + uint32 pa;
1886 +
1887 + DMA_TRACE(("%s: dma_tx\n", di->name));
1888 +
1889 + txout = di->txout;
1890 + ctrl = 0;
1891 +
1892 + /*
1893 + * Walk the chain of packet buffers
1894 + * splitting those that cross 4 Kbyte boundaries
1895 + * allocating and initializing transmit descriptor entries.
1896 + */
1897 + for (p = p0; p; p = next) {
1898 + data = PKTDATA(di->drv, p);
1899 + plen = PKTLEN(di->drv, p);
1900 + next = PKTNEXT(di->drv, p);
1901 +
1902 + if (plen == 0)
1903 + continue;
1904 +
1905 + for (page = (uchar*)PAGEBASE(data);
1906 + page <= (uchar*)PAGEBASE(data + plen - 1);
1907 + page += PAGESZ) {
1908 +
1909 + /* return nonzero if out of tx descriptors */
1910 + if (NEXTTXD(txout) == di->txin)
1911 + goto outoftxd;
1912 +
1913 + start = (page == (uchar*)PAGEBASE(data))? data: page;
1914 + end = (page == (uchar*)PAGEBASE(data + plen))?
1915 + (data + plen): (page + PAGESZ);
1916 + len = end - start;
1917 +
1918 + /* build the descriptor control value */
1919 + ctrl = len & CTRL_BC_MASK;
1920 +
1921 + ctrl |= coreflags;
1922 +
1923 + if ((p == p0) && (start == data))
1924 + ctrl |= CTRL_SOF;
1925 + if ((next == NULL) && (end == (data + plen)))
1926 + ctrl |= (CTRL_IOC | CTRL_EOF);
1927 + if (txout == (di->ntxd - 1))
1928 + ctrl |= CTRL_EOT;
1929 +
1930 + /* get physical address of buffer start */
1931 + pa = (uint32) DMA_MAP(di->dev, start, len, DMA_TX, p);
1932 +
1933 + /* init the tx descriptor */
1934 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
1935 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
1936 +
1937 + ASSERT(di->txp[txout] == NULL);
1938 +
1939 + txout = NEXTTXD(txout);
1940 + }
1941 + }
1942 +
1943 + /* if last txd eof not set, fix it */
1944 + if (!(ctrl & CTRL_EOF))
1945 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
1946 +
1947 + /* save the packet */
1948 + di->txp[PREVTXD(txout)] = p0;
1949 +
1950 + /* bump the tx descriptor index */
1951 + di->txout = txout;
1952 +
1953 + /* kick the chip */
1954 + W_REG(&di->regs->xmtptr, I2B(txout));
1955 +
1956 + /* tx flow control */
1957 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1958 +
1959 + return (0);
1960 +
1961 +outoftxd:
1962 + DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
1963 + PKTFREE(di->drv, p0, TRUE);
1964 + di->txavail = 0;
1965 + di->hnddma.txnobuf++;
1966 + return (-1);
1967 +}
1968 +
1969 +/* returns a pointer to the next frame received, or NULL if there are no more */
1970 +void*
1971 +dma_rx(dma_info_t *di)
1972 +{
1973 + void *p;
1974 + uint len;
1975 + int skiplen = 0;
1976 +
1977 + while ((p = dma_getnextrxp(di, FALSE))) {
1978 + /* skip giant packets which span multiple rx descriptors */
1979 + if (skiplen > 0) {
1980 + skiplen -= di->rxbufsize;
1981 + if (skiplen < 0)
1982 + skiplen = 0;
1983 + PKTFREE(di->drv, p, FALSE);
1984 + continue;
1985 + }
1986 +
1987 + len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
1988 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
1989 +
1990 + /* bad frame length check */
1991 + if (len > (di->rxbufsize - di->rxoffset)) {
1992 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
1993 + if (len > 0)
1994 + skiplen = len - (di->rxbufsize - di->rxoffset);
1995 + PKTFREE(di->drv, p, FALSE);
1996 + di->hnddma.rxgiants++;
1997 + continue;
1998 + }
1999 +
2000 + /* set actual length */
2001 + PKTSETLEN(di->drv, p, (di->rxoffset + len));
2002 +
2003 + break;
2004 + }
2005 +
2006 + return (p);
2007 +}
2008 +
2009 +/* post receive buffers */
2010 +void
2011 +dma_rxfill(dma_info_t *di)
2012 +{
2013 + void *p;
2014 + uint rxin, rxout;
2015 + uint ctrl;
2016 + uint n;
2017 + uint i;
2018 + uint32 pa;
2019 + uint rxbufsize;
2020 +
2021 + /*
2022 + * Determine how many receive buffers we're lacking
2023 + * from the full complement, allocate, initialize,
2024 + * and post them, then update the chip rx lastdscr.
2025 + */
2026 +
2027 + rxin = di->rxin;
2028 + rxout = di->rxout;
2029 + rxbufsize = di->rxbufsize;
2030 +
2031 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
2032 +
2033 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
2034 +
2035 + for (i = 0; i < n; i++) {
2036 + if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
2037 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
2038 + di->hnddma.rxnobuf++;
2039 + break;
2040 + }
2041 +
2042 + *(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
2043 +
2044 + pa = (uint32) DMA_MAP(di->dev, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
2045 + ASSERT(ISALIGNED(pa, 4));
2046 +
2047 + /* save the free packet pointer */
2048 + ASSERT(di->rxp[rxout] == NULL);
2049 + di->rxp[rxout] = p;
2050 +
2051 + /* prep the descriptor control value */
2052 + ctrl = rxbufsize;
2053 + if (rxout == (di->nrxd - 1))
2054 + ctrl |= CTRL_EOT;
2055 +
2056 + /* init the rx descriptor */
2057 + W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
2058 + W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
2059 +
2060 + rxout = NEXTRXD(rxout);
2061 + }
2062 +
2063 + di->rxout = rxout;
2064 +
2065 + /* update the chip lastdscr pointer */
2066 + W_REG(&di->regs->rcvptr, I2B(rxout));
2067 +}
2068 +
2069 +void
2070 +dma_txreclaim(dma_info_t *di, bool forceall)
2071 +{
2072 + void *p;
2073 +
2074 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
2075 +
2076 + while ((p = dma_getnexttxp(di, forceall)))
2077 + PKTFREE(di->drv, p, TRUE);
2078 +}
2079 +
2080 +/*
2081 + * Reclaim next completed txd (txds if using chained buffers) and
2082 + * return associated packet.
2083 + * If 'force' is true, reclaim txd(s) and return associated packet
2084 + * regardless of the value of the hardware "curr" pointer.
2085 + */
2086 +void*
2087 +dma_getnexttxp(dma_info_t *di, bool forceall)
2088 +{
2089 + uint start, end, i;
2090 + void *txp;
2091 +
2092 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
2093 +
2094 + txp = NULL;
2095 +
2096 + start = di->txin;
2097 + if (forceall)
2098 + end = di->txout;
2099 + else
2100 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
2101 +
2102 + if ((start == 0) && (end > di->txout))
2103 + goto bogus;
2104 +
2105 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
2106 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
2107 + (BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
2108 + W_SM(&di->txd[i].addr, 0xdeadbeef);
2109 + txp = di->txp[i];
2110 + di->txp[i] = NULL;
2111 + }
2112 +
2113 + di->txin = i;
2114 +
2115 + /* tx flow control */
2116 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2117 +
2118 + return (txp);
2119 +
2120 +bogus:
2121 +/*
2122 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
2123 + start, end, di->txout, forceall));
2124 +*/
2125 + return (NULL);
2126 +}
2127 +
2128 +void
2129 +dma_rxreclaim(dma_info_t *di)
2130 +{
2131 + void *p;
2132 +
2133 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
2134 +
2135 + while ((p = dma_getnextrxp(di, TRUE)))
2136 + PKTFREE(di->drv, p, FALSE);
2137 +}
2138 +
2139 +void *
2140 +dma_getnextrxp(dma_info_t *di, bool forceall)
2141 +{
2142 + uint i;
2143 + void *rxp;
2144 +
2145 + /* if forcing, dma engine must be disabled */
2146 + ASSERT(!forceall || !dma_rxenabled(di));
2147 +
2148 + i = di->rxin;
2149 +
2150 + /* return if no packets posted */
2151 + if (i == di->rxout)
2152 + return (NULL);
2153 +
2154 + /* ignore curr if forceall */
2155 + if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
2156 + return (NULL);
2157 +
2158 + /* get the packet pointer that corresponds to the rx descriptor */
2159 + rxp = di->rxp[i];
2160 + ASSERT(rxp);
2161 + di->rxp[i] = NULL;
2162 +
2163 + /* clear this packet from the descriptor ring */
2164 + DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
2165 + di->rxbufsize, DMA_RX, rxp);
2166 + W_SM(&di->rxd[i].addr, 0xdeadbeef);
2167 +
2168 + di->rxin = NEXTRXD(i);
2169 +
2170 + return (rxp);
2171 +}
2172 +
2173 +char*
2174 +dma_dumptx(dma_info_t *di, char *buf)
2175 +{
2176 + buf += sprintf(buf, "txd 0x%lx txdpa 0x%lx txp 0x%lx txin %d txout %d txavail %d\n",
2177 + (ulong)di->txd, di->txdpa, (ulong)di->txp, di->txin, di->txout, di->txavail);
2178 + buf += sprintf(buf, "xmtcontrol 0x%x xmtaddr 0x%x xmtptr 0x%x xmtstatus 0x%x\n",
2179 + R_REG(&di->regs->xmtcontrol),
2180 + R_REG(&di->regs->xmtaddr),
2181 + R_REG(&di->regs->xmtptr),
2182 + R_REG(&di->regs->xmtstatus));
2183 + return (buf);
2184 +}
2185 +
2186 +char*
2187 +dma_dumprx(dma_info_t *di, char *buf)
2188 +{
2189 + buf += sprintf(buf, "rxd 0x%lx rxdpa 0x%lx rxp 0x%lx rxin %d rxout %d\n",
2190 + (ulong)di->rxd, di->rxdpa, (ulong)di->rxp, di->rxin, di->rxout);
2191 + buf += sprintf(buf, "rcvcontrol 0x%x rcvaddr 0x%x rcvptr 0x%x rcvstatus 0x%x\n",
2192 + R_REG(&di->regs->rcvcontrol),
2193 + R_REG(&di->regs->rcvaddr),
2194 + R_REG(&di->regs->rcvptr),
2195 + R_REG(&di->regs->rcvstatus));
2196 + return (buf);
2197 +}
2198 +
2199 +char*
2200 +dma_dump(dma_info_t *di, char *buf)
2201 +{
2202 + buf = dma_dumptx(di, buf);
2203 + buf = dma_dumprx(di, buf);
2204 + return (buf);
2205 +}
2206 +
2207 +uint
2208 +dma_getvar(dma_info_t *di, char *name)
2209 +{
2210 + if (!strcmp(name, "&txavail"))
2211 + return ((uint) &di->txavail);
2212 + else {
2213 + ASSERT(0);
2214 + }
2215 + return (0);
2216 +}
2217 +
2218 +void
2219 +dma_txblock(dma_info_t *di)
2220 +{
2221 + di->txavail = 0;
2222 +}
2223 +
2224 +void
2225 +dma_txunblock(dma_info_t *di)
2226 +{
2227 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
2228 +}
2229 +
2230 +uint
2231 +dma_txactive(dma_info_t *di)
2232 +{
2233 + return (NTXDACTIVE(di->txin, di->txout));
2234 +}
2235 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/linux_osl.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/linux_osl.c
2236 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
2237 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-09-16 10:29:18.166593160 +0200
2238 @@ -0,0 +1,420 @@
2239 +/*
2240 + * Linux OS Independent Layer
2241 + *
2242 + * Copyright 2001-2003, Broadcom Corporation
2243 + * All Rights Reserved.
2244 + *
2245 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2246 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2247 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2248 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2249 + *
2250 + * $Id: linux_osl.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
2251 + */
2252 +
2253 +#define LINUX_OSL
2254 +
2255 +#include <typedefs.h>
2256 +#include <bcmendian.h>
2257 +#include <linuxver.h>
2258 +#include <linux_osl.h>
2259 +#include <bcmutils.h>
2260 +#include <linux/delay.h>
2261 +#ifdef mips
2262 +#include <asm/paccess.h>
2263 +#endif
2264 +#include <pcicfg.h>
2265 +
2266 +#define PCI_CFG_RETRY 10
2267 +
2268 +void*
2269 +osl_pktget(void *drv, uint len, bool send)
2270 +{
2271 + struct sk_buff *skb;
2272 +
2273 + if ((skb = dev_alloc_skb(len)) == NULL)
2274 + return (NULL);
2275 +
2276 + skb_put(skb, len);
2277 +
2278 + /* ensure the cookie field is cleared */
2279 + PKTSETCOOKIE(skb, NULL);
2280 +
2281 + return ((void*) skb);
2282 +}
2283 +
2284 +void
2285 +osl_pktfree(void *p)
2286 +{
2287 + struct sk_buff *skb, *nskb;
2288 +
2289 + skb = (struct sk_buff*) p;
2290 +
2291 + /* perversion: we use skb->next to chain multi-skb packets */
2292 + while (skb) {
2293 + nskb = skb->next;
2294 + skb->next = NULL;
2295 + if (skb->destructor) {
2296 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
2297 + dev_kfree_skb_any(skb);
2298 + } else {
2299 + /* can free immediately (even in_irq()) if destructor does not exist */
2300 + dev_kfree_skb(skb);
2301 + }
2302 + skb = nskb;
2303 + }
2304 +}
2305 +
2306 +uint32
2307 +osl_pci_read_config(void *loc, uint offset, uint size)
2308 +{
2309 + struct pci_dev *pdev;
2310 + uint val;
2311 + uint retry=PCI_CFG_RETRY;
2312 +
2313 + /* only 4byte access supported */
2314 + ASSERT(size == 4);
2315 +
2316 + pdev = (struct pci_dev*)loc;
2317 + do {
2318 + pci_read_config_dword(pdev, offset, &val);
2319 + if (val != 0xffffffff)
2320 + break;
2321 + } while (retry--);
2322 +
2323 +
2324 + return (val);
2325 +}
2326 +
2327 +void
2328 +osl_pci_write_config(void *loc, uint offset, uint size, uint val)
2329 +{
2330 + struct pci_dev *pdev;
2331 + uint retry=PCI_CFG_RETRY;
2332 +
2333 + /* only 4byte access supported */
2334 + ASSERT(size == 4);
2335 +
2336 + pdev = (struct pci_dev*)loc;
2337 +
2338 + do {
2339 + pci_write_config_dword(pdev, offset, val);
2340 + if (offset!=PCI_BAR0_WIN)
2341 + break;
2342 + if (osl_pci_read_config(loc,offset,size) == val)
2343 + break;
2344 + } while (retry--);
2345 +
2346 +}
2347 +
2348 +void
2349 +osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size)
2350 +{
2351 + ASSERT(0);
2352 +}
2353 +
2354 +void
2355 +osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size)
2356 +{
2357 + ASSERT(0);
2358 +}
2359 +
2360 +void
2361 +osl_assert(char *exp, char *file, int line)
2362 +{
2363 + char tempbuf[255];
2364 +
2365 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
2366 + panic(tempbuf);
2367 +}
2368 +
2369 +/*
2370 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
2371 + */
2372 +#ifdef BINOSL
2373 +
2374 +int
2375 +osl_printf(const char *format, ...)
2376 +{
2377 + va_list args;
2378 + char buf[1024];
2379 + int len;
2380 +
2381 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
2382 + va_start(args, format);
2383 + len = vsprintf(buf, format, args);
2384 + va_end(args);
2385 +
2386 + if (len > sizeof (buf)) {
2387 + printk("osl_printf: buffer overrun\n");
2388 + return (0);
2389 + }
2390 +
2391 + return (printk(buf));
2392 +}
2393 +
2394 +int
2395 +osl_sprintf(char *buf, const char *format, ...)
2396 +{
2397 + va_list args;
2398 + int rc;
2399 +
2400 + va_start(args, format);
2401 + rc = vsprintf(buf, format, args);
2402 + va_end(args);
2403 + return (rc);
2404 +}
2405 +
2406 +int
2407 +osl_strcmp(const char *s1, const char *s2)
2408 +{
2409 + return (strcmp(s1, s2));
2410 +}
2411 +
2412 +int
2413 +osl_strncmp(const char *s1, const char *s2, uint n)
2414 +{
2415 + return (strncmp(s1, s2, n));
2416 +}
2417 +
2418 +int
2419 +osl_strlen(char *s)
2420 +{
2421 + return (strlen(s));
2422 +}
2423 +
2424 +char*
2425 +osl_strcpy(char *d, const char *s)
2426 +{
2427 + return (strcpy(d, s));
2428 +}
2429 +
2430 +char*
2431 +osl_strncpy(char *d, const char *s, uint n)
2432 +{
2433 + return (strncpy(d, s, n));
2434 +}
2435 +
2436 +void
2437 +bcopy(const void *src, void *dst, int len)
2438 +{
2439 + memcpy(dst, src, len);
2440 +}
2441 +
2442 +int
2443 +bcmp(const void *b1, const void *b2, int len)
2444 +{
2445 + return (memcmp(b1, b2, len));
2446 +}
2447 +
2448 +void
2449 +bzero(void *b, int len)
2450 +{
2451 + memset(b, '\0', len);
2452 +}
2453 +
2454 +void*
2455 +osl_malloc(uint size)
2456 +{
2457 + return (kmalloc(size, GFP_ATOMIC));
2458 +}
2459 +
2460 +void
2461 +osl_mfree(void *addr, uint size)
2462 +{
2463 + kfree(addr);
2464 +}
2465 +
2466 +uint32
2467 +osl_readl(volatile uint32 *r)
2468 +{
2469 + return (readl(r));
2470 +}
2471 +
2472 +uint16
2473 +osl_readw(volatile uint16 *r)
2474 +{
2475 + return (readw(r));
2476 +}
2477 +
2478 +uint8
2479 +osl_readb(volatile uint8 *r)
2480 +{
2481 + return (readb(r));
2482 +}
2483 +
2484 +void
2485 +osl_writel(uint32 v, volatile uint32 *r)
2486 +{
2487 + writel(v, r);
2488 +}
2489 +
2490 +void
2491 +osl_writew(uint16 v, volatile uint16 *r)
2492 +{
2493 + writew(v, r);
2494 +}
2495 +
2496 +void
2497 +osl_writeb(uint8 v, volatile uint8 *r)
2498 +{
2499 + writeb(v, r);
2500 +}
2501 +
2502 +void *
2503 +osl_uncached(void *va)
2504 +{
2505 +#ifdef mips
2506 + return ((void*)KSEG1ADDR(va));
2507 +#else
2508 + return ((void*)va);
2509 +#endif
2510 +}
2511 +
2512 +uint
2513 +osl_getcycles(void)
2514 +{
2515 + uint cycles;
2516 +
2517 +#if defined(mips)
2518 + cycles = read_c0_count() * 2;
2519 +#elif defined(__i386__)
2520 + rdtscl(cycles);
2521 +#else
2522 + cycles = 0;
2523 +#endif
2524 + return cycles;
2525 +}
2526 +
2527 +void *
2528 +osl_reg_map(uint32 pa, uint size)
2529 +{
2530 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
2531 +}
2532 +
2533 +void
2534 +osl_reg_unmap(void *va)
2535 +{
2536 + iounmap(va);
2537 +}
2538 +
2539 +int
2540 +osl_busprobe(uint32 *val, uint32 addr)
2541 +{
2542 +#ifdef mips
2543 + return get_dbe(*val, (uint32*)addr);
2544 +#else
2545 + *val = readl(addr);
2546 + return 0;
2547 +#endif
2548 +}
2549 +
2550 +void*
2551 +osl_dma_alloc_consistent(void *dev, uint size, ulong *pap)
2552 +{
2553 + return (pci_alloc_consistent((struct pci_dev*)dev, size, (dma_addr_t*)pap));
2554 +}
2555 +
2556 +void
2557 +osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa)
2558 +{
2559 + pci_free_consistent((struct pci_dev*)dev, size, va, (dma_addr_t)pa);
2560 +}
2561 +
2562 +uint
2563 +osl_dma_map(void *dev, void *va, uint size, int direction)
2564 +{
2565 + int dir;
2566 +
2567 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2568 + return (pci_map_single(dev, va, size, dir));
2569 +}
2570 +
2571 +void
2572 +osl_dma_unmap(void *dev, uint pa, uint size, int direction)
2573 +{
2574 + int dir;
2575 +
2576 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
2577 + pci_unmap_single(dev, (uint32)pa, size, dir);
2578 +}
2579 +
2580 +void
2581 +osl_delay(uint usec)
2582 +{
2583 + udelay(usec);
2584 +}
2585 +
2586 +uchar*
2587 +osl_pktdata(void *drv, void *skb)
2588 +{
2589 + return (((struct sk_buff*)skb)->data);
2590 +}
2591 +
2592 +uint
2593 +osl_pktlen(void *drv, void *skb)
2594 +{
2595 + return (((struct sk_buff*)skb)->len);
2596 +}
2597 +
2598 +void*
2599 +osl_pktnext(void *drv, void *skb)
2600 +{
2601 + return (((struct sk_buff*)skb)->next);
2602 +}
2603 +
2604 +void
2605 +osl_pktsetnext(void *skb, void *x)
2606 +{
2607 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
2608 +}
2609 +
2610 +void
2611 +osl_pktsetlen(void *drv, void *skb, uint len)
2612 +{
2613 + __skb_trim((struct sk_buff*)skb, len);
2614 +}
2615 +
2616 +uchar*
2617 +osl_pktpush(void *drv, void *skb, int bytes)
2618 +{
2619 + return (skb_push((struct sk_buff*)skb, bytes));
2620 +}
2621 +
2622 +uchar*
2623 +osl_pktpull(void *drv, void *skb, int bytes)
2624 +{
2625 + return (skb_pull((struct sk_buff*)skb, bytes));
2626 +}
2627 +
2628 +void*
2629 +osl_pktdup(void *drv, void *skb)
2630 +{
2631 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
2632 +}
2633 +
2634 +void*
2635 +osl_pktcookie(void *skb)
2636 +{
2637 + return ((void*)((struct sk_buff*)skb)->csum);
2638 +}
2639 +
2640 +void
2641 +osl_pktsetcookie(void *skb, void *x)
2642 +{
2643 + ((struct sk_buff*)skb)->csum = (uint)x;
2644 +}
2645 +
2646 +void*
2647 +osl_pktlink(void *skb)
2648 +{
2649 + return (((struct sk_buff*)skb)->prev);
2650 +}
2651 +
2652 +void
2653 +osl_pktsetlink(void *skb, void *x)
2654 +{
2655 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
2656 +}
2657 +
2658 +#endif
2659 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbmips.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbmips.c
2660 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
2661 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbmips.c 2005-09-16 10:29:18.168592856 +0200
2662 @@ -0,0 +1,950 @@
2663 +/*
2664 + * BCM47XX Sonics SiliconBackplane MIPS core routines
2665 + *
2666 + * Copyright 2001-2003, Broadcom Corporation
2667 + * All Rights Reserved.
2668 + *
2669 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2670 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2671 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2672 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2673 + *
2674 + * $Id: sbmips.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
2675 + */
2676 +
2677 +#include <typedefs.h>
2678 +#include <osl.h>
2679 +#include <sbutils.h>
2680 +#include <bcmdevs.h>
2681 +#include <bcmnvram.h>
2682 +#include <bcmutils.h>
2683 +#include <hndmips.h>
2684 +#include <sbconfig.h>
2685 +#include <sbextif.h>
2686 +#include <sbchipc.h>
2687 +#include <sbmemc.h>
2688 +
2689 +/*
2690 + * Memory segments (32bit kernel mode addresses)
2691 + */
2692 +#undef KUSEG
2693 +#undef KSEG0
2694 +#undef KSEG1
2695 +#undef KSEG2
2696 +#undef KSEG3
2697 +#define KUSEG 0x00000000
2698 +#define KSEG0 0x80000000
2699 +#define KSEG1 0xa0000000
2700 +#define KSEG2 0xc0000000
2701 +#define KSEG3 0xe0000000
2702 +
2703 +/*
2704 + * Map an address to a certain kernel segment
2705 + */
2706 +#undef KSEG0ADDR
2707 +#undef KSEG1ADDR
2708 +#undef KSEG2ADDR
2709 +#undef KSEG3ADDR
2710 +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
2711 +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
2712 +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
2713 +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
2714 +
2715 +/*
2716 + * The following macros are especially useful for __asm__
2717 + * inline assembler.
2718 + */
2719 +#ifndef __STR
2720 +#define __STR(x) #x
2721 +#endif
2722 +#ifndef STR
2723 +#define STR(x) __STR(x)
2724 +#endif
2725 +
2726 +/* *********************************************************************
2727 + * CP0 Registers
2728 + ********************************************************************* */
2729 +
2730 +#define C0_INX 0 /* CP0: TLB Index */
2731 +#define C0_RAND 1 /* CP0: TLB Random */
2732 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
2733 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
2734 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
2735 +#define C0_CTEXT 4 /* CP0: Context */
2736 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
2737 +#define C0_WIRED 6 /* CP0: TLB Wired */
2738 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
2739 +#define C0_COUNT 9 /* CP0: Count */
2740 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
2741 +#define C0_COMPARE 11 /* CP0: Compare */
2742 +#define C0_SR 12 /* CP0: Processor Status */
2743 +#define C0_STATUS C0_SR /* CP0: Processor Status */
2744 +#define C0_CAUSE 13 /* CP0: Exception Cause */
2745 +#define C0_EPC 14 /* CP0: Exception PC */
2746 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
2747 +#define C0_CONFIG 16 /* CP0: Config */
2748 +#define C0_LLADDR 17 /* CP0: LLAddr */
2749 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
2750 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
2751 +#define C0_XCTEXT 20 /* CP0: XContext */
2752 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
2753 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
2754 +#define C0_ECC 26 /* CP0: ECC */
2755 +#define C0_CACHEERR 27 /* CP0: CacheErr */
2756 +#define C0_TAGLO 28 /* CP0: TagLo */
2757 +#define C0_TAGHI 29 /* CP0: TagHi */
2758 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
2759 +
2760 +/*
2761 + * Macros to access the system control coprocessor
2762 + */
2763 +
2764 +#define MFC0(source, sel) \
2765 +({ \
2766 + int __res; \
2767 + __asm__ __volatile__( \
2768 + ".set\tnoreorder\n\t" \
2769 + ".set\tnoat\n\t" \
2770 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
2771 + "move\t%0,$1\n\t" \
2772 + ".set\tat\n\t" \
2773 + ".set\treorder" \
2774 + :"=r" (__res) \
2775 + : \
2776 + :"$1"); \
2777 + __res; \
2778 +})
2779 +
2780 +#define MTC0(source, sel, value) \
2781 +do { \
2782 + __asm__ __volatile__( \
2783 + ".set\tnoreorder\n\t" \
2784 + ".set\tnoat\n\t" \
2785 + "move\t$1,%z0\n\t" \
2786 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
2787 + ".set\tat\n\t" \
2788 + ".set\treorder" \
2789 + : \
2790 + :"Jr" (value) \
2791 + :"$1"); \
2792 +} while (0)
2793 +
2794 +/*
2795 + * R4x00 interrupt enable / cause bits
2796 + */
2797 +#undef IE_SW0
2798 +#undef IE_SW1
2799 +#undef IE_IRQ0
2800 +#undef IE_IRQ1
2801 +#undef IE_IRQ2
2802 +#undef IE_IRQ3
2803 +#undef IE_IRQ4
2804 +#undef IE_IRQ5
2805 +#define IE_SW0 (1<< 8)
2806 +#define IE_SW1 (1<< 9)
2807 +#define IE_IRQ0 (1<<10)
2808 +#define IE_IRQ1 (1<<11)
2809 +#define IE_IRQ2 (1<<12)
2810 +#define IE_IRQ3 (1<<13)
2811 +#define IE_IRQ4 (1<<14)
2812 +#define IE_IRQ5 (1<<15)
2813 +
2814 +/*
2815 + * Bitfields in the R4xx0 cp0 status register
2816 + */
2817 +#define ST0_IE 0x00000001
2818 +#define ST0_EXL 0x00000002
2819 +#define ST0_ERL 0x00000004
2820 +#define ST0_KSU 0x00000018
2821 +# define KSU_USER 0x00000010
2822 +# define KSU_SUPERVISOR 0x00000008
2823 +# define KSU_KERNEL 0x00000000
2824 +#define ST0_UX 0x00000020
2825 +#define ST0_SX 0x00000040
2826 +#define ST0_KX 0x00000080
2827 +#define ST0_DE 0x00010000
2828 +#define ST0_CE 0x00020000
2829 +
2830 +/*
2831 + * Status register bits available in all MIPS CPUs.
2832 + */
2833 +#define ST0_IM 0x0000ff00
2834 +#define ST0_CH 0x00040000
2835 +#define ST0_SR 0x00100000
2836 +#define ST0_TS 0x00200000
2837 +#define ST0_BEV 0x00400000
2838 +#define ST0_RE 0x02000000
2839 +#define ST0_FR 0x04000000
2840 +#define ST0_CU 0xf0000000
2841 +#define ST0_CU0 0x10000000
2842 +#define ST0_CU1 0x20000000
2843 +#define ST0_CU2 0x40000000
2844 +#define ST0_CU3 0x80000000
2845 +#define ST0_XX 0x80000000 /* MIPS IV naming */
2846 +
2847 +/*
2848 + * Cache Operations
2849 + */
2850 +
2851 +#ifndef Fill_I
2852 +#define Fill_I 0x14
2853 +#endif
2854 +
2855 +#define cache_unroll(base,op) \
2856 + __asm__ __volatile__(" \
2857 + .set noreorder; \
2858 + .set mips3; \
2859 + cache %1, (%0); \
2860 + .set mips0; \
2861 + .set reorder" \
2862 + : \
2863 + : "r" (base), \
2864 + "i" (op));
2865 +
2866 +/*
2867 + * These are the UART port assignments, expressed as offsets from the base
2868 + * register. These assignments should hold for any serial port based on
2869 + * a 8250, 16450, or 16550(A).
2870 + */
2871 +
2872 +#define UART_MCR 4 /* Out: Modem Control Register */
2873 +#define UART_MSR 6 /* In: Modem Status Register */
2874 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
2875 +
2876 +/*
2877 + * Returns TRUE if an external UART exists at the given base
2878 + * register.
2879 + */
2880 +static bool
2881 +serial_exists(uint8 *regs)
2882 +{
2883 + uint8 save_mcr, status1;
2884 +
2885 + save_mcr = R_REG(&regs[UART_MCR]);
2886 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2887 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
2888 + W_REG(&regs[UART_MCR], save_mcr);
2889 +
2890 + return (status1 == 0x90);
2891 +}
2892 +
2893 +/*
2894 + * Initializes UART access. The callback function will be called once
2895 + * per found UART.
2896 +*/
2897 +void
2898 +sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
2899 +{
2900 + void *regs;
2901 + ulong base;
2902 + uint irq;
2903 + int i, n;
2904 +
2905 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2906 + extifregs_t *eir = (extifregs_t *) regs;
2907 + sbconfig_t *sb;
2908 +
2909 + /* Determine external UART register base */
2910 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2911 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
2912 +
2913 + /* Determine IRQ */
2914 + irq = sb_irq(sbh);
2915 +
2916 + /* Disable GPIO interrupt initially */
2917 + W_REG(&eir->gpiointpolarity, 0);
2918 + W_REG(&eir->gpiointmask, 0);
2919 +
2920 + /* Search for external UARTs */
2921 + n = 2;
2922 + for (i = 0; i < 2; i++) {
2923 + regs = (void *) REG_MAP(base + (i * 8), 8);
2924 + if (serial_exists(regs)) {
2925 + /* Set GPIO 1 to be the external UART IRQ */
2926 + W_REG(&eir->gpiointmask, 2);
2927 + if (add)
2928 + add(regs, irq, 13500000, 0);
2929 + }
2930 + }
2931 +
2932 + /* Add internal UART if enabled */
2933 + if (R_REG(&eir->corecontrol) & CC_UE)
2934 + if (add)
2935 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2936 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2937 + chipcregs_t *cc = (chipcregs_t *) regs;
2938 + uint32 rev, cap, pll, baud_base, div;
2939 +
2940 + /* Determine core revision and capabilities */
2941 + rev = sb_corerev(sbh);
2942 + cap = R_REG(&cc->capabilities);
2943 + pll = cap & CAP_PLL_MASK;
2944 +
2945 + /* Determine IRQ */
2946 + irq = sb_irq(sbh);
2947 +
2948 + if (pll == PLL_TYPE1) {
2949 + /* PLL clock */
2950 + baud_base = sb_clock_rate(pll,
2951 + R_REG(&cc->clockcontrol_n),
2952 + R_REG(&cc->clockcontrol_m2));
2953 + div = 1;
2954 + } else if (rev >= 3) {
2955 + /* Internal backplane clock */
2956 + baud_base = sb_clock_rate(pll,
2957 + R_REG(&cc->clockcontrol_n),
2958 + R_REG(&cc->clockcontrol_sb));
2959 + div = 2; /* Minimum divisor */
2960 + W_REG(&cc->uart_clkdiv, div);
2961 + } else {
2962 + /* Fixed internal backplane clock */
2963 + baud_base = 88000000;
2964 + div = 48;
2965 + }
2966 +
2967 + /* Clock source depends on strapping if UartClkOverride is unset */
2968 + if ((rev > 0) && ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
2969 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2970 + /* Internal divided backplane clock */
2971 + baud_base /= div;
2972 + } else {
2973 + /* Assume external clock of 1.8432 MHz */
2974 + baud_base = 1843200;
2975 + }
2976 + }
2977 +
2978 + /* Add internal UARTs */
2979 + n = cap & CAP_UARTS_MASK;
2980 + for (i = 0; i < n; i++) {
2981 + /* Register offset changed after revision 0 */
2982 + if (rev)
2983 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2984 + else
2985 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2986 +
2987 + if (add)
2988 + add(regs, irq, baud_base, 0);
2989 + }
2990 + }
2991 +}
2992 +
2993 +/* Returns the SB interrupt flag of the current core. */
2994 +uint32
2995 +sb_flag(void *sbh)
2996 +{
2997 + void *regs;
2998 + sbconfig_t *sb;
2999 +
3000 + regs = sb_coreregs(sbh);
3001 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3002 +
3003 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
3004 +}
3005 +
3006 +static const uint32 sbips_int_mask[] = {
3007 + 0,
3008 + SBIPS_INT1_MASK,
3009 + SBIPS_INT2_MASK,
3010 + SBIPS_INT3_MASK,
3011 + SBIPS_INT4_MASK
3012 +};
3013 +
3014 +static const uint32 sbips_int_shift[] = {
3015 + 0,
3016 + 0,
3017 + SBIPS_INT2_SHIFT,
3018 + SBIPS_INT3_SHIFT,
3019 + SBIPS_INT4_SHIFT
3020 +};
3021 +
3022 +/*
3023 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
3024 + * 0 is returned.
3025 + */
3026 +uint
3027 +sb_irq(void *sbh)
3028 +{
3029 + uint idx;
3030 + void *regs;
3031 + sbconfig_t *sb;
3032 + uint32 flag, sbipsflag;
3033 + uint irq = 0;
3034 +
3035 + flag = sb_flag(sbh);
3036 +
3037 + idx = sb_coreidx(sbh);
3038 +
3039 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3040 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3041 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3042 +
3043 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
3044 + sbipsflag = R_REG(&sb->sbipsflag);
3045 + for (irq = 1; irq <= 4; irq++) {
3046 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
3047 + break;
3048 + }
3049 + if (irq == 5)
3050 + irq = 0;
3051 + }
3052 +
3053 + sb_setcoreidx(sbh, idx);
3054 +
3055 + return irq;
3056 +}
3057 +
3058 +/* Clears the specified MIPS IRQ. */
3059 +static void
3060 +sb_clearirq(void *sbh, uint irq)
3061 +{
3062 + void *regs;
3063 + sbconfig_t *sb;
3064 +
3065 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3066 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3067 + ASSERT(regs);
3068 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3069 +
3070 + if (irq == 0)
3071 + W_REG(&sb->sbintvec, 0);
3072 + else
3073 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
3074 +}
3075 +
3076 +/*
3077 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
3078 + * IRQ 0 may be assigned more than once.
3079 + */
3080 +static void
3081 +sb_setirq(void *sbh, uint irq, uint coreid, uint coreunit)
3082 +{
3083 + void *regs;
3084 + sbconfig_t *sb;
3085 + uint32 flag;
3086 +
3087 + regs = sb_setcore(sbh, coreid, coreunit);
3088 + ASSERT(regs);
3089 + flag = sb_flag(sbh);
3090 +
3091 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
3092 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
3093 + ASSERT(regs);
3094 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3095 +
3096 + if (irq == 0)
3097 + OR_REG(&sb->sbintvec, 1 << flag);
3098 + else {
3099 + flag <<= sbips_int_shift[irq];
3100 + ASSERT(!(flag & ~sbips_int_mask[irq]));
3101 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
3102 + W_REG(&sb->sbipsflag, flag);
3103 + }
3104 +}
3105 +
3106 +/*
3107 + * Initializes clocks and interrupts. SB and NVRAM access must be
3108 + * initialized prior to calling.
3109 + */
3110 +void
3111 +sb_mips_init(void *sbh)
3112 +{
3113 + ulong hz, ns, tmp;
3114 + extifregs_t *eir;
3115 + chipcregs_t *cc;
3116 + char *value;
3117 + uint irq;
3118 +
3119 + /* Figure out current SB clock speed */
3120 + if ((hz = sb_clock(sbh)) == 0)
3121 + hz = 100000000;
3122 + ns = 1000000000 / hz;
3123 +
3124 + /* Setup external interface timing */
3125 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
3126 + /* Initialize extif so we can get to the LEDs and external UART */
3127 + W_REG(&eir->prog_config, CF_EN);
3128 +
3129 + /* Set timing for the flash */
3130 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3131 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
3132 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3133 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
3134 +
3135 + /* Set programmable interface timing for external uart */
3136 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3137 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
3138 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
3139 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
3140 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
3141 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
3142 + /* Set timing for the flash */
3143 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
3144 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
3145 + tmp |= CEIL(120, ns); /* W0 = 120nS */
3146 + W_REG(&cc->parallelflashwaitcnt, tmp);
3147 +
3148 + W_REG(&cc->cs01memwaitcnt, tmp);
3149 + }
3150 +
3151 + /* Chip specific initialization */
3152 + switch (sb_chip(sbh)) {
3153 + case BCM4710_DEVICE_ID:
3154 + /* Clear interrupt map */
3155 + for (irq = 0; irq <= 4; irq++)
3156 + sb_clearirq(sbh, irq);
3157 + sb_setirq(sbh, 0, SB_CODEC, 0);
3158 + sb_setirq(sbh, 0, SB_EXTIF, 0);
3159 + sb_setirq(sbh, 2, SB_ENET, 1);
3160 + sb_setirq(sbh, 3, SB_ILINE20, 0);
3161 + sb_setirq(sbh, 4, SB_PCI, 0);
3162 + ASSERT(eir);
3163 + value = nvram_get("et0phyaddr");
3164 + if (value && !strcmp(value, "31")) {
3165 + /* Enable internal UART */
3166 + W_REG(&eir->corecontrol, CC_UE);
3167 + /* Give USB its own interrupt */
3168 + sb_setirq(sbh, 1, SB_USB, 0);
3169 + } else {
3170 + /* Disable internal UART */
3171 + W_REG(&eir->corecontrol, 0);
3172 + /* Give Ethernet its own interrupt */
3173 + sb_setirq(sbh, 1, SB_ENET, 0);
3174 + sb_setirq(sbh, 0, SB_USB, 0);
3175 + }
3176 + break;
3177 + case BCM4310_DEVICE_ID:
3178 + MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
3179 + break;
3180 + }
3181 +}
3182 +
3183 +uint32
3184 +sb_mips_clock(void *sbh)
3185 +{
3186 + extifregs_t *eir;
3187 + chipcregs_t *cc;
3188 + uint32 n, m;
3189 + uint idx;
3190 + uint32 pll_type, rate = 0;
3191 +
3192 + /* get index of the current core */
3193 + idx = sb_coreidx(sbh);
3194 + pll_type = PLL_TYPE1;
3195 +
3196 + /* switch to extif or chipc core */
3197 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
3198 + n = R_REG(&eir->clockcontrol_n);
3199 + m = R_REG(&eir->clockcontrol_sb);
3200 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
3201 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
3202 + n = R_REG(&cc->clockcontrol_n);
3203 + if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4))
3204 + m = R_REG(&cc->clockcontrol_mips);
3205 + else if (pll_type == PLL_TYPE3) {
3206 + rate = 200000000;
3207 + goto out;
3208 + } else
3209 + m = R_REG(&cc->clockcontrol_sb);
3210 + } else
3211 + goto out;
3212 +
3213 + /* calculate rate */
3214 + rate = sb_clock_rate(pll_type, n, m);
3215 +
3216 +out:
3217 + /* switch back to previous core */
3218 + sb_setcoreidx(sbh, idx);
3219 +
3220 + return rate;
3221 +}
3222 +
3223 +static void
3224 +icache_probe(int *size, int *lsize)
3225 +{
3226 + uint32 config1;
3227 + uint sets, ways;
3228 +
3229 + config1 = MFC0(C0_CONFIG, 1);
3230 +
3231 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
3232 + if ((*lsize = ((config1 >> 19) & 7)))
3233 + *lsize = 2 << *lsize;
3234 + sets = 64 << ((config1 >> 22) & 7);
3235 + ways = 1 + ((config1 >> 16) & 7);
3236 + *size = *lsize * sets * ways;
3237 +}
3238 +
3239 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
3240 +
3241 +static void
3242 +handler(void)
3243 +{
3244 + /* Step 11 */
3245 + __asm__ (
3246 + ".set\tmips32\n\t"
3247 + "ssnop\n\t"
3248 + "ssnop\n\t"
3249 + /* Disable interrupts */
3250 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
3251 + "mfc0 $15, $12\n\t"
3252 + "and $15, $15, -31746\n\t"
3253 + "mtc0 $15, $12\n\t"
3254 + "eret\n\t"
3255 + "nop\n\t"
3256 + "nop\n\t"
3257 + ".set\tmips0"
3258 + );
3259 +}
3260 +
3261 +/* The following MUST come right after handler() */
3262 +static void
3263 +afterhandler(void)
3264 +{
3265 +}
3266 +
3267 +/*
3268 + * Set the MIPS, backplane and PCI clocks as closely as possible.
3269 + */
3270 +bool
3271 +sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
3272 +{
3273 + extifregs_t *eir = NULL;
3274 + chipcregs_t *cc = NULL;
3275 + mipsregs_t *mipsr = NULL;
3276 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci;
3277 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, new_ratio;
3278 + uint32 pll_type, sync_mode;
3279 + uint idx, i;
3280 + struct {
3281 + uint32 mipsclock;
3282 + uint16 n;
3283 + uint32 sb;
3284 + uint32 pci33;
3285 + uint32 pci25;
3286 + } type1_table[] = {
3287 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
3288 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
3289 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
3290 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
3291 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
3292 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
3293 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
3294 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
3295 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
3296 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
3297 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
3298 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
3299 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
3300 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
3301 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
3302 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
3303 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
3304 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
3305 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
3306 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
3307 + };
3308 + typedef struct {
3309 + uint32 mipsclock;
3310 + uint32 sbclock;
3311 + uint16 n;
3312 + uint32 sb;
3313 + uint32 pci33;
3314 + uint32 m2;
3315 + uint32 m3;
3316 + uint32 ratio;
3317 + uint32 ratio_parm;
3318 + } n4m_table_t;
3319 +
3320 + n4m_table_t type2_table[] = {
3321 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3322 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
3323 + { 200000000, 100000000, 0x0303, 0x01000000, 0x01000600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3324 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3325 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3326 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3327 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3328 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3329 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
3330 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
3331 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3332 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3333 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3334 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3335 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
3336 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 0x94, 0x012a0115 },
3337 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 }
3338 + };
3339 +
3340 + n4m_table_t type4_table[] = {
3341 + { 192000000, 96000000, 0x0702, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
3342 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
3343 + { 216000000, 108000000, 0x0211, 0x11020005, 0x11030303, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
3344 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x11030305, 0x04000005, 0x94, 0x012a00a9 },
3345 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
3346 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 0x21, 0x0aaa0555 },
3347 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
3348 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
3349 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3350 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3351 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
3352 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 0x52, 0x02520129 }
3353 + };
3354 + uint icache_size, ic_lsize;
3355 + ulong start, end, dst;
3356 + bool ret = FALSE;
3357 +
3358 + /* get index of the current core */
3359 + idx = sb_coreidx(sbh);
3360 +
3361 + /* switch to extif or chipc core */
3362 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
3363 + pll_type = PLL_TYPE1;
3364 + clockcontrol_n = &eir->clockcontrol_n;
3365 + clockcontrol_sb = &eir->clockcontrol_sb;
3366 + clockcontrol_pci = &eir->clockcontrol_pci;
3367 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
3368 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
3369 + clockcontrol_n = &cc->clockcontrol_n;
3370 + clockcontrol_sb = &cc->clockcontrol_sb;
3371 + clockcontrol_pci = &cc->clockcontrol_pci;
3372 + } else
3373 + goto done;
3374 +
3375 + /* Store the current clock register values */
3376 + orig_n = R_REG(clockcontrol_n);
3377 + orig_sb = R_REG(clockcontrol_sb);
3378 + orig_pci = R_REG(clockcontrol_pci);
3379 +
3380 + if (pll_type == PLL_TYPE1) {
3381 + /* Keep the current PCI clock if not specified */
3382 + if (pciclock == 0) {
3383 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
3384 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
3385 + }
3386 +
3387 + /* Search for the closest MIPS clock less than or equal to a preferred value */
3388 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
3389 + ASSERT(type1_table[i].mipsclock ==
3390 + sb_clock_rate(pll_type, type1_table[i].n, type1_table[i].sb));
3391 + if (type1_table[i].mipsclock > mipsclock)
3392 + break;
3393 + }
3394 + if (i == 0) {
3395 + ret = FALSE;
3396 + goto done;
3397 + } else {
3398 + ret = TRUE;
3399 + i--;
3400 + }
3401 + ASSERT(type1_table[i].mipsclock <= mipsclock);
3402 +
3403 + /* No PLL change */
3404 + if ((orig_n == type1_table[i].n) &&
3405 + (orig_sb == type1_table[i].sb) &&
3406 + (orig_pci == type1_table[i].pci33))
3407 + goto done;
3408 +
3409 + /* Set the PLL controls */
3410 + W_REG(clockcontrol_n, type1_table[i].n);
3411 + W_REG(clockcontrol_sb, type1_table[i].sb);
3412 + if (pciclock == 25000000)
3413 + W_REG(clockcontrol_pci, type1_table[i].pci25);
3414 + else
3415 + W_REG(clockcontrol_pci, type1_table[i].pci33);
3416 +
3417 + /* Reset */
3418 + sb_watchdog(sbh, 1);
3419 + while (1);
3420 + } else if ((pll_type == PLL_TYPE2) || (pll_type == PLL_TYPE4)) {
3421 + n4m_table_t *table = (pll_type == PLL_TYPE2) ? type2_table : type4_table;
3422 + uint tabsz = (pll_type == PLL_TYPE2) ? ARRAYSIZE(type2_table) : ARRAYSIZE(type4_table);
3423 +
3424 + ASSERT(cc);
3425 +
3426 + /* Store the current clock register values */
3427 + orig_m2 = R_REG(&cc->clockcontrol_m2);
3428 + orig_mips = R_REG(&cc->clockcontrol_mips);
3429 + orig_ratio_parm = 0;
3430 +
3431 + /* Look up current ratio */
3432 + for (i = 0; i < tabsz; i++) {
3433 + if ((orig_n == table[i].n) &&
3434 + (orig_sb == table[i].sb) &&
3435 + (orig_pci == table[i].pci33) &&
3436 + (orig_m2 == table[i].m2) &&
3437 + (orig_mips == table[i].m3)) {
3438 + orig_ratio_parm = table[i].ratio_parm;
3439 + break;
3440 + }
3441 + }
3442 +
3443 + /* Search for the closest MIPS clock greater or equal to a preferred value */
3444 + for (i = 0; i < tabsz; i++) {
3445 + ASSERT(table[i].mipsclock ==
3446 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
3447 + if ((mipsclock <= table[i].mipsclock) &&
3448 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
3449 + break;
3450 + }
3451 + if (i == tabsz) {
3452 + ret = FALSE;
3453 + goto done;
3454 + } else {
3455 + ret = TRUE;
3456 + }
3457 +
3458 + /* No PLL change */
3459 + if ((orig_n == table[i].n) &&
3460 + (orig_sb == table[i].sb) &&
3461 + (orig_pci == table[i].pci33) &&
3462 + (orig_m2 == table[i].m2) &&
3463 + (orig_mips == table[i].m3))
3464 + goto done;
3465 +
3466 + /* Set the PLL controls */
3467 + W_REG(clockcontrol_n, table[i].n);
3468 + W_REG(clockcontrol_sb, table[i].sb);
3469 + W_REG(clockcontrol_pci, table[i].pci33);
3470 + W_REG(&cc->clockcontrol_m2, table[i].m2);
3471 + W_REG(&cc->clockcontrol_mips, table[i].m3);
3472 +
3473 + /* No ratio change */
3474 + if (orig_ratio_parm == table[i].ratio_parm)
3475 + goto end_fill;
3476 +
3477 + new_ratio = table[i].ratio_parm;
3478 +
3479 + icache_probe(&icache_size, &ic_lsize);
3480 +
3481 + /* Preload the code into the cache */
3482 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
3483 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
3484 + while (start < end) {
3485 + cache_unroll(start, Fill_I);
3486 + start += ic_lsize;
3487 + }
3488 +
3489 + /* Copy the handler */
3490 + start = (ulong) &handler;
3491 + end = (ulong) &afterhandler;
3492 + dst = KSEG1ADDR(0x180);
3493 + for (i = 0; i < (end - start); i += 4)
3494 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
3495 +
3496 + /* Preload handler into the cache one line at a time */
3497 + for (i = 0; i < (end - start); i += 4)
3498 + cache_unroll(dst + i, Fill_I);
3499 +
3500 + /* Clear BEV bit */
3501 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
3502 +
3503 + /* Enable interrupts */
3504 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
3505 +
3506 + /* Enable MIPS timer interrupt */
3507 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
3508 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
3509 + ASSERT(mipsr);
3510 + W_REG(&mipsr->intmask, 1);
3511 +
3512 + start_fill:
3513 + /* step 1, set clock ratios */
3514 + MTC0(C0_BROADCOM, 3, new_ratio);
3515 + MTC0(C0_BROADCOM, 1, 8);
3516 +
3517 + /* step 2: program timer intr */
3518 + W_REG(&mipsr->timer, 100);
3519 + (void) R_REG(&mipsr->timer);
3520 +
3521 + /* step 3, switch to async */
3522 + sync_mode = MFC0(C0_BROADCOM, 4);
3523 + MTC0(C0_BROADCOM, 4, 1 << 22);
3524 +
3525 + /* step 4, set cfg active */
3526 + MTC0(C0_BROADCOM, 2, 0x9);
3527 +
3528 +
3529 + /* steps 5 & 6 */
3530 + __asm__ __volatile__ (
3531 + ".set\tmips3\n\t"
3532 + "wait\n\t"
3533 + ".set\tmips0"
3534 + );
3535 +
3536 + /* step 7, clear cfg_active */
3537 + MTC0(C0_BROADCOM, 2, 0);
3538 +
3539 + /* Additional Step: set back to orig sync mode */
3540 + MTC0(C0_BROADCOM, 4, sync_mode);
3541 +
3542 + /* step 8, fake soft reset */
3543 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
3544 +
3545 + end_fill:
3546 + /* step 9 set watchdog timer */
3547 + sb_watchdog(sbh, 20);
3548 + (void) R_REG(&cc->chipid);
3549 +
3550 + /* step 11 */
3551 + __asm__ __volatile__ (
3552 + ".set\tmips3\n\t"
3553 + "sync\n\t"
3554 + "wait\n\t"
3555 + ".set\tmips0"
3556 + );
3557 + while (1);
3558 + }
3559 +
3560 +done:
3561 + /* switch back to previous core */
3562 + sb_setcoreidx(sbh, idx);
3563 +
3564 + return ret;
3565 +}
3566 +
3567 +
3568 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
3569 +uint32
3570 +sb_memc_get_ncdl(void *sbh)
3571 +{
3572 + sbmemcregs_t *memc;
3573 + uint32 ret = 0;
3574 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
3575 + uint idx, rev;
3576 +
3577 + idx = sb_coreidx(sbh);
3578 +
3579 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
3580 + if (memc == 0)
3581 + goto out;
3582 +
3583 + rev = sb_corerev(sbh);
3584 +
3585 + config = R_REG(&memc->config);
3586 + wr = R_REG(&memc->wrncdlcor);
3587 + rd = R_REG(&memc->rdncdlcor);
3588 + misc = R_REG(&memc->miscdlyctl);
3589 + dqsg = R_REG(&memc->dqsgatencdl);
3590 +
3591 + rd &= MEMC_RDNCDLCOR_RD_MASK;
3592 + wr &= MEMC_WRNCDLCOR_WR_MASK;
3593 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
3594 +
3595 + if (config & MEMC_CONFIG_DDR) {
3596 + ret = (wr << 16) | (rd << 8) | dqsg;
3597 + } else {
3598 + if (rev > 0)
3599 + cd = rd;
3600 + else
3601 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
3602 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
3603 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
3604 + ret = (sm << 16) | (sd << 8) | cd;
3605 + }
3606 +
3607 +out:
3608 + /* switch back to previous core */
3609 + sb_setcoreidx(sbh, idx);
3610 +
3611 + return ret;
3612 +}
3613 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbpci.c
3614 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
3615 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbpci.c 2005-09-16 10:29:18.169592704 +0200
3616 @@ -0,0 +1,530 @@
3617 +/*
3618 + * Low-Level PCI and SB support for BCM47xx
3619 + *
3620 + * Copyright 2001-2003, Broadcom Corporation
3621 + * All Rights Reserved.
3622 + *
3623 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3624 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3625 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3626 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3627 + *
3628 + * $Id: sbpci.c,v 1.2 2005/02/28 13:34:25 jolt Exp $
3629 + */
3630 +
3631 +#include <typedefs.h>
3632 +#include <pcicfg.h>
3633 +#include <bcmdevs.h>
3634 +#include <sbconfig.h>
3635 +#include <sbpci.h>
3636 +#include <osl.h>
3637 +#include <bcmendian.h>
3638 +#include <bcmutils.h>
3639 +#include <sbutils.h>
3640 +#include <bcmnvram.h>
3641 +#include <hndmips.h>
3642 +
3643 +/* Can free sbpci_init() memory after boot */
3644 +#ifndef linux
3645 +#define __init
3646 +#endif
3647 +
3648 +/* Emulated configuration space */
3649 +static pci_config_regs sb_config_regs[SB_MAXCORES];
3650 +
3651 +/* Banned cores */
3652 +static uint16 pci_ban[32] = { 0 };
3653 +static uint pci_banned = 0;
3654 +
3655 +/* CardBus mode */
3656 +static bool cardbus = FALSE;
3657 +
3658 +/*
3659 + * Functions for accessing external PCI configuration space
3660 + */
3661 +
3662 +/* Assume one-hot slot wiring */
3663 +#define PCI_SLOT_MAX 16
3664 +
3665 +static uint32
3666 +config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
3667 +{
3668 + uint coreidx;
3669 + sbpciregs_t *regs;
3670 + uint32 addr = 0;
3671 +
3672 + /* CardBusMode supports only one device */
3673 + if (cardbus && dev > 1)
3674 + return 0;
3675 +
3676 + coreidx = sb_coreidx(sbh);
3677 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
3678 +
3679 + /* Type 0 transaction */
3680 + if (bus == 1) {
3681 + /* Skip unwired slots */
3682 + if (dev < PCI_SLOT_MAX) {
3683 + /* Slide the PCI window to the appropriate slot */
3684 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
3685 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
3686 + (func << 8) | (off & ~3);
3687 + }
3688 + }
3689 +
3690 + /* Type 1 transaction */
3691 + else {
3692 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
3693 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
3694 + }
3695 +
3696 + sb_setcoreidx(sbh, coreidx);
3697 +
3698 + return addr;
3699 +}
3700 +
3701 +static int
3702 +extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3703 +{
3704 + uint32 addr, *reg = NULL, val;
3705 + int ret = 0;
3706 +
3707 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
3708 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
3709 + BUSPROBE(val, reg))
3710 + val = 0xffffffff;
3711 +
3712 + val >>= 8 * (off & 3);
3713 + if (len == 4)
3714 + *((uint32 *) buf) = val;
3715 + else if (len == 2)
3716 + *((uint16 *) buf) = (uint16) val;
3717 + else if (len == 1)
3718 + *((uint8 *) buf) = (uint8) val;
3719 + else
3720 + ret = -1;
3721 +
3722 + if (reg)
3723 + REG_UNMAP(reg);
3724 +
3725 + return ret;
3726 +}
3727 +
3728 +static int
3729 +extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3730 +{
3731 + uint32 addr, *reg = NULL, val;
3732 + int ret = 0;
3733 +
3734 + if (!(addr = config_cmd(sbh, bus, dev, func, off)) ||
3735 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
3736 + BUSPROBE(val, reg))
3737 + goto done;
3738 +
3739 + if (len == 4)
3740 + val = *((uint32 *) buf);
3741 + else if (len == 2) {
3742 + val &= ~(0xffff << (8 * (off & 3)));
3743 + val |= *((uint16 *) buf) << (8 * (off & 3));
3744 + } else if (len == 1) {
3745 + val &= ~(0xff << (8 * (off & 3)));
3746 + val |= *((uint8 *) buf) << (8 * (off & 3));
3747 + } else
3748 + ret = -1;
3749 +
3750 + W_REG(reg, val);
3751 +
3752 + done:
3753 + if (reg)
3754 + REG_UNMAP(reg);
3755 +
3756 + return ret;
3757 +}
3758 +
3759 +/*
3760 + * Functions for accessing translated SB configuration space
3761 + */
3762 +
3763 +static int
3764 +sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3765 +{
3766 + pci_config_regs *cfg;
3767 +
3768 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
3769 + return -1;
3770 + cfg = &sb_config_regs[dev];
3771 +
3772 + ASSERT(ISALIGNED(off, len));
3773 + ASSERT(ISALIGNED(buf, len));
3774 +
3775 + if (len == 4)
3776 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
3777 + else if (len == 2)
3778 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
3779 + else if (len == 1)
3780 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
3781 + else
3782 + return -1;
3783 +
3784 + return 0;
3785 +}
3786 +
3787 +static int
3788 +sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3789 +{
3790 + uint coreidx, n;
3791 + void *regs;
3792 + sbconfig_t *sb;
3793 + pci_config_regs *cfg;
3794 +
3795 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
3796 + return -1;
3797 + cfg = &sb_config_regs[dev];
3798 +
3799 + ASSERT(ISALIGNED(off, len));
3800 + ASSERT(ISALIGNED(buf, len));
3801 +
3802 + /* Emulate BAR sizing */
3803 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
3804 + len == 4 && *((uint32 *) buf) == ~0) {
3805 + coreidx = sb_coreidx(sbh);
3806 + if ((regs = sb_setcoreidx(sbh, dev))) {
3807 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3808 + /* Highest numbered address match register */
3809 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
3810 + if (off == OFFSETOF(pci_config_regs, base[0]))
3811 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
3812 + /*else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
3813 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
3814 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
3815 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
3816 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
3817 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);*/
3818 + }
3819 + sb_setcoreidx(sbh, coreidx);
3820 + return 0;
3821 + }
3822 +
3823 + if (len == 4)
3824 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
3825 + else if (len == 2)
3826 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
3827 + else if (len == 1)
3828 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
3829 + else
3830 + return -1;
3831 +
3832 + return 0;
3833 +}
3834 +
3835 +int
3836 +sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3837 +{
3838 + if (bus == 0)
3839 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
3840 + else
3841 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
3842 +}
3843 +
3844 +int
3845 +sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
3846 +{
3847 + if (bus == 0)
3848 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
3849 + else
3850 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
3851 +}
3852 +
3853 +void
3854 +sbpci_ban(uint16 core)
3855 +{
3856 + if (pci_banned < ARRAYSIZE(pci_ban))
3857 + pci_ban[pci_banned++] = core;
3858 +}
3859 +
3860 +int __init
3861 +sbpci_init(void *sbh)
3862 +{
3863 + uint chip, chiprev, chippkg, coreidx, host, i;
3864 + sbpciregs_t *pci;
3865 + sbconfig_t *sb;
3866 + pci_config_regs *cfg;
3867 + void *regs;
3868 + char varname[8];
3869 + uint wlidx = 0;
3870 + uint16 vendor, core;
3871 + uint8 class, subclass, progif;
3872 + uint32 val;
3873 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
3874 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
3875 +
3876 + chip = sb_chip(sbh);
3877 + chiprev = sb_chiprev(sbh);
3878 + chippkg = sb_chippkg(sbh);
3879 + coreidx = sb_coreidx(sbh);
3880 +
3881 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
3882 + return -1;
3883 + sb_core_reset(sbh, 0);
3884 +
3885 + if (((chip == BCM4310_DEVICE_ID) && (chiprev == 0)) ||
3886 + ((chip == BCM4712_DEVICE_ID) && (chippkg == BCM4712SMALL_PKG_ID)))
3887 + host = 0;
3888 + else
3889 + host = !BUSPROBE(val, &pci->control);
3890 +
3891 + if (!host) {
3892 + /* Disable PCI interrupts in client mode */
3893 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
3894 + W_REG(&sb->sbintvec, 0);
3895 +
3896 + /* Disable the PCI bridge in client mode */
3897 + sbpci_ban(SB_PCI);
3898 + printf("PCI: Disabled\n");
3899 + } else {
3900 + /* Reset the external PCI bus and enable the clock */
3901 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
3902 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
3903 + OSL_DELAY(100); /* delay 100 us */
3904 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
3905 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
3906 + OSL_DELAY(1); /* delay 1 us */
3907 +
3908 + /* Enable CardBusMode */
3909 + cardbus = nvram_match("cardbus", "1");
3910 + if (cardbus) {
3911 + printf("PCI: Enabling CardBus\n");
3912 + /* GPIO 1 resets the CardBus device on bcm94710ap */
3913 + sb_gpioout(sbh, 1, 1);
3914 + sb_gpioouten(sbh, 1, 1);
3915 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
3916 + }
3917 +
3918 + /* 64 MB I/O access window */
3919 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
3920 + /* 64 MB configuration access window */
3921 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
3922 + /* 1 GB memory access window */
3923 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
3924 +
3925 + /* Enable PCI bridge BAR0 prefetch and burst */
3926 + val = 6;
3927 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
3928 +
3929 + /* Enable PCI interrupts */
3930 + W_REG(&pci->intmask, PCI_INTA);
3931 + }
3932 +
3933 + /* Scan the SB bus */
3934 + bzero(sb_config_regs, sizeof(sb_config_regs));
3935 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
3936 + cfg->vendor = 0xffff;
3937 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
3938 + continue;
3939 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3940 +
3941 + /* Read ID register and parse vendor and core */
3942 + val = R_REG(&sb->sbidhigh);
3943 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
3944 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
3945 + progif = 0;
3946 +
3947 + /* Check if this core is banned */
3948 + for (i = 0; i < pci_banned; i++)
3949 + if (core == pci_ban[i])
3950 + break;
3951 + if (i < pci_banned)
3952 + continue;
3953 +
3954 + /* Known vendor translations */
3955 + switch (vendor) {
3956 + case SB_VEND_BCM:
3957 + vendor = VENDOR_BROADCOM;
3958 + break;
3959 + }
3960 +
3961 + /* Determine class based on known core codes */
3962 + switch (core) {
3963 + case SB_ILINE20:
3964 + class = PCI_CLASS_NET;
3965 + subclass = PCI_NET_ETHER;
3966 + core = BCM47XX_ILINE_ID;
3967 + break;
3968 + case SB_ILINE100:
3969 + class = PCI_CLASS_NET;
3970 + subclass = PCI_NET_ETHER;
3971 + core = BCM4610_ILINE_ID;
3972 + break;
3973 + case SB_ENET:
3974 + class = PCI_CLASS_NET;
3975 + subclass = PCI_NET_ETHER;
3976 + core = BCM47XX_ENET_ID;
3977 + break;
3978 + case SB_SDRAM:
3979 + case SB_MEMC:
3980 + class = PCI_CLASS_MEMORY;
3981 + subclass = PCI_MEMORY_RAM;
3982 + break;
3983 + case SB_PCI:
3984 + class = PCI_CLASS_BRIDGE;
3985 + subclass = PCI_BRIDGE_PCI;
3986 + //break;
3987 + case SB_MIPS:
3988 + case SB_MIPS33:
3989 + class = PCI_CLASS_CPU;
3990 + subclass = PCI_CPU_MIPS;
3991 + break;
3992 + case SB_CODEC:
3993 + class = PCI_CLASS_COMM;
3994 + subclass = PCI_COMM_MODEM;
3995 + core = BCM47XX_V90_ID;
3996 + break;
3997 + case SB_USB:
3998 + class = PCI_CLASS_SERIAL;
3999 + subclass = PCI_SERIAL_USB;
4000 + progif = 0x10; /* OHCI */
4001 + core = BCM47XX_USB_ID;
4002 + break;
4003 + case SB_USB11H:
4004 + class = PCI_CLASS_SERIAL;
4005 + subclass = PCI_SERIAL_USB;
4006 + progif = 0x10; /* OHCI */
4007 + core = BCM47XX_USBH_ID;
4008 + break;
4009 + case SB_USB11D:
4010 + class = PCI_CLASS_SERIAL;
4011 + subclass = PCI_SERIAL_USB;
4012 + core = BCM47XX_USBD_ID;
4013 + break;
4014 + case SB_IPSEC:
4015 + class = PCI_CLASS_CRYPT;
4016 + subclass = PCI_CRYPT_NETWORK;
4017 + core = BCM47XX_IPSEC_ID;
4018 + break;
4019 + case SB_EXTIF:
4020 + case SB_CC:
4021 + class = PCI_CLASS_MEMORY;
4022 + subclass = PCI_MEMORY_FLASH;
4023 + break;
4024 + case SB_D11:
4025 + class = PCI_CLASS_NET;
4026 + subclass = PCI_NET_OTHER;
4027 + /* Let an nvram variable override this */
4028 + sprintf(varname, "wl%did", wlidx);
4029 + wlidx++;
4030 + if ((core = getintvar(NULL, varname)) == 0) {
4031 + if (chip == BCM4712_DEVICE_ID) {
4032 + if (chippkg == BCM4712SMALL_PKG_ID)
4033 + core = BCM4306_D11G_ID;
4034 + else
4035 + core = BCM4306_D11DUAL_ID;
4036 + } else {
4037 + /* 4310 */
4038 + core = BCM4310_D11B_ID;
4039 + }
4040 + }
4041 + break;
4042 +
4043 + default:
4044 + class = subclass = progif = 0xff;
4045 + break;
4046 + }
4047 +
4048 + /* Supported translations */
4049 + cfg->vendor = htol16(vendor);
4050 + cfg->device = htol16(core);
4051 + cfg->rev_id = chiprev;
4052 + cfg->prog_if = progif;
4053 + cfg->sub_class = subclass;
4054 + cfg->base_class = class;
4055 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
4056 + cfg->base[1] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch1)))*/;
4057 + cfg->base[2] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch2)))*/;
4058 + cfg->base[3] = 0/*htol32(sb_base(R_REG(&sb->sbadmatch3)))*/;
4059 + cfg->base[4] = 0;
4060 + cfg->base[5] = 0;
4061 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
4062 + cfg->header_type = PCI_HEADER_BRIDGE;
4063 + else
4064 + cfg->header_type = PCI_HEADER_NORMAL;
4065 + /* Save core interrupt flag */
4066 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
4067 + /* Default to MIPS shared interrupt 0 */
4068 + cfg->int_line = 0;
4069 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
4070 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
4071 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
4072 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
4073 + val = R_REG(&sb->sbipsflag);
4074 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
4075 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
4076 + break;
4077 + }
4078 + if (cfg->int_line > 4)
4079 + cfg->int_line = 0;
4080 + }
4081 + /* Emulated core */
4082 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
4083 + }
4084 +
4085 + sb_setcoreidx(sbh, coreidx);
4086 + return 0;
4087 +}
4088 +
4089 +void
4090 +sbpci_check(void *sbh)
4091 +{
4092 + uint coreidx;
4093 + sbpciregs_t *pci;
4094 + uint32 sbtopci1;
4095 + uint32 buf[64], *ptr, i;
4096 + ulong pa;
4097 + volatile uint j;
4098 +
4099 + coreidx = sb_coreidx(sbh);
4100 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
4101 +
4102 + /* Clear the test array */
4103 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
4104 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
4105 + memset(ptr, 0, sizeof(buf));
4106 +
4107 + /* Point PCI window 1 to memory */
4108 + sbtopci1 = R_REG(&pci->sbtopci1);
4109 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
4110 +
4111 + /* Fill the test array via PCI window 1 */
4112 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
4113 + for (i = 0; i < ARRAYSIZE(buf); i++) {
4114 + for (j = 0; j < 2; j++);
4115 + W_REG(&ptr[i], i);
4116 + }
4117 + REG_UNMAP(ptr);
4118 +
4119 + /* Restore PCI window 1 */
4120 + W_REG(&pci->sbtopci1, sbtopci1);
4121 +
4122 + /* Check the test array */
4123 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
4124 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
4125 + for (i = 0; i < ARRAYSIZE(buf); i++) {
4126 + if (ptr[i] != i)
4127 + break;
4128 + }
4129 +
4130 + /* Change the clock if the test fails */
4131 + if (i < ARRAYSIZE(buf)) {
4132 + uint32 req, cur;
4133 +
4134 + cur = sb_clock(sbh);
4135 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
4136 + for (req = 104000000; req < 176000000; req += 4000000) {
4137 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
4138 + /* This will only reset if the clocks are valid and have changed */
4139 + sb_mips_setclock(sbh, req, 0, 0);
4140 + }
4141 + /* Should not reach here */
4142 + ASSERT(0);
4143 + }
4144 +
4145 + sb_setcoreidx(sbh, coreidx);
4146 +}
4147 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbutils.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbutils.c
4148 --- linux-2.6.12.5/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
4149 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/broadcom/sbutils.c 2005-09-16 10:29:18.172592248 +0200
4150 @@ -0,0 +1,1895 @@
4151 +/*
4152 + * Misc utility routines for accessing chip-specific features
4153 + * of the SiliconBackplane-based Broadcom chips.
4154 + *
4155 + * Copyright 2001-2003, Broadcom Corporation
4156 + * All Rights Reserved.
4157 + *
4158 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4159 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4160 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4161 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4162 + *
4163 + * $Id: sbutils.c,v 1.1 2005/02/28 13:33:32 jolt Exp $
4164 + */
4165 +
4166 +#include <typedefs.h>
4167 +#include <osl.h>
4168 +#include <bcmutils.h>
4169 +#include <bcmdevs.h>
4170 +#include <sbconfig.h>
4171 +#include <sbchipc.h>
4172 +#include <sbpci.h>
4173 +#include <pcicfg.h>
4174 +#include <sbpcmcia.h>
4175 +#include <sbextif.h>
4176 +#include <sbutils.h>
4177 +#include <bcmsrom.h>
4178 +
4179 +/* debug/trace */
4180 +#define SB_ERROR(args)
4181 +
4182 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
4183 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
4184 +
4185 +/* misc sb info needed by some of the routines */
4186 +typedef struct sb_info {
4187 + uint chip; /* chip number */
4188 + uint chiprev; /* chip revision */
4189 + uint chippkg; /* chip package option */
4190 + uint boardtype; /* board type */
4191 + uint boardvendor; /* board vendor id */
4192 + uint bus; /* what bus type we are going through */
4193 +
4194 + void *osh; /* osl os handle */
4195 + void *sdh; /* bcmsdh handle */
4196 +
4197 + void *curmap; /* current regs va */
4198 + void *regs[SB_MAXCORES]; /* other regs va */
4199 +
4200 + uint curidx; /* current core index */
4201 + uint dev_coreid; /* the core provides driver functions */
4202 + uint pciidx; /* pci core index */
4203 + uint pcirev; /* pci core rev */
4204 +
4205 + uint pcmciaidx; /* pcmcia core index */
4206 + uint pcmciarev; /* pcmcia core rev */
4207 + bool memseg; /* flag to toggle MEM_SEG register */
4208 +
4209 + uint ccrev; /* chipc core rev */
4210 +
4211 + uint gpioidx; /* gpio control core index */
4212 + uint gpioid; /* gpio control coretype */
4213 +
4214 + uint numcores; /* # discovered cores */
4215 + uint coreid[SB_MAXCORES]; /* id of each core */
4216 +
4217 + void *intr_arg; /* interrupt callback function arg */
4218 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
4219 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
4220 +} sb_info_t;
4221 +
4222 +/* local prototypes */
4223 +static void* sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
4224 +static void sb_scan(sb_info_t *si);
4225 +static uint sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val);
4226 +static uint _sb_coreidx(void *sbh);
4227 +static uint sb_findcoreidx(void *sbh, uint coreid, uint coreunit);
4228 +static uint sb_pcidev2chip(uint pcidev);
4229 +static uint sb_chip2numcores(uint chip);
4230 +
4231 +#define SB_INFO(sbh) (sb_info_t*)sbh
4232 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
4233 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) \
4234 + && ISALIGNED((x), SB_CORE_SIZE))
4235 +#define GOODREGS(regs) (regs && ISALIGNED(regs, SB_CORE_SIZE))
4236 +#define REGS2SB(va) (sbconfig_t*) ((uint)(va) + SBCONFIGOFF)
4237 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
4238 +#define BADIDX (SB_MAXCORES+1)
4239 +
4240 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
4241 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
4242 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
4243 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
4244 +
4245 +/*
4246 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
4247 + * after core switching to avoid invalid register accesss inside ISR.
4248 + */
4249 +#define INTR_OFF(si, intr_val) \
4250 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
4251 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
4252 +#define INTR_RESTORE(si, intr_val) \
4253 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
4254 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
4255 +
4256 +/* power control defines */
4257 +#define PLL_DELAY 150 /* 150us pll on delay */
4258 +#define FREF_DELAY 15 /* 15us fref change delay */
4259 +#define LPOMINFREQ 25000 /* low power oscillator min */
4260 +#define LPOMAXFREQ 43000 /* low power oscillator max */
4261 +#define XTALMINFREQ 19800000 /* 20mhz - 1% */
4262 +#define XTALMAXFREQ 20200000 /* 20mhz + 1% */
4263 +#define PCIMINFREQ 25000000 /* 25mhz */
4264 +#define PCIMAXFREQ 34000000 /* 33mhz + fudge */
4265 +
4266 +#define SCC_LOW2FAST_LIMIT 5000 /* turn on fast clock time, in unit of ms */
4267 +
4268 +
4269 +static uint32
4270 +sb_read_sbreg(void *sbh, volatile uint32 *sbr)
4271 +{
4272 + sb_info_t *si;
4273 + uint8 tmp;
4274 + uint32 val, intr_val = 0;
4275 +
4276 + si = SB_INFO(sbh);
4277 +
4278 + /*
4279 + * compact flash only has 11 bits address, while we needs 12 bits address.
4280 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
4281 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
4282 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
4283 + */
4284 + if(si->memseg) {
4285 + INTR_OFF(si, intr_val);
4286 + tmp = 1;
4287 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4288 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11*/
4289 + }
4290 +
4291 + val = R_REG(sbr);
4292 +
4293 + if(si->memseg) {
4294 + tmp = 0;
4295 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4296 + INTR_RESTORE(si, intr_val);
4297 + }
4298 +
4299 + return (val);
4300 +}
4301 +
4302 +static void
4303 +sb_write_sbreg(void *sbh, volatile uint32 *sbr, uint32 v)
4304 +{
4305 + sb_info_t *si;
4306 + uint8 tmp;
4307 + volatile uint32 dummy;
4308 + uint32 intr_val = 0;
4309 +
4310 + si = SB_INFO(sbh);
4311 +
4312 + /*
4313 + * compact flash only has 11 bits address, while we needs 12 bits address.
4314 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
4315 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
4316 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
4317 + */
4318 + if(si->memseg) {
4319 + INTR_OFF(si, intr_val);
4320 + tmp = 1;
4321 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4322 + (uint32)sbr &= ~(1 << 11); /* mask out bit 11 */
4323 + }
4324 +
4325 + if ((si->bus == PCMCIA_BUS) || (si->bus == PCI_BUS)) {
4326 +#ifdef IL_BIGENDIAN
4327 + dummy = R_REG(sbr);
4328 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
4329 + dummy = R_REG(sbr);
4330 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
4331 +#else
4332 + dummy = R_REG(sbr);
4333 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
4334 + dummy = R_REG(sbr);
4335 + W_REG((volatile uint16 *)((uint32)sbr + 2), (uint16)((v >> 16) & 0xffff));
4336 +#endif
4337 + } else
4338 + W_REG(sbr, v);
4339 +
4340 + if(si->memseg) {
4341 + tmp = 0;
4342 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
4343 + INTR_RESTORE(si, intr_val);
4344 + }
4345 +}
4346 +
4347 +/*
4348 + * Allocate a sb handle.
4349 + * devid - pci device id (used to determine chip#)
4350 + * osh - opaque OS handle
4351 + * regs - virtual address of initial core registers
4352 + * bustype - pci/pcmcia/sb/sdio/etc
4353 + * vars - pointer to a pointer area for "environment" variables
4354 + * varsz - pointer to int to return the size of the vars
4355 + */
4356 +void*
4357 +sb_attach(uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
4358 +{
4359 + sb_info_t *si;
4360 +
4361 + /* alloc sb_info_t */
4362 + if ((si = MALLOC(sizeof (sb_info_t))) == NULL) {
4363 + SB_ERROR(("sb_attach: malloc failed!\n"));
4364 + return (NULL);
4365 + }
4366 +
4367 + return (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, varsz));
4368 +}
4369 +
4370 +/* global kernel resource */
4371 +static sb_info_t ksi;
4372 +
4373 +/* generic kernel variant of sb_attach() */
4374 +void*
4375 +sb_kattach()
4376 +{
4377 + uint32 *regs;
4378 + char *unused;
4379 + int varsz;
4380 +
4381 + if (ksi.curmap == NULL) {
4382 + uint32 cid;
4383 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
4384 + cid = R_REG((uint32 *)regs);
4385 + if ((cid == 0x08104712) || (cid == 0x08114712)) {
4386 + uint32 *scc, val;
4387 +
4388 + scc = (uint32 *)((uint32)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
4389 + val = R_REG(scc);
4390 + SB_ERROR((" initial scc = 0x%x\n", val));
4391 + val |= SCC_SS_XTAL;
4392 + W_REG(scc, val);
4393 + }
4394 +
4395 + sb_doattach(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
4396 + SB_BUS, NULL, &unused, &varsz);
4397 + }
4398 +
4399 + return &ksi;
4400 +}
4401 +
4402 +static void*
4403 +sb_doattach(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
4404 +{
4405 + uint origidx;
4406 + chipcregs_t *cc;
4407 + uint32 w;
4408 +
4409 + ASSERT(GOODREGS(regs));
4410 +
4411 + bzero((uchar*)si, sizeof (sb_info_t));
4412 +
4413 + si->pciidx = si->gpioidx = BADIDX;
4414 +
4415 + si->osh = osh;
4416 + si->curmap = regs;
4417 + si->sdh = sdh;
4418 +
4419 + /* 4317A0 PCMCIA is no longer supported */
4420 + if ((bustype == PCMCIA_BUS) && (R_REG((uint32 *)regs) == 0x04104317))
4421 + return NULL;
4422 +
4423 + /* check to see if we are a sb core mimic'ing a pci core */
4424 + if (bustype == PCI_BUS) {
4425 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
4426 + bustype = SB_BUS;
4427 + else
4428 + bustype = PCI_BUS;
4429 + }
4430 +
4431 + si->bus = bustype;
4432 +
4433 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
4434 + if (si->bus == PCI_BUS)
4435 + sb_pwrctl_xtal((void*)si, XTAL|PLL, ON);
4436 +
4437 + /* clear any previous epidiag-induced target abort */
4438 + sb_taclear((void*)si);
4439 +
4440 + /* initialize current core index value */
4441 + si->curidx = _sb_coreidx((void*)si);
4442 +
4443 + /* keep and reuse the initial register mapping */
4444 + origidx = si->curidx;
4445 + if (si->bus == SB_BUS)
4446 + si->regs[origidx] = regs;
4447 +
4448 + /* initialize the vars */
4449 + if (srom_var_init(si->bus, si->curmap, osh, vars, varsz)) {
4450 + SB_ERROR(("sb_attach: srom_var_init failed\n"));
4451 + goto bad;
4452 + }
4453 +
4454 + if (si->bus == PCMCIA_BUS) {
4455 + w = getintvar(*vars, "regwindowsz");
4456 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
4457 + }
4458 +
4459 + /* is core-0 a chipcommon core? */
4460 + si->numcores = 1;
4461 + cc = (chipcregs_t*) sb_setcoreidx((void*)si, 0);
4462 + if (sb_coreid((void*)si) != SB_CC)
4463 + cc = NULL;
4464 +
4465 + /* determine chip id and rev */
4466 + if (cc) {
4467 + /* chip common core found! */
4468 + si->chip = R_REG(&cc->chipid) & CID_ID_MASK;
4469 + si->chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
4470 + si->chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
4471 + } else {
4472 + /* without chip common core, get devid for PCMCIA */
4473 + if (si->bus == PCMCIA_BUS)
4474 + devid = getintvar(*vars, "devid");
4475 +
4476 + /* no chip common core -- must convert device id to chip id */
4477 + if ((si->chip = sb_pcidev2chip(devid)) == 0) {
4478 + SB_ERROR(("sb_attach: unrecognized device id 0x%04x\n", devid));
4479 + goto bad;
4480 + }
4481 +
4482 + /*
4483 + * The chip revision number is hardwired into all
4484 + * of the pci function config rev fields and is
4485 + * independent from the individual core revision numbers.
4486 + * For example, the "A0" silicon of each chip is chip rev 0.
4487 + * For PCMCIA we get it from the CIS instead.
4488 + */
4489 + if (si->bus == PCMCIA_BUS) {
4490 + ASSERT(vars);
4491 + si->chiprev = getintvar(*vars, "chiprev");
4492 + } else if (si->bus == PCI_BUS) {
4493 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
4494 + si->chiprev = w & 0xff;
4495 + } else
4496 + si->chiprev = 0;
4497 + }
4498 +
4499 + /* get chipcommon rev */
4500 + si->ccrev = cc? sb_corerev((void*)si) : 0;
4501 +
4502 + /* determine numcores */
4503 + if ((si->ccrev == 4) || (si->ccrev >= 6))
4504 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
4505 + else
4506 + si->numcores = sb_chip2numcores(si->chip);
4507 +
4508 + /* return to original core */
4509 + sb_setcoreidx((void*)si, origidx);
4510 +
4511 + /* sanity checks */
4512 + ASSERT(si->chip);
4513 + /* 4704A1 is chiprev 8 :-( */
4514 + ASSERT((si->chiprev < 8) ||
4515 + ((si->chip == BCM4704_DEVICE_ID) && ((si->chiprev == 8))));
4516 +
4517 + /* scan for cores */
4518 + sb_scan(si);
4519 +
4520 + /* pci core is required */
4521 + if (!GOODIDX(si->pciidx)) {
4522 + SB_ERROR(("sb_attach: pci core not found\n"));
4523 + goto bad;
4524 + }
4525 +
4526 + /* gpio control core is required */
4527 + if (!GOODIDX(si->gpioidx)) {
4528 + SB_ERROR(("sb_attach: gpio control core not found\n"));
4529 + goto bad;
4530 + }
4531 +
4532 + /* get boardtype and boardrev */
4533 + switch (si->bus) {
4534 + case PCI_BUS:
4535 + /* do a pci config read to get subsystem id and subvendor id */
4536 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
4537 + si->boardvendor = w & 0xffff;
4538 + si->boardtype = (w >> 16) & 0xffff;
4539 + break;
4540 +
4541 + case PCMCIA_BUS:
4542 + case SDIO_BUS:
4543 + si->boardvendor = getintvar(*vars, "manfid");
4544 + si->boardtype = getintvar(*vars, "prodid");
4545 + break;
4546 +
4547 + case SB_BUS:
4548 + si->boardvendor = VENDOR_BROADCOM;
4549 + si->boardtype = 0xffff;
4550 + break;
4551 + }
4552 +
4553 + if (si->boardtype == 0) {
4554 + SB_ERROR(("sb_attach: unknown board type\n"));
4555 + ASSERT(si->boardtype);
4556 + }
4557 +
4558 + return ((void*)si);
4559 +
4560 +bad:
4561 + MFREE(si, sizeof (sb_info_t));
4562 + return (NULL);
4563 +}
4564 +
4565 +uint
4566 +sb_coreid(void *sbh)
4567 +{
4568 + sb_info_t *si;
4569 + sbconfig_t *sb;
4570 +
4571 + si = SB_INFO(sbh);
4572 + sb = REGS2SB(si->curmap);
4573 +
4574 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
4575 +}
4576 +
4577 +uint
4578 +sb_coreidx(void *sbh)
4579 +{
4580 + sb_info_t *si;
4581 +
4582 + si = SB_INFO(sbh);
4583 + return (si->curidx);
4584 +}
4585 +
4586 +/* return current index of core */
4587 +static uint
4588 +_sb_coreidx(void *sbh)
4589 +{
4590 + sb_info_t *si;
4591 + sbconfig_t *sb;
4592 + uint32 sbaddr = 0;
4593 +
4594 + si = SB_INFO(sbh);
4595 + ASSERT(si);
4596 +
4597 + switch (si->bus) {
4598 + case SB_BUS:
4599 + sb = REGS2SB(si->curmap);
4600 + sbaddr = sb_base(R_SBREG(sbh, &sb->sbadmatch0));
4601 + break;
4602 +
4603 + case PCI_BUS:
4604 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
4605 + break;
4606 +
4607 + case PCMCIA_BUS: {
4608 + uint8 tmp;
4609 +
4610 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
4611 + sbaddr = (uint)tmp << 12;
4612 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
4613 + sbaddr |= (uint)tmp << 16;
4614 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
4615 + sbaddr |= (uint)tmp << 24;
4616 + break;
4617 + }
4618 + default:
4619 + ASSERT(0);
4620 + }
4621 +
4622 + ASSERT(GOODCOREADDR(sbaddr));
4623 + return ((sbaddr - SB_ENUM_BASE)/SB_CORE_SIZE);
4624 +}
4625 +
4626 +uint
4627 +sb_corevendor(void *sbh)
4628 +{
4629 + sb_info_t *si;
4630 + sbconfig_t *sb;
4631 +
4632 + si = SB_INFO(sbh);
4633 + sb = REGS2SB(si->curmap);
4634 +
4635 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
4636 +}
4637 +
4638 +uint
4639 +sb_corerev(void *sbh)
4640 +{
4641 + sb_info_t *si;
4642 + sbconfig_t *sb;
4643 +
4644 + si = SB_INFO(sbh);
4645 + sb = REGS2SB(si->curmap);
4646 +
4647 + return (R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_RC_MASK);
4648 +}
4649 +
4650 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
4651 +
4652 +/* set/clear sbtmstatelow core-specific flags */
4653 +uint32
4654 +sb_coreflags(void *sbh, uint32 mask, uint32 val)
4655 +{
4656 + sb_info_t *si;
4657 + sbconfig_t *sb;
4658 + uint32 w;
4659 +
4660 + si = SB_INFO(sbh);
4661 + sb = REGS2SB(si->curmap);
4662 +
4663 + ASSERT((val & ~mask) == 0);
4664 + ASSERT((mask & ~SBTML_ALLOW) == 0);
4665 +
4666 + /* mask and set */
4667 + if (mask || val) {
4668 + w = (R_SBREG(sbh, &sb->sbtmstatelow) & ~mask) | val;
4669 + W_SBREG(sbh, &sb->sbtmstatelow, w);
4670 + }
4671 +
4672 + /* return the new value */
4673 + return (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_ALLOW);
4674 +}
4675 +
4676 +/* set/clear sbtmstatehigh core-specific flags */
4677 +uint32
4678 +sb_coreflagshi(void *sbh, uint32 mask, uint32 val)
4679 +{
4680 + sb_info_t *si;
4681 + sbconfig_t *sb;
4682 + uint32 w;
4683 +
4684 + si = SB_INFO(sbh);
4685 + sb = REGS2SB(si->curmap);
4686 +
4687 + ASSERT((val & ~mask) == 0);
4688 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
4689 +
4690 + /* mask and set */
4691 + if (mask || val) {
4692 + w = (R_SBREG(sbh, &sb->sbtmstatehigh) & ~mask) | val;
4693 + W_SBREG(sbh, &sb->sbtmstatehigh, w);
4694 + }
4695 +
4696 + /* return the new value */
4697 + return (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
4698 +}
4699 +
4700 +bool
4701 +sb_iscoreup(void *sbh)
4702 +{
4703 + sb_info_t *si;
4704 + sbconfig_t *sb;
4705 +
4706 + si = SB_INFO(sbh);
4707 + sb = REGS2SB(si->curmap);
4708 +
4709 + return ((R_SBREG(sbh, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK);
4710 +}
4711 +
4712 +/*
4713 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
4714 + * switch back to the original core, and return the new value.
4715 + */
4716 +static uint
4717 +sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val)
4718 +{
4719 + sb_info_t *si;
4720 + uint origidx;
4721 + uint32 *r;
4722 + uint w;
4723 + uint intr_val = 0;
4724 +
4725 + ASSERT(GOODIDX(coreidx));
4726 + ASSERT(regoff < SB_CORE_SIZE);
4727 + ASSERT((val & ~mask) == 0);
4728 +
4729 + si = SB_INFO(sbh);
4730 +
4731 + /* save current core index */
4732 + origidx = sb_coreidx(sbh);
4733 +
4734 + /* switch core */
4735 + INTR_OFF(si, intr_val);
4736 + r = (uint32*) ((uint) sb_setcoreidx(sbh, coreidx) + regoff);
4737 +
4738 + /* mask and set */
4739 + if (mask || val) {
4740 + if (regoff >= SBCONFIGOFF) {
4741 + w = (R_SBREG(sbh, r) & ~mask) | val;
4742 + W_SBREG(sbh, r, w);
4743 + } else {
4744 + w = (R_REG(r) & ~mask) | val;
4745 + W_REG(r, w);
4746 + }
4747 + }
4748 +
4749 + /* readback */
4750 + w = R_SBREG(sbh, r);
4751 +
4752 + /* restore core index */
4753 + if (origidx != coreidx)
4754 + sb_setcoreidx(sbh, origidx);
4755 +
4756 + INTR_RESTORE(si, intr_val);
4757 + return (w);
4758 +}
4759 +
4760 +/* scan the sb enumerated space to identify all cores */
4761 +static void
4762 +sb_scan(sb_info_t *si)
4763 +{
4764 + void *sbh;
4765 + uint origidx;
4766 + uint i;
4767 +
4768 + sbh = (void*) si;
4769 +
4770 + /* numcores should already be set */
4771 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
4772 +
4773 + /* save current core index */
4774 + origidx = sb_coreidx(sbh);
4775 +
4776 + si->pciidx = si->gpioidx = BADIDX;
4777 +
4778 + for (i = 0; i < si->numcores; i++) {
4779 + sb_setcoreidx(sbh, i);
4780 + si->coreid[i] = sb_coreid(sbh);
4781 +
4782 + if (si->coreid[i] == SB_CC)
4783 + si->ccrev = sb_corerev(sbh);
4784 +
4785 + else if (si->coreid[i] == SB_PCI) {
4786 + si->pciidx = i;
4787 + si->pcirev = sb_corerev(sbh);
4788 +
4789 + }else if (si->coreid[i] == SB_PCMCIA){
4790 + si->pcmciaidx = i;
4791 + si->pcmciarev = sb_corerev(sbh);
4792 + }
4793 + }
4794 +
4795 + /*
4796 + * Find the gpio "controlling core" type and index.
4797 + * Precedence:
4798 + * - if there's a chip common core - use that
4799 + * - else if there's a pci core (rev >= 2) - use that
4800 + * - else there had better be an extif core (4710 only)
4801 + */
4802 + if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) {
4803 + si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0);
4804 + si->gpioid = SB_CC;
4805 + } else if (GOODIDX(si->pciidx) && (si->pcirev >= 2)) {
4806 + si->gpioidx = si->pciidx;
4807 + si->gpioid = SB_PCI;
4808 + } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) {
4809 + si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0);
4810 + si->gpioid = SB_EXTIF;
4811 + }
4812 +
4813 + /* return to original core index */
4814 + sb_setcoreidx(sbh, origidx);
4815 +}
4816 +
4817 +/* may be called with core in reset */
4818 +void
4819 +sb_detach(void *sbh)
4820 +{
4821 + sb_info_t *si;
4822 + uint idx;
4823 +
4824 + si = SB_INFO(sbh);
4825 +
4826 + if (si == NULL)
4827 + return;
4828 +
4829 + if (si->bus == SB_BUS)
4830 + for (idx = 0; idx < SB_MAXCORES; idx++)
4831 + if (si->regs[idx]) {
4832 + REG_UNMAP(si->regs[idx]);
4833 + si->regs[idx] = NULL;
4834 + }
4835 +
4836 + MFREE(si, sizeof (sb_info_t));
4837 +}
4838 +
4839 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
4840 +static uint
4841 +sb_pcidev2chip(uint pcidev)
4842 +{
4843 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
4844 + return (BCM4710_DEVICE_ID);
4845 + if ((pcidev >= BCM4610_DEVICE_ID) && (pcidev <= BCM4610_USB_ID))
4846 + return (BCM4610_DEVICE_ID);
4847 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
4848 + return (BCM4402_DEVICE_ID);
4849 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
4850 + return (BCM4307_DEVICE_ID);
4851 + if (pcidev == BCM4301_DEVICE_ID)
4852 + return (BCM4301_DEVICE_ID);
4853 +
4854 + return (0);
4855 +}
4856 +
4857 +/* convert chip number to number of i/o cores */
4858 +static uint
4859 +sb_chip2numcores(uint chip)
4860 +{
4861 + if (chip == 0x4710)
4862 + return (9);
4863 + if (chip == 0x4610)
4864 + return (9);
4865 + if (chip == 0x4402)
4866 + return (3);
4867 + if ((chip == 0x4307) || (chip == 0x4301))
4868 + return (5);
4869 + if (chip == 0x4310)
4870 + return (8);
4871 + if (chip == 0x4306) /* < 4306c0 */
4872 + return (6);
4873 + if (chip == 0x4704)
4874 + return (9);
4875 + if (chip == 0x5365)
4876 + return (7);
4877 +
4878 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
4879 + ASSERT(0);
4880 + return (1);
4881 +}
4882 +
4883 +/* return index of coreid or BADIDX if not found */
4884 +static uint
4885 +sb_findcoreidx(void *sbh, uint coreid, uint coreunit)
4886 +{
4887 + sb_info_t *si;
4888 + uint found;
4889 + uint i;
4890 +
4891 + si = SB_INFO(sbh);
4892 + found = 0;
4893 +
4894 + for (i = 0; i < si->numcores; i++)
4895 + if (si->coreid[i] == coreid) {
4896 + if (found == coreunit)
4897 + return (i);
4898 + found++;
4899 + }
4900 +
4901 + return (BADIDX);
4902 +}
4903 +
4904 +/* change logical "focus" to the indiciated core */
4905 +void*
4906 +sb_setcoreidx(void *sbh, uint coreidx)
4907 +{
4908 + sb_info_t *si;
4909 + uint32 sbaddr;
4910 + uint8 tmp;
4911 +
4912 + si = SB_INFO(sbh);
4913 +
4914 + if (coreidx >= si->numcores)
4915 + return (NULL);
4916 +
4917 + /*
4918 + * If the user has provided an interrupt mask enabled function,
4919 + * then assert interrupts are disabled before switching the core.
4920 + */
4921 + ASSERT((si->imf == NULL) || !(*si->imf)(si->imfarg));
4922 +
4923 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
4924 +
4925 + switch (si->bus) {
4926 + case SB_BUS:
4927 + /* map new one */
4928 + if (!si->regs[coreidx]) {
4929 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
4930 + ASSERT(GOODREGS(si->regs[coreidx]));
4931 + }
4932 + si->curmap = si->regs[coreidx];
4933 + break;
4934 +
4935 + case PCI_BUS:
4936 + /* point bar0 window */
4937 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
4938 + break;
4939 +
4940 + case PCMCIA_BUS:
4941 + tmp = (sbaddr >> 12) & 0x0f;
4942 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
4943 + tmp = (sbaddr >> 16) & 0xff;
4944 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
4945 + tmp = (sbaddr >> 24) & 0xff;
4946 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
4947 + break;
4948 + }
4949 +
4950 + si->curidx = coreidx;
4951 +
4952 + return (si->curmap);
4953 +}
4954 +
4955 +/* change logical "focus" to the indicated core */
4956 +void*
4957 +sb_setcore(void *sbh, uint coreid, uint coreunit)
4958 +{
4959 + sb_info_t *si;
4960 + uint idx;
4961 +
4962 + si = SB_INFO(sbh);
4963 +
4964 + idx = sb_findcoreidx(sbh, coreid, coreunit);
4965 + if (!GOODIDX(idx))
4966 + return (NULL);
4967 +
4968 + return (sb_setcoreidx(sbh, idx));
4969 +}
4970 +
4971 +/* return chip number */
4972 +uint
4973 +sb_chip(void *sbh)
4974 +{
4975 + sb_info_t *si;
4976 +
4977 + si = SB_INFO(sbh);
4978 + return (si->chip);
4979 +}
4980 +
4981 +/* return chip revision number */
4982 +uint
4983 +sb_chiprev(void *sbh)
4984 +{
4985 + sb_info_t *si;
4986 +
4987 + si = SB_INFO(sbh);
4988 + return (si->chiprev);
4989 +}
4990 +
4991 +/* return chip package option */
4992 +uint
4993 +sb_chippkg(void *sbh)
4994 +{
4995 + sb_info_t *si;
4996 +
4997 + si = SB_INFO(sbh);
4998 + return (si->chippkg);
4999 +}
5000 +
5001 +/* return board vendor id */
5002 +uint
5003 +sb_boardvendor(void *sbh)
5004 +{
5005 + sb_info_t *si;
5006 +
5007 + si = SB_INFO(sbh);
5008 + return (si->boardvendor);
5009 +}
5010 +
5011 +/* return boardtype */
5012 +uint
5013 +sb_boardtype(void *sbh)
5014 +{
5015 + sb_info_t *si;
5016 + char *var;
5017 +
5018 + si = SB_INFO(sbh);
5019 +
5020 + if (si->bus == SB_BUS && si->boardtype == 0xffff) {
5021 + /* boardtype format is a hex string */
5022 + si->boardtype = getintvar(NULL, "boardtype");
5023 +
5024 + /* backward compatibility for older boardtype string format */
5025 + if ((si->boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
5026 + if (!strcmp(var, "bcm94710dev"))
5027 + si->boardtype = BCM94710D_BOARD;
5028 + else if (!strcmp(var, "bcm94710ap"))
5029 + si->boardtype = BCM94710AP_BOARD;
5030 + else if (!strcmp(var, "bcm94310u"))
5031 + si->boardtype = BCM94310U_BOARD;
5032 + else if (!strcmp(var, "bu4711"))
5033 + si->boardtype = BU4711_BOARD;
5034 + else if (!strcmp(var, "bu4710"))
5035 + si->boardtype = BU4710_BOARD;
5036 + else if (!strcmp(var, "bcm94702mn"))
5037 + si->boardtype = BCM94702MN_BOARD;
5038 + else if (!strcmp(var, "bcm94710r1"))
5039 + si->boardtype = BCM94710R1_BOARD;
5040 + else if (!strcmp(var, "bcm94710r4"))
5041 + si->boardtype = BCM94710R4_BOARD;
5042 + else if (!strcmp(var, "bcm94702cpci"))
5043 + si->boardtype = BCM94702CPCI_BOARD;
5044 + else if (!strcmp(var, "bcm95380_rr"))
5045 + si->boardtype = BCM95380RR_BOARD;
5046 + }
5047 + }
5048 +
5049 + return (si->boardtype);
5050 +}
5051 +
5052 +/* return board bus style */
5053 +uint
5054 +sb_boardstyle(void *sbh)
5055 +{
5056 + sb_info_t *si;
5057 + uint16 w;
5058 +
5059 + si = SB_INFO(sbh);
5060 +
5061 + if (si->bus == PCMCIA_BUS)
5062 + return (BOARDSTYLE_PCMCIA);
5063 +
5064 + if (si->bus == SB_BUS)
5065 + return (BOARDSTYLE_SOC);
5066 +
5067 + /* bus is PCI */
5068 +
5069 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CIS, sizeof (uint32)) != 0)
5070 + return (BOARDSTYLE_CARDBUS);
5071 +
5072 + if ((srom_read(si->bus, si->curmap, si->osh, (SPROM_SIZE - 1) * 2, 2, &w) == 0) &&
5073 + (w == 0x0313))
5074 + return (BOARDSTYLE_CARDBUS);
5075 +
5076 + return (BOARDSTYLE_PCI);
5077 +}
5078 +
5079 +/* return boolean if sbh device is in pci hostmode or client mode */
5080 +uint
5081 +sb_bus(void *sbh)
5082 +{
5083 + sb_info_t *si;
5084 +
5085 + si = SB_INFO(sbh);
5086 + return (si->bus);
5087 +}
5088 +
5089 +/* return list of found cores */
5090 +uint
5091 +sb_corelist(void *sbh, uint coreid[])
5092 +{
5093 + sb_info_t *si;
5094 +
5095 + si = SB_INFO(sbh);
5096 +
5097 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
5098 + return (si->numcores);
5099 +}
5100 +
5101 +/* return current register mapping */
5102 +void *
5103 +sb_coreregs(void *sbh)
5104 +{
5105 + sb_info_t *si;
5106 +
5107 + si = SB_INFO(sbh);
5108 + ASSERT(GOODREGS(si->curmap));
5109 +
5110 + return (si->curmap);
5111 +}
5112 +
5113 +/* Check if a target abort has happened and clear it */
5114 +bool
5115 +sb_taclear(void *sbh)
5116 +{
5117 + sb_info_t *si;
5118 + bool rc = FALSE;
5119 + sbconfig_t *sb;
5120 +
5121 + si = SB_INFO(sbh);
5122 + sb = REGS2SB(si->curmap);
5123 +
5124 + if (si->bus == PCI_BUS) {
5125 + uint32 stcmd;
5126 +
5127 + stcmd = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd));
5128 + rc = (stcmd & 0x08000000) != 0;
5129 +
5130 + if (rc) {
5131 + /* Target abort bit is set, clear it */
5132 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_CFG_CMD, sizeof(stcmd), stcmd);
5133 + }
5134 + } else if (si->bus == PCMCIA_BUS) {
5135 + rc = FALSE;
5136 + }
5137 + else if (si->bus == SDIO_BUS) {
5138 + /* due to 4317 A0 HW bug, sdio core wedged on target abort,
5139 + just clear SBSErr bit blindly */
5140 + if (0x0 != R_SBREG(sbh, &sb->sbtmerrlog)) {
5141 + SB_ERROR(("SDIO target abort, clean it"));
5142 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
5143 + }
5144 + rc = FALSE;
5145 + }
5146 +
5147 + return (rc);
5148 +}
5149 +
5150 +/* do buffered registers update */
5151 +void
5152 +sb_commit(void *sbh)
5153 +{
5154 + sb_info_t *si;
5155 + sbpciregs_t *pciregs;
5156 + uint origidx;
5157 + uint intr_val = 0;
5158 +
5159 + si = SB_INFO(sbh);
5160 +
5161 + origidx = si->curidx;
5162 + ASSERT(GOODIDX(origidx));
5163 +
5164 + INTR_OFF(si, intr_val);
5165 + /* switch over to pci core */
5166 + pciregs = (sbpciregs_t*) sb_setcore(sbh, SB_PCI, 0);
5167 +
5168 + /* do the buffer registers update */
5169 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
5170 + W_REG(&pciregs->bcastdata, 0x0);
5171 +
5172 + /* restore core index */
5173 + sb_setcoreidx(sbh, origidx);
5174 + INTR_RESTORE(si, intr_val);
5175 +}
5176 +
5177 +/* reset and re-enable a core */
5178 +void
5179 +sb_core_reset(void *sbh, uint32 bits)
5180 +{
5181 + sb_info_t *si;
5182 + sbconfig_t *sb;
5183 + volatile uint32 dummy;
5184 +
5185 + si = SB_INFO(sbh);
5186 + ASSERT(GOODREGS(si->curmap));
5187 + sb = REGS2SB(si->curmap);
5188 +
5189 + /*
5190 + * Must do the disable sequence first to work for arbitrary current core state.
5191 + */
5192 + sb_core_disable(sbh, bits);
5193 +
5194 + /*
5195 + * Now do the initialization sequence.
5196 + */
5197 +
5198 + /* set reset while enabling the clock and forcing them on throughout the core */
5199 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
5200 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5201 +
5202 + if (sb_coreid(sbh) == SB_ILINE100) {
5203 + bcm_mdelay(50);
5204 + } else {
5205 + OSL_DELAY(1);
5206 + }
5207 +
5208 + if (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_SERR) {
5209 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
5210 + }
5211 + if ((dummy = R_SBREG(sbh, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
5212 + AND_SBREG(sbh, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
5213 + }
5214 +
5215 + /* clear reset and allow it to propagate throughout the core */
5216 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
5217 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5218 + OSL_DELAY(1);
5219 +
5220 + /* leave clock enabled */
5221 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | bits));
5222 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5223 + OSL_DELAY(1);
5224 +}
5225 +
5226 +void
5227 +sb_core_tofixup(void *sbh)
5228 +{
5229 + sb_info_t *si;
5230 + sbconfig_t *sb;
5231 +
5232 + si = SB_INFO(sbh);
5233 +
5234 + if (si->pcirev >= 5)
5235 + return;
5236 +
5237 + ASSERT(GOODREGS(si->curmap));
5238 + sb = REGS2SB(si->curmap);
5239 +
5240 + if (si->bus == SB_BUS) {
5241 + SET_SBREG(sbh, &sb->sbimconfiglow,
5242 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5243 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
5244 + } else {
5245 + if (sb_coreid(sbh) == SB_PCI) {
5246 + SET_SBREG(sbh, &sb->sbimconfiglow,
5247 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5248 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
5249 + } else {
5250 + SET_SBREG(sbh, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
5251 + }
5252 + }
5253 +
5254 + sb_commit(sbh);
5255 +}
5256 +
5257 +void
5258 +sb_core_disable(void *sbh, uint32 bits)
5259 +{
5260 + sb_info_t *si;
5261 + volatile uint32 dummy;
5262 + sbconfig_t *sb;
5263 +
5264 + si = SB_INFO(sbh);
5265 +
5266 + ASSERT(GOODREGS(si->curmap));
5267 + sb = REGS2SB(si->curmap);
5268 +
5269 + /* must return if core is already in reset */
5270 + if (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_RESET)
5271 + return;
5272 +
5273 + /* put into reset and return if clocks are not enabled */
5274 + if ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_CLK) == 0)
5275 + goto disable;
5276 +
5277 + /* set the reject bit */
5278 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | SBTML_REJ));
5279 +
5280 + /* spin until reject is set */
5281 + while ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_REJ) == 0)
5282 + OSL_DELAY(1);
5283 +
5284 + /* spin until sbtmstatehigh.busy is clear */
5285 + while (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_BUSY)
5286 + OSL_DELAY(1);
5287 +
5288 + /* set reset and reject while enabling the clocks */
5289 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET));
5290 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
5291 + OSL_DELAY(10);
5292 +
5293 + disable:
5294 + /* leave reset and reject asserted */
5295 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_REJ | SBTML_RESET));
5296 + OSL_DELAY(1);
5297 +}
5298 +
5299 +void
5300 +sb_watchdog(void *sbh, uint ticks)
5301 +{
5302 + sb_info_t *si = SB_INFO(sbh);
5303 +
5304 + /* instant NMI */
5305 + switch (si->gpioid) {
5306 + case SB_CC:
5307 + sb_corereg(sbh, si->gpioidx, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
5308 + break;
5309 + case SB_EXTIF:
5310 + sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
5311 + break;
5312 + }
5313 +}
5314 +
5315 +/* initialize the pcmcia core */
5316 +void
5317 +sb_pcmcia_init(void *sbh)
5318 +{
5319 + sb_info_t *si;
5320 + uint8 cor;
5321 +
5322 + si = SB_INFO(sbh);
5323 +
5324 + /* enable d11 mac interrupts */
5325 + if (si->chip == BCM4301_DEVICE_ID) {
5326 + /* Have to use FCR2 in 4301 */
5327 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
5328 + cor |= COR_IRQEN | COR_FUNEN;
5329 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
5330 + } else {
5331 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
5332 + cor |= COR_IRQEN | COR_FUNEN;
5333 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
5334 + }
5335 +
5336 +}
5337 +
5338 +
5339 +/*
5340 + * Configure the pci core for pci client (NIC) action
5341 + * and get appropriate dma offset value.
5342 + * coremask is the bitvec of cores by index to be enabled.
5343 + */
5344 +void
5345 +sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask)
5346 +{
5347 + sb_info_t *si;
5348 + sbconfig_t *sb;
5349 + sbpciregs_t *pciregs;
5350 + uint32 sbflag;
5351 + uint32 w;
5352 + uint idx;
5353 +
5354 + si = SB_INFO(sbh);
5355 +
5356 + if (dmaoffset)
5357 + *dmaoffset = 0;
5358 +
5359 + /* if not pci bus, we're done */
5360 + if (si->bus != PCI_BUS)
5361 + return;
5362 +
5363 + ASSERT(si->pciidx);
5364 +
5365 + /* get current core index */
5366 + idx = si->curidx;
5367 +
5368 + /* we interrupt on this backplane flag number */
5369 + ASSERT(GOODREGS(si->curmap));
5370 + sb = REGS2SB(si->curmap);
5371 + sbflag = R_SBREG(sbh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
5372 +
5373 + /* switch over to pci core */
5374 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->pciidx);
5375 + sb = REGS2SB(pciregs);
5376 +
5377 + /*
5378 + * Enable sb->pci interrupts. Assume
5379 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
5380 + */
5381 + if (si->pcirev < 6) {
5382 + /* set sbintvec bit for our flag number */
5383 + OR_SBREG(sbh, &sb->sbintvec, (1 << sbflag));
5384 + } else {
5385 + /* pci config write to set this core bit in PCIIntMask */
5386 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
5387 + w |= (coremask << PCI_SBIM_SHIFT);
5388 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
5389 + }
5390 +
5391 + /* enable prefetch and bursts for sonics-to-pci translation 2 */
5392 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
5393 +
5394 + if (si->pcirev < 5) {
5395 + SET_SBREG(sbh, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
5396 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
5397 + sb_commit(sbh);
5398 + }
5399 +
5400 + /* switch back to previous core */
5401 + sb_setcoreidx(sbh, idx);
5402 +
5403 + /* use large sb pci dma window */
5404 + if (dmaoffset)
5405 + *dmaoffset = SB_PCI_DMA;
5406 +}
5407 +
5408 +uint32
5409 +sb_base(uint32 admatch)
5410 +{
5411 + uint32 base;
5412 + uint type;
5413 +
5414 + type = admatch & SBAM_TYPE_MASK;
5415 + ASSERT(type < 3);
5416 +
5417 + base = 0;
5418 +
5419 + if (type == 0) {
5420 + base = admatch & SBAM_BASE0_MASK;
5421 + } else if (type == 1) {
5422 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5423 + base = admatch & SBAM_BASE1_MASK;
5424 + } else if (type == 2) {
5425 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5426 + base = admatch & SBAM_BASE2_MASK;
5427 + }
5428 +
5429 + return (base);
5430 +}
5431 +
5432 +uint32
5433 +sb_size(uint32 admatch)
5434 +{
5435 + uint32 size;
5436 + uint type;
5437 +
5438 + type = admatch & SBAM_TYPE_MASK;
5439 + ASSERT(type < 3);
5440 +
5441 + size = 0;
5442 +
5443 + if (type == 0) {
5444 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
5445 + } else if (type == 1) {
5446 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5447 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
5448 + } else if (type == 2) {
5449 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
5450 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
5451 + }
5452 +
5453 + return (size);
5454 +}
5455 +
5456 +/* return the core-type instantiation # of the current core */
5457 +uint
5458 +sb_coreunit(void *sbh)
5459 +{
5460 + sb_info_t *si;
5461 + uint idx;
5462 + uint coreid;
5463 + uint coreunit;
5464 + uint i;
5465 +
5466 + si = SB_INFO(sbh);
5467 + coreunit = 0;
5468 +
5469 + idx = si->curidx;
5470 +
5471 + ASSERT(GOODREGS(si->curmap));
5472 + coreid = sb_coreid(sbh);
5473 +
5474 + /* count the cores of our type */
5475 + for (i = 0; i < idx; i++)
5476 + if (si->coreid[i] == coreid)
5477 + coreunit++;
5478 +
5479 + return (coreunit);
5480 +}
5481 +
5482 +static INLINE uint32
5483 +factor6(uint32 x)
5484 +{
5485 + switch (x) {
5486 + case CC_F6_2: return 2;
5487 + case CC_F6_3: return 3;
5488 + case CC_F6_4: return 4;
5489 + case CC_F6_5: return 5;
5490 + case CC_F6_6: return 6;
5491 + case CC_F6_7: return 7;
5492 + default: return 0;
5493 + }
5494 +}
5495 +
5496 +/* calculate the speed the SB would run at given a set of clockcontrol values */
5497 +uint32
5498 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
5499 +{
5500 + uint32 n1, n2, clock, m1, m2, m3, mc;
5501 +
5502 + n1 = n & CN_N1_MASK;
5503 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
5504 +
5505 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
5506 + n1 = factor6(n1);
5507 + n2 += CC_F5_BIAS;
5508 + } else if (pll_type == PLL_TYPE2) {
5509 + n1 += CC_T2_BIAS;
5510 + n2 += CC_T2_BIAS;
5511 + ASSERT((n1 >= 2) && (n1 <= 7));
5512 + ASSERT((n2 >= 5) && (n2 <= 23));
5513 + } else if (pll_type == PLL_TYPE3) {
5514 + return (100000000);
5515 + } else
5516 + ASSERT((pll_type >= PLL_TYPE1) && (pll_type <= PLL_TYPE4));
5517 +
5518 + clock = CC_CLOCK_BASE * n1 * n2;
5519 +
5520 + if (clock == 0)
5521 + return 0;
5522 +
5523 + m1 = m & CC_M1_MASK;
5524 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
5525 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
5526 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
5527 +
5528 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE4)) {
5529 + m1 = factor6(m1);
5530 + if (pll_type == PLL_TYPE1)
5531 + m2 += CC_F5_BIAS;
5532 + else
5533 + m2 = factor6(m2);
5534 + m3 = factor6(m3);
5535 +
5536 + switch (mc) {
5537 + case CC_MC_BYPASS: return (clock);
5538 + case CC_MC_M1: return (clock / m1);
5539 + case CC_MC_M1M2: return (clock / (m1 * m2));
5540 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
5541 + case CC_MC_M1M3: return (clock / (m1 * m3));
5542 + default: return (0);
5543 + }
5544 + } else {
5545 + ASSERT(pll_type == PLL_TYPE2);
5546 +
5547 + m1 += CC_T2_BIAS;
5548 + m2 += CC_T2M2_BIAS;
5549 + m3 += CC_T2_BIAS;
5550 + ASSERT((m1 >= 2) && (m1 <= 7));
5551 + ASSERT((m2 >= 3) && (m2 <= 10));
5552 + ASSERT((m3 >= 2) && (m3 <= 7));
5553 +
5554 + if ((mc & CC_T2MC_M1BYP) == 0)
5555 + clock /= m1;
5556 + if ((mc & CC_T2MC_M2BYP) == 0)
5557 + clock /= m2;
5558 + if ((mc & CC_T2MC_M3BYP) == 0)
5559 + clock /= m3;
5560 +
5561 + return(clock);
5562 + }
5563 +}
5564 +
5565 +/* returns the current speed the SB is running at */
5566 +uint32
5567 +sb_clock(void *sbh)
5568 +{
5569 + sb_info_t *si;
5570 + extifregs_t *eir;
5571 + chipcregs_t *cc;
5572 + uint32 n, m;
5573 + uint idx;
5574 + uint32 pll_type, rate;
5575 + uint intr_val = 0;
5576 +
5577 + si = SB_INFO(sbh);
5578 + idx = si->curidx;
5579 + pll_type = PLL_TYPE1;
5580 +
5581 + INTR_OFF(si, intr_val);
5582 +
5583 + /* switch to extif or chipc core */
5584 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
5585 + n = R_REG(&eir->clockcontrol_n);
5586 + m = R_REG(&eir->clockcontrol_sb);
5587 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
5588 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
5589 + n = R_REG(&cc->clockcontrol_n);
5590 + m = R_REG(&cc->clockcontrol_sb);
5591 + } else {
5592 + INTR_RESTORE(si, intr_val);
5593 + return 0;
5594 + }
5595 +
5596 + /* calculate rate */
5597 + rate = sb_clock_rate(pll_type, n, m);
5598 +
5599 + /* switch back to previous core */
5600 + sb_setcoreidx(sbh, idx);
5601 +
5602 + INTR_RESTORE(si, intr_val);
5603 +
5604 + return rate;
5605 +}
5606 +
5607 +/* change logical "focus" to the gpio core for optimized access */
5608 +void*
5609 +sb_gpiosetcore(void *sbh)
5610 +{
5611 + sb_info_t *si;
5612 +
5613 + si = SB_INFO(sbh);
5614 +
5615 + return (sb_setcoreidx(sbh, si->gpioidx));
5616 +}
5617 +
5618 +/* mask&set gpiocontrol bits */
5619 +uint32
5620 +sb_gpiocontrol(void *sbh, uint32 mask, uint32 val)
5621 +{
5622 + sb_info_t *si;
5623 + uint regoff;
5624 +
5625 + si = SB_INFO(sbh);
5626 + regoff = 0;
5627 +
5628 + switch (si->gpioid) {
5629 + case SB_CC:
5630 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
5631 + break;
5632 +
5633 + case SB_PCI:
5634 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
5635 + break;
5636 +
5637 + case SB_EXTIF:
5638 + return (0);
5639 + }
5640 +
5641 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5642 +}
5643 +
5644 +/* mask&set gpio output enable bits */
5645 +uint32
5646 +sb_gpioouten(void *sbh, uint32 mask, uint32 val)
5647 +{
5648 + sb_info_t *si;
5649 + uint regoff;
5650 +
5651 + si = SB_INFO(sbh);
5652 + regoff = 0;
5653 +
5654 + switch (si->gpioid) {
5655 + case SB_CC:
5656 + regoff = OFFSETOF(chipcregs_t, gpioouten);
5657 + break;
5658 +
5659 + case SB_PCI:
5660 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
5661 + break;
5662 +
5663 + case SB_EXTIF:
5664 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
5665 + break;
5666 + }
5667 +
5668 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5669 +}
5670 +
5671 +/* mask&set gpio output bits */
5672 +uint32
5673 +sb_gpioout(void *sbh, uint32 mask, uint32 val)
5674 +{
5675 + sb_info_t *si;
5676 + uint regoff;
5677 +
5678 + si = SB_INFO(sbh);
5679 + regoff = 0;
5680 +
5681 + switch (si->gpioid) {
5682 + case SB_CC:
5683 + regoff = OFFSETOF(chipcregs_t, gpioout);
5684 + break;
5685 +
5686 + case SB_PCI:
5687 + regoff = OFFSETOF(sbpciregs_t, gpioout);
5688 + break;
5689 +
5690 + case SB_EXTIF:
5691 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
5692 + break;
5693 + }
5694 +
5695 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5696 +}
5697 +
5698 +/* return the current gpioin register value */
5699 +uint32
5700 +sb_gpioin(void *sbh)
5701 +{
5702 + sb_info_t *si;
5703 + uint regoff;
5704 +
5705 + si = SB_INFO(sbh);
5706 + regoff = 0;
5707 +
5708 + switch (si->gpioid) {
5709 + case SB_CC:
5710 + regoff = OFFSETOF(chipcregs_t, gpioin);
5711 + break;
5712 +
5713 + case SB_PCI:
5714 + regoff = OFFSETOF(sbpciregs_t, gpioin);
5715 + break;
5716 +
5717 + case SB_EXTIF:
5718 + regoff = OFFSETOF(extifregs_t, gpioin);
5719 + break;
5720 + }
5721 +
5722 + return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0));
5723 +}
5724 +
5725 +/* mask&set gpio interrupt polarity bits */
5726 +uint32
5727 +sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val)
5728 +{
5729 + sb_info_t *si;
5730 + uint regoff;
5731 +
5732 + si = SB_INFO(sbh);
5733 + regoff = 0;
5734 +
5735 + switch (si->gpioid) {
5736 + case SB_CC:
5737 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
5738 + break;
5739 +
5740 + case SB_PCI:
5741 + /* pci gpio implementation does not support interrupt polarity */
5742 + ASSERT(0);
5743 + break;
5744 +
5745 + case SB_EXTIF:
5746 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
5747 + break;
5748 + }
5749 +
5750 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5751 +}
5752 +
5753 +/* mask&set gpio interrupt mask bits */
5754 +uint32
5755 +sb_gpiointmask(void *sbh, uint32 mask, uint32 val)
5756 +{
5757 + sb_info_t *si;
5758 + uint regoff;
5759 +
5760 + si = SB_INFO(sbh);
5761 + regoff = 0;
5762 +
5763 + switch (si->gpioid) {
5764 + case SB_CC:
5765 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
5766 + break;
5767 +
5768 + case SB_PCI:
5769 + /* pci gpio implementation does not support interrupt mask */
5770 + ASSERT(0);
5771 + break;
5772 +
5773 + case SB_EXTIF:
5774 + regoff = OFFSETOF(extifregs_t, gpiointmask);
5775 + break;
5776 + }
5777 +
5778 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
5779 +}
5780 +
5781 +
5782 +/*
5783 + * Return the slowclock min or max frequency.
5784 + * Three sources of SLOW CLOCK:
5785 + * 1. On Chip LPO - 32khz or 160khz
5786 + * 2. On Chip Xtal OSC - 20mhz/4*(divider+1)
5787 + * 3. External PCI clock - 66mhz/4*(divider+1)
5788 + */
5789 +static uint
5790 +slowfreq(void *sbh, bool max)
5791 +{
5792 + sb_info_t *si;
5793 + chipcregs_t *cc;
5794 + uint32 v;
5795 + uint div;
5796 +
5797 + si = SB_INFO(sbh);
5798 +
5799 + ASSERT(sb_coreid(sbh) == SB_CC);
5800 +
5801 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
5802 +
5803 + /* shouldn't be here unless we've established the chip has dynamic power control */
5804 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
5805 +
5806 + if (si->ccrev < 6) {
5807 + v = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5808 +
5809 + if (v & PCI_CFG_GPIO_SCS)
5810 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
5811 + else
5812 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
5813 + } else {
5814 + v = R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
5815 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
5816 + if (v == SCC_SS_LPO)
5817 + return (max? LPOMAXFREQ : LPOMINFREQ);
5818 + else if (v == SCC_SS_XTAL)
5819 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
5820 + else if (v == SCC_SS_PCI)
5821 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
5822 + else
5823 + ASSERT(0);
5824 + }
5825 + return (0);
5826 +}
5827 +
5828 +/* initialize power control delay registers */
5829 +void
5830 +sb_pwrctl_init(void *sbh)
5831 +{
5832 + sb_info_t *si;
5833 + uint origidx;
5834 + chipcregs_t *cc;
5835 + uint slowmaxfreq;
5836 + uint pll_on_delay, fref_sel_delay;
5837 +
5838 + si = SB_INFO(sbh);
5839 +
5840 + if (si->bus == SB_BUS)
5841 + return;
5842 +
5843 + origidx = si->curidx;
5844 +
5845 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5846 + return;
5847 +
5848 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5849 + goto done;
5850 +
5851 + slowmaxfreq = slowfreq(sbh, TRUE);
5852 + pll_on_delay = ((slowmaxfreq * PLL_DELAY) + 999999) / 1000000;
5853 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
5854 +
5855 + W_REG(&cc->pll_on_delay, pll_on_delay);
5856 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
5857 +
5858 + /* 4317pc does not work with SlowClock less than 5Mhz */
5859 + if (si->bus == PCMCIA_BUS)
5860 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (0 << SCC_CD_SHF));
5861 +
5862 +done:
5863 + sb_setcoreidx(sbh, origidx);
5864 +}
5865 +
5866 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5867 +uint16
5868 +sb_pwrctl_fast_pwrup_delay(void *sbh)
5869 +{
5870 + sb_info_t *si;
5871 + uint origidx;
5872 + chipcregs_t *cc;
5873 + uint slowminfreq;
5874 + uint16 fpdelay;
5875 + uint intr_val = 0;
5876 +
5877 + si = SB_INFO(sbh);
5878 + fpdelay = 0;
5879 + origidx = si->curidx;
5880 +
5881 + if (si->bus == SB_BUS)
5882 + goto done;
5883 +
5884 + INTR_OFF(si, intr_val);
5885 +
5886 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5887 + goto done;
5888 +
5889 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5890 + goto done;
5891 +
5892 + slowminfreq = slowfreq(sbh, FALSE);
5893 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5894 +
5895 +done:
5896 + sb_setcoreidx(sbh, origidx);
5897 + INTR_RESTORE(si, intr_val);
5898 + return (fpdelay);
5899 +}
5900 +
5901 +/* turn primary xtal and/or pll off/on */
5902 +int
5903 +sb_pwrctl_xtal(void *sbh, uint what, bool on)
5904 +{
5905 + sb_info_t *si;
5906 + uint32 in, out, outen;
5907 +
5908 + si = SB_INFO(sbh);
5909 +
5910 +
5911 + if (si->bus == PCMCIA_BUS) {
5912 + return (0);
5913 + }
5914 +
5915 + if (si->bus != PCI_BUS)
5916 + return (-1);
5917 +
5918 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5919 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5920 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5921 +
5922 + /*
5923 + * We can't actually read the state of the PLLPD so we infer it
5924 + * by the value of XTAL_PU which *is* readable via gpioin.
5925 + */
5926 + if (on && (in & PCI_CFG_GPIO_XTAL))
5927 + return (0);
5928 +
5929 + if (what & XTAL)
5930 + outen |= PCI_CFG_GPIO_XTAL;
5931 + if (what & PLL)
5932 + outen |= PCI_CFG_GPIO_PLL;
5933 +
5934 + if (on) {
5935 + /* turn primary xtal on */
5936 + if (what & XTAL) {
5937 + out |= PCI_CFG_GPIO_XTAL;
5938 + if (what & PLL)
5939 + out |= PCI_CFG_GPIO_PLL;
5940 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5941 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5942 + OSL_DELAY(200);
5943 + }
5944 +
5945 + /* turn pll on */
5946 + if (what & PLL) {
5947 + out &= ~PCI_CFG_GPIO_PLL;
5948 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5949 + OSL_DELAY(2000);
5950 + }
5951 + } else {
5952 + if (what & XTAL)
5953 + out &= ~PCI_CFG_GPIO_XTAL;
5954 + if (what & PLL)
5955 + out |= PCI_CFG_GPIO_PLL;
5956 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5957 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5958 + }
5959 +
5960 + return (0);
5961 +}
5962 +
5963 +/* set dynamic power control mode (forceslow, forcefast, dynamic) */
5964 +/* returns true if ignore pll off is set and false if it is not */
5965 +bool
5966 +sb_pwrctl_clk(void *sbh, uint mode)
5967 +{
5968 + sb_info_t *si;
5969 + uint origidx;
5970 + chipcregs_t *cc;
5971 + uint32 scc;
5972 + bool forcefastclk=FALSE;
5973 + uint intr_val = 0;
5974 +
5975 + si = SB_INFO(sbh);
5976 +
5977 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
5978 + if (si->ccrev < 6)
5979 + return (FALSE);
5980 +
5981 + INTR_OFF(si, intr_val);
5982 +
5983 + origidx = si->curidx;
5984 +
5985 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5986 + ASSERT(cc != NULL);
5987 +
5988 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5989 + goto done;
5990 +
5991 + switch (mode) {
5992 + case CLK_FAST: /* force fast (pll) clock */
5993 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5994 + sb_pwrctl_xtal(sbh, XTAL, ON);
5995 +
5996 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5997 + break;
5998 +
5999 + case CLK_SLOW: /* force slow clock */
6000 + if ((si->bus == SDIO_BUS) || (si->bus == PCMCIA_BUS))
6001 + return (-1);
6002 +
6003 + if (si->ccrev >= 6)
6004 + OR_REG(&cc->slow_clk_ctl, SCC_FS);
6005 + break;
6006 +
6007 + case CLK_DYNAMIC: /* enable dynamic power control */
6008 + scc = R_REG(&cc->slow_clk_ctl);
6009 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
6010 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
6011 + scc |= SCC_XC;
6012 + W_REG(&cc->slow_clk_ctl, scc);
6013 +
6014 + /* for dynamic control, we have to release our xtal_pu "force on" */
6015 + if (scc & SCC_XC)
6016 + sb_pwrctl_xtal(sbh, XTAL, OFF);
6017 + break;
6018 + }
6019 +
6020 + /* Is the h/w forcing the use of the fast clk */
6021 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
6022 +
6023 +done:
6024 + sb_setcoreidx(sbh, origidx);
6025 + INTR_RESTORE(si, intr_val);
6026 + return (forcefastclk);
6027 +}
6028 +
6029 +/* register driver interrupt disabling and restoring callback functions */
6030 +void
6031 +sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg)
6032 +{
6033 + sb_info_t *si;
6034 +
6035 + si = SB_INFO(sbh);
6036 + si->intr_arg = intr_arg;
6037 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
6038 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
6039 + /* save current core id. when this function called, the current core
6040 + * must be the core which provides driver functions(il, et, wl, etc.)
6041 + */
6042 + si->dev_coreid = si->coreid[si->curidx];
6043 +}
6044 +
6045 +
6046 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcm4710.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcm4710.h
6047 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
6048 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcm4710.h 2005-09-16 10:29:18.172592248 +0200
6049 @@ -0,0 +1,90 @@
6050 +/*
6051 + * BCM4710 address space map and definitions
6052 + * Think twice before adding to this file, this is not the kitchen sink
6053 + * These definitions are not guaranteed for all 47xx chips, only the 4710
6054 + *
6055 + * Copyright 2001-2003, Broadcom Corporation
6056 + * All Rights Reserved.
6057 + *
6058 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6059 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6060 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6061 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6062 + * $Id$
6063 + */
6064 +
6065 +#ifndef _bcm4710_h_
6066 +#define _bcm4710_h_
6067 +
6068 +/* Address map */
6069 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
6070 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
6071 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
6072 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
6073 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6074 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
6075 +
6076 +/* Core register space */
6077 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
6078 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
6079 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
6080 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
6081 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
6082 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
6083 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
6084 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
6085 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
6086 +
6087 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
6088 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
6089 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
6090 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
6091 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
6092 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
6093 +
6094 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6095 +
6096 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
6097 +
6098 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
6099 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
6100 +
6101 +#define SBFLAG_PCI 0
6102 +#define SBFLAG_ENET0 1
6103 +#define SBFLAG_ILINE20 2
6104 +#define SBFLAG_CODEC 3
6105 +#define SBFLAG_USB 4
6106 +#define SBFLAG_EXTIF 5
6107 +#define SBFLAG_ENET1 6
6108 +
6109 +#ifdef CONFIG_HWSIM
6110 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
6111 +#else
6112 +#define BCM4710_TRACE(trval)
6113 +#endif
6114 +
6115 +
6116 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
6117 +
6118 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
6119 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
6120 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
6121 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
6122 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
6123 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
6124 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
6125 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
6126 +
6127 +#define LED_REG(x) \
6128 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
6129 +
6130 +/*
6131 + * Reset function implemented in PLD. Read or write should trigger hard reset
6132 + */
6133 +#define SYS_HARD_RESET() \
6134 + { for (;;) \
6135 + *( (volatile unsigned char *)\
6136 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
6137 + }
6138 +
6139 +#endif /* _bcm4710_h_ */
6140 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmdevs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmdevs.h
6141 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
6142 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-09-16 10:29:18.173592096 +0200
6143 @@ -0,0 +1,238 @@
6144 +/*
6145 + * Broadcom device-specific manifest constants.
6146 + *
6147 + * $Id$
6148 + * Copyright 2001-2003, Broadcom Corporation
6149 + * All Rights Reserved.
6150 + *
6151 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6152 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6153 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6154 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6155 + */
6156 +
6157 +#ifndef _BCMDEVS_H
6158 +#define _BCMDEVS_H
6159 +
6160 +
6161 +/* Known PCI vendor Id's */
6162 +#define VENDOR_EPIGRAM 0xfeda
6163 +#define VENDOR_BROADCOM 0x14e4
6164 +#define VENDOR_3COM 0x10b7
6165 +#define VENDOR_NETGEAR 0x1385
6166 +#define VENDOR_DIAMOND 0x1092
6167 +#define VENDOR_DELL 0x1028
6168 +#define VENDOR_HP 0x0e11
6169 +#define VENDOR_APPLE 0x106b
6170 +
6171 +/* PCI Device Id's */
6172 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
6173 +#define BCM4211_DEVICE_ID 0x4211
6174 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
6175 +#define BCM4231_DEVICE_ID 0x4231
6176 +
6177 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
6178 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
6179 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
6180 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
6181 +
6182 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
6183 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
6184 +
6185 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
6186 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
6187 +
6188 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
6189 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
6190 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
6191 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
6192 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
6193 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
6194 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
6195 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
6196 +
6197 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
6198 +
6199 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
6200 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
6201 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
6202 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
6203 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
6204 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
6205 +
6206 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
6207 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
6208 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
6209 +
6210 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
6211 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
6212 +
6213 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
6214 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
6215 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
6216 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
6217 +
6218 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
6219 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
6220 +#define BCM4306_D11G_ID2 0x4325
6221 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
6222 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
6223 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
6224 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
6225 +
6226 +#define BCM4309_PKG_ID 1 /* 4309 package id */
6227 +
6228 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
6229 +#define BCM4303_PKG_ID 2 /* 4303 package id */
6230 +
6231 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
6232 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
6233 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
6234 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
6235 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
6236 +
6237 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
6238 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
6239 +
6240 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
6241 +
6242 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
6243 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
6244 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
6245 +
6246 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
6247 +
6248 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
6249 +
6250 +
6251 +/* PCMCIA vendor Id's */
6252 +
6253 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
6254 +
6255 +/* SDIO vendor Id's */
6256 +#define VENDOR_BROADCOM_SDIO 0x00BF
6257 +
6258 +
6259 +/* boardflags */
6260 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
6261 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
6262 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
6263 +#define BFL_ENETSPI 0x0010 /* This board has ephy roboswitch spi */
6264 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
6265 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
6266 +#define BFL_ENETVLAN 0x0100 /* This board can do vlan */
6267 +
6268 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6269 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6270 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6271 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6272 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6273 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6274 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6275 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6276 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6277 +
6278 +/* Bus types */
6279 +#define SB_BUS 0 /* Silicon Backplane */
6280 +#define PCI_BUS 1 /* PCI target */
6281 +#define PCMCIA_BUS 2 /* PCMCIA target */
6282 +#define SDIO_BUS 3 /* SDIO target */
6283 +
6284 +/* Reference Board Types */
6285 +
6286 +#define BU4710_BOARD 0x0400
6287 +#define VSIM4710_BOARD 0x0401
6288 +#define QT4710_BOARD 0x0402
6289 +
6290 +#define BU4610_BOARD 0x0403
6291 +#define VSIM4610_BOARD 0x0404
6292 +
6293 +#define BU4307_BOARD 0x0405
6294 +#define BCM94301CB_BOARD 0x0406
6295 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6296 +#define BCM94301MP_BOARD 0x0407
6297 +#define BCM94307MP_BOARD 0x0408
6298 +#define BCMAP4307_BOARD 0x0409
6299 +
6300 +#define BU4309_BOARD 0x040a
6301 +#define BCM94309CB_BOARD 0x040b
6302 +#define BCM94309MP_BOARD 0x040c
6303 +#define BCM4309AP_BOARD 0x040d
6304 +
6305 +#define BCM94302MP_BOARD 0x040e
6306 +
6307 +#define VSIM4310_BOARD 0x040f
6308 +#define BU4711_BOARD 0x0410
6309 +#define BCM94310U_BOARD 0x0411
6310 +#define BCM94310AP_BOARD 0x0412
6311 +#define BCM94310MP_BOARD 0x0414
6312 +
6313 +#define BU4306_BOARD 0x0416
6314 +#define BCM94306CB_BOARD 0x0417
6315 +#define BCM94306MP_BOARD 0x0418
6316 +
6317 +#define BCM94710D_BOARD 0x041a
6318 +#define BCM94710R1_BOARD 0x041b
6319 +#define BCM94710R4_BOARD 0x041c
6320 +#define BCM94710AP_BOARD 0x041d
6321 +
6322 +
6323 +#define BU2050_BOARD 0x041f
6324 +
6325 +
6326 +#define BCM94309G_BOARD 0x0421
6327 +
6328 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6329 +
6330 +#define BU4704_BOARD 0x0423
6331 +#define BU4702_BOARD 0x0424
6332 +
6333 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6334 +
6335 +#define BU4317_BOARD 0x0426
6336 +
6337 +
6338 +#define BCM94702MN_BOARD 0x0428
6339 +
6340 +/* BCM4702 1U CompactPCI Board */
6341 +#define BCM94702CPCI_BOARD 0x0429
6342 +
6343 +/* BCM4702 with BCM95380 VLAN Router */
6344 +#define BCM95380RR_BOARD 0x042a
6345 +
6346 +/* cb4306 with SiGe PA */
6347 +#define BCM94306CBSG_BOARD 0x042b
6348 +
6349 +/* mp4301 with 2050 radio */
6350 +#define BCM94301MPL_BOARD 0x042c
6351 +
6352 +/* cb4306 with SiGe PA */
6353 +#define PCSG94306_BOARD 0x042d
6354 +
6355 +/* bu4704 with sdram */
6356 +#define BU4704SD_BOARD 0x042e
6357 +
6358 +/* Dual 11a/11g Router */
6359 +#define BCM94704AGR_BOARD 0x042f
6360 +
6361 +/* 11a-only minipci */
6362 +#define BCM94308MP_BOARD 0x0430
6363 +
6364 +
6365 +
6366 +/* BCM94317 boards */
6367 +#define BCM94317CB_BOARD 0x0440
6368 +#define BCM94317MP_BOARD 0x0441
6369 +#define BCM94317PCMCIA_BOARD 0x0442
6370 +#define BCM94317SDIO_BOARD 0x0443
6371 +
6372 +#define BU4712_BOARD 0x0444
6373 +
6374 +/* BCM4712 boards */
6375 +#define BCM94712AGR_BOARD 0x0445
6376 +#define BCM94712AP_BOARD 0x0446
6377 +
6378 +/* BCM4702 boards */
6379 +#define CT4702AP_BOARD 0x0447
6380 +
6381 +#endif /* _BCMDEVS_H */
6382 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmendian.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmendian.h
6383 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6384 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-09-16 10:29:18.173592096 +0200
6385 @@ -0,0 +1,125 @@
6386 +/*******************************************************************************
6387 + * $Id$
6388 + * Copyright 2001-2003, Broadcom Corporation
6389 + * All Rights Reserved.
6390 + *
6391 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6392 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6393 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6394 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6395 + * local version of endian.h - byte order defines
6396 + ******************************************************************************/
6397 +
6398 +#ifndef _BCMENDIAN_H_
6399 +#define _BCMENDIAN_H_
6400 +
6401 +#include <typedefs.h>
6402 +
6403 +/* Byte swap a 16 bit value */
6404 +#define BCMSWAP16(val) \
6405 + ((uint16)( \
6406 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6407 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6408 +
6409 +/* Byte swap a 32 bit value */
6410 +#define BCMSWAP32(val) \
6411 + ((uint32)( \
6412 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6413 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6414 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6415 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6416 +
6417 +static INLINE uint16
6418 +bcmswap16(uint16 val)
6419 +{
6420 + return BCMSWAP16(val);
6421 +}
6422 +
6423 +static INLINE uint32
6424 +bcmswap32(uint32 val)
6425 +{
6426 + return BCMSWAP32(val);
6427 +}
6428 +
6429 +/* buf - start of buffer of shorts to swap */
6430 +/* len - byte length of buffer */
6431 +static INLINE void
6432 +bcmswap16_buf(uint16 *buf, uint len)
6433 +{
6434 + len = len/2;
6435 +
6436 + while(len--){
6437 + *buf = bcmswap16(*buf);
6438 + buf++;
6439 + }
6440 +}
6441 +
6442 +#ifndef hton16
6443 +#ifndef IL_BIGENDIAN
6444 +#define HTON16(i) BCMSWAP16(i)
6445 +#define hton16(i) bcmswap16(i)
6446 +#define hton32(i) bcmswap32(i)
6447 +#define ntoh16(i) bcmswap16(i)
6448 +#define ntoh32(i) bcmswap32(i)
6449 +#define ltoh16(i) (i)
6450 +#define ltoh32(i) (i)
6451 +#define htol16(i) (i)
6452 +#define htol32(i) (i)
6453 +#else
6454 +#define HTON16(i) (i)
6455 +#define hton16(i) (i)
6456 +#define hton32(i) (i)
6457 +#define ntoh16(i) (i)
6458 +#define ntoh32(i) (i)
6459 +#define ltoh16(i) bcmswap16(i)
6460 +#define ltoh32(i) bcmswap32(i)
6461 +#define htol16(i) bcmswap16(i)
6462 +#define htol32(i) bcmswap32(i)
6463 +#endif
6464 +#endif
6465 +
6466 +#ifndef IL_BIGENDIAN
6467 +#define ltoh16_buf(buf, i)
6468 +#define htol16_buf(buf, i)
6469 +#else
6470 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6471 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6472 +#endif
6473 +
6474 +/*
6475 +* load 16-bit value from unaligned little endian byte array.
6476 +*/
6477 +static INLINE uint16
6478 +ltoh16_ua(uint8 *bytes)
6479 +{
6480 + return (bytes[1]<<8)+bytes[0];
6481 +}
6482 +
6483 +/*
6484 +* load 32-bit value from unaligned little endian byte array.
6485 +*/
6486 +static INLINE uint32
6487 +ltoh32_ua(uint8 *bytes)
6488 +{
6489 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6490 +}
6491 +
6492 +/*
6493 +* load 16-bit value from unaligned big(network) endian byte array.
6494 +*/
6495 +static INLINE uint16
6496 +ntoh16_ua(uint8 *bytes)
6497 +{
6498 + return (bytes[0]<<8)+bytes[1];
6499 +}
6500 +
6501 +/*
6502 +* load 32-bit value from unaligned big(network) endian byte array.
6503 +*/
6504 +static INLINE uint32
6505 +ntoh32_ua(uint8 *bytes)
6506 +{
6507 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6508 +}
6509 +
6510 +#endif /* _BCMENDIAN_H_ */
6511 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
6512 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
6513 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-09-16 10:29:18.174591944 +0200
6514 @@ -0,0 +1,229 @@
6515 +/*
6516 + * Hardware-specific definitions for
6517 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
6518 + *
6519 + * Copyright 2001-2003, Broadcom Corporation
6520 + * All Rights Reserved.
6521 + *
6522 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6523 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6524 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6525 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6526 + * $Id$
6527 + */
6528 +
6529 +#ifndef _bcmenet_47xx_h_
6530 +#define _bcmenet_47xx_h_
6531 +
6532 +#include <bcmdevs.h>
6533 +#include <hnddma.h>
6534 +
6535 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
6536 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
6537 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
6538 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
6539 +
6540 +/* power management event wakeup pattern constants */
6541 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
6542 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
6543 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
6544 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
6545 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
6546 +
6547 +/* cpp contortions to concatenate w/arg prescan */
6548 +#ifndef PAD
6549 +#define _PADLINE(line) pad ## line
6550 +#define _XSTR(line) _PADLINE(line)
6551 +#define PAD _XSTR(__LINE__)
6552 +#endif /* PAD */
6553 +
6554 +/* sometimes you just need the enet mib definitions */
6555 +#include <bcmenetmib.h>
6556 +
6557 +/*
6558 + * Host Interface Registers
6559 + */
6560 +typedef volatile struct _bcmenettregs {
6561 + /* Device and Power Control */
6562 + uint32 devcontrol;
6563 + uint32 PAD[2];
6564 + uint32 biststatus;
6565 + uint32 wakeuplength;
6566 + uint32 PAD[3];
6567 +
6568 + /* Interrupt Control */
6569 + uint32 intstatus;
6570 + uint32 intmask;
6571 + uint32 gptimer;
6572 + uint32 PAD[23];
6573 +
6574 + /* Ethernet MAC Address Filtering Control */
6575 + uint32 PAD[2];
6576 + uint32 enetftaddr;
6577 + uint32 enetftdata;
6578 + uint32 PAD[2];
6579 +
6580 + /* Ethernet MAC Control */
6581 + uint32 emactxmaxburstlen;
6582 + uint32 emacrxmaxburstlen;
6583 + uint32 emaccontrol;
6584 + uint32 emacflowcontrol;
6585 +
6586 + uint32 PAD[20];
6587 +
6588 + /* DMA Lazy Interrupt Control */
6589 + uint32 intrecvlazy;
6590 + uint32 PAD[63];
6591 +
6592 + /* DMA engine */
6593 + dmaregs_t dmaregs;
6594 + dmafifo_t dmafifo;
6595 + uint32 PAD[116];
6596 +
6597 + /* EMAC Registers */
6598 + uint32 rxconfig;
6599 + uint32 rxmaxlength;
6600 + uint32 txmaxlength;
6601 + uint32 PAD;
6602 + uint32 mdiocontrol;
6603 + uint32 mdiodata;
6604 + uint32 emacintmask;
6605 + uint32 emacintstatus;
6606 + uint32 camdatalo;
6607 + uint32 camdatahi;
6608 + uint32 camcontrol;
6609 + uint32 enetcontrol;
6610 + uint32 txcontrol;
6611 + uint32 txwatermark;
6612 + uint32 mibcontrol;
6613 + uint32 PAD[49];
6614 +
6615 + /* EMAC MIB counters */
6616 + bcmenetmib_t mib;
6617 +
6618 + uint32 PAD[585];
6619 +
6620 + /* Sonics SiliconBackplane config registers */
6621 + sbconfig_t sbconfig;
6622 +} bcmenetregs_t;
6623 +
6624 +/* device control */
6625 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
6626 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
6627 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
6628 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
6629 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
6630 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
6631 +#define DC_PA_SHIFT 18
6632 +
6633 +/* wakeup length */
6634 +#define WL_P0_MASK 0x7f /* pattern 0 */
6635 +#define WL_D0 ((uint32)1 << 7)
6636 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
6637 +#define WL_P1_SHIFT 8
6638 +#define WL_D1 ((uint32)1 << 15)
6639 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
6640 +#define WL_P2_SHIFT 16
6641 +#define WL_D2 ((uint32)1 << 23)
6642 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
6643 +#define WL_P3_SHIFT 24
6644 +#define WL_D3 ((uint32)1 << 31)
6645 +
6646 +/* intstatus and intmask */
6647 +#define I_PME ((uint32)1 << 6) /* power management event */
6648 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
6649 +#define I_PC ((uint32)1 << 10) /* descriptor error */
6650 +#define I_PD ((uint32)1 << 11) /* data error */
6651 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
6652 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
6653 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
6654 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
6655 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
6656 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
6657 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
6658 +#define I_MW ((uint32)1 << 27) /* mii write */
6659 +#define I_MR ((uint32)1 << 28) /* mii read */
6660 +
6661 +/* emaccontrol */
6662 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
6663 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
6664 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
6665 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
6666 +#define EMC_LC_SHIFT 5
6667 +
6668 +/* emacflowcontrol */
6669 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
6670 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
6671 +
6672 +/* interrupt receive lazy */
6673 +#define IRL_TO_MASK 0x00ffffff /* timeout */
6674 +#define IRL_FC_MASK 0xff000000 /* frame count */
6675 +#define IRL_FC_SHIFT 24 /* frame count */
6676 +
6677 +/* emac receive config */
6678 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
6679 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
6680 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
6681 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
6682 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
6683 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
6684 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
6685 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
6686 +
6687 +/* emac mdio control */
6688 +#define MC_MF_MASK 0x7f /* mdc frequency */
6689 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
6690 +
6691 +/* emac mdio data */
6692 +#define MD_DATA_MASK 0xffff /* r/w data */
6693 +#define MD_TA_MASK 0x30000 /* turnaround value */
6694 +#define MD_TA_SHIFT 16
6695 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
6696 +#define MD_RA_MASK 0x7c0000 /* register address */
6697 +#define MD_RA_SHIFT 18
6698 +#define MD_PMD_MASK 0xf800000 /* physical media device */
6699 +#define MD_PMD_SHIFT 23
6700 +#define MD_OP_MASK 0x30000000 /* opcode */
6701 +#define MD_OP_SHIFT 28
6702 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
6703 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
6704 +#define MD_SB_MASK 0xc0000000 /* start bits */
6705 +#define MD_SB_SHIFT 30
6706 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
6707 +
6708 +/* emac intstatus and intmask */
6709 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
6710 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
6711 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
6712 +
6713 +/* emac cam data high */
6714 +#define CD_V ((uint32)1 << 16) /* valid bit */
6715 +
6716 +/* emac cam control */
6717 +#define CC_CE ((uint32)1 << 0) /* cam enable */
6718 +#define CC_MS ((uint32)1 << 1) /* mask select */
6719 +#define CC_RD ((uint32)1 << 2) /* read */
6720 +#define CC_WR ((uint32)1 << 3) /* write */
6721 +#define CC_INDEX_MASK 0x3f0000 /* index */
6722 +#define CC_INDEX_SHIFT 16
6723 +#define CC_CB ((uint32)1 << 31) /* cam busy */
6724 +
6725 +/* emac ethernet control */
6726 +#define EC_EE ((uint32)1 << 0) /* emac enable */
6727 +#define EC_ED ((uint32)1 << 1) /* emac disable */
6728 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
6729 +#define EC_EP ((uint32)1 << 3) /* external phy select */
6730 +
6731 +/* emac transmit control */
6732 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
6733 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
6734 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
6735 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
6736 +
6737 +/* emac mib control */
6738 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
6739 +
6740 +/* sometimes you just need the enet rxheader definitions */
6741 +#include <bcmenetrxh.h>
6742 +
6743 +#endif /* _bcmenet_47xx_h_ */
6744 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
6745 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
6746 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-09-16 10:29:18.174591944 +0200
6747 @@ -0,0 +1,81 @@
6748 +/*
6749 + * Hardware-specific MIB definition for
6750 + * Broadcom Home Networking Division
6751 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
6752 + *
6753 + * Copyright 2001-2003, Broadcom Corporation
6754 + * All Rights Reserved.
6755 + *
6756 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6757 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6758 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6759 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6760 + * $Id$
6761 + */
6762 +
6763 +#ifndef _bcmenetmib_h_
6764 +#define _bcmenetmib_h_
6765 +
6766 +/* cpp contortions to concatenate w/arg prescan */
6767 +#ifndef PAD
6768 +#define _PADLINE(line) pad ## line
6769 +#define _XSTR(line) _PADLINE(line)
6770 +#define PAD _XSTR(__LINE__)
6771 +#endif /* PAD */
6772 +
6773 +/*
6774 + * EMAC MIB Registers
6775 + */
6776 +typedef volatile struct {
6777 + uint32 tx_good_octets;
6778 + uint32 tx_good_pkts;
6779 + uint32 tx_octets;
6780 + uint32 tx_pkts;
6781 + uint32 tx_broadcast_pkts;
6782 + uint32 tx_multicast_pkts;
6783 + uint32 tx_len_64;
6784 + uint32 tx_len_65_to_127;
6785 + uint32 tx_len_128_to_255;
6786 + uint32 tx_len_256_to_511;
6787 + uint32 tx_len_512_to_1023;
6788 + uint32 tx_len_1024_to_max;
6789 + uint32 tx_jabber_pkts;
6790 + uint32 tx_oversize_pkts;
6791 + uint32 tx_fragment_pkts;
6792 + uint32 tx_underruns;
6793 + uint32 tx_total_cols;
6794 + uint32 tx_single_cols;
6795 + uint32 tx_multiple_cols;
6796 + uint32 tx_excessive_cols;
6797 + uint32 tx_late_cols;
6798 + uint32 tx_defered;
6799 + uint32 tx_carrier_lost;
6800 + uint32 tx_pause_pkts;
6801 + uint32 PAD[8];
6802 +
6803 + uint32 rx_good_octets;
6804 + uint32 rx_good_pkts;
6805 + uint32 rx_octets;
6806 + uint32 rx_pkts;
6807 + uint32 rx_broadcast_pkts;
6808 + uint32 rx_multicast_pkts;
6809 + uint32 rx_len_64;
6810 + uint32 rx_len_65_to_127;
6811 + uint32 rx_len_128_to_255;
6812 + uint32 rx_len_256_to_511;
6813 + uint32 rx_len_512_to_1023;
6814 + uint32 rx_len_1024_to_max;
6815 + uint32 rx_jabber_pkts;
6816 + uint32 rx_oversize_pkts;
6817 + uint32 rx_fragment_pkts;
6818 + uint32 rx_missed_pkts;
6819 + uint32 rx_crc_align_errs;
6820 + uint32 rx_undersize;
6821 + uint32 rx_crc_errs;
6822 + uint32 rx_align_errs;
6823 + uint32 rx_symbol_errs;
6824 + uint32 rx_pause_pkts;
6825 + uint32 rx_nonpause_pkts;
6826 +} bcmenetmib_t;
6827 +
6828 +#endif /* _bcmenetmib_h_ */
6829 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
6830 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
6831 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-09-16 10:29:18.183590576 +0200
6832 @@ -0,0 +1,43 @@
6833 +/*
6834 + * Hardware-specific Receive Data Header for the
6835 + * Broadcom Home Networking Division
6836 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
6837 + *
6838 + * Copyright 2001-2003, Broadcom Corporation
6839 + * All Rights Reserved.
6840 + *
6841 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6842 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6843 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6844 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6845 + * $Id$
6846 + */
6847 +
6848 +#ifndef _bcmenetrxh_h_
6849 +#define _bcmenetrxh_h_
6850 +
6851 +/*
6852 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
6853 + * with every frame consisting of
6854 + * 16bits of frame length, followed by
6855 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
6856 + */
6857 +typedef volatile struct {
6858 + uint16 len;
6859 + uint16 flags;
6860 + uint16 pad[12];
6861 +} bcmenetrxh_t;
6862 +
6863 +#define RXHDR_LEN 28
6864 +
6865 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
6866 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
6867 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
6868 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
6869 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
6870 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
6871 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
6872 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
6873 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
6874 +
6875 +#endif /* _bcmenetrxh_h_ */
6876 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmnvram.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmnvram.h
6877 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6878 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-09-16 10:29:18.184590424 +0200
6879 @@ -0,0 +1,131 @@
6880 +/*
6881 + * NVRAM variable manipulation
6882 + *
6883 + * $Copyright Open Broadcom Corporation$
6884 + *
6885 + * $Id: bcmnvram.h,v 1.1.1.1 2004/01/21 03:50:44 gigis Exp $
6886 + */
6887 +
6888 +#ifndef _bcmnvram_h_
6889 +#define _bcmnvram_h_
6890 +
6891 +#ifndef _LANGUAGE_ASSEMBLY
6892 +
6893 +#include <typedefs.h>
6894 +
6895 +struct nvram_header {
6896 + uint32 magic;
6897 + uint32 len;
6898 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
6899 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
6900 + uint32 config_ncdl; /* ncdl values for memc */
6901 +};
6902 +
6903 +struct nvram_tuple {
6904 + char *name;
6905 + char *value;
6906 + struct nvram_tuple *next;
6907 +};
6908 +
6909 +/*
6910 + * Initialize NVRAM access. May be unnecessary or undefined on certain
6911 + * platforms.
6912 + */
6913 +extern int nvram_init(void *sbh);
6914 +
6915 +/*
6916 + * Disable NVRAM access. May be unnecessary or undefined on certain
6917 + * platforms.
6918 + */
6919 +extern void nvram_exit(void);
6920 +
6921 +/*
6922 + * Get the value of an NVRAM variable. The pointer returned may be
6923 + * invalid after a set.
6924 + * @param name name of variable to get
6925 + * @return value of variable or NULL if undefined
6926 + */
6927 +extern char * nvram_get(const char *name);
6928 +
6929 +/*
6930 + * Get the value of an NVRAM variable.
6931 + * @param name name of variable to get
6932 + * @return value of variable or NUL if undefined
6933 + */
6934 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
6935 +
6936 +/*
6937 + * Match an NVRAM variable.
6938 + * @param name name of variable to match
6939 + * @param match value to compare against value of variable
6940 + * @return TRUE if variable is defined and its value is string equal
6941 + * to match or FALSE otherwise
6942 + */
6943 +static INLINE int
6944 +nvram_match(char *name, char *match) {
6945 + const char *value = nvram_get(name);
6946 + return (value && !strcmp(value, match));
6947 +}
6948 +
6949 +/*
6950 + * Inversely match an NVRAM variable.
6951 + * @param name name of variable to match
6952 + * @param match value to compare against value of variable
6953 + * @return TRUE if variable is defined and its value is not string
6954 + * equal to invmatch or FALSE otherwise
6955 + */
6956 +static INLINE int
6957 +nvram_invmatch(char *name, char *invmatch) {
6958 + const char *value = nvram_get(name);
6959 + return (value && strcmp(value, invmatch));
6960 +}
6961 +
6962 +/*
6963 + * Set the value of an NVRAM variable. The name and value strings are
6964 + * copied into private storage. Pointers to previously set values
6965 + * may become invalid. The new value may be immediately
6966 + * retrieved but will not be permanently stored until a commit.
6967 + * @param name name of variable to set
6968 + * @param value value of variable
6969 + * @return 0 on success and errno on failure
6970 + */
6971 +extern int nvram_set(const char *name, const char *value);
6972 +
6973 +/*
6974 + * Unset an NVRAM variable. Pointers to previously set values
6975 + * remain valid until a set.
6976 + * @param name name of variable to unset
6977 + * @return 0 on success and errno on failure
6978 + * NOTE: use nvram_commit to commit this change to flash.
6979 + */
6980 +extern int nvram_unset(const char *name);
6981 +
6982 +/*
6983 + * Commit NVRAM variables to permanent storage. All pointers to values
6984 + * may be invalid after a commit.
6985 + * NVRAM values are undefined after a commit.
6986 + * @return 0 on success and errno on failure
6987 + */
6988 +extern int nvram_commit(void);
6989 +
6990 +/*
6991 + * Get all NVRAM variables (format name=value\0 ... \0\0).
6992 + * @param buf buffer to store variables
6993 + * @param count size of buffer in bytes
6994 + * @return 0 on success and errno on failure
6995 + */
6996 +extern int nvram_getall(char *buf, int count);
6997 +
6998 +extern int kernel_write(unsigned char *buffer, int offset, int length);
6999 +
7000 +#endif /* _LANGUAGE_ASSEMBLY */
7001 +
7002 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
7003 +#define NVRAM_VERSION 1
7004 +#define NVRAM_HEADER_SIZE 20
7005 +#define NVRAM_LOC_GAP 0x100000
7006 +#define NVRAM_SPACE 0x2000
7007 +#define NVRAM_FIRST_LOC (0xbfd00000 - NVRAM_SPACE)
7008 +#define NVRAM_LAST_LOC (0xc0000000 - NVRAM_SPACE)
7009 +
7010 +#endif /* _bcmnvram_h_ */
7011 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmsrom.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmsrom.h
7012 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
7013 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-09-16 10:29:18.184590424 +0200
7014 @@ -0,0 +1,24 @@
7015 +/*
7016 + * Misc useful routines to access NIC srom
7017 + *
7018 + * Copyright 2001-2003, Broadcom Corporation
7019 + * All Rights Reserved.
7020 + *
7021 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7022 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7023 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7024 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7025 + *
7026 + * $Id$
7027 + */
7028 +
7029 +#ifndef _bcmsrom_h_
7030 +#define _bcmsrom_h_
7031 +
7032 +extern int srom_var_init(uint bus, void *curmap, void *osh, char **vars, int *count);
7033 +
7034 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7035 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
7036 +extern int srom_parsecis(uint8 *cis, char **vars, int *count);
7037 +
7038 +#endif /* _bcmsrom_h_ */
7039 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bcmutils.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmutils.h
7040 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
7041 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-09-16 10:29:18.184590424 +0200
7042 @@ -0,0 +1,136 @@
7043 +/*
7044 + * Misc useful os-independent macros and functions.
7045 + *
7046 + * Copyright 2001-2003, Broadcom Corporation
7047 + * All Rights Reserved.
7048 + *
7049 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7050 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7051 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7052 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7053 + * $Id$
7054 + */
7055 +
7056 +#ifndef _bcmutils_h_
7057 +#define _bcmutils_h_
7058 +
7059 +#ifndef MIN
7060 +#define MIN(a, b) (((a)<(b))?(a):(b))
7061 +#endif
7062 +
7063 +#ifndef MAX
7064 +#define MAX(a, b) (((a)>(b))?(a):(b))
7065 +#endif
7066 +
7067 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
7068 +#define ROUNDUP(x, y) ((((ulong)(x)+((y)-1))/(y))*(y))
7069 +#define ISALIGNED(a, x) (((uint)(a) & ((x)-1)) == 0)
7070 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
7071 +#define OFFSETOF(type, member) ((uint) &((type *)0)->member)
7072 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
7073 +
7074 +/* bit map related macros */
7075 +#ifndef setbit
7076 +#define NBBY 8 /* 8 bits per byte */
7077 +#define setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY))
7078 +#define clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
7079 +#define isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY)))
7080 +#define isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
7081 +#endif
7082 +
7083 +#define NBITS(type) (sizeof (type) * 8)
7084 +
7085 +#define _BCM_U 0x01 /* upper */
7086 +#define _BCM_L 0x02 /* lower */
7087 +#define _BCM_D 0x04 /* digit */
7088 +#define _BCM_C 0x08 /* cntrl */
7089 +#define _BCM_P 0x10 /* punct */
7090 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
7091 +#define _BCM_X 0x40 /* hex digit */
7092 +#define _BCM_SP 0x80 /* hard space (0x20) */
7093 +
7094 +extern unsigned char bcm_ctype[];
7095 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
7096 +
7097 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
7098 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
7099 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
7100 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
7101 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
7102 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
7103 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
7104 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
7105 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
7106 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
7107 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
7108 +
7109 +/*
7110 + * Spin at most 'us' microseconds while 'exp' is true.
7111 + * Caller should explicitly test 'exp' when this completes
7112 + * and take appropriate error action if 'exp' is still true.
7113 + */
7114 +#define SPINWAIT(exp, us) { \
7115 + uint countdown = (us) + 9; \
7116 + while ((exp) && (countdown >= 10)) {\
7117 + OSL_DELAY(10); \
7118 + countdown -= 10; \
7119 + } \
7120 +}
7121 +
7122 +/* generic osl packet queue */
7123 +struct pktq {
7124 + void *head;
7125 + void *tail;
7126 + uint len;
7127 + uint maxlen;
7128 +};
7129 +#define DEFAULT_QLEN 128
7130 +
7131 +#define pktq_len(q) ((q)->len)
7132 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
7133 +#define pktq_head(q) ((q)->head)
7134 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
7135 +
7136 +/* crc defines */
7137 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
7138 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
7139 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
7140 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
7141 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
7142 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
7143 +
7144 +/* tag_ID/length/value_buffer tuple */
7145 +typedef struct bcm_tlv {
7146 + uint8 id;
7147 + uint8 len;
7148 + uint8 data[1];
7149 +} bcm_tlv_t;
7150 +
7151 +/* externs */
7152 +extern uint bcm_atoi(char *s);
7153 +extern uchar bcm_toupper(uchar c);
7154 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
7155 +extern void deadbeef(char *p, uint len);
7156 +extern void prhex(char *msg, uchar *buf, uint len);
7157 +extern void prpkt(char *msg, void *drv, void *p0);
7158 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
7159 +extern uint pkttotlen(void *drv, void *);
7160 +extern uchar *bcm_ether_ntoa(char *ea, char *buf);
7161 +extern int bcm_ether_atoe(char *p, char *ea);
7162 +extern void bcm_mdelay(uint ms);
7163 +extern char *getvar(char *vars, char *name);
7164 +extern int getintvar(char *vars, char *name);
7165 +
7166 +extern uint8 crc8(uint8 *p, uint nbytes, uint8 crc);
7167 +extern uint16 crc16(uint8 *p, uint nbytes, uint16 crc);
7168 +extern uint32 crc32(uint8 *p, uint nbytes, uint32 crc);
7169 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
7170 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
7171 +extern void pktqinit(struct pktq *q, int maxlen);
7172 +extern void pktenq(struct pktq *q, void *p, bool lifo);
7173 +extern void *pktdeq(struct pktq *q);
7174 +
7175 +#define bcmlog(fmt, a1, a2)
7176 +#define bcmdumplog(buf, size) *buf = '\0'
7177 +
7178 +#endif /* _bcmutils_h_ */
7179 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/bitfuncs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bitfuncs.h
7180 --- linux-2.6.12.5/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
7181 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-09-16 10:29:18.185590272 +0200
7182 @@ -0,0 +1,85 @@
7183 +/*
7184 + * bit manipulation utility functions
7185 + *
7186 + * Copyright 2001-2003, Broadcom Corporation
7187 + * All Rights Reserved.
7188 + *
7189 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7190 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7191 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7192 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7193 + * $Id$
7194 + */
7195 +
7196 +#ifndef _BITFUNCS_H
7197 +#define _BITFUNCS_H
7198 +
7199 +#include <typedefs.h>
7200 +
7201 +/* local prototypes */
7202 +static INLINE uint32 find_msbit(uint32 x);
7203 +
7204 +
7205 +/*
7206 + * find_msbit: returns index of most significant set bit in x, with index
7207 + * range defined as 0-31. NOTE: returns zero if input is zero.
7208 + */
7209 +
7210 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
7211 +
7212 +/*
7213 + * Implementation for Pentium processors and gcc. Note that this
7214 + * instruction is actually very slow on some processors (e.g., family 5,
7215 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
7216 + * implementation instead.
7217 + */
7218 +static INLINE uint32 find_msbit(uint32 x)
7219 +{
7220 + uint msbit;
7221 + __asm__("bsrl %1,%0"
7222 + :"=r" (msbit)
7223 + :"r" (x));
7224 + return msbit;
7225 +}
7226 +
7227 +#else
7228 +
7229 +/*
7230 + * Generic Implementation
7231 + */
7232 +
7233 +#define DB_POW_MASK16 0xffff0000
7234 +#define DB_POW_MASK8 0x0000ff00
7235 +#define DB_POW_MASK4 0x000000f0
7236 +#define DB_POW_MASK2 0x0000000c
7237 +#define DB_POW_MASK1 0x00000002
7238 +
7239 +static INLINE uint32 find_msbit(uint32 x)
7240 +{
7241 + uint32 temp_x = x;
7242 + uint msbit = 0;
7243 + if (temp_x & DB_POW_MASK16) {
7244 + temp_x >>= 16;
7245 + msbit = 16;
7246 + }
7247 + if (temp_x & DB_POW_MASK8) {
7248 + temp_x >>= 8;
7249 + msbit += 8;
7250 + }
7251 + if (temp_x & DB_POW_MASK4) {
7252 + temp_x >>= 4;
7253 + msbit += 4;
7254 + }
7255 + if (temp_x & DB_POW_MASK2) {
7256 + temp_x >>= 2;
7257 + msbit += 2;
7258 + }
7259 + if (temp_x & DB_POW_MASK1) {
7260 + msbit += 1;
7261 + }
7262 + return(msbit);
7263 +}
7264 +
7265 +#endif
7266 +
7267 +#endif /* _BITFUNCS_H */
7268 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h
7269 --- linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
7270 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h 2005-09-16 10:29:18.185590272 +0200
7271 @@ -0,0 +1,69 @@
7272 +/*
7273 + * Copyright 2001-2003, Broadcom Corporation
7274 + * All Rights Reserved.
7275 + *
7276 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7277 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7278 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7279 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7280 + *
7281 + * $Id$
7282 + *
7283 +*/
7284 +
7285 +#ifndef _epivers_h_
7286 +#define _epivers_h_
7287 +
7288 +#ifdef linux
7289 +#include <linux/config.h>
7290 +#endif
7291 +
7292 +/* Vendor Name, ASCII, 32 chars max */
7293 +#ifdef COMPANYNAME
7294 +#define HPNA_VENDOR COMPANYNAME
7295 +#else
7296 +#define HPNA_VENDOR "Broadcom Corporation"
7297 +#endif
7298 +
7299 +/* Driver Date, ASCII, 32 chars max */
7300 +#define HPNA_DRV_BUILD_DATE __DATE__
7301 +
7302 +/* Hardware Manufacture Date, ASCII, 32 chars max */
7303 +#define HPNA_HW_MFG_DATE "Not Specified"
7304 +
7305 +/* See documentation for Device Type values, 32 values max */
7306 +#ifndef HPNA_DEV_TYPE
7307 +
7308 +#if defined(CONFIG_BRCM_VJ)
7309 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
7310 +
7311 +#elif defined(CONFIG_BCRM_93725)
7312 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
7313 +
7314 +#else
7315 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
7316 +
7317 +#endif
7318 +
7319 +#endif /* !HPNA_DEV_TYPE */
7320 +
7321 +
7322 +#define EPI_MAJOR_VERSION 1
7323 +
7324 +#define EPI_MINOR_VERSION 1
7325 +
7326 +#define EPI_RC_NUMBER 2
7327 +
7328 +#define EPI_INCREMENTAL_NUMBER 0
7329 +
7330 +#define EPI_BUILD_NUMBER 0
7331 +
7332 +#define EPI_VERSION 1,1,2,0
7333 +
7334 +#define EPI_VERSION_NUM 0x01010200
7335 +
7336 +/* Driver Version String, ASCII, 32 chars max */
7337 +#define EPI_VERSION_STR "1.1.2.0"
7338 +#define EPI_ROUTER_VERSION_STR "1.1.2.0"
7339 +
7340 +#endif /* _epivers_h_ */
7341 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h.in linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h.in
7342 --- linux-2.6.12.5/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
7343 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-09-16 10:29:18.186590120 +0200
7344 @@ -0,0 +1,69 @@
7345 +/*
7346 + * Copyright 2001-2003, Broadcom Corporation
7347 + * All Rights Reserved.
7348 + *
7349 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7350 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7351 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7352 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7353 + *
7354 + * $Id$
7355 + *
7356 +*/
7357 +
7358 +#ifndef _epivers_h_
7359 +#define _epivers_h_
7360 +
7361 +#ifdef linux
7362 +#include <linux/config.h>
7363 +#endif
7364 +
7365 +/* Vendor Name, ASCII, 32 chars max */
7366 +#ifdef COMPANYNAME
7367 +#define HPNA_VENDOR COMPANYNAME
7368 +#else
7369 +#define HPNA_VENDOR "Broadcom Corporation"
7370 +#endif
7371 +
7372 +/* Driver Date, ASCII, 32 chars max */
7373 +#define HPNA_DRV_BUILD_DATE __DATE__
7374 +
7375 +/* Hardware Manufacture Date, ASCII, 32 chars max */
7376 +#define HPNA_HW_MFG_DATE "Not Specified"
7377 +
7378 +/* See documentation for Device Type values, 32 values max */
7379 +#ifndef HPNA_DEV_TYPE
7380 +
7381 +#if defined(CONFIG_BRCM_VJ)
7382 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
7383 +
7384 +#elif defined(CONFIG_BCRM_93725)
7385 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
7386 +
7387 +#else
7388 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
7389 +
7390 +#endif
7391 +
7392 +#endif /* !HPNA_DEV_TYPE */
7393 +
7394 +
7395 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
7396 +
7397 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
7398 +
7399 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
7400 +
7401 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
7402 +
7403 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
7404 +
7405 +#define EPI_VERSION @EPI_VERSION@
7406 +
7407 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
7408 +
7409 +/* Driver Version String, ASCII, 32 chars max */
7410 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
7411 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
7412 +
7413 +#endif /* _epivers_h_ */
7414 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/etsockio.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/etsockio.h
7415 --- linux-2.6.12.5/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
7416 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-09-16 10:29:18.186590120 +0200
7417 @@ -0,0 +1,60 @@
7418 +/*
7419 + * Driver-specific socket ioctls
7420 + * used by BSD, Linux, and PSOS
7421 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
7422 + *
7423 + * Copyright 2001-2003, Broadcom Corporation
7424 + * All Rights Reserved.
7425 + *
7426 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7427 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7428 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7429 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7430 + *
7431 + * $Id$
7432 + */
7433 +
7434 +#ifndef _etsockio_h_
7435 +#define _etsockio_h_
7436 +
7437 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
7438 +
7439 +
7440 +#if defined(linux)
7441 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
7442 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
7443 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
7444 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
7445 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
7446 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
7447 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
7448 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
7449 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
7450 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
7451 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
7452 +#define SIOCPERF (SIOCDEVPRIVATE + 11)
7453 +#define SIOCPERFDMA (SIOCDEVPRIVATE + 12)
7454 +
7455 +#else /* !linux */
7456 +
7457 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
7458 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
7459 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
7460 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
7461 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
7462 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
7463 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
7464 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
7465 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
7466 +
7467 +#endif
7468 +
7469 +/* arg to SIOCTXGEN */
7470 +struct txg {
7471 + uint32 num; /* number of frames to send */
7472 + uint32 delay; /* delay in microseconds between sending each */
7473 + uint32 size; /* size of ether frame to send */
7474 + uchar buf[1514]; /* starting ether frame data */
7475 +};
7476 +
7477 +#endif
7478 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/flash.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flash.h
7479 --- linux-2.6.12.5/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
7480 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flash.h 2005-09-16 10:29:18.187589968 +0200
7481 @@ -0,0 +1,184 @@
7482 +/*
7483 + * flash.h: Common definitions for flash access.
7484 + *
7485 + * Copyright 2001-2003, Broadcom Corporation
7486 + * All Rights Reserved.
7487 + *
7488 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7489 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7490 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7491 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7492 + *
7493 + * $Id$
7494 + */
7495 +
7496 +/* Types of flashes we know about */
7497 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST} flash_type_t;
7498 +
7499 +/* Commands to write/erase the flases */
7500 +typedef struct _flash_cmds{
7501 + flash_type_t type;
7502 + bool need_unlock;
7503 + uint16 pre_erase;
7504 + uint16 erase_block;
7505 + uint16 erase_chip;
7506 + uint16 write_word;
7507 + uint16 write_buf;
7508 + uint16 clear_csr;
7509 + uint16 read_csr;
7510 + uint16 read_id;
7511 + uint16 confirm;
7512 + uint16 read_array;
7513 +} flash_cmds_t;
7514 +
7515 +#define UNLOCK_CMD_WORDS 2
7516 +
7517 +typedef struct _unlock_cmd {
7518 + uint addr[UNLOCK_CMD_WORDS];
7519 + uint16 cmd[UNLOCK_CMD_WORDS];
7520 +} unlock_cmd_t;
7521 +
7522 +/* Flash descriptors */
7523 +typedef struct _flash_desc {
7524 + uint16 mfgid; /* Manufacturer Id */
7525 + uint16 devid; /* Device Id */
7526 + uint size; /* Total size in bytes */
7527 + uint width; /* Device width in bytes */
7528 + flash_type_t type; /* Device type old, S, J */
7529 + uint bsize; /* Block size */
7530 + uint nb; /* Number of blocks */
7531 + uint ff; /* First full block */
7532 + uint lf; /* Last full block */
7533 + uint nsub; /* Number of subblocks */
7534 + uint *subblocks; /* Offsets for subblocks */
7535 + char *desc; /* Description */
7536 +} flash_desc_t;
7537 +
7538 +
7539 +#ifdef DECLARE_FLASHES
7540 +
7541 +flash_cmds_t flash_cmds[] = {
7542 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
7543 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
7544 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
7545 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
7546 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
7547 + { 0 }
7548 +};
7549 +
7550 +unlock_cmd_t unlock_cmd_amd = {
7551 +#ifdef MIPSEB
7552 +/* addr: */ { 0x0aa8, 0x0556},
7553 +#else
7554 +/* addr: */ { 0x0aaa, 0x0554},
7555 +#endif
7556 +/* data: */ { 0xaa, 0x55}
7557 +};
7558 +
7559 +unlock_cmd_t unlock_cmd_sst = {
7560 +#ifdef MIPSEB
7561 +/* addr: */ { 0xaaa8, 0x5556},
7562 +#else
7563 +/* addr: */ { 0xaaaa, 0x5554},
7564 +#endif
7565 +/* data: */ { 0xaa, 0x55}
7566 +};
7567 +
7568 +#define AMD_CMD 0xaaa
7569 +#define SST_CMD 0xaaaa
7570 +
7571 +/* intel unlock block cmds */
7572 +#define INTEL_UNLOCK1 0x60
7573 +#define INTEL_UNLOCK2 0xD0
7574 +
7575 +/* Just eight blocks of 8KB byte each */
7576 +
7577 +uint blk8x8k[] = { 0x00000000,
7578 + 0x00002000,
7579 + 0x00004000,
7580 + 0x00006000,
7581 + 0x00008000,
7582 + 0x0000a000,
7583 + 0x0000c000,
7584 + 0x0000e000,
7585 + 0x00010000
7586 +};
7587 +
7588 +/* Funky AMD arrangement for 29xx800's */
7589 +uint amd800[] = { 0x00000000, /* 16KB */
7590 + 0x00004000, /* 32KB */
7591 + 0x0000c000, /* 8KB */
7592 + 0x0000e000, /* 8KB */
7593 + 0x00010000, /* 8KB */
7594 + 0x00012000, /* 8KB */
7595 + 0x00014000, /* 32KB */
7596 + 0x0001c000, /* 16KB */
7597 + 0x00020000
7598 +};
7599 +
7600 +/* AMD arrangement for 29xx160's */
7601 +uint amd4112[] = { 0x00000000, /* 32KB */
7602 + 0x00008000, /* 8KB */
7603 + 0x0000a000, /* 8KB */
7604 + 0x0000c000, /* 16KB */
7605 + 0x00010000
7606 +};
7607 +uint amd2114[] = { 0x00000000, /* 16KB */
7608 + 0x00004000, /* 8KB */
7609 + 0x00006000, /* 8KB */
7610 + 0x00008000, /* 32KB */
7611 + 0x00010000
7612 +};
7613 +
7614 +
7615 +
7616 +flash_desc_t flashes[] = {
7617 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7618 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7619 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7620 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7621 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7622 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7623 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7624 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7625 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7626 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7627 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7628 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7629 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7630 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7631 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7632 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7633 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7634 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7635 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7636 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7637 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7638 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7639 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7640 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7641 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7642 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7643 + { 0x0001, 0x2201, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7644 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7645 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7646 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7647 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7648 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7649 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7650 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7651 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7652 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7653 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7654 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7655 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7656 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7657 +};
7658 +
7659 +#else
7660 +
7661 +extern flash_cmds_t flash_cmds[];
7662 +extern unlock_cmd_t unlock_cmd;
7663 +extern flash_desc_t flashes[];
7664 +
7665 +#endif
7666 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/flashutl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flashutl.h
7667 --- linux-2.6.12.5/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7668 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-09-16 10:29:18.187589968 +0200
7669 @@ -0,0 +1,34 @@
7670 +/*
7671 + * BCM47XX FLASH driver interface
7672 + *
7673 + * Copyright 2001-2003, Broadcom Corporation
7674 + * All Rights Reserved.
7675 + *
7676 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7677 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7678 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7679 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7680 + * $Id$
7681 + */
7682 +
7683 +#ifndef _flashutl_h_
7684 +#define _flashutl_h_
7685 +
7686 +#define FLASH_BASE 0xbfc00000 /* BCM4710 */
7687 +
7688 +int flash_init(void* base_addr, char *flash_str);
7689 +int flash_erase(void);
7690 +int flash_eraseblk(unsigned long off);
7691 +int flash_write(unsigned long off, uint16 *src, uint nbytes);
7692 +unsigned long flash_block_base(unsigned long off);
7693 +unsigned long flash_block_lim(unsigned long off);
7694 +int FlashWriteRange(unsigned short* dst, unsigned short* src, unsigned int numbytes);
7695 +
7696 +void nvWrite(unsigned short *data, unsigned int len);
7697 +
7698 +/* Global vars */
7699 +extern char* flashutl_base;
7700 +extern flash_desc_t* flashutl_desc;
7701 +extern flash_cmds_t* flashutl_cmd;
7702 +
7703 +#endif /* _flashutl_h_ */
7704 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/hnddma.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hnddma.h
7705 --- linux-2.6.12.5/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
7706 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-09-16 10:29:18.188589816 +0200
7707 @@ -0,0 +1,181 @@
7708 +/*
7709 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
7710 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7711 + *
7712 + * $Id$
7713 + * Copyright 2001-2003, Broadcom Corporation
7714 + * All Rights Reserved.
7715 + *
7716 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7717 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7718 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7719 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7720 + */
7721 +
7722 +#ifndef _hnddma_h_
7723 +#define _hnddma_h_
7724 +
7725 +/*
7726 + * Each DMA processor consists of a transmit channel and a receive channel.
7727 + */
7728 +typedef volatile struct {
7729 + /* transmit channel */
7730 + uint32 xmtcontrol; /* enable, et al */
7731 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
7732 + uint32 xmtptr; /* last descriptor posted to chip */
7733 + uint32 xmtstatus; /* current active descriptor, et al */
7734 +
7735 + /* receive channel */
7736 + uint32 rcvcontrol; /* enable, et al */
7737 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
7738 + uint32 rcvptr; /* last descriptor posted to chip */
7739 + uint32 rcvstatus; /* current active descriptor, et al */
7740 +} dmaregs_t;
7741 +
7742 +typedef volatile struct {
7743 + /* diag access */
7744 + uint32 fifoaddr; /* diag address */
7745 + uint32 fifodatalow; /* low 32bits of data */
7746 + uint32 fifodatahigh; /* high 32bits of data */
7747 + uint32 pad; /* reserved */
7748 +} dmafifo_t;
7749 +
7750 +/* transmit channel control */
7751 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7752 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7753 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7754 +#define XC_FL ((uint32)1 << 4) /* flush request */
7755 +
7756 +/* transmit descriptor table pointer */
7757 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7758 +
7759 +/* transmit channel status */
7760 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7761 +#define XS_XS_MASK 0xf000 /* transmit state */
7762 +#define XS_XS_SHIFT 12
7763 +#define XS_XS_DISABLED 0x0000 /* disabled */
7764 +#define XS_XS_ACTIVE 0x1000 /* active */
7765 +#define XS_XS_IDLE 0x2000 /* idle wait */
7766 +#define XS_XS_STOPPED 0x3000 /* stopped */
7767 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7768 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7769 +#define XS_XE_SHIFT 16
7770 +#define XS_XE_NOERR 0x00000 /* no error */
7771 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7772 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7773 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7774 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7775 +#define XS_FL ((uint32)1 << 20) /* flushed */
7776 +
7777 +/* receive channel control */
7778 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7779 +#define RC_RO_MASK 0xfe /* receive frame offset */
7780 +#define RC_RO_SHIFT 1
7781 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7782 +
7783 +/* receive descriptor table pointer */
7784 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7785 +
7786 +/* receive channel status */
7787 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7788 +#define RS_RS_MASK 0xf000 /* receive state */
7789 +#define RS_RS_SHIFT 12
7790 +#define RS_RS_DISABLED 0x0000 /* disabled */
7791 +#define RS_RS_ACTIVE 0x1000 /* active */
7792 +#define RS_RS_IDLE 0x2000 /* idle wait */
7793 +#define RS_RS_STOPPED 0x3000 /* reserved */
7794 +#define RS_RE_MASK 0xf0000 /* receive errors */
7795 +#define RS_RE_SHIFT 16
7796 +#define RS_RE_NOERR 0x00000 /* no error */
7797 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7798 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7799 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7800 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7801 +
7802 +/* fifoaddr */
7803 +#define FA_OFF_MASK 0xffff /* offset */
7804 +#define FA_SEL_MASK 0xf0000 /* select */
7805 +#define FA_SEL_SHIFT 16
7806 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7807 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7808 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7809 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7810 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7811 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7812 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7813 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7814 +
7815 +/*
7816 + * DMA Descriptor
7817 + * Descriptors are only read by the hardware, never written back.
7818 + */
7819 +typedef volatile struct {
7820 + uint32 ctrl; /* misc control bits & bufcount */
7821 + uint32 addr; /* data buffer address */
7822 +} dmadd_t;
7823 +
7824 +/*
7825 + * Each descriptor ring must be 4096byte aligned
7826 + * and fit within a single 4096byte page.
7827 + */
7828 +#define DMAMAXRINGSZ 4096
7829 +#define DMARINGALIGN 4096
7830 +
7831 +/* control flags */
7832 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7833 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7834 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7835 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7836 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7837 +
7838 +/* control flags in the range [27:20] are core-specific and not defined here */
7839 +#define CTRL_CORE_MASK 0x0ff00000
7840 +
7841 +/* export structure */
7842 +typedef volatile struct {
7843 + /* rx error counters */
7844 + uint rxgiants; /* rx giant frames */
7845 + uint rxnobuf; /* rx out of dma descriptors */
7846 + /* tx error counters */
7847 + uint txnobuf; /* tx out of dma descriptors */
7848 +} hnddma_t;
7849 +
7850 +#ifndef di_t
7851 +#define di_t void
7852 +#endif
7853 +
7854 +/* externs */
7855 +extern void *dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
7856 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
7857 + uint ddoffset, uint dataoffset, uint *msg_level);
7858 +extern void dma_detach(di_t *di);
7859 +extern void dma_txreset(di_t *di);
7860 +extern void dma_rxreset(di_t *di);
7861 +extern void dma_txinit(di_t *di);
7862 +extern bool dma_txenabled(di_t *di);
7863 +extern void dma_rxinit(di_t *di);
7864 +extern void dma_rxenable(di_t *di);
7865 +extern bool dma_rxenabled(di_t *di);
7866 +extern void dma_txsuspend(di_t *di);
7867 +extern void dma_txresume(di_t *di);
7868 +extern bool dma_txsuspended(di_t *di);
7869 +extern bool dma_txstopped(di_t *di);
7870 +extern bool dma_rxstopped(di_t *di);
7871 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
7872 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
7873 +extern void dma_fifoloopbackenable(di_t *di);
7874 +extern void *dma_rx(di_t *di);
7875 +extern void dma_rxfill(di_t *di);
7876 +extern void dma_txreclaim(di_t *di, bool forceall);
7877 +extern void dma_rxreclaim(di_t *di);
7878 +extern char *dma_dump(di_t *di, char *buf);
7879 +extern char *dma_dumptx(di_t *di, char *buf);
7880 +extern char *dma_dumprx(di_t *di, char *buf);
7881 +extern uint dma_getvar(di_t *di, char *name);
7882 +extern void *dma_getnexttxp(di_t *di, bool forceall);
7883 +extern void *dma_getnextrxp(di_t *di, bool forceall);
7884 +extern void dma_txblock(di_t *di);
7885 +extern void dma_txunblock(di_t *di);
7886 +extern uint dma_txactive(di_t *di);
7887 +
7888 +#endif /* _hnddma_h_ */
7889 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/hndmips.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hndmips.h
7890 --- linux-2.6.12.5/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7891 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-09-16 10:29:18.188589816 +0200
7892 @@ -0,0 +1,16 @@
7893 +/*
7894 + * Alternate include file for HND sbmips.h since CFE also ships with
7895 + * a sbmips.h.
7896 + *
7897 + * Copyright 2001-2003, Broadcom Corporation
7898 + * All Rights Reserved.
7899 + *
7900 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7901 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7902 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7903 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7904 + *
7905 + * $Id$
7906 + */
7907 +
7908 +#include "sbmips.h"
7909 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/linux_osl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linux_osl.h
7910 --- linux-2.6.12.5/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7911 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-09-16 10:29:18.190589512 +0200
7912 @@ -0,0 +1,313 @@
7913 +/*
7914 + * Linux OS Independent Layer
7915 + *
7916 + * Copyright 2001-2003, Broadcom Corporation
7917 + * All Rights Reserved.
7918 + *
7919 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7920 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7921 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7922 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7923 + *
7924 + * $Id$
7925 + */
7926 +
7927 +#ifndef _linux_osl_h_
7928 +#define _linux_osl_h_
7929 +
7930 +#include <typedefs.h>
7931 +
7932 +/* use current 2.4.x calling conventions */
7933 +#include <linuxver.h>
7934 +
7935 +/* assert and panic */
7936 +#define ASSERT(exp) do {} while (0)
7937 +
7938 +/* PCMCIA attribute space access macros */
7939 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
7940 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
7941 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
7942 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
7943 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
7944 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
7945 +
7946 +/* PCI configuration space access macros */
7947 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
7948 + osl_pci_read_config((loc), (offset), (size))
7949 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
7950 + osl_pci_write_config((loc), (offset), (size), (val))
7951 +extern uint32 osl_pci_read_config(void *loc, uint size, uint offset);
7952 +extern void osl_pci_write_config(void *loc, uint offset, uint size, uint val);
7953 +
7954 +/* OSL initialization */
7955 +#define osl_init() do {} while (0)
7956 +
7957 +/* host/bus architecture-specific byte swap */
7958 +#define BUS_SWAP32(v) (v)
7959 +
7960 +/*
7961 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7962 + * Macros expand to calls to functions defined in linux_osl.c .
7963 + */
7964 +#ifndef BINOSL
7965 +
7966 +/* string library, kernel mode */
7967 +#define printf(fmt, args...) printk(fmt, ## args)
7968 +#include <linux/kernel.h>
7969 +#include <linux/string.h>
7970 +
7971 +/* register access macros */
7972 +#define R_REG(r) ({ \
7973 + __typeof(*(r)) __osl_v; \
7974 + switch (sizeof(*(r))) { \
7975 + case sizeof(uint8): __osl_v = readb((volatile uint8*)(r)); break; \
7976 + case sizeof(uint16): __osl_v = readw((volatile uint16*)(r)); break; \
7977 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7978 + } \
7979 + __osl_v; \
7980 +})
7981 +#define W_REG(r, v) do { \
7982 + switch (sizeof(*(r))) { \
7983 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7984 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7985 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7986 + } \
7987 +} while (0)
7988 +
7989 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7990 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7991 +
7992 +/* bcopy, bcmp, and bzero */
7993 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7994 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7995 +#define bzero(b, len) memset((b), '\0', (len))
7996 +
7997 +/* general purpose memory allocation */
7998 +#define MALLOC(size) kmalloc((size), GFP_ATOMIC)
7999 +#define MFREE(addr, size) kfree((addr))
8000 +
8001 +/* uncached virtual address */
8002 +#ifdef mips
8003 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
8004 +#include <asm/addrspace.h>
8005 +#else
8006 +#define OSL_UNCACHED(va) (va)
8007 +#endif
8008 +
8009 +/* get processor cycle count */
8010 +#if defined(mips)
8011 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
8012 +#elif defined(__i386__)
8013 +#define OSL_GETCYCLES(x) rdtscl((x))
8014 +#else
8015 +#define OSL_GETCYCLES(x) ((x) = 0)
8016 +#endif
8017 +
8018 +/* dereference an address that may cause a bus exception */
8019 +#ifdef mips
8020 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
8021 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
8022 +#else
8023 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
8024 +#include <asm/paccess.h>
8025 +#endif
8026 +#else
8027 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
8028 +#endif
8029 +
8030 +/* map/unmap physical to virtual I/O */
8031 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
8032 +#define REG_UNMAP(va) iounmap((void *)(va))
8033 +
8034 +/* allocate/free shared (dma-able) consistent (uncached) memory */
8035 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
8036 + pci_alloc_consistent((dev), (size), (dma_addr_t*)(pap))
8037 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
8038 + pci_free_consistent((dev), (size), (va), (dma_addr_t)(pa))
8039 +
8040 +/* map/unmap direction */
8041 +#define DMA_TX PCI_DMA_TODEVICE
8042 +#define DMA_RX PCI_DMA_FROMDEVICE
8043 +
8044 +/* map/unmap shared (dma-able) memory */
8045 +#define DMA_MAP(dev, va, size, direction, p) \
8046 + pci_map_single((dev), (va), (size), (direction))
8047 +#define DMA_UNMAP(dev, pa, size, direction, p) \
8048 + pci_unmap_single((dev), (dma_addr_t)(pa), (size), (direction))
8049 +
8050 +/* microsecond delay */
8051 +#define OSL_DELAY(usec) udelay(usec)
8052 +#include <linux/delay.h>
8053 +#define OSL_SLEEP(usec) set_current_state(TASK_INTERRUPTIBLE); \
8054 + schedule_timeout((usec*HZ)/1000000);
8055 +#define OSL_IN_INTERRUPT() in_interrupt()
8056 +
8057 +/* shared (dma-able) memory access macros */
8058 +#define R_SM(r) *(r)
8059 +#define W_SM(r, v) (*(r) = (v))
8060 +#define BZERO_SM(r, len) memset((r), '\0', (len))
8061 +
8062 +/* packet primitives */
8063 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
8064 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
8065 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
8066 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
8067 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
8068 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
8069 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
8070 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
8071 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
8072 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
8073 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
8074 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
8075 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
8076 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
8077 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
8078 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
8079 +extern void *osl_pktget(void *drv, uint len, bool send);
8080 +extern void osl_pktfree(void *skb);
8081 +
8082 +#else /* BINOSL */
8083 +
8084 +/* string library */
8085 +#ifndef LINUX_OSL
8086 +#undef printf
8087 +#define printf(fmt, args...) osl_printf((fmt), ## args)
8088 +#undef sprintf
8089 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
8090 +#undef strcmp
8091 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
8092 +#undef strncmp
8093 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
8094 +#undef strlen
8095 +#define strlen(s) osl_strlen((s))
8096 +#undef strcpy
8097 +#define strcpy(d, s) osl_strcpy((d), (s))
8098 +#undef strncpy
8099 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
8100 +#endif
8101 +extern int osl_printf(const char *format, ...);
8102 +extern int osl_sprintf(char *buf, const char *format, ...);
8103 +extern int osl_strcmp(const char *s1, const char *s2);
8104 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
8105 +extern int osl_strlen(char *s);
8106 +extern char* osl_strcpy(char *d, const char *s);
8107 +extern char* osl_strncpy(char *d, const char *s, uint n);
8108 +
8109 +/* register access macros */
8110 +#define R_REG(r) ({ \
8111 + __typeof(*(r)) __osl_v; \
8112 + switch (sizeof(*(r))) { \
8113 + case sizeof(uint8): __osl_v = osl_readb((volatile uint8*)(r)); break; \
8114 + case sizeof(uint16): __osl_v = osl_readw((volatile uint16*)(r)); break; \
8115 + case sizeof(uint32): __osl_v = osl_readl((volatile uint32*)(r)); break; \
8116 + } \
8117 + __osl_v; \
8118 +})
8119 +#define W_REG(r, v) do { \
8120 + switch (sizeof(*(r))) { \
8121 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
8122 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
8123 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
8124 + } \
8125 +} while (0)
8126 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
8127 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
8128 +extern uint8 osl_readb(volatile uint8 *r);
8129 +extern uint16 osl_readw(volatile uint16 *r);
8130 +extern uint32 osl_readl(volatile uint32 *r);
8131 +extern void osl_writeb(uint8 v, volatile uint8 *r);
8132 +extern void osl_writew(uint16 v, volatile uint16 *r);
8133 +extern void osl_writel(uint32 v, volatile uint32 *r);
8134 +
8135 +/* bcopy, bcmp, and bzero */
8136 +extern void bcopy(const void *src, void *dst, int len);
8137 +extern int bcmp(const void *b1, const void *b2, int len);
8138 +extern void bzero(void *b, int len);
8139 +
8140 +/* general purpose memory allocation */
8141 +#define MALLOC(size) osl_malloc((size))
8142 +#define MFREE(addr, size) osl_mfree((char*)(addr), (size))
8143 +extern void *osl_malloc(uint size);
8144 +extern void osl_mfree(void *addr, uint size);
8145 +
8146 +/* uncached virtual address */
8147 +#define OSL_UNCACHED(va) osl_uncached((va))
8148 +extern void *osl_uncached(void *va);
8149 +
8150 +/* get processor cycle count */
8151 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
8152 +extern uint osl_getcycles(void);
8153 +
8154 +/* dereference an address that may target abort */
8155 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
8156 +extern int osl_busprobe(uint32 *val, uint32 addr);
8157 +
8158 +/* map/unmap physical to virtual */
8159 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
8160 +#define REG_UNMAP(va) osl_reg_unmap((va))
8161 +extern void *osl_reg_map(uint32 pa, uint size);
8162 +extern void osl_reg_unmap(void *va);
8163 +
8164 +/* allocate/free shared (dma-able) consistent (uncached) memory */
8165 +#define DMA_ALLOC_CONSISTENT(dev, size, pap) \
8166 + osl_dma_alloc_consistent((dev), (size), (pap))
8167 +#define DMA_FREE_CONSISTENT(dev, va, size, pa) \
8168 + osl_dma_free_consistent((dev), (void*)(va), (size), (pa))
8169 +extern void *osl_dma_alloc_consistent(void *dev, uint size, ulong *pap);
8170 +extern void osl_dma_free_consistent(void *dev, void *va, uint size, ulong pa);
8171 +
8172 +/* map/unmap direction */
8173 +#define DMA_TX 1
8174 +#define DMA_RX 2
8175 +
8176 +/* map/unmap shared (dma-able) memory */
8177 +#define DMA_MAP(dev, va, size, direction, p) \
8178 + osl_dma_map((dev), (va), (size), (direction))
8179 +#define DMA_UNMAP(dev, pa, size, direction, p) \
8180 + osl_dma_unmap((dev), (pa), (size), (direction))
8181 +extern uint osl_dma_map(void *dev, void *va, uint size, int direction);
8182 +extern void osl_dma_unmap(void *dev, uint pa, uint size, int direction);
8183 +
8184 +/* microsecond delay */
8185 +#define OSL_DELAY(usec) osl_delay((usec))
8186 +extern void osl_delay(uint usec);
8187 +
8188 +/* shared (dma-able) memory access macros */
8189 +#define R_SM(r) *(r)
8190 +#define W_SM(r, v) (*(r) = (v))
8191 +#define BZERO_SM(r, len) bzero((r), (len))
8192 +
8193 +/* packet primitives */
8194 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
8195 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
8196 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
8197 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
8198 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
8199 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
8200 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
8201 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
8202 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
8203 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
8204 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
8205 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
8206 +#define PKTLINK(skb) osl_pktlink((skb))
8207 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
8208 +extern void *osl_pktget(void *drv, uint len, bool send);
8209 +extern void osl_pktfree(void *skb);
8210 +extern uchar *osl_pktdata(void *drv, void *skb);
8211 +extern uint osl_pktlen(void *drv, void *skb);
8212 +extern void *osl_pktnext(void *drv, void *skb);
8213 +extern void osl_pktsetnext(void *skb, void *x);
8214 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
8215 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
8216 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
8217 +extern void *osl_pktdup(void *drv, void *skb);
8218 +extern void *osl_pktcookie(void *skb);
8219 +extern void osl_pktsetcookie(void *skb, void *x);
8220 +extern void *osl_pktlink(void *skb);
8221 +extern void osl_pktsetlink(void *skb, void *x);
8222 +
8223 +#endif /* BINOSL */
8224 +
8225 +#endif /* _linux_osl_h_ */
8226 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/linuxver.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linuxver.h
8227 --- linux-2.6.12.5/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
8228 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-09-16 10:29:18.191589360 +0200
8229 @@ -0,0 +1,326 @@
8230 +/*
8231 + * Linux-specific abstractions to gain some independence from linux kernel versions.
8232 + * Pave over some 2.2 versus 2.4 kernel differences.
8233 + *
8234 + * Copyright 2001-2003, Broadcom Corporation
8235 + * All Rights Reserved.
8236 + *
8237 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8238 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8239 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8240 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8241 + * $Id$
8242 + */
8243 +
8244 +#ifndef _linuxver_h_
8245 +#define _linuxver_h_
8246 +
8247 +#include <linux/config.h>
8248 +#include <linux/version.h>
8249 +
8250 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
8251 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
8252 +#ifdef __UNDEF_NO_VERSION__
8253 +#undef __NO_VERSION__
8254 +#else
8255 +#define __NO_VERSION__
8256 +#endif
8257 +#endif
8258 +
8259 +#if defined(MODULE) && defined(MODVERSIONS)
8260 +#include <linux/modversions.h>
8261 +#endif
8262 +
8263 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
8264 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
8265 +#include <linux/malloc.h>
8266 +#else
8267 +#include <linux/slab.h>
8268 +#endif
8269 +
8270 +#include <linux/types.h>
8271 +#include <linux/init.h>
8272 +#include <linux/module.h>
8273 +#include <linux/mm.h>
8274 +#include <linux/string.h>
8275 +#include <linux/pci.h>
8276 +#include <linux/interrupt.h>
8277 +#include <linux/netdevice.h>
8278 +#include <asm/io.h>
8279 +
8280 +#ifndef __exit
8281 +#define __exit
8282 +#endif
8283 +#ifndef __devexit
8284 +#define __devexit
8285 +#endif
8286 +#ifndef __devinit
8287 +#define __devinit __init
8288 +#endif
8289 +#ifndef __devinitdata
8290 +#define __devinitdata
8291 +#endif
8292 +#ifndef __devexit_p
8293 +#define __devexit_p(x) x
8294 +#endif
8295 +
8296 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
8297 +
8298 +#define pci_get_drvdata(dev) (dev)->sysdata
8299 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
8300 +
8301 +/*
8302 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
8303 + */
8304 +
8305 +struct pci_device_id {
8306 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
8307 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
8308 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
8309 + unsigned long driver_data; /* Data private to the driver */
8310 +};
8311 +
8312 +struct pci_driver {
8313 + struct list_head node;
8314 + char *name;
8315 + const struct pci_device_id *id_table; /* NULL if wants all devices */
8316 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
8317 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
8318 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
8319 + void (*resume)(struct pci_dev *dev); /* Device woken up */
8320 +};
8321 +
8322 +#define MODULE_DEVICE_TABLE(type, name)
8323 +#define PCI_ANY_ID (~0)
8324 +
8325 +/* compatpci.c */
8326 +#define pci_module_init pci_register_driver
8327 +extern int pci_register_driver(struct pci_driver *drv);
8328 +extern void pci_unregister_driver(struct pci_driver *drv);
8329 +
8330 +#endif /* PCI registration */
8331 +
8332 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
8333 +#ifdef MODULE
8334 +#define module_init(x) int init_module(void) { return x(); }
8335 +#define module_exit(x) void cleanup_module(void) { x(); }
8336 +#else
8337 +#define module_init(x) __initcall(x);
8338 +#define module_exit(x) __exitcall(x);
8339 +#endif
8340 +#endif
8341 +
8342 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
8343 +#define list_for_each(pos, head) \
8344 + for (pos = (head)->next; pos != (head); pos = pos->next)
8345 +#endif
8346 +
8347 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
8348 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
8349 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
8350 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
8351 +#endif
8352 +
8353 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
8354 +#define pci_enable_device(dev) do { } while (0)
8355 +#endif
8356 +
8357 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
8358 +#define net_device device
8359 +#endif
8360 +
8361 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
8362 +
8363 +/*
8364 + * DMA mapping
8365 + *
8366 + * See linux/Documentation/DMA-mapping.txt
8367 + */
8368 +
8369 +#ifndef PCI_DMA_TODEVICE
8370 +#define PCI_DMA_TODEVICE 1
8371 +#define PCI_DMA_FROMDEVICE 2
8372 +#endif
8373 +
8374 +typedef u32 dma_addr_t;
8375 +
8376 +/* Pure 2^n version of get_order */
8377 +static inline int get_order(unsigned long size)
8378 +{
8379 + int order;
8380 +
8381 + size = (size-1) >> (PAGE_SHIFT-1);
8382 + order = -1;
8383 + do {
8384 + size >>= 1;
8385 + order++;
8386 + } while (size);
8387 + return order;
8388 +}
8389 +
8390 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
8391 + dma_addr_t *dma_handle)
8392 +{
8393 + void *ret;
8394 + int gfp = GFP_ATOMIC | GFP_DMA;
8395 +
8396 + ret = (void *)__get_free_pages(gfp, get_order(size));
8397 +
8398 + if (ret != NULL) {
8399 + memset(ret, 0, size);
8400 + *dma_handle = virt_to_bus(ret);
8401 + }
8402 + return ret;
8403 +}
8404 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
8405 + void *vaddr, dma_addr_t dma_handle)
8406 +{
8407 + free_pages((unsigned long)vaddr, get_order(size));
8408 +}
8409 +#ifdef ILSIM
8410 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
8411 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
8412 +#else
8413 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
8414 +#define pci_unmap_single(cookie, address, size, dir)
8415 +#endif
8416 +
8417 +#endif /* DMA mapping */
8418 +
8419 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
8420 +
8421 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
8422 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
8423 +
8424 +/* pcmcia-cs provides its own netdevice compatibility layer */
8425 +#ifndef _COMPAT_NETDEVICE_H
8426 +
8427 +/*
8428 + * SoftNet
8429 + *
8430 + * For pre-softnet kernels we need to tell the upper layer not to
8431 + * re-enter start_xmit() while we are in there. However softnet
8432 + * guarantees not to enter while we are in there so there is no need
8433 + * to do the netif_stop_queue() dance unless the transmit queue really
8434 + * gets stuck. This should also improve performance according to tests
8435 + * done by Aman Singla.
8436 + */
8437 +
8438 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
8439 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
8440 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
8441 +
8442 +static inline void netif_start_queue(struct net_device *dev)
8443 +{
8444 + dev->tbusy = 0;
8445 + dev->interrupt = 0;
8446 + dev->start = 1;
8447 +}
8448 +
8449 +#define netif_queue_stopped(dev) (dev)->tbusy
8450 +#define netif_running(dev) (dev)->start
8451 +
8452 +#endif /* _COMPAT_NETDEVICE_H */
8453 +
8454 +#define netif_device_attach(dev) netif_start_queue(dev)
8455 +#define netif_device_detach(dev) netif_stop_queue(dev)
8456 +
8457 +/* 2.4.x renamed bottom halves to tasklets */
8458 +#define tasklet_struct tq_struct
8459 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
8460 +{
8461 + queue_task(tasklet, &tq_immediate);
8462 + mark_bh(IMMEDIATE_BH);
8463 +}
8464 +
8465 +static inline void tasklet_init(struct tasklet_struct *tasklet,
8466 + void (*func)(unsigned long),
8467 + unsigned long data)
8468 +{
8469 + tasklet->next = NULL;
8470 + tasklet->sync = 0;
8471 + tasklet->routine = (void (*)(void *))func;
8472 + tasklet->data = (void *)data;
8473 +}
8474 +#define tasklet_kill(tasklet) {do{} while(0);}
8475 +
8476 +/* 2.4.x introduced del_timer_sync() */
8477 +#define del_timer_sync(timer) del_timer(timer)
8478 +
8479 +#else
8480 +
8481 +#define netif_down(dev)
8482 +
8483 +#endif /* SoftNet */
8484 +
8485 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
8486 +
8487 +/*
8488 + * Emit code to initialise a tq_struct's routine and data pointers
8489 + */
8490 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
8491 + do { \
8492 + (_tq)->routine = _routine; \
8493 + (_tq)->data = _data; \
8494 + } while (0)
8495 +
8496 +/*
8497 + * Emit code to initialise all of a tq_struct
8498 + */
8499 +#define INIT_TQUEUE(_tq, _routine, _data) \
8500 + do { \
8501 + INIT_LIST_HEAD(&(_tq)->list); \
8502 + (_tq)->sync = 0; \
8503 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
8504 + } while (0)
8505 +
8506 +#endif
8507 +
8508 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
8509 +
8510 +/* Power management related routines */
8511 +
8512 +static inline int
8513 +pci_save_state(struct pci_dev *dev, u32 *buffer)
8514 +{
8515 + int i;
8516 + if (buffer) {
8517 + for (i = 0; i < 16; i++)
8518 + pci_read_config_dword(dev, i * 4,&buffer[i]);
8519 + }
8520 + return 0;
8521 +}
8522 +
8523 +static inline int
8524 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
8525 +{
8526 + int i;
8527 +
8528 + if (buffer) {
8529 + for (i = 0; i < 16; i++)
8530 + pci_write_config_dword(dev,i * 4, buffer[i]);
8531 + }
8532 + /*
8533 + * otherwise, write the context information we know from bootup.
8534 + * This works around a problem where warm-booting from Windows
8535 + * combined with a D3(hot)->D0 transition causes PCI config
8536 + * header data to be forgotten.
8537 + */
8538 + else {
8539 + for (i = 0; i < 6; i ++)
8540 + pci_write_config_dword(dev,
8541 + PCI_BASE_ADDRESS_0 + (i * 4),
8542 + pci_resource_start(dev, i));
8543 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
8544 + }
8545 + return 0;
8546 +}
8547 +
8548 +#endif /* PCI power management */
8549 +
8550 +/* Old cp0 access macros deprecated in 2.4.19 */
8551 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
8552 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
8553 +#endif
8554 +
8555 +#endif /* _linuxver_h_ */
8556 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h
8557 --- linux-2.6.12.5/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
8558 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/nvports.h 2005-09-16 10:29:18.191589360 +0200
8559 @@ -0,0 +1,62 @@
8560 +/*
8561 + * Broadcom Home Gateway Reference Design
8562 + * Ports Web Page Configuration Support Routines
8563 + *
8564 + * Copyright 2001-2003, Broadcom Corporation
8565 + * All Rights Reserved.
8566 + *
8567 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8568 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8569 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8570 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8571 + * $Id$
8572 + */
8573 +
8574 +#ifndef _nvports_h_
8575 +#define _nvports_h_
8576 +
8577 +#define uint32 unsigned long
8578 +#define uint16 unsigned short
8579 +#define uint unsigned int
8580 +#define uint8 unsigned char
8581 +#define uint64 unsigned long long
8582 +
8583 +enum FORCE_PORT {
8584 + FORCE_OFF,
8585 + FORCE_10H,
8586 + FORCE_10F,
8587 + FORCE_100H,
8588 + FORCE_100F,
8589 + FORCE_DOWN,
8590 + POWER_OFF
8591 +};
8592 +
8593 +typedef struct _PORT_ATTRIBS
8594 +{
8595 + uint autoneg;
8596 + uint force;
8597 + uint native;
8598 +} PORT_ATTRIBS;
8599 +
8600 +extern uint
8601 +nvExistsPortAttrib(char *attrib, uint portno);
8602 +
8603 +extern int
8604 +nvExistsAnyForcePortAttrib(uint portno);
8605 +
8606 +extern void
8607 +nvSetPortAttrib(char *attrib, uint portno);
8608 +
8609 +extern void
8610 +nvUnsetPortAttrib(char *attrib, uint portno);
8611 +
8612 +extern void
8613 +nvUnsetAllForcePortAttrib(uint portno);
8614 +
8615 +extern PORT_ATTRIBS
8616 +nvGetSwitchPortAttribs(uint portno);
8617 +
8618 +#endif /* _nvports_h_ */
8619 +
8620 +
8621 +
8622 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h
8623 --- linux-2.6.12.5/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8624 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/osl.h 2005-09-16 10:29:18.192589208 +0200
8625 @@ -0,0 +1,38 @@
8626 +/*
8627 + * OS Independent Layer
8628 + *
8629 + * Copyright 2001-2003, Broadcom Corporation
8630 + * All Rights Reserved.
8631 + *
8632 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8633 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8634 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8635 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8636 + * $Id$
8637 + */
8638 +
8639 +#ifndef _osl_h_
8640 +#define _osl_h_
8641 +
8642 +#ifdef V2_HAL
8643 +#include <v2hal_osl.h>
8644 +#elif defined(linux)
8645 +#include <linux_osl.h>
8646 +#elif PMON
8647 +#include <pmon_osl.h>
8648 +#elif defined(NDIS)
8649 +#include <ndis_osl.h>
8650 +#elif defined(_CFE_)
8651 +#include <cfe_osl.h>
8652 +#elif defined(MACOS9)
8653 +#include <macos9_osl.h>
8654 +#elif defined(MACOSX)
8655 +#include <macosx_osl.h>
8656 +#else
8657 +#error "Unsupported OSL requested"
8658 +#endif
8659 +
8660 +/* handy */
8661 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8662 +
8663 +#endif /* _osl_h_ */
8664 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h
8665 --- linux-2.6.12.5/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8666 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-09-16 10:29:18.192589208 +0200
8667 @@ -0,0 +1,362 @@
8668 +/*
8669 + * pcicfg.h: PCI configuration constants and structures.
8670 + *
8671 + * Copyright 2001-2003, Broadcom Corporation
8672 + * All Rights Reserved.
8673 + *
8674 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8675 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8676 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8677 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8678 + *
8679 + * $Id$
8680 + */
8681 +
8682 +#ifndef _h_pci_
8683 +#define _h_pci_
8684 +
8685 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8686 +#ifndef PCI_MAX_BUS
8687 +#define PCI_MAX_BUS 0x100
8688 +#endif
8689 +#ifndef PCI_MAX_DEVICES
8690 +#define PCI_MAX_DEVICES 0x20
8691 +#endif
8692 +#ifndef PCI_MAX_FUNCTION
8693 +#define PCI_MAX_FUNCTION 0x8
8694 +#endif
8695 +
8696 +#ifndef PCI_INVALID_VENDORID
8697 +#define PCI_INVALID_VENDORID 0xffff
8698 +#endif
8699 +#ifndef PCI_INVALID_DEVICEID
8700 +#define PCI_INVALID_DEVICEID 0xffff
8701 +#endif
8702 +
8703 +
8704 +/* Convert between bus-slot-function-register and config addresses */
8705 +
8706 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8707 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8708 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8709 +#define PCICFG_OFF_SHIFT 0 /* Bus shift */
8710 +
8711 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8712 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8713 +#define PCICFG_FUN_MASK 7 /* Function mask */
8714 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8715 +
8716 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8717 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8718 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8719 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8720 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8721 +
8722 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8723 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8724 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8725 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8726 +
8727 +
8728 +/* The actual config space */
8729 +
8730 +#define PCI_BAR_MAX 6
8731 +
8732 +#define PCI_ROM_BAR 8
8733 +
8734 +#define PCR_RSVDA_MAX 2
8735 +
8736 +typedef struct _pci_config_regs {
8737 + unsigned short vendor;
8738 + unsigned short device;
8739 + unsigned short command;
8740 + unsigned short status;
8741 + unsigned char rev_id;
8742 + unsigned char prog_if;
8743 + unsigned char sub_class;
8744 + unsigned char base_class;
8745 + unsigned char cache_line_size;
8746 + unsigned char latency_timer;
8747 + unsigned char header_type;
8748 + unsigned char bist;
8749 + unsigned long base[PCI_BAR_MAX];
8750 + unsigned long cardbus_cis;
8751 + unsigned short subsys_vendor;
8752 + unsigned short subsys_id;
8753 + unsigned long baserom;
8754 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8755 + unsigned char int_line;
8756 + unsigned char int_pin;
8757 + unsigned char min_gnt;
8758 + unsigned char max_lat;
8759 + unsigned char dev_dep[192];
8760 +} pci_config_regs;
8761 +
8762 +#define SZPCR (sizeof (pci_config_regs))
8763 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8764 +
8765 +/* A structure for the config registers is nice, but in most
8766 + * systems the config space is not memory mapped, so we need
8767 + * filed offsetts. :-(
8768 + */
8769 +#define PCI_CFG_VID 0
8770 +#define PCI_CFG_DID 2
8771 +#define PCI_CFG_CMD 4
8772 +#define PCI_CFG_STAT 6
8773 +#define PCI_CFG_REV 8
8774 +#define PCI_CFG_PROGIF 9
8775 +#define PCI_CFG_SUBCL 0xa
8776 +#define PCI_CFG_BASECL 0xb
8777 +#define PCI_CFG_CLSZ 0xc
8778 +#define PCI_CFG_LATTIM 0xd
8779 +#define PCI_CFG_HDR 0xe
8780 +#define PCI_CFG_BIST 0xf
8781 +#define PCI_CFG_BAR0 0x10
8782 +#define PCI_CFG_BAR1 0x14
8783 +#define PCI_CFG_BAR2 0x18
8784 +#define PCI_CFG_BAR3 0x1c
8785 +#define PCI_CFG_BAR4 0x20
8786 +#define PCI_CFG_BAR5 0x24
8787 +#define PCI_CFG_CIS 0x28
8788 +#define PCI_CFG_SVID 0x2c
8789 +#define PCI_CFG_SSID 0x2e
8790 +#define PCI_CFG_ROMBAR 0x30
8791 +#define PCI_CFG_INT 0x3c
8792 +#define PCI_CFG_PIN 0x3d
8793 +#define PCI_CFG_MINGNT 0x3e
8794 +#define PCI_CFG_MAXLAT 0x3f
8795 +
8796 +/* Classes and subclasses */
8797 +
8798 +typedef enum {
8799 + PCI_CLASS_OLD = 0,
8800 + PCI_CLASS_DASDI,
8801 + PCI_CLASS_NET,
8802 + PCI_CLASS_DISPLAY,
8803 + PCI_CLASS_MMEDIA,
8804 + PCI_CLASS_MEMORY,
8805 + PCI_CLASS_BRIDGE,
8806 + PCI_CLASS_COMM,
8807 + PCI_CLASS_BASE,
8808 + PCI_CLASS_INPUT,
8809 + PCI_CLASS_DOCK,
8810 + PCI_CLASS_CPU,
8811 + PCI_CLASS_SERIAL,
8812 + PCI_CLASS_INTELLIGENT = 0xe,
8813 + PCI_CLASS_SATELLITE,
8814 + PCI_CLASS_CRYPT,
8815 + PCI_CLASS_DSP,
8816 + PCI_CLASS_MAX
8817 +} pci_classes;
8818 +
8819 +typedef enum {
8820 + PCI_DASDI_SCSI,
8821 + PCI_DASDI_IDE,
8822 + PCI_DASDI_FLOPPY,
8823 + PCI_DASDI_IPI,
8824 + PCI_DASDI_RAID,
8825 + PCI_DASDI_OTHER = 0x80
8826 +} pci_dasdi_subclasses;
8827 +
8828 +typedef enum {
8829 + PCI_NET_ETHER,
8830 + PCI_NET_TOKEN,
8831 + PCI_NET_FDDI,
8832 + PCI_NET_ATM,
8833 + PCI_NET_OTHER = 0x80
8834 +} pci_net_subclasses;
8835 +
8836 +typedef enum {
8837 + PCI_DISPLAY_VGA,
8838 + PCI_DISPLAY_XGA,
8839 + PCI_DISPLAY_3D,
8840 + PCI_DISPLAY_OTHER = 0x80
8841 +} pci_display_subclasses;
8842 +
8843 +typedef enum {
8844 + PCI_MMEDIA_VIDEO,
8845 + PCI_MMEDIA_AUDIO,
8846 + PCI_MMEDIA_PHONE,
8847 + PCI_MEDIA_OTHER = 0x80
8848 +} pci_mmedia_subclasses;
8849 +
8850 +typedef enum {
8851 + PCI_MEMORY_RAM,
8852 + PCI_MEMORY_FLASH,
8853 + PCI_MEMORY_OTHER = 0x80
8854 +} pci_memory_subclasses;
8855 +
8856 +typedef enum {
8857 + PCI_BRIDGE_HOST,
8858 + PCI_BRIDGE_ISA,
8859 + PCI_BRIDGE_EISA,
8860 + PCI_BRIDGE_MC,
8861 + PCI_BRIDGE_PCI,
8862 + PCI_BRIDGE_PCMCIA,
8863 + PCI_BRIDGE_NUBUS,
8864 + PCI_BRIDGE_CARDBUS,
8865 + PCI_BRIDGE_RACEWAY,
8866 + PCI_BRIDGE_OTHER = 0x80
8867 +} pci_bridge_subclasses;
8868 +
8869 +typedef enum {
8870 + PCI_COMM_UART,
8871 + PCI_COMM_PARALLEL,
8872 + PCI_COMM_MULTIUART,
8873 + PCI_COMM_MODEM,
8874 + PCI_COMM_OTHER = 0x80
8875 +} pci_comm_subclasses;
8876 +
8877 +typedef enum {
8878 + PCI_BASE_PIC,
8879 + PCI_BASE_DMA,
8880 + PCI_BASE_TIMER,
8881 + PCI_BASE_RTC,
8882 + PCI_BASE_PCI_HOTPLUG,
8883 + PCI_BASE_OTHER = 0x80
8884 +} pci_base_subclasses;
8885 +
8886 +typedef enum {
8887 + PCI_INPUT_KBD,
8888 + PCI_INPUT_PEN,
8889 + PCI_INPUT_MOUSE,
8890 + PCI_INPUT_SCANNER,
8891 + PCI_INPUT_GAMEPORT,
8892 + PCI_INPUT_OTHER = 0x80
8893 +} pci_input_subclasses;
8894 +
8895 +typedef enum {
8896 + PCI_DOCK_GENERIC,
8897 + PCI_DOCK_OTHER = 0x80
8898 +} pci_dock_subclasses;
8899 +
8900 +typedef enum {
8901 + PCI_CPU_386,
8902 + PCI_CPU_486,
8903 + PCI_CPU_PENTIUM,
8904 + PCI_CPU_ALPHA = 0x10,
8905 + PCI_CPU_POWERPC = 0x20,
8906 + PCI_CPU_MIPS = 0x30,
8907 + PCI_CPU_COPROC = 0x40,
8908 + PCI_CPU_OTHER = 0x80
8909 +} pci_cpu_subclasses;
8910 +
8911 +typedef enum {
8912 + PCI_SERIAL_IEEE1394,
8913 + PCI_SERIAL_ACCESS,
8914 + PCI_SERIAL_SSA,
8915 + PCI_SERIAL_USB,
8916 + PCI_SERIAL_FIBER,
8917 + PCI_SERIAL_SMBUS,
8918 + PCI_SERIAL_OTHER = 0x80
8919 +} pci_serial_subclasses;
8920 +
8921 +typedef enum {
8922 + PCI_INTELLIGENT_I2O,
8923 +} pci_intelligent_subclasses;
8924 +
8925 +typedef enum {
8926 + PCI_SATELLITE_TV,
8927 + PCI_SATELLITE_AUDIO,
8928 + PCI_SATELLITE_VOICE,
8929 + PCI_SATELLITE_DATA,
8930 + PCI_SATELLITE_OTHER = 0x80
8931 +} pci_satellite_subclasses;
8932 +
8933 +typedef enum {
8934 + PCI_CRYPT_NETWORK,
8935 + PCI_CRYPT_ENTERTAINMENT,
8936 + PCI_CRYPT_OTHER = 0x80
8937 +} pci_crypt_subclasses;
8938 +
8939 +typedef enum {
8940 + PCI_DSP_DPIO,
8941 + PCI_DSP_OTHER = 0x80
8942 +} pci_dsp_subclasses;
8943 +
8944 +/* Header types */
8945 +typedef enum {
8946 + PCI_HEADER_NORMAL,
8947 + PCI_HEADER_BRIDGE,
8948 + PCI_HEADER_CARDBUS
8949 +} pci_header_types;
8950 +
8951 +
8952 +/* Overlay for a PCI-to-PCI bridge */
8953 +
8954 +#define PPB_RSVDA_MAX 2
8955 +#define PPB_RSVDD_MAX 8
8956 +
8957 +typedef struct _ppb_config_regs {
8958 + unsigned short vendor;
8959 + unsigned short device;
8960 + unsigned short command;
8961 + unsigned short status;
8962 + unsigned char rev_id;
8963 + unsigned char prog_if;
8964 + unsigned char sub_class;
8965 + unsigned char base_class;
8966 + unsigned char cache_line_size;
8967 + unsigned char latency_timer;
8968 + unsigned char header_type;
8969 + unsigned char bist;
8970 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8971 + unsigned char prim_bus;
8972 + unsigned char sec_bus;
8973 + unsigned char sub_bus;
8974 + unsigned char sec_lat;
8975 + unsigned char io_base;
8976 + unsigned char io_lim;
8977 + unsigned short sec_status;
8978 + unsigned short mem_base;
8979 + unsigned short mem_lim;
8980 + unsigned short pf_mem_base;
8981 + unsigned short pf_mem_lim;
8982 + unsigned long pf_mem_base_hi;
8983 + unsigned long pf_mem_lim_hi;
8984 + unsigned short io_base_hi;
8985 + unsigned short io_lim_hi;
8986 + unsigned short subsys_vendor;
8987 + unsigned short subsys_id;
8988 + unsigned long rsvd_b;
8989 + unsigned char rsvd_c;
8990 + unsigned char int_pin;
8991 + unsigned short bridge_ctrl;
8992 + unsigned char chip_ctrl;
8993 + unsigned char diag_ctrl;
8994 + unsigned short arb_ctrl;
8995 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8996 + unsigned char dev_dep[192];
8997 +} ppb_config_regs;
8998 +
8999 +/* Eveything below is BRCM HND proprietary */
9000 +
9001 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
9002 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
9003 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
9004 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
9005 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
9006 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
9007 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
9008 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
9009 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
9010 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
9011 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
9012 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
9013 +
9014 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
9015 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
9016 +
9017 +/* PCI_INT_MASK */
9018 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
9019 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
9020 +
9021 +/* PCI_SPROM_CONTROL */
9022 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
9023 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
9024 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
9025 +
9026 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
9027 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
9028 +
9029 +#endif
9030 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h
9031 --- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
9032 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-09-16 10:29:18.204587384 +0200
9033 @@ -0,0 +1,679 @@
9034 +/*
9035 + * Copyright 2001-2003, Broadcom Corporation
9036 + * All Rights Reserved.
9037 + *
9038 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9039 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9040 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9041 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9042 + *
9043 + * Fundamental types and constants relating to 802.11
9044 + *
9045 + * $Id$
9046 + */
9047 +
9048 +#ifndef _802_11_H_
9049 +#define _802_11_H_
9050 +
9051 +#ifndef _TYPEDEFS_H_
9052 +#include <typedefs.h>
9053 +#endif
9054 +
9055 +#ifndef _NET_ETHERNET_H_
9056 +#include <proto/ethernet.h>
9057 +#endif
9058 +
9059 +/* enable structure packing */
9060 +#if !defined(__GNUC__)
9061 +#pragma pack(1)
9062 +#endif
9063 +
9064 +/* some platforms require stronger medicine */
9065 +#if defined(__GNUC__)
9066 +#define PACKED __attribute__((packed))
9067 +#else
9068 +#define PACKED
9069 +#endif
9070 +
9071 +
9072 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
9073 +
9074 +/* Generic 802.11 frame constants */
9075 +#define DOT11_A3_HDR_LEN 24
9076 +#define DOT11_A4_HDR_LEN 30
9077 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
9078 +#define DOT11_FCS_LEN 4
9079 +#define DOT11_ICV_LEN 4
9080 +#define DOT11_ICV_AES_LEN 8
9081 +
9082 +
9083 +#define DOT11_KEY_INDEX_SHIFT 6
9084 +#define DOT11_IV_LEN 4
9085 +#define DOT11_IV_TKIP_LEN 8
9086 +#define DOT11_IV_AES_OCB_LEN 4
9087 +#define DOT11_IV_AES_CCM_LEN 8
9088 +
9089 +#define DOT11_MAX_MPDU_BODY_LEN 2312
9090 +#define DOT11_MAX_MPDU_LEN 2346 /* body len + A4 hdr + FCS */
9091 +#define DOT11_MAX_SSID_LEN 32
9092 +
9093 +/* dot11RTSThreshold */
9094 +#define DOT11_DEFAULT_RTS_LEN 2347
9095 +#define DOT11_MAX_RTS_LEN 2347
9096 +
9097 +/* dot11FragmentationThreshold */
9098 +#define DOT11_MIN_FRAG_LEN 256
9099 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
9100 +#define DOT11_DEFAULT_FRAG_LEN 2346
9101 +
9102 +/* dot11BeaconPeriod */
9103 +#define DOT11_MIN_BEACON_PERIOD 1
9104 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
9105 +
9106 +/* dot11DTIMPeriod */
9107 +#define DOT11_MIN_DTIM_PERIOD 1
9108 +#define DOT11_MAX_DTIM_PERIOD 0xFF
9109 +
9110 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
9111 +#define DOT11_LLC_SNAP_HDR_LEN 8
9112 +#define DOT11_OUI_LEN 3
9113 +struct dot11_llc_snap_header {
9114 + uint8 dsap; /* always 0xAA */
9115 + uint8 ssap; /* always 0xAA */
9116 + uint8 ctl; /* always 0x03 */
9117 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
9118 + Bridge-Tunnel: 0x00 0x00 0xF8 */
9119 + uint16 type; /* ethertype */
9120 +} PACKED;
9121 +
9122 +/* RFC1042 header used by 802.11 per 802.1H */
9123 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
9124 +
9125 +/* Generic 802.11 MAC header */
9126 +/*
9127 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
9128 + * The fields are defined such that the shorter 1, 2, and 3
9129 + * address headers just use the first k fields.
9130 + */
9131 +struct dot11_header {
9132 + uint16 fc; /* frame control */
9133 + uint16 durid; /* duration/ID */
9134 + struct ether_addr a1; /* address 1 */
9135 + struct ether_addr a2; /* address 2 */
9136 + struct ether_addr a3; /* address 3 */
9137 + uint16 seq; /* sequence control */
9138 + struct ether_addr a4; /* address 4 */
9139 +} PACKED;
9140 +
9141 +/* Control frames */
9142 +
9143 +struct dot11_rts_frame {
9144 + uint16 fc; /* frame control */
9145 + uint16 durid; /* duration/ID */
9146 + struct ether_addr ra; /* receiver address */
9147 + struct ether_addr ta; /* transmitter address */
9148 +} PACKED;
9149 +#define DOT11_RTS_LEN 16
9150 +
9151 +struct dot11_cts_frame {
9152 + uint16 fc; /* frame control */
9153 + uint16 durid; /* duration/ID */
9154 + struct ether_addr ra; /* receiver address */
9155 +} PACKED;
9156 +#define DOT11_CTS_LEN 10
9157 +
9158 +struct dot11_ack_frame {
9159 + uint16 fc; /* frame control */
9160 + uint16 durid; /* duration/ID */
9161 + struct ether_addr ra; /* receiver address */
9162 +} PACKED;
9163 +#define DOT11_ACK_LEN 10
9164 +
9165 +struct dot11_ps_poll_frame {
9166 + uint16 fc; /* frame control */
9167 + uint16 durid; /* AID */
9168 + struct ether_addr bssid; /* receiver address, STA in AP */
9169 + struct ether_addr ta; /* transmitter address */
9170 +} PACKED;
9171 +#define DOT11_PS_POLL_LEN 16
9172 +
9173 +struct dot11_cf_end_frame {
9174 + uint16 fc; /* frame control */
9175 + uint16 durid; /* duration/ID */
9176 + struct ether_addr ra; /* receiver address */
9177 + struct ether_addr bssid; /* transmitter address, STA in AP */
9178 +} PACKED;
9179 +#define DOT11_CS_END_LEN 16
9180 +
9181 +/* Management frame header */
9182 +struct dot11_management_header {
9183 + uint16 fc; /* frame control */
9184 + uint16 durid; /* duration/ID */
9185 + struct ether_addr da; /* receiver address */
9186 + struct ether_addr sa; /* transmitter address */
9187 + struct ether_addr bssid; /* BSS ID */
9188 + uint16 seq; /* sequence control */
9189 +} PACKED;
9190 +#define DOT11_MGMT_HDR_LEN 24
9191 +
9192 +/* Management frame payloads */
9193 +
9194 +struct dot11_bcn_prb {
9195 + uint32 timestamp[2];
9196 + uint16 beacon_interval;
9197 + uint16 capability;
9198 +} PACKED;
9199 +#define DOT11_BCN_PRB_LEN 12
9200 +
9201 +struct dot11_auth {
9202 + uint16 alg; /* algorithm */
9203 + uint16 seq; /* sequence control */
9204 + uint16 status; /* status code */
9205 +} PACKED;
9206 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
9207 +
9208 +struct dot11_assoc_req {
9209 + uint16 capability; /* capability information */
9210 + uint16 listen; /* listen interval */
9211 +} PACKED;
9212 +
9213 +struct dot11_assoc_resp {
9214 + uint16 capability; /* capability information */
9215 + uint16 status; /* status code */
9216 + uint16 aid; /* association ID */
9217 +} PACKED;
9218 +
9219 +struct dot11_action_measure {
9220 + uint8 category;
9221 + uint8 action;
9222 + uint8 token;
9223 + uint8 data[1];
9224 +} PACKED;
9225 +#define DOT11_ACTION_MEASURE_LEN 3
9226 +
9227 +/**************
9228 + 802.11h related definitions.
9229 +**************/
9230 +typedef struct {
9231 + uint8 id;
9232 + uint8 len;
9233 + uint8 power;
9234 +} dot11_power_cnst_t;
9235 +
9236 +typedef struct {
9237 + uint8 min;
9238 + uint8 max;
9239 +} dot11_power_cap_t;
9240 +
9241 +typedef struct {
9242 + uint8 id;
9243 + uint8 len;
9244 + uint8 tx_pwr;
9245 + uint8 margin;
9246 +} dot11_tpc_rep_t;
9247 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
9248 +
9249 +typedef struct {
9250 + uint8 id;
9251 + uint8 len;
9252 + uint8 first_channel;
9253 + uint8 num_channels;
9254 +} dot11_supp_channels_t;
9255 +
9256 +struct dot11_channel_switch {
9257 + uint8 id;
9258 + uint8 len;
9259 + uint8 mode;
9260 + uint8 channel;
9261 + uint8 count;
9262 +} PACKED;
9263 +typedef struct dot11_channel_switch dot11_channel_switch_t;
9264 +
9265 +/* 802.11h Measurement Request/Report IEs */
9266 +/* Measurement Type field */
9267 +#define DOT11_MEASURE_TYPE_BASIC 0
9268 +#define DOT11_MEASURE_TYPE_CCA 1
9269 +#define DOT11_MEASURE_TYPE_RPI 2
9270 +
9271 +/* Measurement Mode field */
9272 +
9273 +/* Measurement Request Modes */
9274 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
9275 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
9276 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
9277 +/* Measurement Report Modes */
9278 +#define DOT11_MEASURE_MODE_LATE (1<<0)
9279 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
9280 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
9281 +/* Basic Measurement Map bits */
9282 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
9283 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
9284 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
9285 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
9286 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
9287 +
9288 +typedef struct {
9289 + uint8 id;
9290 + uint8 len;
9291 + uint8 token;
9292 + uint8 mode;
9293 + uint8 type;
9294 + uint8 channel;
9295 + uint8 start_time[8];
9296 + uint16 duration;
9297 +} dot11_meas_req_t;
9298 +#define DOT11_MNG_IE_MREQ_LEN 14
9299 +/* length of Measure Request IE data not including variable len */
9300 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
9301 +
9302 +struct dot11_meas_rep {
9303 + uint8 id;
9304 + uint8 len;
9305 + uint8 token;
9306 + uint8 mode;
9307 + uint8 type;
9308 + union
9309 + {
9310 + struct {
9311 + uint8 channel;
9312 + uint8 start_time[8];
9313 + uint16 duration;
9314 + uint8 map;
9315 + } PACKED basic;
9316 + uint8 data[1];
9317 + } PACKED rep;
9318 +} PACKED;
9319 +typedef struct dot11_meas_rep dot11_meas_rep_t;
9320 +
9321 +/* length of Measure Report IE data not including variable len */
9322 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
9323 +
9324 +struct dot11_meas_rep_basic {
9325 + uint8 channel;
9326 + uint8 start_time[8];
9327 + uint16 duration;
9328 + uint8 map;
9329 +} PACKED;
9330 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
9331 +#define DOT11_MEASURE_BASIC_REP_LEN 12
9332 +
9333 +struct dot11_quiet {
9334 + uint8 id;
9335 + uint8 len;
9336 + uint8 count; /* TBTTs until beacon interval in quiet starts */
9337 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
9338 + uint16 duration;/* Length of quiet period, in TU's */
9339 + uint16 offset; /* TU's offset from TBTT in Count field */
9340 +} PACKED;
9341 +typedef struct dot11_quiet dot11_quiet_t;
9342 +
9343 +typedef struct {
9344 + uint8 channel;
9345 + uint8 map;
9346 +} chan_map_tuple_t;
9347 +
9348 +typedef struct {
9349 + uint8 id;
9350 + uint8 len;
9351 + uint8 eaddr[ETHER_ADDR_LEN];
9352 + uint8 interval;
9353 + chan_map_tuple_t map[1];
9354 +} dot11_ibss_dfs_t;
9355 +
9356 +
9357 +/* Macro to take a pointer to a beacon or probe response
9358 + * header and return the char* pointer to the SSID info element
9359 + */
9360 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
9361 +
9362 +/* Authentication frame payload constants */
9363 +#define DOT11_OPEN_SYSTEM 0
9364 +#define DOT11_SHARED_KEY 1
9365 +#define DOT11_CHALLENGE_LEN 128
9366 +
9367 +/* Frame control macros */
9368 +#define FC_PVER_MASK 0x3
9369 +#define FC_PVER_SHIFT 0
9370 +#define FC_TYPE_MASK 0xC
9371 +#define FC_TYPE_SHIFT 2
9372 +#define FC_SUBTYPE_MASK 0xF0
9373 +#define FC_SUBTYPE_SHIFT 4
9374 +#define FC_TODS 0x100
9375 +#define FC_TODS_SHIFT 8
9376 +#define FC_FROMDS 0x200
9377 +#define FC_FROMDS_SHIFT 9
9378 +#define FC_MOREFRAG 0x400
9379 +#define FC_MOREFRAG_SHIFT 10
9380 +#define FC_RETRY 0x800
9381 +#define FC_RETRY_SHIFT 11
9382 +#define FC_PM 0x1000
9383 +#define FC_PM_SHIFT 12
9384 +#define FC_MOREDATA 0x2000
9385 +#define FC_MOREDATA_SHIFT 13
9386 +#define FC_WEP 0x4000
9387 +#define FC_WEP_SHIFT 14
9388 +#define FC_ORDER 0x8000
9389 +#define FC_ORDER_SHIFT 15
9390 +
9391 +/* sequence control macros */
9392 +#define SEQNUM_SHIFT 4
9393 +#define FRAGNUM_MASK 0xF
9394 +
9395 +/* Frame Control type/subtype defs */
9396 +
9397 +/* FC Types */
9398 +#define FC_TYPE_MNG 0
9399 +#define FC_TYPE_CTL 1
9400 +#define FC_TYPE_DATA 2
9401 +
9402 +/* Management Subtypes */
9403 +#define FC_SUBTYPE_ASSOC_REQ 0
9404 +#define FC_SUBTYPE_ASSOC_RESP 1
9405 +#define FC_SUBTYPE_REASSOC_REQ 2
9406 +#define FC_SUBTYPE_REASSOC_RESP 3
9407 +#define FC_SUBTYPE_PROBE_REQ 4
9408 +#define FC_SUBTYPE_PROBE_RESP 5
9409 +#define FC_SUBTYPE_BEACON 8
9410 +#define FC_SUBTYPE_ATIM 9
9411 +#define FC_SUBTYPE_DISASSOC 10
9412 +#define FC_SUBTYPE_AUTH 11
9413 +#define FC_SUBTYPE_DEAUTH 12
9414 +#define FC_SUBTYPE_ACTION 13
9415 +
9416 +/* Control Subtypes */
9417 +#define FC_SUBTYPE_PS_POLL 10
9418 +#define FC_SUBTYPE_RTS 11
9419 +#define FC_SUBTYPE_CTS 12
9420 +#define FC_SUBTYPE_ACK 13
9421 +#define FC_SUBTYPE_CF_END 14
9422 +#define FC_SUBTYPE_CF_END_ACK 15
9423 +
9424 +/* Data Subtypes */
9425 +#define FC_SUBTYPE_DATA 0
9426 +#define FC_SUBTYPE_DATA_CF_ACK 1
9427 +#define FC_SUBTYPE_DATA_CF_POLL 2
9428 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
9429 +#define FC_SUBTYPE_NULL 4
9430 +#define FC_SUBTYPE_CF_ACK 5
9431 +#define FC_SUBTYPE_CF_POLL 6
9432 +#define FC_SUBTYPE_CF_ACK_POLL 7
9433 +
9434 +/* type-subtype combos */
9435 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
9436 +
9437 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
9438 +
9439 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
9440 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
9441 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
9442 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
9443 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
9444 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
9445 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
9446 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
9447 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
9448 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
9449 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
9450 +
9451 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
9452 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
9453 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
9454 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
9455 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
9456 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
9457 +
9458 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
9459 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
9460 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
9461 +
9462 +/* Management Frames */
9463 +
9464 +/* Management Frame Constants */
9465 +
9466 +/* Fixed fields */
9467 +#define DOT11_MNG_AUTH_ALGO_LEN 2
9468 +#define DOT11_MNG_AUTH_SEQ_LEN 2
9469 +#define DOT11_MNG_BEACON_INT_LEN 2
9470 +#define DOT11_MNG_CAP_LEN 2
9471 +#define DOT11_MNG_AP_ADDR_LEN 6
9472 +#define DOT11_MNG_LISTEN_INT_LEN 2
9473 +#define DOT11_MNG_REASON_LEN 2
9474 +#define DOT11_MNG_AID_LEN 2
9475 +#define DOT11_MNG_STATUS_LEN 2
9476 +#define DOT11_MNG_TIMESTAMP_LEN 8
9477 +
9478 +/* DUR/ID field in assoc resp is 0xc000 | AID */
9479 +#define DOT11_AID_MASK 0x3fff
9480 +
9481 +/* Reason Codes */
9482 +#define DOT11_RC_RESERVED 0
9483 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
9484 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
9485 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
9486 + leaving (or has left) IBSS or ESS */
9487 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
9488 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
9489 + all currently associated stations */
9490 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
9491 + nonauthenticated station */
9492 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
9493 + nonassociated station */
9494 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
9495 + leaving (or has left) BSS */
9496 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
9497 + not authenticated with responding station */
9498 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
9499 +
9500 +/* Status Codes */
9501 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
9502 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
9503 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
9504 + in the Capability Information field */
9505 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
9506 + confirm that association exists */
9507 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
9508 + the scope of this standard */
9509 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
9510 + specified authentication algorithm */
9511 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
9512 + authentication transaction sequence number
9513 + out of expected sequence */
9514 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
9515 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
9516 + for next frame in sequence */
9517 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
9518 + handle additional associated stations */
9519 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
9520 + not supporting all of the data rates in the
9521 + BSSBasicRateSet parameter */
9522 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
9523 + not supporting the Short Preamble option */
9524 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
9525 + not supporting the PBCC Modulation option */
9526 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
9527 + not supporting the Channel Agility option */
9528 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
9529 + capability is required. */
9530 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
9531 + Power Cap element is unacceptable. */
9532 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
9533 + Supported Channel element is unacceptable */
9534 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
9535 + not supporting the Short Slot Time option */
9536 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
9537 + not supporting the ER-PBCC Modulation option */
9538 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
9539 + not supporting the DSS-OFDM option */
9540 +
9541 +/* Info Elts, length of INFORMATION portion of Info Elts */
9542 +#define DOT11_MNG_DS_PARAM_LEN 1
9543 +#define DOT11_MNG_IBSS_PARAM_LEN 2
9544 +
9545 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
9546 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
9547 +#define DOT11_MNG_TIM_FIXED_LEN 3
9548 +#define DOT11_MNG_TIM_DTIM_COUNT 0
9549 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
9550 +#define DOT11_MNG_TIM_BITMAP_CTL 2
9551 +#define DOT11_MNG_TIM_PVB 3
9552 +
9553 +/* TLV defines */
9554 +#define TLV_TAG_OFF 0
9555 +#define TLV_LEN_OFF 1
9556 +#define TLV_HDR_LEN 2
9557 +#define TLV_BODY_OFF 2
9558 +
9559 +/* Management Frame Information Element IDs */
9560 +#define DOT11_MNG_SSID_ID 0
9561 +#define DOT11_MNG_RATES_ID 1
9562 +#define DOT11_MNG_FH_PARMS_ID 2
9563 +#define DOT11_MNG_DS_PARMS_ID 3
9564 +#define DOT11_MNG_CF_PARMS_ID 4
9565 +#define DOT11_MNG_TIM_ID 5
9566 +#define DOT11_MNG_IBSS_PARMS_ID 6
9567 +#define DOT11_MNG_COUNTRY_ID 7
9568 +#define DOT11_MNG_HOPPING_PARMS_ID 8
9569 +#define DOT11_MNG_HOPPING_TABLE_ID 9
9570 +#define DOT11_MNG_REQUEST_ID 10
9571 +#define DOT11_MNG_CHALLENGE_ID 16
9572 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
9573 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
9574 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
9575 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
9576 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
9577 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
9578 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
9579 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
9580 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
9581 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
9582 +#define DOT11_MNG_ERP_ID 42
9583 +#define DOT11_MNG_NONERP_ID 47
9584 +#define DOT11_MNG_EXT_RATES_ID 50
9585 +#define DOT11_MNG_WPA_ID 221
9586 +#define DOT11_MNG_PROPR_ID 221
9587 +
9588 +/* ERP info element bit values */
9589 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
9590 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
9591 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
9592 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
9593 +
9594 +/* Capability Information Field */
9595 +#define DOT11_CAP_ESS 0x0001
9596 +#define DOT11_CAP_IBSS 0x0002
9597 +#define DOT11_CAP_POLLABLE 0x0004
9598 +#define DOT11_CAP_POLL_RQ 0x0008
9599 +#define DOT11_CAP_PRIVACY 0x0010
9600 +#define DOT11_CAP_SHORT 0x0020
9601 +#define DOT11_CAP_PBCC 0x0040
9602 +#define DOT11_CAP_AGILITY 0x0080
9603 +#define DOT11_CAP_SPECTRUM 0x0100
9604 +#define DOT11_CAP_SHORTSLOT 0x0400
9605 +#define DOT11_CAP_CCK_OFDM 0x2000
9606 +
9607 +/* Action Frame Constants */
9608 +#define DOT11_ACTION_CAT_ERR_MASK 0x10
9609 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
9610 +
9611 +#define DOT11_ACTION_ID_M_REQ 0
9612 +#define DOT11_ACTION_ID_M_REP 1
9613 +#define DOT11_ACTION_ID_TPC_REQ 2
9614 +#define DOT11_ACTION_ID_TPC_REP 3
9615 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
9616 +
9617 +/* MLME Enumerations */
9618 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
9619 +#define DOT11_BSSTYPE_INDEPENDENT 1
9620 +#define DOT11_BSSTYPE_ANY 2
9621 +#define DOT11_SCANTYPE_ACTIVE 0
9622 +#define DOT11_SCANTYPE_PASSIVE 1
9623 +
9624 +/* 802.11 A PHY constants */
9625 +#define APHY_SLOT_TIME 9
9626 +#define APHY_SIFS_TIME 16
9627 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
9628 +#define APHY_PREAMBLE_TIME 16
9629 +#define APHY_SIGNAL_TIME 4
9630 +#define APHY_SYMBOL_TIME 4
9631 +#define APHY_SERVICE_NBITS 16
9632 +#define APHY_TAIL_NBITS 6
9633 +#define APHY_CWMIN 15
9634 +
9635 +/* 802.11 B PHY constants */
9636 +#define BPHY_SLOT_TIME 20
9637 +#define BPHY_SIFS_TIME 10
9638 +#define BPHY_DIFS_TIME 50
9639 +#define BPHY_PLCP_TIME 192
9640 +#define BPHY_PLCP_SHORT_TIME 96
9641 +#define BPHY_CWMIN 31
9642 +
9643 +/* 802.11 G constants */
9644 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
9645 +
9646 +#define PHY_CWMAX 1023
9647 +
9648 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
9649 +
9650 +/* dot11Counters Table - 802.11 spec., Annex D */
9651 +typedef struct d11cnt {
9652 + uint32 txfrag; /* dot11TransmittedFragmentCount */
9653 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
9654 + uint32 txfail; /* dot11FailedCount */
9655 + uint32 txretry; /* dot11RetryCount */
9656 + uint32 txretrie; /* dot11MultipleRetryCount */
9657 + uint32 rxdup; /* dot11FrameduplicateCount */
9658 + uint32 txrts; /* dot11RTSSuccessCount */
9659 + uint32 txnocts; /* dot11RTSFailureCount */
9660 + uint32 txnoack; /* dot11ACKFailureCount */
9661 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
9662 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
9663 + uint32 rxcrc; /* dot11FCSErrorCount */
9664 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
9665 + uint32 rxundec; /* dot11WEPUndecryptableCount */
9666 +} d11cnt_t;
9667 +
9668 +/* BRCM OUI */
9669 +#define BRCM_OUI "\x00\x10\x18"
9670 +
9671 +/* WPA definitions */
9672 +#define WPA_VERSION 1
9673 +#define WPA_OUI "\x00\x50\xF2"
9674 +
9675 +#define WPA_OUI_LEN 3
9676 +
9677 +/* WPA authentication modes */
9678 +#define WPA_AUTH_NONE 0 /* None */
9679 +#define WPA_AUTH_UNSPECIFIED 1 /* Unspecified authentication over 802.1X: default for WPA */
9680 +#define WPA_AUTH_PSK 2 /* Pre-shared Key over 802.1X */
9681 +#define WPA_AUTH_DISABLED 255 /* Legacy (i.e., non-WPA) */
9682 +
9683 +#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
9684 + (auth) == WPA_AUTH_UNSPECIFIED || \
9685 + (auth) == WPA_AUTH_PSK)
9686 +
9687 +
9688 +/* Key related defines */
9689 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
9690 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
9691 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
9692 +
9693 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
9694 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
9695 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
9696 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
9697 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
9698 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
9699 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
9700 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
9701 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
9702 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
9703 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
9704 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
9705 +#define AES_KEY_SIZE 16 /* size of AES key */
9706 +
9707 +#undef PACKED
9708 +#if !defined(__GNUC__)
9709 +#pragma pack()
9710 +#endif
9711 +
9712 +#endif /* _802_11_H_ */
9713 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
9714 --- linux-2.6.12.5/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
9715 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-09-16 10:29:18.205587232 +0200
9716 @@ -0,0 +1,145 @@
9717 +/*******************************************************************************
9718 + * $Id$
9719 + * Copyright 2001-2003, Broadcom Corporation
9720 + * All Rights Reserved.
9721 + *
9722 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9723 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9724 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9725 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9726 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
9727 + ******************************************************************************/
9728 +
9729 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
9730 +#define _NET_ETHERNET_H_
9731 +
9732 +#ifndef _TYPEDEFS_H_
9733 +#include "typedefs.h"
9734 +#endif
9735 +
9736 +#if defined(__GNUC__)
9737 +#define PACKED __attribute__((packed))
9738 +#else
9739 +#define PACKED
9740 +#endif
9741 +
9742 +/*
9743 + * The number of bytes in an ethernet (MAC) address.
9744 + */
9745 +#define ETHER_ADDR_LEN 6
9746 +
9747 +/*
9748 + * The number of bytes in the type field.
9749 + */
9750 +#define ETHER_TYPE_LEN 2
9751 +
9752 +/*
9753 + * The number of bytes in the trailing CRC field.
9754 + */
9755 +#define ETHER_CRC_LEN 4
9756 +
9757 +/*
9758 + * The length of the combined header.
9759 + */
9760 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
9761 +
9762 +/*
9763 + * The minimum packet length.
9764 + */
9765 +#define ETHER_MIN_LEN 64
9766 +
9767 +/*
9768 + * The minimum packet user data length.
9769 + */
9770 +#define ETHER_MIN_DATA 46
9771 +
9772 +/*
9773 + * The maximum packet length.
9774 + */
9775 +#define ETHER_MAX_LEN 1518
9776 +
9777 +/*
9778 + * The maximum packet user data length.
9779 + */
9780 +#define ETHER_MAX_DATA 1500
9781 +
9782 +/*
9783 + * Used to uniquely identify a 802.1q VLAN-tagged header.
9784 + */
9785 +#define VLAN_TAG 0x8100
9786 +
9787 +/*
9788 + * Located after dest & src address in ether header.
9789 + */
9790 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
9791 +
9792 +/*
9793 + * 4 bytes of vlan field info.
9794 + */
9795 +#define VLAN_FIELDS_SIZE 4
9796 +
9797 +/* location of pri bits in 16-bit vlan fields */
9798 +#define VLAN_PRI_SHIFT 13
9799 +
9800 +/* 3 bits of priority */
9801 +#define VLAN_PRI_MASK 7
9802 +
9803 +/* 802.1X ethertype */
9804 +#define ETHER_TYPE_802_1X 0x888e
9805 +
9806 +/*
9807 + * A macro to validate a length with
9808 + */
9809 +#define ETHER_IS_VALID_LEN(foo) \
9810 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
9811 +
9812 +
9813 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
9814 +/*
9815 + * Structure of a 10Mb/s Ethernet header.
9816 + */
9817 +struct ether_header {
9818 + uint8 ether_dhost[ETHER_ADDR_LEN];
9819 + uint8 ether_shost[ETHER_ADDR_LEN];
9820 + uint16 ether_type;
9821 +} PACKED ;
9822 +
9823 +/*
9824 + * Structure of a 48-bit Ethernet address.
9825 + */
9826 +struct ether_addr {
9827 + uint8 octet[ETHER_ADDR_LEN];
9828 +} PACKED ;
9829 +#endif
9830 +
9831 +/*
9832 + * Takes a pointer, returns true if a 48-bit multicast address
9833 + * (including broadcast, since it is all ones)
9834 + */
9835 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
9836 +
9837 +/*
9838 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
9839 + */
9840 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9841 + ((uint8 *)(ea))[1] & \
9842 + ((uint8 *)(ea))[2] & \
9843 + ((uint8 *)(ea))[3] & \
9844 + ((uint8 *)(ea))[4] & \
9845 + ((uint8 *)(ea))[5]) == 0xff)
9846 +
9847 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9848 +
9849 +/*
9850 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9851 + */
9852 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9853 + ((uint8 *)(ea))[1] | \
9854 + ((uint8 *)(ea))[2] | \
9855 + ((uint8 *)(ea))[3] | \
9856 + ((uint8 *)(ea))[4] | \
9857 + ((uint8 *)(ea))[5]) == 0)
9858 +
9859 +#undef PACKED
9860 +
9861 +#endif /* _NET_ETHERNET_H_ */
9862 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h
9863 --- linux-2.6.12.5/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
9864 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-09-16 10:29:18.205587232 +0200
9865 @@ -0,0 +1,69 @@
9866 +/*******************************************************************************
9867 + * $Id$
9868 + * Copyright 2001-2003, Broadcom Corporation
9869 + * All Rights Reserved.
9870 + *
9871 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9872 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9873 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9874 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9875 + * crc.h - a function to compute crc for iLine10 headers
9876 + ******************************************************************************/
9877 +
9878 +#ifndef _RTS_CRC_H_
9879 +#define _RTS_CRC_H_ 1
9880 +
9881 +#include "typedefs.h"
9882 +
9883 +#ifdef __cplusplus
9884 +extern "C" {
9885 +#endif
9886 +
9887 +
9888 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
9889 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
9890 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
9891 +
9892 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
9893 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
9894 +
9895 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
9896 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
9897 +
9898 +void hcs(uint8 *, uint);
9899 +uint8 crc8(uint8 *, uint, uint8);
9900 +uint16 crc16(uint8 *, uint, uint16);
9901 +uint32 crc32(uint8 *, uint, uint32);
9902 +
9903 +/* macros for common usage */
9904 +
9905 +#define APPEND_CRC8(pbytes, nbytes) \
9906 +do { \
9907 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
9908 + (pbytes)[(nbytes)] = tmp; \
9909 + (nbytes) += 1; \
9910 +} while (0)
9911 +
9912 +#define APPEND_CRC16(pbytes, nbytes) \
9913 +do { \
9914 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
9915 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
9916 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
9917 + (nbytes) += 2; \
9918 +} while (0)
9919 +
9920 +#define APPEND_CRC32(pbytes, nbytes) \
9921 +do { \
9922 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
9923 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
9924 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
9925 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
9926 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
9927 + (nbytes) += 4; \
9928 +} while (0)
9929 +
9930 +#ifdef __cplusplus
9931 +}
9932 +#endif
9933 +
9934 +#endif /* _RTS_CRC_H_ */
9935 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h
9936 --- linux-2.6.12.5/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9937 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/s5.h 2005-09-16 10:29:18.206587080 +0200
9938 @@ -0,0 +1,103 @@
9939 +#ifndef _S5_H_
9940 +#define _S5_H_
9941 +/*
9942 + * Copyright 2003, Broadcom Corporation
9943 + * All Rights Reserved.
9944 + *
9945 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9946 + * and MIPS3301 (R4K) System Address Space
9947 + *
9948 + * This program is free software; you can redistribute it and/or
9949 + * modify it under the terms of the GNU General Public License as
9950 + * published by the Free Software Foundation, located in the file
9951 + * LICENSE.
9952 + *
9953 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9954 + *
9955 + */
9956 +
9957 +/* BCM5365 Address map */
9958 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9959 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9960 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9961 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9962 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9963 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9964 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9965 +
9966 +/* BCM5365 Core register space */
9967 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9968 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9969 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9970 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9971 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9972 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9973 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9974 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9975 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9976 +
9977 +/* COM Ports 1/2 */
9978 +#define BCM5365_UART (BCM5365_REG_UARTS)
9979 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9980 +
9981 +/* Registers common to MIPS33 Core used in 5365 */
9982 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9983 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9984 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9985 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9986 +
9987 +/* Internal Core Sonics Backplane Devices */
9988 +#define INTERNAL_UART_COM1 BCM5365_UART
9989 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9990 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9991 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9992 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9993 +#define SB_REG_USB BCM5365_REG_USB
9994 +#define SB_REG_PCI BCM5365_REG_PCI
9995 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9996 +#define SB_REG_MEMC BCM5365_REG_MEMC
9997 +#define SB_REG_MEMC_OFF 0x6000
9998 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9999 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
10000 +
10001 +/*
10002 + * XXX
10003 + * 5365-specific backplane interrupt flag numbers. This should be done
10004 + * dynamically instead.
10005 + */
10006 +#define SBFLAG_PCI 0
10007 +#define SBFLAG_ENET0 1
10008 +#define SBFLAG_ILINE20 2
10009 +#define SBFLAG_CODEC 3
10010 +#define SBFLAG_USB 4
10011 +#define SBFLAG_EXTIF 5
10012 +#define SBFLAG_ENET1 6
10013 +
10014 +/* BCM95365 Local Bus devices */
10015 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
10016 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
10017 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
10018 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
10019 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
10020 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
10021 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
10022 +
10023 +/* Write to DLR2416 VFD Display character RAM */
10024 +#define LED_REG(x) \
10025 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
10026 +
10027 +#ifdef CONFIG_VSIM
10028 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
10029 + } while (0)
10030 +#else
10031 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
10032 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
10033 + *((int *)0xa0002ff8) = (trval); } while (0)
10034 +#endif
10035 +
10036 +/* BCM9536R Local Bus devices */
10037 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
10038 +
10039 +
10040 +
10041 +#endif /*!_S5_H_ */
10042 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h
10043 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
10044 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-09-16 10:29:18.207586928 +0200
10045 @@ -0,0 +1,281 @@
10046 +/*
10047 + * SiliconBackplane Chipcommon core hardware definitions.
10048 + *
10049 + * The chipcommon core provides chip identification, SB control,
10050 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
10051 + * gpio interface, extbus, and support for serial and parallel flashes.
10052 + *
10053 + * Copyright 2001-2003, Broadcom Corporation
10054 + * All Rights Reserved.
10055 + *
10056 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10057 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10058 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10059 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10060 + *
10061 + * $Id$
10062 + */
10063 +
10064 +#ifndef _SBCHIPC_H
10065 +#define _SBCHIPC_H
10066 +
10067 +
10068 +/* cpp contortions to concatenate w/arg prescan */
10069 +#ifndef PAD
10070 +#define _PADLINE(line) pad ## line
10071 +#define _XSTR(line) _PADLINE(line)
10072 +#define PAD _XSTR(__LINE__)
10073 +#endif /* PAD */
10074 +
10075 +typedef volatile struct {
10076 + uint32 chipid; /* 0x0 */
10077 + uint32 capabilities;
10078 + uint32 corecontrol; /* corerev >= 1 */
10079 + uint32 PAD[5];
10080 +
10081 + /* Interrupt control */
10082 + uint32 intstatus; /* 0x20 */
10083 + uint32 intmask;
10084 + uint32 PAD[6];
10085 +
10086 + /* serial flash interface registers */
10087 + uint32 flashcontrol; /* 0x40 */
10088 + uint32 flashaddress;
10089 + uint32 flashdata;
10090 + uint32 PAD[1];
10091 +
10092 + /* Silicon backplane configuration broadcast control */
10093 + uint32 broadcastaddress;
10094 + uint32 broadcastdata;
10095 + uint32 PAD[2];
10096 +
10097 + /* gpio - cleared only by power-on-reset */
10098 + uint32 gpioin; /* 0x60 */
10099 + uint32 gpioout;
10100 + uint32 gpioouten;
10101 + uint32 gpiocontrol;
10102 + uint32 gpiointpolarity;
10103 + uint32 gpiointmask;
10104 + uint32 PAD[2];
10105 +
10106 + /* Watchdog timer */
10107 + uint32 watchdog; /* 0x80 */
10108 + uint32 PAD[3];
10109 +
10110 + /* clock control */
10111 + uint32 clockcontrol_n; /* 0x90 */
10112 + uint32 clockcontrol_sb; /* aka m0 */
10113 + uint32 clockcontrol_pci; /* aka m1 */
10114 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
10115 + uint32 clockcontrol_mips; /* aka m3 */
10116 + uint32 uart_clkdiv; /* corerev >= 3 */
10117 + uint32 PAD[2];
10118 +
10119 + /* pll delay registers (corerev >= 4) */
10120 + uint32 pll_on_delay; /* 0xb0 */
10121 + uint32 fref_sel_delay;
10122 + uint32 slow_clk_ctl;
10123 + uint32 PAD[17];
10124 +
10125 + /* ExtBus control registers (corerev >= 3) */
10126 + uint32 cs01config; /* 0x100 */
10127 + uint32 cs01memwaitcnt;
10128 + uint32 cs01attrwaitcnt;
10129 + uint32 cs01iowaitcnt;
10130 + uint32 cs23config;
10131 + uint32 cs23memwaitcnt;
10132 + uint32 cs23attrwaitcnt;
10133 + uint32 cs23iowaitcnt;
10134 + uint32 cs4config;
10135 + uint32 cs4waitcnt;
10136 + uint32 parallelflashconfig;
10137 + uint32 parallelflashwaitcnt;
10138 + uint32 PAD[116];
10139 +
10140 + /* uarts */
10141 + uint8 uart0data; /* 0x300 */
10142 + uint8 uart0imr;
10143 + uint8 uart0fcr;
10144 + uint8 uart0lcr;
10145 + uint8 uart0mcr;
10146 + uint8 uart0lsr;
10147 + uint8 uart0msr;
10148 + uint8 uart0scratch;
10149 + uint8 PAD[248]; /* corerev >= 1 */
10150 +
10151 + uint8 uart1data; /* 0x400 */
10152 + uint8 uart1imr;
10153 + uint8 uart1fcr;
10154 + uint8 uart1lcr;
10155 + uint8 uart1mcr;
10156 + uint8 uart1lsr;
10157 + uint8 uart1msr;
10158 + uint8 uart1scratch;
10159 +} chipcregs_t;
10160 +
10161 +/* chipid */
10162 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
10163 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
10164 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
10165 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
10166 +#define CID_PKG_SHIFT 20 /* Package Option shift */
10167 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
10168 +#define CID_CC_SHIFT 24
10169 +
10170 +/* capabilities */
10171 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
10172 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
10173 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
10174 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
10175 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
10176 +#define CAP_EXTBUS 0x00000040 /* External bus present */
10177 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
10178 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
10179 +#define CAP_PWR_CTL 0x00040000 /* Power control */
10180 +
10181 +/* PLL type */
10182 +#define PLL_NONE 0x00000000
10183 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
10184 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
10185 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
10186 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
10187 +
10188 +/* corecontrol */
10189 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
10190 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
10191 +
10192 +/* intstatus/intmask */
10193 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
10194 +
10195 +/* slow_clk_ctl */
10196 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
10197 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
10198 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
10199 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
10200 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
10201 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
10202 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
10203 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
10204 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
10205 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
10206 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
10207 +#define SCC_CD_SHF 16 /* CLockDivider shift */
10208 +
10209 +/* clockcontrol_n */
10210 +#define CN_N1_MASK 0x3f /* n1 control */
10211 +#define CN_N2_MASK 0x3f00 /* n2 control */
10212 +#define CN_N2_SHIFT 8
10213 +
10214 +/* clockcontrol_sb/pci/uart */
10215 +#define CC_M1_MASK 0x3f /* m1 control */
10216 +#define CC_M2_MASK 0x3f00 /* m2 control */
10217 +#define CC_M2_SHIFT 8
10218 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10219 +#define CC_M3_SHIFT 16
10220 +#define CC_MC_MASK 0x1f000000 /* mux control */
10221 +#define CC_MC_SHIFT 24
10222 +
10223 +/* N3M Clock control values for 125Mhz */
10224 +#define CC_125_N 0x0802 /* Default values for bcm4310 */
10225 +#define CC_125_M 0x04020009
10226 +#define CC_125_M25 0x11090009
10227 +#define CC_125_M33 0x11090005
10228 +
10229 +/* N3M Clock control magic field values */
10230 +#define CC_F6_2 0x02 /* A factor of 2 in */
10231 +#define CC_F6_3 0x03 /* 6-bit fields like */
10232 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10233 +#define CC_F6_5 0x09
10234 +#define CC_F6_6 0x11
10235 +#define CC_F6_7 0x21
10236 +
10237 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10238 +
10239 +#define CC_MC_BYPASS 0x08
10240 +#define CC_MC_M1 0x04
10241 +#define CC_MC_M1M2 0x02
10242 +#define CC_MC_M1M2M3 0x01
10243 +#define CC_MC_M1M3 0x11
10244 +
10245 +/* Type 2 Clock control magic field values */
10246 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
10247 +#define CC_T2M2_BIAS 3 /* m2 bias */
10248 +
10249 +#define CC_T2MC_M1BYP 1
10250 +#define CC_T2MC_M2BYP 2
10251 +#define CC_T2MC_M3BYP 4
10252 +
10253 +/* Common clock base */
10254 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq */
10255 +
10256 +/* Flash types in the chipcommon capabilities register */
10257 +#define FLASH_NONE 0x000 /* No flash */
10258 +#define SFLASH_ST 0x100 /* ST serial flash */
10259 +#define SFLASH_AT 0x200 /* Atmel serial flash */
10260 +#define PFLASH 0x700 /* Parallel flash */
10261 +
10262 +/* Bits in the config registers */
10263 +#define CC_CFG_EN 0x0001 /* Enable */
10264 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
10265 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
10266 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
10267 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
10268 +#define CC_CFG_EM_IDE 0x000a /* IDE */
10269 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
10270 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
10271 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
10272 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
10273 +
10274 +/* Start/busy bit in flashcontrol */
10275 +#define SFLASH_START 0x80000000
10276 +#define SFLASH_BUSY SFLASH_START
10277 +
10278 +/* flashcontrol opcodes for ST flashes */
10279 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
10280 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
10281 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
10282 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
10283 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
10284 +#define SFLASH_ST_PP 0x0302 /* Page Program */
10285 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
10286 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
10287 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
10288 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
10289 +
10290 +/* Status register bits for ST flashes */
10291 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
10292 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
10293 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
10294 +#define SFLASH_ST_BP_SHIFT 2
10295 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
10296 +
10297 +/* flashcontrol opcodes for Atmel flashes */
10298 +#define SFLASH_AT_READ 0x07e8
10299 +#define SFLASH_AT_PAGE_READ 0x07d2
10300 +#define SFLASH_AT_BUF1_READ
10301 +#define SFLASH_AT_BUF2_READ
10302 +#define SFLASH_AT_STATUS 0x01d7
10303 +#define SFLASH_AT_BUF1_WRITE 0x0384
10304 +#define SFLASH_AT_BUF2_WRITE 0x0387
10305 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
10306 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
10307 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
10308 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
10309 +#define SFLASH_AT_PAGE_ERASE 0x0281
10310 +#define SFLASH_AT_BLOCK_ERASE 0x0250
10311 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
10312 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
10313 +#define SFLASH_AT_BUF1_LOAD 0x0253
10314 +#define SFLASH_AT_BUF2_LOAD 0x0255
10315 +#define SFLASH_AT_BUF1_COMPARE 0x0260
10316 +#define SFLASH_AT_BUF2_COMPARE 0x0261
10317 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
10318 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
10319 +
10320 +/* Status register bits for Atmel flashes */
10321 +#define SFLASH_AT_READY 0x80
10322 +#define SFLASH_AT_MISMATCH 0x40
10323 +#define SFLASH_AT_ID_MASK 0x38
10324 +#define SFLASH_AT_ID_SHIFT 3
10325 +
10326 +#endif /* _SBCHIPC_H */
10327 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h
10328 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
10329 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-09-16 10:29:18.207586928 +0200
10330 @@ -0,0 +1,296 @@
10331 +/*
10332 + * Broadcom SiliconBackplane hardware register definitions.
10333 + *
10334 + * Copyright 2001-2003, Broadcom Corporation
10335 + * All Rights Reserved.
10336 + *
10337 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10338 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10339 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10340 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10341 + * $Id$
10342 + */
10343 +
10344 +#ifndef _SBCONFIG_H
10345 +#define _SBCONFIG_H
10346 +
10347 +/* cpp contortions to concatenate w/arg prescan */
10348 +#ifndef PAD
10349 +#define _PADLINE(line) pad ## line
10350 +#define _XSTR(line) _PADLINE(line)
10351 +#define PAD _XSTR(__LINE__)
10352 +#endif
10353 +
10354 +/*
10355 + * SiliconBackplane Address Map.
10356 + * All regions may not exist on all chips.
10357 + */
10358 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
10359 +#define SB_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
10360 +#define SB_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
10361 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
10362 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
10363 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
10364 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
10365 +#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
10366 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
10367 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
10368 +
10369 +/* enumeration space related defs */
10370 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
10371 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
10372 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
10373 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
10374 +
10375 +/* mips address */
10376 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
10377 +
10378 +/*
10379 + * Sonics Configuration Space Registers.
10380 + */
10381 +#ifdef _LANGUAGE_ASSEMBLY
10382 +
10383 +#define SBIPSFLAG 0x08
10384 +#define SBTPSFLAG 0x18
10385 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
10386 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
10387 +#define SBADMATCH3 0x60
10388 +#define SBADMATCH2 0x68
10389 +#define SBADMATCH1 0x70
10390 +#define SBIMSTATE 0x90
10391 +#define SBINTVEC 0x94
10392 +#define SBTMSTATELOW 0x98
10393 +#define SBTMSTATEHIGH 0x9c
10394 +#define SBBWA0 0xa0
10395 +#define SBIMCONFIGLOW 0xa8
10396 +#define SBIMCONFIGHIGH 0xac
10397 +#define SBADMATCH0 0xb0
10398 +#define SBTMCONFIGLOW 0xb8
10399 +#define SBTMCONFIGHIGH 0xbc
10400 +#define SBBCONFIG 0xc0
10401 +#define SBBSTATE 0xc8
10402 +#define SBACTCNFG 0xd8
10403 +#define SBFLAGST 0xe8
10404 +#define SBIDLOW 0xf8
10405 +#define SBIDHIGH 0xfc
10406 +
10407 +
10408 +#else
10409 +
10410 +typedef volatile struct _sbconfig {
10411 + uint32 PAD[2];
10412 + uint32 sbipsflag; /* initiator port ocp slave flag */
10413 + uint32 PAD[3];
10414 + uint32 sbtpsflag; /* target port ocp slave flag */
10415 + uint32 PAD[11];
10416 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
10417 + uint32 PAD;
10418 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
10419 + uint32 PAD[3];
10420 + uint32 sbadmatch3; /* address match3 */
10421 + uint32 PAD;
10422 + uint32 sbadmatch2; /* address match2 */
10423 + uint32 PAD;
10424 + uint32 sbadmatch1; /* address match1 */
10425 + uint32 PAD[7];
10426 + uint32 sbimstate; /* initiator agent state */
10427 + uint32 sbintvec; /* interrupt mask */
10428 + uint32 sbtmstatelow; /* target state */
10429 + uint32 sbtmstatehigh; /* target state */
10430 + uint32 sbbwa0; /* bandwidth allocation table0 */
10431 + uint32 PAD;
10432 + uint32 sbimconfiglow; /* initiator configuration */
10433 + uint32 sbimconfighigh; /* initiator configuration */
10434 + uint32 sbadmatch0; /* address match0 */
10435 + uint32 PAD;
10436 + uint32 sbtmconfiglow; /* target configuration */
10437 + uint32 sbtmconfighigh; /* target configuration */
10438 + uint32 sbbconfig; /* broadcast configuration */
10439 + uint32 PAD;
10440 + uint32 sbbstate; /* broadcast state */
10441 + uint32 PAD[3];
10442 + uint32 sbactcnfg; /* activate configuration */
10443 + uint32 PAD[3];
10444 + uint32 sbflagst; /* current sbflags */
10445 + uint32 PAD[3];
10446 + uint32 sbidlow; /* identification */
10447 + uint32 sbidhigh; /* identification */
10448 +} sbconfig_t;
10449 +
10450 +#endif /* _LANGUAGE_ASSEMBLY */
10451 +
10452 +/* sbipsflag */
10453 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
10454 +#define SBIPS_INT1_SHIFT 0
10455 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
10456 +#define SBIPS_INT2_SHIFT 8
10457 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
10458 +#define SBIPS_INT3_SHIFT 16
10459 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
10460 +#define SBIPS_INT4_SHIFT 24
10461 +
10462 +/* sbtpsflag */
10463 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
10464 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
10465 +
10466 +/* sbtmerrlog */
10467 +#define SBTMEL_CM 0x00000007 /* command */
10468 +#define SBTMEL_CI 0x0000ff00 /* connection id */
10469 +#define SBTMEL_EC 0x0f000000 /* error code */
10470 +#define SBTMEL_ME 0x80000000 /* multiple error */
10471 +
10472 +/* sbimstate */
10473 +#define SBIM_PC 0xf /* pipecount */
10474 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
10475 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
10476 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
10477 +#define SBIM_AP_TK 0x20 /* use token only */
10478 +#define SBIM_AP_RSV 0x30 /* reserved */
10479 +#define SBIM_IBE 0x20000 /* inbanderror */
10480 +#define SBIM_TO 0x40000 /* timeout */
10481 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
10482 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
10483 +
10484 +/* sbtmstatelow */
10485 +#define SBTML_RESET 0x1 /* reset */
10486 +#define SBTML_REJ 0x2 /* reject */
10487 +#define SBTML_CLK 0x10000 /* clock enable */
10488 +#define SBTML_FGC 0x20000 /* force gated clocks on */
10489 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
10490 +#define SBTML_PE 0x40000000 /* pme enable */
10491 +#define SBTML_BE 0x80000000 /* bist enable */
10492 +
10493 +/* sbtmstatehigh */
10494 +#define SBTMH_SERR 0x1 /* serror */
10495 +#define SBTMH_INT 0x2 /* interrupt */
10496 +#define SBTMH_BUSY 0x4 /* busy */
10497 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
10498 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
10499 +#define SBTMH_GCR 0x20000000 /* gated clock request */
10500 +#define SBTMH_BISTF 0x40000000 /* bist failed */
10501 +#define SBTMH_BISTD 0x80000000 /* bist done */
10502 +
10503 +/* sbbwa0 */
10504 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
10505 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
10506 +#define SBBWA_TAB1_SHIFT 16
10507 +
10508 +/* sbimconfiglow */
10509 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
10510 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
10511 +#define SBIMCL_RTO_SHIFT 4
10512 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
10513 +#define SBIMCL_CID_SHIFT 16
10514 +
10515 +/* sbimconfighigh */
10516 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
10517 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
10518 +#define SBIMCH_TEM_SHIFT 4
10519 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
10520 +#define SBIMCH_BEM_SHIFT 6
10521 +
10522 +/* sbadmatch0 */
10523 +#define SBAM_TYPE_MASK 0x3 /* address type */
10524 +#define SBAM_AD64 0x4 /* reserved */
10525 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
10526 +#define SBAM_ADINT0_SHIFT 3
10527 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
10528 +#define SBAM_ADINT1_SHIFT 3
10529 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
10530 +#define SBAM_ADINT2_SHIFT 3
10531 +#define SBAM_ADEN 0x400 /* enable */
10532 +#define SBAM_ADNEG 0x800 /* negative decode */
10533 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
10534 +#define SBAM_BASE0_SHIFT 8
10535 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
10536 +#define SBAM_BASE1_SHIFT 12
10537 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
10538 +#define SBAM_BASE2_SHIFT 16
10539 +
10540 +/* sbtmconfiglow */
10541 +#define SBTMCL_CD_MASK 0xff /* clock divide */
10542 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
10543 +#define SBTMCL_CO_SHIFT 11
10544 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
10545 +#define SBTMCL_IF_SHIFT 18
10546 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
10547 +#define SBTMCL_IM_SHIFT 24
10548 +
10549 +/* sbtmconfighigh */
10550 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
10551 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
10552 +#define SBTMCH_RM_SHIFT 2
10553 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
10554 +#define SBTMCH_SM_SHIFT 4
10555 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
10556 +#define SBTMCH_EM_SHIFT 8
10557 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
10558 +#define SBTMCH_IM_SHIFT 10
10559 +
10560 +/* sbbconfig */
10561 +#define SBBC_LAT_MASK 0x3 /* sb latency */
10562 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
10563 +#define SBBC_MAX0_SHIFT 16
10564 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
10565 +#define SBBC_MAX1_SHIFT 20
10566 +
10567 +/* sbbstate */
10568 +#define SBBS_SRD 0x1 /* st reg disable */
10569 +#define SBBS_HRD 0x2 /* hold reg disable */
10570 +
10571 +/* sbidlow */
10572 +#define SBIDL_CS_MASK 0x3 /* config space */
10573 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
10574 +#define SBIDL_AR_SHIFT 3
10575 +#define SBIDL_SYNCH 0x40 /* sync */
10576 +#define SBIDL_INIT 0x80 /* initiator */
10577 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
10578 +#define SBIDL_MINLAT_SHIFT 8
10579 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
10580 +#define SBIDL_MAXLAT_SHIFT 12
10581 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
10582 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
10583 +#define SBIDL_CW_SHIFT 18
10584 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
10585 +#define SBIDL_TP_SHIFT 20
10586 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
10587 +#define SBIDL_IP_SHIFT 24
10588 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
10589 +#define SBIDL_RV_SHIFT 28
10590 +
10591 +/* sbidhigh */
10592 +#define SBIDH_RC_MASK 0xf /* revision code*/
10593 +#define SBIDH_CC_MASK 0xfff0 /* core code */
10594 +#define SBIDH_CC_SHIFT 4
10595 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
10596 +#define SBIDH_VC_SHIFT 16
10597 +
10598 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
10599 +
10600 +/* vendor codes */
10601 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
10602 +
10603 +/* core codes */
10604 +#define SB_CC 0x800 /* chipcommon core */
10605 +#define SB_ILINE20 0x801 /* iline20 core */
10606 +#define SB_SDRAM 0x803 /* sdram core */
10607 +#define SB_PCI 0x804 /* pci core */
10608 +#define SB_MIPS 0x805 /* mips core */
10609 +#define SB_ENET 0x806 /* enet mac core */
10610 +#define SB_CODEC 0x807 /* v90 codec core */
10611 +#define SB_USB 0x808 /* usb 1.1 host/device core */
10612 +#define SB_ILINE100 0x80a /* iline100 core */
10613 +#define SB_IPSEC 0x80b /* ipsec core */
10614 +#define SB_PCMCIA 0x80d /* pcmcia core */
10615 +#define SB_MEMC 0x80f /* memc sdram core */
10616 +#define SB_EXTIF 0x811 /* external interface core */
10617 +#define SB_D11 0x812 /* 802.11 MAC core */
10618 +#define SB_MIPS33 0x816 /* mips3302 core */
10619 +#define SB_USB11H 0x817 /* usb 1.1 host core */
10620 +#define SB_USB11D 0x818 /* usb 1.1 device core */
10621 +#define SB_USB20H 0x819 /* usb 2.0 host core */
10622 +#define SB_USB20D 0x81A /* usb 2.0 device core */
10623 +#define SB_SDIOH 0x81B /* sdio host core */
10624 +#define SB_ROBO 0x81C /* robo switch core */
10625 +
10626 +#endif /* _SBCONFIG_H */
10627 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h
10628 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
10629 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-09-16 10:29:18.208586776 +0200
10630 @@ -0,0 +1,242 @@
10631 +/*
10632 + * Hardware-specific External Interface I/O core definitions
10633 + * for the BCM47xx family of SiliconBackplane-based chips.
10634 + *
10635 + * The External Interface core supports a total of three external chip selects
10636 + * supporting external interfaces. One of the external chip selects is
10637 + * used for Flash, one is used for PCMCIA, and the other may be
10638 + * programmed to support either a synchronous interface or an
10639 + * asynchronous interface. The asynchronous interface can be used to
10640 + * support external devices such as UARTs and the BCM2019 Bluetooth
10641 + * baseband processor.
10642 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
10643 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
10644 + *
10645 + * Copyright 2001-2003, Broadcom Corporation
10646 + * All Rights Reserved.
10647 + *
10648 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10649 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10650 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10651 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10652 + * $Id$
10653 + */
10654 +
10655 +#ifndef _SBEXTIF_H
10656 +#define _SBEXTIF_H
10657 +
10658 +/* external interface address space */
10659 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
10660 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
10661 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
10662 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
10663 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
10664 +
10665 +/* cpp contortions to concatenate w/arg prescan */
10666 +#ifndef PAD
10667 +#define _PADLINE(line) pad ## line
10668 +#define _XSTR(line) _PADLINE(line)
10669 +#define PAD _XSTR(__LINE__)
10670 +#endif /* PAD */
10671 +
10672 +/*
10673 + * The multiple instances of output and output enable registers
10674 + * are present to allow driver software for multiple cores to control
10675 + * gpio outputs without needing to share a single register pair.
10676 + */
10677 +struct gpiouser {
10678 + uint32 out;
10679 + uint32 outen;
10680 +};
10681 +#define NGPIOUSER 5
10682 +
10683 +typedef volatile struct {
10684 + uint32 corecontrol;
10685 + uint32 extstatus;
10686 + uint32 PAD[2];
10687 +
10688 + /* pcmcia control registers */
10689 + uint32 pcmcia_config;
10690 + uint32 pcmcia_memwait;
10691 + uint32 pcmcia_attrwait;
10692 + uint32 pcmcia_iowait;
10693 +
10694 + /* programmable interface control registers */
10695 + uint32 prog_config;
10696 + uint32 prog_waitcount;
10697 +
10698 + /* flash control registers */
10699 + uint32 flash_config;
10700 + uint32 flash_waitcount;
10701 + uint32 PAD[4];
10702 +
10703 + uint32 watchdog;
10704 +
10705 + /* clock control */
10706 + uint32 clockcontrol_n;
10707 + uint32 clockcontrol_sb;
10708 + uint32 clockcontrol_pci;
10709 + uint32 clockcontrol_mii;
10710 + uint32 PAD[3];
10711 +
10712 + /* gpio */
10713 + uint32 gpioin;
10714 + struct gpiouser gpio[NGPIOUSER];
10715 + uint32 PAD;
10716 + uint32 ejtagouten;
10717 + uint32 gpiointpolarity;
10718 + uint32 gpiointmask;
10719 + uint32 PAD[153];
10720 +
10721 + uint8 uartdata;
10722 + uint8 PAD[3];
10723 + uint8 uartimer;
10724 + uint8 PAD[3];
10725 + uint8 uartfcr;
10726 + uint8 PAD[3];
10727 + uint8 uartlcr;
10728 + uint8 PAD[3];
10729 + uint8 uartmcr;
10730 + uint8 PAD[3];
10731 + uint8 uartlsr;
10732 + uint8 PAD[3];
10733 + uint8 uartmsr;
10734 + uint8 PAD[3];
10735 + uint8 uartscratch;
10736 + uint8 PAD[3];
10737 +} extifregs_t;
10738 +
10739 +/* corecontrol */
10740 +#define CC_UE (1 << 0) /* uart enable */
10741 +
10742 +/* extstatus */
10743 +#define ES_EM (1 << 0) /* endian mode (ro) */
10744 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10745 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10746 +
10747 +/* gpio bit mask */
10748 +#define GPIO_BIT0 (1 << 0)
10749 +#define GPIO_BIT1 (1 << 1)
10750 +#define GPIO_BIT2 (1 << 2)
10751 +#define GPIO_BIT3 (1 << 3)
10752 +#define GPIO_BIT4 (1 << 4)
10753 +#define GPIO_BIT5 (1 << 5)
10754 +#define GPIO_BIT6 (1 << 6)
10755 +#define GPIO_BIT7 (1 << 7)
10756 +
10757 +
10758 +/* pcmcia/prog/flash_config */
10759 +#define CF_EN (1 << 0) /* enable */
10760 +#define CF_EM_MASK 0xe /* mode */
10761 +#define CF_EM_SHIFT 1
10762 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10763 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10764 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10765 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10766 +#define CF_BS (1 << 5) /* byteswap */
10767 +#define CF_CD_MASK 0xc0 /* clock divider */
10768 +#define CF_CD_SHIFT 6
10769 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10770 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10771 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10772 +#define CF_CE (1 << 8) /* clock enable */
10773 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10774 +
10775 +/* pcmcia_memwait */
10776 +#define PM_W0_MASK 0x3f /* waitcount0 */
10777 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10778 +#define PM_W1_SHIFT 8
10779 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10780 +#define PM_W2_SHIFT 16
10781 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10782 +#define PM_W3_SHIFT 24
10783 +
10784 +/* pcmcia_attrwait */
10785 +#define PA_W0_MASK 0x3f /* waitcount0 */
10786 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10787 +#define PA_W1_SHIFT 8
10788 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10789 +#define PA_W2_SHIFT 16
10790 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10791 +#define PA_W3_SHIFT 24
10792 +
10793 +/* pcmcia_iowait */
10794 +#define PI_W0_MASK 0x3f /* waitcount0 */
10795 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10796 +#define PI_W1_SHIFT 8
10797 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10798 +#define PI_W2_SHIFT 16
10799 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10800 +#define PI_W3_SHIFT 24
10801 +
10802 +/* prog_waitcount */
10803 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10804 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10805 +#define PW_W1_SHIFT 8
10806 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10807 +#define PW_W2_SHIFT 16
10808 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10809 +#define PW_W3_SHIFT 24
10810 +
10811 +#define PW_W0 0x0000000c
10812 +#define PW_W1 0x00000a00
10813 +#define PW_W2 0x00020000
10814 +#define PW_W3 0x01000000
10815 +
10816 +/* flash_waitcount */
10817 +#define FW_W0_MASK 0x1f /* waitcount0 */
10818 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10819 +#define FW_W1_SHIFT 8
10820 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10821 +#define FW_W2_SHIFT 16
10822 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10823 +#define FW_W3_SHIFT 24
10824 +
10825 +/* watchdog */
10826 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10827 +
10828 +/* clockcontrol_n */
10829 +#define CN_N1_MASK 0x3f /* n1 control */
10830 +#define CN_N2_MASK 0x3f00 /* n2 control */
10831 +#define CN_N2_SHIFT 8
10832 +
10833 +/* clockcontrol_sb/pci/mii */
10834 +#define CC_M1_MASK 0x3f /* m1 control */
10835 +#define CC_M2_MASK 0x3f00 /* m2 control */
10836 +#define CC_M2_SHIFT 8
10837 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10838 +#define CC_M3_SHIFT 16
10839 +#define CC_MC_MASK 0x1f000000 /* mux control */
10840 +#define CC_MC_SHIFT 24
10841 +
10842 +/* Clock control default values */
10843 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10844 +#define CC_DEF_100 0x04020011
10845 +#define CC_DEF_33 0x11030011
10846 +#define CC_DEF_25 0x11050011
10847 +
10848 +/* Clock control values for 125Mhz */
10849 +#define CC_125_N 0x0802
10850 +#define CC_125_M 0x04020009
10851 +#define CC_125_M25 0x11090009
10852 +#define CC_125_M33 0x11090005
10853 +
10854 +/* Clock control magic field values */
10855 +#define CC_F6_2 0x02 /* A factor of 2 in */
10856 +#define CC_F6_3 0x03 /* 6-bit fields like */
10857 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10858 +#define CC_F6_5 0x09
10859 +#define CC_F6_6 0x11
10860 +#define CC_F6_7 0x21
10861 +
10862 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10863 +
10864 +#define CC_MC_BYPASS 0x08
10865 +#define CC_MC_M1 0x04
10866 +#define CC_MC_M1M2 0x02
10867 +#define CC_MC_M1M2M3 0x01
10868 +#define CC_MC_M1M3 0x11
10869 +
10870 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10871 +
10872 +#endif /* _SBEXTIF_H */
10873 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h
10874 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10875 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-09-16 10:29:18.209586624 +0200
10876 @@ -0,0 +1,144 @@
10877 +/*
10878 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10879 + *
10880 + * Copyright 2001-2003, Broadcom Corporation
10881 + * All Rights Reserved.
10882 + *
10883 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10884 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10885 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10886 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10887 + * $Id$
10888 + */
10889 +
10890 +#ifndef _SBMEMC_H
10891 +#define _SBMEMC_H
10892 +
10893 +#ifdef _LANGUAGE_ASSEMBLY
10894 +
10895 +#define MEMC_CONTROL 0x00
10896 +#define MEMC_CONFIG 0x04
10897 +#define MEMC_REFRESH 0x08
10898 +#define MEMC_BISTSTAT 0x0c
10899 +#define MEMC_MODEBUF 0x10
10900 +#define MEMC_BKCLS 0x14
10901 +#define MEMC_PRIORINV 0x18
10902 +#define MEMC_DRAMTIM 0x1c
10903 +#define MEMC_INTSTAT 0x20
10904 +#define MEMC_INTMASK 0x24
10905 +#define MEMC_INTINFO 0x28
10906 +#define MEMC_NCDLCTL 0x30
10907 +#define MEMC_RDNCDLCOR 0x34
10908 +#define MEMC_WRNCDLCOR 0x38
10909 +#define MEMC_MISCDLYCTL 0x3c
10910 +#define MEMC_DQSGATENCDL 0x40
10911 +#define MEMC_SPARE 0x44
10912 +#define MEMC_TPADDR 0x48
10913 +#define MEMC_TPDATA 0x4c
10914 +#define MEMC_BARRIER 0x50
10915 +#define MEMC_CORE 0x54
10916 +
10917 +
10918 +#else
10919 +
10920 +/* Sonics side: MEMC core registers */
10921 +typedef volatile struct sbmemcregs {
10922 + uint32 control;
10923 + uint32 config;
10924 + uint32 refresh;
10925 + uint32 biststat;
10926 + uint32 modebuf;
10927 + uint32 bkcls;
10928 + uint32 priorinv;
10929 + uint32 dramtim;
10930 + uint32 intstat;
10931 + uint32 intmask;
10932 + uint32 intinfo;
10933 + uint32 reserved1;
10934 + uint32 ncdlctl;
10935 + uint32 rdncdlcor;
10936 + uint32 wrncdlcor;
10937 + uint32 miscdlyctl;
10938 + uint32 dqsgatencdl;
10939 + uint32 spare;
10940 + uint32 tpaddr;
10941 + uint32 tpdata;
10942 + uint32 barrier;
10943 + uint32 core;
10944 +} sbmemcregs_t;
10945 +
10946 +#endif
10947 +
10948 +/* MEMC Core Init values (OCP ID 0x80f) */
10949 +
10950 +/* For sdr: */
10951 +#define MEMC_SD_CONFIG_INIT 0x00048000
10952 +#define MEMC_SD_DRAMTIM_INIT 0x000754da
10953 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10954 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10955 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10956 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10957 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10958 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10959 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10960 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10961 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10962 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10963 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10964 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10965 +
10966 +
10967 +/* This is for SDRM8X8X4 */
10968 +#define MEMC_SDR_INIT 0x0008
10969 +#define MEMC_SDR_MODE 0x32
10970 +#define MEMC_SDR_NCDL 0x00020032
10971 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10972 +
10973 +/* For ddr: */
10974 +#define MEMC_CONFIG_INIT 0x00048000
10975 +#define MEMC_DRAMTIM_INIT 0x000754d9
10976 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10977 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10978 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10979 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10980 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10981 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10982 +#define MEMC_NCDLCTL_INIT 0x00002001
10983 +#define MEMC_CONTROL_INIT0 0x00000002
10984 +#define MEMC_CONTROL_INIT1 0x00000008
10985 +#define MEMC_MODEBUF_INIT0 0x00004000
10986 +#define MEMC_CONTROL_INIT2 0x00000010
10987 +#define MEMC_MODEBUF_INIT1 0x00000100
10988 +#define MEMC_CONTROL_INIT3 0x00000010
10989 +#define MEMC_CONTROL_INIT4 0x00000008
10990 +#define MEMC_REFRESH_INIT 0x0000840f
10991 +#define MEMC_CONTROL_INIT5 0x00000004
10992 +#define MEMC_MODEBUF_INIT2 0x00000000
10993 +#define MEMC_CONTROL_INIT6 0x00000010
10994 +#define MEMC_CONTROL_INIT7 0x00000001
10995 +
10996 +
10997 +/* This is for DDRM16X16X2 */
10998 +#define MEMC_DDR_INIT 0x0009
10999 +#define MEMC_DDR_MODE 0x62
11000 +#define MEMC_DDR_NCDL 0x0005050a
11001 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
11002 +
11003 +/* mask for sdr/ddr calibration registers */
11004 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
11005 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
11006 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
11007 +
11008 +/* masks for miscdlyctl registers */
11009 +#define MEMC_MISC_SM_MASK 0x30000000
11010 +#define MEMC_MISC_SM_SHIFT 28
11011 +#define MEMC_MISC_SD_MASK 0x0f000000
11012 +#define MEMC_MISC_SD_SHIFT 24
11013 +
11014 +/* hw threshhold for calculating wr/rd for sdr memc */
11015 +#define MEMC_CD_THRESHOLD 128
11016 +
11017 +/* Low bit of init register says if memc is ddr or sdr */
11018 +#define MEMC_CONFIG_DDR 0x00000001
11019 +
11020 +#endif /* _SBMEMC_H */
11021 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h
11022 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
11023 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-09-16 10:29:18.209586624 +0200
11024 @@ -0,0 +1,56 @@
11025 +/*
11026 + * Broadcom SiliconBackplane MIPS definitions
11027 + *
11028 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
11029 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
11030 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
11031 + * interface. The core revision is stored in the SB ID register in SB
11032 + * configuration space.
11033 + *
11034 + * Copyright 2001-2003, Broadcom Corporation
11035 + * All Rights Reserved.
11036 + *
11037 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11038 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11039 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11040 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11041 + *
11042 + * $Id$
11043 + */
11044 +
11045 +#ifndef _SBMIPS_H
11046 +#define _SBMIPS_H
11047 +
11048 +#ifndef _LANGUAGE_ASSEMBLY
11049 +
11050 +/* cpp contortions to concatenate w/arg prescan */
11051 +#ifndef PAD
11052 +#define _PADLINE(line) pad ## line
11053 +#define _XSTR(line) _PADLINE(line)
11054 +#define PAD _XSTR(__LINE__)
11055 +#endif /* PAD */
11056 +
11057 +typedef volatile struct {
11058 + uint32 corecontrol;
11059 + uint32 PAD[2];
11060 + uint32 biststatus;
11061 + uint32 PAD[4];
11062 + uint32 intstatus;
11063 + uint32 intmask;
11064 + uint32 timer;
11065 +} mipsregs_t;
11066 +
11067 +extern uint32 sb_flag(void *sbh);
11068 +extern uint sb_irq(void *sbh);
11069 +
11070 +extern void sb_serial_init(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
11071 +
11072 +extern void sb_mips_init(void *sbh);
11073 +extern uint32 sb_mips_clock(void *sbh);
11074 +extern bool sb_mips_setclock(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
11075 +
11076 +extern uint32 sb_memc_get_ncdl(void *sbh);
11077 +
11078 +#endif /* _LANGUAGE_ASSEMBLY */
11079 +
11080 +#endif /* _SBMIPS_H */
11081 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h
11082 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
11083 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-09-16 10:29:18.209586624 +0200
11084 @@ -0,0 +1,113 @@
11085 +/*
11086 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
11087 + *
11088 + * $Id$
11089 + * Copyright 2001-2003, Broadcom Corporation
11090 + * All Rights Reserved.
11091 + *
11092 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11093 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11094 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11095 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11096 + */
11097 +
11098 +#ifndef _SBPCI_H
11099 +#define _SBPCI_H
11100 +
11101 +/* cpp contortions to concatenate w/arg prescan */
11102 +#ifndef PAD
11103 +#define _PADLINE(line) pad ## line
11104 +#define _XSTR(line) _PADLINE(line)
11105 +#define PAD _XSTR(__LINE__)
11106 +#endif
11107 +
11108 +/* Sonics side: PCI core and host control registers */
11109 +typedef struct sbpciregs {
11110 + uint32 control; /* PCI control */
11111 + uint32 PAD[3];
11112 + uint32 arbcontrol; /* PCI arbiter control */
11113 + uint32 PAD[3];
11114 + uint32 intstatus; /* Interrupt status */
11115 + uint32 intmask; /* Interrupt mask */
11116 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
11117 + uint32 PAD[9];
11118 + uint32 bcastaddr; /* Sonics broadcast address */
11119 + uint32 bcastdata; /* Sonics broadcast data */
11120 + uint32 PAD[2];
11121 + uint32 gpioin; /* ro: gpio input (>=rev2) */
11122 + uint32 gpioout; /* rw: gpio output (>=rev2) */
11123 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
11124 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
11125 + uint32 PAD[36];
11126 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
11127 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
11128 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
11129 + uint32 PAD[445];
11130 + uint16 sprom[36]; /* SPROM shadow Area */
11131 + uint32 PAD[46];
11132 +} sbpciregs_t;
11133 +
11134 +/* PCI control */
11135 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
11136 +#define PCI_RST 0x02 /* Value driven out to pin */
11137 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
11138 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
11139 +
11140 +/* PCI arbiter control */
11141 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
11142 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
11143 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
11144 +#define PCI_PARKID_SHIFT 1
11145 +#define PCI_PARKID_LAST 0 /* Last requestor */
11146 +#define PCI_PARKID_4710 1 /* 4710 */
11147 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
11148 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
11149 +
11150 +/* Interrupt status/mask */
11151 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
11152 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
11153 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
11154 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
11155 +#define PCI_PME 0x10 /* PCI PME# is asserted */
11156 +
11157 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
11158 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
11159 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
11160 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
11161 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
11162 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
11163 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
11164 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
11165 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
11166 +
11167 +/* Sonics broadcast address */
11168 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
11169 +
11170 +/* Sonics to PCI translation types */
11171 +#define SBTOPCI0_MASK 0xfc000000
11172 +#define SBTOPCI1_MASK 0xfc000000
11173 +#define SBTOPCI2_MASK 0xc0000000
11174 +#define SBTOPCI_MEM 0
11175 +#define SBTOPCI_IO 1
11176 +#define SBTOPCI_CFG0 2
11177 +#define SBTOPCI_CFG1 3
11178 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
11179 +#define SBTOPCI_BURST 0x8 /* burst enable */
11180 +
11181 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
11182 +#define cap_list rsvd_a[0]
11183 +#define bar0_window dev_dep[0x80 - 0x40]
11184 +#define bar1_window dev_dep[0x84 - 0x40]
11185 +#define sprom_control dev_dep[0x88 - 0x40]
11186 +
11187 +#ifndef _LANGUAGE_ASSEMBLY
11188 +
11189 +extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
11190 +extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
11191 +extern void sbpci_ban(uint16 core);
11192 +extern int sbpci_init(void *sbh);
11193 +extern void sbpci_check(void *sbh);
11194 +
11195 +#endif /* !_LANGUAGE_ASSEMBLY */
11196 +
11197 +#endif /* _SBPCI_H */
11198 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
11199 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
11200 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-09-16 10:29:18.210586472 +0200
11201 @@ -0,0 +1,131 @@
11202 +/*
11203 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
11204 + *
11205 + * $Id$
11206 + * Copyright 2001-2003, Broadcom Corporation
11207 + * All Rights Reserved.
11208 + *
11209 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11210 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11211 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11212 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11213 + */
11214 +
11215 +#ifndef _SBPCMCIA_H
11216 +#define _SBPCMCIA_H
11217 +
11218 +
11219 +/* All the addresses that are offsets in attribute space are divided
11220 + * by two to account for the fact that odd bytes are invalid in
11221 + * attribute space and our read/write routines make the space appear
11222 + * as if they didn't exist. Still we want to show the original numbers
11223 + * as documented in the hnd_pcmcia core manual.
11224 + */
11225 +
11226 +/* PCMCIA Function Configuration Registers */
11227 +#define PCMCIA_FCR (0x700 / 2)
11228 +
11229 +#define FCR0_OFF 0
11230 +#define FCR1_OFF (0x40 / 2)
11231 +#define FCR2_OFF (0x80 / 2)
11232 +#define FCR3_OFF (0xc0 / 2)
11233 +
11234 +#define PCMCIA_FCR0 (0x700 / 2)
11235 +#define PCMCIA_FCR1 (0x740 / 2)
11236 +#define PCMCIA_FCR2 (0x780 / 2)
11237 +#define PCMCIA_FCR3 (0x7c0 / 2)
11238 +
11239 +/* Standard PCMCIA FCR registers */
11240 +
11241 +#define PCMCIA_COR 0
11242 +
11243 +#define COR_RST 0x80
11244 +#define COR_LEV 0x40
11245 +#define COR_IRQEN 0x04
11246 +#define COR_BLREN 0x01
11247 +#define COR_FUNEN 0x01
11248 +
11249 +
11250 +#define PCICIA_FCSR (2 / 2)
11251 +#define PCICIA_PRR (4 / 2)
11252 +#define PCICIA_SCR (6 / 2)
11253 +#define PCICIA_ESR (8 / 2)
11254 +
11255 +
11256 +#define PCM_MEMOFF 0x0000
11257 +#define F0_MEMOFF 0x1000
11258 +#define F1_MEMOFF 0x2000
11259 +#define F2_MEMOFF 0x3000
11260 +#define F3_MEMOFF 0x4000
11261 +
11262 +/* Memory base in the function fcr's */
11263 +#define MEM_ADDR0 (0x728 / 2)
11264 +#define MEM_ADDR1 (0x72a / 2)
11265 +#define MEM_ADDR2 (0x72c / 2)
11266 +
11267 +/* PCMCIA base plus Srom access in fcr0: */
11268 +#define PCMCIA_ADDR0 (0x072e / 2)
11269 +#define PCMCIA_ADDR1 (0x0730 / 2)
11270 +#define PCMCIA_ADDR2 (0x0732 / 2)
11271 +
11272 +#define MEM_SEG (0x0734 / 2)
11273 +#define SROM_CS (0x0736 / 2)
11274 +#define SROM_DATAL (0x0738 / 2)
11275 +#define SROM_DATAH (0x073a / 2)
11276 +#define SROM_ADDRL (0x073c / 2)
11277 +#define SROM_ADDRH (0x073e / 2)
11278 +
11279 +/* Values for srom_cs: */
11280 +#define SROM_IDLE 0
11281 +#define SROM_WRITE 1
11282 +#define SROM_READ 2
11283 +#define SROM_WEN 4
11284 +#define SROM_WDS 7
11285 +#define SROM_DONE 8
11286 +
11287 +/* CIS stuff */
11288 +
11289 +/* The CIS stops where the FCRs start */
11290 +#define CIS_SIZE PCMCIA_FCR
11291 +
11292 +/* Standard tuples we know about */
11293 +
11294 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
11295 +#define CISTPL_FUNCE 0x22 /* Function extensions */
11296 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
11297 +
11298 +/* Function extensions for LANs */
11299 +
11300 +#define LAN_TECH 1 /* Technology type */
11301 +#define LAN_SPEED 2 /* Raw bit rate */
11302 +#define LAN_MEDIA 3 /* Transmission media */
11303 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
11304 +#define LAN_CONN 5 /* Connector standard */
11305 +
11306 +
11307 +/* CFTable */
11308 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
11309 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
11310 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
11311 +
11312 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
11313 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
11314 + */
11315 +
11316 +#define CISTPL_BRCM_HNBU 0x80
11317 +
11318 +/* Subtypes of BRCM_HNBU: */
11319 +
11320 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
11321 + * device id and chiprev
11322 + */
11323 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
11324 +#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
11325 +#define HNBU_OEM 0x04 /* Eight bytes OEM data */
11326 +#define HNBU_CC 0x05 /* Default country code */
11327 +#define HNBU_AA 0x06 /* Antennas available */
11328 +#define HNBU_AG 0x07 /* Antenna gain */
11329 +#define HNBU_BOARDFLAGS 0x08 /* board flags */
11330 +#define HNBU_LED 0x09 /* LED set */
11331 +
11332 +#endif /* _SBPCMCIA_H */
11333 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h
11334 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
11335 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-09-16 10:29:18.210586472 +0200
11336 @@ -0,0 +1,75 @@
11337 +/*
11338 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
11339 + *
11340 + * Copyright 2001-2003, Broadcom Corporation
11341 + * All Rights Reserved.
11342 + *
11343 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11344 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11345 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11346 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11347 + * $Id$
11348 + */
11349 +
11350 +#ifndef _SBSDRAM_H
11351 +#define _SBSDRAM_H
11352 +
11353 +#ifndef _LANGUAGE_ASSEMBLY
11354 +
11355 +/* Sonics side: SDRAM core registers */
11356 +typedef volatile struct sbsdramregs {
11357 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
11358 + uint32 config; /* Initializes external SDRAM mode register */
11359 + uint32 refresh; /* Controls external SDRAM refresh rate */
11360 + uint32 pad1;
11361 + uint32 pad2;
11362 +} sbsdramregs_t;
11363 +
11364 +#endif
11365 +
11366 +/* SDRAM initialization control (initcontrol) register bits */
11367 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
11368 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
11369 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
11370 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
11371 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
11372 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
11373 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
11374 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
11375 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
11376 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
11377 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
11378 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
11379 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
11380 +
11381 +/* SDRAM configuration (config) register bits */
11382 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
11383 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
11384 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
11385 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
11386 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
11387 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
11388 +
11389 +/* SDRAM refresh control (refresh) register bits */
11390 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
11391 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
11392 +
11393 +/* SDRAM Core default Init values (OCP ID 0x803) */
11394 +#define SDRAM_INIT MEM4MX16X2
11395 +#define SDRAM_CONFIG SDRAM_BURSTFULL
11396 +#define SDRAM_REFRESH SDRAM_REF(0x40)
11397 +
11398 +#define MEM1MX16 0x009 /* 2 MB */
11399 +#define MEM1MX16X2 0x409 /* 4 MB */
11400 +#define MEM2MX8X2 0x809 /* 4 MB */
11401 +#define MEM2MX8X4 0xc09 /* 8 MB */
11402 +#define MEM2MX32 0x439 /* 8 MB */
11403 +#define MEM4MX16 0x019 /* 8 MB */
11404 +#define MEM4MX16X2 0x419 /* 16 MB */
11405 +#define MEM8MX8X2 0x819 /* 16 MB */
11406 +#define MEM8MX16 0x829 /* 16 MB */
11407 +#define MEM4MX32 0x429 /* 16 MB */
11408 +#define MEM8MX8X4 0xc19 /* 32 MB */
11409 +#define MEM8MX16X2 0xc29 /* 32 MB */
11410 +
11411 +#endif /* _SBSDRAM_H */
11412 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h
11413 --- linux-2.6.12.5/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
11414 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-09-16 10:29:18.211586320 +0200
11415 @@ -0,0 +1,90 @@
11416 +/*
11417 + * Misc utility routines for accessing chip-specific features
11418 + * of Broadcom HNBU SiliconBackplane-based chips.
11419 + *
11420 + * Copyright 2001-2003, Broadcom Corporation
11421 + * All Rights Reserved.
11422 + *
11423 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11424 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11425 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11426 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11427 + *
11428 + * $Id$
11429 + */
11430 +
11431 +#ifndef _sbutils_h_
11432 +#define _sbutils_h_
11433 +
11434 +/* Board styles (bustype) */
11435 +#define BOARDSTYLE_SOC 0 /* Silicon Backplane */
11436 +#define BOARDSTYLE_PCI 1 /* PCI/MiniPCI board */
11437 +#define BOARDSTYLE_PCMCIA 2 /* PCMCIA board */
11438 +#define BOARDSTYLE_CARDBUS 3 /* Cardbus board */
11439 +
11440 +/*
11441 + * Many of the routines below take an 'sbh' handle as their first arg.
11442 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
11443 + * At any one time, the sbh is logically focused on one particular sb core
11444 + * (the "current core").
11445 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
11446 + */
11447 +
11448 +/* exported externs */
11449 +extern void *sb_attach(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
11450 +extern void *sb_kattach(void);
11451 +extern void sb_detach(void *sbh);
11452 +extern uint sb_chip(void *sbh);
11453 +extern uint sb_chiprev(void *sbh);
11454 +extern uint sb_chippkg(void *sbh);
11455 +extern uint sb_boardvendor(void *sbh);
11456 +extern uint sb_boardtype(void *sbh);
11457 +extern uint sb_boardstyle(void *sbh);
11458 +extern uint sb_bus(void *sbh);
11459 +extern uint sb_corelist(void *sbh, uint coreid[]);
11460 +extern uint sb_coreid(void *sbh);
11461 +extern uint sb_coreidx(void *sbh);
11462 +extern uint sb_coreunit(void *sbh);
11463 +extern uint sb_corevendor(void *sbh);
11464 +extern uint sb_corerev(void *sbh);
11465 +extern void *sb_coreregs(void *sbh);
11466 +extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
11467 +extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
11468 +extern bool sb_iscoreup(void *sbh);
11469 +extern void *sb_setcoreidx(void *sbh, uint coreidx);
11470 +extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
11471 +extern void sb_commit(void *sbh);
11472 +extern uint32 sb_base(uint32 admatch);
11473 +extern uint32 sb_size(uint32 admatch);
11474 +extern void sb_core_reset(void *sbh, uint32 bits);
11475 +extern void sb_core_tofixup(void *sbh);
11476 +extern void sb_core_disable(void *sbh, uint32 bits);
11477 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
11478 +extern uint32 sb_clock(void *sbh);
11479 +extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
11480 +extern void sb_pcmcia_init(void *sbh);
11481 +extern void sb_watchdog(void *sbh, uint ticks);
11482 +extern void *sb_gpiosetcore(void *sbh);
11483 +extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
11484 +extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
11485 +extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
11486 +extern uint32 sb_gpioin(void *sbh);
11487 +extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
11488 +extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
11489 +extern bool sb_taclear(void *sbh);
11490 +extern void sb_pwrctl_init(void *sbh);
11491 +extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
11492 +extern bool sb_pwrctl_clk(void *sbh, uint mode);
11493 +extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
11494 +extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intr_arg);
11495 +
11496 +/* pwrctl xtal what flags */
11497 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
11498 +#define PLL 0x2 /* main chip pll */
11499 +
11500 +/* pwrctl clk mode */
11501 +#define CLK_FAST 0 /* force fast (pll) clock */
11502 +#define CLK_SLOW 1 /* force slow clock */
11503 +#define CLK_DYNAMIC 2 /* enable dynamic power control */
11504 +
11505 +#endif /* _sbutils_h_ */
11506 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h
11507 --- linux-2.6.12.5/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
11508 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-09-16 10:29:18.211586320 +0200
11509 @@ -0,0 +1,31 @@
11510 +/*
11511 + * TRX image file header format.
11512 + *
11513 + * Copyright 2001-2003, Broadcom Corporation
11514 + * All Rights Reserved.
11515 + *
11516 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11517 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11518 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11519 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11520 + *
11521 + * $Id$
11522 + */
11523 +
11524 +#include <typedefs.h>
11525 +
11526 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
11527 +#define TRX_VERSION 1
11528 +#define TRX_MAX_LEN 0x3A0000
11529 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
11530 +
11531 +struct trx_header {
11532 + uint32 magic; /* "HDR0" */
11533 + uint32 len; /* Length of file including header */
11534 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
11535 + uint32 flag_version; /* 0:15 flags, 16:31 version */
11536 + uint32 offsets[3]; /* Offsets of partitions from start of header */
11537 +};
11538 +
11539 +/* Compatibility */
11540 +typedef struct trx_header TRXHDR, *PTRXHDR;
11541 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h
11542 --- linux-2.6.12.5/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
11543 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-09-16 10:29:18.212586168 +0200
11544 @@ -0,0 +1,162 @@
11545 +/*
11546 + * Copyright 2001-2003, Broadcom Corporation
11547 + * All Rights Reserved.
11548 + *
11549 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11550 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11551 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11552 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11553 + * $Id$
11554 + */
11555 +
11556 +#ifndef _TYPEDEFS_H_
11557 +#define _TYPEDEFS_H_
11558 +
11559 +/*----------------------- define TRUE, FALSE, NULL, bool ----------------*/
11560 +#ifdef __cplusplus
11561 +
11562 +#ifndef FALSE
11563 +#define FALSE false
11564 +#endif
11565 +#ifndef TRUE
11566 +#define TRUE true
11567 +#endif
11568 +
11569 +#else /* !__cplusplus */
11570 +
11571 +#if defined(_WIN32)
11572 +
11573 +typedef unsigned char bool;
11574 +
11575 +#else
11576 +
11577 +#if defined(MACOSX) && defined(KERNEL)
11578 +#include <IOKit/IOTypes.h>
11579 +#else
11580 +typedef int bool;
11581 +#endif
11582 +
11583 +#endif
11584 +
11585 +#ifndef FALSE
11586 +#define FALSE 0
11587 +#endif
11588 +#ifndef TRUE
11589 +#define TRUE 1
11590 +
11591 +#ifndef NULL
11592 +#define NULL 0
11593 +#endif
11594 +
11595 +#endif
11596 +
11597 +#endif /* __cplusplus */
11598 +
11599 +#ifndef OFF
11600 +#define OFF 0
11601 +#endif
11602 +
11603 +#ifndef ON
11604 +#define ON 1
11605 +#endif
11606 +
11607 +/*----------------------- define uchar, ushort, uint, ulong ----------------*/
11608 +
11609 +typedef unsigned char uchar;
11610 +
11611 +#if defined(_WIN32) || defined(PMON) || defined(__MRC__) || defined(V2_HAL) || defined(_CFE_)
11612 +
11613 +#ifndef V2_HAL
11614 +typedef unsigned short ushort;
11615 +#endif
11616 +
11617 +typedef unsigned int uint;
11618 +typedef unsigned long ulong;
11619 +
11620 +#else
11621 +
11622 +/* pick up ushort & uint from standard types.h */
11623 +#if defined(linux) && defined(__KERNEL__)
11624 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
11625 +#else
11626 +#include <sys/types.h>
11627 +#if !defined(TARGETENV_sun4) && !defined(linux)
11628 +typedef unsigned long ulong;
11629 +#endif /* TARGETENV_sun4 */
11630 +#endif
11631 +#if defined(PMON)
11632 +typedef unsigned int uint;
11633 +typedef unsigned long long uint64;
11634 +#endif
11635 +
11636 +#endif /* WIN32 || PMON || .. */
11637 +
11638 +/*----------------------- define [u]int8/16/32/64 --------------------------*/
11639 +
11640 +
11641 +#ifdef V2_HAL
11642 +#include <bcmos.h>
11643 +#else
11644 +typedef signed char int8;
11645 +typedef signed short int16;
11646 +typedef signed int int32;
11647 +
11648 +typedef unsigned char uint8;
11649 +typedef unsigned short uint16;
11650 +typedef unsigned int uint32;
11651 +#endif /* V2_HAL */
11652 +
11653 +typedef float float32;
11654 +typedef double float64;
11655 +
11656 +/*
11657 + * abstracted floating point type allows for compile time selection of
11658 + * single or double precision arithmetic. Compiling with -DFLOAT32
11659 + * selects single precision; the default is double precision.
11660 + */
11661 +
11662 +#if defined(FLOAT32)
11663 +typedef float32 float_t;
11664 +#else /* default to double precision floating point */
11665 +typedef float64 float_t;
11666 +#endif /* FLOAT32 */
11667 +
11668 +#ifdef _MSC_VER /* Microsoft C */
11669 +typedef signed __int64 int64;
11670 +typedef unsigned __int64 uint64;
11671 +
11672 +#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
11673 +/* gcc understands signed/unsigned 64 bit types, but complains in ANSI mode */
11674 +typedef signed long long int64;
11675 +typedef unsigned long long uint64;
11676 +
11677 +#elif defined(__ICL) && !defined(__STDC__)
11678 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode */
11679 +typedef unsigned long long uint64;
11680 +
11681 +#endif /* _MSC_VER */
11682 +
11683 +
11684 +/*----------------------- define PTRSZ, INLINE --------------------------*/
11685 +
11686 +#define PTRSZ sizeof (char*)
11687 +
11688 +#ifndef INLINE
11689 +
11690 +#ifdef _MSC_VER
11691 +
11692 +#define INLINE __inline
11693 +
11694 +#elif __GNUC__
11695 +
11696 +#define INLINE __inline__
11697 +
11698 +#else
11699 +
11700 +#define INLINE
11701 +
11702 +#endif /* _MSC_VER */
11703 +
11704 +#endif /* INLINE */
11705 +
11706 +#endif /* _TYPEDEFS_H_ */
11707 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h
11708 --- linux-2.6.12.5/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
11709 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-09-16 10:29:18.213586016 +0200
11710 @@ -0,0 +1,690 @@
11711 +/*
11712 + * Custom OID/ioctl definitions for
11713 + * Broadcom 802.11abg Networking Device Driver
11714 + *
11715 + * Definitions subject to change without notice.
11716 + *
11717 + * Copyright 2001-2003, Broadcom Corporation
11718 + * All Rights Reserved.
11719 + *
11720 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11721 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11722 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11723 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11724 + *
11725 + * $Id$
11726 + */
11727 +
11728 +#ifndef _wlioctl_h_
11729 +#define _wlioctl_h_
11730 +
11731 +#include <typedefs.h>
11732 +#include <proto/ethernet.h>
11733 +#include <proto/802.11.h>
11734 +
11735 +#if defined(__GNUC__)
11736 +#define PACKED __attribute__((packed))
11737 +#else
11738 +#define PACKED
11739 +#endif
11740 +
11741 +/*
11742 + * Per-bss information structure.
11743 + */
11744 +
11745 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
11746 +
11747 +typedef struct wl_rateset {
11748 + uint32 count; /* # rates in this set */
11749 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
11750 +} wl_rateset_t;
11751 +
11752 +#define WL_LEGACY_BSS_INFO_VERSION 106 /* an older supported version of wl_bss_info struct */
11753 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
11754 +
11755 +typedef struct wl_bss_info106 {
11756 + uint version; /* version field */
11757 + struct ether_addr BSSID;
11758 + uint8 SSID_len;
11759 + uint8 SSID[32];
11760 + uint8 Privacy; /* 0=No WEP, 1=Use WEP */
11761 + int16 RSSI; /* receive signal strength (in dBm) */
11762 + uint16 beacon_period; /* units are Kusec */
11763 + uint16 atim_window; /* units are Kusec */
11764 + uint8 channel; /* Channel no. */
11765 + int8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
11766 + struct {
11767 + uint count; /* # rates in this set */
11768 + uint8 rates[12]; /* rates in 500kbps units w/hi bit set if basic */
11769 + } rateset; /* supported rates */
11770 + uint8 dtim_period; /* DTIM period */
11771 + int8 phy_noise; /* noise right after tx (in dBm) */
11772 + uint16 capability; /* Capability information */
11773 + struct dot11_bcn_prb *prb; /* probe response frame (ioctl na) */
11774 + uint16 prb_len; /* probe response frame length (ioctl na) */
11775 + struct {
11776 + uint8 supported; /* wpa supported */
11777 + uint8 multicast; /* multicast cipher */
11778 + uint8 ucount; /* count of unicast ciphers */
11779 + uint8 unicast[4]; /* unicast ciphers */
11780 + uint8 acount; /* count of auth modes */
11781 + uint8 auth[4]; /* Authentication modes */
11782 + } wpa;
11783 +} wl_bss_info106_t;
11784 +
11785 +typedef struct wl_bss_info {
11786 + uint32 version; /* version field */
11787 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
11788 + struct ether_addr BSSID;
11789 + uint16 beacon_period; /* units are Kusec */
11790 + uint16 capability; /* Capability information */
11791 + uint8 SSID_len;
11792 + uint8 SSID[32];
11793 + struct {
11794 + uint count; /* # rates in this set */
11795 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
11796 + } rateset; /* supported rates */
11797 + uint8 channel; /* Channel no. */
11798 + uint16 atim_window; /* units are Kusec */
11799 + uint8 dtim_period; /* DTIM period */
11800 + int16 RSSI; /* receive signal strength (in dBm) */
11801 + int8 phy_noise; /* noise (in dBm) */
11802 + uint32 ie_length; /* byte length of Information Elements */
11803 + /* variable length Information Elements */
11804 +} wl_bss_info_t;
11805 +
11806 +typedef struct wl_scan_results {
11807 + uint32 buflen;
11808 + uint32 version;
11809 + uint32 count;
11810 + wl_bss_info_t bss_info[1];
11811 +} wl_scan_results_t;
11812 +/* size of wl_scan_results not including variable length array */
11813 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
11814 +
11815 +/* uint32 list */
11816 +typedef struct wl_uint32_list {
11817 + /* in - # of elements, out - # of entries */
11818 + uint32 count;
11819 + /* variable length uint32 list */
11820 + uint32 element[1];
11821 +} wl_uint32_list_t;
11822 +
11823 +typedef struct wlc_ssid {
11824 + uint32 SSID_len;
11825 + uchar SSID[32];
11826 +} wlc_ssid_t;
11827 +
11828 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
11829 +
11830 +typedef struct wl_channels_in_country {
11831 + uint32 buflen;
11832 + uint32 band;
11833 + char country_abbrev[WLC_CNTRY_BUF_SZ];
11834 + uint32 count;
11835 + uint32 channel[1];
11836 +} wl_channels_in_country_t;
11837 +
11838 +typedef struct wl_country_list {
11839 + uint32 buflen;
11840 + uint32 band_set;
11841 + uint32 band;
11842 + uint32 count;
11843 + char country_abbrev[1];
11844 +} wl_country_list_t;
11845 +
11846 +
11847 +/*
11848 +* Maximum # of keys that wl driver supports in S/W. Keys supported
11849 +* in H/W is less than or equal to WSEC_MAX_KEYS.
11850 +*/
11851 +#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
11852 +#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
11853 +
11854 +/*
11855 +* Remove these two defines if access to crypto/tkhash.h
11856 +* is unconditionally permitted.
11857 +*/
11858 +#define TKHASH_P1_KEY_SIZE 10 /* size of TKHash Phase1 output, in bytes */
11859 +#define TKHASH_P2_KEY_SIZE 16 /* size of TKHash Phase2 output */
11860 +
11861 +/* Enumerate crypto algorithms */
11862 +#define CRYPTO_ALGO_OFF 0
11863 +#define CRYPTO_ALGO_WEP1 1
11864 +#define CRYPTO_ALGO_TKIP 2
11865 +#define CRYPTO_ALGO_WEP128 3
11866 +#define CRYPTO_ALGO_AES_CCM 4
11867 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
11868 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
11869 +#define CRYPTO_ALGO_NALG 7
11870 +
11871 +/* For use with wlc_wep_key.flags */
11872 +#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
11873 +#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
11874 +#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
11875 +
11876 +#define WSEC_GEN_MIC_ERROR 0x0001
11877 +#define WSEC_GEN_REPLAY 0x0002
11878 +
11879 +typedef struct tkip_info {
11880 + uint16 phase1[TKHASH_P1_KEY_SIZE/sizeof(uint16)]; /* tkhash phase1 result */
11881 + uint8 phase2[TKHASH_P2_KEY_SIZE]; /* tkhash phase2 result */
11882 + uint32 micl;
11883 + uint32 micr;
11884 +} tkip_info_t;
11885 +
11886 +typedef struct wsec_iv {
11887 + uint32 hi; /* upper 32 bits of IV */
11888 + uint16 lo; /* lower 16 bits of IV */
11889 +} wsec_iv_t;
11890 +
11891 +typedef struct wsec_key {
11892 + uint32 index; /* key index */
11893 + uint32 len; /* key length */
11894 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
11895 + tkip_info_t tkip_tx; /* tkip transmit state */
11896 + tkip_info_t tkip_rx; /* tkip receive state */
11897 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
11898 + uint32 flags; /* misc flags */
11899 + uint32 algo_hw; /* cache for hw register*/
11900 + uint32 aes_mode; /* cache for hw register*/
11901 + int iv_len; /* IV length */
11902 + int iv_initialized; /* has IV been initialized already? */
11903 + int icv_len; /* ICV length */
11904 + wsec_iv_t rxiv; /* Rx IV */
11905 + wsec_iv_t txiv; /* Tx IV */
11906 + struct ether_addr ea; /* per station */
11907 +} wsec_key_t;
11908 +
11909 +/* wireless security bitvec */
11910 +#define WEP_ENABLED 1
11911 +#define TKIP_ENABLED 2
11912 +#define AES_ENABLED 4
11913 +#define WSEC_SWFLAG 8
11914 +
11915 +#define WSEC_SW(wsec) ((wsec) & WSEC_SWFLAG)
11916 +#define WSEC_HW(wsec) (!WSEC_SW(wsec))
11917 +#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
11918 +#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
11919 +#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
11920 +#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
11921 +
11922 +/* wireless authentication bit vector */
11923 +#define WPA_ENABLED 1
11924 +#define PSK_ENABLED 2
11925 +
11926 +#define WAUTH_WPA_ENABLED(wauth) ((wauth) & WPA_ENABLED)
11927 +#define WAUTH_PSK_ENABLED(wauth) ((wauth) & PSK_ENABLED)
11928 +#define WAUTH_ENABLED(wauth) ((wauth) & (WPA_ENABLED | PSK_ENABLED))
11929 +
11930 +/* group/mcast cipher */
11931 +#define WPA_MCAST_CIPHER(wsec) (((wsec) & TKIP_ENABLED) ? WPA_CIPHER_TKIP : \
11932 + ((wsec) & AES_ENABLED) ? WPA_CIPHER_AES_CCM : \
11933 + WPA_CIPHER_NONE)
11934 +
11935 +typedef struct wl_led_info {
11936 + uint32 index; /* led index */
11937 + uint32 behavior;
11938 + bool activehi;
11939 +} wl_led_info_t;
11940 +
11941 +/*
11942 + * definitions for driver messages passed from WL to NAS.
11943 + */
11944 +/* Use this to recognize wpa and 802.1x driver messages. */
11945 +static const uint8 wl_wpa_snap_template[] =
11946 + { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
11947 +
11948 +#define WL_WPA_MSG_IFNAME_MAX 16
11949 +
11950 +/* WPA driver message */
11951 +typedef struct wl_wpa_header {
11952 + struct ether_header eth;
11953 + struct dot11_llc_snap_header snap;
11954 + uint8 version;
11955 + uint8 type;
11956 + /* version 2 additions */
11957 + char ifname[WL_WPA_MSG_IFNAME_MAX];
11958 + /* version specific data */
11959 + /* uint8 data[1]; */
11960 +} wl_wpa_header_t PACKED;
11961 +
11962 +#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
11963 +
11964 +/* WPA driver message ethertype - private between wlc and nas */
11965 +#define WL_WPA_ETHER_TYPE 0x9999
11966 +
11967 +/* WPA driver message current version */
11968 +#define WL_WPA_MSG_VERSION 2
11969 +
11970 +/* Type field values for the 802.2 driver messages for WPA. */
11971 +#define WLC_ASSOC_MSG 1
11972 +#define WLC_DISASSOC_MSG 2
11973 +#define WLC_PTK_MIC_MSG 3
11974 +#define WLC_GTK_MIC_MSG 4
11975 +
11976 +/* 802.1x driver message */
11977 +typedef struct wl_eapol_header {
11978 + struct ether_header eth;
11979 + struct dot11_llc_snap_header snap;
11980 + uint8 version;
11981 + uint8 reserved;
11982 + char ifname[WL_WPA_MSG_IFNAME_MAX];
11983 + /* version specific data */
11984 + /* uint8 802_1x_msg[1]; */
11985 +} wl_eapol_header_t PACKED;
11986 +
11987 +#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
11988 +
11989 +/* 802.1x driver message ethertype - private between wlc and nas */
11990 +#define WL_EAPOL_ETHER_TYPE 0x999A
11991 +
11992 +/* 802.1x driver message current version */
11993 +#define WL_EAPOL_MSG_VERSION 1
11994 +
11995 +/* srom read/write struct passed through ioctl */
11996 +typedef struct {
11997 + uint byteoff; /* byte offset */
11998 + uint nbytes; /* number of bytes */
11999 + uint16 buf[1];
12000 +} srom_rw_t;
12001 +
12002 +/* R_REG and W_REG struct passed through ioctl */
12003 +typedef struct {
12004 + uint32 byteoff; /* byte offset of the field in d11regs_t */
12005 + uint32 val; /* read/write value of the field */
12006 + uint32 size; /* sizeof the field */
12007 +} rw_reg_t;
12008 +
12009 +/* Structure used by GET/SET_ATTEN ioctls */
12010 +typedef struct {
12011 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
12012 + uint16 bb; /* Baseband attenuation */
12013 + uint16 radio; /* Radio attenuation */
12014 + uint16 txctl1; /* Radio TX_CTL1 value */
12015 +} atten_t;
12016 +
12017 +/* Used to get specific STA parameters */
12018 +typedef struct {
12019 + uint32 val;
12020 + struct ether_addr ea;
12021 +} scb_val_t;
12022 +
12023 +/* callback registration data types */
12024 +
12025 +typedef struct _mac_event_params {
12026 + uint msg;
12027 + struct ether_addr *addr;
12028 + uint result;
12029 + uint status;
12030 + uint auth_type;
12031 +} mac_event_params_t;
12032 +
12033 +typedef struct _mic_error_params {
12034 + struct ether_addr *ea;
12035 + bool group;
12036 + bool flush_txq;
12037 +} mic_error_params_t;
12038 +
12039 +typedef enum _wl_callback {
12040 + WL_MAC_EVENT_CALLBACK = 0,
12041 + WL_LINK_UP_CALLBACK,
12042 + WL_LINK_DOWN_CALLBACK,
12043 + WL_MIC_ERROR_CALLBACK,
12044 + WL_LAST_CALLBACK
12045 +} wl_callback_t;
12046 +
12047 +typedef struct _callback {
12048 + void (*fn)(void *, void *);
12049 + void *context;
12050 +} callback_t;
12051 +
12052 +typedef struct _scan_callback {
12053 + void (*fn)(void *);
12054 + void *context;
12055 +} scan_callback_t;
12056 +
12057 +/* used to register an arbitrary callback via the IOCTL interface */
12058 +typedef struct _set_callback {
12059 + int index;
12060 + callback_t callback;
12061 +} set_callback_t;
12062 +
12063 +/*
12064 + * Country locale determines which channels are available to us.
12065 + */
12066 +typedef enum _wlc_locale {
12067 + WLC_WW = 0, /* Worldwide */
12068 + WLC_THA, /* Thailand */
12069 + WLC_ISR, /* Israel */
12070 + WLC_JDN, /* Jordan */
12071 + WLC_PRC, /* China */
12072 + WLC_JPN, /* Japan */
12073 + WLC_FCC, /* USA */
12074 + WLC_EUR, /* Europe */
12075 + WLC_USL, /* US Low Band only */
12076 + WLC_JPH, /* Japan High Band only */
12077 + WLC_ALL, /* All the channels in this band */
12078 + WLC_11D, /* Represents locale recieved by 11d beacons */
12079 + WLC_LAST_LOCALE,
12080 + WLC_UNDEFINED_LOCALE = 0xf
12081 +} wlc_locale_t;
12082 +
12083 +/* channel encoding */
12084 +typedef struct channel_info {
12085 + int hw_channel;
12086 + int target_channel;
12087 + int scan_channel;
12088 +} channel_info_t;
12089 +
12090 +/* For ioctls that take a list of MAC addresses */
12091 +struct maclist {
12092 + uint count; /* number of MAC addresses */
12093 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
12094 +};
12095 +
12096 +/* get pkt count struct passed through ioctl */
12097 +typedef struct get_pktcnt {
12098 + uint rx_good_pkt;
12099 + uint rx_bad_pkt;
12100 + uint tx_good_pkt;
12101 + uint tx_bad_pkt;
12102 +} get_pktcnt_t;
12103 +
12104 +/* Linux network driver ioctl encoding */
12105 +typedef struct wl_ioctl {
12106 + int cmd; /* common ioctl definition */
12107 + void *buf; /* pointer to user buffer */
12108 + int len; /* length of user buffer */
12109 +} wl_ioctl_t;
12110 +
12111 +/*
12112 + * Structure for passing hardware and software
12113 + * revision info up from the driver.
12114 + */
12115 +typedef struct wlc_rev_info {
12116 + uint vendorid; /* PCI vendor id */
12117 + uint deviceid; /* device id of chip */
12118 + uint radiorev; /* radio revision */
12119 + uint chiprev; /* chip revision */
12120 + uint corerev; /* core revision */
12121 + uint boardid; /* board identifier (usu. PCI sub-device id) */
12122 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
12123 + uint boardrev; /* board revision */
12124 + uint driverrev; /* driver version */
12125 + uint ucoderev; /* microcode version */
12126 + uint bus; /* bus type */
12127 + uint chipnum; /* chip number */
12128 +} wlc_rev_info_t;
12129 +
12130 +/* check this magic number */
12131 +#define WLC_IOCTL_MAGIC 0x14e46c77
12132 +
12133 +/* bump this number if you change the ioctl interface */
12134 +#define WLC_IOCTL_VERSION 1
12135 +
12136 +/* maximum length buffer required */
12137 +#define WLC_IOCTL_MAXLEN 8192
12138 +
12139 +/* common ioctl definitions */
12140 +#define WLC_GET_MAGIC 0
12141 +#define WLC_GET_VERSION 1
12142 +#define WLC_UP 2
12143 +#define WLC_DOWN 3
12144 +#define WLC_DUMP 6
12145 +#define WLC_GET_MSGLEVEL 7
12146 +#define WLC_SET_MSGLEVEL 8
12147 +#define WLC_GET_PROMISC 9
12148 +#define WLC_SET_PROMISC 10
12149 +#define WLC_GET_RATE 12
12150 +#define WLC_SET_RATE 13
12151 +#define WLC_GET_INSTANCE 14
12152 +#define WLC_GET_FRAG 15
12153 +#define WLC_SET_FRAG 16
12154 +#define WLC_GET_RTS 17
12155 +#define WLC_SET_RTS 18
12156 +#define WLC_GET_INFRA 19
12157 +#define WLC_SET_INFRA 20
12158 +#define WLC_GET_AUTH 21
12159 +#define WLC_SET_AUTH 22
12160 +#define WLC_GET_BSSID 23
12161 +#define WLC_SET_BSSID 24
12162 +#define WLC_GET_SSID 25
12163 +#define WLC_SET_SSID 26
12164 +#define WLC_RESTART 27
12165 +#define WLC_GET_CHANNEL 29
12166 +#define WLC_SET_CHANNEL 30
12167 +#define WLC_GET_SRL 31
12168 +#define WLC_SET_SRL 32
12169 +#define WLC_GET_LRL 33
12170 +#define WLC_SET_LRL 34
12171 +#define WLC_GET_PLCPHDR 35
12172 +#define WLC_SET_PLCPHDR 36
12173 +#define WLC_GET_RADIO 37
12174 +#define WLC_SET_RADIO 38
12175 +#define WLC_GET_PHYTYPE 39
12176 +#define WLC_GET_WEP 42
12177 +#define WLC_SET_WEP 43
12178 +#define WLC_GET_KEY 44
12179 +#define WLC_SET_KEY 45
12180 +#define WLC_SCAN 50
12181 +#define WLC_SCAN_RESULTS 51
12182 +#define WLC_DISASSOC 52
12183 +#define WLC_REASSOC 53
12184 +#define WLC_GET_ROAM_TRIGGER 54
12185 +#define WLC_SET_ROAM_TRIGGER 55
12186 +#define WLC_GET_TXANT 61
12187 +#define WLC_SET_TXANT 62
12188 +#define WLC_GET_ANTDIV 63
12189 +#define WLC_SET_ANTDIV 64
12190 +#define WLC_GET_TXPWR 65
12191 +#define WLC_SET_TXPWR 66
12192 +#define WLC_GET_CLOSED 67
12193 +#define WLC_SET_CLOSED 68
12194 +#define WLC_GET_MACLIST 69
12195 +#define WLC_SET_MACLIST 70
12196 +#define WLC_GET_RATESET 71
12197 +#define WLC_SET_RATESET 72
12198 +#define WLC_GET_LOCALE 73
12199 +#define WLC_SET_LOCALE 74
12200 +#define WLC_GET_BCNPRD 75
12201 +#define WLC_SET_BCNPRD 76
12202 +#define WLC_GET_DTIMPRD 77
12203 +#define WLC_SET_DTIMPRD 78
12204 +#define WLC_GET_SROM 79
12205 +#define WLC_SET_SROM 80
12206 +#define WLC_GET_WEP_RESTRICT 81
12207 +#define WLC_SET_WEP_RESTRICT 82
12208 +#define WLC_GET_COUNTRY 83
12209 +#define WLC_SET_COUNTRY 84
12210 +#define WLC_GET_REVINFO 98
12211 +#define WLC_GET_MACMODE 105
12212 +#define WLC_SET_MACMODE 106
12213 +#define WLC_GET_GMODE 109
12214 +#define WLC_SET_GMODE 110
12215 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
12216 +#define WLC_GET_SCANSUPPRESS 115
12217 +#define WLC_SET_SCANSUPPRESS 116
12218 +#define WLC_GET_AP 117
12219 +#define WLC_SET_AP 118
12220 +#define WLC_GET_EAP_RESTRICT 119
12221 +#define WLC_SET_EAP_RESTRICT 120
12222 +#define WLC_GET_WDSLIST 123
12223 +#define WLC_SET_WDSLIST 124
12224 +#define WLC_GET_RSSI 127
12225 +#define WLC_GET_WSEC 133
12226 +#define WLC_SET_WSEC 134
12227 +#define WLC_GET_BSS_INFO 136
12228 +#define WLC_GET_LAZYWDS 138
12229 +#define WLC_SET_LAZYWDS 139
12230 +#define WLC_GET_BANDLIST 140
12231 +#define WLC_GET_BAND 141
12232 +#define WLC_SET_BAND 142
12233 +#define WLC_GET_SHORTSLOT 144
12234 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
12235 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
12236 +#define WLC_GET_SHORTSLOT_RESTRICT 147
12237 +#define WLC_SET_SHORTSLOT_RESTRICT 148
12238 +#define WLC_GET_GMODE_PROTECTION 149
12239 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
12240 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
12241 +#define WLC_UPGRADE 152
12242 +#define WLC_GET_ASSOCLIST 159
12243 +#define WLC_GET_CLK 160
12244 +#define WLC_SET_CLK 161
12245 +#define WLC_GET_UP 162
12246 +#define WLC_OUT 163
12247 +#define WLC_GET_WPA_AUTH 164
12248 +#define WLC_SET_WPA_AUTH 165
12249 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
12250 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
12251 +#define WLC_GET_PHYLIST 180
12252 +#define WLC_GET_GMODE_PROTECTION_CTS 198
12253 +#define WLC_SET_GMODE_PROTECTION_CTS 199
12254 +#define WLC_GET_PIOMODE 203
12255 +#define WLC_SET_PIOMODE 204
12256 +#define WLC_SET_LED 209
12257 +#define WLC_GET_LED 210
12258 +#define WLC_GET_CHANNEL_SEL 215
12259 +#define WLC_START_CHANNEL_SEL 216
12260 +#define WLC_GET_VALID_CHANNELS 217
12261 +#define WLC_GET_FAKEFRAG 218
12262 +#define WLC_SET_FAKEFRAG 219
12263 +#define WLC_GET_WET 230
12264 +#define WLC_SET_WET 231
12265 +#define WLC_GET_KEY_PRIMARY 235
12266 +#define WLC_SET_KEY_PRIMARY 236
12267 +#define WLC_SCAN_WITH_CALLBACK 240
12268 +#define WLC_SET_CS_SCAN_TIMER 248
12269 +#define WLC_GET_CS_SCAN_TIMER 249
12270 +#define WLC_CURRENT_PWR 256
12271 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
12272 +#define WLC_GET_COUNTRY_LIST 261
12273 +#define WLC_NVRAM_GET 264
12274 +#define WLC_NVRAM_SET 265
12275 +#define WLC_LAST 271 /* bump after adding */
12276 +
12277 +/*
12278 + * Minor kludge alert:
12279 + * Duplicate a few definitions that irelay requires from epiioctl.h here
12280 + * so caller doesn't have to include this file and epiioctl.h .
12281 + * If this grows any more, it would be time to move these irelay-specific
12282 + * definitions out of the epiioctl.h and into a separate driver common file.
12283 + */
12284 +#ifndef EPICTRL_COOKIE
12285 +#define EPICTRL_COOKIE 0xABADCEDE
12286 +#endif
12287 +
12288 +/* vx wlc ioctl's offset */
12289 +#define CMN_IOCTL_OFF 0x180
12290 +
12291 +/*
12292 + * custom OID support
12293 + *
12294 + * 0xFF - implementation specific OID
12295 + * 0xE4 - first byte of Broadcom PCI vendor ID
12296 + * 0x14 - second byte of Broadcom PCI vendor ID
12297 + * 0xXX - the custom OID number
12298 + */
12299 +
12300 +/* begin 0x1f values beyond the start of the ET driver range. */
12301 +#define WL_OID_BASE 0xFFE41420
12302 +
12303 +/* NDIS overrides */
12304 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
12305 +
12306 +#define WL_DECRYPT_STATUS_SUCCESS 1
12307 +#define WL_DECRYPT_STATUS_FAILURE 2
12308 +#define WL_DECRYPT_STATUS_UNKNOWN 3
12309 +
12310 +/* allows user-mode app to poll the status of USB image upgrade */
12311 +#define WLC_UPGRADE_SUCCESS 0
12312 +#define WLC_UPGRADE_PENDING 1
12313 +
12314 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
12315 +#define WL_RADIO_SW_DISABLE (1<<0)
12316 +#define WL_RADIO_HW_DISABLE (1<<1)
12317 +
12318 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
12319 +#define WL_TXPWR_OVERRIDE (1<<31)
12320 +
12321 +
12322 +/* Bus types */
12323 +#define WL_SB_BUS 0 /* Silicon Backplane */
12324 +#define WL_PCI_BUS 1 /* PCI target */
12325 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
12326 +
12327 +/* band types */
12328 +#define WLC_BAND_AUTO 0 /* auto-select */
12329 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
12330 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
12331 +
12332 +/* MAC list modes */
12333 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
12334 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
12335 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
12336 +
12337 +/*
12338 + *
12339 + */
12340 +#define GMODE_LEGACY_B 0
12341 +#define GMODE_AUTO 1
12342 +#define GMODE_ONLY 2
12343 +#define GMODE_B_DEFERRED 3
12344 +#define GMODE_PERFORMANCE 4
12345 +#define GMODE_LRS 5
12346 +#define GMODE_MAX 6
12347 +
12348 +/* values for PLCPHdr_override */
12349 +#define WLC_PLCP_AUTO -1
12350 +#define WLC_PLCP_SHORT 0
12351 +#define WLC_PLCP_LONG 1
12352 +
12353 +/* values for g_protection_override */
12354 +#define WLC_G_PROTECTION_AUTO -1
12355 +#define WLC_G_PROTECTION_OFF 0
12356 +#define WLC_G_PROTECTION_ON 1
12357 +
12358 +/* values for g_protection_control */
12359 +#define WLC_G_PROTECTION_CTL_OFF 0
12360 +#define WLC_G_PROTECTION_CTL_LOCAL 1
12361 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
12362 +
12363 +
12364 +
12365 +
12366 +
12367 +
12368 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
12369 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
12370 +
12371 +/* led per-pin behaviors */
12372 +#define WL_LED_OFF 0 /* always off */
12373 +#define WL_LED_ON 1 /* always on */
12374 +#define WL_LED_ACTIVITY 2 /* activity */
12375 +#define WL_LED_RADIO 3 /* radio enabled */
12376 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
12377 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
12378 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
12379 +#define WL_LED_WI1 7
12380 +#define WL_LED_WI2 8
12381 +#define WL_LED_WI3 9
12382 +#define WL_LED_ASSOC 10 /* associated state indicator */
12383 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
12384 +#define WL_LED_NUMBEHAVIOR 12
12385 +
12386 +/* led behavior numeric value format */
12387 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
12388 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
12389 +
12390 +
12391 +/* rate check */
12392 +#define WL_RATE_OFDM(r) (((r) & 0x7f) == 12 || ((r) & 0x7f) == 18 || \
12393 + ((r) & 0x7f) == 24 || ((r) & 0x7f) == 36 || \
12394 + ((r) & 0x7f) == 48 || ((r) & 0x7f) == 72 || \
12395 + ((r) & 0x7f) == 96 || ((r) & 0x7f) == 108)
12396 +
12397 +
12398 +#undef PACKED
12399 +
12400 +#endif /* _wlioctl_h_ */
12401 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S
12402 --- linux-2.6.12.5/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
12403 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/int-handler.S 2005-09-16 10:29:18.213586016 +0200
12404 @@ -0,0 +1,48 @@
12405 +/*
12406 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12407 + *
12408 + * This program is free software; you can redistribute it and/or modify it
12409 + * under the terms of the GNU General Public License as published by the
12410 + * Free Software Foundation; either version 2 of the License, or (at your
12411 + * option) any later version.
12412 + *
12413 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12414 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12415 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12416 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12417 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12418 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12419 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12420 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12421 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12422 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12423 + *
12424 + * You should have received a copy of the GNU General Public License along
12425 + * with this program; if not, write to the Free Software Foundation, Inc.,
12426 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12427 + */
12428 +
12429 +#include <asm/asm.h>
12430 +#include <asm/mipsregs.h>
12431 +#include <asm/regdef.h>
12432 +#include <asm/stackframe.h>
12433 +
12434 + .text
12435 + .set noreorder
12436 + .set noat
12437 + .align 5
12438 +
12439 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
12440 + SAVE_ALL
12441 + CLI
12442 +
12443 + .set at
12444 + .set noreorder
12445 +
12446 + jal bcm47xx_irq_dispatch
12447 + move a0, sp
12448 +
12449 + j ret_from_irq
12450 + nop
12451 +
12452 + END(bcm47xx_irq_handler)
12453 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/irq.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c
12454 --- linux-2.6.12.5/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
12455 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/irq.c 2005-09-16 10:29:18.214585864 +0200
12456 @@ -0,0 +1,68 @@
12457 +/*
12458 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12459 + *
12460 + * This program is free software; you can redistribute it and/or modify it
12461 + * under the terms of the GNU General Public License as published by the
12462 + * Free Software Foundation; either version 2 of the License, or (at your
12463 + * option) any later version.
12464 + *
12465 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12466 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12467 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12468 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12469 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12470 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12471 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12472 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12473 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12474 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12475 + *
12476 + * You should have received a copy of the GNU General Public License along
12477 + * with this program; if not, write to the Free Software Foundation, Inc.,
12478 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12479 + */
12480 +
12481 +#include <linux/config.h>
12482 +#include <linux/errno.h>
12483 +#include <linux/init.h>
12484 +#include <linux/interrupt.h>
12485 +#include <linux/irq.h>
12486 +#include <linux/module.h>
12487 +#include <linux/smp.h>
12488 +#include <linux/types.h>
12489 +
12490 +#include <asm/cpu.h>
12491 +#include <asm/io.h>
12492 +#include <asm/irq.h>
12493 +#include <asm/irq_cpu.h>
12494 +#include <asm/gdb-stub.h>
12495 +
12496 +extern asmlinkage void bcm47xx_irq_handler(void);
12497 +
12498 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
12499 +{
12500 + u32 cause;
12501 +
12502 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
12503 +
12504 + clear_c0_status(cause);
12505 +
12506 + if (cause & CAUSEF_IP7)
12507 + do_IRQ(7, regs);
12508 + if (cause & CAUSEF_IP2)
12509 + do_IRQ(2, regs);
12510 + if (cause & CAUSEF_IP3)
12511 + do_IRQ(3, regs);
12512 + if (cause & CAUSEF_IP4)
12513 + do_IRQ(4, regs);
12514 + if (cause & CAUSEF_IP5)
12515 + do_IRQ(5, regs);
12516 + if (cause & CAUSEF_IP6)
12517 + do_IRQ(6, regs);
12518 +}
12519 +
12520 +void __init arch_init_irq(void)
12521 +{
12522 + set_except_vector(0, bcm47xx_irq_handler);
12523 + mips_cpu_irq_init(0);
12524 +}
12525 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/prom.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c
12526 --- linux-2.6.12.5/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
12527 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/prom.c 2005-09-16 10:29:18.214585864 +0200
12528 @@ -0,0 +1,59 @@
12529 +/*
12530 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12531 + *
12532 + * This program is free software; you can redistribute it and/or modify it
12533 + * under the terms of the GNU General Public License as published by the
12534 + * Free Software Foundation; either version 2 of the License, or (at your
12535 + * option) any later version.
12536 + *
12537 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12538 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12539 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12540 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12541 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12542 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12543 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12544 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12545 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12546 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12547 + *
12548 + * You should have received a copy of the GNU General Public License along
12549 + * with this program; if not, write to the Free Software Foundation, Inc.,
12550 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12551 + */
12552 +
12553 +#include <linux/init.h>
12554 +#include <linux/mm.h>
12555 +#include <linux/sched.h>
12556 +#include <linux/bootmem.h>
12557 +
12558 +#include <asm/addrspace.h>
12559 +#include <asm/bootinfo.h>
12560 +#include <asm/pmon.h>
12561 +
12562 +const char *get_system_type(void)
12563 +{
12564 + return "Broadcom BCM47xx";
12565 +}
12566 +
12567 +void __init prom_init(void)
12568 +{
12569 + unsigned long mem;
12570 +
12571 + mips_machgroup = MACH_GROUP_BRCM;
12572 + mips_machtype = MACH_BCM47XX;
12573 +
12574 + /* Figure out memory size by finding aliases */
12575 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
12576 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
12577 + *(unsigned long *)(prom_init))
12578 + break;
12579 + }
12580 +
12581 + add_memory_region(0, mem, BOOT_MEM_RAM);
12582 +}
12583 +
12584 +unsigned long __init prom_free_prom_memory(void)
12585 +{
12586 + return 0;
12587 +}
12588 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/setup.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c
12589 --- linux-2.6.12.5/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
12590 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/setup.c 2005-09-16 10:29:18.215585712 +0200
12591 @@ -0,0 +1,127 @@
12592 +/*
12593 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12594 + *
12595 + * This program is free software; you can redistribute it and/or modify it
12596 + * under the terms of the GNU General Public License as published by the
12597 + * Free Software Foundation; either version 2 of the License, or (at your
12598 + * option) any later version.
12599 + *
12600 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12601 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12602 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12603 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12604 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12605 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12606 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12607 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12608 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12609 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12610 + *
12611 + * You should have received a copy of the GNU General Public License along
12612 + * with this program; if not, write to the Free Software Foundation, Inc.,
12613 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12614 + */
12615 +
12616 +#include <linux/init.h>
12617 +#include <linux/types.h>
12618 +#include <linux/tty.h>
12619 +#include <linux/serial.h>
12620 +#include <linux/serial_core.h>
12621 +#include <linux/serial_reg.h>
12622 +#include <asm/time.h>
12623 +#include <asm/reboot.h>
12624 +
12625 +#include <typedefs.h>
12626 +#include <sbutils.h>
12627 +#include <sbmips.h>
12628 +#include <sbpci.h>
12629 +#include <sbconfig.h>
12630 +#include <bcmdevs.h>
12631 +
12632 +#if 1
12633 +
12634 +#define SER_PORT1(reg) (*((volatile unsigned char *)(0xb8000400+reg)))
12635 +
12636 +int putDebugChar(char c)
12637 +{
12638 + while (!(SER_PORT1(UART_LSR) & UART_LSR_THRE));
12639 + SER_PORT1(UART_TX) = c;
12640 +
12641 + return 1;
12642 +}
12643 +
12644 +char getDebugChar(void)
12645 +{
12646 + while (!(SER_PORT1(UART_LSR) & 1));
12647 + return SER_PORT1(UART_RX);
12648 +}
12649 +
12650 +
12651 +static int ser_line = 0;
12652 +
12653 +static void
12654 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
12655 +{
12656 + struct uart_port s;
12657 +
12658 + memset(&s, 0, sizeof(s));
12659 +
12660 + s.line = ser_line++;
12661 + s.membase = regs;
12662 + s.irq = irq + 2;
12663 + s.uartclk = baud_base;
12664 + s.flags = ASYNC_BOOT_AUTOCONF;
12665 + s.iotype = SERIAL_IO_MEM;
12666 + s.regshift = reg_shift;
12667 +
12668 + if (early_serial_setup(&s) != 0) {
12669 + printk(KERN_ERR "Serial setup failed!\n");
12670 + }
12671 +}
12672 +#endif
12673 +
12674 +extern void bcm47xx_time_init(void);
12675 +extern void bcm47xx_timer_setup(struct irqaction *irq);
12676 +
12677 +void *nvram_get(char *foo)
12678 +{
12679 + return NULL;
12680 +}
12681 +
12682 +void *sbh;
12683 +
12684 +static void bcm47xx_machine_restart(char *command)
12685 +{
12686 + /* Set the watchdog timer to reset immediately */
12687 + local_irq_disable();
12688 + sb_watchdog(sbh, 1);
12689 + while (1);
12690 +}
12691 +
12692 +static void bcm47xx_machine_halt(void)
12693 +{
12694 + /* Disable interrupts and watchdog and spin forever */
12695 + local_irq_disable();
12696 + sb_watchdog(sbh, 0);
12697 + while (1);
12698 +}
12699 +
12700 +static int __init bcm47xx_init(void)
12701 +{
12702 +
12703 + sbh = sb_kattach();
12704 + sb_mips_init(sbh);
12705 + sbpci_init(sbh);
12706 + sb_serial_init(sbh, serial_add);
12707 +
12708 + _machine_restart = bcm47xx_machine_restart;
12709 + _machine_halt = bcm47xx_machine_halt;
12710 + _machine_power_off = bcm47xx_machine_halt;
12711 +
12712 + board_time_init = bcm47xx_time_init;
12713 + board_timer_setup = bcm47xx_timer_setup;
12714 +
12715 + return 0;
12716 +}
12717 +
12718 +early_initcall(bcm47xx_init);
12719 diff -Nur linux-2.6.12.5/arch/mips/bcm947xx/time.c linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c
12720 --- linux-2.6.12.5/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
12721 +++ linux-2.6.12.5-brcm/arch/mips/bcm947xx/time.c 2005-09-16 10:29:18.215585712 +0200
12722 @@ -0,0 +1,59 @@
12723 +/*
12724 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12725 + *
12726 + * This program is free software; you can redistribute it and/or modify it
12727 + * under the terms of the GNU General Public License as published by the
12728 + * Free Software Foundation; either version 2 of the License, or (at your
12729 + * option) any later version.
12730 + *
12731 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12732 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12733 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12734 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
12735 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12736 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
12737 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12738 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12739 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
12740 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12741 + *
12742 + * You should have received a copy of the GNU General Public License along
12743 + * with this program; if not, write to the Free Software Foundation, Inc.,
12744 + * 675 Mass Ave, Cambridge, MA 02139, USA.
12745 + */
12746 +
12747 +#include <linux/config.h>
12748 +#include <linux/init.h>
12749 +#include <linux/kernel.h>
12750 +#include <linux/sched.h>
12751 +#include <linux/serial_reg.h>
12752 +#include <linux/interrupt.h>
12753 +#include <asm/addrspace.h>
12754 +#include <asm/io.h>
12755 +#include <asm/time.h>
12756 +
12757 +void __init
12758 +bcm47xx_time_init(void)
12759 +{
12760 + unsigned int hz;
12761 +
12762 + /*
12763 + * Use deterministic values for initial counter interrupt
12764 + * so that calibrate delay avoids encountering a counter wrap.
12765 + */
12766 + write_c0_count(0);
12767 + write_c0_compare(0xffff);
12768 +
12769 + hz = 200 * 1000 * 1000;
12770 +
12771 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
12772 + mips_hpt_frequency = hz / 2;
12773 +
12774 +}
12775 +
12776 +void __init
12777 +bcm47xx_timer_setup(struct irqaction *irq)
12778 +{
12779 + /* Enable the timer interrupt */
12780 + setup_irq(7, irq);
12781 +}
12782 diff -Nur linux-2.6.12.5/arch/mips/kernel/cpu-probe.c linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c
12783 --- linux-2.6.12.5/arch/mips/kernel/cpu-probe.c 2005-08-15 02:20:18.000000000 +0200
12784 +++ linux-2.6.12.5-brcm/arch/mips/kernel/cpu-probe.c 2005-09-16 10:29:18.243581456 +0200
12785 @@ -555,6 +555,28 @@
12786 }
12787 }
12788
12789 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
12790 +{
12791 + decode_config1(c);
12792 + switch (c->processor_id & 0xff00) {
12793 + case PRID_IMP_BCM3302:
12794 + c->cputype = CPU_BCM3302;
12795 + c->isa_level = MIPS_CPU_ISA_M32;
12796 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12797 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12798 + break;
12799 + case PRID_IMP_BCM4710:
12800 + c->cputype = CPU_BCM4710;
12801 + c->isa_level = MIPS_CPU_ISA_M32;
12802 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12803 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12804 + break;
12805 + default:
12806 + c->cputype = CPU_UNKNOWN;
12807 + break;
12808 + }
12809 +}
12810 +
12811 __init void cpu_probe(void)
12812 {
12813 struct cpuinfo_mips *c = &current_cpu_data;
12814 @@ -577,7 +599,9 @@
12815 case PRID_COMP_SIBYTE:
12816 cpu_probe_sibyte(c);
12817 break;
12818 -
12819 + case PRID_COMP_BROADCOM:
12820 + cpu_probe_broadcom(c);
12821 + break;
12822 case PRID_COMP_SANDCRAFT:
12823 cpu_probe_sandcraft(c);
12824 break;
12825 diff -Nur linux-2.6.12.5/arch/mips/kernel/head.S linux-2.6.12.5-brcm/arch/mips/kernel/head.S
12826 --- linux-2.6.12.5/arch/mips/kernel/head.S 2005-08-15 02:20:18.000000000 +0200
12827 +++ linux-2.6.12.5-brcm/arch/mips/kernel/head.S 2005-09-16 10:29:18.244581304 +0200
12828 @@ -122,6 +122,14 @@
12829 #endif
12830 .endm
12831
12832 +#ifdef CONFIG_BCM4710
12833 +#undef eret
12834 +#define eret nop; nop; eret
12835 +#endif
12836 +
12837 + j kernel_entry
12838 + nop
12839 +
12840 /*
12841 * Reserved space for exception handlers.
12842 * Necessary for machines which link their kernels at KSEG0.
12843 diff -Nur linux-2.6.12.5/arch/mips/kernel/proc.c linux-2.6.12.5-brcm/arch/mips/kernel/proc.c
12844 --- linux-2.6.12.5/arch/mips/kernel/proc.c 2005-08-15 02:20:18.000000000 +0200
12845 +++ linux-2.6.12.5-brcm/arch/mips/kernel/proc.c 2005-09-16 10:29:18.250580392 +0200
12846 @@ -75,7 +75,9 @@
12847 [CPU_VR4133] "NEC VR4133",
12848 [CPU_VR4181] "NEC VR4181",
12849 [CPU_VR4181A] "NEC VR4181A",
12850 - [CPU_SR71000] "Sandcraft SR71000"
12851 + [CPU_SR71000] "Sandcraft SR71000",
12852 + [CPU_BCM3302] "Broadcom BCM3302",
12853 + [CPU_BCM4710] "Broadcom BCM4710"
12854 };
12855
12856
12857 diff -Nur linux-2.6.12.5/arch/mips/mm/tlbex.c linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c
12858 --- linux-2.6.12.5/arch/mips/mm/tlbex.c 2005-08-15 02:20:18.000000000 +0200
12859 +++ linux-2.6.12.5-brcm/arch/mips/mm/tlbex.c 2005-09-16 10:29:18.273576896 +0200
12860 @@ -851,6 +851,8 @@
12861 case CPU_4KSC:
12862 case CPU_20KC:
12863 case CPU_25KF:
12864 + case CPU_BCM3302:
12865 + case CPU_BCM4710:
12866 tlbw(p);
12867 break;
12868
12869 diff -Nur linux-2.6.12.5/arch/mips/pci/Makefile linux-2.6.12.5-brcm/arch/mips/pci/Makefile
12870 --- linux-2.6.12.5/arch/mips/pci/Makefile 2005-08-15 02:20:18.000000000 +0200
12871 +++ linux-2.6.12.5-brcm/arch/mips/pci/Makefile 2005-09-16 10:29:18.311571120 +0200
12872 @@ -18,6 +18,7 @@
12873 obj-$(CONFIG_MIPS_TX3927) += ops-jmr3927.o
12874 obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
12875 obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
12876 +obj-$(CONFIG_BCM947XX) += ops-sb.o fixup-bcm47xx.o pci-bcm47xx.o
12877
12878 #
12879 # These are still pretty much in the old state, watch, go blind.
12880 diff -Nur linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c
12881 --- linux-2.6.12.5/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
12882 +++ linux-2.6.12.5-brcm/arch/mips/pci/fixup-bcm47xx.c 2005-09-16 10:29:18.312570968 +0200
12883 @@ -0,0 +1,23 @@
12884 +#include <linux/init.h>
12885 +#include <linux/pci.h>
12886 +
12887 +/* Do platform specific device initialization at pci_enable_device() time */
12888 +int pcibios_plat_dev_init(struct pci_dev *dev)
12889 +{
12890 + return 0;
12891 +}
12892 +
12893 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
12894 +{
12895 + u8 irq;
12896 +
12897 + if (dev->bus->number == 1)
12898 + return 2;
12899 +
12900 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
12901 + return irq + 2;
12902 +}
12903 +
12904 +struct pci_fixup pcibios_fixups[] __initdata = {
12905 + { 0 }
12906 +};
12907 diff -Nur linux-2.6.12.5/arch/mips/pci/ops-sb.c linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c
12908 --- linux-2.6.12.5/arch/mips/pci/ops-sb.c 1970-01-01 01:00:00.000000000 +0100
12909 +++ linux-2.6.12.5-brcm/arch/mips/pci/ops-sb.c 2005-09-16 10:29:18.312570968 +0200
12910 @@ -0,0 +1,44 @@
12911 +#include <linux/kernel.h>
12912 +#include <linux/init.h>
12913 +#include <linux/pci.h>
12914 +#include <linux/types.h>
12915 +#include <asm/pci.h>
12916 +
12917 +#include <typedefs.h>
12918 +#include <sbpci.h>
12919 +
12920 +extern void *sbh;
12921 +//extern spinlock_t bcm47xx_sbh_lock;
12922 +
12923 +static int
12924 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
12925 + int reg, int size, u32 *val)
12926 +{
12927 + //unsigned long flags;
12928 + int ret;
12929 +
12930 +
12931 + //spin_lock_irqsave(&sbh_lock, flags);
12932 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
12933 + //spin_unlock_irqrestore(&sbh_lock, flags);
12934 +
12935 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
12936 +}
12937 +
12938 +static int
12939 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
12940 + int reg, int size, u32 val)
12941 +{
12942 +// unsigned long flags;
12943 + int ret;
12944 +
12945 +// spin_lock_irqsave(&sbh_lock, flags);
12946 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
12947 +// spin_unlock_irqrestore(&sbh_lock, flags);
12948 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
12949 +}
12950 +
12951 +struct pci_ops sb_pci_ops = {
12952 + .read = sb_pci_read_config,
12953 + .write = sb_pci_write_config,
12954 +};
12955 diff -Nur linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c
12956 --- linux-2.6.12.5/arch/mips/pci/pci-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
12957 +++ linux-2.6.12.5-brcm/arch/mips/pci/pci-bcm47xx.c 2005-09-16 10:29:18.313570816 +0200
12958 @@ -0,0 +1,61 @@
12959 +#include <linux/init.h>
12960 +#include <linux/pci.h>
12961 +#include <linux/types.h>
12962 +
12963 +#include <asm/cpu.h>
12964 +#include <asm/io.h>
12965 +
12966 +#include <typedefs.h>
12967 +#include <sbconfig.h>
12968 +
12969 +extern struct pci_ops sb_pci_ops;
12970 +
12971 +static struct resource sb_pci_mem_resource = {
12972 + .name = "SB PCI Memory resources",
12973 + .start = SB_ENUM_BASE,
12974 + .end = SB_ENUM_LIM - 1,
12975 + .flags = IORESOURCE_MEM,
12976 +};
12977 +
12978 +static struct resource sb_pci_io_resource = {
12979 + .name = "SB PCI I/O resources",
12980 + .start = 0x100,
12981 + .end = 0x1FF,
12982 + .flags = IORESOURCE_IO,
12983 +};
12984 +
12985 +static struct pci_controller bcm47xx_sb_pci_controller = {
12986 + .pci_ops = &sb_pci_ops,
12987 + .mem_resource = &sb_pci_mem_resource,
12988 + .io_resource = &sb_pci_io_resource,
12989 +};
12990 +
12991 +static struct resource ext_pci_mem_resource = {
12992 + .name = "Ext PCI Memory resources",
12993 + .start = SB_PCI_DMA,
12994 +// .end = 0x7FFFFFFF,
12995 + .end = 0x40FFFFFF,
12996 + .flags = IORESOURCE_MEM,
12997 +};
12998 +
12999 +static struct resource ext_pci_io_resource = {
13000 + .name = "Ext PCI I/O resources",
13001 + .start = 0x200,
13002 + .end = 0x2FF,
13003 + .flags = IORESOURCE_IO,
13004 +};
13005 +
13006 +static struct pci_controller bcm47xx_ext_pci_controller = {
13007 + .pci_ops = &sb_pci_ops,
13008 + .mem_resource = &ext_pci_mem_resource,
13009 + .io_resource = &ext_pci_io_resource,
13010 +};
13011 +
13012 +static int __init bcm47xx_pci_init(void)
13013 +{
13014 + register_pci_controller(&bcm47xx_sb_pci_controller);
13015 + register_pci_controller(&bcm47xx_ext_pci_controller);
13016 + return 0;
13017 +}
13018 +
13019 +early_initcall(bcm47xx_pci_init);
13020 diff -Nur linux-2.6.12.5/arch/mips/pci/pci.c linux-2.6.12.5-brcm/arch/mips/pci/pci.c
13021 --- linux-2.6.12.5/arch/mips/pci/pci.c 2005-08-15 02:20:18.000000000 +0200
13022 +++ linux-2.6.12.5-brcm/arch/mips/pci/pci.c 2005-09-16 10:29:18.327568688 +0200
13023 @@ -238,7 +238,8 @@
13024 if (dev->resource[i].flags & IORESOURCE_IO)
13025 offset = hose->io_offset;
13026 else if (dev->resource[i].flags & IORESOURCE_MEM)
13027 - offset = hose->mem_offset;
13028 + offset = 0x26000000;
13029 + // offset = hose->mem_offset;
13030
13031 dev->resource[i].start += offset;
13032 dev->resource[i].end += offset;
13033 diff -Nur linux-2.6.12.5/include/asm-mips/bootinfo.h linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h
13034 --- linux-2.6.12.5/include/asm-mips/bootinfo.h 2005-08-15 02:20:18.000000000 +0200
13035 +++ linux-2.6.12.5-brcm/include/asm-mips/bootinfo.h 2005-09-16 10:29:18.415555312 +0200
13036 @@ -213,6 +213,12 @@
13037 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
13038 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
13039
13040 +/*
13041 + * Valid machtype for group Broadcom
13042 + */
13043 +#define MACH_GROUP_BRCM 23 /* Broadcom */
13044 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
13045 +
13046 #define CL_SIZE COMMAND_LINE_SIZE
13047
13048 const char *get_system_type(void);
13049 diff -Nur linux-2.6.12.5/include/asm-mips/cpu.h linux-2.6.12.5-brcm/include/asm-mips/cpu.h
13050 --- linux-2.6.12.5/include/asm-mips/cpu.h 2005-08-15 02:20:18.000000000 +0200
13051 +++ linux-2.6.12.5-brcm/include/asm-mips/cpu.h 2005-09-16 10:29:18.416555160 +0200
13052 @@ -87,6 +87,13 @@
13053 #define PRID_IMP_SR71000 0x0400
13054
13055 /*
13056 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
13057 + */
13058 +
13059 +#define PRID_IMP_BCM4710 0x4000
13060 +#define PRID_IMP_BCM3302 0x9000
13061 +
13062 +/*
13063 * Definitions for 7:0 on legacy processors
13064 */
13065
13066 @@ -177,7 +184,9 @@
13067 #define CPU_VR4133 56
13068 #define CPU_AU1550 57
13069 #define CPU_24K 58
13070 -#define CPU_LAST 58
13071 +#define CPU_BCM3302 59
13072 +#define CPU_BCM4710 60
13073 +#define CPU_LAST 60
13074
13075 /*
13076 * ISA Level encodings
13077 diff -Nur linux-2.6.12.5/include/asm-mips/mipsregs.h linux-2.6.12.5-brcm/include/asm-mips/mipsregs.h
13078 --- linux-2.6.12.5/include/asm-mips/mipsregs.h 2005-08-15 02:20:18.000000000 +0200
13079 +++ linux-2.6.12.5-brcm/include/asm-mips/mipsregs.h 2005-09-16 10:29:18.426553640 +0200
13080 @@ -790,10 +790,18 @@
13081 #define read_c0_config1() __read_32bit_c0_register($16, 1)
13082 #define read_c0_config2() __read_32bit_c0_register($16, 2)
13083 #define read_c0_config3() __read_32bit_c0_register($16, 3)
13084 +#define read_c0_config4() __read_32bit_c0_register($16, 4)
13085 +#define read_c0_config5() __read_32bit_c0_register($16, 5)
13086 +#define read_c0_config6() __read_32bit_c0_register($16, 6)
13087 +#define read_c0_config7() __read_32bit_c0_register($16, 7)
13088 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
13089 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
13090 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
13091 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
13092 +#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
13093 +#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
13094 +#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
13095 +#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
13096
13097 /*
13098 * The WatchLo register. There may be upto 8 of them.
13099 diff -Nur linux-2.6.12.5/include/linux/init.h linux-2.6.12.5-brcm/include/linux/init.h
13100 --- linux-2.6.12.5/include/linux/init.h 2005-08-15 02:20:18.000000000 +0200
13101 +++ linux-2.6.12.5-brcm/include/linux/init.h 2005-09-16 10:29:18.426553640 +0200
13102 @@ -86,6 +86,8 @@
13103 static initcall_t __initcall_##fn __attribute_used__ \
13104 __attribute__((__section__(".initcall" level ".init"))) = fn
13105
13106 +#define early_initcall(fn) __define_initcall(".early1",fn)
13107 +
13108 #define core_initcall(fn) __define_initcall("1",fn)
13109 #define postcore_initcall(fn) __define_initcall("2",fn)
13110 #define arch_initcall(fn) __define_initcall("3",fn)
13111 diff -Nur linux-2.6.12.5/include/linux/pci_ids.h linux-2.6.12.5-brcm/include/linux/pci_ids.h
13112 --- linux-2.6.12.5/include/linux/pci_ids.h 2005-08-15 02:20:18.000000000 +0200
13113 +++ linux-2.6.12.5-brcm/include/linux/pci_ids.h 2005-09-16 10:29:18.429553184 +0200
13114 @@ -2110,6 +2110,7 @@
13115 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
13116 #define PCI_DEVICE_ID_BCM4401 0x4401
13117 #define PCI_DEVICE_ID_BCM4401B0 0x4402
13118 +#define PCI_DEVICE_ID_BCM4713 0x4713
13119
13120 #define PCI_VENDOR_ID_TOPIC 0x151f
13121 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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