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ar71xx: add error handling to ar724x_pcibios_init
[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c
1 /*
2 * Atheros AR71xx PCI host controller driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/resource.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/pci.h>
19 #include <linux/pci_regs.h>
20 #include <linux/interrupt.h>
21
22 #include <asm/mach-ar71xx/ar71xx.h>
23 #include <asm/mach-ar71xx/pci.h>
24
25 #undef DEBUG
26 #ifdef DEBUG
27 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
28 #else
29 #define DBG(fmt, args...)
30 #endif
31
32 #define AR71XX_PCI_DELAY 100 /* msecs */
33
34 #if 0
35 #define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
36 #else
37 #define PCI_IDSEL_BASE 0
38 #endif
39
40 static void __iomem *ar71xx_pcicfg_base;
41 static DEFINE_SPINLOCK(ar71xx_pci_lock);
42 static int ar71xx_pci_fixup_enable;
43
44 static inline void ar71xx_pci_delay(void)
45 {
46 mdelay(AR71XX_PCI_DELAY);
47 }
48
49 static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
50 {
51 return __raw_readl(ar71xx_pcicfg_base + reg);
52 }
53
54 static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
55 {
56 __raw_writel(val, ar71xx_pcicfg_base + reg);
57 }
58
59 /* Byte lane enable bits */
60 static u8 ble_table[4][4] = {
61 {0x0, 0xf, 0xf, 0xf},
62 {0xe, 0xd, 0xb, 0x7},
63 {0xc, 0xf, 0x3, 0xf},
64 {0xf, 0xf, 0xf, 0xf},
65 };
66
67 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
68 {
69 u32 t;
70
71 t = ble_table[size & 3][where & 3];
72 BUG_ON(t == 0xf);
73 t <<= (local) ? 20 : 4;
74 return t;
75 }
76
77 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
78 int where)
79 {
80 u32 ret;
81
82 if (!bus->number) {
83 /* type 0 */
84 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
85 | (PCI_FUNC(devfn) << 8) | (where & ~3);
86 } else {
87 /* type 1 */
88 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
89 | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
90 }
91
92 return ret;
93 }
94
95 int ar71xx_pci_be_handler(int is_fixup)
96 {
97 u32 pci_err;
98 u32 ahb_err;
99
100 pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
101 if (pci_err) {
102 if (!is_fixup)
103 printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
104 pci_err,
105 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
106
107 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
108 }
109
110 ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
111 if (ahb_err) {
112 if (!is_fixup)
113 printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
114 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
115
116 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
117 }
118
119 return ((ahb_err | pci_err) ? 1 : 0);
120 }
121
122 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
123 unsigned int devfn, int where, int size, u32 cmd)
124 {
125 u32 addr;
126
127 addr = ar71xx_pci_bus_addr(bus, devfn, where);
128
129 DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
130 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
131 where, size, addr);
132
133 ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
134 ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
135 cmd | ar71xx_pci_get_ble(where, size, 0));
136
137 return ar71xx_pci_be_handler(1);
138 }
139
140 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 *value)
142 {
143 static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
144 unsigned long flags;
145 u32 data;
146 int ret;
147
148 ret = PCIBIOS_SUCCESSFUL;
149
150 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
151 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
152
153 spin_lock_irqsave(&ar71xx_pci_lock, flags);
154
155 if (bus->number == 0 && devfn == 0) {
156 u32 t;
157
158 t = PCI_CRP_CMD_READ | (where & ~3);
159
160 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
161 data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
162
163 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
164
165 } else {
166 int err;
167
168 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
169 PCI_CFG_CMD_READ);
170
171 if (err == 0) {
172 data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
173 } else {
174 ret = PCIBIOS_DEVICE_NOT_FOUND;
175 data = ~0;
176 }
177 }
178
179 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
180
181 DBG("PCI: read config: data=%08x raw=%08x\n",
182 (data >> (8 * (where & 3))) & mask[size & 7], data);
183
184 *value = (data >> (8 * (where & 3))) & mask[size & 7];
185
186 return ret;
187 }
188
189 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
190 int where, int size, u32 value)
191 {
192 unsigned long flags;
193 int ret;
194
195 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
196 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
197 where, size, value);
198
199 value = value << (8 * (where & 3));
200 ret = PCIBIOS_SUCCESSFUL;
201
202 spin_lock_irqsave(&ar71xx_pci_lock, flags);
203 if (bus->number == 0 && devfn == 0) {
204 u32 t;
205
206 t = PCI_CRP_CMD_WRITE | (where & ~3);
207 t |= ar71xx_pci_get_ble(where, size, 1);
208
209 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
210
211 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
212 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
213 } else {
214 int err;
215
216 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
217 PCI_CFG_CMD_WRITE);
218
219 if (err == 0)
220 ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
221 else
222 ret = PCIBIOS_DEVICE_NOT_FOUND;
223 }
224 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
225
226 return ret;
227 }
228
229 static void ar71xx_pci_fixup(struct pci_dev *dev)
230 {
231 u32 t;
232
233 if (!ar71xx_pci_fixup_enable)
234 return;
235
236 if (dev->bus->number != 0 || dev->devfn != 0)
237 return;
238
239 DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
240 dev->vendor, dev->device);
241
242 /* setup COMMAND register */
243 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
244 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
245
246 pci_write_config_word(dev, PCI_COMMAND, t);
247 }
248 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
249
250 int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
251 uint8_t pin)
252 {
253 int irq = -1;
254 int i;
255
256 slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
257
258 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
259 struct ar71xx_pci_irq *entry;
260
261 entry = &ar71xx_pci_irq_map[i];
262 if (entry->slot == slot && entry->pin == pin) {
263 irq = entry->irq;
264 break;
265 }
266 }
267
268 if (irq < 0) {
269 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
270 pin, pci_name((struct pci_dev *)dev));
271 } else {
272 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
273 irq, pin, pci_name((struct pci_dev *)dev));
274 }
275
276 return irq;
277 }
278
279 static struct pci_ops ar71xx_pci_ops = {
280 .read = ar71xx_pci_read_config,
281 .write = ar71xx_pci_write_config,
282 };
283
284 static struct resource ar71xx_pci_io_resource = {
285 .name = "PCI IO space",
286 .start = 0,
287 .end = 0,
288 .flags = IORESOURCE_IO,
289 };
290
291 static struct resource ar71xx_pci_mem_resource = {
292 .name = "PCI memory space",
293 .start = AR71XX_PCI_MEM_BASE,
294 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
295 .flags = IORESOURCE_MEM
296 };
297
298 static struct pci_controller ar71xx_pci_controller = {
299 .pci_ops = &ar71xx_pci_ops,
300 .mem_resource = &ar71xx_pci_mem_resource,
301 .io_resource = &ar71xx_pci_io_resource,
302 };
303
304 static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
305 {
306 u32 pending;
307
308 pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
309 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
310
311 if (pending & PCI_INT_DEV0)
312 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
313
314 else if (pending & PCI_INT_DEV1)
315 generic_handle_irq(AR71XX_PCI_IRQ_DEV1);
316
317 else if (pending & PCI_INT_DEV2)
318 generic_handle_irq(AR71XX_PCI_IRQ_DEV2);
319
320 else if (pending & PCI_INT_CORE)
321 generic_handle_irq(AR71XX_PCI_IRQ_CORE);
322
323 else
324 spurious_interrupt();
325 }
326
327 static void ar71xx_pci_irq_unmask(unsigned int irq)
328 {
329 irq -= AR71XX_PCI_IRQ_BASE;
330 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
331 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
332
333 /* flush write */
334 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
335 }
336
337 static void ar71xx_pci_irq_mask(unsigned int irq)
338 {
339 irq -= AR71XX_PCI_IRQ_BASE;
340 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
341 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
342
343 /* flush write */
344 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
345 }
346
347 static struct irq_chip ar71xx_pci_irq_chip = {
348 .name = "AR71XX PCI ",
349 .mask = ar71xx_pci_irq_mask,
350 .unmask = ar71xx_pci_irq_unmask,
351 .mask_ack = ar71xx_pci_irq_mask,
352 };
353
354 static void __init ar71xx_pci_irq_init(void)
355 {
356 int i;
357
358 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
359 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
360
361 for (i = AR71XX_PCI_IRQ_BASE;
362 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
363 irq_desc[i].status = IRQ_DISABLED;
364 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
365 handle_level_irq);
366 }
367
368 set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
369 }
370
371 int __init ar71xx_pcibios_init(void)
372 {
373 ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
374 ar71xx_pci_delay();
375
376 ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
377 ar71xx_pci_delay();
378
379 ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
380 AR71XX_PCI_CFG_SIZE);
381
382 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
383 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
384 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
385 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
386 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
387 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
388 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
389 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
390
391 ar71xx_pci_delay();
392
393 /* clear bus errors */
394 (void)ar71xx_pci_be_handler(1);
395
396 ar71xx_pci_fixup_enable = 1;
397 ar71xx_pci_irq_init();
398 register_pci_controller(&ar71xx_pci_controller);
399
400 return 0;
401 }
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