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generic: rtl8366: move common VLAN handling functions to rtl8366_smi.c
[openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366RB_DRIVER_VER "0.2.2"
29
30 #define RTL8366RB_PHY_NO_MAX 4
31 #define RTL8366RB_PHY_PAGE_MAX 7
32 #define RTL8366RB_PHY_ADDR_MAX 31
33
34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 /* Switch Global Configuration register */
39 #define RTL8366RB_SGCR 0x0000
40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
47
48 /* Port Enable Control register */
49 #define RTL8366RB_PECR 0x0001
50
51 /* Switch Security Control registers */
52 #define RTL8366RB_SSCR0 0x0002
53 #define RTL8366RB_SSCR1 0x0003
54 #define RTL8366RB_SSCR2 0x0004
55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
56
57 #define RTL8366RB_RESET_CTRL_REG 0x0100
58 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
59 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
60
61 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366RB_CHIP_VERSION_MASK 0xf
63 #define RTL8366RB_CHIP_ID_REG 0x0509
64 #define RTL8366RB_CHIP_ID_8366 0x5937
65
66 /* PHY registers control */
67 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
69
70 #define RTL8366RB_PHY_CTRL_READ 1
71 #define RTL8366RB_PHY_CTRL_WRITE 0
72
73 #define RTL8366RB_PHY_REG_MASK 0x1f
74 #define RTL8366RB_PHY_PAGE_OFFSET 5
75 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366RB_PHY_NO_OFFSET 9
77 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
78
79 /* LED control registers */
80 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
81 #define RTL8366RB_LED_BLINKRATE_BIT 0
82 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
83
84 #define RTL8366RB_LED_CTRL_REG 0x0431
85 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
87
88 #define RTL8366RB_MIB_COUNT 33
89 #define RTL8366RB_GLOBAL_MIB_COUNT 1
90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
92 #define RTL8366RB_MIB_CTRL_REG 0x13F0
93 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
95 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
98
99 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
101 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
102 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104
105
106 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
108
109
110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
111 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
113
114 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
115
116
117 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
118 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
124
125
126 #define RTL8366RB_PORT_NUM_CPU 5
127 #define RTL8366RB_NUM_PORTS 6
128 #define RTL8366RB_NUM_VLANS 16
129 #define RTL8366RB_NUM_LEDGROUPS 4
130 #define RTL8366RB_NUM_VIDS 4096
131 #define RTL8366RB_PRIORITYMAX 7
132 #define RTL8366RB_FIDMAX 7
133
134
135 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
140
141 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
142
143 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
144 RTL8366RB_PORT_2 | \
145 RTL8366RB_PORT_3 | \
146 RTL8366RB_PORT_4 | \
147 RTL8366RB_PORT_5 | \
148 RTL8366RB_PORT_CPU)
149
150 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
151 RTL8366RB_PORT_2 | \
152 RTL8366RB_PORT_3 | \
153 RTL8366RB_PORT_4 | \
154 RTL8366RB_PORT_5)
155
156 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
157 RTL8366RB_PORT_2 | \
158 RTL8366RB_PORT_3 | \
159 RTL8366RB_PORT_4)
160
161 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
162
163 struct rtl8366rb {
164 struct device *parent;
165 struct rtl8366_smi smi;
166 struct switch_dev dev;
167 char buf[4096];
168 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
169 struct dentry *debugfs_root;
170 #endif
171 };
172
173 struct rtl8366rb_vlan_mc {
174 u16 reserved2:1;
175 u16 priority:3;
176 u16 vid:12;
177 u16 untag:8;
178 u16 member:8;
179 u16 stag_mbr:8;
180 u16 stag_idx:3;
181 u16 reserved1:2;
182 u16 fid:3;
183 };
184
185 struct rtl8366rb_vlan_4k {
186 u16 reserved1:4;
187 u16 vid:12;
188 u16 untag:8;
189 u16 member:8;
190 u16 reserved2:13;
191 u16 fid:3;
192 };
193
194 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
195 u16 gl_dbg_reg;
196 #endif
197
198 struct mib_counter {
199 unsigned offset;
200 unsigned length;
201 const char *name;
202 };
203
204 static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
205 { 0, 4, "IfInOctets" },
206 { 4, 4, "EtherStatsOctets" },
207 { 8, 2, "EtherStatsUnderSizePkts" },
208 { 10, 2, "EtherFragments" },
209 { 12, 2, "EtherStatsPkts64Octets" },
210 { 14, 2, "EtherStatsPkts65to127Octets" },
211 { 16, 2, "EtherStatsPkts128to255Octets" },
212 { 18, 2, "EtherStatsPkts256to511Octets" },
213 { 20, 2, "EtherStatsPkts512to1023Octets" },
214 { 22, 2, "EtherStatsPkts1024to1518Octets" },
215 { 24, 2, "EtherOversizeStats" },
216 { 26, 2, "EtherStatsJabbers" },
217 { 28, 2, "IfInUcastPkts" },
218 { 30, 2, "EtherStatsMulticastPkts" },
219 { 32, 2, "EtherStatsBroadcastPkts" },
220 { 34, 2, "EtherStatsDropEvents" },
221 { 36, 2, "Dot3StatsFCSErrors" },
222 { 38, 2, "Dot3StatsSymbolErrors" },
223 { 40, 2, "Dot3InPauseFrames" },
224 { 42, 2, "Dot3ControlInUnknownOpcodes" },
225 { 44, 4, "IfOutOctets" },
226 { 48, 2, "Dot3StatsSingleCollisionFrames" },
227 { 50, 2, "Dot3StatMultipleCollisionFrames" },
228 { 52, 2, "Dot3sDeferredTransmissions" },
229 { 54, 2, "Dot3StatsLateCollisions" },
230 { 56, 2, "EtherStatsCollisions" },
231 { 58, 2, "Dot3StatsExcessiveCollisions" },
232 { 60, 2, "Dot3OutPauseFrames" },
233 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
234 { 64, 2, "Dot1dTpPortInDiscards" },
235 { 66, 2, "IfOutUcastPkts" },
236 { 68, 2, "IfOutMulticastPkts" },
237 { 70, 2, "IfOutBroadcastPkts" },
238 };
239
240 #define REG_WR(_smi, _reg, _val) \
241 do { \
242 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
243 if (err) \
244 return err; \
245 } while (0)
246
247 #define REG_RMW(_smi, _reg, _mask, _val) \
248 do { \
249 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
250 if (err) \
251 return err; \
252 } while (0)
253
254 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
255 {
256 return container_of(smi, struct rtl8366rb, smi);
257 }
258
259 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
260 {
261 return container_of(sw, struct rtl8366rb, dev);
262 }
263
264 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
265 {
266 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
267 return &rtl->smi;
268 }
269
270 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
271 {
272 int timeout = 10;
273 u32 data;
274
275 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
276 RTL8366RB_CHIP_CTRL_RESET_HW);
277 do {
278 msleep(1);
279 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
280 return -EIO;
281
282 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
283 break;
284 } while (--timeout);
285
286 if (!timeout) {
287 printk("Timeout waiting for the switch to reset\n");
288 return -EIO;
289 }
290
291 return 0;
292 }
293
294 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
295 {
296 int err;
297
298 /* set maximum packet length to 1536 bytes */
299 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
300 RTL8366RB_SGCR_MAX_LENGTH_1536);
301
302 /* enable all ports */
303 REG_WR(smi, RTL8366RB_PECR, 0);
304
305 /* disable learning for all ports */
306 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
307
308 /* disable auto ageing for all ports */
309 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
310
311 /* don't drop packets whose DA has not been learned */
312 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
313
314 return 0;
315 }
316
317 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
318 u32 phy_no, u32 page, u32 addr, u32 *data)
319 {
320 u32 reg;
321 int ret;
322
323 if (phy_no > RTL8366RB_PHY_NO_MAX)
324 return -EINVAL;
325
326 if (page > RTL8366RB_PHY_PAGE_MAX)
327 return -EINVAL;
328
329 if (addr > RTL8366RB_PHY_ADDR_MAX)
330 return -EINVAL;
331
332 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
333 RTL8366RB_PHY_CTRL_READ);
334 if (ret)
335 return ret;
336
337 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
338 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
339 (addr & RTL8366RB_PHY_REG_MASK);
340
341 ret = rtl8366_smi_write_reg(smi, reg, 0);
342 if (ret)
343 return ret;
344
345 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
346 if (ret)
347 return ret;
348
349 return 0;
350 }
351
352 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
353 u32 phy_no, u32 page, u32 addr, u32 data)
354 {
355 u32 reg;
356 int ret;
357
358 if (phy_no > RTL8366RB_PHY_NO_MAX)
359 return -EINVAL;
360
361 if (page > RTL8366RB_PHY_PAGE_MAX)
362 return -EINVAL;
363
364 if (addr > RTL8366RB_PHY_ADDR_MAX)
365 return -EINVAL;
366
367 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
368 RTL8366RB_PHY_CTRL_WRITE);
369 if (ret)
370 return ret;
371
372 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
373 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
374 (addr & RTL8366RB_PHY_REG_MASK);
375
376 ret = rtl8366_smi_write_reg(smi, reg, data);
377 if (ret)
378 return ret;
379
380 return 0;
381 }
382
383 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
384 int port, unsigned long long *val)
385 {
386 int i;
387 int err;
388 u32 addr, data;
389 u64 mibvalue;
390
391 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
392 return -EINVAL;
393
394 addr = RTL8366RB_MIB_COUNTER_BASE +
395 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
396 rtl8366rb_mib_counters[counter].offset;
397
398 /*
399 * Writing access counter address first
400 * then ASIC will prepare 64bits counter wait for being retrived
401 */
402 data = 0; /* writing data will be discard by ASIC */
403 err = rtl8366_smi_write_reg(smi, addr, data);
404 if (err)
405 return err;
406
407 /* read MIB control register */
408 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
409 if (err)
410 return err;
411
412 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
413 return -EBUSY;
414
415 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
416 return -EIO;
417
418 mibvalue = 0;
419 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
420 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
421 if (err)
422 return err;
423
424 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
425 }
426
427 *val = mibvalue;
428 return 0;
429 }
430
431 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
432 struct rtl8366_vlan_4k *vlan4k)
433 {
434 struct rtl8366rb_vlan_4k vlan4k_priv;
435 int err;
436 u32 data;
437 u16 *tableaddr;
438
439 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
440 vlan4k_priv.vid = vid;
441
442 if (vid >= RTL8366RB_NUM_VIDS)
443 return -EINVAL;
444
445 tableaddr = (u16 *)&vlan4k_priv;
446
447 /* write VID */
448 data = *tableaddr;
449 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
450 if (err)
451 return err;
452
453 /* write table access control word */
454 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
455 RTL8366RB_TABLE_VLAN_READ_CTRL);
456 if (err)
457 return err;
458
459 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
460 if (err)
461 return err;
462
463 *tableaddr = data;
464 tableaddr++;
465
466 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
467 &data);
468 if (err)
469 return err;
470
471 *tableaddr = data;
472 tableaddr++;
473
474 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
475 &data);
476 if (err)
477 return err;
478 *tableaddr = data;
479
480 vlan4k->vid = vid;
481 vlan4k->untag = vlan4k_priv.untag;
482 vlan4k->member = vlan4k_priv.member;
483 vlan4k->fid = vlan4k_priv.fid;
484
485 return 0;
486 }
487
488 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
489 const struct rtl8366_vlan_4k *vlan4k)
490 {
491 struct rtl8366rb_vlan_4k vlan4k_priv;
492 int err;
493 u32 data;
494 u16 *tableaddr;
495
496 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
497 vlan4k->member > RTL8366RB_PORT_ALL ||
498 vlan4k->untag > RTL8366RB_PORT_ALL ||
499 vlan4k->fid > RTL8366RB_FIDMAX)
500 return -EINVAL;
501
502 vlan4k_priv.vid = vlan4k->vid;
503 vlan4k_priv.untag = vlan4k->untag;
504 vlan4k_priv.member = vlan4k->member;
505 vlan4k_priv.fid = vlan4k->fid;
506
507 tableaddr = (u16 *)&vlan4k_priv;
508
509 data = *tableaddr;
510
511 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
512 if (err)
513 return err;
514
515 tableaddr++;
516
517 data = *tableaddr;
518
519 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
520 data);
521 if (err)
522 return err;
523
524 tableaddr++;
525
526 data = *tableaddr;
527
528 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
529 data);
530 if (err)
531 return err;
532
533 /* write table access control word */
534 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
535 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
536
537 return err;
538 }
539
540 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
541 struct rtl8366_vlan_mc *vlanmc)
542 {
543 struct rtl8366rb_vlan_mc vlanmc_priv;
544 int err;
545 u32 addr;
546 u32 data;
547 u16 *tableaddr;
548
549 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
550
551 if (index >= RTL8366RB_NUM_VLANS)
552 return -EINVAL;
553
554 tableaddr = (u16 *)&vlanmc_priv;
555
556 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
557 err = rtl8366_smi_read_reg(smi, addr, &data);
558 if (err)
559 return err;
560
561 *tableaddr = data;
562 tableaddr++;
563
564 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
565 err = rtl8366_smi_read_reg(smi, addr, &data);
566 if (err)
567 return err;
568
569 *tableaddr = data;
570 tableaddr++;
571
572 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
573 err = rtl8366_smi_read_reg(smi, addr, &data);
574 if (err)
575 return err;
576
577 *tableaddr = data;
578
579 vlanmc->vid = vlanmc_priv.vid;
580 vlanmc->priority = vlanmc_priv.priority;
581 vlanmc->untag = vlanmc_priv.untag;
582 vlanmc->member = vlanmc_priv.member;
583 vlanmc->fid = vlanmc_priv.fid;
584
585 return 0;
586 }
587
588 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
589 const struct rtl8366_vlan_mc *vlanmc)
590 {
591 struct rtl8366rb_vlan_mc vlanmc_priv;
592 int err;
593 u32 addr;
594 u32 data;
595 u16 *tableaddr;
596
597 if (index >= RTL8366RB_NUM_VLANS ||
598 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
599 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
600 vlanmc->member > RTL8366RB_PORT_ALL ||
601 vlanmc->untag > RTL8366RB_PORT_ALL ||
602 vlanmc->fid > RTL8366RB_FIDMAX)
603 return -EINVAL;
604
605 vlanmc_priv.vid = vlanmc->vid;
606 vlanmc_priv.priority = vlanmc->priority;
607 vlanmc_priv.untag = vlanmc->untag;
608 vlanmc_priv.member = vlanmc->member;
609 vlanmc_priv.stag_mbr = 0;
610 vlanmc_priv.stag_idx = 0;
611 vlanmc_priv.fid = vlanmc->fid;
612
613 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
614
615 tableaddr = (u16 *)&vlanmc_priv;
616 data = *tableaddr;
617
618 err = rtl8366_smi_write_reg(smi, addr, data);
619 if (err)
620 return err;
621
622 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
623
624 tableaddr++;
625 data = *tableaddr;
626
627 err = rtl8366_smi_write_reg(smi, addr, data);
628 if (err)
629 return err;
630
631 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
632
633 tableaddr++;
634 data = *tableaddr;
635
636 err = rtl8366_smi_write_reg(smi, addr, data);
637 if (err)
638 return err;
639 return 0;
640 }
641
642 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
643 {
644 u32 data;
645 int err;
646
647 if (port >= RTL8366RB_NUM_PORTS)
648 return -EINVAL;
649
650 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
651 &data);
652 if (err)
653 return err;
654
655 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
656 RTL8366RB_PORT_VLAN_CTRL_MASK;
657
658 return 0;
659
660 }
661
662 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
663 {
664 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
665 return -EINVAL;
666
667 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
668 RTL8366RB_PORT_VLAN_CTRL_MASK <<
669 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
670 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
671 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
672 }
673
674 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
675 {
676 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
677 RTL8366RB_CHIP_CTRL_VLAN,
678 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
679 }
680
681 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
682 {
683 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
684 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
685 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
686 }
687
688 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
689 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
690 {
691 file->private_data = inode->i_private;
692 return 0;
693 }
694
695 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
696 char __user *user_buf,
697 size_t count, loff_t *ppos)
698 {
699 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
700 struct rtl8366_smi *smi = &rtl->smi;
701 int i, j, len = 0;
702 char *buf = rtl->buf;
703
704 len += snprintf(buf + len, sizeof(rtl->buf) - len,
705 "%-36s %12s %12s %12s %12s %12s %12s\n",
706 "Counter",
707 "Port 0", "Port 1", "Port 2",
708 "Port 3", "Port 4", "Port 5");
709
710 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
711 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
712 rtl8366rb_mib_counters[i].name);
713 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
714 unsigned long long counter = 0;
715
716 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
717 len += snprintf(buf + len,
718 sizeof(rtl->buf) - len,
719 "%12llu ", counter);
720 else
721 len += snprintf(buf + len,
722 sizeof(rtl->buf) - len,
723 "%12s ", "error");
724 }
725 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
726 }
727
728 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
729 }
730
731 static ssize_t rtl8366rb_read_debugfs_vlan_mc(struct file *file,
732 char __user *user_buf,
733 size_t count, loff_t *ppos)
734 {
735 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
736 struct rtl8366_smi *smi = &rtl->smi;
737 int i, len = 0;
738 char *buf = rtl->buf;
739
740 len += snprintf(buf + len, sizeof(rtl->buf) - len,
741 "%2s %6s %4s %6s %6s %3s\n",
742 "id", "vid","prio", "member", "untag", "fid");
743
744 for (i = 0; i < RTL8366RB_NUM_VLANS; ++i) {
745 struct rtl8366_vlan_mc vlanmc;
746
747 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
748
749 len += snprintf(buf + len, sizeof(rtl->buf) - len,
750 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
751 i, vlanmc.vid, vlanmc.priority,
752 vlanmc.member, vlanmc.untag, vlanmc.fid);
753 }
754
755 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
756 }
757
758 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
759 char __user *user_buf,
760 size_t count, loff_t *ppos)
761 {
762 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
763 struct rtl8366_smi *smi = &rtl->smi;
764 u32 t, reg = gl_dbg_reg;
765 int err, len = 0;
766 char *buf = rtl->buf;
767
768 memset(buf, '\0', sizeof(rtl->buf));
769
770 err = rtl8366_smi_read_reg(smi, reg, &t);
771 if (err) {
772 len += snprintf(buf, sizeof(rtl->buf),
773 "Read failed (reg: 0x%04x)\n", reg);
774 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
775 }
776
777 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
778 reg, t);
779
780 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
781 }
782
783 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
784 const char __user *user_buf,
785 size_t count, loff_t *ppos)
786 {
787 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
788 struct rtl8366_smi *smi = &rtl->smi;
789 unsigned long data;
790 u32 reg = gl_dbg_reg;
791 int err;
792 size_t len;
793 char *buf = rtl->buf;
794
795 len = min(count, sizeof(rtl->buf) - 1);
796 if (copy_from_user(buf, user_buf, len)) {
797 dev_err(rtl->parent, "copy from user failed\n");
798 return -EFAULT;
799 }
800
801 buf[len] = '\0';
802 if (len > 0 && buf[len - 1] == '\n')
803 buf[len - 1] = '\0';
804
805
806 if (strict_strtoul(buf, 16, &data)) {
807 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
808 } else {
809 err = rtl8366_smi_write_reg(smi, reg, data);
810 if (err) {
811 dev_err(rtl->parent,
812 "writing reg 0x%04x val 0x%04lx failed\n",
813 reg, data);
814 }
815 }
816
817 return count;
818 }
819
820 static const struct file_operations fops_rtl8366rb_regs = {
821 .read = rtl8366rb_read_debugfs_reg,
822 .write = rtl8366rb_write_debugfs_reg,
823 .open = rtl8366rb_debugfs_open,
824 .owner = THIS_MODULE
825 };
826
827 static const struct file_operations fops_rtl8366rb_vlan_mc = {
828 .read = rtl8366rb_read_debugfs_vlan_mc,
829 .open = rtl8366rb_debugfs_open,
830 .owner = THIS_MODULE
831 };
832
833 static const struct file_operations fops_rtl8366rb_mibs = {
834 .read = rtl8366rb_read_debugfs_mibs,
835 .open = rtl8366rb_debugfs_open,
836 .owner = THIS_MODULE
837 };
838
839 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
840 {
841 struct dentry *node;
842 struct dentry *root;
843
844 if (!rtl->debugfs_root)
845 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
846
847 if (!rtl->debugfs_root) {
848 dev_err(rtl->parent, "Unable to create debugfs dir\n");
849 return;
850 }
851 root = rtl->debugfs_root;
852
853 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
854 if (!node) {
855 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
856 "reg");
857 return;
858 }
859
860 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
861 &fops_rtl8366rb_regs);
862 if (!node) {
863 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
864 "val");
865 return;
866 }
867
868 node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
869 &fops_rtl8366rb_vlan_mc);
870 if (!node) {
871 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
872 "vlan_mc");
873 return;
874 }
875
876 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
877 &fops_rtl8366rb_mibs);
878 if (!node) {
879 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
880 "mibs");
881 return;
882 }
883 }
884
885 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
886 {
887 if (rtl->debugfs_root) {
888 debugfs_remove_recursive(rtl->debugfs_root);
889 rtl->debugfs_root = NULL;
890 }
891 }
892
893 #else
894 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
895 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
896 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
897
898 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
899 const struct switch_attr *attr,
900 struct switch_val *val)
901 {
902 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
903 int err = 0;
904
905 if (val->value.i == 1)
906 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
907 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
908
909 return err;
910 }
911
912 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
913 const struct switch_attr *attr,
914 struct switch_val *val)
915 {
916 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
917 u32 data;
918
919 if (attr->ofs == 1) {
920 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
921
922 if (data & RTL8366RB_CHIP_CTRL_VLAN)
923 val->value.i = 1;
924 else
925 val->value.i = 0;
926 } else if (attr->ofs == 2) {
927 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
928
929 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
930 val->value.i = 1;
931 else
932 val->value.i = 0;
933 }
934
935 return 0;
936 }
937
938 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
939 const struct switch_attr *attr,
940 struct switch_val *val)
941 {
942 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
943 u32 data;
944
945 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
946
947 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
948
949 return 0;
950 }
951
952 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
953 const struct switch_attr *attr,
954 struct switch_val *val)
955 {
956 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
957
958 if (val->value.i >= 6)
959 return -EINVAL;
960
961 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
962 RTL8366RB_LED_BLINKRATE_MASK,
963 val->value.i);
964 }
965
966 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
967 const struct switch_attr *attr,
968 struct switch_val *val)
969 {
970 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
971
972 if (attr->ofs == 1)
973 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
974 else
975 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
976 }
977
978 static const char *rtl8366rb_speed_str(unsigned speed)
979 {
980 switch (speed) {
981 case 0:
982 return "10baseT";
983 case 1:
984 return "100baseT";
985 case 2:
986 return "1000baseT";
987 }
988
989 return "unknown";
990 }
991
992 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
993 const struct switch_attr *attr,
994 struct switch_val *val)
995 {
996 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
997 struct rtl8366_smi *smi = &rtl->smi;
998 u32 len = 0, data = 0;
999
1000 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1001 return -EINVAL;
1002
1003 memset(rtl->buf, '\0', sizeof(rtl->buf));
1004 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
1005 (val->port_vlan / 2), &data);
1006
1007 if (val->port_vlan % 2)
1008 data = data >> 8;
1009
1010 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
1011 len = snprintf(rtl->buf, sizeof(rtl->buf),
1012 "port:%d link:up speed:%s %s-duplex %s%s%s",
1013 val->port_vlan,
1014 rtl8366rb_speed_str(data &
1015 RTL8366RB_PORT_STATUS_SPEED_MASK),
1016 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
1017 "full" : "half",
1018 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
1019 "tx-pause ": "",
1020 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
1021 "rx-pause " : "",
1022 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
1023 "nway ": "");
1024 } else {
1025 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1026 val->port_vlan);
1027 }
1028
1029 val->value.s = rtl->buf;
1030 val->len = len;
1031
1032 return 0;
1033 }
1034
1035 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1036 const struct switch_attr *attr,
1037 struct switch_val *val)
1038 {
1039 int i;
1040 u32 len = 0;
1041 struct rtl8366_vlan_4k vlan4k;
1042 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1043 struct rtl8366_smi *smi = &rtl->smi;
1044 char *buf = rtl->buf;
1045 int err;
1046
1047 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1048 return -EINVAL;
1049
1050 memset(buf, '\0', sizeof(rtl->buf));
1051
1052 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1053 if (err)
1054 return err;
1055
1056 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1057 "VLAN %d: Ports: '", vlan4k.vid);
1058
1059 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1060 if (!(vlan4k.member & (1 << i)))
1061 continue;
1062
1063 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
1064 (vlan4k.untag & (1 << i)) ? "" : "t");
1065 }
1066
1067 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1068 "', members=%04x, untag=%04x, fid=%u",
1069 vlan4k.member, vlan4k.untag, vlan4k.fid);
1070
1071 val->value.s = buf;
1072 val->len = len;
1073
1074 return 0;
1075 }
1076
1077 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1078 const struct switch_attr *attr,
1079 struct switch_val *val)
1080 {
1081 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1082 u32 data;
1083 u32 mask;
1084 u32 reg;
1085
1086 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1087 return -EINVAL;
1088
1089 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
1090 reg = RTL8366RB_LED_BLINKRATE_REG;
1091 mask = 0xF << 4;
1092 data = val->value.i << 4;
1093 } else {
1094 reg = RTL8366RB_LED_CTRL_REG;
1095 mask = 0xF << (val->port_vlan * 4),
1096 data = val->value.i << (val->port_vlan * 4);
1097 }
1098
1099 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
1100 }
1101
1102 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1103 const struct switch_attr *attr,
1104 struct switch_val *val)
1105 {
1106 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1107 u32 data = 0;
1108
1109 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
1110 return -EINVAL;
1111
1112 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
1113 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1114
1115 return 0;
1116 }
1117
1118 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1119 const struct switch_attr *attr,
1120 struct switch_val *val)
1121 {
1122 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1123
1124 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1125 return -EINVAL;
1126
1127 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1128 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1129 }
1130
1131 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1132 const struct switch_attr *attr,
1133 struct switch_val *val)
1134 {
1135 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1136 struct rtl8366_smi *smi = &rtl->smi;
1137 int i, len = 0;
1138 unsigned long long counter = 0;
1139 char *buf = rtl->buf;
1140
1141 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1142 return -EINVAL;
1143
1144 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1145 "Port %d MIB counters\n",
1146 val->port_vlan);
1147
1148 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1149 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1150 "%-36s: ", rtl8366rb_mib_counters[i].name);
1151 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1152 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1153 "%llu\n", counter);
1154 else
1155 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1156 "%s\n", "error");
1157 }
1158
1159 val->value.s = buf;
1160 val->len = len;
1161 return 0;
1162 }
1163
1164 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1165 struct switch_val *val)
1166 {
1167 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1168 struct switch_port *port;
1169 struct rtl8366_vlan_4k vlan4k;
1170 int i;
1171
1172 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1173 return -EINVAL;
1174
1175 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1176
1177 port = &val->value.ports[0];
1178 val->len = 0;
1179 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1180 if (!(vlan4k.member & BIT(i)))
1181 continue;
1182
1183 port->id = i;
1184 port->flags = (vlan4k.untag & BIT(i)) ?
1185 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1186 val->len++;
1187 port++;
1188 }
1189 return 0;
1190 }
1191
1192 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1193 struct switch_val *val)
1194 {
1195 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1196 struct switch_port *port;
1197 u32 member = 0;
1198 u32 untag = 0;
1199 int i;
1200
1201 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1202 return -EINVAL;
1203
1204 port = &val->value.ports[0];
1205 for (i = 0; i < val->len; i++, port++) {
1206 member |= BIT(port->id);
1207
1208 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1209 untag |= BIT(port->id);
1210 }
1211
1212 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1213 }
1214
1215 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1216 {
1217 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1218 return rtl8366_get_pvid(smi, port, val);
1219 }
1220
1221 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1222 {
1223 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1224 return rtl8366_set_pvid(smi, port, val);
1225 }
1226
1227 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1228 {
1229 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1230 int err;
1231
1232 err = rtl8366rb_reset_chip(smi);
1233 if (err)
1234 return err;
1235
1236 err = rtl8366rb_hw_init(smi);
1237 if (err)
1238 return err;
1239
1240 return rtl8366_reset_vlan(smi);
1241 }
1242
1243 static struct switch_attr rtl8366rb_globals[] = {
1244 {
1245 .type = SWITCH_TYPE_INT,
1246 .name = "enable_vlan",
1247 .description = "Enable VLAN mode",
1248 .set = rtl8366rb_sw_set_vlan_enable,
1249 .get = rtl8366rb_sw_get_vlan_enable,
1250 .max = 1,
1251 .ofs = 1
1252 }, {
1253 .type = SWITCH_TYPE_INT,
1254 .name = "enable_vlan4k",
1255 .description = "Enable VLAN 4K mode",
1256 .set = rtl8366rb_sw_set_vlan_enable,
1257 .get = rtl8366rb_sw_get_vlan_enable,
1258 .max = 1,
1259 .ofs = 2
1260 }, {
1261 .type = SWITCH_TYPE_INT,
1262 .name = "reset_mibs",
1263 .description = "Reset all MIB counters",
1264 .set = rtl8366rb_sw_reset_mibs,
1265 .get = NULL,
1266 .max = 1
1267 }, {
1268 .type = SWITCH_TYPE_INT,
1269 .name = "blinkrate",
1270 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1271 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1272 .set = rtl8366rb_sw_set_blinkrate,
1273 .get = rtl8366rb_sw_get_blinkrate,
1274 .max = 5
1275 },
1276 };
1277
1278 static struct switch_attr rtl8366rb_port[] = {
1279 {
1280 .type = SWITCH_TYPE_STRING,
1281 .name = "link",
1282 .description = "Get port link information",
1283 .max = 1,
1284 .set = NULL,
1285 .get = rtl8366rb_sw_get_port_link,
1286 }, {
1287 .type = SWITCH_TYPE_INT,
1288 .name = "reset_mib",
1289 .description = "Reset single port MIB counters",
1290 .max = 1,
1291 .set = rtl8366rb_sw_reset_port_mibs,
1292 .get = NULL,
1293 }, {
1294 .type = SWITCH_TYPE_STRING,
1295 .name = "mib",
1296 .description = "Get MIB counters for port",
1297 .max = 33,
1298 .set = NULL,
1299 .get = rtl8366rb_sw_get_port_mib,
1300 }, {
1301 .type = SWITCH_TYPE_INT,
1302 .name = "led",
1303 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1304 .max = 15,
1305 .set = rtl8366rb_sw_set_port_led,
1306 .get = rtl8366rb_sw_get_port_led,
1307 },
1308 };
1309
1310 static struct switch_attr rtl8366rb_vlan[] = {
1311 {
1312 .type = SWITCH_TYPE_STRING,
1313 .name = "info",
1314 .description = "Get vlan information",
1315 .max = 1,
1316 .set = NULL,
1317 .get = rtl8366rb_sw_get_vlan_info,
1318 },
1319 };
1320
1321 /* template */
1322 static struct switch_dev rtl8366_switch_dev = {
1323 .name = "RTL8366S",
1324 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1325 .ports = RTL8366RB_NUM_PORTS,
1326 .vlans = RTL8366RB_NUM_VLANS,
1327 .attr_global = {
1328 .attr = rtl8366rb_globals,
1329 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1330 },
1331 .attr_port = {
1332 .attr = rtl8366rb_port,
1333 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1334 },
1335 .attr_vlan = {
1336 .attr = rtl8366rb_vlan,
1337 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1338 },
1339
1340 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1341 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1342 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1343 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1344 .reset_switch = rtl8366rb_sw_reset_switch,
1345 };
1346
1347 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1348 {
1349 struct switch_dev *dev = &rtl->dev;
1350 int err;
1351
1352 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1353 dev->priv = rtl;
1354 dev->devname = dev_name(rtl->parent);
1355
1356 err = register_switch(dev, NULL);
1357 if (err)
1358 dev_err(rtl->parent, "switch registration failed\n");
1359
1360 return err;
1361 }
1362
1363 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1364 {
1365 unregister_switch(&rtl->dev);
1366 }
1367
1368 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1369 {
1370 struct rtl8366_smi *smi = bus->priv;
1371 u32 val = 0;
1372 int err;
1373
1374 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1375 if (err)
1376 return 0xffff;
1377
1378 return val;
1379 }
1380
1381 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1382 {
1383 struct rtl8366_smi *smi = bus->priv;
1384 u32 t;
1385 int err;
1386
1387 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1388 /* flush write */
1389 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1390
1391 return err;
1392 }
1393
1394 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1395 {
1396 return (bus->read == rtl8366rb_mii_read &&
1397 bus->write == rtl8366rb_mii_write);
1398 }
1399
1400 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1401 {
1402 struct rtl8366_smi *smi = &rtl->smi;
1403 int ret;
1404
1405 rtl8366rb_debugfs_init(rtl);
1406
1407 ret = rtl8366rb_reset_chip(smi);
1408 if (ret)
1409 return ret;
1410
1411 ret = rtl8366rb_hw_init(smi);
1412 return ret;
1413 }
1414
1415 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1416 {
1417 u32 chip_id = 0;
1418 u32 chip_ver = 0;
1419 int ret;
1420
1421 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1422 if (ret) {
1423 dev_err(smi->parent, "unable to read chip id\n");
1424 return ret;
1425 }
1426
1427 switch (chip_id) {
1428 case RTL8366RB_CHIP_ID_8366:
1429 break;
1430 default:
1431 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1432 return -ENODEV;
1433 }
1434
1435 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1436 &chip_ver);
1437 if (ret) {
1438 dev_err(smi->parent, "unable to read chip version\n");
1439 return ret;
1440 }
1441
1442 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1443 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1444
1445 return 0;
1446 }
1447
1448 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1449 .detect = rtl8366rb_detect,
1450 .mii_read = rtl8366rb_mii_read,
1451 .mii_write = rtl8366rb_mii_write,
1452
1453 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1454 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1455 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1456 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1457 .get_mc_index = rtl8366rb_get_mc_index,
1458 .set_mc_index = rtl8366rb_set_mc_index,
1459 };
1460
1461 static int __init rtl8366rb_probe(struct platform_device *pdev)
1462 {
1463 static int rtl8366_smi_version_printed;
1464 struct rtl8366rb_platform_data *pdata;
1465 struct rtl8366rb *rtl;
1466 struct rtl8366_smi *smi;
1467 int err;
1468
1469 if (!rtl8366_smi_version_printed++)
1470 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1471 " version " RTL8366RB_DRIVER_VER"\n");
1472
1473 pdata = pdev->dev.platform_data;
1474 if (!pdata) {
1475 dev_err(&pdev->dev, "no platform data specified\n");
1476 err = -EINVAL;
1477 goto err_out;
1478 }
1479
1480 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1481 if (!rtl) {
1482 dev_err(&pdev->dev, "no memory for private data\n");
1483 err = -ENOMEM;
1484 goto err_out;
1485 }
1486
1487 rtl->parent = &pdev->dev;
1488
1489 smi = &rtl->smi;
1490 smi->parent = &pdev->dev;
1491 smi->gpio_sda = pdata->gpio_sda;
1492 smi->gpio_sck = pdata->gpio_sck;
1493 smi->ops = &rtl8366rb_smi_ops;
1494 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1495 smi->num_ports = RTL8366RB_NUM_PORTS;
1496 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1497
1498 err = rtl8366_smi_init(smi);
1499 if (err)
1500 goto err_free_rtl;
1501
1502 platform_set_drvdata(pdev, rtl);
1503
1504 err = rtl8366rb_setup(rtl);
1505 if (err)
1506 goto err_clear_drvdata;
1507
1508 err = rtl8366rb_switch_init(rtl);
1509 if (err)
1510 goto err_clear_drvdata;
1511
1512 return 0;
1513
1514 err_clear_drvdata:
1515 platform_set_drvdata(pdev, NULL);
1516 rtl8366_smi_cleanup(smi);
1517 err_free_rtl:
1518 kfree(rtl);
1519 err_out:
1520 return err;
1521 }
1522
1523 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1524 {
1525 if (!rtl8366rb_mii_bus_match(phydev->bus))
1526 return -EINVAL;
1527
1528 return 0;
1529 }
1530
1531 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1532 {
1533 return 0;
1534 }
1535
1536 static struct phy_driver rtl8366rb_phy_driver = {
1537 .phy_id = 0x001cc960,
1538 .name = "Realtek RTL8366RB",
1539 .phy_id_mask = 0x1ffffff0,
1540 .features = PHY_GBIT_FEATURES,
1541 .config_aneg = rtl8366rb_phy_config_aneg,
1542 .config_init = rtl8366rb_phy_config_init,
1543 .read_status = genphy_read_status,
1544 .driver = {
1545 .owner = THIS_MODULE,
1546 },
1547 };
1548
1549 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1550 {
1551 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1552
1553 if (rtl) {
1554 rtl8366rb_switch_cleanup(rtl);
1555 rtl8366rb_debugfs_remove(rtl);
1556 platform_set_drvdata(pdev, NULL);
1557 rtl8366_smi_cleanup(&rtl->smi);
1558 kfree(rtl);
1559 }
1560
1561 return 0;
1562 }
1563
1564 static struct platform_driver rtl8366rb_driver = {
1565 .driver = {
1566 .name = RTL8366RB_DRIVER_NAME,
1567 .owner = THIS_MODULE,
1568 },
1569 .probe = rtl8366rb_probe,
1570 .remove = __devexit_p(rtl8366rb_remove),
1571 };
1572
1573 static int __init rtl8366rb_module_init(void)
1574 {
1575 int ret;
1576 ret = platform_driver_register(&rtl8366rb_driver);
1577 if (ret)
1578 return ret;
1579
1580 ret = phy_driver_register(&rtl8366rb_phy_driver);
1581 if (ret)
1582 goto err_platform_unregister;
1583
1584 return 0;
1585
1586 err_platform_unregister:
1587 platform_driver_unregister(&rtl8366rb_driver);
1588 return ret;
1589 }
1590 module_init(rtl8366rb_module_init);
1591
1592 static void __exit rtl8366rb_module_exit(void)
1593 {
1594 phy_driver_unregister(&rtl8366rb_phy_driver);
1595 platform_driver_unregister(&rtl8366rb_driver);
1596 }
1597 module_exit(rtl8366rb_module_exit);
1598
1599 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1600 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1601 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1602 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1603 MODULE_LICENSE("GPL v2");
1604 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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