1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
7 +#include <linux/module.h>
8 #include <linux/ssb/ssb.h>
10 #include "ssb_private.h"
11 --- a/drivers/ssb/driver_pcicore.c
12 +++ b/drivers/ssb/driver_pcicore.c
13 @@ -516,10 +516,14 @@ static void ssb_pcicore_pcie_setup_worka
15 static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
17 - ssb_pcicore_fix_sprom_core_index(pc);
18 + struct ssb_device *pdev = pc->dev;
19 + struct ssb_bus *bus = pdev->bus;
21 + if (bus->bustype == SSB_BUSTYPE_PCI)
22 + ssb_pcicore_fix_sprom_core_index(pc);
24 /* Disable PCI interrupts. */
25 - ssb_write32(pc->dev, SSB_INTVEC, 0);
26 + ssb_write32(pdev, SSB_INTVEC, 0);
28 /* Additional PCIe always once-executed workarounds */
29 if (pc->dev->id.coreid == SSB_DEV_PCIE) {
30 --- a/drivers/ssb/main.c
31 +++ b/drivers/ssb/main.c
34 #include <linux/delay.h>
36 +#include <linux/module.h>
37 #include <linux/ssb/ssb.h>
38 #include <linux/ssb/ssb_regs.h>
39 #include <linux/ssb/ssb_driver_gige.h>
40 @@ -1260,16 +1261,34 @@ void ssb_device_disable(struct ssb_devic
42 EXPORT_SYMBOL(ssb_device_disable);
44 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
45 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
47 + u16 chip_id = dev->bus->chip_id;
49 + if (dev->id.coreid == SSB_DEV_80211) {
50 + return (chip_id == 0x4322 || chip_id == 43221 ||
51 + chip_id == 43231 || chip_id == 43222);
57 u32 ssb_dma_translation(struct ssb_device *dev)
59 switch (dev->bus->bustype) {
63 - if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
64 + if (pci_is_pcie(dev->bus->host_pci) &&
65 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
66 return SSB_PCIE_DMA_H32;
70 + if (ssb_dma_translation_special_bit(dev))
71 + return SSB_PCIE_DMA_H32;
76 __ssb_dma_not_implemented(dev);
78 --- a/drivers/ssb/pci.c
79 +++ b/drivers/ssb/pci.c
80 @@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
81 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
82 sizeof(out->antenna_gain.ghz5));
84 + /* Extract FEM info */
85 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
86 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
87 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
88 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
89 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
90 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
91 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
92 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
93 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
94 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
96 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
97 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
98 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
99 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
100 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
101 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
102 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
103 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
104 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
105 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
107 sprom_extract_r458(out, in);
109 /* TODO - get remaining rev 8 stuff needed */
110 --- a/include/linux/ssb/ssb.h
111 +++ b/include/linux/ssb/ssb.h
112 @@ -25,7 +25,7 @@ struct ssb_sprom {
113 u8 et1phyaddr; /* MII address for enet1 */
114 u8 et0mdcport; /* MDIO for enet0 */
115 u8 et1mdcport; /* MDIO for enet1 */
116 - u8 board_rev; /* Board revision number from SPROM. */
117 + u16 board_rev; /* Board revision number from SPROM. */
118 u8 country_code; /* Country Code */
119 u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
120 u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
121 @@ -94,6 +94,15 @@ struct ssb_sprom {
122 } ghz5; /* 5GHz band */
127 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
130 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
134 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
137 @@ -231,10 +240,9 @@ struct ssb_driver {
138 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
140 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
141 -static inline int ssb_driver_register(struct ssb_driver *drv)
143 - return __ssb_driver_register(drv, THIS_MODULE);
145 +#define ssb_driver_register(drv) \
146 + __ssb_driver_register(drv, THIS_MODULE)
148 extern void ssb_driver_unregister(struct ssb_driver *drv);
151 --- a/include/linux/ssb/ssb_regs.h
152 +++ b/include/linux/ssb/ssb_regs.h
154 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
155 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
156 #define SSB_SPROM8_RXPO5G_SHIFT 8
157 +#define SSB_SPROM8_FEM2G 0x00AE
158 +#define SSB_SPROM8_FEM5G 0x00B0
159 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
160 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
161 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
162 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
163 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
164 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
165 +#define SSB_SROM8_FEM_TR_ISO 0x0700
166 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
167 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
168 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
169 +#define SSB_SPROM8_THERMAL 0x00B2
170 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
171 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
172 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
173 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
174 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
175 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
176 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
178 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
179 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
181 +/* Values for boardflags_lo read from SPROM */
182 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
183 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
184 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
185 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
186 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
187 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
188 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
189 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
190 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
191 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
192 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
193 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
194 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
195 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
196 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
197 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
199 +/* Values for boardflags_hi read from SPROM */
200 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
201 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
202 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
203 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
204 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
205 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
206 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
208 +/* Values for boardflags2_lo read from SPROM */
209 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
210 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
211 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
212 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
213 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
214 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
215 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
216 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
217 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
218 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
219 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
221 /* Values for SSB_SPROM1_BINF_CCODE */
223 SSB_SPROM1CCODE_WORLD = 0,