move parts of the failsafe code to the generic base-files - will be used on atheros...
[openwrt.git] / target / linux / brcm-2.4 / patches / 012-aec62xx.patch
1 --- linux-2.4.34/drivers/ide/pci/aec62xx.c.old 2006-12-23 22:34:20.000000000 +0200
2 +++ linux-2.4.34/drivers/ide/pci/aec62xx.c 2007-01-14 12:06:05.000000000 +0200
3 @@ -3,6 +3,8 @@
4 *
5 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
6 *
7 + * With Broadcom 4780 patches
8 + *
9 */
10
11 #include <linux/module.h>
12 @@ -329,7 +331,11 @@
13 ide_hwif_t *hwif = HWIF(drive);
14 struct hd_driveid *id = drive->id;
15
16 - if ((id->capability & 1) && drive->autodma) {
17 +#ifndef CONFIG_BCM947XX
18 + if ((id->capability & 1) && drive->autodma) {
19 +#else
20 + if (1) {
21 +#endif
22 /* Consult the list of known "bad" drives */
23 if (hwif->ide_dma_bad_drive(drive))
24 goto fast_ata_pio;
25 @@ -414,10 +416,60 @@
26 {
27 int bus_speed = system_bus_clock();
28
29 +#ifndef CONFIG_BCM947XX
30 if (dev->resource[PCI_ROM_RESOURCE].start) {
31 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
32 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
33 }
34 +#else
35 + if (dev->resource[PCI_ROM_RESOURCE].start) {
36 + pci_write_config_dword(dev, PCI_ROM_ADDRESS,
37 + dev->resource[PCI_ROM_RESOURCE].
38 + start | PCI_ROM_ADDRESS_ENABLE);
39 + } else {
40 + pci_write_config_dword(dev, PCI_ROM_ADDRESS,
41 + dev->resource[PCI_ROM_RESOURCE].
42 + start);
43 + }
44 +
45 + /* Set IDE controller parameters manually - FIXME: replace magic values */
46 + {
47 + byte setting;
48 +
49 + pci_write_config_word(dev, PCI_COMMAND, 0x0007);
50 + //pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A);
51 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13);
52 +
53 + pci_write_config_byte(dev, 0x40, 0x31);
54 + pci_write_config_byte(dev, 0x41, 0x31);
55 + pci_write_config_byte(dev, 0x42, 0x31);
56 + pci_write_config_byte(dev, 0x43, 0x31);
57 + // Set IDE Command Speed
58 + pci_write_config_byte(dev, 0x48, 0x31);
59 +
60 + // Disable WriteSubSysID & PIOROM
61 + pci_read_config_byte(dev, 0x49, &setting);
62 + setting &= 0x07;
63 + pci_write_config_byte(dev, 0x49, setting);
64 +
65 + // Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80
66 + pci_read_config_byte(dev, 0x4A, &setting);
67 + //setting = (setting & 0xFE) | 0xA8;
68 + setting = (setting & 0xFE) | 0xD8;
69 + setting = (setting & 0xF7);
70 + pci_write_config_byte(dev, 0x4A, setting);
71 +
72 + //pci_write_config_byte(dev, 0x4B, 0x20);
73 + pci_write_config_byte(dev, 0x4B, 0x2C);
74 + //pci_write_config_byte(dev, 0x4B, 0x0C);
75 +
76 + // Set PreRead count: 512 byte
77 + pci_write_config_byte(dev, 0x4C, 0);
78 + pci_write_config_word(dev, 0x4D, 0x0002);
79 + pci_write_config_byte(dev, 0x54, 0);
80 + pci_write_config_word(dev, 0x55, 0x0002);
81 + }
82 +#endif
83
84 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
85 aec_devs[n_aec_devs++] = dev;
86 @@ -500,6 +552,7 @@
87
88 static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
89 {
90 +#ifndef CONFIG_BCM947XX /* Causes OOPS on BCM4780 */
91 unsigned long bar4reg = pci_resource_start(dev, 4);
92
93 if (inb(bar4reg+2) & 0x10) {
94 @@ -512,6 +565,7 @@
95 strcpy(d->name, "AEC6280R");
96 }
97
98 +#endif
99 ide_setup_pci_device(dev, d);
100 }
101
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