target/linux/ar7/patches-2.6.22/100-board_support.patch

   1 diff -urN linux-2.6.22/arch/mips/Kconfig linux-2.6.22.new/arch/mips/Kconfig
   2 --- linux-2.6.22/arch/mips/Kconfig      2007-07-09 01:32:17.000000000 +0200
   3 +++ linux-2.6.22.new/arch/mips/Kconfig  2007-07-11 02:34:51.000000000 +0200
   4 @@ -15,6 +15,21 @@
   5         prompt "System type"
   6         default SGI_IP22
   7
   8 +config AR7
   9 +       bool "Texas Instruments AR7"
  10 +       select BOOT_ELF32
  11 +       select DMA_NONCOHERENT
  12 +       select HW_HAS_PCI
  13 +       select IRQ_CPU
  14 +       select SWAP_IO_SPACE
  15 +       select SYS_HAS_CPU_MIPS32_R1
  16 +       select SYS_HAS_EARLY_PRINTK
  17 +       select SYS_SUPPORTS_32BIT_KERNEL
  18 +       select SYS_SUPPORTS_KGDB
  19 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  20 +       select SYS_SUPPORTS_BIG_ENDIAN
  21 +       select GENERIC_GPIO
  22 +
  23  config MACH_ALCHEMY
  24         bool "Alchemy processor based machines"
  25
  26 diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
  27 --- linux-2.6.22/arch/mips/kernel/traps.c       2007-07-09 01:32:17.000000000 +0200
  28 +++ linux-2.6.22.new/arch/mips/kernel/traps.c   2007-07-11 02:32:39.000000000 +0200
  29 @@ -1074,11 +1074,23 @@ void *set_except_vector(int n, void *addr)
  30         unsigned long old_handler = exception_handlers[n];
  31
  32         exception_handlers[n] = handler;
  33 -       if (n == 0 && cpu_has_divec) {
  34 -               *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
  35 -                                                (0x03ffffff & (handler >> 2));
  36 -               flush_icache_range(ebase + 0x200, ebase + 0x204);
  37 -       }
  38 +       if (n == 0 && cpu_has_divec)
  39 +               if ((handler ^ (ebase + 4)) & 0xfc000000) {
  40 +                       /* lui k0, 0x0000 */
  41 +                       *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
  42 +                       /* ori k0, 0x0000 */
  43 +                       *(u32 *)(ebase + 0x204) =
  44 +                                       0x375a0000 | (handler & 0xffff);
  45 +                       /* jr k0 */
  46 +                       *(u32 *)(ebase + 0x208) = 0x03400008;
  47 +                       /* nop */
  48 +                       *(u32 *)(ebase + 0x20C) = 0x00000000;
  49 +                       flush_icache_range(ebase + 0x200, ebase + 0x210);
  50 +               } else {
  51 +                       *(volatile u32 *)(ebase + 0x200) =
  52 +                               0x08000000 | (0x03ffffff & (handler >> 2));
  53 +                       flush_icache_range(ebase + 0x200, ebase + 0x204);
  54 +               }
  55         return (void *)old_handler;
  56  }
  57
  58 diff -urN linux-2.6.22/arch/mips/Makefile linux-2.6.22.new/arch/mips/Makefile
  59 --- linux-2.6.22/arch/mips/Makefile     2007-07-09 01:32:17.000000000 +0200
  60 +++ linux-2.6.22.new/arch/mips/Makefile 2007-07-11 02:32:39.000000000 +0200
  61 @@ -158,6 +158,13 @@
  62  #
  63
  64  #
  65 +# Texas Instruments AR7
  66 +#
  67 +core-$(CONFIG_AR7)             += arch/mips/ar7/
  68 +cflags-$(CONFIG_AR7)           += -Iinclude/asm-mips/ar7
  69 +load-$(CONFIG_AR7)             += 0xffffffff94100000
  70 +
  71 +#
  72  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  73  #
  74  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  75 diff -urN linux-2.6.22.4/include/asm-mips/page.h linux-2.6.22.4.new/include/asm-mips/page.h
  76 --- linux-2.6.22.4/include/asm-mips/page.h      2007-08-21 12:33:06.000000000 +0800
  77 +++ linux-2.6.22.4.new/include/asm-mips/page.h  2007-09-13 15:13:00.000000000 +0800
  78 @@ -187,8 +187,10 @@
  79  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  80                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  81
  82 -#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE)
  83 -#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET)
  84 +#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
  85 +                                PHYS_OFFSET)
  86 +#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
  87 +                                PHYS_OFFSET)
  88
  89  #include <asm-generic/memory_model.h>
  90  #include <asm-generic/page.h>