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add support for serial console with different rate (specified by the boot loader...
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S
2 --- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-07 04:39:14.418226000 +0200
4 @@ -0,0 +1,69 @@
5 +#include <linux/config.h>
6 +#include <linux/threads.h>
7 +
8 +#include <asm/asm.h>
9 +#include <asm/cacheops.h>
10 +#include <asm/current.h>
11 +#include <asm/offset.h>
12 +#include <asm/processor.h>
13 +#include <asm/regdef.h>
14 +#include <asm/cachectl.h>
15 +#include <asm/mipsregs.h>
16 +#include <asm/stackframe.h>
17 +
18 +.text
19 +
20 +.set noreorder
21 +.set noat
22 +
23 +/* TLB Miss Vector */
24 +
25 +LEAF(jump_tlb_miss)
26 + .set mips2
27 + lui k0,0x9400
28 + ori k0,0
29 + jr k0
30 + nop
31 +END(jump_tlb_miss)
32 +
33 + /* Unused TLB Miss Vector */
34 +
35 +LEAF(jump_tlb_miss_unused)
36 + .set mips2
37 + lui k0,0x9400
38 + ori k0,0x80
39 + jr k0
40 + nop
41 +END(jump_tlb_miss_unused)
42 +
43 + /* Cache Error Vector */
44 +
45 +LEAF(jump_cache_error)
46 + .set mips2
47 + lui k0,0x9400
48 + ori k0,0x100
49 + jr k0
50 + nop
51 +END(jump_cache_error)
52 +
53 + /* General Exception */
54 +
55 +LEAF(jump_general_exception)
56 + .set mips2
57 + lui k0,0x9400
58 + ori k0,0x180
59 + jr k0
60 + nop
61 +END(jump_general_exception)
62 +
63 + /* Dedicated Interrupt */
64 +
65 +LEAF(jump_dedicated_interrupt)
66 + .set mips2
67 + lui k0,0x9400
68 + ori k0,0x200
69 + jr k0
70 + nop
71 +END(jump_dedicated_interrupt)
72 +
73 + .set at
74 diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c
75 --- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
76 +++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-07 04:39:14.418226000 +0200
77 @@ -0,0 +1,314 @@
78 +/*
79 + * -*- linux-c -*-
80 + * This file is subject to the terms and conditions of the GNU General Public
81 + * License. See the file "COPYING" in the main directory of this archive
82 + * for more details.
83 + *
84 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
85 + * Copyright (C) 2002 Texas Instruments, Inc.
86 + *
87 + */
88 +
89 +/*
90 + * This file takes care of the "memory hole" issue that exists with the standard
91 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
92 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
93 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
94 + *
95 + * -JAH
96 + */
97 +#include <linux/config.h>
98 +#include <linux/signal.h>
99 +#include <linux/sched.h>
100 +#include <linux/kernel.h>
101 +#include <linux/errno.h>
102 +#include <linux/string.h>
103 +#include <linux/types.h>
104 +#include <linux/ptrace.h>
105 +#include <linux/mman.h>
106 +#include <linux/mm.h>
107 +#include <linux/swap.h>
108 +#include <linux/smp.h>
109 +#include <linux/init.h>
110 +#ifdef CONFIG_BLK_DEV_INITRD
111 +#include <linux/blk.h>
112 +#endif /* CONFIG_BLK_DEV_INITRD */
113 +#include <linux/highmem.h>
114 +#include <linux/bootmem.h>
115 +
116 +#include <asm/processor.h>
117 +#include <asm/system.h>
118 +#include <asm/uaccess.h>
119 +#include <asm/pgtable.h>
120 +#include <asm/pgalloc.h>
121 +#include <asm/mmu_context.h>
122 +#include <asm/io.h>
123 +#include <asm/tlb.h>
124 +#include <asm/cpu.h>
125 +
126 +#define __MEMORY_START CONFIG_AR7_MEMORY
127 +
128 +#ifdef CONFIG_DISCONTIGMEM
129 +pg_data_t discontig_page_data[NR_NODES];
130 +bootmem_data_t discontig_node_bdata[NR_NODES];
131 +#endif
132 +
133 +static unsigned long totalram_pages;
134 +/* static unsigned long totalhigh_pages; */
135 +
136 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
137 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
138 +
139 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
140 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
141 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
142 +
143 +unsigned long bootmap_size;
144 +
145 +extern char *prom_getenv(char *envname);
146 +
147 +/*
148 + * We have upto 8 empty zeroed pages so we can map one of the right colour
149 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
150 + * where we have to avoid VCED / VECI exceptions for good performance at
151 + * any price. Since page is never written to after the initialization we
152 + * don't have to care about aliases on other CPUs.
153 + */
154 +
155 +static inline unsigned long setup_zero_pages(void)
156 +{
157 + unsigned long order, size;
158 + struct page *page;
159 + if(current_cpu_data.options & MIPS_CPU_VCE)
160 + order = 3;
161 + else
162 + order = 0;
163 +
164 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
165 +
166 + if (!empty_zero_page)
167 + panic("Oh boy, that early out of memory?");
168 +
169 + page = virt_to_page(empty_zero_page);
170 +
171 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
172 + set_bit(PG_reserved, &page->flags);
173 + set_page_count(page, 0);
174 + page++;
175 + }
176 +
177 + size = PAGE_SIZE << order;
178 + zero_page_mask = (size - 1) & PAGE_MASK;
179 + memset((void *)empty_zero_page, 0, size);
180 +
181 + return 1UL << order;
182 +}
183 +
184 +/*
185 + * paging_init() sets up the page tables
186 + *
187 + * This routines also unmaps the page at virtual kernel address 0, so
188 + * that we can trap those pesky NULL-reference errors in the kernel.
189 + */
190 +void __init paging_init(void)
191 +{
192 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
193 + unsigned long low, start_pfn;
194 +
195 + /* Initialize the entire pgd. */
196 + pgd_init((unsigned long)swapper_pg_dir);
197 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
198 +
199 +
200 + start_pfn = START_PFN;
201 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
202 + low = MAX_LOW_PFN;
203 +
204 + /* Avalanche DMA-able memory 0x14000000+memsize */
205 +
206 + zones_size[ZONE_DMA] = low - start_pfn;
207 +
208 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
209 +
210 +#ifdef CONFIG_DISCONTIGMEM
211 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
212 + zones_size[ZONE_NORMAL] = 0;
213 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
214 +#endif /* CONFIG_DISCONTIGMEM */
215 +
216 +}
217 +
218 +extern char _ftext, _etext, _fdata, _edata, _end;
219 +extern char __init_begin, __init_end;
220 +
221 +void __init mem_init(void)
222 +{
223 + int codesize, reservedpages, datasize, initsize;
224 + int tmp;
225 +
226 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
227 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
228 +
229 + /* free up the memory associated with Adam2 -
230 + * that is the, after the first page that is
231 + * reserved all the way up to the start of the kernel
232 + */
233 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
234 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
235 +
236 + /* this will put all low memory onto the freelists */
237 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
238 +
239 + /* Setup zeroed pages */
240 + totalram_pages -= setup_zero_pages();
241 +
242 +
243 +#ifdef CONFIG_DISCONTIGMEM
244 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
245 +#endif
246 + reservedpages = 0;
247 + for (tmp = 0; tmp < num_physpages; tmp++)
248 + /*
249 + * Only count reserved RAM pages
250 + */
251 + if (PageReserved(mem_map+tmp))
252 + reservedpages++;
253 +
254 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
255 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
256 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
257 +
258 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
259 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
260 + max_mapnr << (PAGE_SHIFT-10),
261 + codesize >> 10,
262 + reservedpages << (PAGE_SHIFT-10),
263 + datasize >> 10,
264 + initsize >> 10);
265 +
266 +}
267 +
268 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
269 +
270 +void avalanche_bootmem_init(void)
271 +{
272 + unsigned long start_pfn, max_pfn;
273 + unsigned long max_low_pfn;
274 + unsigned int memsize,memory_end,memory_start;
275 + char *memsize_str;
276 +
277 + memsize_str = prom_getenv("memsize");
278 + if (!memsize_str) {
279 + memsize = 0x02000000;
280 + } else {
281 + memsize = simple_strtol(memsize_str, NULL, 0);
282 + }
283 +
284 +
285 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
286 + memory_end = memory_start + memsize;
287 +
288 + /*
289 + * Find the highest memory page fram number we have available
290 + */
291 +
292 + max_pfn = PFN_DOWN(__pa(memory_end));
293 +
294 + /*
295 + * Determine the low and high memory ranges
296 + */
297 +
298 + max_low_pfn = max_pfn;
299 +
300 + /*
301 + * Partially used pages are not usable - thus we are
302 + * rounding upwards:
303 + */
304 +
305 + start_pfn = PFN_UP(__pa(&_end));
306 +
307 + /*
308 + * Find a proper area for the bootmem bitmap. After this
309 + * bootstrap step all allocations (until the page allocator is
310 + * intact) must be done via bootmem_alloc().
311 + */
312 +
313 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
314 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
315 +
316 +
317 + /*
318 + * Register fully available low RAM pages with the bootmem allocator.
319 + */
320 +
321 + {
322 + unsigned long curr_pfn, last_pfn, pages;
323 +
324 + /*
325 + * We are rounding up the start address of usable memory:
326 + */
327 + curr_pfn = PFN_UP(__MEMORY_START);
328 +
329 + /*
330 + * ... and at the end of the usable range downwards:
331 + */
332 + last_pfn = PFN_DOWN(__pa(memory_end));
333 +
334 + if (last_pfn > max_low_pfn)
335 + last_pfn = max_low_pfn;
336 +
337 + pages = last_pfn - curr_pfn;
338 +
339 +
340 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
341 + PFN_PHYS(pages));
342 + }
343 +
344 + /*
345 + * Reserve the kernel text and
346 + * Reserve the bootmem bitmap. We do this in two steps (first step
347 + * was init_bootmem()), because this catches the (definitely buggy)
348 + * case of us accidentally initializing the bootmem allocator with
349 + * an invalid RAM area.
350 + */
351 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
352 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
353 +
354 + /*
355 + * reserve physical page 0 - it's a special BIOS page on many boxes,
356 + * enabling clean reboots, SMP operation, laptop functions.
357 + */
358 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
359 +}
360 +
361 +extern char __init_begin, __init_end;
362 +
363 +void free_initmem(void)
364 +{
365 + unsigned long addr;
366 + // prom_free_prom_memory ();
367 +
368 + addr = (unsigned long) &__init_begin;
369 + while (addr < (unsigned long) &__init_end) {
370 + ClearPageReserved(virt_to_page(addr));
371 + set_page_count(virt_to_page(addr), 1);
372 + free_page(addr);
373 + totalram_pages++;
374 + addr += PAGE_SIZE;
375 + }
376 + printk("Freeing unused kernel memory: %dk freed\n",
377 + (&__init_end - &__init_begin) >> 10);
378 +}
379 +
380 +void si_meminfo(struct sysinfo *val)
381 +{
382 + val->totalram = totalram_pages;
383 + val->sharedram = 0;
384 + val->freeram = nr_free_pages();
385 + val->bufferram = atomic_read(&buffermem_pages);
386 + val->totalhigh = 0;
387 + val->freehigh = nr_free_highpages();
388 + val->mem_unit = PAGE_SIZE;
389 +
390 + return;
391 +}
392 diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile
393 --- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
394 +++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-07 04:39:14.417226000 +0200
395 @@ -0,0 +1,13 @@
396 +.S.s:
397 + $(CPP) $(AFLAGS) $< -o $*.s
398 +
399 +.S.o:
400 + $(CC) $(AFLAGS) -c $< -o $*.o
401 +
402 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
403 +
404 +O_TARGET := avalanche.o
405 +
406 +obj-y += avalanche_paging.o avalanche_jump.o
407 +
408 +include $(TOPDIR)/Rules.make
409 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
410 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
411 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-07 04:39:14.419226000 +0200
412 @@ -0,0 +1,64 @@
413 +/*
414 + * Carsten Langgaard, carstenl@mips.com
415 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
416 + *
417 + * This program is free software; you can distribute it and/or modify it
418 + * under the terms of the GNU General Public License (Version 2) as
419 + * published by the Free Software Foundation.
420 + *
421 + * This program is distributed in the hope it will be useful, but WITHOUT
422 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
423 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
424 + * for more details.
425 + *
426 + * You should have received a copy of the GNU General Public License along
427 + * with this program; if not, write to the Free Software Foundation, Inc.,
428 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
429 + *
430 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
431 + */
432 +#include <linux/init.h>
433 +#include <linux/string.h>
434 +
435 +#include <asm/bootinfo.h>
436 +
437 +extern int prom_argc;
438 +extern int *_prom_argv;
439 +
440 +/*
441 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
442 + * This macro take care of sign extension.
443 + */
444 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
445 +
446 +char arcs_cmdline[CL_SIZE];
447 +
448 +char * __init prom_getcmdline(void)
449 +{
450 + return &(arcs_cmdline[0]);
451 +}
452 +
453 +
454 +void __init prom_init_cmdline(void)
455 +{
456 + char *cp;
457 + int actr;
458 +
459 + actr = 1; /* Always ignore argv[0] */
460 +
461 + cp = &(arcs_cmdline[0]);
462 +#ifdef CONFIG_CMDLINE_BOOL
463 + strcpy(cp, CONFIG_CMDLINE);
464 + cp += strlen(CONFIG_CMDLINE);
465 + *cp++ = ' ';
466 +#endif
467 + while(actr < prom_argc) {
468 + strcpy(cp, prom_argv(actr));
469 + cp += strlen(prom_argv(actr));
470 + *cp++ = ' ';
471 + actr++;
472 + }
473 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
474 + --cp;
475 + *cp = '\0';
476 +}
477 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
478 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
479 +++ linux.dev/arch/mips/ar7/init.c 2005-07-07 04:39:14.419226000 +0200
480 @@ -0,0 +1,144 @@
481 +/*
482 + * Carsten Langgaard, carstenl@mips.com
483 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
484 + *
485 + * This program is free software; you can distribute it and/or modify it
486 + * under the terms of the GNU General Public License (Version 2) as
487 + * published by the Free Software Foundation.
488 + *
489 + * This program is distributed in the hope it will be useful, but WITHOUT
490 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
491 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
492 + * for more details.
493 + *
494 + * You should have received a copy of the GNU General Public License along
495 + * with this program; if not, write to the Free Software Foundation, Inc.,
496 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
497 + *
498 + * PROM library initialisation code.
499 + */
500 +#include <linux/config.h>
501 +#include <linux/init.h>
502 +#include <linux/string.h>
503 +#include <linux/kernel.h>
504 +
505 +#include <asm/io.h>
506 +#include <asm/mips-boards/prom.h>
507 +#include <asm/mips-boards/generic.h>
508 +
509 +/* Environment variable */
510 +typedef struct {
511 + char *name;
512 + char *val;
513 +} t_env_var;
514 +
515 +int prom_argc;
516 +int *_prom_argv, *_prom_envp;
517 +
518 +/* max # of Adam2 environment variables */
519 +#define MAX_ENV_ENTRY 80
520 +
521 +static t_env_var local_envp[MAX_ENV_ENTRY];
522 +
523 +int init_debug = 0;
524 +
525 +char *prom_getenv(char *envname)
526 +{
527 + /*
528 + * Return a pointer to the given environment variable.
529 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
530 + * in the PROM structures are only 32-bit, so we need some
531 + * workarounds, if we are running in 64-bit mode.
532 + */
533 + int i, index=0;
534 + t_env_var *env = (t_env_var *) local_envp;
535 +
536 + i = strlen(envname);
537 + while (env->name) {
538 + if(strncmp(envname, env->name, i) == 0) {
539 + return(env->val);
540 + }
541 + env++;
542 + }
543 +
544 + return NULL;
545 +}
546 +
547 +static inline unsigned char str2hexnum(unsigned char c)
548 +{
549 + if (c >= '0' && c <= '9')
550 + return c - '0';
551 + if (c >= 'a' && c <= 'f')
552 + return c - 'a' + 10;
553 + return 0; /* foo */
554 +}
555 +
556 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
557 +{
558 + int i;
559 +
560 + for (i = 0; i < 6; i++) {
561 + unsigned char num;
562 +
563 + if((*str == '.') || (*str == ':'))
564 + str++;
565 + num = str2hexnum(*str++) << 4;
566 + num |= (str2hexnum(*str++));
567 + ea[i] = num;
568 + }
569 +}
570 +
571 +int get_ethernet_addr(char *ethernet_addr)
572 +{
573 + char *ethaddr_str;
574 +
575 + ethaddr_str = prom_getenv("ethaddr");
576 + if (!ethaddr_str) {
577 + printk("ethaddr not set in boot prom\n");
578 + return -1;
579 + }
580 + str2eaddr(ethernet_addr, ethaddr_str);
581 +
582 + if (init_debug > 1) {
583 + int i;
584 + printk("get_ethernet_addr: ");
585 + for (i=0; i<5; i++)
586 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
587 + printk("%02x\n", *(ethernet_addr+i));
588 + }
589 +
590 + return 0;
591 +}
592 +
593 +int __init prom_init(int argc, char **argv, char **envp)
594 +{
595 + int i;
596 + t_env_var *env = (t_env_var *) envp;
597 +
598 + prom_argc = argc;
599 + _prom_argv = (int *)argv;
600 + _prom_envp = (int *)envp;
601 +
602 + /* Copy what we need locally so we are not dependent on
603 + * bootloader RAM. In Adam2, the environment parameters
604 + * are in flash but the table that references them is in
605 + * RAM
606 + */
607 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
608 + if (env->name) {
609 + local_envp[i].name = env->name;
610 + local_envp[i].val = env->val;
611 + } else {
612 + local_envp[i].name = NULL;
613 + local_envp[i].val = NULL;
614 + }
615 + }
616 +
617 + set_io_port_base(0);
618 +
619 + prom_printf("\nLINUX started...\n");
620 + prom_init_cmdline();
621 + prom_meminit();
622 +
623 + return 0;
624 +}
625 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
626 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
627 +++ linux.dev/arch/mips/ar7/irq.c 2005-07-07 04:39:14.420226000 +0200
628 @@ -0,0 +1,669 @@
629 +/*
630 + * Nitin Dhingra, iamnd@ti.com
631 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
632 + *
633 + * ########################################################################
634 + *
635 + * This program is free software; you can distribute it and/or modify it
636 + * under the terms of the GNU General Public License (Version 2) as
637 + * published by the Free Software Foundation.
638 + *
639 + * This program is distributed in the hope it will be useful, but WITHOUT
640 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
641 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
642 + * for more details.
643 + *
644 + * You should have received a copy of the GNU General Public License along
645 + * with this program; if not, write to the Free Software Foundation, Inc.,
646 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
647 + *
648 + * ########################################################################
649 + *
650 + * Routines for generic manipulation of the interrupts found on the Texas
651 + * Instruments avalanche board
652 + *
653 + */
654 +
655 +#include <linux/config.h>
656 +#include <linux/init.h>
657 +#include <linux/sched.h>
658 +#include <linux/slab.h>
659 +#include <linux/interrupt.h>
660 +#include <linux/kernel_stat.h>
661 +#include <linux/proc_fs.h>
662 +#include <asm/irq.h>
663 +#include <asm/mips-boards/prom.h>
664 +#include <asm/ar7/ar7.h>
665 +#include <asm/ar7/avalanche_intc.h>
666 +#include <asm/gdb-stub.h>
667 +
668 +
669 +#define shutdown_avalanche_irq disable_avalanche_irq
670 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
671 +
672 +static unsigned int startup_avalanche_irq(unsigned int irq);
673 +static void end_avalanche_irq(unsigned int irq);
674 +void enable_avalanche_irq(unsigned int irq_nr);
675 +void disable_avalanche_irq(unsigned int irq_nr);
676 +
677 +static struct hw_interrupt_type avalanche_irq_type = {
678 + "TI AVALANCHE",
679 + startup_avalanche_irq,
680 + shutdown_avalanche_irq,
681 + enable_avalanche_irq,
682 + disable_avalanche_irq,
683 + mask_and_ack_avalanche_irq,
684 + end_avalanche_irq,
685 + NULL
686 +};
687 +
688 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
689 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
690 +
691 +
692 +unsigned long spurious_count = 0;
693 +
694 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
695 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
696 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
697 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
698 +
699 +extern asmlinkage void mipsIRQ(void);
700 +
701 +
702 +/*
703 + * The avalanche/MIPS interrupt line numbers are used to represent the
704 + * interrupts within the irqaction arrays. The index notation is
705 + * is as follows:
706 + *
707 + * 0-7 MIPS CPU Exceptions (HW/SW)
708 + * 8-47 Primary Interrupts (Avalanche)
709 + * 48-79 Secondary Interrupts (Avalanche)
710 + *
711 + */
712 +
713 +
714 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
715 +{
716 + NULL, NULL, NULL, NULL,
717 + NULL, NULL, NULL, NULL,
718 + NULL, NULL, NULL, NULL,
719 + NULL, NULL, NULL, NULL,
720 + NULL, NULL, NULL, NULL,
721 + NULL, NULL, NULL, NULL,
722 + NULL, NULL, NULL, NULL,
723 + NULL, NULL, NULL, NULL,
724 + NULL, NULL, NULL, NULL,
725 + NULL, NULL, NULL, NULL
726 +};
727 +
728 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
729 +{
730 + NULL, NULL, NULL, NULL,
731 + NULL, NULL, NULL, NULL,
732 + NULL, NULL, NULL, NULL,
733 + NULL, NULL, NULL, NULL,
734 + NULL, NULL, NULL, NULL,
735 + NULL, NULL, NULL, NULL,
736 + NULL, NULL, NULL, NULL,
737 + NULL, NULL, NULL, NULL
738 +};
739 +
740 +/*
741 + This remaps interrupts to exist on other channels than the default
742 + channels. essentially we can use the line # as the index for this
743 + array
744 + */
745 +
746 +
747 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
748 +unsigned long uni_secondary_interrupt = 0;
749 +
750 +static struct irqaction r4ktimer_action = {
751 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
752 +};
753 +
754 +static struct irqaction *irq_action[8] = {
755 + NULL, /* SW int 0 */
756 + NULL, /* SW int 1 */
757 + NULL, /* HW int 0 */
758 + NULL,
759 + NULL,
760 + NULL, /* HW int 3 */
761 + NULL, /* HW int 4 */
762 + &r4ktimer_action /* HW int 5 */
763 +};
764 +
765 +static void end_avalanche_irq(unsigned int irq)
766 +{
767 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
768 + enable_avalanche_irq(irq);
769 +}
770 +
771 +void disable_avalanche_irq(unsigned int irq_nr)
772 +{
773 + unsigned long flags;
774 + unsigned long chan_nr=0;
775 + unsigned long int_bit=0;
776 +
777 + if(irq_nr >= AVALANCHE_INT_END)
778 + {
779 + printk("whee, invalid irq_nr %d\n", irq_nr);
780 + panic("IRQ, you lose...");
781 + }
782 +
783 + save_and_cli(flags);
784 +
785 +
786 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
787 + {
788 + /* disable mips exception */
789 +
790 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
791 + change_c0_status(ST0_IM,int_bit);
792 + restore_flags(flags);
793 + return;
794 + }
795 +
796 + /* irq_nr represents the line number for the interrupt. We must
797 + * disable the channel number associated with that line number.
798 + */
799 +
800 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
801 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
802 + else
803 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
804 +
805 + /* disable the interrupt channel bit */
806 +
807 + /* primary interrupt #'s 0-31 */
808 +
809 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
810 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
811 +
812 + /* primary interrupt #'s 32-39 */
813 +
814 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
815 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
816 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
817 +
818 + else /* secondary interrupt #'s 0-31 */
819 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
820 +
821 + restore_flags(flags);
822 +}
823 +
824 +void enable_avalanche_irq(unsigned int irq_nr)
825 +{
826 + unsigned long flags;
827 + unsigned long chan_nr=0;
828 + unsigned long int_bit=0;
829 +
830 + if(irq_nr > AVALANCHE_INT_END) {
831 + printk("whee, invalid irq_nr %d\n", irq_nr);
832 + panic("IRQ, you lose...");
833 + }
834 +
835 + save_and_cli(flags);
836 +
837 +
838 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
839 + {
840 + /* Enable MIPS exceptions */
841 + int_bit = read_c0_status();
842 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
843 + restore_flags(flags);
844 + return;
845 + }
846 +
847 + /* irq_nr represents the line number for the interrupt. We must
848 + * disable the channel number associated with that line number.
849 + */
850 +
851 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
852 + chan_nr = AVINTNUM(irq_nr);
853 + else
854 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
855 +
856 + /* enable the interrupt channel bit */
857 +
858 + /* primary interrupt #'s 0-31 */
859 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
860 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
861 +
862 + /* primary interrupt #'s 32 throuth 39 */
863 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
864 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
865 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
866 +
867 + else /* secondary interrupt #'s 0-31 */
868 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
869 +
870 + restore_flags(flags);
871 +}
872 +
873 +static unsigned int startup_avalanche_irq(unsigned int irq)
874 +{
875 + enable_avalanche_irq(irq);
876 + return 0; /* never anything pending */
877 +}
878 +
879 +
880 +int get_irq_list(char *buf)
881 +{
882 + int i, len = 0;
883 + int num = 0;
884 + struct irqaction *action;
885 +
886 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
887 + {
888 + action = irq_action[i];
889 + if (!action)
890 + continue;
891 + len += sprintf(buf+len, "%2d: %8d %c %s",
892 + num, kstat.irqs[0][num],
893 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
894 + action->name);
895 + for (action=action->next; action; action = action->next) {
896 + len += sprintf(buf+len, ",%s %s",
897 + (action->flags & SA_INTERRUPT) ? " +" : "",
898 + action->name);
899 + }
900 + len += sprintf(buf+len, " [MIPS interrupt]\n");
901 + }
902 +
903 +
904 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
905 + {
906 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
907 + action = hw0_irq_action_primary[i];
908 + else
909 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
910 + if (!action)
911 + continue;
912 + len += sprintf(buf+len, "%2d: %8d %c %s",
913 + num, kstat.irqs[0][ LNXINTNUM(i) ],
914 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
915 + action->name);
916 +
917 + for (action=action->next; action; action = action->next)
918 + {
919 + len += sprintf(buf+len, ",%s %s",
920 + (action->flags & SA_INTERRUPT) ? " +" : "",
921 + action->name);
922 + }
923 +
924 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
925 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
926 + else
927 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
928 +
929 + }
930 +
931 + return len;
932 +}
933 +
934 +int request_irq(unsigned int irq,
935 + void (*handler)(int, void *, struct pt_regs *),
936 + unsigned long irqflags,
937 + const char * devname,
938 + void *dev_id)
939 +{
940 + struct irqaction *action;
941 +
942 + if (irq > AVALANCHE_INT_END)
943 + return -EINVAL;
944 + if (!handler)
945 + return -EINVAL;
946 +
947 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
948 + if(!action)
949 + return -ENOMEM;
950 +
951 + action->handler = handler;
952 + action->flags = irqflags;
953 + action->mask = 0;
954 + action->name = devname;
955 + irq_desc_ti[irq].action = action;
956 + action->dev_id = dev_id;
957 +
958 + action->next = 0;
959 +
960 + if(irq < MIPS_EXCEPTION_OFFSET)
961 + {
962 + irq_action[irq] = action;
963 + enable_avalanche_irq(irq);
964 + return 0;
965 + }
966 +
967 + if(irq < AVALANCHE_INT_END_PRIMARY)
968 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
969 + else
970 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
971 +
972 + enable_avalanche_irq(irq);
973 +
974 + return 0;
975 +}
976 +
977 +void free_irq(unsigned int irq, void *dev_id)
978 +{
979 + struct irqaction *action;
980 +
981 + if (irq > AVALANCHE_INT_END) {
982 + printk("Trying to free IRQ%d\n",irq);
983 + return;
984 + }
985 +
986 + if(irq < MIPS_EXCEPTION_OFFSET)
987 + {
988 + action = irq_action[irq];
989 + irq_action[irq] = NULL;
990 + irq_desc_ti[irq].action = NULL;
991 + disable_avalanche_irq(irq);
992 + kfree(action);
993 + return;
994 + }
995 +
996 + if(irq < AVALANCHE_INT_END_PRIMARY) {
997 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
998 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
999 + irq_desc_ti[irq].action = NULL;
1000 + }
1001 + else {
1002 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1003 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1004 + irq_desc_ti[irq].action = NULL;
1005 + }
1006 +
1007 + disable_avalanche_irq(irq);
1008 + kfree(action);
1009 +}
1010 +
1011 +#ifdef CONFIG_KGDB
1012 +extern void breakpoint(void);
1013 +extern int remote_debug;
1014 +#endif
1015 +
1016 +//void init_IRQ(void) __init;
1017 +void __init init_IRQ(void)
1018 +{
1019 + int i;
1020 +
1021 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1022 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1023 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1024 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1025 +
1026 + /* Disable interrupts and clear pending
1027 + */
1028 +
1029 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1030 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1031 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1032 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1033 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1034 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1035 +
1036 +
1037 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1038 + /* hack for speeding up the pacing. */
1039 + printk("the pacing pre-scalar has been set as 600.\n");
1040 + avalanche_hw0_ipaceregs->ipacep = 600;
1041 + /* Channel to line mapping, Line to Channel mapping */
1042 +
1043 + for(i = 0; i < 40; i++)
1044 + avalanche_int_set(i,i);
1045 +
1046 + /* Now safe to set the exception vector. */
1047 + set_except_vector(0, mipsIRQ);
1048 +
1049 + /* Setup the IRQ description array. These will be mapped
1050 + * as flat interrupts numbers. The mapping is as follows
1051 + *
1052 + * 0-7 MIPS CPU Exceptions (HW/SW)
1053 + * 8-46 Primary Interrupts (Avalanche)
1054 + * 47-78 Secondary Interrupts (Avalanche)
1055 + */
1056 +
1057 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1058 + {
1059 + irq_desc_ti[i].status = IRQ_DISABLED;
1060 + irq_desc_ti[i].action = 0;
1061 + irq_desc_ti[i].depth = 1;
1062 + irq_desc_ti[i].handler = &avalanche_irq_type;
1063 + }
1064 +
1065 +#ifdef CONFIG_KGDB
1066 + if (remote_debug)
1067 + {
1068 + set_debug_traps();
1069 + breakpoint();
1070 + }
1071 +#endif
1072 +}
1073 +
1074 +
1075 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1076 +{
1077 + struct irqaction *action;
1078 + int irq, cpu = smp_processor_id();
1079 + unsigned long int_line_number,status;
1080 + int i,secondary = 0;
1081 + int chan_nr=0;
1082 +
1083 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1084 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1085 +
1086 +
1087 + if(chan_nr < 32)
1088 + {
1089 + if( chan_nr != uni_secondary_interrupt)
1090 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1091 +
1092 + }
1093 +
1094 + if((chan_nr < 40) && (chan_nr > 31))
1095 + {
1096 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1097 + }
1098 +
1099 +
1100 + /* If the Priority Interrupt Index Register returns 40 then no
1101 + * interrupts are pending
1102 + */
1103 +
1104 + if(chan_nr == 40)
1105 + return;
1106 +
1107 + if(chan_nr == uni_secondary_interrupt)
1108 + {
1109 + status = avalanche_hw0_ecregs->exsr;
1110 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1111 + {
1112 + if (status & 1<<i)
1113 + {
1114 + /* clear secondary interrupt */
1115 + avalanche_hw0_ecregs->excr = 1 << i;
1116 + break;
1117 + }
1118 + }
1119 + irq = i;
1120 + secondary = 1;
1121 +
1122 + /* clear the universal secondary interrupt */
1123 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1124 +
1125 + }
1126 + else
1127 + irq = chan_nr;
1128 +
1129 + /* Suraj Add code to clear secondary interrupt */
1130 +
1131 + if(secondary)
1132 + action = hw0_irq_action_secondary[irq];
1133 + else
1134 + action = hw0_irq_action_primary[irq];
1135 +
1136 + /* if action == NULL, then we don't have a handler for the irq */
1137 +
1138 + if ( action == NULL ) {
1139 + printk("No handler for hw0 irq: %i\n", irq);
1140 + return;
1141 + }
1142 +
1143 + irq_enter(cpu,irq);
1144 + if(secondary)
1145 + {
1146 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1147 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1148 + }
1149 + else
1150 + {
1151 + kstat.irqs[0][irq + 8]++;
1152 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1153 + }
1154 +
1155 + irq_exit(cpu,irq);
1156 +
1157 + if(softirq_pending(cpu))
1158 + do_softirq();
1159 +
1160 + return;
1161 +}
1162 +
1163 +void avalanche_int_set(int channel, int line)
1164 +{
1165 + switch(channel)
1166 + {
1167 + case(0):
1168 + avalanche_hw0_chregs->cintnr0 = line;
1169 + break;
1170 + case(1):
1171 + avalanche_hw0_chregs->cintnr1 = line;
1172 + break;
1173 + case(2):
1174 + avalanche_hw0_chregs->cintnr2 = line;
1175 + break;
1176 + case(3):
1177 + avalanche_hw0_chregs->cintnr3 = line;
1178 + break;
1179 + case(4):
1180 + avalanche_hw0_chregs->cintnr4 = line;
1181 + break;
1182 + case(5):
1183 + avalanche_hw0_chregs->cintnr5 = line;
1184 + break;
1185 + case(6):
1186 + avalanche_hw0_chregs->cintnr6 = line;
1187 + break;
1188 + case(7):
1189 + avalanche_hw0_chregs->cintnr7 = line;
1190 + break;
1191 + case(8):
1192 + avalanche_hw0_chregs->cintnr8 = line;
1193 + break;
1194 + case(9):
1195 + avalanche_hw0_chregs->cintnr9 = line;
1196 + break;
1197 + case(10):
1198 + avalanche_hw0_chregs->cintnr10 = line;
1199 + break;
1200 + case(11):
1201 + avalanche_hw0_chregs->cintnr11 = line;
1202 + break;
1203 + case(12):
1204 + avalanche_hw0_chregs->cintnr12 = line;
1205 + break;
1206 + case(13):
1207 + avalanche_hw0_chregs->cintnr13 = line;
1208 + break;
1209 + case(14):
1210 + avalanche_hw0_chregs->cintnr14 = line;
1211 + break;
1212 + case(15):
1213 + avalanche_hw0_chregs->cintnr15 = line;
1214 + break;
1215 + case(16):
1216 + avalanche_hw0_chregs->cintnr16 = line;
1217 + break;
1218 + case(17):
1219 + avalanche_hw0_chregs->cintnr17 = line;
1220 + break;
1221 + case(18):
1222 + avalanche_hw0_chregs->cintnr18 = line;
1223 + break;
1224 + case(19):
1225 + avalanche_hw0_chregs->cintnr19 = line;
1226 + break;
1227 + case(20):
1228 + avalanche_hw0_chregs->cintnr20 = line;
1229 + break;
1230 + case(21):
1231 + avalanche_hw0_chregs->cintnr21 = line;
1232 + break;
1233 + case(22):
1234 + avalanche_hw0_chregs->cintnr22 = line;
1235 + break;
1236 + case(23):
1237 + avalanche_hw0_chregs->cintnr23 = line;
1238 + break;
1239 + case(24):
1240 + avalanche_hw0_chregs->cintnr24 = line;
1241 + break;
1242 + case(25):
1243 + avalanche_hw0_chregs->cintnr25 = line;
1244 + break;
1245 + case(26):
1246 + avalanche_hw0_chregs->cintnr26 = line;
1247 + break;
1248 + case(27):
1249 + avalanche_hw0_chregs->cintnr27 = line;
1250 + break;
1251 + case(28):
1252 + avalanche_hw0_chregs->cintnr28 = line;
1253 + break;
1254 + case(29):
1255 + avalanche_hw0_chregs->cintnr29 = line;
1256 + break;
1257 + case(30):
1258 + avalanche_hw0_chregs->cintnr30 = line;
1259 + break;
1260 + case(31):
1261 + avalanche_hw0_chregs->cintnr31 = line;
1262 + break;
1263 + case(32):
1264 + avalanche_hw0_chregs->cintnr32 = line;
1265 + break;
1266 + case(33):
1267 + avalanche_hw0_chregs->cintnr33 = line;
1268 + break;
1269 + case(34):
1270 + avalanche_hw0_chregs->cintnr34 = line;
1271 + break;
1272 + case(35):
1273 + avalanche_hw0_chregs->cintnr35 = line;
1274 + break;
1275 + case(36):
1276 + avalanche_hw0_chregs->cintnr36 = line;
1277 + break;
1278 + case(37):
1279 + avalanche_hw0_chregs->cintnr37 = line;
1280 + break;
1281 + case(38):
1282 + avalanche_hw0_chregs->cintnr38 = line;
1283 + break;
1284 + case(39):
1285 + avalanche_hw0_chregs->cintnr39 = line;
1286 + break;
1287 + default:
1288 + printk("Error: Unknown Avalanche interrupt channel\n");
1289 + }
1290 +
1291 + line_to_channel[line] = channel; /* Suraj check */
1292 +
1293 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1294 + uni_secondary_interrupt = line;
1295 +
1296 +}
1297 +
1298 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
1299 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
1300 +++ linux.dev/arch/mips/ar7/Makefile 2005-07-07 04:39:14.417226000 +0200
1301 @@ -0,0 +1,12 @@
1302 +.S.s:
1303 + $(CPP) $(AFLAGS) $< -o $*.s
1304 +
1305 +.S.o:
1306 + $(CC) $(AFLAGS) -c $< -o $*.o
1307 +
1308 +O_TARGET := ar7.o
1309 +
1310 +obj-y := tnetd73xx_misc.o
1311 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
1312 +
1313 +include $(TOPDIR)/Rules.make
1314 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
1315 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1316 +++ linux.dev/arch/mips/ar7/memory.c 2005-07-07 04:39:14.420226000 +0200
1317 @@ -0,0 +1,130 @@
1318 +/*
1319 + * Carsten Langgaard, carstenl@mips.com
1320 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1321 + *
1322 + * ########################################################################
1323 + *
1324 + * This program is free software; you can distribute it and/or modify it
1325 + * under the terms of the GNU General Public License (Version 2) as
1326 + * published by the Free Software Foundation.
1327 + *
1328 + * This program is distributed in the hope it will be useful, but WITHOUT
1329 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1330 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1331 + * for more details.
1332 + *
1333 + * You should have received a copy of the GNU General Public License along
1334 + * with this program; if not, write to the Free Software Foundation, Inc.,
1335 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1336 + *
1337 + * ########################################################################
1338 + *
1339 + * PROM library functions for acquiring/using memory descriptors given to
1340 + * us from the YAMON.
1341 + *
1342 + */
1343 +#include <linux/config.h>
1344 +#include <linux/init.h>
1345 +#include <linux/mm.h>
1346 +#include <linux/bootmem.h>
1347 +
1348 +#include <asm/bootinfo.h>
1349 +#include <asm/page.h>
1350 +#include <asm/mips-boards/prom.h>
1351 +#include <asm/ar7/ar7.h>
1352 +
1353 +enum yamon_memtypes {
1354 + yamon_dontuse,
1355 + yamon_prom,
1356 + yamon_free,
1357 +};
1358 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1359 +
1360 +/* References to section boundaries */
1361 +extern char _end;
1362 +
1363 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1364 +
1365 +
1366 +struct prom_pmemblock * __init prom_getmdesc(void)
1367 +{
1368 + char *memsize_str;
1369 + unsigned int memsize;
1370 +
1371 + memsize_str = prom_getenv("memsize");
1372 + if (!memsize_str) {
1373 + memsize = 0x02000000;
1374 + } else {
1375 + memsize = simple_strtol(memsize_str, NULL, 0);
1376 + }
1377 +
1378 + memset(mdesc, 0, sizeof(mdesc));
1379 +
1380 + mdesc[0].type = yamon_dontuse;
1381 + mdesc[0].base = 0x00000000;
1382 + mdesc[0].size = AVALANCHE_SDRAM_BASE;
1383 +
1384 + mdesc[1].type = yamon_prom;
1385 + mdesc[1].base = AVALANCHE_SDRAM_BASE;
1386 + mdesc[1].size = 0x00020000;
1387 +
1388 + mdesc[2].type = yamon_free;
1389 + mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
1390 + mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
1391 +
1392 + return &mdesc[0];
1393 +}
1394 +
1395 +static int __init prom_memtype_classify (unsigned int type)
1396 +{
1397 + switch (type) {
1398 + case yamon_free:
1399 + return BOOT_MEM_RAM;
1400 + case yamon_prom:
1401 + return BOOT_MEM_ROM_DATA;
1402 + default:
1403 + return BOOT_MEM_RESERVED;
1404 + }
1405 +}
1406 +
1407 +void __init prom_meminit(void)
1408 +{
1409 + struct prom_pmemblock *p;
1410 +
1411 + p = prom_getmdesc();
1412 +
1413 + while (p->size) {
1414 + long type;
1415 + unsigned long base, size;
1416 +
1417 + type = prom_memtype_classify (p->type);
1418 + base = p->base;
1419 + size = p->size;
1420 +
1421 + add_memory_region(base, size, type);
1422 + p++;
1423 + }
1424 +}
1425 +
1426 +void __init prom_free_prom_memory (void)
1427 +{
1428 + int i;
1429 + unsigned long freed = 0;
1430 + unsigned long addr;
1431 +
1432 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1433 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1434 + continue;
1435 +
1436 + addr = boot_mem_map.map[i].addr;
1437 + while (addr < boot_mem_map.map[i].addr
1438 + + boot_mem_map.map[i].size) {
1439 + ClearPageReserved(virt_to_page(__va(addr)));
1440 + set_page_count(virt_to_page(__va(addr)), 1);
1441 + free_page((unsigned long)__va(addr));
1442 + addr += PAGE_SIZE;
1443 + freed += PAGE_SIZE;
1444 + }
1445 + }
1446 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1447 +}
1448 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1449 --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1450 +++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-07 04:39:14.421226000 +0200
1451 @@ -0,0 +1,120 @@
1452 +/*
1453 + * Carsten Langgaard, carstenl@mips.com
1454 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1455 + *
1456 + * ########################################################################
1457 + *
1458 + * This program is free software; you can distribute it and/or modify it
1459 + * under the terms of the GNU General Public License (Version 2) as
1460 + * published by the Free Software Foundation.
1461 + *
1462 + * This program is distributed in the hope it will be useful, but WITHOUT
1463 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1464 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1465 + * for more details.
1466 + *
1467 + * You should have received a copy of the GNU General Public License along
1468 + * with this program; if not, write to the Free Software Foundation, Inc.,
1469 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1470 + *
1471 + * ########################################################################
1472 + *
1473 + * Interrupt exception dispatch code.
1474 + *
1475 + */
1476 +#include <linux/config.h>
1477 +
1478 +#include <asm/asm.h>
1479 +#include <asm/mipsregs.h>
1480 +#include <asm/regdef.h>
1481 +#include <asm/stackframe.h>
1482 +
1483 +/* A lot of complication here is taken away because:
1484 + *
1485 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1486 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1487 + * common case is one pending IRQ so optimize in that direction.
1488 + *
1489 + * 2) We need not check against bits in the status register IRQ mask, that
1490 + * would make this routine slow as hell.
1491 + *
1492 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1493 + * between like BSD spl() brain-damage.
1494 + *
1495 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1496 + * IRQs which we don't use at all and all external interrupt sources are
1497 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1498 + *
1499 + * MIPS IRQ Source
1500 + * -------- ------
1501 + * 0 Software (ignored)
1502 + * 1 Software (ignored)
1503 + * 2 Combined hardware interrupt (hw0)
1504 + * 3 Hardware (ignored)
1505 + * 4 Hardware (ignored)
1506 + * 5 Hardware (ignored)
1507 + * 6 Hardware (ignored)
1508 + * 7 R4k timer (what we use)
1509 + *
1510 + * Note: On the SEAD board thing are a little bit different.
1511 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1512 + * wired to UART1.
1513 + *
1514 + * We handle the IRQ according to _our_ priority which is:
1515 + *
1516 + * Highest ---- R4k Timer
1517 + * Lowest ---- Combined hardware interrupt
1518 + *
1519 + * then we just return, if multiple IRQs are pending then we will just take
1520 + * another exception, big deal.
1521 + */
1522 +
1523 +.text
1524 +.set noreorder
1525 +.set noat
1526 + .align 5
1527 +NESTED(mipsIRQ, PT_SIZE, sp)
1528 + SAVE_ALL
1529 + CLI
1530 + .set at
1531 +
1532 + mfc0 s0, CP0_CAUSE # get irq bits
1533 +
1534 + /* First we check for r4k counter/timer IRQ. */
1535 + andi a0, s0, CAUSEF_IP7
1536 + beq a0, zero, 1f
1537 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1538 +
1539 + /* Wheee, a timer interrupt. */
1540 + move a0, sp
1541 + jal ar7_timer_interrupt
1542 + nop
1543 +
1544 + j ret_from_irq
1545 + nop
1546 +
1547 + 1:
1548 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1549 + nop
1550 +
1551 + /* Wheee, combined hardware level zero interrupt. */
1552 + jal avalanche_hw0_irqdispatch
1553 + move a0, sp # delay slot
1554 +
1555 + j ret_from_irq
1556 + nop # delay slot
1557 +
1558 + 1:
1559 + /*
1560 + * Here by mistake? This is possible, what can happen is that by the
1561 + * time we take the exception the IRQ pin goes low, so just leave if
1562 + * this is the case.
1563 + */
1564 + move a1,s0
1565 + PRINT("Got interrupt: c0_cause = %08x\n")
1566 + mfc0 a1, CP0_EPC
1567 + PRINT("c0_epc = %08x\n")
1568 +
1569 + j ret_from_irq
1570 + nop
1571 +END(mipsIRQ)
1572 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1573 --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1574 +++ linux.dev/arch/mips/ar7/printf.c 2005-07-07 04:39:14.421226000 +0200
1575 @@ -0,0 +1,51 @@
1576 +/*
1577 + * Carsten Langgaard, carstenl@mips.com
1578 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1579 + *
1580 + * This program is free software; you can distribute it and/or modify it
1581 + * under the terms of the GNU General Public License (Version 2) as
1582 + * published by the Free Software Foundation.
1583 + *
1584 + * This program is distributed in the hope it will be useful, but WITHOUT
1585 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1586 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1587 + * for more details.
1588 + *
1589 + * You should have received a copy of the GNU General Public License along
1590 + * with this program; if not, write to the Free Software Foundation, Inc.,
1591 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1592 + *
1593 + * Putting things on the screen/serial line using Adam2 facilities.
1594 + */
1595 +
1596 +#include <linux/config.h>
1597 +#include <linux/init.h>
1598 +#include <linux/kernel.h>
1599 +#include <linux/serial_reg.h>
1600 +#include <linux/spinlock.h>
1601 +#include <asm/io.h>
1602 +#include <asm/serial.h>
1603 +#include <asm/addrspace.h>
1604 +#include <asm/ar7/ar7.h>
1605 +
1606 +static char ppbuf[1024];
1607 +
1608 +void (*prom_print_str)(unsigned int out, char *s, int len);
1609 +
1610 +void prom_printf(char *fmt, ...) __init;
1611 +void prom_printf(char *fmt, ...)
1612 +{
1613 + va_list args;
1614 + int len;
1615 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1616 +
1617 + va_start(args, fmt);
1618 + vsprintf(ppbuf, fmt, args);
1619 + len = strlen(ppbuf);
1620 +
1621 + prom_print_str(1, ppbuf, len);
1622 +
1623 + va_end(args);
1624 + return;
1625 +
1626 +}
1627 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1628 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1629 +++ linux.dev/arch/mips/ar7/reset.c 2005-07-07 04:39:14.421226000 +0200
1630 @@ -0,0 +1,54 @@
1631 +/*
1632 + * Carsten Langgaard, carstenl@mips.com
1633 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1634 + *
1635 + * ########################################################################
1636 + *
1637 + * This program is free software; you can distribute it and/or modify it
1638 + * under the terms of the GNU General Public License (Version 2) as
1639 + * published by the Free Software Foundation.
1640 + *
1641 + * This program is distributed in the hope it will be useful, but WITHOUT
1642 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1643 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1644 + * for more details.
1645 + *
1646 + * You should have received a copy of the GNU General Public License along
1647 + * with this program; if not, write to the Free Software Foundation, Inc.,
1648 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1649 + *
1650 + * ########################################################################
1651 + *
1652 + * Reset the MIPS boards.
1653 + *
1654 + */
1655 +#include <linux/config.h>
1656 +
1657 +#include <asm/reboot.h>
1658 +#include <asm/mips-boards/generic.h>
1659 +
1660 +static void ar7_machine_restart(char *command);
1661 +static void ar7_machine_halt(void);
1662 +static void ar7_machine_power_off(void);
1663 +
1664 +static void ar7_machine_restart(char *command)
1665 +{
1666 +
1667 +}
1668 +
1669 +static void ar7_machine_halt(void)
1670 +{
1671 +
1672 +}
1673 +
1674 +static void ar7_machine_power_off(void)
1675 +{
1676 +
1677 +}
1678 +
1679 +void ar7_reboot_setup(void)
1680 +{
1681 + _machine_restart = ar7_machine_restart;
1682 + _machine_halt = ar7_machine_halt;
1683 + _machine_power_off = ar7_machine_power_off;
1684 +}
1685 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1686 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1687 +++ linux.dev/arch/mips/ar7/setup.c 2005-07-07 06:45:41.786771352 +0200
1688 @@ -0,0 +1,167 @@
1689 +/*
1690 + * Carsten Langgaard, carstenl@mips.com
1691 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1692 + *
1693 + * This program is free software; you can distribute it and/or modify it
1694 + * under the terms of the GNU General Public License (Version 2) as
1695 + * published by the Free Software Foundation.
1696 + *
1697 + * This program is distributed in the hope it will be useful, but WITHOUT
1698 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1699 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1700 + * for more details.
1701 + *
1702 + * You should have received a copy of the GNU General Public License along
1703 + * with this program; if not, write to the Free Software Foundation, Inc.,
1704 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1705 + */
1706 +#include <linux/config.h>
1707 +#include <linux/init.h>
1708 +#include <linux/sched.h>
1709 +#include <linux/mc146818rtc.h>
1710 +#include <linux/ioport.h>
1711 +
1712 +#include <asm/cpu.h>
1713 +#include <asm/bootinfo.h>
1714 +#include <asm/irq.h>
1715 +#include <asm/mips-boards/generic.h>
1716 +#include <asm/mips-boards/prom.h>
1717 +
1718 +#include <asm/dma.h>
1719 +#include <asm/time.h>
1720 +#include <asm/traps.h>
1721 +
1722 +
1723 +#define _LINK_KSEG0_
1724 +#define LITTLE_ENDIAN
1725 +#include <asm/ar7/tnetd73xx.h>
1726 +#include <asm/ar7/tnetd73xx_misc.h>
1727 +
1728 +// Specific for ar7wrd
1729 +unsigned int tnetd73xx_vbus_freq;
1730 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
1731 +#define AFECLK_FREQ 35328000
1732 +#define REFCLK_FREQ 25000000
1733 +#define OSC3_FREQ 24000000
1734 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
1735 +
1736 +#if defined(CONFIG_AR7_MARVELL)
1737 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
1738 +#else
1739 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
1740 +#endif
1741 +
1742 +
1743 +#ifdef CONFIG_KGDB
1744 +extern void rs_kgdb_hook(int);
1745 +int remote_debug = 0;
1746 +#endif
1747 +
1748 +extern struct rtc_ops no_rtc_ops;
1749 +
1750 +extern void ar7_reboot_setup(void);
1751 +
1752 +extern void ar7_time_init(void);
1753 +extern void ar7_timer_setup(struct irqaction *irq);
1754 +
1755 +/* maybe some of this is not needed? */
1756 +static void ar7_platform_init(void)
1757 +{
1758 + //tnetd73xx_gpio_init();
1759 +
1760 + tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
1761 + //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
1762 + //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
1763 +
1764 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
1765 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
1766 +
1767 + tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
1768 +
1769 + tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
1770 +
1771 +#if defined(CONFIG_AR7WRD)
1772 + if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
1773 + tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
1774 + }
1775 +#endif
1776 +
1777 +}
1778 +
1779 +const char *get_system_type(void)
1780 +{
1781 + return "Texas Instruments AR7";
1782 +}
1783 +
1784 +void __init ar7_setup(void)
1785 +{
1786 +#ifdef CONFIG_KGDB
1787 + int rs_putDebugChar(char);
1788 + char rs_getDebugChar(void);
1789 + extern int (*generic_putDebugChar)(char);
1790 + extern char (*generic_getDebugChar)(void);
1791 +#endif
1792 + char *argptr;
1793 +#ifdef CONFIG_SERIAL_CONSOLE
1794 + argptr = prom_getcmdline();
1795 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1796 + char console[20];
1797 + char *s;
1798 + int i = 0;
1799 +
1800 + s = prom_getenv("modetty0");
1801 + strcpy(console, "38400");
1802 +
1803 + if (s != NULL) {
1804 + while (s[i] >= '0' && s[i] <= '9')
1805 + i++;
1806 +
1807 + if (i > 0) {
1808 + strncpy(console, s, i);
1809 + console[i] = 0;
1810 + }
1811 + }
1812 +
1813 + argptr = prom_getcmdline();
1814 + strcat(argptr, " console=ttyS0,");
1815 + strcat(argptr, console);
1816 + }
1817 +#endif
1818 +
1819 +#ifdef CONFIG_KGDB
1820 + argptr = prom_getcmdline();
1821 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1822 + int line;
1823 + argptr += strlen("kgdb=ttyS");
1824 + if (*argptr != '0' && *argptr != '1')
1825 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1826 + "falling back to /dev/ttyS1\n", *argptr);
1827 + line = *argptr == '0' ? 0 : 1;
1828 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1829 + line ? 1 : 0);
1830 +
1831 + rs_kgdb_hook(line);
1832 + generic_putDebugChar = rs_putDebugChar;
1833 + generic_getDebugChar = rs_getDebugChar;
1834 +
1835 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1836 + "please connect your debugger\n", line ? 1 : 0);
1837 +
1838 + remote_debug = 1;
1839 + /* Breakpoints are in init_IRQ() */
1840 + }
1841 +#endif
1842 +
1843 + argptr = prom_getcmdline();
1844 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1845 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1846 +
1847 + rtc_ops = &no_rtc_ops;
1848 +
1849 + ar7_platform_init();
1850 +
1851 + ar7_reboot_setup();
1852 +
1853 + board_time_init = ar7_time_init;
1854 + board_timer_setup = ar7_timer_setup;
1855 +}
1856 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
1857 --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
1858 +++ linux.dev/arch/mips/ar7/time.c 2005-07-07 04:39:14.422226000 +0200
1859 @@ -0,0 +1,125 @@
1860 +/*
1861 + * Carsten Langgaard, carstenl@mips.com
1862 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1863 + *
1864 + * ########################################################################
1865 + *
1866 + * This program is free software; you can distribute it and/or modify it
1867 + * under the terms of the GNU General Public License (Version 2) as
1868 + * published by the Free Software Foundation.
1869 + *
1870 + * This program is distributed in the hope it will be useful, but WITHOUT
1871 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1872 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1873 + * for more details.
1874 + *
1875 + * You should have received a copy of the GNU General Public License along
1876 + * with this program; if not, write to the Free Software Foundation, Inc.,
1877 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1878 + *
1879 + * ########################################################################
1880 + *
1881 + * Setting up the clock on the MIPS boards.
1882 + *
1883 + */
1884 +
1885 +#include <linux/types.h>
1886 +#include <linux/config.h>
1887 +#include <linux/init.h>
1888 +#include <linux/kernel_stat.h>
1889 +#include <linux/sched.h>
1890 +#include <linux/spinlock.h>
1891 +
1892 +#include <asm/mipsregs.h>
1893 +#include <asm/ptrace.h>
1894 +#include <asm/hardirq.h>
1895 +#include <asm/div64.h>
1896 +
1897 +#include <linux/interrupt.h>
1898 +#include <linux/mc146818rtc.h>
1899 +#include <linux/timex.h>
1900 +
1901 +#include <asm/mips-boards/generic.h>
1902 +#include <asm/mips-boards/prom.h>
1903 +#include <asm/ar7/ar7.h>
1904 +
1905 +extern asmlinkage void mipsIRQ(void);
1906 +
1907 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
1908 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1909 +
1910 +#define MIPS_CPU_TIMER_IRQ 7
1911 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1912 +
1913 +static inline void ack_r4ktimer(unsigned long newval)
1914 +{
1915 + write_c0_compare(newval);
1916 +}
1917 +
1918 +void ar7_timer_interrupt(struct pt_regs *regs)
1919 +{
1920 + int cpu = smp_processor_id();
1921 +
1922 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
1923 +
1924 + if (r4k_offset == 0)
1925 + goto null;
1926 +
1927 + do {
1928 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
1929 + do_timer(regs);
1930 + r4k_cur += r4k_offset;
1931 + ack_r4ktimer(r4k_cur);
1932 +
1933 + } while (((unsigned long)read_c0_count()
1934 + - r4k_cur) < 0x7fffffff);
1935 +
1936 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
1937 +
1938 + if (softirq_pending(cpu))
1939 + do_softirq();
1940 +
1941 + return;
1942 +
1943 +null:
1944 + ack_r4ktimer(0);
1945 +}
1946 +
1947 +/*
1948 + * Figure out the r4k offset, the amount to increment the compare
1949 + * register for each time tick.
1950 + */
1951 +static unsigned long __init cal_r4koff(void)
1952 +{
1953 + return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
1954 +}
1955 +
1956 +void __init ar7_time_init(void)
1957 +{
1958 + unsigned long flags;
1959 + unsigned int est_freq;
1960 +
1961 + set_except_vector(0, mipsIRQ);
1962 + write_c0_count(0);
1963 +
1964 + printk("calculating r4koff... ");
1965 + r4k_offset = cal_r4koff();
1966 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1967 +
1968 + est_freq = 2*r4k_offset*HZ;
1969 + est_freq += 5000; /* round */
1970 + est_freq -= est_freq%10000;
1971 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1972 + (est_freq%1000000)*100/1000000);
1973 +}
1974 +
1975 +void __init ar7_timer_setup(struct irqaction *irq)
1976 +{
1977 + /* we are using the cpu counter for timer interrupts */
1978 + irq->handler = no_action; /* we use our own handler */
1979 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1980 +
1981 + r4k_cur = (read_c0_count() + r4k_offset);
1982 + write_c0_compare(r4k_cur);
1983 + set_c0_status(ALLINTS);
1984 +}
1985 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
1986 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
1987 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-07 04:39:14.423225000 +0200
1988 @@ -0,0 +1,924 @@
1989 +/******************************************************************************
1990 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1991 + ******************************************************************************
1992 + * FILE NAME: tnetd73xx_misc.c
1993 + *
1994 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1995 + * FSER Modules API
1996 + * As per TNETD73xx specifications
1997 + *
1998 + * REVISION HISTORY:
1999 + * 27 Nov 02 - Sharath Kumar PSP TII
2000 + * 14 Feb 03 - Anant Gole PSP TII
2001 + *
2002 + * (C) Copyright 2002, Texas Instruments, Inc
2003 + *******************************************************************************/
2004 +
2005 +#define LITTLE_ENDIAN
2006 +#define _LINK_KSEG0_
2007 +
2008 +#include <linux/types.h>
2009 +#include <asm/ar7/tnetd73xx.h>
2010 +#include <asm/ar7/tnetd73xx_misc.h>
2011 +
2012 +/* TNETD73XX Revision */
2013 +u32 tnetd73xx_get_revision(void)
2014 +{
2015 + /* Read Chip revision register - This register is from GPIO module */
2016 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2017 +}
2018 +
2019 +/*****************************************************************************
2020 + * Reset Control Module
2021 + *****************************************************************************/
2022 +
2023 +
2024 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2025 +{
2026 + u32 reset_status;
2027 +
2028 + /* read current reset register */
2029 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2030 +
2031 + if (reset_ctrl == OUT_OF_RESET)
2032 + {
2033 + /* bring module out of reset */
2034 + reset_status |= (1 << reset_module);
2035 + }
2036 + else
2037 + {
2038 + /* put module in reset */
2039 + reset_status &= (~(1 << reset_module));
2040 + }
2041 +
2042 + /* write to the reset register */
2043 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2044 +}
2045 +
2046 +
2047 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2048 +{
2049 + u32 reset_status;
2050 +
2051 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2052 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2053 +}
2054 +
2055 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2056 +{
2057 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2058 +}
2059 +
2060 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2061 +
2062 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2063 +{
2064 + u32 sys_reset_status;
2065 +
2066 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2067 +
2068 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2069 +}
2070 +
2071 +
2072 +/*****************************************************************************
2073 + * Power Control Module
2074 + *****************************************************************************/
2075 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2076 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2077 +
2078 +
2079 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2080 +{
2081 + u32 power_status;
2082 +
2083 + /* read current power down control register */
2084 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2085 +
2086 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2087 + {
2088 + /* power down the module */
2089 + power_status |= (1 << power_module);
2090 + }
2091 + else
2092 + {
2093 + /* power on the module */
2094 + power_status &= (~(1 << power_module));
2095 + }
2096 +
2097 + /* write to the reset register */
2098 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2099 +}
2100 +
2101 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2102 +{
2103 + u32 power_status;
2104 +
2105 + /* read current power down control register */
2106 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2107 +
2108 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2109 +}
2110 +
2111 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2112 +{
2113 + u32 power_status;
2114 +
2115 + /* read current power down control register */
2116 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2117 +
2118 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2119 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2120 +
2121 + /* write to power down control register */
2122 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2123 +}
2124 +
2125 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2126 +{
2127 + u32 power_status;
2128 +
2129 + /* read current power down control register */
2130 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2131 +
2132 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2133 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2134 +
2135 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2136 +}
2137 +
2138 +
2139 +/*****************************************************************************
2140 + * Wakeup Control
2141 + *****************************************************************************/
2142 +
2143 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2144 +
2145 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2146 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2147 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2148 +{
2149 + u32 wakeup_status;
2150 +
2151 + /* read the wakeup control register */
2152 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2153 +
2154 + /* enable/disable */
2155 + if (wakeup_ctrl == WAKEUP_ENABLED)
2156 + {
2157 + /* enable wakeup */
2158 + wakeup_status |= wakeup_int;
2159 + }
2160 + else
2161 + {
2162 + /* disable wakeup */
2163 + wakeup_status &= (~wakeup_int);
2164 + }
2165 +
2166 + /* set polarity */
2167 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2168 + {
2169 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2170 + }
2171 + else
2172 + {
2173 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2174 + }
2175 +
2176 + /* write the wakeup control register */
2177 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2178 +}
2179 +
2180 +
2181 +/*****************************************************************************
2182 + * FSER Control
2183 + *****************************************************************************/
2184 +
2185 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2186 +{
2187 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2188 +}
2189 +
2190 +/*****************************************************************************
2191 + * Clock Control
2192 + *****************************************************************************/
2193 +
2194 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2195 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2196 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2197 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2198 +
2199 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2200 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2201 +
2202 +#define CLKC_PRE_DIVIDER 0x0000001F
2203 +#define CLKC_POST_DIVIDER 0x001F0000
2204 +
2205 +#define CLKC_PLL_STATUS 0x1
2206 +#define CLKC_PLL_FACTOR 0x0000F000
2207 +
2208 +#define BOOTCR_PLL_BYPASS (1 << 5)
2209 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2210 +
2211 +#define MIPS_PLL_SELECT 0x00030000
2212 +#define SYSTEM_PLL_SELECT 0x0000C000
2213 +#define USB_PLL_SELECT 0x000C0000
2214 +#define ADSLSS_PLL_SELECT 0x00C00000
2215 +
2216 +#define MIPS_AFECLKI_SELECT 0x00000000
2217 +#define MIPS_REFCLKI_SELECT 0x00010000
2218 +#define MIPS_XTAL3IN_SELECT 0x00020000
2219 +
2220 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2221 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2222 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2223 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2224 +
2225 +#define USB_SYSPLL_SELECT 0x00000000
2226 +#define USB_REFCLKI_SELECT 0x00040000
2227 +#define USB_XTAL3IN_SELECT 0x00080000
2228 +#define USB_MIPSPLL_SELECT 0x000C0000
2229 +
2230 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2231 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2232 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2233 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2234 +
2235 +#define SYS_MAX CLK_MHZ(150)
2236 +#define SYS_MIN CLK_MHZ(1)
2237 +
2238 +#define MIPS_SYNC_MAX SYS_MAX
2239 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2240 +#define MIPS_MIN CLK_MHZ(1)
2241 +
2242 +#define USB_MAX CLK_MHZ(100)
2243 +#define USB_MIN CLK_MHZ(1)
2244 +
2245 +#define ADSL_MAX CLK_MHZ(180)
2246 +#define ADSL_MIN CLK_MHZ(1)
2247 +
2248 +#define PLL_MUL_MAXFACTOR 15
2249 +#define MAX_DIV_VALUE 32
2250 +#define MIN_DIV_VALUE 1
2251 +
2252 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2253 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2254 +
2255 +#define DIVIDER_LOCK_TIME 10100
2256 +#define PLL_LOCK_TIME 10100 * 75
2257 +
2258 +
2259 +
2260 + /****************************************************************************
2261 + * DATA PURPOSE: PRIVATE Variables
2262 + **************************************************************************/
2263 + static u32 *clk_src[4];
2264 + static u32 mips_pll_out;
2265 + static u32 sys_pll_out;
2266 + static u32 afeclk_inp;
2267 + static u32 refclk_inp;
2268 + static u32 xtal_inp;
2269 + static u32 present_min;
2270 + static u32 present_max;
2271 +
2272 + /* Forward References */
2273 + static u32 find_gcd(u32 min, u32 max);
2274 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2275 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2276 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2277 + static void find_approx(u32 *,u32 *,u32);
2278 +
2279 + /****************************************************************************
2280 + * FUNCTION: tnetd73xx_clkc_init
2281 + ****************************************************************************
2282 + * Description: The routine initializes the internal variables depending on
2283 + * on the sources selected for different clocks.
2284 + ***************************************************************************/
2285 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2286 +{
2287 +
2288 + u32 choice;
2289 +
2290 + afeclk_inp = afeclk;
2291 + refclk_inp = refclk;
2292 + xtal_inp = xtal3in;
2293 +
2294 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2295 + switch(choice)
2296 + {
2297 + case MIPS_AFECLKI_SELECT:
2298 + clk_src[CLKC_MIPS] = &afeclk_inp;
2299 + break;
2300 +
2301 + case MIPS_REFCLKI_SELECT:
2302 + clk_src[CLKC_MIPS] = &refclk_inp;
2303 + break;
2304 +
2305 + case MIPS_XTAL3IN_SELECT:
2306 + clk_src[CLKC_MIPS] = &xtal_inp;
2307 + break;
2308 +
2309 + default :
2310 + clk_src[CLKC_MIPS] = 0;
2311 +
2312 + }
2313 +
2314 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2315 + switch(choice)
2316 + {
2317 + case SYSTEM_AFECLKI_SELECT:
2318 + clk_src[CLKC_SYS] = &afeclk_inp;
2319 + break;
2320 +
2321 + case SYSTEM_REFCLKI_SELECT:
2322 + clk_src[CLKC_SYS] = &refclk_inp;
2323 + break;
2324 +
2325 + case SYSTEM_XTAL3IN_SELECT:
2326 + clk_src[CLKC_SYS] = &xtal_inp;
2327 + break;
2328 +
2329 + case SYSTEM_MIPSPLL_SELECT:
2330 + clk_src[CLKC_SYS] = &mips_pll_out;
2331 + break;
2332 +
2333 + default :
2334 + clk_src[CLKC_SYS] = 0;
2335 +
2336 + }
2337 +
2338 +
2339 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2340 + switch(choice)
2341 + {
2342 + case ADSLSS_AFECLKI_SELECT:
2343 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2344 + break;
2345 +
2346 + case ADSLSS_REFCLKI_SELECT:
2347 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2348 + break;
2349 +
2350 + case ADSLSS_XTAL3IN_SELECT:
2351 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2352 + break;
2353 +
2354 + case ADSLSS_MIPSPLL_SELECT:
2355 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2356 + break;
2357 +
2358 + default :
2359 + clk_src[CLKC_ADSLSS] = 0;
2360 +
2361 + }
2362 +
2363 +
2364 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2365 + switch(choice)
2366 + {
2367 + case USB_SYSPLL_SELECT:
2368 + clk_src[CLKC_USB] = &sys_pll_out ;
2369 + break;
2370 +
2371 + case USB_REFCLKI_SELECT:
2372 + clk_src[CLKC_USB] = &refclk_inp;
2373 + break;
2374 +
2375 + case USB_XTAL3IN_SELECT:
2376 + clk_src[CLKC_USB] = &xtal_inp;
2377 + break;
2378 +
2379 + case USB_MIPSPLL_SELECT:
2380 + clk_src[CLKC_USB] = &mips_pll_out;
2381 + break;
2382 +
2383 + default :
2384 + clk_src[CLKC_USB] = 0;
2385 +
2386 + }
2387 +}
2388 +
2389 +
2390 +
2391 +/****************************************************************************
2392 + * FUNCTION: tnetd73xx_clkc_set_freq
2393 + ****************************************************************************
2394 + * Description: The above routine is called to set the output_frequency of the
2395 + * selected clock(using clk_id) to the required value given
2396 + * by the variable output_freq.
2397 + ***************************************************************************/
2398 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2399 +(
2400 + TNETD73XX_CLKC_ID_T clk_id,
2401 + u32 output_freq
2402 + )
2403 +{
2404 + u32 base_freq;
2405 + u32 multiplier;
2406 + u32 divider;
2407 + u32 min_prediv;
2408 + u32 max_prediv;
2409 + u32 prediv;
2410 + u32 postdiv;
2411 + u32 temp;
2412 +
2413 + /* check if PLLs are bypassed*/
2414 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2415 + {
2416 + return TNETD73XX_ERR_ERROR;
2417 + }
2418 +
2419 + /*check if the requested output_frequency is in valid range*/
2420 + switch( clk_id )
2421 + {
2422 + case CLKC_SYS:
2423 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2424 + {
2425 + return TNETD73XX_ERR_ERROR;
2426 + }
2427 + present_min = SYS_MIN;
2428 + present_max = SYS_MAX;
2429 + break;
2430 +
2431 + case CLKC_MIPS:
2432 + if((output_freq < MIPS_MIN) ||
2433 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2434 + {
2435 + return TNETD73XX_ERR_ERROR;
2436 + }
2437 + present_min = MIPS_MIN;
2438 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2439 + break;
2440 +
2441 + case CLKC_USB:
2442 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2443 + {
2444 + return TNETD73XX_ERR_ERROR;
2445 + }
2446 + present_min = USB_MIN;
2447 + present_max = USB_MAX;
2448 + break;
2449 +
2450 + case CLKC_ADSLSS:
2451 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2452 + {
2453 + return TNETD73XX_ERR_ERROR;
2454 + }
2455 + present_min = ADSL_MIN;
2456 + present_max = ADSL_MAX;
2457 + break;
2458 + }
2459 +
2460 +
2461 + base_freq = get_base_frequency(clk_id);
2462 +
2463 +
2464 + /* check for minimum base frequency value */
2465 + if( base_freq < MIN_PLL_INP_FREQ)
2466 + {
2467 + return TNETD73XX_ERR_ERROR;
2468 + }
2469 +
2470 + get_val(output_freq, base_freq, &multiplier, &divider);
2471 +
2472 + /* check multiplier range */
2473 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2474 + {
2475 + return TNETD73XX_ERR_ERROR;
2476 + }
2477 +
2478 + /* check divider value */
2479 + if( divider == 0 )
2480 + {
2481 + return TNETD73XX_ERR_ERROR;
2482 + }
2483 +
2484 + /*compute minimum and maximum predivider values */
2485 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2486 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2487 +
2488 + /*adjust the value of divider so that it not less than minimum predivider value*/
2489 + if (divider < min_prediv)
2490 + {
2491 + temp = CEIL(min_prediv, divider);
2492 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2493 + {
2494 + return TNETD73XX_ERR_ERROR ;
2495 + }
2496 + else
2497 + {
2498 + multiplier = temp * multiplier;
2499 + divider = min_prediv;
2500 + }
2501 +
2502 + }
2503 +
2504 + /* compute predivider and postdivider values */
2505 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2506 + postdiv = CEIL(divider,prediv);
2507 +
2508 + /*return fail if postdivider value falls out of range */
2509 + if(postdiv > MAX_DIV_VALUE)
2510 + {
2511 + return TNETD73XX_ERR_ERROR;
2512 + }
2513 +
2514 +
2515 + /*write predivider and postdivider values*/
2516 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2517 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2518 +
2519 + /*wait for divider output to stabilise*/
2520 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2521 +
2522 + /*write to PLL clock register*/
2523 +
2524 + if(clk_id == CLKC_SYS)
2525 + {
2526 + /* but before writing put DRAM to hold mode */
2527 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2528 + }
2529 + /*Bring PLL into div mode */
2530 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2531 +
2532 + /*compute the word to be written to PLLCR
2533 + *corresponding to multiplier value
2534 + */
2535 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2536 +
2537 + /* wait till PLL enters div mode */
2538 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2539 + /*nothing*/;
2540 +
2541 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2542 +
2543 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2544 + /*nothing*/;
2545 +
2546 +
2547 + /*wait for External pll to lock*/
2548 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2549 +
2550 + if(clk_id == CLKC_SYS)
2551 + {
2552 + /* Bring DRAM out of hold */
2553 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2554 + }
2555 +
2556 + return TNETD73XX_ERR_OK ;
2557 +}
2558 +
2559 +/****************************************************************************
2560 + * FUNCTION: tnetd73xx_clkc_get_freq
2561 + ****************************************************************************
2562 + * Description: The above routine is called to get the output_frequency of the
2563 + * selected clock( clk_id)
2564 + ***************************************************************************/
2565 +u32 tnetd73xx_clkc_get_freq
2566 +(
2567 + TNETD73XX_CLKC_ID_T clk_id
2568 + )
2569 +{
2570 +
2571 + u32 clk_ctrl_register;
2572 + u32 clk_pll_setting;
2573 + u32 clk_predivider;
2574 + u32 clk_postdivider;
2575 + u16 pll_factor;
2576 + u32 base_freq;
2577 + u32 divider;
2578 +
2579 + base_freq = get_base_frequency(clk_id);
2580 +
2581 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2582 +
2583 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2584 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2585 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2586 +
2587 + divider = clk_predivider * clk_postdivider;
2588 +
2589 +
2590 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2591 + {
2592 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2593 + }
2594 +
2595 +
2596 + else
2597 + {
2598 + /* return the current clock speed based upon the PLL setting */
2599 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2600 +
2601 + /* Get the PLL multiplication factor */
2602 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2603 +
2604 + /* Check if we're in divide mode or multiply mode */
2605 + if((clk_pll_setting & 0x1) == 0)
2606 + {
2607 + /* We're in divide mode */
2608 + if(pll_factor < 0x10)
2609 + return (CEIL(base_freq >> 1, divider));
2610 + else
2611 + return (CEIL(base_freq >> 2, divider));
2612 + }
2613 +
2614 + else /* We're in PLL mode */
2615 + {
2616 + /* See if PLLNDIV & PLLDIV are set */
2617 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2618 + {
2619 + if(clk_pll_setting & 0x1000)
2620 + {
2621 + /* clk = base_freq * k/2 */
2622 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2623 + }
2624 + else
2625 + {
2626 + /* clk = base_freq * (k-1) / 4)*/
2627 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2628 + }
2629 + }
2630 + else
2631 + {
2632 + if(pll_factor < 0x10)
2633 + {
2634 + /* clk = base_freq * k */
2635 + return(CEIL(base_freq * pll_factor, divider));
2636 + }
2637 +
2638 + else
2639 + {
2640 + /* clk = base_freq */
2641 + return(CEIL(base_freq, divider));
2642 + }
2643 + }
2644 + }
2645 + return(0); /* Should never reach here */
2646 +
2647 + }
2648 +
2649 +}
2650 +
2651 +
2652 +/* local helper functions */
2653 +
2654 +/****************************************************************************
2655 + * FUNCTION: get_base_frequency
2656 + ****************************************************************************
2657 + * Description: The above routine is called to get base frequency of the clocks.
2658 + ***************************************************************************/
2659 +
2660 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2661 +{
2662 + /* update the current MIPs PLL output value, if the required
2663 + * source is MIPS PLL
2664 + */
2665 + if ( clk_src[clk_id] == &mips_pll_out)
2666 + {
2667 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2668 + }
2669 +
2670 +
2671 + /* update the current System PLL output value, if the required
2672 + * source is system PLL
2673 + */
2674 + if ( clk_src[clk_id] == &sys_pll_out)
2675 + {
2676 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2677 + }
2678 +
2679 + return (*clk_src[clk_id]);
2680 +
2681 +}
2682 +
2683 +
2684 +
2685 +/****************************************************************************
2686 + * FUNCTION: find_gcd
2687 + ****************************************************************************
2688 + * Description: The above routine is called to find gcd of 2 numbers.
2689 + ***************************************************************************/
2690 +static u32 find_gcd
2691 +(
2692 + u32 min,
2693 + u32 max
2694 + )
2695 +{
2696 + if (max % min == 0)
2697 + {
2698 + return min;
2699 + }
2700 + else
2701 + {
2702 + return find_gcd(max % min, min);
2703 + }
2704 +}
2705 +
2706 +/****************************************************************************
2707 + * FUNCTION: compute_prediv
2708 + ****************************************************************************
2709 + * Description: The above routine is called to compute predivider value
2710 + ***************************************************************************/
2711 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2712 +{
2713 + u16 prediv;
2714 +
2715 + /* return the divider itself it it falls within the range of predivider*/
2716 + if (min <= divider && divider <= max)
2717 + {
2718 + return divider;
2719 + }
2720 +
2721 + /* find a value for prediv such that it is a factor of divider */
2722 + for (prediv = max; prediv >= min ; prediv--)
2723 + {
2724 + if ( (divider % prediv) == 0 )
2725 + {
2726 + return prediv;
2727 + }
2728 + }
2729 +
2730 + /* No such factor exists, return min as prediv */
2731 + return min;
2732 +}
2733 +
2734 +/****************************************************************************
2735 + * FUNCTION: get_val
2736 + ****************************************************************************
2737 + * Description: This routine is called to get values of divider and multiplier.
2738 + ***************************************************************************/
2739 +
2740 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2741 +{
2742 + u32 temp_mul;
2743 + u32 temp_div;
2744 + u32 gcd;
2745 + u32 min_freq;
2746 + u32 max_freq;
2747 +
2748 + /* find gcd of base_freq, output_freq */
2749 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2750 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2751 + gcd = find_gcd(min_freq , max_freq);
2752 +
2753 + if(gcd == 0)
2754 + return; /* ERROR */
2755 +
2756 + /* compute values of multiplier and divider */
2757 + temp_mul = output_freq / gcd;
2758 + temp_div = base_freq / gcd;
2759 +
2760 +
2761 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2762 + if( temp_mul > PLL_MUL_MAXFACTOR )
2763 + {
2764 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2765 + return;
2766 +
2767 + find_approx(&temp_mul,&temp_div,base_freq);
2768 + }
2769 +
2770 + *multiplier = temp_mul;
2771 + *divider = temp_div;
2772 +}
2773 +
2774 +/****************************************************************************
2775 + * FUNCTION: find_approx
2776 + ****************************************************************************
2777 + * Description: This function gets the approx value of num/denom.
2778 + ***************************************************************************/
2779 +
2780 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2781 +{
2782 + u32 num1;
2783 + u32 denom1;
2784 + u32 num2;
2785 + u32 denom2;
2786 + int32_t closest;
2787 + int32_t prev_closest;
2788 + u32 temp_num;
2789 + u32 temp_denom;
2790 + u32 normalize;
2791 + u32 gcd;
2792 + u32 output_freq;
2793 +
2794 + num1 = *num;
2795 + denom1 = *denom;
2796 +
2797 + prev_closest = 0x7fffffff; /* maximum possible value */
2798 + num2 = num1;
2799 + denom2 = denom1;
2800 +
2801 + /* start with max */
2802 + for(temp_num = 15; temp_num >=1; temp_num--)
2803 + {
2804 +
2805 + temp_denom = CEIL(temp_num * denom1, num1);
2806 + output_freq = (temp_num * base_freq) / temp_denom;
2807 +
2808 + if(temp_denom < 1)
2809 + {
2810 + break;
2811 + }
2812 + else
2813 + {
2814 + normalize = CEIL(num1,temp_num);
2815 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2816 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2817 + {
2818 + prev_closest = closest;
2819 + num2 = temp_num;
2820 + denom2 = temp_denom;
2821 + }
2822 +
2823 + }
2824 +
2825 + }
2826 +
2827 + gcd = find_gcd(num2,denom2);
2828 + num2 = num2 / gcd;
2829 + denom2 = denom2 /gcd;
2830 +
2831 + *num = num2;
2832 + *denom = denom2;
2833 +}
2834 +
2835 +
2836 +/*****************************************************************************
2837 + * GPIO Control
2838 + *****************************************************************************/
2839 +
2840 +/****************************************************************************
2841 + * FUNCTION: tnetd73xx_gpio_init
2842 + ***************************************************************************/
2843 +void tnetd73xx_gpio_init()
2844 +{
2845 + /* Bring module out of reset */
2846 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2847 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2848 +}
2849 +
2850 +/****************************************************************************
2851 + * FUNCTION: tnetd73xx_gpio_ctrl
2852 + ***************************************************************************/
2853 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2854 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2855 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2856 +{
2857 + u32 pin_status;
2858 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2859 + if (pin_mode == GPIO_PIN)
2860 + {
2861 + pin_status |= (1 << gpio_pin);
2862 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2863 +
2864 + /* Set pin direction */
2865 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2866 + if (pin_direction == GPIO_INPUT_PIN)
2867 + {
2868 + pin_status |= (1 << gpio_pin);
2869 + }
2870 + else /* GPIO_OUTPUT_PIN */
2871 + {
2872 + pin_status &= (~(1 << gpio_pin));
2873 + }
2874 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2875 + }
2876 + else /* FUNCTIONAL PIN */
2877 + {
2878 + pin_status &= (~(1 << gpio_pin));
2879 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2880 + }
2881 +
2882 +}
2883 +
2884 +/****************************************************************************
2885 + * FUNCTION: tnetd73xx_gpio_out
2886 + ***************************************************************************/
2887 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2888 +{
2889 + u32 pin_value;
2890 +
2891 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2892 + if (value == 1)
2893 + {
2894 + pin_value |= (1 << gpio_pin);
2895 + }
2896 + else
2897 + {
2898 + pin_value &= (~(1 << gpio_pin));
2899 + }
2900 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2901 +}
2902 +
2903 +/****************************************************************************
2904 + * FUNCTION: tnetd73xx_gpio_in
2905 + ***************************************************************************/
2906 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2907 +{
2908 + u32 pin_value;
2909 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2910 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2911 +}
2912 +
2913 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2914 --- linux.old/arch/mips/config-shared.in 2005-07-07 05:38:31.343491864 +0200
2915 +++ linux.dev/arch/mips/config-shared.in 2005-07-07 04:39:14.424225000 +0200
2916 @@ -20,6 +20,15 @@
2917 mainmenu_option next_comment
2918 comment 'Machine selection'
2919 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2920 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2921 +if [ "$CONFIG_AR7" = "y" ]; then
2922 + choice 'Texas Instruments Reference Platform' \
2923 + "AR7DB CONFIG_AR7DB \
2924 + AR7RD CONFIG_AR7RD \
2925 + AR7WRD CONFIG_AR7WRD" AR7DB
2926 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
2927 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2928 +fi
2929 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2930 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2931 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2932 @@ -239,6 +248,11 @@
2933 define_bool CONFIG_NONCOHERENT_IO y
2934 define_bool CONFIG_PC_KEYB y
2935 fi
2936 +if [ "$CONFIG_AR7" = "y" ]; then
2937 + define_bool CONFIG_NONCOHERENT_IO y
2938 + define_bool CONFIG_SWAP_IO_SPACE y
2939 + define_bool CONFIG_AR7_PAGING y
2940 +fi
2941 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2942 define_bool CONFIG_IRQ_CPU y
2943 define_bool CONFIG_NONCOHERENT_IO y
2944 @@ -736,6 +750,7 @@
2945 mainmenu_option next_comment
2946 comment 'General setup'
2947 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2948 + "$CONFIG_AR7" = "y" -o \
2949 "$CONFIG_CASIO_E55" = "y" -o \
2950 "$CONFIG_DDB5074" = "y" -o \
2951 "$CONFIG_DDB5476" = "y" -o \
2952 @@ -797,6 +812,7 @@
2953 bool 'Networking support' CONFIG_NET
2954
2955 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2956 + "$CONFIG_AR7" = "y" -o \
2957 "$CONFIG_CASIO_E55" = "y" -o \
2958 "$CONFIG_DECSTATION" = "y" -o \
2959 "$CONFIG_IBM_WORKPAD" = "y" -o \
2960 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
2961 --- linux.old/arch/mips/kernel/irq.c 2005-07-07 05:38:31.343491864 +0200
2962 +++ linux.dev/arch/mips/kernel/irq.c 2005-07-07 04:39:14.424225000 +0200
2963 @@ -76,6 +76,7 @@
2964 * Generic, controller-independent functions:
2965 */
2966
2967 +#ifndef CONFIG_AR7
2968 int get_irq_list(char *buf)
2969 {
2970 int i, j;
2971 @@ -110,6 +111,7 @@
2972 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2973 return p - buf;
2974 }
2975 +#endif
2976
2977 #ifdef CONFIG_SMP
2978 int global_irq_holder = NO_PROC_ID;
2979 @@ -525,6 +527,7 @@
2980 *
2981 */
2982
2983 +#ifndef CONFIG_AR7
2984 int request_irq(unsigned int irq,
2985 void (*handler)(int, void *, struct pt_regs *),
2986 unsigned long irqflags,
2987 @@ -569,6 +572,7 @@
2988 kfree(action);
2989 return retval;
2990 }
2991 +#endif
2992
2993 /**
2994 * free_irq - free an interrupt
2995 @@ -588,6 +592,7 @@
2996 * the machine.
2997 */
2998
2999 +#ifndef CONFIG_AR7
3000 void free_irq(unsigned int irq, void *dev_id)
3001 {
3002 irq_desc_t *desc;
3003 @@ -629,6 +634,7 @@
3004 return;
3005 }
3006 }
3007 +#endif
3008
3009 /*
3010 * IRQ autodetection code..
3011 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3012 --- linux.old/arch/mips/kernel/setup.c 2005-07-07 05:38:31.344491712 +0200
3013 +++ linux.dev/arch/mips/kernel/setup.c 2005-07-07 04:39:14.425225000 +0200
3014 @@ -109,6 +109,7 @@
3015 unsigned long isa_slot_offset;
3016 EXPORT_SYMBOL(isa_slot_offset);
3017
3018 +extern void avalanche_bootmem_init(void);
3019 extern void SetUpBootInfo(void);
3020 extern void load_mmu(void);
3021 extern asmlinkage void start_kernel(void);
3022 @@ -267,6 +268,9 @@
3023 #endif /* CONFIG_BLK_DEV_INITRD */
3024
3025 /* Find the highest page frame number we have available. */
3026 +#ifdef CONFIG_AR7_PAGING
3027 + avalanche_bootmem_init();
3028 +#else
3029 max_pfn = 0;
3030 first_usable_pfn = -1UL;
3031 for (i = 0; i < boot_mem_map.nr_map; i++) {
3032 @@ -376,7 +380,7 @@
3033
3034 /* Reserve the bootmap memory. */
3035 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3036 -
3037 +#endif
3038 #ifdef CONFIG_BLK_DEV_INITRD
3039 /* Board specific code should have set up initrd_start and initrd_end */
3040 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3041 @@ -494,6 +498,7 @@
3042 void hp_setup(void);
3043 void au1x00_setup(void);
3044 void frame_info_init(void);
3045 + void ar7_setup(void);
3046
3047 frame_info_init();
3048 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3049 @@ -691,6 +696,11 @@
3050 pmc_yosemite_setup();
3051 break;
3052 #endif
3053 +#ifdef CONFIG_AR7
3054 + case MACH_GROUP_UNKNOWN:
3055 + ar7_setup();
3056 + break;
3057 +#endif
3058 default:
3059 panic("Unsupported architecture");
3060 }
3061 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3062 --- linux.old/arch/mips/kernel/traps.c 2005-07-07 05:38:31.345491560 +0200
3063 +++ linux.dev/arch/mips/kernel/traps.c 2005-07-07 04:39:14.425225000 +0200
3064 @@ -40,6 +40,10 @@
3065 #include <asm/uaccess.h>
3066 #include <asm/mmu_context.h>
3067
3068 +#ifdef CONFIG_AR7
3069 +#include <asm/ar7/ar7.h>
3070 +#endif
3071 +
3072 extern asmlinkage void handle_mod(void);
3073 extern asmlinkage void handle_tlbl(void);
3074 extern asmlinkage void handle_tlbs(void);
3075 @@ -869,9 +873,15 @@
3076
3077 exception_handlers[n] = handler;
3078 if (n == 0 && cpu_has_divec) {
3079 +#ifdef CONFIG_AR7
3080 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
3081 + (0x03ffffff & (handler >> 2));
3082 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
3083 +#else
3084 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3085 (0x03ffffff & (handler >> 2));
3086 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3087 +#endif
3088 }
3089 return (void *)old_handler;
3090 }
3091 @@ -920,14 +930,46 @@
3092 void __init trap_init(void)
3093 {
3094 extern char except_vec1_generic;
3095 + extern char except_vec2_generic;
3096 extern char except_vec3_generic, except_vec3_r4000;
3097 extern char except_vec_ejtag_debug;
3098 extern char except_vec4;
3099 unsigned long i;
3100
3101 +#ifdef CONFIG_AR7
3102 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3103 + extern char jump_cache_error,jump_general_exception;
3104 + extern char jump_dedicated_interrupt;
3105 + clear_c0_status(ST0_BEV);
3106 +#endif
3107 +
3108 /* Copy the generic exception handler code to it's final destination. */
3109 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3110 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3111 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3112
3113 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3114 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3115 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3116 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3117 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3118 +
3119 +#ifdef CONFIG_AR7
3120 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
3121 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
3122 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3123 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3124 +
3125 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3126 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3127 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3128 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3129 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3130 +#else
3131 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3132 +#endif
3133 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3134 +
3135 /*
3136 * Setup default vectors
3137 */
3138 @@ -951,8 +993,12 @@
3139 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3140 * interrupt processing overhead. Use it where available.
3141 */
3142 +#ifdef CONFIG_AR7
3143 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
3144 +#else
3145 if (cpu_has_divec)
3146 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3147 +#endif
3148
3149 /*
3150 * Some CPUs can enable/disable for cache parity detection, but does
3151 @@ -991,12 +1037,17 @@
3152 if (cpu_has_mcheck)
3153 set_except_vector(24, handle_mcheck);
3154
3155 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3156 +#ifdef CONFIG_AR7
3157 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3158 +#else
3159 if (cpu_has_vce)
3160 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3161 else if (cpu_has_4kex)
3162 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3163 else
3164 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3165 +#endif
3166
3167 if (current_cpu_data.cputype == CPU_R6000 ||
3168 current_cpu_data.cputype == CPU_R6000A) {
3169 @@ -1023,7 +1074,11 @@
3170 if (board_nmi_handler_setup)
3171 board_nmi_handler_setup();
3172
3173 +#ifdef CONFIG_AR7
3174 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3175 +#else
3176 flush_icache_range(KSEG0, KSEG0 + 0x400);
3177 +#endif
3178
3179 per_cpu_trap_init();
3180 }
3181 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3182 --- linux.old/arch/mips/lib/promlib.c 2005-07-07 05:38:31.345491560 +0200
3183 +++ linux.dev/arch/mips/lib/promlib.c 2005-07-07 04:39:14.426225000 +0200
3184 @@ -1,3 +1,4 @@
3185 +#ifndef CONFIG_AR7
3186 #include <stdarg.h>
3187 #include <linux/kernel.h>
3188
3189 @@ -22,3 +23,4 @@
3190 }
3191 va_end(args);
3192 }
3193 +#endif
3194 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
3195 --- linux.old/arch/mips/Makefile 2005-07-07 05:38:31.320495360 +0200
3196 +++ linux.dev/arch/mips/Makefile 2005-07-07 04:39:14.510212000 +0200
3197 @@ -369,6 +369,16 @@
3198 endif
3199
3200 #
3201 +# Texas Instruments AR7
3202 +#
3203 +
3204 +ifdef CONFIG_AR7
3205 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
3206 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
3207 +LOADADDR += 0x94020000
3208 +endif
3209 +
3210 +#
3211 # DECstation family
3212 #
3213 ifdef CONFIG_DECSTATION
3214 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3215 --- linux.old/arch/mips/mm/init.c 2005-07-07 05:38:31.345491560 +0200
3216 +++ linux.dev/arch/mips/mm/init.c 2005-07-07 04:39:14.426225000 +0200
3217 @@ -40,8 +40,10 @@
3218
3219 mmu_gather_t mmu_gathers[NR_CPUS];
3220 unsigned long highstart_pfn, highend_pfn;
3221 +#ifndef CONFIG_AR7_PAGING
3222 static unsigned long totalram_pages;
3223 static unsigned long totalhigh_pages;
3224 +#endif
3225
3226 void pgd_init(unsigned long page)
3227 {
3228 @@ -235,6 +237,7 @@
3229 #endif
3230 }
3231
3232 +#ifndef CONFIG_AR7_PAGING
3233 void __init paging_init(void)
3234 {
3235 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3236 @@ -272,6 +275,7 @@
3237
3238 free_area_init(zones_size);
3239 }
3240 +#endif
3241
3242 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3243 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3244 @@ -298,6 +302,7 @@
3245 return 0;
3246 }
3247
3248 +#ifndef CONFIG_AR7_PAGING
3249 void __init mem_init(void)
3250 {
3251 unsigned long codesize, reservedpages, datasize, initsize;
3252 @@ -359,6 +364,7 @@
3253 initsize >> 10,
3254 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3255 }
3256 +#endif
3257
3258 #ifdef CONFIG_BLK_DEV_INITRD
3259 void free_initrd_mem(unsigned long start, unsigned long end)
3260 @@ -376,6 +382,7 @@
3261 }
3262 #endif
3263
3264 +#ifndef CONFIG_AR7_PAGING
3265 extern char __init_begin, __init_end;
3266 extern void prom_free_prom_memory(void) __init;
3267
3268 @@ -383,7 +390,9 @@
3269 {
3270 unsigned long addr;
3271
3272 +#ifndef CONFIG_AR7
3273 prom_free_prom_memory ();
3274 +#endif
3275
3276 addr = (unsigned long) &__init_begin;
3277 while (addr < (unsigned long) &__init_end) {
3278 @@ -409,3 +418,4 @@
3279
3280 return;
3281 }
3282 +#endif
3283 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
3284 --- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-07 05:38:31.346491408 +0200
3285 +++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-07 04:39:14.427225000 +0200
3286 @@ -20,6 +20,10 @@
3287 #include <asm/pgtable.h>
3288 #include <asm/system.h>
3289
3290 +#ifdef CONFIG_AR7
3291 +#include <asm/ar7/ar7.h>
3292 +#endif
3293 +
3294 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3295
3296 /* CP0 hazard avoidance. */
3297 @@ -375,7 +379,12 @@
3298 else if (current_cpu_data.cputype == CPU_R4600)
3299 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3300 else
3301 +#ifdef CONFIG_AR7
3302 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
3303 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
3304 +#else
3305 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3306 flush_icache_range(KSEG0, KSEG0 + 0x80);
3307 +#endif
3308 }
3309 }
3310 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
3311 --- linux.old/drivers/char/serial.c 2005-07-07 05:38:31.348491104 +0200
3312 +++ linux.dev/drivers/char/serial.c 2005-07-07 04:39:14.429225000 +0200
3313 @@ -419,7 +419,40 @@
3314 return 0;
3315 }
3316
3317 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3318 +#if defined(CONFIG_AR7)
3319 +
3320 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3321 +{
3322 + return (inb(info->port + (offset * 4)) & 0xff);
3323 +}
3324 +
3325 +
3326 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3327 +{
3328 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3329 + return (inb(info->port + (offset * 4)) & 0xff);
3330 +#else
3331 + return (inb_p(info->port + (offset * 4)) & 0xff);
3332 +#endif
3333 +}
3334 +
3335 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3336 +{
3337 + outb(value, info->port + (offset * 4));
3338 +}
3339 +
3340 +
3341 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3342 + int value)
3343 +{
3344 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3345 + outb(value, info->port + (offset * 4));
3346 +#else
3347 + outb_p(value, info->port + (offset * 4));
3348 +#endif
3349 +}
3350 +
3351 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3352
3353 #include <asm/mips-boards/atlas.h>
3354
3355 @@ -478,8 +511,10 @@
3356 * needed for certain old 386 machines, I've left these #define's
3357 * in....
3358 */
3359 +#ifdef CONFIG_AR7
3360 #define serial_inp(info, offset) serial_in(info, offset)
3361 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3362 +#endif
3363
3364
3365 /*
3366 @@ -1728,7 +1763,15 @@
3367 /* Special case since 134 is really 134.5 */
3368 quot = (2*baud_base / 269);
3369 else if (baud)
3370 +#ifdef CONFIG_AR7
3371 + quot = get_avalanche_vbus_freq() / baud;
3372 +
3373 + if ((quot%16)>7)
3374 + quot += 8;
3375 + quot /=16;
3376 +#else
3377 quot = baud_base / baud;
3378 +#endif
3379 }
3380 /* If the quotient is zero refuse the change */
3381 if (!quot && old_termios) {
3382 @@ -5552,8 +5595,10 @@
3383 state->irq = irq_cannonicalize(state->irq);
3384 if (state->hub6)
3385 state->io_type = SERIAL_IO_HUB6;
3386 +#ifndef CONFIG_AR7
3387 if (state->port && check_region(state->port,8))
3388 continue;
3389 +#endif
3390 #ifdef CONFIG_MCA
3391 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3392 continue;
3393 @@ -6009,7 +6054,15 @@
3394 info->io_type = state->io_type;
3395 info->iomem_base = state->iomem_base;
3396 info->iomem_reg_shift = state->iomem_reg_shift;
3397 +#ifdef CONFIG_AR7
3398 + quot = get_avalanche_vbus_freq() / baud;
3399 +
3400 + if ((quot%16)>7)
3401 + quot += 8;
3402 + quot /=16;
3403 +#else
3404 quot = state->baud_base / baud;
3405 +#endif
3406 cval = cflag & (CSIZE | CSTOPB);
3407 #if defined(__powerpc__) || defined(__alpha__)
3408 cval >>= 8;
3409 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
3410 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3411 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-07 04:39:14.430224000 +0200
3412 @@ -0,0 +1,137 @@
3413 +#ifndef _MIPS_AR7_H
3414 +#define _MIPS_AR7_H
3415 +
3416 +#include <linux/config.h>
3417 +#include <asm/addrspace.h>
3418 +
3419 +
3420 +#ifndef LITTLE_ENDIAN
3421 +#define LITTLE_ENDIAN
3422 +#endif
3423 +
3424 +#ifndef _LINK_KSEG0_
3425 +#define _LINK_KSEG0_
3426 +#endif
3427 +
3428 +#include <asm/ar7/tnetd73xx.h>
3429 +
3430 +#define AVALANCHE_UART0_INT 7
3431 +#define AVALANCHE_UART1_INT 8
3432 +
3433 +#define MIPS_EXCEPTION_OFFSET 8
3434 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3435 +
3436 +/*
3437 + * AR7 board SDRAM base address. This is used to setup the
3438 + * bootmem tables
3439 + */
3440 +
3441 +#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
3442 +#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
3443 +
3444 +
3445 +/*
3446 + * AR7 board vectors
3447 + */
3448 +
3449 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3450 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3451 +
3452 +
3453 +/*
3454 + * Yamon Prom print address.
3455 + */
3456 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3457 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3458 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3459 +
3460 +/*
3461 + * AR7 Reset and PSU standby register.
3462 + */
3463 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3464 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3465 +#define AVALANCHE_GORESET 0x1
3466 +#define AVALANCHE_GOSTBY 0x1
3467 +#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
3468 +
3469 +/*
3470 + * Avalanche UART register base.
3471 + */
3472 +
3473 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3474 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3475 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3476 +
3477 +/*
3478 + * AVALANCHE DMA controller base
3479 + */
3480 +
3481 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3482 +
3483 +
3484 +
3485 +/*
3486 + * GPIO register map
3487 + */
3488 +
3489 +/* to be obtained from avalanche_map.h */
3490 +#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
3491 +#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
3492 +#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
3493 +#define AVALANCHE_GPIO_PIN_COUNT 32
3494 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
3495 +
3496 +
3497 +// Let us define board specific information here.
3498 +
3499 +#if defined(CONFIG_AR7DB)
3500 +
3501 +#define AFECLK_FREQ 35328000
3502 +#define REFCLK_FREQ 25000000
3503 +#define OSC3_FREQ 24000000
3504 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3505 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
3506 +
3507 +#endif
3508 +
3509 +
3510 +#if defined(CONFIG_AR7RD)
3511 +
3512 +#define AFECLK_FREQ 35328000
3513 +#define REFCLK_FREQ 25000000
3514 +#define OSC3_FREQ 24000000
3515 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3516 +
3517 +#if defined(CONFIG_AR7_MARVELL)
3518 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3519 +#else
3520 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3521 +#endif
3522 +
3523 +#endif
3524 +
3525 +
3526 +#if defined(CONFIG_AR7WRD)
3527 +
3528 +#define AFECLK_FREQ 35328000
3529 +#define REFCLK_FREQ 25000000
3530 +#define OSC3_FREQ 24000000
3531 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3532 +
3533 +#if defined(CONFIG_AR7_MARVELL)
3534 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3535 +#else
3536 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3537 +#endif
3538 +
3539 +#endif
3540 +
3541 +extern unsigned int tnetd73xx_vbus_freq;
3542 +#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
3543 +
3544 +static inline unsigned int get_avalanche_vbus_freq(void)
3545 +{
3546 + return (tnetd73xx_vbus_freq);
3547 +}
3548 +
3549 +#endif /*_MIPS_AR7_H */
3550 diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h
3551 --- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
3552 +++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-07 04:39:14.430224000 +0200
3553 @@ -0,0 +1,183 @@
3554 +/* $Id$
3555 + *
3556 + * avalanche.h
3557 + *
3558 + * Jeff Harrell, jharrell@ti.com
3559 + * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
3560 + *
3561 + *
3562 + * ########################################################################
3563 + *
3564 + * This program is free software; you can distribute it and/or modify it
3565 + * under the terms of the GNU General Public License (Version 2) as
3566 + * published by the Free Software Foundation.
3567 + *
3568 + * This program is distributed in the hope it will be useful, but WITHOUT
3569 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3570 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3571 + * for more details.
3572 + *
3573 + * You should have received a copy of the GNU General Public License along
3574 + * with this program; if not, write to the Free Software Foundation, Inc.,
3575 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3576 + *
3577 + * ########################################################################
3578 + *
3579 + * Defines of the AVALANCHE board specific address-MAP, registers, etc.
3580 + *
3581 + */
3582 +#ifndef _MIPS_AVALANCHE_H
3583 +#define _MIPS_AVALANCHE_H
3584 +
3585 +#include <asm/addrspace.h>
3586 +
3587 +/*
3588 + * AVALANCHE board SDRAM base address. This is used to setup the
3589 + * bootmem tables
3590 + */
3591 +
3592 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
3593 +
3594 +/*
3595 + * AVALANCHE board vectors
3596 + */
3597 +
3598 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3599 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3600 +/*
3601 + * Avalanche RTC-device indirect register access.
3602 + */
3603 +
3604 +#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
3605 +#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
3606 +
3607 +/*
3608 + * Evm3 interrupt controller register base (primary)
3609 + */
3610 +
3611 +#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
3612 +
3613 +/*
3614 + * Avalanche exception controller register base (secondary)
3615 + */
3616 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
3617 +
3618 +
3619 +/*
3620 + * Avalanche Interrupt Channel Control register base
3621 + */
3622 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3623 +
3624 +
3625 +/*
3626 + * Avalanche UART register base.
3627 + */
3628 +
3629 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3630 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3631 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3632 +/*
3633 + * AVALANCHE DMA controller base
3634 + */
3635 +
3636 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3637 +
3638 +
3639 +/*
3640 + * AVALANCHE display register base.
3641 + */
3642 +
3643 +#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
3644 +#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
3645 +
3646 +
3647 +#define EVM3_ASCIIPOS0 0x1D000038
3648 +#define EVM3_ASCIIPOS1 0x1D000039
3649 +#define EVM3_ASCIIPOS2 0x1D00003A
3650 +#define EVM3_ASCIIPOS3 0x1D00003B
3651 +#define EVM3_ASCIIPOS4 0x1D00003C
3652 +#define EVM3_ASCIIPOS5 0x1D00003D
3653 +#define EVM3_ASCIIPOS6 0x1D00003E
3654 +#define EVM3_ASCIIPOS7 0x1D00003F
3655 +
3656 +/*
3657 + * Yamon Prom print address.
3658 + */
3659 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3660 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3661 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3662 +
3663 +/*
3664 + * Evm3 Reset and PSU standby register.
3665 + */
3666 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3667 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3668 +#define AVALANCHE_GORESET 0x1
3669 +#define AVALANCHE_GOSTBY 0x1
3670 +
3671 +/************************************************************************
3672 + * PERIPHERAL BUS LEDs (P-LED):
3673 +*************************************************************************/
3674 +
3675 +/************************************************************************
3676 + * P-LED Register Addresses
3677 +*************************************************************************/
3678 +
3679 +#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
3680 +
3681 +
3682 +/************************************************************************
3683 + * Register field encodings
3684 +*************************************************************************/
3685 +
3686 +/******** reg: PLED ********/
3687 +/* bits 7:0: VAL */
3688 +#define EVM3_PLED_VAL_MSK 0xff
3689 +
3690 +/* bit 0: */
3691 +#define EVM3_PLED_BIT0_SHF 0
3692 +#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
3693 +#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
3694 +
3695 +/* bit 1: */
3696 +#define EVM3_PLED_BIT1_SHF 1
3697 +#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
3698 +#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
3699 +
3700 +/* bit 2: */
3701 +#define EVM3_PLED_BIT2_SHF 2
3702 +#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
3703 +#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
3704 +
3705 +/* bit 3: */
3706 +#define EVM3_PLED_BIT3_SHF 3
3707 +#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
3708 +#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
3709 +
3710 +/* bit 4: */
3711 +#define EVM3_PLED_BIT4_SHF 4
3712 +#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
3713 +#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
3714 +
3715 +/* bit 5: */
3716 +#define EVM3_PLED_BIT5_SHF 5
3717 +#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
3718 +#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
3719 +
3720 +/* bit 6: */
3721 +#define EVM3_PLED_BIT6_SHF 6
3722 +#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
3723 +#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
3724 +
3725 +/* bit 7: */
3726 +#define EVM3_PLED_BIT7_SHF 7
3727 +#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
3728 +#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
3729 +
3730 +#endif /* !(_MIPS_AVALANCHE_H) */
3731 +
3732 +
3733 +
3734 +
3735 +
3736 +
3737 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
3738 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
3739 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-07 04:39:14.431224000 +0200
3740 @@ -0,0 +1,273 @@
3741 + /*
3742 + * Nitin Dhingra, iamnd@ti.com
3743 + * Copyright (C) 2000 Texas Instruments Inc.
3744 + *
3745 + *
3746 + * ########################################################################
3747 + *
3748 + * This program is free software; you can distribute it and/or modify it
3749 + * under the terms of the GNU General Public License (Version 2) as
3750 + * published by the Free Software Foundation.
3751 + *
3752 + * This program is distributed in the hope it will be useful, but WITHOUT
3753 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3754 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3755 + * for more details.
3756 + *
3757 + * You should have received a copy of the GNU General Public License along
3758 + * with this program; if not, write to the Free Software Foundation, Inc.,
3759 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3760 + *
3761 + * ########################################################################
3762 + *
3763 + * Defines of the Sead board specific address-MAP, registers, etc.
3764 + *
3765 + */
3766 +#ifndef _AVALANCHE_INTC_H
3767 +#define _AVALANCHE_INTC_H
3768 +
3769 +#define MIPS_EXCEPTION_OFFSET 8
3770 +
3771 +/******************************************************************************
3772 + Avalanche Interrupt number
3773 +******************************************************************************/
3774 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3775 +
3776 +/*******************************************************************************
3777 +*Linux Interrupt number
3778 +*******************************************************************************/
3779 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3780 +
3781 +
3782 +
3783 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
3784 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
3785 +
3786 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3787 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3788 +
3789 +
3790 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
3791 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
3792 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
3793 +
3794 +
3795 +/*
3796 + * Avalanche interrupt controller register base (primary)
3797 + */
3798 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
3799 +
3800 +/******************************************************************************
3801 + * Avalanche exception controller register base (secondary)
3802 + ******************************************************************************/
3803 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
3804 +
3805 +
3806 +/******************************************************************************
3807 + * Avalanche Interrupt pacing register base (secondary)
3808 + ******************************************************************************/
3809 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
3810 +
3811 +
3812 +
3813 +/******************************************************************************
3814 + * Avalanche Interrupt Channel Control register base
3815 + *****************************************************************************/
3816 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3817 +
3818 +
3819 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3820 +{
3821 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
3822 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
3823 + volatile unsigned long unused1; /*0x08 */
3824 + volatile unsigned long unused2; /*0x0C */
3825 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
3826 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
3827 + volatile unsigned long unused3; /*0x18 */
3828 + volatile unsigned long unused4; /*0x1C */
3829 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
3830 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
3831 + volatile unsigned long unused5; /*0x28 */
3832 + volatile unsigned long unused6; /*0x2C */
3833 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
3834 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
3835 + volatile unsigned long unused7; /* 0x38 */
3836 + volatile unsigned long unused8; /* 0x3c */
3837 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
3838 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
3839 + volatile unsigned long unused9; /* 0x48 */
3840 + volatile unsigned long unused10; /* 0x4C */
3841 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
3842 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
3843 + volatile unsigned long unused11; /* 0x58 */
3844 + volatile unsigned long unused12; /*0x5C */
3845 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
3846 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
3847 +};
3848 +
3849 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3850 +{
3851 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
3852 + volatile unsigned long reserved; /*0x84 */
3853 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
3854 + volatile unsigned long reserved1; /*0x8c */
3855 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
3856 + volatile unsigned long reserved2; /*0x94 */
3857 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
3858 +};
3859 +struct avalanche_ipace_regs
3860 +{
3861 +
3862 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
3863 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
3864 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
3865 +};
3866 +struct avalanche_channel_int_number
3867 +{
3868 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
3869 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
3870 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
3871 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
3872 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
3873 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
3874 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
3875 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
3876 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
3877 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
3878 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
3879 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
3880 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
3881 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
3882 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
3883 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
3884 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
3885 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
3886 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
3887 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
3888 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
3889 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
3890 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
3891 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
3892 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
3893 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
3894 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
3895 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
3896 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
3897 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
3898 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
3899 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
3900 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
3901 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
3902 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
3903 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
3904 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
3905 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
3906 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
3907 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
3908 +};
3909 +
3910 +struct avalanche_interrupt_line_to_channel
3911 +{
3912 + unsigned long int_line0; /* Start of primary interrupts */
3913 + unsigned long int_line1;
3914 + unsigned long int_line2;
3915 + unsigned long int_line3;
3916 + unsigned long int_line4;
3917 + unsigned long int_line5;
3918 + unsigned long int_line6;
3919 + unsigned long int_line7;
3920 + unsigned long int_line8;
3921 + unsigned long int_line9;
3922 + unsigned long int_line10;
3923 + unsigned long int_line11;
3924 + unsigned long int_line12;
3925 + unsigned long int_line13;
3926 + unsigned long int_line14;
3927 + unsigned long int_line15;
3928 + unsigned long int_line16;
3929 + unsigned long int_line17;
3930 + unsigned long int_line18;
3931 + unsigned long int_line19;
3932 + unsigned long int_line20;
3933 + unsigned long int_line21;
3934 + unsigned long int_line22;
3935 + unsigned long int_line23;
3936 + unsigned long int_line24;
3937 + unsigned long int_line25;
3938 + unsigned long int_line26;
3939 + unsigned long int_line27;
3940 + unsigned long int_line28;
3941 + unsigned long int_line29;
3942 + unsigned long int_line30;
3943 + unsigned long int_line31;
3944 + unsigned long int_line32;
3945 + unsigned long int_line33;
3946 + unsigned long int_line34;
3947 + unsigned long int_line35;
3948 + unsigned long int_line36;
3949 + unsigned long int_line37;
3950 + unsigned long int_line38;
3951 + unsigned long int_line39;
3952 +};
3953 +
3954 +
3955 +/* Interrupt Line #'s (Sangam peripherals) */
3956 +
3957 +/*------------------------------*/
3958 +/* Sangam primary interrupts */
3959 +/*------------------------------*/
3960 +
3961 +#define UNIFIED_SECONDARY_INTERRUPT 0
3962 +#define AVALANCHE_EXT_INT_0 1
3963 +#define AVALANCHE_EXT_INT_1 2
3964 +/* Line #3 Reserved */
3965 +/* Line #4 Reserved */
3966 +#define AVALANCHE_TIMER_0_INT 5
3967 +#define AVALANCHE_TIMER_1_INT 6
3968 +#define AVALANCHE_UART0_INT 7
3969 +#define AVALANCHE_UART1_INT 8
3970 +#define AVALANCHE_PDMA_INT0 9
3971 +#define AVALANCHE_PDMA_INT1 10
3972 +/* Line #11 Reserved */
3973 +/* Line #12 Reserved */
3974 +/* Line #13 Reserved */
3975 +/* Line #14 Reserved */
3976 +#define AVALANCHE_ATM_SAR_INT 15
3977 +/* Line #16 Reserved */
3978 +/* Line #17 Reserved */
3979 +/* Line #18 Reserved */
3980 +#define AVALANCHE_MAC0_INT 19
3981 +/* Line #20 Reserved */
3982 +#define AVALANCHE_VLYNQ0_INT 21
3983 +#define AVALANCHE_CODEC_WAKE_INT 22
3984 +/* Line #23 Reserved */
3985 +#define AVALANCHE_USB_INT 24
3986 +#define AVALANCHE_VLYNQ1_INT 25
3987 +/* Line #26 Reserved */
3988 +/* Line #27 Reserved */
3989 +#define AVALANCHE_MAC1_INT 28
3990 +#define AVALANCHE_I2CM_INT 29
3991 +#define AVALANCHE_PDMA_INT2 30
3992 +#define AVALANCHE_PDMA_INT3 31
3993 +/* Line #32 Reserved */
3994 +/* Line #33 Reserved */
3995 +/* Line #34 Reserved */
3996 +/* Line #35 Reserved */
3997 +/* Line #36 Reserved */
3998 +#define AVALANCHE_VDMA_VT_RX_INT 37
3999 +#define AVALANCHE_VDMA_VT_TX_INT 38
4000 +#define AVALANCHE_ADSLSS_INT 39
4001 +
4002 +/*-----------------------------------*/
4003 +/* Sangam Secondary Interrupts */
4004 +/*-----------------------------------*/
4005 +#define PRIMARY_INTS 40
4006 +
4007 +#define EMIF_INT (7 + PRIMARY_INTS)
4008 +
4009 +
4010 +extern void avalanche_int_set(int channel, int line);
4011 +
4012 +
4013 +#endif /* _AVALANCHE_INTC_H */
4014 diff -urN linux.old/include/asm-mips/ar7/avalanche_int.h linux.dev/include/asm-mips/ar7/avalanche_int.h
4015 --- linux.old/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100
4016 +++ linux.dev/include/asm-mips/ar7/avalanche_int.h 2005-07-07 04:39:14.431224000 +0200
4017 @@ -0,0 +1,298 @@
4018 +/* $Id$
4019 + *
4020 + * avalancheint.h
4021 + *
4022 + * Jeff Harrell, jharrell@ti.com
4023 + * Copyright (C) 2000,2001 Texas Instruments , Inc.
4024 + *
4025 + * ########################################################################
4026 + *
4027 + * This program is free software; you can distribute it and/or modify it
4028 + * under the terms of the GNU General Public License (Version 2) as
4029 + * published by the Free Software Foundation.
4030 + *
4031 + * This program is distributed in the hope it will be useful, but WITHOUT
4032 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4033 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4034 + * for more details.
4035 + *
4036 + * You should have received a copy of the GNU General Public License along
4037 + * with this program; if not, write to the Free Software Foundation, Inc.,
4038 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4039 + *
4040 + * ########################################################################
4041 + *
4042 + * Defines for the AVALANCHE interrupt controller.
4043 + *
4044 + */
4045 +#ifndef _MIPS_AVALANCHEINT_H
4046 +#define _MIPS_AVALANCHEINT_H
4047 +
4048 +#include <linux/config.h>
4049 +
4050 +/* Avalanche Interrupt number */
4051 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
4052 +/* Linux Interrupt number */
4053 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
4054 +/* Number of IRQ supported on hw interrupt 0. */
4055 +
4056 +//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
4057 +//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
4058 +
4059 +
4060 +#define MIPS_EXCEPTION_OFFSET 8
4061 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
4062 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
4063 +
4064 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
4065 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
4066 +
4067 +
4068 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
4069 + + MIPS_EXCEPTION_OFFSET - 1)
4070 +
4071 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
4072 +{
4073 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */
4074 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */
4075 + volatile unsigned long unused1; /* 0x08 */
4076 + volatile unsigned long unused2; /* 0x0C */
4077 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */
4078 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */
4079 + volatile unsigned long unused3; /* 0x18 */
4080 + volatile unsigned long unused4; /* 0x1C */
4081 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
4082 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
4083 + volatile unsigned long unused5; /* 0x28 */
4084 + volatile unsigned long unused6; /* 0x2C */
4085 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */
4086 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */
4087 + volatile unsigned long unused7; /* 0x38 */
4088 + volatile unsigned long unused8; /* 0x3c */
4089 + volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */
4090 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
4091 + volatile unsigned long unused9; /* 0x48 */
4092 + volatile unsigned long unused10; /* 0x4C */
4093 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */
4094 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */
4095 +};
4096 +
4097 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
4098 +{
4099 + volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */
4100 + volatile unsigned long reserved; /* 0x84 */
4101 + volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */
4102 + volatile unsigned long reserved1; /* 0x8c */
4103 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */
4104 + volatile unsigned long reserved2; /* 0x94 */
4105 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
4106 +};
4107 +
4108 +struct avalanche_channel_int_number
4109 +{
4110 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */
4111 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */
4112 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */
4113 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */
4114 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */
4115 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */
4116 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */
4117 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */
4118 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */
4119 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */
4120 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */
4121 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */
4122 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */
4123 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */
4124 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */
4125 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */
4126 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */
4127 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */
4128 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */
4129 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */
4130 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */
4131 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */
4132 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */
4133 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */
4134 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */
4135 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */
4136 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */
4137 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */
4138 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */
4139 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */
4140 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */
4141 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */
4142 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */
4143 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */
4144 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */
4145 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */
4146 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */
4147 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */
4148 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */
4149 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */
4150 +};
4151 +
4152 +struct avalanche_interrupt_line_to_channel
4153 +{
4154 + unsigned long int_line0; /* Start of primary interrupts */
4155 + unsigned long int_line1;
4156 + unsigned long int_line2;
4157 + unsigned long int_line3;
4158 + unsigned long int_line4;
4159 + unsigned long int_line5;
4160 + unsigned long int_line6;
4161 + unsigned long int_line7;
4162 + unsigned long int_line8;
4163 + unsigned long int_line9;
4164 + unsigned long int_line10;
4165 + unsigned long int_line11;
4166 + unsigned long int_line12;
4167 + unsigned long int_line13;
4168 + unsigned long int_line14;
4169 + unsigned long int_line15;
4170 + unsigned long int_line16;
4171 + unsigned long int_line17;
4172 + unsigned long int_line18;
4173 + unsigned long int_line19;
4174 + unsigned long int_line20;
4175 + unsigned long int_line21;
4176 + unsigned long int_line22;
4177 + unsigned long int_line23;
4178 + unsigned long int_line24;
4179 + unsigned long int_line25;
4180 + unsigned long int_line26;
4181 + unsigned long int_line27;
4182 + unsigned long int_line28;
4183 + unsigned long int_line29;
4184 + unsigned long int_line30;
4185 + unsigned long int_line31;
4186 + unsigned long int_line32;
4187 + unsigned long int_line33;
4188 + unsigned long int_line34;
4189 + unsigned long int_line35;
4190 + unsigned long int_line36;
4191 + unsigned long int_line37;
4192 + unsigned long int_line38;
4193 + unsigned long int_line39;
4194 +};
4195 +
4196 +/* Interrupt Line #'s (Avalanche peripherals) */
4197 +
4198 +/*------------------------------*/
4199 +/* Avalanche primary interrupts */
4200 +/*------------------------------*/
4201 +#define UNIFIED_SECONDARY_INTERRUPT 0
4202 +#define AVALANCHE_EXT_INT_0 1
4203 +#define AVALANCHE_EXT_INT_1 2
4204 +#define AVALANCHE_EXT_INT_2 3
4205 +#define AVALANCHE_EXT_INT_3 4
4206 +#define AVALANCHE_TIMER_0_INT 5
4207 +#define AVALANCHE_TIMER_1_INT 6
4208 +#define AVALANCHE_UART0_INT 7
4209 +#define AVALANCHE_UART1_INT 8
4210 +#define AVALANCHE_PDMA_INT0 9
4211 +#define AVALANCHE_PDMA_INT1 10
4212 +#define AVALANCHE_HDLC_TXA 11
4213 +#define AVALANCHE_HDLC_TXB 12
4214 +#define AVALANCHE_HDLC_RXA 13
4215 +#define AVALANCHE_HDLC_RXB 14
4216 +#define AVALANCHE_ATM_SAR_TXA 15
4217 +#define AVALANCHE_ATM_SAR_TXB 16
4218 +#define AVALANCHE_ATM_SAR_RXA 17
4219 +#define AVALANCHE_ATM_SAR_RXB 18
4220 +#define AVALANCHE_MAC_TXA 19
4221 +#define AVALANCHE_MAC_RXA 20
4222 +#define AVALANCHE_DSP_SUB0 21
4223 +#define AVALANCHE_DSP_SUB1 22
4224 +#define AVALANCHE_DES_INT 23
4225 +#define AVALANCHE_USB_INT 24
4226 +#define AVALANCHE_PCI_INTA 25
4227 +#define AVALANCHE_PCI_INTB 26
4228 +#define AVALANCHE_PCI_INTC 27
4229 +/* Line #28 Reserved */
4230 +#define AVALANCHE_I2CM_INT 29
4231 +#define AVALANCHE_PDMA_INT2 30
4232 +#define AVALANCHE_PDMA_INT3 31
4233 +#define AVALANCHE_CODEC 32
4234 +#define AVALANCHE_MAC_TXB 33
4235 +#define AVALANCHE_MAC_RXB 34
4236 +/* Line #35 Reserved */
4237 +/* Line #36 Reserved */
4238 +/* Line #37 Reserved */
4239 +/* Line #38 Reserved */
4240 +/* Line #39 Reserved */
4241 +
4242 +#define DEBUG_MISSED_INTS 1
4243 +
4244 +#ifdef DEBUG_MISSED_INTS
4245 +struct debug_missed_int
4246 +{
4247 + unsigned int atm_sar_txa;
4248 + unsigned int atm_sar_txb;
4249 + unsigned int atm_sar_rxa;
4250 + unsigned int atm_sar_rxb;
4251 + unsigned int mac_txa;
4252 + unsigned int mac_rxa;
4253 + unsigned int mac_txb;
4254 + unsigned int mac_rxb;
4255 +};
4256 +#endif /* DEBUG_MISSED_INTS */
4257 +
4258 +/*-----------------------------------*/
4259 +/* Avalanche Secondary Interrupts */
4260 +/*-----------------------------------*/
4261 +#define PRIMARY_INTS 40
4262 +
4263 +#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS)
4264 +#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS)
4265 +/* Line #02 Reserved */
4266 +#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS)
4267 +#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS)
4268 +#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS)
4269 +/* Line #06 Reserved */
4270 +#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS)
4271 +#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS)
4272 +#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS)
4273 +/* Line #10-#20 Reserved */
4274 +#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS)
4275 +#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS)
4276 +#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS)
4277 +/* Line #24-#31 Reserved */
4278 +
4279 +#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT)
4280 +#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT)
4281 +#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
4282 +#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
4283 +
4284 +#ifdef JIMK_INT_CTRLR
4285 +/*-----------------------------------*/
4286 +/* Jim Kennedy's Interrupt Controller*/
4287 +/*-----------------------------------*/
4288 +
4289 +/* to clear the interrupt write the bit back to the status reg */
4290 +
4291 +#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
4292 +#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404))
4293 +#define JIMK_SAR_STATUS (1<<0)
4294 +#define JIMK_SAR_TX_A (1<<1)
4295 +#define JIMK_SAR_TX_B (1<<2)
4296 +#define JIMK_SAR_RX_A (1<<3)
4297 +#define JIMK_SAR_RX_B (1<<4)
4298 +#define JIMK_AAL2_STATUS (1<<5)
4299 +#define JIMK_UART0_INT (1<<11)
4300 +
4301 +#ifdef SEAD_USB_DEVELOPMENT
4302 +#define JIMK_USB_INT (1<<0)
4303 +#endif /* SEAD_USB_DEVELOPMENT */
4304 +
4305 +#endif /* JIMK_INT_CTRLR */
4306 +
4307 +extern void avalanche_int_set(int channel, int line);
4308 +extern void avalancheint_init(void);
4309 +
4310 +
4311 +#endif /* !(_MIPS_AVALANCHEINT_H) */
4312 +
4313 +
4314 +
4315 +
4316 diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h
4317 --- linux.old/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
4318 +++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-07 04:39:14.431224000 +0200
4319 @@ -0,0 +1,54 @@
4320 +/* $Id$
4321 + *
4322 + * prom.h
4323 + *
4324 + * Carsten Langgaard, carstenl@mips.com
4325 + * Copyright (C) 1999 MIPS Technologies, Inc.
4326 + *
4327 + * ########################################################################
4328 + *
4329 + * This program is free software; you can distribute it and/or modify it
4330 + * under the terms of the GNU General Public License (Version 2) as
4331 + * published by the Free Software Foundation.
4332 + *
4333 + * This program is distributed in the hope it will be useful, but WITHOUT
4334 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4335 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4336 + * for more details.
4337 + *
4338 + * You should have received a copy of the GNU General Public License along
4339 + * with this program; if not, write to the Free Software Foundation, Inc.,
4340 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4341 + *
4342 + * ########################################################################
4343 + *
4344 + * Sead bootprom interface for the Linux kernel.
4345 + *
4346 + */
4347 +
4348 +#ifndef _MIPS_PROM_H
4349 +#define _MIPS_PROM_H
4350 +
4351 +extern char *prom_getcmdline(void);
4352 +extern char *prom_getenv(char *name);
4353 +extern void setup_prom_printf(void);
4354 +extern void prom_printf(char *fmt, ...);
4355 +extern void prom_init_cmdline(void);
4356 +extern void prom_meminit(void);
4357 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
4358 +extern void prom_free_prom_memory (void);
4359 +extern void sead_display_message(const char *str);
4360 +extern void sead_display_word(unsigned int num);
4361 +extern int get_ethernet_addr(char *ethernet_addr);
4362 +
4363 +/* Memory descriptor management. */
4364 +#define PROM_MAX_PMEMBLOCKS 32
4365 +struct prom_pmemblock {
4366 + unsigned long base; /* Within KSEG0. */
4367 + unsigned int size; /* In bytes. */
4368 + unsigned int type; /* free or prom memory */
4369 +};
4370 +
4371 +
4372 +#endif /* !(_MIPS_PROM_H) */
4373 +
4374 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
4375 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4376 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-07 04:39:14.433224000 +0200
4377 @@ -0,0 +1,567 @@
4378 +/*
4379 + * $Id$
4380 + * Avalanche Register Descriptions
4381 + *
4382 + * Jeff Harrell, jharrell@ti.com
4383 + * 2000 (c) Texas Instruments Inc.
4384 + */
4385 +
4386 +#ifndef __AVALANCHE_REGS_H
4387 +#define __AVALANCHE_REGS_H
4388 +
4389 +#include <asm/addrspace.h>
4390 +#include <linux/config.h>
4391 +
4392 +/*----------------------------------------*/
4393 +/* Base offsets within the Avalanche ASIC */
4394 +/*----------------------------------------*/
4395 +
4396 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4397 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4398 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4399 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4400 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4401 +#define DES_BASE (KSEG1ADDR(0x08600000))
4402 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4403 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4404 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4405 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4406 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4407 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4408 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4409 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4410 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4411 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4412 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4413 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4414 +#define USB_BASE (KSEG1ADDR(0x08611200))
4415 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4416 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4417 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4418 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4419 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4420 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4421 +
4422 +/*---------------------------------*/
4423 +/* Device ID, chip version number */
4424 +/*---------------------------------*/
4425 +
4426 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4427 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4428 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4429 +
4430 +/*----------------------------------*/
4431 +/* Reset Control VW changed to ptrs */
4432 +/*----------------------------------*/
4433 +
4434 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4435 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4436 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4437 +
4438 +/* reset control bits */
4439 +
4440 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4441 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4442 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4443 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4444 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4445 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4446 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4447 +/*
4448 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4449 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4450 + interface pins are inputs and must be reconfigured so as not to lose the
4451 + serial console interface
4452 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4453 +*/
4454 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4455 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4456 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4457 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4458 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4459 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4460 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4461 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4462 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4463 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4464 +
4465 +/*----------------------*/
4466 +/* Physical interfaces */
4467 +/*----------------------*/
4468 +
4469 +/* Phy loopback */
4470 +#define PHY_LOOPBACK 1
4471 +
4472 +
4473 +/* Phy 0 */
4474 +#define PHY0BASE (PHY_BASE)
4475 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4476 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4477 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4478 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4479 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4480 +
4481 +
4482 +/* Phy 1 */
4483 +
4484 +#define PHY1BASE (PHY_BASE + 0x100000)
4485 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4486 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4487 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4488 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4489 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4490 +
4491 +/* Phy 2 */
4492 +
4493 +#define PHY2BASE (PHY_BASE + 0x200000)
4494 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4495 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4496 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4497 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4498 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4499 +
4500 +/*-------------------*/
4501 +/* Avalanche ATM SAR */
4502 +/*-------------------*/
4503 +
4504 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4505 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4506 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4507 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4508 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4509 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4510 +
4511 +/* Transmit completion ring registers */
4512 +
4513 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4514 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4515 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4516 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4517 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4518 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4519 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4520 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4521 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4522 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4523 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4524 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4525 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4526 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4527 +
4528 +/* Transmit Queue Packet registers */
4529 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4530 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4531 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4532 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4533 +/* Receive completion ring registers */
4534 +
4535 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4536 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4537 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4538 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4539 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4540 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4541 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4542 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4543 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4544 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4545 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4546 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4547 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4548 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4549 +
4550 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4551 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4552 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4553 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4554 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4555 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4556 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4557 +
4558 +
4559 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4560 +
4561 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4562 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4563 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4564 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4565 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4566 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4567 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4568 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4569 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4570 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4571 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4572 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4573 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4574 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4575 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4576 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4577 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4578 +
4579 +
4580 +/*
4581 +
4582 +#define OAM_CPID_ADD 0xa30104e0
4583 +
4584 +#define OAM_LLID_ADD 0xa30104f0
4585 +
4586 +#define OAM_LLID_VAL 0xffffffff
4587 +
4588 +#define OAM_CORR_TAG 0xa3010500
4589 +
4590 +#define OAM_FAR_COUNT_ADD 0xa3010520
4591 +
4592 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4593 +
4594 +#define OAM_CONFIG_REG_ADD 0xa3000018
4595 +*/
4596 +
4597 +
4598 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4599 +
4600 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4601 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4602 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4603 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4604 +
4605 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4606 +
4607 +
4608 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4609 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4610 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4611 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4612 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4613 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4614 +
4615 +/*------------------------------------------*/
4616 +/* DSL Interface */
4617 +/*------------------------------------------*/
4618 +
4619 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4620 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4621 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4622 +
4623 +/* Fast */
4624 +
4625 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4626 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4627 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4628 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4629 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4630 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4631 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4632 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4633 +
4634 +/* Interleaved */
4635 +
4636 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4637 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4638 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4639 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4640 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4641 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4642 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4643 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4644 +
4645 +/*------------------------------------------*/
4646 +/* Broadband I/F */
4647 +/*------------------------------------------*/
4648 +
4649 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4650 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4651 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4652 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4653 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4654 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4655 +
4656 +#define AVBBIF_DISABLED 0x0
4657 +#define AVBBIF_LBT4040_INT 0x1
4658 +#define AVBBIF_XBUS 0x2
4659 +#define AVBBIF_LBT4040_EXT 0x4
4660 +
4661 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4662 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4663 +#define AVBBIF_TRANS_MASK 0xff000000
4664 +/*------------------------------------------*/
4665 +/* GPIO I/F */
4666 +/*------------------------------------------*/
4667 +
4668 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4669 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4670 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4671 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4672 +
4673 +#define GPIO_0 (1<<21)
4674 +#define GPIO_1 (1<<22)
4675 +#define GPIO_2 (1<<23)
4676 +#define GPIO_3 (1<<24)
4677 +#define EINT_1 (1<<18)
4678 +
4679 +/*
4680 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4681 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4682 + interface pins are inputs and must be reconfigured so as not to lose the
4683 + serial console interface
4684 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4685 +*/
4686 +
4687 +/*------------------------------------------*/
4688 +/* CLK_CTRL */
4689 +/*------------------------------------------*/
4690 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4691 +
4692 +#define PCLK_0_HALF_VBUS (0<<16)
4693 +#define PCLK_EQ_INPUT (1<<16)
4694 +#define BBIF_CLK_HALF_VBUS (0<<17)
4695 +#define BBIF_CLK_EQ_VBUS (1<<17)
4696 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4697 +#define DSP_MODCLK_DSPCLKI (0<<20)
4698 +#define DSP_MODCLK_REFCLKI (1<<20)
4699 +#define USB_CLK_EQ_USBCLKI (0<<21)
4700 +#define USB_CLK_EQ_REFCLKI (1<<21)
4701 +
4702 +/*------------------------------------------*/
4703 +/* PCI Control Registers */
4704 +/*------------------------------------------*/
4705 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4706 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4707 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4708 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4709 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4710 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4711 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4712 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4713 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4714 +#define PCIC_CONTROL_IO_MASK (1<<8)
4715 +/* PCIC_CONTROL_RESERVED (1<<9) */
4716 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4717 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4718 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4719 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4720 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4721 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4722 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4723 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4724 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4725 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4726 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4727 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4728 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4729 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4730 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4731 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4732 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4733 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4734 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4735 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4736 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4737 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4738 +#define PCIC_INT_CLEAR_PM (1<<0)
4739 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4740 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4741 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4742 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4743 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4744 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4745 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4746 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4747 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4748 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4749 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4750 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4751 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4752 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4753 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4754 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4755 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4756 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4757 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4758 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4759 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4760 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4761 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4762 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4763 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4764 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4765 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4766 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4767 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4768 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4769 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4770 +#define PCIC_INT_EN_PCI_PM (1<<0)
4771 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4772 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4773 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4774 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4775 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4776 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4777 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4778 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4779 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4780 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4781 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
4782 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
4783 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
4784 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
4785 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4786 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
4787 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
4788 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
4789 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
4790 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4791 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
4792 +/* PCIC_PM_CTL_RESERVED (1<<2) */
4793 +/* PCIC_PM_CTL_RESERVED (1<<3) */
4794 +/* PCIC_PM_CTL_RESERVED (1<<4) */
4795 +/* PCIC_PM_CTL_RESERVED (1<<5) */
4796 +/* PCIC_PM_CTL_RESERVED (1<<6) */
4797 +/* PCIC_PM_CTL_RESERVED (1<<7) */
4798 +/* PCIC_PM_CTL_RESERVED (1<<8) */
4799 +/* PCIC_PM_CTL_RESERVED (1<<9) */
4800 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
4801 +#define PCIC_PM_CTL_PMEIN (1<<11)
4802 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4803 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4804 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4805 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4806 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4807 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4808 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4809 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4810 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4811 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4812 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4813 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4814 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4815 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4816 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4817 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4818 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4819 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4820 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4821 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4822 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4823 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4824 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4825 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4826 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4827 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4828 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4829 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4830 +
4831 +/*------------------------------------------*/
4832 +/* IIC_INTERFACE */
4833 +/*------------------------------------------*/
4834 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
4835 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
4836 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
4837 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
4838 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
4839 +
4840 +#define I2CWRITE 0x200
4841 +#define I2CREAD 0x300
4842 +#define I2C_END_BURST 0x400
4843 +
4844 +/* read bits */
4845 +#define I2C_READ_ERROR 0x8000
4846 +#define I2C_READ_COMPLETE 0x4000
4847 +#define I2C_READ_BUSY 0x2000
4848 +
4849 +/* device types */
4850 +#define I2C_IO_EXPANDER 0x2
4851 +#define I2C_RTC 0xd
4852 +
4853 +/* device Addresses on I2C bus (EVM3) */
4854 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
4855 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
4856 +#define EVM3_RTC_I2C_ADDR 0x0
4857 +
4858 +/*------------------------------------------*/
4859 +/* Ethernet MAC register offset definitions */
4860 +/*------------------------------------------*/
4861 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
4862 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
4863 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
4864 +
4865 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4866 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
4867 +
4868 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
4869 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
4870 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
4871 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
4872 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
4873 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
4874 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
4875 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
4876 +
4877 +
4878 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
4879 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
4880 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
4881 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
4882 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
4883 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
4884 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
4885 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
4886 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
4887 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
4888 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
4889 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
4890 +
4891 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
4892 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
4893 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
4894 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
4895 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
4896 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
4897 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
4898 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
4899 +
4900 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
4901 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
4902 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
4903 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
4904 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
4905 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
4906 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
4907 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
4908 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
4909 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
4910 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
4911 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
4912 +
4913 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
4914 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
4915 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
4916 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
4917 +
4918 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
4919 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
4920 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
4921 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
4922 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
4923 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
4924 +
4925 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4926 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
4927 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
4928 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
4929 +
4930 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
4931 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4932 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
4933 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
4934 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
4935 +
4936 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
4937 +
4938 +#endif
4939 +
4940 +
4941 +
4942 +
4943 +
4944 +
4945 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
4946 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
4947 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-07 04:39:14.434224000 +0200
4948 @@ -0,0 +1,42 @@
4949 +/******************************************************************************
4950 + * FILE PURPOSE: TNETD73xx Error Definations Header File
4951 + ******************************************************************************
4952 + * FILE NAME: tnetd73xx_err.h
4953 + *
4954 + * DESCRIPTION: Error definations for TNETD73XX
4955 + *
4956 + * REVISION HISTORY:
4957 + * 27 Nov 02 - PSP TII
4958 + *
4959 + * (C) Copyright 2002, Texas Instruments, Inc
4960 + *******************************************************************************/
4961 +
4962 +
4963 +#ifndef __TNETD73XX_ERR_H__
4964 +#define __TNETD73XX_ERR_H__
4965 +
4966 +typedef enum TNETD73XX_ERR_t
4967 +{
4968 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
4969 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
4970 +
4971 + /* Pointers and args */
4972 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
4973 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
4974 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
4975 +
4976 + /* Memory issues */
4977 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
4978 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
4979 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
4980 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
4981 +
4982 + /* Device issues */
4983 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
4984 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
4985 +
4986 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
4987 +
4988 +} TNETD73XX_ERR;
4989 +
4990 +#endif /* __TNETD73XX_ERR_H__ */
4991 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
4992 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
4993 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-07 04:39:14.433224000 +0200
4994 @@ -0,0 +1,340 @@
4995 +/******************************************************************************
4996 + * FILE PURPOSE: TNETD73xx Common Header File
4997 + ******************************************************************************
4998 + * FILE NAME: tnetd73xx.h
4999 + *
5000 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
5001 + *
5002 + * REVISION HISTORY:
5003 + * 27 Nov 02 - PSP TII
5004 + *
5005 + * (C) Copyright 2002, Texas Instruments, Inc
5006 + *******************************************************************************/
5007 +
5008 +/*
5009 + *
5010 + *
5011 + * These are const, typedef, and api definitions for tnetd73xx.
5012 + *
5013 + * NOTES:
5014 + * 1. This file may be included into both C and Assembly files.
5015 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5016 + * avoid C data types (typedefs) below;
5017 + * - for .c files, you don't have to do anything special.
5018 + *
5019 + * 2. This file has a number of sections for each SOC subsystem. When adding
5020 + * a new constant, find the subsystem you are working on and follow the
5021 + * name pattern. If you are adding another typedef for your interface, please,
5022 + * place it with other typedefs and function prototypes.
5023 + *
5024 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5025 + * cluttering. Include such items directly into the module's .c file or have a
5026 + * local .h file to pass data between smaller modules. This file defines only
5027 + * shared items.
5028 + */
5029 +
5030 +#ifndef __TNETD73XX_H__
5031 +#define __TNETD73XX_H__
5032 +
5033 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
5034 +
5035 +#include <linux/types.h>
5036 +
5037 +extern unsigned int tnetd73xx_mips_freq;
5038 +extern unsigned int tnetd73xx_vbus_freq;
5039 +
5040 +#include "tnetd73xx_err.h"
5041 +
5042 +#endif /* _ASMLANGUAGE */
5043 +
5044 +
5045 +/*******************************************************************************************
5046 +* Emerald core specific
5047 +******************************************************************************************** */
5048 +
5049 +#ifdef BIG_ENDIAN
5050 +#elif defined(LITTLE_ENDIAN)
5051 +#else
5052 +#error Need to define endianism
5053 +#endif
5054 +
5055 +#ifndef KSEG_MSK
5056 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5057 +#endif
5058 +
5059 +#ifndef KSEG_INV_MASK
5060 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5061 +#endif
5062 +
5063 +#ifndef KSEG0_BASE
5064 +#define KSEG0_BASE 0x80000000
5065 +#endif
5066 +
5067 +#ifndef KSEG1_BASE
5068 +#define KSEG1_BASE 0xA0000000
5069 +#endif
5070 +
5071 +#ifndef KSEG0
5072 +#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5073 +#endif
5074 +
5075 +#ifndef KSEG1
5076 +#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5077 +#endif
5078 +
5079 +#ifndef KUSEG
5080 +#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
5081 +#endif
5082 +
5083 +#ifndef PHYS_ADDR
5084 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5085 +#endif
5086 +
5087 +#ifndef PHYS_TO_K0
5088 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5089 +#endif
5090 +
5091 +#ifndef PHYS_TO_K1
5092 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5093 +#endif
5094 +
5095 +#ifndef REG8_ADDR
5096 +#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
5097 +#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
5098 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5099 +#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
5100 +#endif
5101 +
5102 +#ifndef REG16_ADDR
5103 +#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
5104 +#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
5105 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5106 +#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
5107 +#endif
5108 +
5109 +#ifndef REG32_ADDR
5110 +#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
5111 +#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
5112 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5113 +#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
5114 +#endif
5115 +
5116 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5117 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5118 +#endif
5119 +
5120 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5121 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5122 +#endif
5123 +
5124 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5125 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5126 +#endif
5127 +
5128 +/* TNETD73XX chip definations */
5129 +
5130 +#define FREQ_1MHZ 1000000
5131 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5132 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5133 +
5134 +#ifdef AR7SEAD2
5135 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5136 +#else
5137 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5138 +#endif
5139 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5140 +
5141 +
5142 +
5143 +/* Module base addresses */
5144 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5145 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5146 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5147 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5148 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5149 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5150 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5151 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5152 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5153 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5154 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5155 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5156 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5157 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5158 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5159 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5160 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5161 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5162 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5163 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5164 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5165 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5166 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5167 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5168 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5169 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5170 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5171 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5172 +
5173 +/* BBIF Registers */
5174 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5175 +
5176 +/* Device Configuration Latch Registers */
5177 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5178 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5179 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5180 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5181 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5182 +
5183 +/* GPIO Control */
5184 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5185 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5186 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5187 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5188 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5189 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5190 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5191 +
5192 +/* Reset Control */
5193 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5194 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5195 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5196 +
5197 +/* Power Control */
5198 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5199 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5200 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5201 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5202 +
5203 +/* Clock Control */
5204 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5205 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5206 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5207 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5208 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5209 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5210 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5211 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5212 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5213 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5214 +
5215 +/* EMIF control */
5216 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5217 +
5218 +/* UART */
5219 +#ifdef AR7SEAD2
5220 +#define TNETD73XX_UART_FREQ 3686400
5221 +#else
5222 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5223 +#endif
5224 +
5225 +/* Interrupt Controller */
5226 +
5227 +/* Primary interrupts */
5228 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5229 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5230 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5231 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5232 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5233 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5234 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5235 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5236 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5237 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5238 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5239 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5240 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5241 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5242 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5243 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5244 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5245 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5246 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5247 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5248 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5249 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5250 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5251 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5252 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5253 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5254 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5255 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5256 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5257 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5258 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5259 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5260 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5261 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5262 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5263 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5264 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5265 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5266 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5267 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5268 +
5269 +/* Secondary interrupts */
5270 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5271 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5272 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5273 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5274 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5275 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5276 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5277 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5278 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5279 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5280 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5281 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5282 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5283 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5284 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5285 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5286 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5287 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5288 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5289 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5290 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5291 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5292 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5293 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5294 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5295 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5296 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5297 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5298 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5299 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5300 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5301 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5302 +
5303 +/* These ugly macros are to access the -1 registers, like config1 */
5304 +#define MFC0_SEL1_OPCODE(dst, src)\
5305 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5306 + nop; \
5307 + nop; \
5308 + nop
5309 +
5310 +#define MTC0_SEL1_OPCODE(dst, src)\
5311 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5312 + nop; \
5313 + nop; \
5314 + nop
5315 +
5316 +
5317 +/* Below are Jade core specific */
5318 +#define CFG0_4K_IL_MASK 0x00380000
5319 +#define CFG0_4K_IL_SHIFT 19
5320 +#define CFG0_4K_IA_MASK 0x00070000
5321 +#define CFG0_4K_IA_SHIFT 16
5322 +#define CFG0_4K_IS_MASK 0x01c00000
5323 +#define CFG0_4K_IS_SHIFT 22
5324 +
5325 +#define CFG0_4K_DL_MASK 0x00001c00
5326 +#define CFG0_4K_DL_SHIFT 10
5327 +#define CFG0_4K_DA_MASK 0x00000380
5328 +#define CFG0_4K_DA_SHIFT 7
5329 +#define CFG0_4K_DS_MASK 0x0000E000
5330 +#define CFG0_4K_DS_SHIFT 13
5331 +
5332 +
5333 +
5334 +#endif /* __TNETD73XX_H_ */
5335 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5336 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5337 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-07 04:39:14.434224000 +0200
5338 @@ -0,0 +1,243 @@
5339 +/******************************************************************************
5340 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5341 + ******************************************************************************
5342 + * FILE NAME: tnetd73xx_misc.h
5343 + *
5344 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5345 + * FSER Modules API
5346 + * As per TNETD73xx specifications
5347 + *
5348 + * REVISION HISTORY:
5349 + * 27 Nov 02 - Sharath Kumar PSP TII
5350 + * 14 Feb 03 - Anant Gole PSP TII
5351 + *
5352 + * (C) Copyright 2002, Texas Instruments, Inc
5353 + *******************************************************************************/
5354 +
5355 +#ifndef __TNETD73XX_MISC_H__
5356 +#define __TNETD73XX_MISC_H__
5357 +
5358 +#include <linux/types.h>
5359 +
5360 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
5361 +
5362 +/*****************************************************************************
5363 + * Reset Control Module
5364 + *****************************************************************************/
5365 +
5366 +typedef enum TNETD73XX_RESET_MODULE_tag
5367 +{
5368 + RESET_MODULE_UART0 = 0,
5369 + RESET_MODULE_UART1 = 1,
5370 + RESET_MODULE_I2C = 2,
5371 + RESET_MODULE_TIMER0 = 3,
5372 + RESET_MODULE_TIMER1 = 4,
5373 + RESET_MODULE_GPIO = 6,
5374 + RESET_MODULE_ADSLSS = 7,
5375 + RESET_MODULE_USBS = 8,
5376 + RESET_MODULE_SAR = 9,
5377 + RESET_MODULE_VDMA_VT = 11,
5378 + RESET_MODULE_FSER = 12,
5379 + RESET_MODULE_VLYNQ1 = 16,
5380 + RESET_MODULE_EMAC0 = 17,
5381 + RESET_MODULE_DMA = 18,
5382 + RESET_MODULE_BIST = 19,
5383 + RESET_MODULE_VLYNQ0 = 20,
5384 + RESET_MODULE_EMAC1 = 21,
5385 + RESET_MODULE_MDIO = 22,
5386 + RESET_MODULE_ADSLSS_DSP = 23,
5387 + RESET_MODULE_EPHY = 26
5388 +} TNETD73XX_RESET_MODULE_T;
5389 +
5390 +typedef enum TNETD73XX_RESET_CTRL_tag
5391 +{
5392 + IN_RESET = 0,
5393 + OUT_OF_RESET
5394 +} TNETD73XX_RESET_CTRL_T;
5395 +
5396 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5397 +{
5398 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5399 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5400 +} TNETD73XX_SYS_RST_MODE_T;
5401 +
5402 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5403 +{
5404 + HARDWARE_RESET = 0,
5405 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5406 + WATCHDOG_RESET,
5407 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
5408 +} TNETD73XX_SYS_RESET_STATUS_T;
5409 +
5410 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5411 + TNETD73XX_RESET_CTRL_T reset_ctrl);
5412 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5413 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5414 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5415 +
5416 +/*****************************************************************************
5417 + * Power Control Module
5418 + *****************************************************************************/
5419 +
5420 +typedef enum TNETD73XX_POWER_MODULE_tag
5421 +{
5422 + POWER_MODULE_USBSP = 0,
5423 + POWER_MODULE_WDTP = 1,
5424 + POWER_MODULE_UT0P = 2,
5425 + POWER_MODULE_UT1P = 3,
5426 + POWER_MODULE_IICP = 4,
5427 + POWER_MODULE_VDMAP = 5,
5428 + POWER_MODULE_GPIOP = 6,
5429 + POWER_MODULE_VLYNQ1P = 7,
5430 + POWER_MODULE_SARP = 8,
5431 + POWER_MODULE_ADSLP = 9,
5432 + POWER_MODULE_EMIFP = 10,
5433 + POWER_MODULE_ADSPP = 12,
5434 + POWER_MODULE_RAMP = 13,
5435 + POWER_MODULE_ROMP = 14,
5436 + POWER_MODULE_DMAP = 15,
5437 + POWER_MODULE_BISTP = 16,
5438 + POWER_MODULE_TIMER0P = 18,
5439 + POWER_MODULE_TIMER1P = 19,
5440 + POWER_MODULE_EMAC0P = 20,
5441 + POWER_MODULE_EMAC1P = 22,
5442 + POWER_MODULE_EPHYP = 24,
5443 + POWER_MODULE_VLYNQ0P = 27,
5444 +} TNETD73XX_POWER_MODULE_T;
5445 +
5446 +typedef enum TNETD73XX_POWER_CTRL_tag
5447 +{
5448 + POWER_CTRL_POWER_UP = 0,
5449 + POWER_CTRL_POWER_DOWN
5450 +} TNETD73XX_POWER_CTRL_T;
5451 +
5452 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5453 +{
5454 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
5455 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
5456 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
5457 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
5458 +} TNETD73XX_SYS_POWER_MODE_T;
5459 +
5460 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
5461 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5462 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5463 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5464 +
5465 +/*****************************************************************************
5466 + * Wakeup Control
5467 + *****************************************************************************/
5468 +
5469 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5470 +{
5471 + WAKEUP_INT0 = 1,
5472 + WAKEUP_INT1 = 2,
5473 + WAKEUP_INT2 = 4,
5474 + WAKEUP_INT3 = 8
5475 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5476 +
5477 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5478 +{
5479 + WAKEUP_DISABLED = 0,
5480 + WAKEUP_ENABLED
5481 +} TNETD73XX_WAKEUP_CTRL_T;
5482 +
5483 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5484 +{
5485 + WAKEUP_ACTIVE_HIGH = 0,
5486 + WAKEUP_ACTIVE_LOW
5487 +} TNETD73XX_WAKEUP_POLARITY_T;
5488 +
5489 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5490 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5491 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5492 +
5493 +/*****************************************************************************
5494 + * FSER Control
5495 + *****************************************************************************/
5496 +
5497 +typedef enum TNETD73XX_FSER_MODE_tag
5498 +{
5499 + FSER_I2C = 0,
5500 + FSER_UART = 1
5501 +} TNETD73XX_FSER_MODE_T;
5502 +
5503 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5504 +
5505 +/*****************************************************************************
5506 + * Clock Control
5507 + *****************************************************************************/
5508 +
5509 +#define CLK_MHZ(x) ( (x) * 1000000 )
5510 +
5511 +typedef enum TNETD73XX_CLKC_ID_tag
5512 +{
5513 + CLKC_SYS = 0,
5514 + CLKC_MIPS,
5515 + CLKC_USB,
5516 + CLKC_ADSLSS
5517 +} TNETD73XX_CLKC_ID_T;
5518 +
5519 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
5520 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
5521 +u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5522 +
5523 +/*****************************************************************************
5524 + * GPIO Control
5525 + *****************************************************************************/
5526 +
5527 +typedef enum TNETD73XX_GPIO_PIN_tag
5528 +{
5529 + GPIO_UART0_RD = 0,
5530 + GPIO_UART0_TD = 1,
5531 + GPIO_UART0_RTS = 2,
5532 + GPIO_UART0_CTS = 3,
5533 + GPIO_FSER_CLK = 4,
5534 + GPIO_FSER_D = 5,
5535 + GPIO_EXT_AFE_SCLK = 6,
5536 + GPIO_EXT_AFE_TX_FS = 7,
5537 + GPIO_EXT_AFE_TXD = 8,
5538 + GPIO_EXT_AFE_RS_FS = 9,
5539 + GPIO_EXT_AFE_RXD1 = 10,
5540 + GPIO_EXT_AFE_RXD0 = 11,
5541 + GPIO_EXT_AFE_CDIN = 12,
5542 + GPIO_EXT_AFE_CDOUT = 13,
5543 + GPIO_EPHY_SPEED100 = 14,
5544 + GPIO_EPHY_LINKON = 15,
5545 + GPIO_EPHY_ACTIVITY = 16,
5546 + GPIO_EPHY_FDUPLEX = 17,
5547 + GPIO_EINT0 = 18,
5548 + GPIO_EINT1 = 19,
5549 + GPIO_MBSP0_TCLK = 20,
5550 + GPIO_MBSP0_RCLK = 21,
5551 + GPIO_MBSP0_RD = 22,
5552 + GPIO_MBSP0_TD = 23,
5553 + GPIO_MBSP0_RFS = 24,
5554 + GPIO_MBSP0_TFS = 25,
5555 + GPIO_MII_DIO = 26,
5556 + GPIO_MII_DCLK = 27,
5557 +} TNETD73XX_GPIO_PIN_T;
5558 +
5559 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5560 +{
5561 + FUNCTIONAL_PIN = 0,
5562 + GPIO_PIN = 1
5563 +} TNETD73XX_GPIO_PIN_MODE_T;
5564 +
5565 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5566 +{
5567 + GPIO_OUTPUT_PIN = 0,
5568 + GPIO_INPUT_PIN = 1
5569 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5570 +
5571 +void tnetd73xx_gpio_init(void);
5572 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5573 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5574 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5575 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5576 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5577 +
5578 +/* TNETD73XX Revision */
5579 +u32 tnetd73xx_get_revision(void);
5580 +
5581 +#endif /* __TNETD73XX_MISC_H__ */
5582 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
5583 --- linux.old/include/asm-mips/io.h 2005-07-07 05:38:31.416480768 +0200
5584 +++ linux.dev/include/asm-mips/io.h 2005-07-07 04:39:14.434224000 +0200
5585 @@ -63,8 +63,12 @@
5586 #ifdef CONFIG_64BIT_PHYS_ADDR
5587 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
5588 #else
5589 +#ifdef CONFIG_AR7_PAGING
5590 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5591 +#else
5592 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
5593 #endif
5594 +#endif
5595
5596 #define IO_SPACE_LIMIT 0xffff
5597
5598 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
5599 --- linux.old/include/asm-mips/irq.h 2005-07-07 05:38:31.424479552 +0200
5600 +++ linux.dev/include/asm-mips/irq.h 2005-07-07 04:39:14.435224000 +0200
5601 @@ -14,7 +14,12 @@
5602 #include <linux/config.h>
5603 #include <linux/linkage.h>
5604
5605 +#ifdef CONFIG_AR7
5606 +#include <asm/ar7/avalanche_intc.h>
5607 +#define NR_IRQS AVALANCHE_INT_END + 1
5608 +#else
5609 #define NR_IRQS 128 /* Largest number of ints of all machines. */
5610 +#endif
5611
5612 #ifdef CONFIG_I8259
5613 static inline int irq_cannonicalize(int irq)
5614 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
5615 --- linux.old/include/asm-mips/page.h 2005-07-07 05:38:31.426479248 +0200
5616 +++ linux.dev/include/asm-mips/page.h 2005-07-07 04:39:14.435224000 +0200
5617 @@ -129,7 +129,11 @@
5618
5619 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
5620 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
5621 +#ifdef CONFIG_AR7_PAGING
5622 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
5623 +#else
5624 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5625 +#endif
5626 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
5627
5628 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
5629 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
5630 --- linux.old/include/asm-mips/pgtable-32.h 2005-07-07 05:38:31.434478032 +0200
5631 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-07 04:39:14.435224000 +0200
5632 @@ -108,7 +108,18 @@
5633 * and a page entry and page directory to the page they refer to.
5634 */
5635
5636 -#ifdef CONFIG_CPU_VR41XX
5637 +#if defined(CONFIG_AR7_PAGING)
5638 +#define mk_pte(page, pgprot) \
5639 +({ \
5640 + pte_t __pte; \
5641 + \
5642 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
5643 + CONFIG_AR7_MEMORY) | \
5644 + pgprot_val(pgprot); \
5645 + \
5646 + __pte; \
5647 +})
5648 +#elif defined(CONFIG_CPU_VR41XX)
5649 #define mk_pte(page, pgprot) \
5650 ({ \
5651 pte_t __pte; \
5652 @@ -130,6 +141,7 @@
5653 })
5654 #endif
5655
5656 +
5657 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5658 {
5659 #ifdef CONFIG_CPU_VR41XX
5660 @@ -175,7 +187,10 @@
5661 set_pte(ptep, __pte(0));
5662 }
5663
5664 -#ifdef CONFIG_CPU_VR41XX
5665 +#if defined(CONFIG_AR7_PAGING)
5666 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5667 +#define pte_page(x) phys_to_page(pte_val(x))
5668 +#elif defined(CONFIG_CPU_VR41XX)
5669 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5670 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5671 #else
5672 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
5673 --- linux.old/include/asm-mips/serial.h 2005-07-07 05:38:31.470472560 +0200
5674 +++ linux.dev/include/asm-mips/serial.h 2005-07-07 04:39:14.436223000 +0200
5675 @@ -65,6 +65,15 @@
5676
5677 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5678
5679 +#ifdef CONFIG_AR7
5680 +#include <asm/ar7/ar7.h>
5681 +#define AR7_SERIAL_PORT_DEFNS \
5682 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5683 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5684 +#else
5685 +#define AR7_SERIAL_PORT_DEFNS
5686 +#endif
5687 +
5688 #ifdef CONFIG_MIPS_JAZZ
5689 #define _JAZZ_SERIAL_INIT(int, base) \
5690 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
5691 @@ -468,6 +477,7 @@
5692 #endif
5693
5694 #define SERIAL_PORT_DFNS \
5695 + AR7_SERIAL_PORT_DEFNS \
5696 ATLAS_SERIAL_PORT_DEFNS \
5697 AU1000_SERIAL_PORT_DEFNS \
5698 COBALT_SERIAL_PORT_DEFNS \
5699 diff -urN linux.old/Makefile linux.dev/Makefile
5700 --- linux.old/Makefile 2005-07-07 05:38:31.320495360 +0200
5701 +++ linux.dev/Makefile 2005-07-07 04:39:14.501214000 +0200
5702 @@ -91,7 +91,7 @@
5703
5704 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
5705
5706 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
5707 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
5708 -fno-strict-aliasing -fno-common
5709 ifndef CONFIG_FRAME_POINTER
5710 CFLAGS += -fomit-frame-pointer
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