target/linux/generic-2.6/files/crypto/ocf/hifn/hifn7751reg.h

   1 /* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */
   2 /*      $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $  */
   3
   4 /*-
   5  * Invertex AEON / Hifn 7751 driver
   6  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   7  * Copyright (c) 1999 Theo de Raadt
   8  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
   9  *                      http://www.netsec.net
  10  *
  11  * Please send any comments, feedback, bug-fixes, or feature requests to
  12  * software@invertex.com.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions
  16  * are met:
  17  *
  18  * 1. Redistributions of source code must retain the above copyright
  19  *    notice, this list of conditions and the following disclaimer.
  20  * 2. Redistributions in binary form must reproduce the above copyright
  21  *    notice, this list of conditions and the following disclaimer in the
  22  *    documentation and/or other materials provided with the distribution.
  23  * 3. The name of the author may not be used to endorse or promote products
  24  *    derived from this software without specific prior written permission.
  25  *
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  28  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  29  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Effort sponsored in part by the Defense Advanced Research Projects
  39  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  40  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  41  *
  42  */
  43 #ifndef __HIFN_H__
  44 #define __HIFN_H__
  45
  46 /*
  47  * Some PCI configuration space offset defines.  The names were made
  48  * identical to the names used by the Linux kernel.
  49  */
  50 #define HIFN_BAR0               PCIR_BAR(0)     /* PUC register map */
  51 #define HIFN_BAR1               PCIR_BAR(1)     /* DMA register map */
  52 #define HIFN_TRDY_TIMEOUT       0x40
  53 #define HIFN_RETRY_TIMEOUT      0x41
  54
  55 /*
  56  * PCI vendor and device identifiers
  57  * (the names are preserved from their OpenBSD source).
  58  */
  59 #define PCI_VENDOR_HIFN         0x13a3          /* Hifn */
  60 #define PCI_PRODUCT_HIFN_7751   0x0005          /* 7751 */
  61 #define PCI_PRODUCT_HIFN_6500   0x0006          /* 6500 */
  62 #define PCI_PRODUCT_HIFN_7811   0x0007          /* 7811 */
  63 #define PCI_PRODUCT_HIFN_7855   0x001f          /* 7855 */
  64 #define PCI_PRODUCT_HIFN_7951   0x0012          /* 7951 */
  65 #define PCI_PRODUCT_HIFN_7955   0x0020          /* 7954/7955 */
  66 #define PCI_PRODUCT_HIFN_7956   0x001d          /* 7956 */
  67
  68 #define PCI_VENDOR_INVERTEX     0x14e1          /* Invertex */
  69 #define PCI_PRODUCT_INVERTEX_AEON 0x0005        /* AEON */
  70
  71 #define PCI_VENDOR_NETSEC       0x1660          /* NetSec */
  72 #define PCI_PRODUCT_NETSEC_7751 0x7751          /* 7751 */
  73
  74 /*
  75  * The values below should multiple of 4 -- and be large enough to handle
  76  * any command the driver implements.
  77  *
  78  * MAX_COMMAND = base command + mac command + encrypt command +
  79  *                      mac-key + rc4-key
  80  * MAX_RESULT  = base result + mac result + mac + encrypt result
  81  *
  82  *
  83  */
  84 #define HIFN_MAX_COMMAND        (8 + 8 + 8 + 64 + 260)
  85 #define HIFN_MAX_RESULT         (8 + 4 + 20 + 4)
  86
  87 /*
  88  * hifn_desc_t
  89  *
  90  * Holds an individual descriptor for any of the rings.
  91  */
  92 typedef struct hifn_desc {
  93         volatile u_int32_t l;           /* length and status bits */
  94         volatile u_int32_t p;
  95 } hifn_desc_t;
  96
  97 /*
  98  * Masks for the "length" field of struct hifn_desc.
  99  */
 100 #define HIFN_D_LENGTH           0x0000ffff      /* length bit mask */
 101 #define HIFN_D_MASKDONEIRQ      0x02000000      /* mask the done interrupt */
 102 #define HIFN_D_DESTOVER         0x04000000      /* destination overflow */
 103 #define HIFN_D_OVER             0x08000000      /* overflow */
 104 #define HIFN_D_LAST             0x20000000      /* last descriptor in chain */
 105 #define HIFN_D_JUMP             0x40000000      /* jump descriptor */
 106 #define HIFN_D_VALID            0x80000000      /* valid bit */
 107
 108
 109 /*
 110  * Processing Unit Registers (offset from BASEREG0)
 111  */
 112 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
 113 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
 114 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
 115 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
 116 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
 117 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
 118 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
 119 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
 120 #define HIFN_0_PUCTRL2          0x28    /* Processing Unit Control (2nd map) */
 121 #define HIFN_0_MUTE1            0x80
 122 #define HIFN_0_MUTE2            0x90
 123 #define HIFN_0_SPACESIZE        0x100   /* Register space size */
 124
 125 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
 126 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
 127 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
 128 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
 129 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
 130 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
 131
 132 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
 133 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
 134 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
 135 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 136 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 137 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
 138 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
 139 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 140 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 141 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 142 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 143
 144 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 145 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 146 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 147 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 148 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 149 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 150 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 151 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 152 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 153 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 154 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 155 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 156 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 157 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 158 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 159 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 160 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 161 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 162 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 163 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 164 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 165 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 166 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 167 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 168
 169 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 170 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 171 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 172 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 173 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 174 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 175 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 176 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 177 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 178 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 179 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 180
 181 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 182 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 183 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 184 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 185 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 186 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 187 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 188 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 189 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 190 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 191 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 192 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 193 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 194 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 195 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 196 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 197 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 198 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 199
 200 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 201 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 202 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 203
 204 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 205 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as this value */
 206
 207 /*
 208  * DMA Interface Registers (offset from BASEREG1)
 209  */
 210 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 211 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 212 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 213 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 214 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 215 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 216 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 217 #define HIFN_1_PLL              0x4c    /* 7955/7956: PLL config */
 218 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 219 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 220 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 221 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 222 #define HIFN_1_DMA_CNFG2        0x6c    /* 7955/7956: dma config #2 */
 223 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 224 #define HIFN_1_REVID            0x98    /* Revision ID */
 225
 226 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 227 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 228 #define HIFN_1_PUB_OPLEN        0x304   /* 7951-compat Public Operand Length */
 229 #define HIFN_1_PUB_OP           0x308   /* 7951-compat Public Operand */
 230 #define HIFN_1_PUB_STATUS       0x30c   /* 7951-compat Public Status */
 231 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 232 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 233 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 234 #define HIFN_1_PUB_MODE         0x320   /* PK mode */
 235 #define HIFN_1_PUB_FIFO_OPLEN   0x380   /* first element of oplen fifo */
 236 #define HIFN_1_PUB_FIFO_OP      0x384   /* first element of op fifo */
 237 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 238 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 239
 240 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 241 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 242 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 243 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 244 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 245 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 246 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 247 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 248 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 249 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 250 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 251 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 252 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 253 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 254 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 255 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 256 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 257 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 258 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 259 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 260 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 261 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 262 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 263 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 264 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 265 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 266 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 267 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 268 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 269 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 270 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 271 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 272 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 273 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 274 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 275 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 276 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 277 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 278 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 279
 280 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 281 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 282 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 283 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 284 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 285 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 286 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 287 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 288 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 289 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 290 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 291 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 292 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 293 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 294 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 295 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 296 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 297 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 298 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 299 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 300 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 301 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 302 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 303
 304 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 305 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 306 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 307 #define HIFN_DMACNFG_UNLOCK     0x00000800
 308 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 309 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 310 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 311 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 312 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 313
 314 /* DMA Configuration Register (HIFN_1_DMA_CNFG2) */
 315 #define HIFN_DMACNFG2_PKSWAP32  (1 << 19)       /* swap the OPLEN/OP reg */
 316 #define HIFN_DMACNFG2_PKSWAP8   (1 << 18)       /* swap the bits of OPLEN/OP */
 317 #define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17)       /* swap the bytes of BAR0 */
 318 #define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16)        /* swap the bits  of BAR0 */
 319 #define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12
 320 #define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8
 321 #define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4
 322 #define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT  0
 323
 324 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
 325 #define HIFN_7811_RNGENA_ENA    0x00000001      /* enable RNG */
 326
 327 /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
 328 #define HIFN_7811_RNGCFG_PRE1   0x00000f00      /* first prescalar */
 329 #define HIFN_7811_RNGCFG_OPRE   0x00000080      /* output prescalar */
 330 #define HIFN_7811_RNGCFG_DEFL   0x00000f80      /* 2 words/ 1/100 sec */
 331
 332 /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
 333 #define HIFN_7811_RNGSTS_RDY    0x00004000      /* two numbers in FIFO */
 334 #define HIFN_7811_RNGSTS_UFL    0x00001000      /* rng underflow */
 335
 336 /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
 337 #define HIFN_MIPSRST_BAR2SIZE   0xffff0000      /* sdram size */
 338 #define HIFN_MIPSRST_GPRAMINIT  0x00008000      /* gpram can be accessed */
 339 #define HIFN_MIPSRST_CRAMINIT   0x00004000      /* ctxram can be accessed */
 340 #define HIFN_MIPSRST_LED2       0x00000400      /* external LED2 */
 341 #define HIFN_MIPSRST_LED1       0x00000200      /* external LED1 */
 342 #define HIFN_MIPSRST_LED0       0x00000100      /* external LED0 */
 343 #define HIFN_MIPSRST_MIPSDIS    0x00000004      /* disable MIPS */
 344 #define HIFN_MIPSRST_MIPSRST    0x00000002      /* warm reset MIPS */
 345 #define HIFN_MIPSRST_MIPSCOLD   0x00000001      /* cold reset MIPS */
 346
 347 /* Public key reset register (HIFN_1_PUB_RESET) */
 348 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 349
 350 /* Public operation register (HIFN_1_PUB_OP) */
 351 #define HIFN_PUBOP_AOFFSET      0x0000003e      /* A offset */
 352 #define HIFN_PUBOP_BOFFSET      0x00000fc0      /* B offset */
 353 #define HIFN_PUBOP_MOFFSET      0x0003f000      /* M offset */
 354 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 355 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 356 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 357 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 358 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 359 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 360 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 361 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 362 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 363 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 364 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 365 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 366 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular Red */
 367 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular Exp */
 368
 369 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 370 #define HIFN_PUBOPLEN_MODLEN    0x0000007f
 371 #define HIFN_PUBOPLEN_EXPLEN    0x0003ff80
 372 #define HIFN_PUBOPLEN_REDLEN    0x003c0000
 373
 374 /* Public status register (HIFN_1_PUB_STATUS) */
 375 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 376 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 377 #define HIFN_PUBSTS_FIFO_EMPTY  0x00000100      /* fifo empty */
 378 #define HIFN_PUBSTS_FIFO_FULL   0x00000200      /* fifo full */
 379 #define HIFN_PUBSTS_FIFO_OVFL   0x00000400      /* fifo overflow */
 380 #define HIFN_PUBSTS_FIFO_WRITE  0x000f0000      /* fifo write */
 381 #define HIFN_PUBSTS_FIFO_READ   0x0f000000      /* fifo read */
 382
 383 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 384 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 385
 386 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 387 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 388
 389 /*
 390  * Register offsets in register set 1
 391  */
 392
 393 #define HIFN_UNLOCK_SECRET1     0xf4
 394 #define HIFN_UNLOCK_SECRET2     0xfc
 395
 396 /*
 397  * PLL config register
 398  *
 399  * This register is present only on 7954/7955/7956 parts. It must be
 400  * programmed according to the bus interface method used by the h/w.
 401  * Note that the parts require a stable clock.  Since the PCI clock
 402  * may vary the reference clock must usually be used.  To avoid
 403  * overclocking the core logic, setup must be done carefully, refer
 404  * to the driver for details.  The exact multiplier required varies
 405  * by part and system configuration; refer to the Hifn documentation.
 406  */
 407 #define HIFN_PLL_REF_SEL        0x00000001      /* REF/HBI clk selection */
 408 #define HIFN_PLL_BP             0x00000002      /* bypass (used during setup) */
 409 /* bit 2 reserved */
 410 #define HIFN_PLL_PK_CLK_SEL     0x00000008      /* public key clk select */
 411 #define HIFN_PLL_PE_CLK_SEL     0x00000010      /* packet engine clk select */
 412 /* bits 5-9 reserved */
 413 #define HIFN_PLL_MBSET          0x00000400      /* must be set to 1 */
 414 #define HIFN_PLL_ND             0x00003800      /* Fpll_ref multiplier select */
 415 #define HIFN_PLL_ND_SHIFT       11
 416 #define HIFN_PLL_ND_2           0x00000000      /* 2x */
 417 #define HIFN_PLL_ND_4           0x00000800      /* 4x */
 418 #define HIFN_PLL_ND_6           0x00001000      /* 6x */
 419 #define HIFN_PLL_ND_8           0x00001800      /* 8x */
 420 #define HIFN_PLL_ND_10          0x00002000      /* 10x */
 421 #define HIFN_PLL_ND_12          0x00002800      /* 12x */
 422 /* bits 14-15 reserved */
 423 #define HIFN_PLL_IS             0x00010000      /* charge pump current select */
 424 /* bits 17-31 reserved */
 425
 426 /*
 427  * Board configuration specifies only these bits.
 428  */
 429 #define HIFN_PLL_CONFIG         (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL)
 430
 431 /*
 432  * Public Key Engine Mode Register
 433  */
 434 #define HIFN_PKMODE_HOSTINVERT  (1 << 0)        /* HOST INVERT */
 435 #define HIFN_PKMODE_ENHANCED    (1 << 1)        /* Enable enhanced mode */
 436
 437
 438 /*********************************************************************
 439  * Structs for board commands
 440  *
 441  *********************************************************************/
 442
 443 /*
 444  * Structure to help build up the command data structure.
 445  */
 446 typedef struct hifn_base_command {
 447         volatile u_int16_t masks;
 448         volatile u_int16_t session_num;
 449         volatile u_int16_t total_source_count;
 450         volatile u_int16_t total_dest_count;
 451 } hifn_base_command_t;
 452
 453 #define HIFN_BASE_CMD_MAC               0x0400
 454 #define HIFN_BASE_CMD_CRYPT             0x0800
 455 #define HIFN_BASE_CMD_DECODE            0x2000
 456 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 457 #define HIFN_BASE_CMD_SRCLEN_S          14
 458 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 459 #define HIFN_BASE_CMD_DSTLEN_S          12
 460 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 461 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 462
 463 /*
 464  * Structure to help build up the command data structure.
 465  */
 466 typedef struct hifn_crypt_command {
 467         volatile u_int16_t masks;
 468         volatile u_int16_t header_skip;
 469         volatile u_int16_t source_count;
 470         volatile u_int16_t reserved;
 471 } hifn_crypt_command_t;
 472
 473 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 474 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 475 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 476 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 477 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 478 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 479 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 480 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 481 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 482 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 483 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 484 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 485 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 486
 487 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 488 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 489
 490 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 491 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*   128 bit */
 492 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*   192 bit */
 493 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*   256 bit */
 494
 495 /*
 496  * Structure to help build up the command data structure.
 497  */
 498 typedef struct hifn_mac_command {
 499         volatile u_int16_t masks;
 500         volatile u_int16_t header_skip;
 501         volatile u_int16_t source_count;
 502         volatile u_int16_t reserved;
 503 } hifn_mac_command_t;
 504
 505 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 506 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 507 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 508 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 509 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 510 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 511 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 512 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 513 #define HIFN_MAC_CMD_TRUNC              0x0010
 514 #define HIFN_MAC_CMD_RESULT             0x0020
 515 #define HIFN_MAC_CMD_APPEND             0x0040
 516 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 517 #define HIFN_MAC_CMD_SRCLEN_S           14
 518
 519 /*
 520  * MAC POS IPsec initiates authentication after encryption on encodes
 521  * and before decryption on decodes.
 522  */
 523 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 524 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 525
 526 /*
 527  * The poll frequency and poll scalar defines are unshifted values used
 528  * to set fields in the DMA Configuration Register.
 529  */
 530 #ifndef HIFN_POLL_FREQUENCY
 531 #define HIFN_POLL_FREQUENCY     0x1
 532 #endif
 533
 534 #ifndef HIFN_POLL_SCALAR
 535 #define HIFN_POLL_SCALAR        0x0
 536 #endif
 537
 538 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 539 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 540 #endif /* __HIFN_H__ */