target/linux/lantiq/patches/901-board_falcon.patch

   1 --- /dev/null
   2 +++ b/arch/mips/lantiq/falcon/Kconfig
   3 @@ -0,0 +1,11 @@
   4 +if SOC_LANTIQ_FALCON
   5 +
   6 +menu "Mips Machine"
   7 +
   8 +config LANTIQ_MACH_EASY98000
   9 +       bool "Easy98000"
  10 +       default y
  11 +
  12 +endmenu
  13 +
  14 +endif
  15 --- /dev/null
  16 +++ b/arch/mips/lantiq/falcon/Makefile
  17 @@ -0,0 +1,3 @@
  18 +obj-y := clk-falcon.o devices.o gpio.o prom.o sysctrl.o reset.o
  19 +obj-y += softdog_vpe.o
  20 +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
  21 --- /dev/null
  22 +++ b/arch/mips/lantiq/falcon/clk-falcon.c
  23 @@ -0,0 +1,46 @@
  24 +/*
  25 + * This program is free software; you can redistribute it and/or modify
  26 + * it under the terms of the GNU General Public License as published by
  27 + * the Free Software Foundation; either version 2 of the License, or
  28 + * (at your option) any later version.
  29 + *
  30 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  31 + */
  32 +
  33 +#include <linux/io.h>
  34 +#include <linux/module.h>
  35 +#include <linux/init.h>
  36 +
  37 +#include <asm/time.h>
  38 +#include <asm/irq.h>
  39 +#include <asm/div64.h>
  40 +
  41 +#include <falcon.h>
  42 +
  43 +#include <falcon/sys1_reg.h>
  44 +
  45 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
  46 +
  47 +unsigned int
  48 +lq_get_io_region_clock(void)
  49 +{
  50 +       return 200000000; /* 200 MHz */
  51 +}
  52 +EXPORT_SYMBOL(lq_get_io_region_clock);
  53 +
  54 +unsigned int
  55 +lq_get_cpu_hz(void)
  56 +{
  57 +       if ((lq_r32(&pSYS1->cpu0cc) & CPU0CC_CPUDIV) == CPU0CC_CPUDIV_SELFHALF)
  58 +               return 200000000; /* 200 MHz */
  59 +       else
  60 +               return 400000000; /* 400 MHz */
  61 +}
  62 +EXPORT_SYMBOL(lq_get_cpu_hz);
  63 +
  64 +unsigned int
  65 +lq_get_fpi_hz(void)
  66 +{
  67 +       return 100000000;
  68 +}
  69 +EXPORT_SYMBOL(lq_get_fpi_hz);
  70 --- /dev/null
  71 +++ b/arch/mips/lantiq/falcon/devices.c
  72 @@ -0,0 +1,180 @@
  73 +#include <linux/init.h>
  74 +#include <linux/module.h>
  75 +#include <linux/types.h>
  76 +#include <linux/string.h>
  77 +#include <linux/mtd/physmap.h>
  78 +#include <linux/kernel.h>
  79 +#include <linux/reboot.h>
  80 +#include <linux/platform_device.h>
  81 +#include <linux/leds.h>
  82 +#include <linux/etherdevice.h>
  83 +#include <linux/reboot.h>
  84 +#include <linux/time.h>
  85 +#include <linux/io.h>
  86 +#include <linux/gpio.h>
  87 +#include <linux/leds.h>
  88 +#include <linux/spi/spi.h>
  89 +
  90 +#include <asm/bootinfo.h>
  91 +#include <asm/irq.h>
  92 +
  93 +#include <lantiq.h>
  94 +
  95 +#include <falcon/falcon_irq.h>
  96 +#include <falcon/gpon_reg_base.h>
  97 +#include <falcon/sys1_reg.h>
  98 +#include <falcon/sys_eth_reg.h>
  99 +
 100 +#include <falcon/sysctrl.h>
 101 +
 102 +#include "devices.h"
 103 +
 104 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 105 +EXPORT_SYMBOL(lq_ethaddr);
 106 +
 107 +static int __init
 108 +falcon_set_ethaddr(char *str)
 109 +{
 110 +       sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 111 +               &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
 112 +               &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
 113 +       return 0;
 114 +}
 115 +__setup("ethaddr=", falcon_set_ethaddr);
 116 +
 117 +/* asc ports */
 118 +static struct resource falcon_asc0_resources[] =
 119 +{
 120 +       MEM_RES("asc0",GPON_ASC0_BASE,GPON_ASC0_END),
 121 +       IRQ_RES("tx",INT_NUM_IM3_IRL0),
 122 +       IRQ_RES("rx",INT_NUM_IM3_IRL0+1),
 123 +       IRQ_RES("err",INT_NUM_IM3_IRL0+2),
 124 +};
 125 +
 126 +static struct resource falcon_asc1_resources[] =
 127 +{
 128 +       MEM_RES("asc1",GPON_ASC1_BASE,GPON_ASC1_END),
 129 +       IRQ_RES("tx",INT_NUM_IM3_IRL0+8),
 130 +       IRQ_RES("rx",INT_NUM_IM3_IRL0+9),
 131 +       IRQ_RES("err",INT_NUM_IM3_IRL0+10),
 132 +};
 133 +
 134 +void __init falcon_register_asc(int port)
 135 +{
 136 +       switch (port) {
 137 +       case 0:
 138 +               platform_device_register_simple("lq_asc", 0,
 139 +                       falcon_asc0_resources, ARRAY_SIZE(falcon_asc0_resources));
 140 +               break;
 141 +       case 1:
 142 +               platform_device_register_simple("lq_asc", 1,
 143 +                       falcon_asc1_resources, ARRAY_SIZE(falcon_asc1_resources));
 144 +               break;
 145 +       default:
 146 +               break;
 147 +       }
 148 +}
 149 +
 150 +/* nor flash */
 151 +static struct resource lq_nor_resource =
 152 +       MEM_RES("nor",LQ_FLASH_START,LQ_FLASH_START + LQ_FLASH_MAX - 1);
 153 +
 154 +static struct platform_device lq_nor = {
 155 +       .name                   = "lq_nor",
 156 +       .resource               = &lq_nor_resource,
 157 +       .num_resources  = 1,
 158 +};
 159 +
 160 +void __init falcon_register_nor(struct physmap_flash_data *data)
 161 +{
 162 +       lq_nor.dev.platform_data = data;
 163 +       platform_device_register(&lq_nor);
 164 +}
 165 +
 166 +/* spi flash */
 167 +static struct resource lq_spi_resources[] = {
 168 +       MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
 169 +       MEM_RES("sys1", GPON_SYS1_BASE, GPON_SYS1_END)
 170 +};
 171 +
 172 +static struct platform_device lq_spi = {
 173 +       .name                   = "falcon_spi",
 174 +       .resource               = lq_spi_resources,
 175 +       .num_resources          = ARRAY_SIZE(lq_spi_resources)
 176 +};
 177 +
 178 +void __init falcon_register_spi_flash(struct spi_board_info *data)
 179 +{
 180 +       spi_register_board_info(data, 1);
 181 +       platform_device_register(&lq_spi);
 182 +}
 183 +
 184 +/* watchdog */
 185 +static struct resource falcon_wdt_resource =
 186 +       MEM_RES("watchdog",GPON_WDT_BASE,GPON_WDT_END);
 187 +
 188 +void __init falcon_register_wdt(void)
 189 +{
 190 +       platform_device_register_simple("lq_wdt", 0, &falcon_wdt_resource, 1);
 191 +}
 192 +
 193 +/* gpio */
 194 +#define DECLARE_GPIO_RES(port) \
 195 +static struct resource falcon_gpio ## port ## _resources[] = { \
 196 +       MEM_RES("gpio"#port,GPON_GPIO ## port ## _BASE,GPON_GPIO ## port ## _END), \
 197 +       MEM_RES("padctrl"#port,GPON_PADCTRL ## port ## _BASE,GPON_PADCTRL ## port ## _END), \
 198 +       IRQ_RES("gpio_mux"#port,FALCON_IRQ_GPIO_P ## port ) \
 199 +}
 200 +DECLARE_GPIO_RES(0);
 201 +DECLARE_GPIO_RES(1);
 202 +DECLARE_GPIO_RES(2);
 203 +#ifdef REGISTER_ALL_GPIO_PORTS
 204 +#if NR_IRQS < 328
 205 +#error NR_IRQS to low for all gpio irqs
 206 +#endif
 207 +DECLARE_GPIO_RES(3);
 208 +DECLARE_GPIO_RES(4);
 209 +#endif
 210 +
 211 +void __init falcon_register_gpio(void)
 212 +{
 213 +       platform_device_register_simple("falcon_gpio", 0,
 214 +               falcon_gpio0_resources, ARRAY_SIZE(falcon_gpio0_resources));
 215 +       platform_device_register_simple("falcon_gpio", 1,
 216 +               falcon_gpio1_resources, ARRAY_SIZE(falcon_gpio1_resources));
 217 +       platform_device_register_simple("falcon_gpio", 2,
 218 +               falcon_gpio2_resources, ARRAY_SIZE(falcon_gpio2_resources));
 219 +       sys1_hw_activate(ACTS_PADCTRL1 | ACTS_P1);
 220 +       sys_eth_hw_activate(SYS_ETH_ACTS_PADCTRL0 | SYS_ETH_ACTS_PADCTRL2 |
 221 +               SYS_ETH_ACTS_P0 | SYS_ETH_ACTS_P2);
 222 +
 223 +#ifdef REGISTER_ALL_GPIO_PORTS
 224 +       /* optional gpio ports: not registered,
 225 +          as the pins are EBU specific and always used by linux */
 226 +       platform_device_register_simple("falcon_gpio", 3,
 227 +               falcon_gpio3_resources, ARRAY_SIZE(falcon_gpio3_resources));
 228 +       platform_device_register_simple("falcon_gpio", 4,
 229 +               falcon_gpio4_resources, ARRAY_SIZE(falcon_gpio4_resources));
 230 +       sys1_hw_activate(ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
 231 +#endif
 232 +}
 233 +
 234 +static struct resource falcon_i2c_resources[] = {
 235 +       MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
 236 +       IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
 237 +       IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
 238 +       IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
 239 +       IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
 240 +};
 241 +
 242 +void __init falcon_register_i2c(void)
 243 +{
 244 +       platform_device_register_simple("i2c-falcon", 0,
 245 +               falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
 246 +       sys1_hw_activate(ACTS_I2C_ACT);
 247 +}
 248 +
 249 +void __init falcon_register_crypto(void)
 250 +{
 251 +       platform_device_register_simple("lq_falcon_deu", 0, NULL, 0);
 252 +}
 253 --- /dev/null
 254 +++ b/arch/mips/lantiq/falcon/devices.h
 255 @@ -0,0 +1,21 @@
 256 +#ifndef _FALCON_DEVICES_H__
 257 +#define _FALCON_DEVICES_H__
 258 +
 259 +#include <linux/mtd/physmap.h>
 260 +#include <linux/spi/spi.h>
 261 +#include <linux/spi/flash.h>
 262 +
 263 +extern void __init falcon_register_asc(int port);
 264 +extern void __init falcon_register_i2c(void);
 265 +extern void __init falcon_register_spi_flash(struct spi_board_info *data);
 266 +extern void __init falcon_register_gpio(void);
 267 +extern void __init falcon_register_nor(struct physmap_flash_data *data);
 268 +extern void __init falcon_register_wdt(void);
 269 +extern void __init falcon_register_crypto(void);
 270 +
 271 +#define IRQ_RES(resname,irq) {.name=resname,.start=(irq),.flags=IORESOURCE_IRQ}
 272 +#define MEM_RES(resname,adr_start,adr_end) \
 273 +       { .name=resname, .flags=IORESOURCE_MEM, \
 274 +         .start=((adr_start)&~KSEG1),.end=((adr_end)&~KSEG1) }
 275 +
 276 +#endif
 277 --- /dev/null
 278 +++ b/arch/mips/lantiq/falcon/prom.c
 279 @@ -0,0 +1,44 @@
 280 +/*
 281 + * This program is free software; you can redistribute it and/or modify
 282 + * it under the terms of the GNU General Public License as published by
 283 + * the Free Software Foundation; either version 2 of the License, or
 284 + * (at your option) any later version.
 285 + *
 286 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 287 + */
 288 +
 289 +#include <linux/module.h>
 290 +#include <linux/clk.h>
 291 +#include <asm/bootinfo.h>
 292 +#include <asm/time.h>
 293 +
 294 +#include <falcon.h>
 295 +
 296 +#include <falcon/gpon_reg_base.h>
 297 +#include <falcon/status_reg.h>
 298 +#include <falcon/sys1_reg.h>
 299 +
 300 +#include "../prom.h"
 301 +
 302 +static struct gpon_reg_status * const pSTATUS = (struct gpon_reg_status *)GPON_STATUS_BASE;
 303 +
 304 +#define SOC_FALCON             "Falcon"
 305 +
 306 +void __init
 307 +lq_soc_detect(struct lq_soc_info *i)
 308 +{
 309 +       i->partnum = (lq_r32(&pSTATUS->chipid) & STATUS_CHIPID_PARTNR_MASK) >> STATUS_CHIPID_PARTNR_OFFSET;
 310 +       i->rev = (lq_r32(&pSTATUS->chipid) & STATUS_CHIPID_VERSION_MASK) >> STATUS_CHIPID_VERSION_OFFSET;
 311 +       switch (i->partnum)
 312 +       {
 313 +       case SOC_ID_FALCON:
 314 +               i->name = SOC_FALCON;
 315 +               i->type = SOC_TYPE_FALCON;
 316 +               break;
 317 +
 318 +       default:
 319 +               printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum);
 320 +               while(1) {      };
 321 +               break;
 322 +       }
 323 +}
 324 --- /dev/null
 325 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 326 @@ -0,0 +1,381 @@
 327 +/*
 328 + * This program is free software; you can redistribute it and/or
 329 + * modify it under the terms of the GNU General Public License as
 330 + * published by the Free Software Foundation; either version 2 of
 331 + * the License, or (at your option) any later version.
 332 + *
 333 + * This program is distributed in the hope that it will be useful,
 334 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 335 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 336 + * GNU General Public License for more details.
 337 + *
 338 + * You should have received a copy of the GNU General Public License
 339 + * along with this program; if not, write to the Free Software
 340 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 341 + * MA 02111-1307 USA
 342 + *
 343 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 344 + */
 345 +
 346 +#include <linux/cpu.h>
 347 +#include <linux/init.h>
 348 +#include <linux/kernel.h>
 349 +#include <linux/pm.h>
 350 +#include <linux/io.h>
 351 +#include <linux/ioport.h>
 352 +#include <linux/clk.h>
 353 +#include <asm/reboot.h>
 354 +
 355 +#include <falcon/gpon_reg_base.h>
 356 +#include <falcon/status_reg.h>
 357 +#include <falcon/sys1_reg.h>
 358 +#include <falcon/sys_eth_reg.h>
 359 +#include <falcon/sys_gpe_reg.h>
 360 +
 361 +#include <falcon/sysctrl.h>
 362 +
 363 +/* mapping to linux hw-accessor routines */
 364 +#define reg_r32(reg)                   __raw_readl(reg)
 365 +#define reg_w32(val, reg)              __raw_writel(val, reg)
 366 +#define reg_w32_mask(clear, set, reg)  reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
 367 +
 368 +static struct gpon_reg_sys1 * const sys1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
 369 +static struct gpon_reg_sys_eth * const sys_eth = (struct gpon_reg_sys_eth *)GPON_SYS_ETH_BASE;
 370 +static struct gpon_reg_sys_gpe * const sys_gpe = (struct gpon_reg_sys_gpe *)GPON_SYS_GPE_BASE;
 371 +static struct gpon_reg_status * const status = (struct gpon_reg_status *)GPON_STATUS_BASE;
 372 +
 373 +/**
 374 + * Activate the selected module(s)
 375 + * Enables the clock of the module and activates the module itself.
 376 + *
 377 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.ACT
 378 + * \return void
 379 + */
 380 +void sys1_hw_activate(u32 mask)
 381 +{
 382 +       sys1_w32(mask, clken);
 383 +       sys1_w32(mask, act);
 384 +
 385 +       while ( (sys1_r32(acts) & mask) != mask) {
 386 +               /*NOP;*/
 387 +       };
 388 +}
 389 +EXPORT_SYMBOL(sys1_hw_activate);
 390 +
 391 +/**
 392 + * Deactivate the selected module(s)
 393 + * Disables the clock of the module and deactivates the module itself.
 394 + *
 395 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.DEACT
 396 + * \return void
 397 + */
 398 +void sys1_hw_deactivate(u32 mask)
 399 +{
 400 +       sys1_w32(mask, clkclr);
 401 +       sys1_w32(mask, deact);
 402 +
 403 +       while ( (sys1_r32(acts) & mask) != 0) {
 404 +               /*NOP;*/
 405 +       };
 406 +}
 407 +EXPORT_SYMBOL(sys1_hw_deactivate);
 408 +
 409 +/**
 410 + * Clock enable for the selected module(s)
 411 + * Enables the clock of the module.
 412 + *
 413 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKEN
 414 + * \return void
 415 + */
 416 +void sys1_hw_clk_enable(u32 mask)
 417 +{
 418 +       sys1_w32(mask, clken);
 419 +
 420 +       while ( (sys1_r32(clks) & mask) != mask) {
 421 +               /*NOP;*/
 422 +       };
 423 +}
 424 +EXPORT_SYMBOL(sys1_hw_clk_enable);
 425 +
 426 +/**
 427 + * Clock disable for the selected module(s)
 428 + * disables the clock of the module.
 429 + *
 430 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKCLR
 431 + * \return void
 432 + */
 433 +void sys1_hw_clk_disable(u32 mask)
 434 +{
 435 +       sys1_w32(mask, clkclr);
 436 +
 437 +       while ( (sys1_r32(clks) & mask) != 0) {
 438 +               /*NOP;*/
 439 +       };
 440 +}
 441 +EXPORT_SYMBOL(sys1_hw_clk_disable);
 442 +
 443 +/**
 444 + * Reboots the selected module(s)
 445 + * Triggers the reboot of the module.
 446 + *
 447 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.RBT
 448 + * \return void
 449 + */
 450 +void sys1_hw_activate_or_reboot(u32 mask)
 451 +{
 452 +       u32 acts = sys1_r32(acts);
 453 +       /* is not already active? */
 454 +       if ((~acts & mask) != 0)
 455 +               sys1_hw_activate(~acts & mask);
 456 +       sys1_w32(acts & mask, rbt);
 457 +       while ( (sys1_r32(acts) & mask) != mask) {
 458 +               /*NOP;*/
 459 +       };
 460 +}
 461 +EXPORT_SYMBOL(sys1_hw_activate_or_reboot);
 462 +
 463 +/**
 464 + * Activate the selected module(s)
 465 + * Enables the clock of the module and activates the module itself.
 466 + *
 467 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.ACT
 468 + * \return void
 469 + */
 470 +void sys_eth_hw_activate(u32 mask)
 471 +{
 472 +       sys_eth_w32(mask, clken);
 473 +       sys_eth_w32(mask, act);
 474 +
 475 +       while ( (sys_eth_r32(acts) & mask) != mask) {
 476 +               /*NOP;*/
 477 +       };
 478 +}
 479 +EXPORT_SYMBOL(sys_eth_hw_activate);
 480 +
 481 +/**
 482 + * Deactivate the selected module(s)
 483 + * Disables the clock of the module and deactivates the module itself.
 484 + *
 485 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.DEACT
 486 + * \return void
 487 + */
 488 +void sys_eth_hw_deactivate(u32 mask)
 489 +{
 490 +       sys_eth_w32(mask, clkclr);
 491 +       sys_eth_w32(mask, deact);
 492 +
 493 +       while ( (sys_eth_r32(acts) & mask) != 0) {
 494 +               /*NOP;*/
 495 +       };
 496 +}
 497 +EXPORT_SYMBOL(sys_eth_hw_deactivate);
 498 +
 499 +/**
 500 + * Clock enable for the selected module(s)
 501 + * Enables the clock of the module.
 502 + *
 503 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKEN
 504 + * \return void
 505 + */
 506 +void sys_eth_hw_clk_enable(u32 mask)
 507 +{
 508 +       sys_eth_w32(mask, clken);
 509 +
 510 +       while ( (sys_eth_r32(clks) & mask) != mask) {
 511 +               /*NOP;*/
 512 +       };
 513 +}
 514 +EXPORT_SYMBOL(sys_eth_hw_clk_enable);
 515 +
 516 +/**
 517 + * Clock disable for the selected module(s)
 518 + * disables the clock of the module.
 519 + *
 520 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKCLR
 521 + * \return void
 522 + */
 523 +void sys_eth_hw_clk_disable(u32 mask)
 524 +{
 525 +       sys_eth_w32(mask, clkclr);
 526 +
 527 +       while ( (sys_eth_r32(clks) & mask) != 0) {
 528 +               /*NOP;*/
 529 +       };
 530 +}
 531 +EXPORT_SYMBOL(sys_eth_hw_clk_disable);
 532 +
 533 +/**
 534 + * Reboots the selected module(s)
 535 + * Triggers the reboot of the module.
 536 + *
 537 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.RBT
 538 + * \return void
 539 + */
 540 +void sys_eth_hw_activate_or_reboot(u32 mask)
 541 +{
 542 +       u32 acts = sys_eth_r32(acts);
 543 +       /* is not already active? */
 544 +       if ((~acts & mask) != 0)
 545 +               sys_eth_hw_activate(~acts & mask);
 546 +       sys_eth_w32(acts & mask, rbt);
 547 +       while ( (sys_eth_r32(acts) & mask) != mask) {
 548 +               /*NOP;*/
 549 +       };
 550 +}
 551 +EXPORT_SYMBOL(sys_eth_hw_activate_or_reboot);
 552 +
 553 +static int gpe_clk_is_enabled(void)
 554 +{
 555 +       u32 rd_data;
 556 +
 557 +       rd_data = sys1_r32(infrac);
 558 +       if (rd_data & (1<<(INFRAC_GP_OFFSET+1)))
 559 +               return 1;
 560 +       return 0;
 561 +}
 562 +
 563 +static void enable_gpe_clk(void)
 564 +{
 565 +       u32 aeFreq;
 566 +       u32 rd_data;
 567 +       u32 rd_data_to_keep;
 568 +       int i;
 569 +
 570 +       if (gpe_clk_is_enabled())
 571 +               /* clock already active, no need to change here */
 572 +               return;
 573 +
 574 +       if (status_r32(config) == 0)
 575 +               aeFreq = 1; /* use 625MHz on unfused chip */
 576 +       else
 577 +               aeFreq = (status_r32(config) & STATUS_CONFIG_GPEFREQ_MASK) >> STATUS_CONFIG_GPEFREQ_OFFSET;
 578 +       rd_data = sys1_r32(infrac);
 579 +       /* clear gpe-fsel and enable bits */
 580 +       rd_data_to_keep = rd_data & ~(7<<(INFRAC_GP_OFFSET+1));
 581 +
 582 +       /* set new fsel */
 583 +       sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)), infrac);
 584 +
 585 +       for (i = 0; i <10; i++) /* wait 10 cycles */
 586 +               {}
 587 +
 588 +       /* keep new fsel and enable */
 589 +       sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)) |
 590 +               (1<<(INFRAC_GP_OFFSET+1)), infrac);
 591 +       for (i = 0; i <100; i++) /* wait 100 cycles */
 592 +               {}
 593 +}
 594 +
 595 +/**
 596 + * Activate the selected module(s)
 597 + * Enables the clock of the module and activates the module itself.
 598 + *
 599 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.ACT
 600 + * \return void
 601 + */
 602 +void sys_gpe_hw_activate(u32 mask)
 603 +{
 604 +       enable_gpe_clk();
 605 +       sys_gpe_w32(mask, clken);
 606 +       sys_gpe_w32(mask, act);
 607 +
 608 +       while ( (sys_gpe_r32(acts) & mask) != mask) {
 609 +               /*NOP;*/
 610 +       };
 611 +}
 612 +EXPORT_SYMBOL(sys_gpe_hw_activate);
 613 +
 614 +/**
 615 + * Deactivate the selected module(s)
 616 + * Disables the clock of the module and deactivates the module itself.
 617 + *
 618 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.DEACT
 619 + * \return void
 620 + */
 621 +void sys_gpe_hw_deactivate(u32 mask)
 622 +{
 623 +       enable_gpe_clk();
 624 +       sys_gpe_w32(mask, clkclr);
 625 +       sys_gpe_w32(mask, deact);
 626 +
 627 +       while ( (sys_gpe_r32(acts) & mask) != 0) {
 628 +               /*NOP;*/
 629 +       };
 630 +}
 631 +EXPORT_SYMBOL(sys_gpe_hw_deactivate);
 632 +
 633 +/**
 634 + * Clock enable for the selected module(s)
 635 + * Enables the clock of the module.
 636 + *
 637 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKEN
 638 + * \return void
 639 + */
 640 +void sys_gpe_hw_clk_enable(u32 mask)
 641 +{
 642 +       enable_gpe_clk();
 643 +       sys_gpe_w32(mask, clken);
 644 +
 645 +       while ( (sys_gpe_r32(clks) & mask) != mask) {
 646 +               /*NOP;*/
 647 +       };
 648 +}
 649 +EXPORT_SYMBOL(sys_gpe_hw_clk_enable);
 650 +
 651 +/**
 652 + * Clock disable for the selected module(s)
 653 + * disables the clock of the module.
 654 + *
 655 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKCLR
 656 + * \return void
 657 + */
 658 +void sys_gpe_hw_clk_disable(u32 mask)
 659 +{
 660 +       enable_gpe_clk();
 661 +       sys_gpe_w32(mask, clkclr);
 662 +
 663 +       while ( (sys_gpe_r32(clks) & mask) != 0) {
 664 +               /*NOP;*/
 665 +       };
 666 +}
 667 +EXPORT_SYMBOL(sys_gpe_hw_clk_disable);
 668 +
 669 +/**
 670 + * Reboots the selected module(s)
 671 + * Triggers the reboot of the module.
 672 + *
 673 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
 674 + * \return void
 675 + */
 676 +void sys_gpe_hw_activate_or_reboot(u32 mask)
 677 +{
 678 +       u32 acts;
 679 +       enable_gpe_clk();
 680 +       acts = sys_gpe_r32(acts);
 681 +       /* is not already active? */
 682 +       if ((~acts & mask) != 0)
 683 +               sys_gpe_hw_activate(~acts & mask);
 684 +       sys_gpe_w32(acts & mask, rbt);
 685 +       while ( (sys_gpe_r32(acts) & mask) != mask) {
 686 +               /*NOP;*/
 687 +       };
 688 +}
 689 +EXPORT_SYMBOL(sys_gpe_hw_activate_or_reboot);
 690 +
 691 +/**
 692 + * Retrieve activation status of the selected hardware module(s)
 693 + *
 694 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
 695 + * \return int 1 - if hardware module(s) is activated (including clock)
 696 + */
 697 + int sys_gpe_hw_is_activated(u32 mask)
 698 +{
 699 +       if (gpe_clk_is_enabled() == 0)
 700 +               return 0;
 701 +
 702 +       if ((sys_gpe_r32(clks) & mask) != mask)
 703 +               return 0;
 704 +
 705 +       return ((sys_gpe_r32(acts) & mask) == mask);
 706 +}
 707 +EXPORT_SYMBOL(sys_gpe_hw_is_activated);
 708 --- /dev/null
 709 +++ b/arch/mips/lantiq/falcon/gpio.c
 710 @@ -0,0 +1,463 @@
 711 +/*
 712 + *   This program is free software; you can redistribute it and/or modify
 713 + *   it under the terms of the GNU General Public License as published by
 714 + *   the Free Software Foundation; either version 2 of the License, or
 715 + *   (at your option) any later version.
 716 + *
 717 + *   This program is distributed in the hope that it will be useful,
 718 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 719 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 720 + *   GNU General Public License for more details.
 721 + *
 722 + *   You should have received a copy of the GNU General Public License
 723 + *   along with this program; if not, write to the Free Software
 724 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 725 + *
 726 + *   Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 727 + */
 728 +
 729 +/**
 730 +       TODO:
 731 +               - add locking?
 732 +               - provide mask of available pins per platform_data
 733 +*/
 734 +
 735 +#include <linux/module.h>
 736 +#include <linux/types.h>
 737 +#include <linux/errno.h>
 738 +#include <linux/init.h>
 739 +#include <linux/seq_file.h>
 740 +#include <linux/platform_device.h>
 741 +#include <linux/uaccess.h>
 742 +#include <linux/gpio.h>
 743 +#include <linux/irq.h>
 744 +#include <linux/interrupt.h>
 745 +#include <linux/slab.h>
 746 +
 747 +#include <falcon.h>
 748 +#include <falcon/falcon_irq.h>
 749 +
 750 +#include <linux/version.h>
 751 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
 752 +#define for_each_set_bit for_each_bit
 753 +#endif
 754 +
 755 +#define gpio_r32(reg)                  __raw_readl(reg)
 756 +#define gpio_w32(val, reg)                     __raw_writel(val, reg)
 757 +#define gpio_w32_mask(clear, set, reg) gpio_w32((gpio_r32(reg) & ~(clear)) | (set), reg)
 758 +
 759 +
 760 +/** register structure for padctrl
 761 +    (mainly needed for mux control) */
 762 +typedef struct gpon_padctrl_s
 763 +{
 764 +       /** Multiplexer Control Register
 765 +           The value 0 (the reset-value) is always the default function corresponding to the pad's name. The value 1 selects always the GPIO functionality (if available). */
 766 +       unsigned int muxc[32];
 767 +       /** Pull Up Enable Register */
 768 +       unsigned int puen; /* 0x00000080 */
 769 +       /** Pull Down Enable Register */
 770 +       unsigned int pden; /* 0x00000084 */
 771 +       /** Slew Rate Control Register */
 772 +       unsigned int src; /* 0x00000088 */
 773 +       /** Drive Current Control Register */
 774 +       unsigned int dcc; /* 0x0000008C */
 775 +       /** Reserved */
 776 +       unsigned int res_0[24]; /* 0x00000090 */
 777 +       /** Pad Control Availability Register */
 778 +       unsigned int avail; /* 0x000000F0 */
 779 +} gpon_padctrl0_t;
 780 +
 781 +/** register structure for gpio port */
 782 +typedef struct gpon_gpio_s
 783 +{
 784 +       /** Data Output Register
 785 +           Via this register the output values of the different bits can be set if they are switched as outputs. */
 786 +       unsigned int out; /* 0x00000000 */
 787 +       /** Data Input Register
 788 +           Via this register the input values of the different bits can be observed. */
 789 +       unsigned int in; /* 0x00000004 */
 790 +       /** Direction Register
 791 +           Via this register the input direction of the different bits can be determined. */
 792 +       unsigned int dir; /* 0x00000008 */
 793 +       /** Reserved */
 794 +       unsigned int res_0[3]; /* 0x0000000C */
 795 +       /** External Interrupt Control Register 0 */
 796 +       unsigned int exintcr0; /* 0x00000018 */
 797 +       /** External Interrupt Control Register 1 */
 798 +       unsigned int exintcr1; /* 0x0000001C */
 799 +       /** IRN Capture Register
 800 +           This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
 801 +       unsigned int irncr; /* 0x00000020 */
 802 +       /** IRN Interrupt Control Register
 803 +           A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
 804 +       unsigned int irnicr; /* 0x00000024 */
 805 +       /** IRN Interrupt Enable Register
 806 +           This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
 807 +       unsigned int irnen; /* 0x00000028 */
 808 +       /** IRN Interrupt Configuration Register
 809 +           Configures the interrupts bitwise to be edge-senstivie or level-sensitive. */
 810 +       unsigned int irncfg; /* 0x0000002C */
 811 +       /** IRN Interrupt Enable Set Register
 812 +           The corresponding bit in the IRNEN register can be set with an atomic access. */
 813 +       unsigned int irnenset; /* 0x00000030 */
 814 +       /** IRN Interrupt Enable Clear Register
 815 +           The corresponding bit in the IRNEN register can be cleared with an atomic access. */
 816 +       unsigned int irnenclr; /* 0x00000034 */
 817 +       /** Reserved */
 818 +       unsigned int res_1[2]; /* 0x00000038 */
 819 +       /** Output Set Register
 820 +           This register can be used to set certain bits within the OUT register without touching the other bits. */
 821 +       unsigned int outset; /* 0x00000040 */
 822 +       /** Output Clear Register
 823 +           This register can be used to clear certain bits within the OUT register without touching the other bits. */
 824 +       unsigned int outclr; /* 0x00000044 */
 825 +       /** Direction Set Register
 826 +           This register can be used to set certain bits within the DIR register without touching the other bits. */
 827 +       unsigned int dirset; /* 0x00000048 */
 828 +       /** Direction Clear Register
 829 +           This register can be used to clear certain bits within the DIR register without touching the other bits. */
 830 +       unsigned int dirclr; /* 0x0000004C */
 831 +} gpon_gpio_t;
 832 +
 833 +struct falcon_gpio_port {
 834 +       struct gpio_chip gpio_chip;
 835 +       gpon_padctrl0_t __iomem *pad;
 836 +       gpon_gpio_t __iomem *port;
 837 +       struct resource *pad_req;   /* resources requested */
 838 +       struct resource *port_req;
 839 +       unsigned int irq_base;
 840 +       unsigned int chained_irq;
 841 +};
 842 +
 843 +static int gpio_exported = 0;
 844 +static int __init gpio_export_setup(char *str)
 845 +{
 846 +       get_option(&str, &gpio_exported);
 847 +       return 1;
 848 +}
 849 +__setup("gpio_exported=", gpio_export_setup);
 850 +
 851 +static inline struct falcon_gpio_port *to_falcon_gpio_port(struct gpio_chip *chip)
 852 +{
 853 +       return container_of(chip, struct falcon_gpio_port, gpio_chip);
 854 +}
 855 +
 856 +static int falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 857 +{
 858 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 859 +       gpio_w32(1<<offset, &gpio_port->port->dirclr);
 860 +       return 0;
 861 +}
 862 +
 863 +static int falcon_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
 864 +{
 865 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 866 +       gpio_w32(1<<offset, &gpio_port->port->dirset);
 867 +       return 0;
 868 +}
 869 +
 870 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 871 +{
 872 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 873 +       if (value)
 874 +               gpio_w32(1<<offset, &gpio_port->port->outset);
 875 +       else
 876 +               gpio_w32(1<<offset, &gpio_port->port->outclr);
 877 +}
 878 +
 879 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 880 +{
 881 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 882 +       if ((gpio_r32(&gpio_port->port->dir) >> offset) & 1)
 883 +               return (gpio_r32(&gpio_port->port->out) >> offset) & 1;
 884 +       else
 885 +               return (gpio_r32(&gpio_port->port->in) >> offset) & 1;
 886 +}
 887 +
 888 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 889 +{
 890 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 891 +       if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
 892 +               if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
 893 +                       return -EBUSY;
 894 +               /* switch on gpio function */
 895 +               gpio_w32(1, &gpio_port->pad->muxc[offset]);
 896 +               return 0;
 897 +       }
 898 +
 899 +       return -ENODEV;
 900 +}
 901 +
 902 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 903 +{
 904 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 905 +       if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
 906 +               if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
 907 +                       return;
 908 +               /* switch off gpio function */
 909 +               gpio_w32(0, &gpio_port->pad->muxc[offset]);
 910 +       }
 911 +}
 912 +
 913 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 914 +{
 915 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 916 +       /* no checks: this functions is only registered with valid irq_base */
 917 +       return gpio_port->irq_base + offset;
 918 +}
 919 +
 920 +static void falcon_gpio_disable_irq(unsigned int irq)
 921 +{
 922 +       struct falcon_gpio_port *gpio_port = get_irq_chip_data(irq);
 923 +       unsigned int offset = irq-gpio_port->irq_base;
 924 +       gpio_w32(1<<offset, &gpio_port->port->irnenclr);
 925 +}
 926 +
 927 +static void falcon_gpio_enable_irq(unsigned int irq)
 928 +{
 929 +       struct falcon_gpio_port *gpio_port = get_irq_chip_data(irq);
 930 +       unsigned int offset = irq-gpio_port->irq_base;
 931 +
 932 +       if (gpio_r32(&gpio_port->pad->muxc[offset]) < 1) {
 933 +               /* switch on gpio function */
 934 +               gpio_w32(1, &gpio_port->pad->muxc[offset]);
 935 +       }
 936 +
 937 +       gpio_w32(1<<offset, &gpio_port->port->irnenset);
 938 +}
 939 +
 940 +static void falcon_gpio_ack_irq(unsigned int irq)
 941 +{
 942 +       struct falcon_gpio_port *gpio_port = get_irq_chip_data(irq);
 943 +       unsigned int offset = irq-gpio_port->irq_base;
 944 +       gpio_w32(1<<offset, &gpio_port->port->irncr);
 945 +}
 946 +
 947 +static void falcon_gpio_mask_and_ack_irq(unsigned int irq)
 948 +{
 949 +       struct falcon_gpio_port *gpio_port = get_irq_chip_data(irq);
 950 +       unsigned int offset = irq-gpio_port->irq_base;
 951 +       gpio_w32(1<<offset, &gpio_port->port->irnenclr);
 952 +       gpio_w32(1<<offset, &gpio_port->port->irncr);
 953 +}
 954 +
 955 +static struct irq_chip falcon_gpio_irq_chip;
 956 +static int falcon_gpio_irq_type(unsigned irq, unsigned int type)
 957 +{
 958 +       struct falcon_gpio_port *gpio_port = get_irq_chip_data(irq);
 959 +       unsigned int offset = irq-gpio_port->irq_base;
 960 +       unsigned int mask = 1 << offset;
 961 +
 962 +       if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
 963 +               return 0;
 964 +
 965 +       if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
 966 +               /* level triggered */
 967 +               gpio_w32_mask(0, mask, &gpio_port->port->irncfg);
 968 +               set_irq_chip_and_handler_name(irq,
 969 +                               &falcon_gpio_irq_chip, handle_level_irq, "mux");
 970 +       } else {
 971 +               /* edge triggered */
 972 +               gpio_w32_mask(mask, 0, &gpio_port->port->irncfg);
 973 +               set_irq_chip_and_handler_name(irq,
 974 +                               &falcon_gpio_irq_chip, handle_simple_irq, "mux");
 975 +       }
 976 +
 977 +       if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 978 +               gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
 979 +               gpio_w32_mask(0, mask, &gpio_port->port->exintcr1);
 980 +       } else {
 981 +               if ((type & (IRQ_TYPE_EDGE_RISING |IRQ_TYPE_LEVEL_HIGH)) != 0) {
 982 +                       /* positive logic: rising edge, high level */
 983 +                       gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
 984 +               } else {
 985 +                       /* negative logic: falling edge, low level */
 986 +                       gpio_w32_mask(0, mask, &gpio_port->port->exintcr0);
 987 +               }
 988 +               gpio_w32_mask(mask, 0, &gpio_port->port->exintcr1);
 989 +       }
 990 +
 991 +       return gpio_direction_input(gpio_port->gpio_chip.base + offset);
 992 +}
 993 +
 994 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 995 +{
 996 +       struct falcon_gpio_port *gpio_port = get_irq_desc_data(desc);
 997 +       unsigned long irncr;
 998 +       int offset;
 999 +
1000 +       irncr = gpio_r32(&gpio_port->port->irncr);
1001 +       /* acknowledge interrupt */
1002 +       gpio_w32(irncr, &gpio_port->port->irncr);
1003 +
1004 +       desc->chip->ack(irq);
1005 +
1006 +       for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
1007 +               generic_handle_irq(gpio_port->irq_base + offset);
1008 +}
1009 +
1010 +static struct irq_chip falcon_gpio_irq_chip = {
1011 +       .name = "gpio_irq_mux",
1012 +       .mask = falcon_gpio_disable_irq,
1013 +       .unmask = falcon_gpio_enable_irq,
1014 +       .ack = falcon_gpio_ack_irq,
1015 +       .mask_ack = falcon_gpio_mask_and_ack_irq,
1016 +       .set_type = falcon_gpio_irq_type,
1017 +};
1018 +
1019 +static struct irqaction gpio_cascade = {
1020 +       .handler = no_action,
1021 +       .flags = IRQF_DISABLED,
1022 +       .name = "gpio_cascade",
1023 +};
1024 +
1025 +static int falcon_gpio_probe(struct platform_device *pdev)
1026 +{
1027 +       struct falcon_gpio_port *gpio_port;
1028 +       int ret, i;
1029 +       struct resource *gpiores, *padres;
1030 +       int irq;
1031 +
1032 +       gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1033 +       padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1034 +       irq = platform_get_irq(pdev, 0);
1035 +       if (!gpiores || !padres)
1036 +               return -ENODEV;
1037 +
1038 +       gpio_port = kzalloc(sizeof(*gpio_port), GFP_KERNEL);
1039 +       if (gpio_port == NULL)
1040 +               return -ENOMEM;
1041 +
1042 +       gpio_port->gpio_chip.label = "falcon-gpio";
1043 +       gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
1044 +       gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
1045 +       gpio_port->gpio_chip.get = falcon_gpio_get;
1046 +       gpio_port->gpio_chip.set = falcon_gpio_set;
1047 +       gpio_port->gpio_chip.request = falcon_gpio_request;
1048 +       gpio_port->gpio_chip.free = falcon_gpio_free;
1049 +       gpio_port->gpio_chip.base = 100 * pdev->id;
1050 +       gpio_port->gpio_chip.ngpio = 32;
1051 +       gpio_port->gpio_chip.dev = &pdev->dev;
1052 +       gpio_port->gpio_chip.exported = gpio_exported;
1053 +
1054 +       gpio_port->port_req = request_mem_region(gpiores->start,
1055 +               resource_size(gpiores), pdev->name);
1056 +       gpio_port->pad_req = request_mem_region(padres->start,
1057 +               resource_size(padres), pdev->name);
1058 +       if (!gpio_port->port_req || !gpio_port->pad_req) {
1059 +               dev_err(&pdev->dev, "cannot claim register area\n");
1060 +               ret = -EIO;
1061 +               goto err;
1062 +       }
1063 +
1064 +       gpio_port->port = ioremap_nocache(gpiores->start,
1065 +               resource_size(gpiores));
1066 +       gpio_port->pad = ioremap_nocache(padres->start,
1067 +               resource_size(padres));
1068 +       if (!gpio_port->port || !gpio_port->pad) {
1069 +               dev_err(&pdev->dev, "Could not map io ranges\n");
1070 +               ret = -ENOMEM;
1071 +               goto err;
1072 +       }
1073 +
1074 +       if (irq>0) {
1075 +               /*
1076 +                * irq_chip support
1077 +                */
1078 +               gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
1079 +               gpio_port->irq_base = INT_NUM_EXTRA_START + 32 * pdev->id;
1080 +
1081 +               for (i = 0; i < 32; i++) {
1082 +                       set_irq_chip_and_handler_name(gpio_port->irq_base + i,
1083 +                               &falcon_gpio_irq_chip, handle_simple_irq, "mux");
1084 +                       set_irq_chip_data(gpio_port->irq_base + i, gpio_port);
1085 +                       /* FIXME: set default cfg to level triggered */
1086 +                       //gpio_w32_mask(0, 1<<i, &gpio_port->port->irncfg);
1087 +                       /* set to negative logic (falling edge, low level) */
1088 +                       gpio_w32_mask(0, 1<<i, &gpio_port->port->exintcr0);
1089 +               }
1090 +
1091 +               gpio_port->chained_irq = irq;
1092 +               setup_irq(irq, &gpio_cascade);
1093 +               set_irq_data(irq, gpio_port);
1094 +               set_irq_chained_handler(irq, falcon_gpio_irq_handler);
1095 +       }
1096 +
1097 +       ret = gpiochip_add(&gpio_port->gpio_chip);
1098 +       if (ret < 0) {
1099 +               dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
1100 +                       pdev->id, ret);
1101 +               goto err;
1102 +       }
1103 +       platform_set_drvdata(pdev, gpio_port);
1104 +       return ret;
1105 +
1106 +err:
1107 +       dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
1108 +       if (gpio_port->port_req)
1109 +               release_resource(gpio_port->port_req);
1110 +       if (gpio_port->pad_req)
1111 +               release_resource(gpio_port->pad_req);
1112 +
1113 +       if (gpio_port->port)
1114 +               iounmap(gpio_port->port);
1115 +       if (gpio_port->pad)
1116 +               iounmap(gpio_port->pad);
1117 +       kfree(gpio_port);
1118 +       return ret;
1119 +}
1120 +
1121 +static int falcon_gpio_remove(struct platform_device *pdev)
1122 +{
1123 +       struct falcon_gpio_port *gpio_port = platform_get_drvdata(pdev);
1124 +       int ret;
1125 +
1126 +       ret = gpiochip_remove(&gpio_port->gpio_chip);
1127 +       if (gpio_port->port_req)
1128 +               release_resource(gpio_port->port_req);
1129 +       if (gpio_port->pad_req)
1130 +               release_resource(gpio_port->pad_req);
1131 +       if (gpio_port->port)
1132 +               iounmap(gpio_port->port);
1133 +       if (gpio_port->pad)
1134 +               iounmap(gpio_port->pad);
1135 +       if (ret == 0)
1136 +               kfree(gpio_port);
1137 +
1138 +       return ret;
1139 +}
1140 +
1141 +static struct platform_driver falcon_gpio_driver = {
1142 +       .probe = falcon_gpio_probe,
1143 +       .remove = __devexit_p(falcon_gpio_remove),
1144 +       .driver = {
1145 +               .name = "falcon_gpio",
1146 +               .owner = THIS_MODULE,
1147 +       },
1148 +};
1149 +
1150 +int __init falcon_gpio_init(void)
1151 +{
1152 +       int ret;
1153 +
1154 +       printk(KERN_INFO "FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
1155 +       ret = platform_driver_register(&falcon_gpio_driver);
1156 +       if (ret)
1157 +               pr_err( "falcon_gpio: Error registering platform driver!");
1158 +       return ret;
1159 +}
1160 +
1161 +void __exit falcon_gpio_exit(void)
1162 +{
1163 +       platform_driver_unregister(&falcon_gpio_driver);
1164 +}
1165 +
1166 +int gpio_to_irq(unsigned int gpio)
1167 +{
1168 +       return __gpio_to_irq(gpio);
1169 +}
1170 +EXPORT_SYMBOL(gpio_to_irq);
1171 +
1172 +module_init(falcon_gpio_init);
1173 +module_exit(falcon_gpio_exit);
1174 --- /dev/null
1175 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon.h
1176 @@ -0,0 +1,30 @@
1177 +/*
1178 + *   This program is free software; you can redistribute it and/or modify
1179 + *   it under the terms of the GNU General Public License as published by
1180 + *   the Free Software Foundation; either version 2 of the License, or
1181 + *   (at your option) any later version.
1182 + *
1183 + *   Copyright (C) 2005 infineon
1184 + *   Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1185 + */
1186 +
1187 +#ifdef CONFIG_SOC_LANTIQ_FALCON
1188 +
1189 +#ifndef _LQ_FALCON_H__
1190 +#define _LQ_FALCON_H__
1191 +
1192 +#include <lantiq.h>
1193 +#include <falcon/gpon_reg_base.h>
1194 +
1195 +/*------------ GENERAL */
1196 +#define BOARD_SYSTEM_TYPE              "LANTIQ"
1197 +
1198 +/*------------ Chip IDs */
1199 +#define SOC_ID_FALCON          0x01B8
1200 +
1201 +/*------------ SoC Types */
1202 +#define SOC_TYPE_FALCON                0x01
1203 +
1204 +#endif
1205 +
1206 +#endif
1207 --- /dev/null
1208 +++ b/arch/mips/lantiq/falcon/reset.c
1209 @@ -0,0 +1,72 @@
1210 +/*
1211 + * This program is free software; you can redistribute it and/or modify
1212 + * it under the terms of the GNU General Public License as published by
1213 + * the Free Software Foundation; either version 2 of the License, or
1214 + * (at your option) any later version.
1215 + *
1216 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1217 + */
1218 +
1219 +#include <linux/init.h>
1220 +#include <linux/io.h>
1221 +#include <linux/pm.h>
1222 +#include <asm/reboot.h>
1223 +
1224 +#include <falcon.h>
1225 +#include <falcon/gpon_reg_base.h>
1226 +#include <falcon/status_reg.h>
1227 +#include <falcon/sys1_reg.h>
1228 +
1229 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
1230 +
1231 +#define WDT_PW1                        0x00BE0000
1232 +#define WDT_PW2                        0x00DC0000
1233 +#define WDT_REG_BASE           (KSEG1 | 0x1F8803F0)
1234 +
1235 +static void
1236 +lq_machine_restart(char *command)
1237 +{
1238 +       printk(KERN_NOTICE "System restart\n");
1239 +       local_irq_disable();
1240 +       lq_w32(0, (void*)0xBF200000); /* reset Bootreg RVEC */
1241 +#if 0
1242 +       lq_w32(RBT_CPU_TRIG, &pSYS1->rbt);
1243 +#else
1244 +       /* use workaround via watchdog timer */
1245 +       lq_w32(WDT_PW1, (void*)WDT_REG_BASE);
1246 +       lq_w32(WDT_PW2 |
1247 +               (0x3 << 26) | /* PWL */
1248 +               (0x2 << 24) | /* CLKDIV */
1249 +               (0x1 << 31) | /* enable */
1250 +               (1), /* reload */
1251 +               (void*)WDT_REG_BASE);
1252 +#endif
1253 +       for(;;);
1254 +}
1255 +
1256 +static void
1257 +lq_machine_halt(void)
1258 +{
1259 +       printk(KERN_NOTICE "System halted.\n");
1260 +       local_irq_disable();
1261 +       for(;;);
1262 +}
1263 +
1264 +static void
1265 +lq_machine_power_off(void)
1266 +{
1267 +       printk(KERN_NOTICE "Please turn off the power now.\n");
1268 +       local_irq_disable();
1269 +       for(;;);
1270 +}
1271 +
1272 +static int __init
1273 +mips_reboot_setup(void)
1274 +{
1275 +       _machine_restart = lq_machine_restart;
1276 +       _machine_halt = lq_machine_halt;
1277 +       pm_power_off = lq_machine_power_off;
1278 +       return 0;
1279 +}
1280 +
1281 +arch_initcall(mips_reboot_setup);
1282 --- /dev/null
1283 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
1284 @@ -0,0 +1,246 @@
1285 +#include <linux/init.h>
1286 +#include <linux/platform_device.h>
1287 +#include <linux/leds.h>
1288 +#include <linux/gpio.h>
1289 +#include <linux/gpio_buttons.h>
1290 +#include <linux/etherdevice.h>
1291 +#include <linux/mtd/mtd.h>
1292 +#include <linux/mtd/partitions.h>
1293 +#include <linux/mtd/physmap.h>
1294 +#include <linux/input.h>
1295 +#include <linux/interrupt.h>
1296 +#include <linux/dm9000.h>
1297 +#include <linux/i2c.h>
1298 +#include <linux/i2c-gpio.h>
1299 +#include <linux/spi/spi.h>
1300 +#include <linux/spi/spi_gpio.h>
1301 +#include <linux/spi/eeprom.h>
1302 +#include <machine.h>
1303 +
1304 +#include "devices.h"
1305 +#include "dev-leds-gpio.h"
1306 +
1307 +#define EASY98000_GPIO_LED_0 9
1308 +#define EASY98000_GPIO_LED_1 10
1309 +#define EASY98000_GPIO_LED_2 11
1310 +#define EASY98000_GPIO_LED_3 12
1311 +#define EASY98000_GPIO_LED_4 13
1312 +#define EASY98000_GPIO_LED_5 14
1313 +
1314 +extern unsigned char lq_ethaddr[6];
1315 +
1316 +#ifdef CONFIG_MTD_PARTITIONS
1317 +static struct mtd_partition easy98000_nor_partitions[] =
1318 +{
1319 +       {
1320 +               .name   = "uboot",
1321 +               .offset = 0x0,
1322 +               .size   = 0x40000,
1323 +       },
1324 +       {
1325 +               .name   = "uboot_env",
1326 +               .offset = 0x40000,
1327 +               .size   = 0x40000,      /* 2 sectors for redundant env. */
1328 +       },
1329 +       {
1330 +               .name   = "linux",
1331 +               .offset = 0x80000,
1332 +               .size   = 0xF80000,     /* map only 16 MiB */
1333 +       },
1334 +};
1335 +#endif
1336 +
1337 +static struct physmap_flash_data easy98000_nor_flash_data = {
1338 +#ifdef CONFIG_MTD_PARTITIONS
1339 +       .nr_parts       = ARRAY_SIZE(easy98000_nor_partitions),
1340 +       .parts          = easy98000_nor_partitions,
1341 +#endif
1342 +};
1343 +
1344 +#ifdef CONFIG_MTD_PARTITIONS
1345 +static struct flash_platform_data easy98000_spi_flash_platform_data = {
1346 +       .name = "sflash",
1347 +       .parts = easy98000_nor_partitions,
1348 +       .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
1349 +};
1350 +#endif
1351 +
1352 +static struct spi_board_info easy98000_spi_flash_data __initdata = {
1353 +       .modalias               = "m25p80",
1354 +       .bus_num                = 0,
1355 +       .chip_select            = 0,
1356 +       .max_speed_hz           = 10 * 1000 * 1000,
1357 +       .mode                   = SPI_MODE_3,
1358 +#ifdef CONFIG_MTD_PARTITIONS
1359 +       .platform_data          = &easy98000_spi_flash_platform_data
1360 +#endif
1361 +};
1362 +
1363 +static struct gpio_led easy98000_leds_gpio[] __initdata = {
1364 +       {
1365 +               .name           = "easy98000:green:0",
1366 +               .gpio           = EASY98000_GPIO_LED_0,
1367 +               .active_low     = 0,
1368 +       }, {
1369 +               .name           = "easy98000:green:1",
1370 +               .gpio           = EASY98000_GPIO_LED_1,
1371 +               .active_low     = 0,
1372 +       }, {
1373 +               .name           = "easy98000:green:2",
1374 +               .gpio           = EASY98000_GPIO_LED_2,
1375 +               .active_low     = 0,
1376 +       }, {
1377 +               .name           = "easy98000:green:3",
1378 +               .gpio           = EASY98000_GPIO_LED_3,
1379 +               .active_low     = 0,
1380 +       }, {
1381 +               .name           = "easy98000:green:4",
1382 +               .gpio           = EASY98000_GPIO_LED_4,
1383 +               .active_low     = 0,
1384 +       }, {
1385 +               .name           = "easy98000:green:5",
1386 +               .gpio           = EASY98000_GPIO_LED_5,
1387 +               .active_low     = 0,
1388 +       }
1389 +};
1390 +
1391 +#define CONFIG_DM9000_BASE             0x14000000
1392 +#define DM9000_IO                      (CONFIG_DM9000_BASE + 3)
1393 +#define DM9000_DATA                    (CONFIG_DM9000_BASE + 1)
1394 +
1395 +static struct dm9000_plat_data dm9000_plat_data = {
1396 +       .flags = DM9000_PLATF_8BITONLY,
1397 +       //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */
1398 +};
1399 +
1400 +static struct resource dm9000_resources[] = {
1401 +       MEM_RES("dm9000_io", DM9000_IO, DM9000_IO),
1402 +       MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA),
1403 +       [2] = {
1404 +               /* with irq (210 -> gpio 110) the driver is very unreliable */
1405 +               .start  = -1,           /* use polling */
1406 +               .end    = -1,
1407 +               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
1408 +       },
1409 +};
1410 +
1411 +static struct platform_device dm9000_platform = {
1412 +       .name = "dm9000",
1413 +       .id = 0,
1414 +       .num_resources  = ARRAY_SIZE(dm9000_resources),
1415 +       .resource       = dm9000_resources,
1416 +       .dev = {
1417 +               .platform_data = (void *) &dm9000_plat_data,
1418 +       }
1419 +};
1420 +
1421 +static void __init register_davicom(void)
1422 +{
1423 +       if (!is_valid_ether_addr(lq_ethaddr))
1424 +               random_ether_addr(dm9000_plat_data.dev_addr);
1425 +       else {
1426 +               memcpy(dm9000_plat_data.dev_addr, lq_ethaddr, 6);
1427 +               /* change to "Locally Administered Address" */
1428 +               dm9000_plat_data.dev_addr[0] |= 0x2;
1429 +       }
1430 +       platform_device_register(&dm9000_platform);
1431 +}
1432 +
1433 +static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = {
1434 +       .sda_pin        = 107,
1435 +       .scl_pin        = 108,
1436 +};
1437 +
1438 +static struct platform_device easy98000_i2c_gpio_device = {
1439 +       .name           = "i2c-gpio",
1440 +       .id             = 0,
1441 +       .dev = {
1442 +               .platform_data  = &easy98000_i2c_gpio_data,
1443 +       }
1444 +};
1445 +
1446 +void __init register_easy98000_cpld_led(void)
1447 +{
1448 +       platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0);
1449 +}
1450 +
1451 +/* setup gpio based spi bus/device for access to the eeprom on the board */
1452 +#define SPI_GPIO_MRST  102
1453 +#define SPI_GPIO_MTSR  103
1454 +#define SPI_GPIO_CLK   104
1455 +#define SPI_GPIO_CS0   105
1456 +#define SPI_GPIO_CS1   106
1457 +#define SPI_GPIO_BUS_NUM       1
1458 +
1459 +static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
1460 +       .sck            = SPI_GPIO_CLK,
1461 +       .mosi           = SPI_GPIO_MTSR,
1462 +       .miso           = SPI_GPIO_MRST,
1463 +       .num_chipselect = 2,
1464 +};
1465 +
1466 +static struct platform_device easy98000_spi_gpio_device = {
1467 +       .name                   = "spi_gpio",
1468 +       .id                     = SPI_GPIO_BUS_NUM,
1469 +       .dev.platform_data      = &easy98000_spi_gpio_data,
1470 +};
1471 +
1472 +static struct spi_eeprom at25160n = {
1473 +       .byte_len       = 16 * 1024 / 8,
1474 +       .name           = "at25160n",
1475 +       .page_size      = 32,
1476 +       .flags          = EE_ADDR2,
1477 +};
1478 +
1479 +static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
1480 +       .modalias               = "at25",
1481 +       .bus_num                = SPI_GPIO_BUS_NUM,
1482 +       .max_speed_hz           = 1000 * 1000,
1483 +       .mode                   = SPI_MODE_3,
1484 +       .chip_select            = 1,
1485 +       .controller_data        = (void *) SPI_GPIO_CS1,
1486 +       .platform_data          = &at25160n,
1487 +};
1488 +
1489 +static void __init easy98000_spi_gpio_init(void)
1490 +{
1491 +       spi_register_board_info(&easy98000_spi_gpio_devices, 1);
1492 +       platform_device_register(&easy98000_spi_gpio_device);
1493 +}
1494 +
1495 +static void __init easy98000_init_common(void)
1496 +{
1497 +       falcon_register_asc(0);
1498 +       falcon_register_gpio();
1499 +       falcon_register_wdt();
1500 +       falcon_register_i2c();
1501 +       platform_device_register(&easy98000_i2c_gpio_device);
1502 +       register_davicom();
1503 +       lq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio),
1504 +                                       easy98000_leds_gpio);
1505 +       register_easy98000_cpld_led();
1506 +       falcon_register_crypto();
1507 +       easy98000_spi_gpio_init();
1508 +}
1509 +
1510 +static void __init easy98000_init(void)
1511 +{
1512 +       easy98000_init_common();
1513 +       falcon_register_nor(&easy98000_nor_flash_data);
1514 +}
1515 +
1516 +static void __init easy98000sf_init(void)
1517 +{
1518 +       easy98000_init_common();
1519 +       falcon_register_spi_flash(&easy98000_spi_flash_data);
1520 +}
1521 +
1522 +MIPS_MACHINE(LANTIQ_MACH_EASY98000,
1523 +                       "EASY98000",
1524 +                       "EASY98000 Eval Board",
1525 +                       easy98000_init);
1526 +
1527 +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
1528 +                       "EASY98000SF",
1529 +                       "EASY98000 Eval Board (Serial Flash)",
1530 +                       easy98000sf_init);
1531 --- /dev/null
1532 +++ b/arch/mips/lantiq/falcon/softdog_vpe.c
1533 @@ -0,0 +1,109 @@
1534 +/*
1535 +** =============================================================================
1536 +** FILE NAME     : softdog_vpe.c
1537 +** MODULES       : LXDB
1538 +** DATE          : 24-03-2008
1539 +** AUTHOR        : LXDB Team
1540 +** DESCRIPTION   : This header file contains the code for the watchdog
1541 +**                 implentation on vpe1 side.
1542 +** REFERENCES    :
1543 +** COPYRIGHT     : Copyright (c) 2008
1544 +**                 Am Campeon 1-12, 85579 Neubiberg, Germany
1545 +** Any use of this software is subject to the conclusion of a respective
1546 +** License agreement. Without such a License agreement no rights to the
1547 +** software are granted
1548 +**
1549 +** HISTORY       :
1550 +** $Date   $Author    $Comment
1551 +** 24-03-2008   LXDB    Initial version
1552 +** ============================================================================
1553 +*/
1554 +
1555 +#include <linux/module.h>
1556 +#include <linux/moduleparam.h>
1557 +#include <linux/types.h>
1558 +#include <linux/timer.h>
1559 +#include <linux/reboot.h>
1560 +#include <linux/init.h>
1561 +#include <linux/jiffies.h>
1562 +
1563 +#include <falcon/vpe.h>
1564 +
1565 +static unsigned long last_wdog_value;
1566 +static unsigned long vpe1_wdog_cleared;
1567 +
1568 +static unsigned long vpe1_wdog_dead;
1569 +static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */
1570 +static void keep_alive_vpe0(unsigned long);
1571 +VPE_SW_WDOG_RESET reset_local_fn;
1572 +
1573 +
1574 +static struct timer_list watchdog_vpe0_ticktock =
1575 +                TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0);
1576 +
1577 +static void watchdog_vpe0_fire (unsigned long flags)
1578 +{
1579 +       volatile unsigned long *wdog_ctr_value;
1580 +       wdog_ctr_value = (void*)vpe1_wdog_ctr;
1581 +       if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */
1582 +               vpe1_sw_wdog_stop(flags);
1583 +               vpe1_wdog_dead++;
1584 +               printk(KERN_DEBUG "VPE1 watchdog reset handler called\n");
1585 +       /* Call the reset handler function */
1586 +               reset_local_fn(flags);
1587 +       } else { /* Everything is OK on vpe1 side. Continue. */
1588 +               last_wdog_value = *wdog_ctr_value;
1589 +               vpe1_wdog_cleared++;
1590 +               keep_alive_vpe0(flags);
1591 +       }
1592 +}
1593 +
1594 +int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn)
1595 +{
1596 +       reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn;
1597 +       return 0;
1598 +}
1599 +
1600 +static void keep_alive_vpe0(unsigned long flags)
1601 +{
1602 +       mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout );
1603 +}
1604 +
1605 +unsigned long vpe1_sw_wdog_start(unsigned long flags)
1606 +{
1607 +       volatile unsigned long *wdog_ctr_value;
1608 +       wdog_ctr_value = (void*)vpe1_wdog_ctr;
1609 +       *wdog_ctr_value = 0;
1610 +       last_wdog_value = 0;
1611 +       keep_alive_vpe0(flags);
1612 +       return 0;
1613 +}
1614 +
1615 +unsigned long vpe1_sw_wdog_stop(unsigned long flags)
1616 +{
1617 +       del_timer(&watchdog_vpe0_ticktock);
1618 +       return 0;
1619 +}
1620 +
1621 +static int __init watchdog_vpe1_init(void)
1622 +{
1623 +       /* Nothing to be done here */
1624 +       return 0;
1625 +}
1626 +
1627 +static void __exit watchdog_vpe1_exit(void)
1628 +{
1629 +       unsigned long flags=0;
1630 +       vpe1_sw_wdog_stop(flags);
1631 +}
1632 +
1633 +module_init(watchdog_vpe1_init);
1634 +module_exit(watchdog_vpe1_exit);
1635 +
1636 +EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler);
1637 +EXPORT_SYMBOL(vpe1_sw_wdog_start);
1638 +EXPORT_SYMBOL(vpe1_sw_wdog_stop);
1639 +
1640 +MODULE_AUTHOR("LXDB");
1641 +MODULE_DESCRIPTION("Software Watchdog For VPE1");
1642 +MODULE_LICENSE("GPL");
1643 --- /dev/null
1644 +++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
1645 @@ -0,0 +1,44 @@
1646 +/*
1647 + *   This program is free software; you can redistribute it and/or modify
1648 + *   it under the terms of the GNU General Public License as published by
1649 + *   the Free Software Foundation; either version 2 of the License, or
1650 + *   (at your option) any later version.
1651 + *
1652 + *   This program is distributed in the hope that it will be useful,
1653 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1654 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1655 + *   GNU General Public License for more details.
1656 + *
1657 + *   You should have received a copy of the GNU General Public License
1658 + *   along with this program; if not, write to the Free Software
1659 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1660 + *
1661 + *   Copyright (C) 2005 infineon
1662 + *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
1663 + *
1664 + */
1665 +#ifndef _IFXMIPS_VPE_H__
1666 +#define _IFXMIPS_VPE_H__
1667 +
1668 +/* For the explanation of the APIs please refer the section "MT APRP Kernel
1669 + * Programming" in AR9 SW Architecture Specification
1670 + */
1671 +int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags);
1672 +int32_t vpe1_sw_stop(uint32_t flags);
1673 +uint32_t vpe1_get_load_addr (uint32_t flags);
1674 +uint32_t vpe1_get_max_mem (uint32_t flags);
1675 +
1676 +int32_t vpe1_set_boot_param(char *field, char *value, char flags);
1677 +int32_t vpe1_get_boot_param(char *field, char **value, char flags);
1678 +
1679 +/* Watchdog APIs */
1680 +extern unsigned long vpe1_wdog_ctr;
1681 +extern unsigned long vpe1_wdog_timeout;
1682 +
1683 +unsigned long vpe1_sw_wdog_start(unsigned long);
1684 +unsigned long vpe1_sw_wdog_stop(unsigned long);
1685 +
1686 +typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
1687 +int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
1688 +
1689 +#endif
1690 --- a/arch/mips/lantiq/Kconfig
1691 +++ b/arch/mips/lantiq/Kconfig
1692 @@ -21,16 +21,16 @@ choice
1693         prompt "SoC Type"
1694         default SOC_LANTIQ_XWAY
1695
1696 -#config SOC_LANTIQ_FALCON
1697 -#      bool "FALCON"
1698 -#      select SOC_LANTIQ
1699 +config SOC_LANTIQ_FALCON
1700 +       bool "FALCON"
1701 +       select SOC_LANTIQ
1702
1703  config SOC_LANTIQ_XWAY
1704         bool "XWAY"
1705         select SOC_LANTIQ
1706  endchoice
1707
1708 -#source "arch/mips/lantiq/falcon/Kconfig"
1709 +source "arch/mips/lantiq/falcon/Kconfig"
1710  source "arch/mips/lantiq/xway/Kconfig"
1711
1712  if EARLY_PRINTK
1713 --- a/arch/mips/include/asm/mach-lantiq/machine.h
1714 +++ b/arch/mips/include/asm/mach-lantiq/machine.h
1715 @@ -5,6 +5,7 @@ enum lantiq_mach_type {
1716
1717         /* FALCON */
1718         LANTIQ_MACH_EASY98000,          /* Falcon Eval Board, NOR Flash */
1719 +       LANTIQ_MACH_EASY98000SF,        /* Falcon Eval Board, Serial Flash */
1720         LANTIQ_MACH_EASY98020,          /* Falcon Reference Board */
1721
1722         /* XWAY */
1723 --- a/arch/mips/lantiq/Makefile
1724 +++ b/arch/mips/lantiq/Makefile
1725 @@ -1,3 +1,4 @@
1726  obj-y := dev-leds-gpio.o irq.o setup.o clk.o prom.o
1727  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
1728 +obj-$(CONFIG_SOC_LANTIQ_FALCON) += falcon/
1729  obj-$(CONFIG_SOC_LANTIQ_XWAY) += xway/
1730 --- a/arch/mips/lantiq/Platform
1731 +++ b/arch/mips/lantiq/Platform
1732 @@ -5,4 +5,5 @@
1733  platform-$(CONFIG_LANTIQ)      += lantiq/
1734  cflags-$(CONFIG_LANTIQ)       += -I$(srctree)/arch/mips/include/asm/mach-lantiq
1735  load-$(CONFIG_LANTIQ)          = 0xffffffff80002000
1736 +cflags-$(CONFIG_SOC_LANTIQ_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
1737  cflags-$(CONFIG_SOC_LANTIQ_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway