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[s3c24xx] glamo: Implement gpiolib for the glamo. Get rid of glamo-spi-gpio and
[openwrt.git] / target / linux / s3c24xx / files-2.6.30 / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 336x/337x driver
2 *
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/workqueue.h>
34 #include <linux/platform_device.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/spinlock.h>
37 #include <linux/mfd/core.h>
38 #include <linux/mfd/glamo.h>
39 #include <linux/spi/glamo.h>
40 #include <linux/glamo-gpio.h>
41 #include <linux/glamofb.h>
42 #include <linux/io.h>
43
44 #include <asm/div64.h>
45
46 #include <linux/pm.h>
47
48 #include "glamo-regs.h"
49 #include "glamo-core.h"
50
51 #define GLAMO_MEM_REFRESH_COUNT 0x100
52
53 /*
54 * Glamo internal settings
55 *
56 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
57 * above. Couple of GTA02 users report trouble with memory bus when they
58 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
59 * scheme if their Glamo chip needs it.
60 *
61 * you can override the faster default on kernel commandline using
62 *
63 * glamo3362.slow_memory=1
64 *
65 * for example
66 */
67
68 static int slow_memory = 0;
69 module_param(slow_memory, int, 0644);
70
71 struct reg_range {
72 int start;
73 int count;
74 char *name;
75 char dump;
76 };
77
78 struct reg_range reg_range[] = {
79 { 0x0000, 0x76, "General", 1 },
80 { 0x0200, 0x18, "Host Bus", 1 },
81 { 0x0300, 0x38, "Memory", 1 },
82 /* { 0x0400, 0x100, "Sensor", 0 }, */
83 /* { 0x0500, 0x300, "ISP", 0 }, */
84 /* { 0x0800, 0x400, "JPEG", 0 }, */
85 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
86 { 0x1100, 0xb2, "LCD 1", 1 },
87 { 0x1200, 0x64, "LCD 2", 1 },
88 { 0x1400, 0x42, "MMC", 1 },
89 /* { 0x1500, 0x080, "MPU 0", 0 },
90 { 0x1580, 0x080, "MPU 1", 0 },
91 { 0x1600, 0x080, "Cmd Queue", 0 },
92 { 0x1680, 0x080, "RISC CPU", 0 },*/
93 { 0x1700, 0x400, "2D Unit", 0 },
94 /* { 0x1b00, 0x900, "3D Unit", 0 }, */
95 };
96
97 static inline void __reg_write(struct glamo_core *glamo,
98 u_int16_t reg, u_int16_t val)
99 {
100 writew(val, glamo->base + reg);
101 }
102
103 static inline u_int16_t __reg_read(struct glamo_core *glamo,
104 u_int16_t reg)
105 {
106 return readw(glamo->base + reg);
107 }
108
109 static void __reg_set_bit_mask(struct glamo_core *glamo,
110 u_int16_t reg, u_int16_t mask,
111 u_int16_t val)
112 {
113 u_int16_t tmp;
114
115 val &= mask;
116
117 tmp = __reg_read(glamo, reg);
118 tmp &= ~mask;
119 tmp |= val;
120 __reg_write(glamo, reg, tmp);
121 }
122
123 static void reg_set_bit_mask(struct glamo_core *glamo,
124 u_int16_t reg, u_int16_t mask,
125 u_int16_t val)
126 {
127 spin_lock(&glamo->lock);
128 __reg_set_bit_mask(glamo, reg, mask, val);
129 spin_unlock(&glamo->lock);
130 }
131
132 static inline void __reg_set_bit(struct glamo_core *glamo,
133 u_int16_t reg, u_int16_t bit)
134 {
135 __reg_set_bit_mask(glamo, reg, bit, 0xffff);
136 }
137
138 static inline void __reg_clear_bit(struct glamo_core *glamo,
139 u_int16_t reg, u_int16_t bit)
140 {
141 __reg_set_bit_mask(glamo, reg, bit, 0);
142 }
143
144 /***********************************************************************
145 * resources of sibling devices
146 ***********************************************************************/
147
148 static struct resource glamo_fb_resources[] = {
149 {
150 .name = "glamo-fb-regs",
151 .start = GLAMO_REGOFS_LCD,
152 .end = GLAMO_REGOFS_MMC - 1,
153 .flags = IORESOURCE_MEM,
154 }, {
155 .name = "glamo-fb-mem",
156 .start = GLAMO_OFFSET_FB,
157 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 };
161
162 static struct resource glamo_mmc_resources[] = {
163 {
164 .start = GLAMO_REGOFS_MMC,
165 .end = GLAMO_REGOFS_MPROC0 - 1,
166 .flags = IORESOURCE_MEM
167 }, {
168 .start = IRQ_GLAMO_MMC,
169 .end = IRQ_GLAMO_MMC,
170 .flags = IORESOURCE_IRQ,
171 }, { /* our data buffer for MMC transfers */
172 .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
173 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
174 GLAMO_MMC_BUFFER_SIZE - 1,
175 .flags = IORESOURCE_MEM
176 },
177 };
178
179 enum glamo_cells {
180 GLAMO_CELL_FB,
181 GLAMO_CELL_MMC,
182 GLAMO_CELL_GPIO,
183 };
184
185 static struct mfd_cell glamo_cells[] = {
186 [GLAMO_CELL_FB] = {
187 .name = "glamo-fb",
188 .num_resources = ARRAY_SIZE(glamo_fb_resources),
189 .resources = glamo_fb_resources,
190 },
191 [GLAMO_CELL_MMC] = {
192 .name = "glamo-mci",
193 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
194 .resources = glamo_mmc_resources,
195 },
196 [GLAMO_CELL_GPIO] = {
197 .name = "glamo-gpio",
198 },
199 };
200
201
202 /***********************************************************************
203 * IRQ demultiplexer
204 ***********************************************************************/
205 #define irq2glamo(x) (x - IRQ_GLAMO(0))
206
207 static void glamo_ack_irq(unsigned int irq)
208 {
209 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
210 /* clear interrupt source */
211 __reg_write(glamo, GLAMO_REG_IRQ_CLEAR,
212 1 << irq2glamo(irq));
213 }
214
215 static void glamo_mask_irq(unsigned int irq)
216 {
217 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
218 u_int16_t tmp;
219
220 /* clear bit in enable register */
221 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
222 tmp &= ~(1 << irq2glamo(irq));
223 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
224 }
225
226 static void glamo_unmask_irq(unsigned int irq)
227 {
228 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
229 u_int16_t tmp;
230
231 /* set bit in enable register */
232 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
233 tmp |= (1 << irq2glamo(irq));
234 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
235 }
236
237 static struct irq_chip glamo_irq_chip = {
238 .name = "glamo",
239 .ack = glamo_ack_irq,
240 .mask = glamo_mask_irq,
241 .unmask = glamo_unmask_irq,
242 };
243
244 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
245 {
246 struct glamo_core *glamo = get_irq_desc_chip_data(desc);
247 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
248
249 if (unlikely(desc->status & IRQ_INPROGRESS)) {
250 desc->status |= (IRQ_PENDING | IRQ_MASKED);
251 desc->chip->mask(irq);
252 desc->chip->ack(irq);
253 return;
254 }
255 kstat_incr_irqs_this_cpu(irq, desc);
256
257 desc->chip->ack(irq);
258 desc->status |= IRQ_INPROGRESS;
259
260 do {
261 u_int16_t irqstatus;
262 int i;
263
264 if (unlikely((desc->status &
265 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
266 (IRQ_PENDING | IRQ_MASKED))) {
267 /* dealing with pending IRQ, unmasking */
268 desc->chip->unmask(irq);
269 desc->status &= ~IRQ_MASKED;
270 }
271
272 desc->status &= ~IRQ_PENDING;
273
274 /* read IRQ status register */
275 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
276 for (i = 0; i < 9; i++)
277 if (irqstatus & (1 << i))
278 desc_handle_irq(IRQ_GLAMO(i),
279 irq_desc+IRQ_GLAMO(i));
280
281 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
282
283 desc->status &= ~IRQ_INPROGRESS;
284 }
285
286
287 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
288 const char *buf, size_t count)
289 {
290 unsigned long reg = simple_strtoul(buf, NULL, 10);
291 struct glamo_core *glamo = dev_get_drvdata(dev);
292
293 while (*buf && (*buf != ' '))
294 buf++;
295 if (*buf != ' ')
296 return -EINVAL;
297 while (*buf && (*buf == ' '))
298 buf++;
299 if (!*buf)
300 return -EINVAL;
301
302 printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
303 reg, simple_strtoul(buf, NULL, 10));
304
305 __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
306
307 return count;
308 }
309
310 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
311 char *buf)
312 {
313 struct glamo_core *glamo = dev_get_drvdata(dev);
314 int n, n1 = 0, r;
315 char * end = buf;
316
317 spin_lock(&glamo->lock);
318
319 for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
320 if (!reg_range[r].dump)
321 continue;
322 n1 = 0;
323 end += sprintf(end, "\n%s\n", reg_range[r].name);
324 for (n = reg_range[r].start;
325 n < reg_range[r].start + reg_range[r].count; n += 2) {
326 if (((n1++) & 7) == 0)
327 end += sprintf(end, "\n%04X: ", n);
328 end += sprintf(end, "%04x ", __reg_read(glamo, n));
329 }
330 end += sprintf(end, "\n");
331 if (!attr) {
332 printk("%s", buf);
333 end = buf;
334 }
335 }
336 spin_unlock(&glamo->lock);
337
338 return end - buf;
339 }
340
341 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
342 static struct attribute *glamo_sysfs_entries[] = {
343 &dev_attr_regs.attr,
344 NULL
345 };
346 static struct attribute_group glamo_attr_group = {
347 .name = NULL,
348 .attrs = glamo_sysfs_entries,
349 };
350
351
352
353 /***********************************************************************
354 * 'engine' support
355 ***********************************************************************/
356
357 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
358 {
359 switch (engine) {
360 case GLAMO_ENGINE_LCD:
361 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
362 GLAMO_HOSTBUS2_MMIO_EN_LCD,
363 GLAMO_HOSTBUS2_MMIO_EN_LCD);
364 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
365 GLAMO_CLOCK_LCD_EN_M5CLK |
366 GLAMO_CLOCK_LCD_EN_DHCLK |
367 GLAMO_CLOCK_LCD_EN_DMCLK |
368 GLAMO_CLOCK_LCD_EN_DCLK |
369 GLAMO_CLOCK_LCD_DG_M5CLK |
370 GLAMO_CLOCK_LCD_DG_DMCLK);
371 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
372 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
373 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
374 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
375 break;
376 case GLAMO_ENGINE_MMC:
377 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
378 GLAMO_HOSTBUS2_MMIO_EN_MMC,
379 GLAMO_HOSTBUS2_MMIO_EN_MMC);
380 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
381 GLAMO_CLOCK_MMC_EN_M9CLK |
382 GLAMO_CLOCK_MMC_EN_TCLK |
383 GLAMO_CLOCK_MMC_DG_M9CLK |
384 GLAMO_CLOCK_MMC_DG_TCLK,
385 0xffff);
386 /* enable the TCLK divider clk input */
387 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
388 GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
389 GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
390 break;
391 case GLAMO_ENGINE_2D:
392 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
393 GLAMO_CLOCK_2D_EN_M7CLK |
394 GLAMO_CLOCK_2D_EN_GCLK |
395 GLAMO_CLOCK_2D_DG_M7CLK |
396 GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
397 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
398 GLAMO_HOSTBUS2_MMIO_EN_2D,
399 GLAMO_HOSTBUS2_MMIO_EN_2D);
400 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
401 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
402 0xffff);
403 break;
404 case GLAMO_ENGINE_CMDQ:
405 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
406 GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
407 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
408 GLAMO_HOSTBUS2_MMIO_EN_CQ,
409 GLAMO_HOSTBUS2_MMIO_EN_CQ);
410 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
411 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
412 0xffff);
413 break;
414 /* FIXME: Implementation */
415 default:
416 return -EINVAL;
417 }
418
419 glamo->engine_enabled_bitfield |= 1 << engine;
420
421 return 0;
422 }
423
424 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
425 {
426 int ret;
427
428 spin_lock(&glamo->lock);
429
430 ret = __glamo_engine_enable(glamo, engine);
431
432 spin_unlock(&glamo->lock);
433
434 return ret;
435 }
436 EXPORT_SYMBOL_GPL(glamo_engine_enable);
437
438 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
439 {
440 switch (engine) {
441 case GLAMO_ENGINE_LCD:
442 /* remove pixel clock to LCM */
443 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
444 GLAMO_CLOCK_LCD_EN_DCLK, 0);
445 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
446 GLAMO_CLOCK_LCD_EN_DHCLK |
447 GLAMO_CLOCK_LCD_EN_DMCLK, 0);
448 /* kill memory clock */
449 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
450 GLAMO_CLOCK_LCD_EN_M5CLK, 0);
451 /* stop dividing the clocks */
452 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
453 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
454 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
455 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
456 break;
457
458 case GLAMO_ENGINE_MMC:
459 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
460 GLAMO_CLOCK_MMC_EN_M9CLK |
461 GLAMO_CLOCK_MMC_EN_TCLK |
462 GLAMO_CLOCK_MMC_DG_M9CLK |
463 GLAMO_CLOCK_MMC_DG_TCLK, 0);
464 /* disable the TCLK divider clk input */
465 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
466 GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
467 break;
468 case GLAMO_ENGINE_CMDQ:
469 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
470 GLAMO_CLOCK_2D_EN_M6CLK,
471 0);
472 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
473 GLAMO_HOSTBUS2_MMIO_EN_CQ,
474 GLAMO_HOSTBUS2_MMIO_EN_CQ);
475 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
476 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
477 0);*/
478 break;
479 case GLAMO_ENGINE_2D:
480 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
481 GLAMO_CLOCK_2D_EN_M7CLK |
482 GLAMO_CLOCK_2D_EN_GCLK |
483 GLAMO_CLOCK_2D_DG_M7CLK |
484 GLAMO_CLOCK_2D_DG_GCLK,
485 0);
486 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
487 GLAMO_HOSTBUS2_MMIO_EN_2D,
488 GLAMO_HOSTBUS2_MMIO_EN_2D);
489 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
490 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
491 0);
492 break;
493 default:
494 return -EINVAL;
495 }
496
497 glamo->engine_enabled_bitfield &= ~(1 << engine);
498
499 return 0;
500 }
501 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
502 {
503 int ret;
504
505 spin_lock(&glamo->lock);
506
507 ret = __glamo_engine_disable(glamo, engine);
508
509 spin_unlock(&glamo->lock);
510
511 return ret;
512 }
513 EXPORT_SYMBOL_GPL(glamo_engine_disable);
514
515 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
516 [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD,
517 [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC,
518 [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP,
519 [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG,
520 [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D,
521 [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D,
522 [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
523 [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
524 };
525
526 void glamo_engine_clkreg_set(struct glamo_core *glamo,
527 enum glamo_engine engine,
528 u_int16_t mask, u_int16_t val)
529 {
530 reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
531 }
532 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
533
534 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
535 enum glamo_engine engine)
536 {
537 u_int16_t val;
538
539 spin_lock(&glamo->lock);
540 val = __reg_read(glamo, engine_clock_regs[engine]);
541 spin_unlock(&glamo->lock);
542
543 return val;
544 }
545 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
546
547 static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
548 [GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
549 [GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
550 [GLAMO_ENGINE_2D] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
551 };
552
553 void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
554 {
555 uint16_t reg = engine_div_regs[engine].reg;
556 uint16_t bit = engine_div_regs[engine].val;
557 uint16_t val;
558
559 spin_lock(&glamo->lock);
560 val = __reg_read(glamo, reg);
561 __reg_write(glamo, reg, val | bit);
562 spin_unlock(&glamo->lock);
563 mdelay(5);
564 }
565 EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
566
567 void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
568 {
569 uint16_t reg = engine_div_regs[engine].reg;
570 uint16_t bit = engine_div_regs[engine].val;
571 uint16_t val;
572
573 spin_lock(&glamo->lock);
574 val = __reg_read(glamo, reg);
575 __reg_write(glamo, reg, val & ~bit);
576 spin_unlock(&glamo->lock);
577 }
578 EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
579
580 static const struct glamo_script reset_regs[] = {
581 [GLAMO_ENGINE_LCD] = {
582 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
583 },
584 #if 0
585 [GLAMO_ENGINE_HOST] = {
586 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
587 },
588 [GLAMO_ENGINE_MEM] = {
589 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
590 },
591 #endif
592 [GLAMO_ENGINE_MMC] = {
593 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
594 },
595 [GLAMO_ENGINE_CMDQ] = {
596 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
597 },
598 [GLAMO_ENGINE_2D] = {
599 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
600 },
601 [GLAMO_ENGINE_JPEG] = {
602 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
603 },
604 };
605
606 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
607 {
608 uint16_t reg = reset_regs[engine].reg;
609 uint16_t val = reset_regs[engine].val;
610
611 if (engine >= ARRAY_SIZE(reset_regs)) {
612 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
613 return;
614 }
615
616
617 spin_lock(&glamo->lock);
618 __reg_set_bit(glamo, reg, val);
619 __reg_clear_bit(glamo, reg, val);
620 spin_unlock(&glamo->lock);
621 }
622 EXPORT_SYMBOL_GPL(glamo_engine_reset);
623
624 int glamo_pll_rate(struct glamo_core *glamo,
625 enum glamo_pll pll)
626 {
627 u_int16_t reg;
628 unsigned int osci = glamo->pdata->osci_clock_rate;
629
630 switch (pll) {
631 case GLAMO_PLL1:
632 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
633 break;
634 case GLAMO_PLL2:
635 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
636 break;
637 default:
638 return -EINVAL;
639 }
640 return osci*reg;
641 }
642 EXPORT_SYMBOL_GPL(glamo_pll_rate);
643
644 int glamo_engine_reclock(struct glamo_core *glamo,
645 enum glamo_engine engine,
646 int hz)
647 {
648 int pll;
649 u_int16_t reg, mask, div;
650
651 if (!hz)
652 return -EINVAL;
653
654 switch (engine) {
655 case GLAMO_ENGINE_LCD:
656 pll = GLAMO_PLL1;
657 reg = GLAMO_REG_CLOCK_GEN7;
658 mask = 0xff;
659 break;
660 case GLAMO_ENGINE_MMC:
661 pll = GLAMO_PLL1;
662 reg = GLAMO_REG_CLOCK_GEN8;
663 mask = 0xff;
664 break;
665 default:
666 dev_warn(&glamo->pdev->dev,
667 "reclock of engine 0x%x not supported\n", engine);
668 return -EINVAL;
669 break;
670 }
671
672 pll = glamo_pll_rate(glamo, pll);
673
674 div = pll / hz;
675
676 if (div != 0 && pll / div <= hz)
677 --div;
678
679 if (div > mask)
680 div = mask;
681
682 dev_dbg(&glamo->pdev->dev,
683 "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
684
685 reg_set_bit_mask(glamo, reg, mask, div);
686 mdelay(5); /* wait some time to stabilize */
687
688 return pll / (div + 1);
689 }
690 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
691
692 /***********************************************************************
693 * script support
694 ***********************************************************************/
695
696 int glamo_run_script(struct glamo_core *glamo, const struct glamo_script *script,
697 int len, int may_sleep)
698 {
699 int i;
700 const struct glamo_script *line = script;
701
702 for (i = 0; i < len; ++i, ++line) {
703 switch (line->reg) {
704 case 0xffff:
705 return 0;
706 case 0xfffe:
707 if (may_sleep)
708 msleep(line->val);
709 else
710 mdelay(line->val * 4);
711 break;
712 case 0xfffd:
713 /* spin until PLLs lock */
714 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
715 ;
716 break;
717
718 /*
719 * couple of people reported artefacts with 2.6.28 changes, this
720 * allows reversion to 2.6.24 settings
721 */
722
723 case 0x200:
724 switch (slow_memory) {
725 /* choice 1 is the most conservative */
726 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
727 __reg_write(glamo, script[i].reg, 0xef0);
728 break;
729 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
730 __reg_write(glamo, script[i].reg, 0xea0);
731 break;
732 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
733 __reg_write(glamo, script[i].reg, 0xe50);
734 break;
735 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
736 __reg_write(glamo, script[i].reg, 0xe00);
737 break;
738
739 /* using PLL2 for memory bus increases CPU bandwidth significantly */
740 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
741 __reg_write(glamo, script[i].reg, 0xef3);
742 break;
743 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
744 __reg_write(glamo, script[i].reg, 0xea3);
745 break;
746 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
747 __reg_write(glamo, script[i].reg, 0xe53);
748 break;
749 /* default of 0 or >7 is fastest */
750 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
751 __reg_write(glamo, script[i].reg, 0xe03);
752 break;
753 }
754 break;
755
756 default:
757 __reg_write(glamo, script[i].reg, script[i].val);
758 break;
759 }
760 }
761
762 return 0;
763 }
764 EXPORT_SYMBOL(glamo_run_script);
765
766 static const struct glamo_script glamo_init_script[] = {
767 { GLAMO_REG_CLOCK_HOST, 0x1000 },
768 { 0xfffe, 2 },
769 { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
770 { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
771 { GLAMO_REG_CLOCK_LCD, 0x1000 },
772 { GLAMO_REG_CLOCK_MMC, 0x1000 },
773 { GLAMO_REG_CLOCK_ISP, 0x1000 },
774 { GLAMO_REG_CLOCK_ISP, 0x3000 },
775 { GLAMO_REG_CLOCK_JPEG, 0x1000 },
776 { GLAMO_REG_CLOCK_3D, 0x1000 },
777 { GLAMO_REG_CLOCK_3D, 0x3000 },
778 { GLAMO_REG_CLOCK_2D, 0x1000 },
779 { GLAMO_REG_CLOCK_2D, 0x3000 },
780 { GLAMO_REG_CLOCK_RISC1, 0x1000 },
781 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
782 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
783 { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
784 { 0xfffe, 2 },
785 { GLAMO_REG_CLOCK_HOST, 0x0000 },
786 { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
787 { GLAMO_REG_CLOCK_LCD, 0x0000 },
788 { GLAMO_REG_CLOCK_MMC, 0x0000 },
789 #if 0
790 /* unused engines must be left in reset to stop MMC block read "blackouts" */
791 { GLAMO_REG_CLOCK_ISP, 0x0000 },
792 { GLAMO_REG_CLOCK_ISP, 0x0000 },
793 { GLAMO_REG_CLOCK_JPEG, 0x0000 },
794 { GLAMO_REG_CLOCK_3D, 0x0000 },
795 { GLAMO_REG_CLOCK_3D, 0x0000 },
796 { GLAMO_REG_CLOCK_2D, 0x0000 },
797 { GLAMO_REG_CLOCK_2D, 0x0000 },
798 { GLAMO_REG_CLOCK_RISC1, 0x0000 },
799 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
800 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
801 #endif
802 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
803 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
804 { 0xfffd, 0 },
805 /*
806 * b9 of this register MUST be zero to get any interrupts on INT#
807 * the other set bits enable all the engine interrupt sources
808 */
809 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
810 { GLAMO_REG_CLOCK_GEN6, 0x2000 },
811 { GLAMO_REG_CLOCK_GEN7, 0x0101 },
812 { GLAMO_REG_CLOCK_GEN8, 0x0100 },
813 { GLAMO_REG_CLOCK_HOST, 0x000d },
814 /*
815 * b7..b4 = 0 = no wait states on read or write
816 * b0 = 1 select PLL2 for Host interface, b1 = enable it
817 */
818 { 0x200, 0x0e03 /* this is replaced by script parser */ },
819 { 0x202, 0x07ff },
820 { 0x212, 0x0000 },
821 { 0x214, 0x4000 },
822 { 0x216, 0xf00e },
823
824 /* S-Media recommended "set tiling mode to 512 mode for memory access
825 * more efficiency when 640x480" */
826 { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
827 { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
828
829 { GLAMO_REGOFS_HOSTBUS + 2, 0xffff }, /* enable on MMIO*/
830
831 { GLAMO_REG_MEM_TIMING1, 0x0108 },
832 { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
833 { GLAMO_REG_MEM_TIMING3, 0x0000 },
834 { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
835 { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
836 { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
837 { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
838 { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
839 { GLAMO_REG_MEM_TIMING9, 0x6006 },
840 { GLAMO_REG_MEM_TIMING10, 0x00ff },
841 { GLAMO_REG_MEM_TIMING11, 0x0001 },
842 { GLAMO_REG_MEM_POWER1, 0x0020 },
843 { GLAMO_REG_MEM_POWER2, 0x0000 },
844 { GLAMO_REG_MEM_DRAM1, 0x0000 },
845 { 0xfffe, 1 },
846 { GLAMO_REG_MEM_DRAM1, 0xc100 },
847 { 0xfffe, 1 },
848 { GLAMO_REG_MEM_DRAM1, 0xe100 },
849 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
850 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
851 };
852 #if 0
853 static struct glamo_script glamo_resume_script[] = {
854
855 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
856 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
857 { GLAMO_REG_DFT_GEN6, 1 },
858 { 0xfffe, 100 },
859 { 0xfffd, 0 },
860 { 0x200, 0x0e03 },
861
862 /*
863 * b9 of this register MUST be zero to get any interrupts on INT#
864 * the other set bits enable all the engine interrupt sources
865 */
866 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
867 { GLAMO_REG_CLOCK_HOST, 0x0018 },
868 { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
869
870 { GLAMO_REG_MEM_DRAM1, 0x0000 },
871 { 0xfffe, 1 },
872 { GLAMO_REG_MEM_DRAM1, 0xc100 },
873 { 0xfffe, 1 },
874 { GLAMO_REG_MEM_DRAM1, 0xe100 },
875 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
876 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
877 };
878 #endif
879
880 enum glamo_power {
881 GLAMO_POWER_ON,
882 GLAMO_POWER_SUSPEND,
883 };
884
885 static void glamo_power(struct glamo_core *glamo,
886 enum glamo_power new_state)
887 {
888 int n;
889 unsigned long flags;
890
891 spin_lock_irqsave(&glamo->lock, flags);
892
893 dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
894
895 /*
896 Power management
897 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
898 {
899 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
900 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
901 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
902 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
903 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
904 };
905
906 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
907 {
908 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
909 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
910 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
911 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
912 };
913
914 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
915 {
916 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
917 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
918 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
919 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
920 };
921 */
922
923 switch (new_state) {
924 case GLAMO_POWER_ON:
925
926 /*
927 * glamo state on resume is nondeterministic in some
928 * fundamental way, it has also been observed that the
929 * Glamo reset pin can get asserted by, eg, touching it with
930 * a scope probe. So the only answer is to roll with it and
931 * force an external reset on the Glamo during resume.
932 */
933
934 (glamo->pdata->glamo_external_reset)(0);
935 udelay(10);
936 (glamo->pdata->glamo_external_reset)(1);
937 mdelay(5);
938
939 glamo_run_script(glamo, glamo_init_script,
940 ARRAY_SIZE(glamo_init_script), 0);
941
942 break;
943
944 case GLAMO_POWER_SUSPEND:
945
946 /* nuke interrupts */
947 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
948
949 /* stash a copy of which engines were running */
950 glamo->engine_enabled_bitfield_suspend =
951 glamo->engine_enabled_bitfield;
952
953 /* take down each engine before we kill mem and pll */
954 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
955 if (glamo->engine_enabled_bitfield & (1 << n))
956 __glamo_engine_disable(glamo, n);
957
958 /* enable self-refresh */
959
960 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
961 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
962 GLAMO_MEM_DRAM1_EN_GATE_CKE |
963 GLAMO_MEM_DRAM1_SELF_REFRESH |
964 GLAMO_MEM_REFRESH_COUNT);
965 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
966 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
967 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
968 GLAMO_MEM_DRAM1_EN_GATE_CKE |
969 GLAMO_MEM_DRAM1_SELF_REFRESH |
970 GLAMO_MEM_REFRESH_COUNT);
971
972 /* force RAM into deep powerdown */
973
974 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
975 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
976 (7 << 6) | /* tRC */
977 (1 << 4) | /* tRP */
978 (1 << 2) | /* tRCD */
979 2); /* CAS latency */
980
981 /* disable clocks to memory */
982 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
983
984 /* all dividers from OSCI */
985 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
986
987 /* PLL2 into bypass */
988 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
989
990 __reg_write(glamo, 0x200, 0x0e00);
991
992
993 /* kill PLLS 1 then 2 */
994 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
995 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
996
997 break;
998 }
999
1000 spin_unlock_irqrestore(&glamo->lock, flags);
1001 }
1002
1003 #if 0
1004 #define MEMDETECT_RETRY 6
1005 static unsigned int detect_memsize(struct glamo_core *glamo)
1006 {
1007 int i;
1008
1009 /*static const u_int16_t pattern[] = {
1010 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1011 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1012 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1013 0x7777, 0x2a2a, 0x8888, 0x1a1a
1014 }; */
1015
1016 for (i = 0; i < MEMDETECT_RETRY; i++) {
1017 switch (glamo->type) {
1018 case 3600:
1019 __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1020 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1021 break;
1022 case 3650:
1023 switch (glamo->revision) {
1024 case GLAMO_CORE_REV_A0:
1025 if (i & 1)
1026 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1027 0x097a);
1028 else
1029 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1030 0x0173);
1031
1032 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1033 msleep(1);
1034 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1035 break;
1036 default:
1037 if (i & 1)
1038 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1039 0x0972);
1040 else
1041 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1042 0x0872);
1043
1044 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1045 msleep(1);
1046 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1047 break;
1048 }
1049 break;
1050 case 3700:
1051 /* FIXME */
1052 default:
1053 break;
1054 }
1055
1056 #if 0
1057 /* FIXME: finish implementation */
1058 for (j = 0; j < 8; j++) {
1059 __
1060 #endif
1061 }
1062
1063 return 0;
1064 }
1065 #endif
1066
1067 /* Find out if we can support this version of the Glamo chip */
1068 static int glamo_supported(struct glamo_core *glamo)
1069 {
1070 u_int16_t dev_id, rev_id; /*, memsize; */
1071
1072 dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1073 rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1074
1075 switch (dev_id) {
1076 case 0x3650:
1077 switch (rev_id) {
1078 case GLAMO_CORE_REV_A2:
1079 break;
1080 case GLAMO_CORE_REV_A0:
1081 case GLAMO_CORE_REV_A1:
1082 case GLAMO_CORE_REV_A3:
1083 dev_warn(&glamo->pdev->dev, "untested core revision "
1084 "%04x, your mileage may vary\n", rev_id);
1085 break;
1086 default:
1087 dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1088 "%04x, your mileage may vary\n", rev_id);
1089 /* maybe should abort ? */
1090 }
1091 break;
1092 case 0x3600:
1093 case 0x3700:
1094 default:
1095 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1096 dev_id);
1097 return 0;
1098 }
1099
1100 dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1101 "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1102 glamo_pll_rate(glamo, GLAMO_PLL1),
1103 glamo_pll_rate(glamo, GLAMO_PLL2));
1104
1105 return 1;
1106 }
1107
1108 static int __init glamo_probe(struct platform_device *pdev)
1109 {
1110 int rc = 0, irq;
1111 struct glamo_core *glamo;
1112
1113 glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1114 if (!glamo)
1115 return -ENOMEM;
1116
1117 spin_lock_init(&glamo->lock);
1118 glamo->pdev = pdev;
1119 glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 glamo->irq = platform_get_irq(pdev, 0);
1121 glamo->pdata = pdev->dev.platform_data;
1122 if (!glamo->mem || !glamo->pdata) {
1123 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1124 rc = -ENOENT;
1125 goto bail_free;
1126 }
1127
1128 /* register a number of sibling devices whoise IOMEM resources
1129 * are siblings of pdev's IOMEM resource */
1130
1131 /* only remap the generic, hostbus and memory controller registers */
1132 glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1133 if (!glamo->base) {
1134 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1135 goto bail_free;
1136 }
1137
1138 platform_set_drvdata(pdev, glamo);
1139
1140 (glamo->pdata->glamo_external_reset)(0);
1141 udelay(10);
1142 (glamo->pdata->glamo_external_reset)(1);
1143 mdelay(10);
1144
1145 /*
1146 * finally set the mfd interrupts up
1147 * can't do them earlier or sibling probes blow up
1148 */
1149
1150 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1151 set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
1152 set_irq_flags(irq, IRQF_VALID);
1153 set_irq_chip_data(irq, glamo);
1154 }
1155
1156 if (glamo->pdata->glamo_irq_is_wired &&
1157 !glamo->pdata->glamo_irq_is_wired()) {
1158 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1159 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1160 set_irq_chip_data(glamo->irq, glamo);
1161 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1162 glamo->irq_works = 1;
1163 } else {
1164 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1165 glamo->irq_works = 0;
1166 }
1167
1168 /* confirm it isn't insane version */
1169 if (!glamo_supported(glamo)) {
1170 dev_err(&pdev->dev, "This Glamo is not supported\n");
1171 goto bail_irq;
1172 }
1173
1174 /* sysfs */
1175 rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1176 if (rc < 0) {
1177 dev_err(&pdev->dev, "cannot create sysfs group\n");
1178 goto bail_irq;
1179 }
1180
1181 /* init the chip with canned register set */
1182
1183 dev_dbg(&glamo->pdev->dev, "running init script\n");
1184 glamo_run_script(glamo, glamo_init_script,
1185 ARRAY_SIZE(glamo_init_script), 1);
1186
1187 dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1188 glamo_pll_rate(glamo, GLAMO_PLL1),
1189 glamo_pll_rate(glamo, GLAMO_PLL2));
1190
1191 /* register siblings */
1192 glamo->pdata->mmc_data->core = glamo;
1193 glamo_cells[GLAMO_CELL_MMC].platform_data = glamo->pdata->mmc_data;
1194 glamo_cells[GLAMO_CELL_MMC].data_size =
1195 sizeof(struct glamo_mmc_platform_data);
1196
1197 glamo->pdata->fb_data->core = glamo;
1198 glamo_cells[GLAMO_CELL_FB].platform_data = glamo->pdata->fb_data;
1199 glamo_cells[GLAMO_CELL_FB].data_size = sizeof(struct glamo_fb_platform_data);
1200
1201 mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1202 ARRAY_SIZE(glamo_cells),
1203 glamo->mem, 0);
1204
1205 /* only request the generic, hostbus and memory controller MMIO */
1206 glamo->mem = request_mem_region(glamo->mem->start,
1207 GLAMO_REGOFS_VIDCAP, "glamo-core");
1208 if (!glamo->mem) {
1209 dev_err(&pdev->dev, "failed to request memory region\n");
1210 goto bail_irq;
1211 }
1212
1213 return 0;
1214
1215 bail_irq:
1216 disable_irq(glamo->irq);
1217 set_irq_chained_handler(glamo->irq, NULL);
1218 set_irq_chip_data(glamo->irq, NULL);
1219
1220 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1221 set_irq_flags(irq, 0);
1222 set_irq_chip(irq, NULL);
1223 set_irq_chip_data(irq, NULL);
1224 }
1225
1226 iounmap(glamo->base);
1227 bail_free:
1228 platform_set_drvdata(pdev, NULL);
1229 kfree(glamo);
1230
1231 return rc;
1232 }
1233
1234 static int glamo_remove(struct platform_device *pdev)
1235 {
1236 struct glamo_core *glamo = platform_get_drvdata(pdev);
1237 int irq;
1238
1239 disable_irq(glamo->irq);
1240 set_irq_chained_handler(glamo->irq, NULL);
1241 set_irq_chip_data(glamo->irq, NULL);
1242
1243 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1244 set_irq_flags(irq, 0);
1245 set_irq_chip(irq, NULL);
1246 set_irq_chip_data(irq, NULL);
1247 }
1248
1249 platform_set_drvdata(pdev, NULL);
1250 mfd_remove_devices(&pdev->dev);
1251 iounmap(glamo->base);
1252 release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1253 kfree(glamo);
1254
1255 return 0;
1256 }
1257
1258 #ifdef CONFIG_PM
1259
1260 static int glamo_suspend(struct device *dev)
1261 {
1262 struct glamo_core *glamo = dev_get_drvdata(dev);
1263 glamo->suspending = 1;
1264 glamo_power(glamo, GLAMO_POWER_SUSPEND);
1265
1266 return 0;
1267 }
1268
1269 static int glamo_resume(struct device *dev)
1270 {
1271 struct glamo_core *glamo = dev_get_drvdata(dev);
1272 glamo_power(glamo, GLAMO_POWER_ON);
1273 glamo->suspending = 0;
1274 return 0;
1275 }
1276
1277 static struct dev_pm_ops glamo_pm_ops = {
1278 .suspend = glamo_suspend,
1279 .resume = glamo_resume,
1280 };
1281
1282 #define GLAMO_PM_OPS (&glamo_pm_ops)
1283
1284 #else
1285 #define GLAMO_PM_OPS NULL
1286 #endif
1287
1288 static struct platform_driver glamo_driver = {
1289 .probe = glamo_probe,
1290 .remove = glamo_remove,
1291 .driver = {
1292 .name = "glamo3362",
1293 .owner = THIS_MODULE,
1294 .pm = GLAMO_PM_OPS,
1295 },
1296 };
1297
1298 static int __devinit glamo_init(void)
1299 {
1300 return platform_driver_register(&glamo_driver);
1301 }
1302
1303 static void __exit glamo_cleanup(void)
1304 {
1305 platform_driver_unregister(&glamo_driver);
1306 }
1307
1308 module_init(glamo_init);
1309 module_exit(glamo_cleanup);
1310
1311 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1312 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1313 MODULE_LICENSE("GPL");
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