target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-mci.c

   1 /*
   2  *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
   3  *
   4  *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
   5  *  Based on S3C MMC driver that was:
   6  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mmc/mmc.h>
  15 #include <linux/mmc/sd.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/irq.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/workqueue.h>
  22 #include <linux/crc7.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/io.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/mfd/glamo.h>
  27
  28 #include "glamo-core.h"
  29 #include "glamo-regs.h"
  30
  31 #define DRIVER_NAME "glamo-mci"
  32
  33 struct glamo_mci_host {
  34         struct platform_device *pdev;
  35         struct glamo_mmc_platform_data *pdata;
  36         struct mmc_host        *mmc;
  37         struct resource        *mmio_mem;
  38         struct resource        *data_mem;
  39         void __iomem           *mmio_base;
  40         u16 __iomem            *data_base;
  41
  42         struct regulator *regulator;
  43         struct mmc_request *mrq;
  44
  45         unsigned int clk_rate;
  46
  47         unsigned short vdd;
  48         char           power_mode;
  49
  50         unsigned char request_counter;
  51
  52         struct timer_list disable_timer;
  53
  54         struct work_struct irq_work;
  55         struct work_struct read_work;
  56
  57         unsigned clk_enabled : 1;
  58 };
  59
  60 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request* mrq);
  61 static void glamo_mci_send_command(struct glamo_mci_host *host,
  62                                   struct mmc_command *cmd);
  63
  64 /*
  65  * Max SD clock rate
  66  *
  67  * held at /(3 + 1) due to concerns of 100R recommended series resistor
  68  * allows 16MHz @ 4-bit --> 8MBytes/sec raw
  69  *
  70  * you can override this on kernel commandline using
  71  *
  72  *   glamo_mci.sd_max_clk=10000000
  73  *
  74  * for example
  75  */
  76
  77 static int sd_max_clk = 21000000;
  78 module_param(sd_max_clk, int, 0644);
  79
  80 /*
  81  * Slow SD clock rate
  82  *
  83  * you can override this on kernel commandline using
  84  *
  85  *   glamo_mci.sd_slow_ratio=8
  86  *
  87  * for example
  88  *
  89  * platform callback is used to decide effective clock rate, if not
  90  * defined then max is used, if defined and returns nonzero, rate is
  91  * divided by this factor
  92  */
  93
  94 static int sd_slow_ratio = 8;
  95 module_param(sd_slow_ratio, int, 0644);
  96
  97 /*
  98  * Post-power SD clock rate
  99  *
 100  * you can override this on kernel commandline using
 101  *
 102  *   glamo_mci.sd_post_power_clock=1000000
 103  *
 104  * for example
 105  *
 106  * After changing power to card, clock is held at this rate until first bulk
 107  * transfer completes
 108  */
 109
 110 static int sd_post_power_clock = 1000000;
 111 module_param(sd_post_power_clock, int, 0644);
 112
 113
 114 static inline void glamo_reg_write(struct glamo_mci_host *glamo,
 115                                 u_int16_t reg, u_int16_t val)
 116 {
 117         writew(val, glamo->mmio_base + reg);
 118 }
 119
 120 static inline u_int16_t glamo_reg_read(struct glamo_mci_host *glamo,
 121                                    u_int16_t reg)
 122 {
 123         return readw(glamo->mmio_base + reg);
 124 }
 125
 126 static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
 127                                 u_int16_t reg, u_int16_t mask,
 128                                 u_int16_t val)
 129 {
 130         u_int16_t tmp;
 131
 132         val &= mask;
 133
 134         tmp = glamo_reg_read(glamo, reg);
 135         tmp &= ~mask;
 136         tmp |= val;
 137         glamo_reg_write(glamo, reg, tmp);
 138 }
 139
 140 static void glamo_mci_clock_disable(struct glamo_mci_host *host) {
 141         if (host->clk_enabled) {
 142                 glamo_engine_div_disable(host->pdata->core, GLAMO_ENGINE_MMC);
 143                 host->clk_enabled = 0;
 144         }
 145 }
 146
 147 static void glamo_mci_clock_enable(struct glamo_mci_host *host) {
 148         del_timer_sync(&host->disable_timer);
 149
 150         if (!host->clk_enabled) {
 151                 glamo_engine_div_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 152                 host->clk_enabled = 1;
 153         }
 154 }
 155
 156 static void glamo_mci_disable_timer(unsigned long data) {
 157         struct glamo_mci_host *host = (struct glamo_mci_host *)data;
 158         glamo_mci_clock_disable(host);
 159 }
 160
 161
 162 static void do_pio_read(struct glamo_mci_host *host, struct mmc_data *data)
 163 {
 164         struct scatterlist *sg;
 165         u16 __iomem *from_ptr = host->data_base;
 166         void *sg_pointer;
 167
 168         dev_dbg(&host->pdev->dev, "pio_read():\n");
 169         for (sg = data->sg; sg; sg = sg_next(sg)) {
 170                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 171
 172
 173                 memcpy(sg_pointer, from_ptr, sg->length);
 174                 from_ptr += sg->length >> 1;
 175
 176                 data->bytes_xfered += sg->length;
 177         }
 178
 179         dev_dbg(&host->pdev->dev, "pio_read(): "
 180                         "complete (no more data).\n");
 181 }
 182
 183 static void do_pio_write(struct glamo_mci_host *host, struct mmc_data *data)
 184 {
 185         struct scatterlist *sg;
 186         u16 __iomem *to_ptr = host->data_base;
 187         void *sg_pointer;
 188
 189         dev_dbg(&host->pdev->dev, "pio_write():\n");
 190         for (sg = data->sg; sg; sg = sg_next(sg)) {
 191                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 192
 193                 data->bytes_xfered += sg->length;
 194
 195                 memcpy(to_ptr, sg_pointer, sg->length);
 196                 to_ptr += sg->length >> 1;
 197         }
 198
 199         dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
 200 }
 201
 202 static int glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq)
 203 {
 204         int real_rate = 0;
 205
 206         if (freq) {
 207                 glamo_mci_clock_enable(host);
 208                 real_rate = glamo_engine_reclock(host->pdata->core, GLAMO_ENGINE_MMC, freq);
 209         } else {
 210                 glamo_mci_clock_disable(host);
 211         }
 212
 213         return real_rate;
 214 }
 215
 216 static void glamo_mci_request_done(struct glamo_mci_host *host, struct
 217 mmc_request *mrq) {
 218         mod_timer(&host->disable_timer, jiffies + HZ / 16);
 219         mmc_request_done(host->mmc, mrq);
 220 }
 221
 222
 223 static void glamo_mci_irq_worker(struct work_struct *work)
 224 {
 225         struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
 226                                                                                                 irq_work);
 227         struct mmc_command *cmd;
 228         uint16_t status;
 229         if (!host->mrq || !host->mrq->cmd)
 230                 return;
 231
 232         cmd = host->mrq->cmd;
 233
 234 #if 0
 235         if (cmd->data->flags & MMC_DATA_READ) {
 236                 return;
 237         }
 238 #endif
 239
 240         status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 241         dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
 242
 243         /* we ignore a data timeout report if we are also told the data came */
 244         if (status & GLAMO_STAT1_MMC_RB_DRDY)
 245                 status &= ~GLAMO_STAT1_MMC_DTOUT;
 246
 247         if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
 248                 cmd->error = -ETIMEDOUT;
 249         if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) {
 250                 cmd->error = -EILSEQ;
 251         }
 252         if (cmd->error) {
 253                 dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
 254                 goto done;
 255         }
 256
 257         /* issue STOP if we have been given one to use */
 258         if (host->mrq->stop) {
 259                 glamo_mci_send_command(host, host->mrq->stop);
 260         }
 261
 262         if (cmd->data->flags & MMC_DATA_READ)
 263                 do_pio_read(host, cmd->data);
 264
 265 done:
 266         host->mrq = NULL;
 267         glamo_mci_request_done(host, cmd->mrq);
 268 }
 269
 270 static void glamo_mci_read_worker(struct work_struct *work)
 271 {
 272         struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
 273                                                                                                 read_work);
 274         struct mmc_command *cmd;
 275         uint16_t status;
 276         uint16_t blocks_ready;
 277         size_t data_read = 0;
 278         size_t data_ready;
 279         struct scatterlist *sg;
 280         u16 __iomem *from_ptr = host->data_base;
 281         void *sg_pointer;
 282
 283
 284         cmd = host->mrq->cmd;
 285         sg = cmd->data->sg;
 286         do {
 287                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 288
 289                 if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
 290                         cmd->error = -ETIMEDOUT;
 291                 if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR))
 292                         cmd->error = -EILSEQ;
 293                 if (cmd->error) {
 294                         dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
 295                         goto done;
 296                 }
 297
 298                 blocks_ready = glamo_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
 299                 data_ready = blocks_ready * cmd->data->blksz;
 300
 301                 if (data_ready == data_read)
 302                         yield();
 303
 304                 while(sg && data_read + sg->length <= data_ready) {
 305                         sg_pointer = page_address(sg_page(sg)) + sg->offset;
 306                         memcpy(sg_pointer, from_ptr, sg->length);
 307                         from_ptr += sg->length >> 1;
 308
 309                         data_read += sg->length;
 310                         sg = sg_next(sg);
 311                 }
 312
 313         } while(sg);
 314         cmd->data->bytes_xfered = data_read;
 315
 316         do {
 317                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 318         } while (!(status & GLAMO_STAT1_MMC_IDLE));
 319
 320         if (host->mrq->stop)
 321                 glamo_mci_send_command(host, host->mrq->stop);
 322
 323         do {
 324                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 325         } while (!(status & GLAMO_STAT1_MMC_IDLE));
 326 done:
 327         host->mrq = NULL;
 328         glamo_mci_request_done(host, cmd->mrq);
 329 }
 330
 331 static irqreturn_t glamo_mci_irq(int irq, void *devid)
 332 {
 333         struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
 334         schedule_work(&host->irq_work);
 335
 336         return IRQ_HANDLED;
 337 }
 338
 339 static void glamo_mci_send_command(struct glamo_mci_host *host,
 340                                   struct mmc_command *cmd)
 341 {
 342         u8 u8a[6];
 343         u16 fire = 0;
 344         unsigned int timeout = 1000000;
 345         u16 * reg_resp = (u16 *)(host->mmio_base + GLAMO_REG_MMC_CMD_RSP1);
 346         u16 status;
 347         int triggers_int = 1;
 348
 349         /* if we can't do it, reject as busy */
 350         if (!glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
 351                  GLAMO_STAT1_MMC_IDLE) {
 352                 cmd->error = -EBUSY;
 353                 return;
 354         }
 355
 356         /* create an array in wire order for CRC computation */
 357         u8a[0] = 0x40 | (cmd->opcode & 0x3f);
 358         u8a[1] = (u8)(cmd->arg >> 24);
 359         u8a[2] = (u8)(cmd->arg >> 16);
 360         u8a[3] = (u8)(cmd->arg >> 8);
 361         u8a[4] = (u8)cmd->arg;
 362         u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01; /* crc7 on first 5 bytes of packet */
 363
 364         /* issue the wire-order array including CRC in register order */
 365         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
 366         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
 367         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
 368
 369         /* command index toggle */
 370         fire |= (host->request_counter & 1) << 12;
 371
 372         /* set type of command */
 373         switch (mmc_cmd_type(cmd)) {
 374         case MMC_CMD_BC:
 375                 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
 376                 break;
 377         case MMC_CMD_BCR:
 378                 fire |= GLAMO_FIRE_MMC_CMDT_BR;
 379                 break;
 380         case MMC_CMD_AC:
 381                 fire |= GLAMO_FIRE_MMC_CMDT_AND;
 382                 break;
 383         case MMC_CMD_ADTC:
 384                 fire |= GLAMO_FIRE_MMC_CMDT_AD;
 385                 break;
 386         }
 387         /*
 388          * if it expects a response, set the type expected
 389          *
 390          * R1, Length  : 48bit, Normal response
 391          * R1b, Length : 48bit, same R1, but added card busy status
 392          * R2, Length  : 136bit (really 128 bits with CRC snipped)
 393          * R3, Length  : 48bit (OCR register value)
 394          * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
 395          * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
 396          * R6, Length  : 48bit (RCA register)
 397          * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
 398          *                     check pattern, CRC7)
 399          */
 400         switch (mmc_resp_type(cmd)) {
 401         case MMC_RSP_R1: /* same index as R6 and R7 */
 402                 fire |= GLAMO_FIRE_MMC_RSPT_R1;
 403                 break;
 404         case MMC_RSP_R1B:
 405                 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
 406                 break;
 407         case MMC_RSP_R2:
 408                 fire |= GLAMO_FIRE_MMC_RSPT_R2;
 409                 break;
 410         case MMC_RSP_R3:
 411                 fire |= GLAMO_FIRE_MMC_RSPT_R3;
 412                 break;
 413         /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
 414         }
 415         /*
 416          * From the command index, set up the command class in the host ctrllr
 417          *
 418          * missing guys present on chip but couldn't figure out how to use yet:
 419          *     0x0 "stream read"
 420          *     0x9 "cancel running command"
 421          */
 422         switch (cmd->opcode) {
 423         case MMC_READ_SINGLE_BLOCK:
 424                 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
 425                 break;
 426         case MMC_SWITCH: /* 64 byte payload */
 427         case SD_APP_SEND_SCR:
 428         case MMC_READ_MULTIPLE_BLOCK:
 429                 /* we will get an interrupt off this */
 430                 if (!cmd->mrq->stop)
 431                         /* multiblock no stop */
 432                         fire |= GLAMO_FIRE_MMC_CC_MBRNS;
 433                 else
 434                          /* multiblock with stop */
 435                         fire |= GLAMO_FIRE_MMC_CC_MBRS;
 436                 break;
 437         case MMC_WRITE_BLOCK:
 438                 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
 439                 break;
 440         case MMC_WRITE_MULTIPLE_BLOCK:
 441                 if (cmd->mrq->stop)
 442                          /* multiblock with stop */
 443                         fire |= GLAMO_FIRE_MMC_CC_MBWS;
 444                 else
 445                          /* multiblock NO stop-- 'RESERVED'? */
 446                         fire |= GLAMO_FIRE_MMC_CC_MBWNS;
 447                 break;
 448         case MMC_STOP_TRANSMISSION:
 449                 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
 450                 triggers_int = 0;
 451                 break;
 452         default:
 453                 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
 454                 triggers_int = 0;
 455                 break;
 456         }
 457
 458         if (cmd->data)
 459                 host->mrq = cmd->mrq;
 460
 461         /* always largest timeout */
 462         glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
 463
 464         /* Generate interrupt on txfer */
 465         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
 466                         0x0800 |
 467                         GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
 468                         GLAMO_BASIC_MMC_EN_COMPL_INT |
 469                         GLAMO_BASIC_MMC_EN_DATA_PUPS |
 470                         GLAMO_BASIC_MMC_EN_CMD_PUP);
 471
 472         /* send the command out on the wire */
 473         /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
 474         glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
 475
 476         /* we are deselecting card?  because it isn't going to ack then... */
 477         if ((cmd->opcode == 7) && (cmd->arg == 0))
 478                 return;
 479
 480         /*
 481          * we must spin until response is ready or timed out
 482          * -- we don't get interrupts unless there is a bulk rx
 483          */
 484         do
 485                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 486         while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
 487                 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
 488                                  GLAMO_STAT1_MMC_RTOUT |
 489                                  GLAMO_STAT1_MMC_DTOUT |
 490                                  GLAMO_STAT1_MMC_BWERR |
 491                                  GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
 492
 493         if ((status & (GLAMO_STAT1_MMC_RTOUT |
 494                                    GLAMO_STAT1_MMC_DTOUT)) ||
 495                 (timeout == 0)) {
 496                 cmd->error = -ETIMEDOUT;
 497         } else if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) {
 498                 cmd->error = -EILSEQ;
 499         }
 500
 501         if (cmd->flags & MMC_RSP_PRESENT) {
 502                 if (cmd->flags & MMC_RSP_136) {
 503                         cmd->resp[3] = readw(&reg_resp[0]) |
 504                                                    (readw(&reg_resp[1]) << 16);
 505                         cmd->resp[2] = readw(&reg_resp[2]) |
 506                                                    (readw(&reg_resp[3]) << 16);
 507                         cmd->resp[1] = readw(&reg_resp[4]) |
 508                                                    (readw(&reg_resp[5]) << 16);
 509                         cmd->resp[0] = readw(&reg_resp[6]) |
 510                                                    (readw(&reg_resp[7]) << 16);
 511                 } else {
 512                         cmd->resp[0] = (readw(&reg_resp[0]) >> 8) |
 513                                                    (readw(&reg_resp[1]) << 8) |
 514                                                    ((readw(&reg_resp[2])) << 24);
 515                 }
 516         }
 517
 518 #if 0
 519         /* We'll only get an interrupt when all data has been transfered.
 520            By starting to copy data when it's avaiable we can increase throughput by
 521            up to 30%. */
 522         if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
 523                 schedule_work(&host->read_work);
 524 #endif
 525
 526 }
 527
 528 static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
 529                                  struct mmc_data *data)
 530 {
 531         /* set up the block info */
 532         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
 533         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
 534
 535         data->bytes_xfered = 0;
 536
 537         /* if write, prep the write into the shared RAM before the command */
 538         if (data->flags & MMC_DATA_WRITE) {
 539                 do_pio_write(host, data);
 540         }
 541
 542         dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
 543                                    data->blksz, data->blocks);
 544         return 0;
 545 }
 546
 547 static int glamo_mci_irq_poll(struct glamo_mci_host *host,
 548                                 struct mmc_command *cmd)
 549 {
 550         int timeout = 1000000;
 551         /*
 552          * if the glamo INT# line isn't wired (*cough* it can happen)
 553          * I'm afraid we have to spin on the IRQ status bit and "be
 554          * our own INT# line"
 555          */
 556         /*
 557          * we have faith we will get an "interrupt"...
 558          * but something insane like suspend problems can mean
 559          * we spin here forever, so we timeout after a LONG time
 560          */
 561         while ((!(readw(host->pdata->core->base +
 562                  GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
 563                    (timeout--));
 564
 565         if (timeout < 0) {
 566                 if (cmd->data->error)
 567                         cmd->data->error = -ETIMEDOUT;
 568                 dev_err(&host->pdev->dev, "Payload timeout\n");
 569                 return -ETIMEDOUT;
 570         }
 571         /* ack this interrupt source */
 572         writew(GLAMO_IRQ_MMC, host->pdata->core->base +
 573                    GLAMO_REG_IRQ_CLEAR);
 574
 575         /* yay we are an interrupt controller! -- call the ISR
 576          * it will stop clock to card
 577          */
 578         glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 579
 580         return 0;
 581 }
 582
 583 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request *mrq)
 584 {
 585         struct glamo_mci_host *host = mmc_priv(mmc);
 586         struct mmc_command *cmd = mrq->cmd;
 587
 588         glamo_mci_clock_enable(host);
 589         host->request_counter++;
 590         if (cmd->data) {
 591                 if(glamo_mci_prepare_pio(host, cmd->data)) {
 592                         cmd->error = -EIO;
 593                         cmd->data->error = -EIO;
 594                         goto done;
 595                 }
 596         }
 597
 598         dev_dbg(&host->pdev->dev,"cmd 0x%x, "
 599                  "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
 600                  cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
 601                  cmd->flags);
 602
 603         glamo_mci_send_command(host, cmd);
 604
 605         /*
 606          * if we don't have bulk data to take care of, we're done
 607          */
 608         if (!cmd->data || cmd->error)
 609                 goto done;
 610
 611
 612         if (!host->pdata->core->irq_works) {
 613                 if (glamo_mci_irq_poll(host, mrq->cmd))
 614                         goto done;
 615         }
 616
 617         /*
 618          * Otherwise can can use the interrupt as async completion --
 619          * if there is read data coming, or we wait for write data to complete,
 620          * exit without mmc_request_done() as the payload interrupt
 621          * will service it
 622          */
 623         dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
 624         return;
 625 done:
 626         glamo_mci_request_done(host, mrq);
 627 }
 628
 629 static void glamo_mci_set_power_mode(struct glamo_mci_host *host,
 630                                 unsigned char power_mode) {
 631         int ret;
 632
 633         if (power_mode == host->power_mode)
 634                 return;
 635
 636         switch(power_mode) {
 637         case MMC_POWER_UP:
 638                 if (host->power_mode == MMC_POWER_OFF) {
 639                         ret = regulator_enable(host->regulator);
 640                         if (ret)
 641                                 dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
 642                 }
 643                 break;
 644         case MMC_POWER_ON:
 645                 break;
 646         case MMC_POWER_OFF:
 647         default:
 648                 glamo_engine_disable(host->pdata->core,
 649                                      GLAMO_ENGINE_MMC);
 650
 651                 ret = regulator_disable(host->regulator);
 652                 if (ret)
 653                         dev_warn(&host->pdev->dev, "Failed to disable regulator: %d\n", ret);
 654                 break;
 655         }
 656         host->power_mode = power_mode;
 657 }
 658
 659 static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 660 {
 661         struct glamo_mci_host *host = mmc_priv(mmc);
 662         int bus_width = 0;
 663         int rate;
 664         int sd_drive;
 665         int ret;
 666
 667         /* Set power */
 668         glamo_mci_set_power_mode(host, ios->power_mode);
 669
 670         if (host->vdd != ios->vdd) {
 671                 ret = mmc_regulator_set_ocr(host->regulator, ios->vdd);
 672                 if (ret)
 673                         dev_err(&host->pdev->dev, "Failed to set regulator voltage: %d\n", ret);
 674                 else
 675                         host->vdd = ios->vdd;
 676         }
 677         rate = glamo_mci_set_card_clock(host, ios->clock);
 678
 679         if ((ios->power_mode == MMC_POWER_ON) ||
 680             (ios->power_mode == MMC_POWER_UP)) {
 681                 dev_info(&host->pdev->dev,
 682                         "powered (vdd = %hu) clk: %dkHz div=%hu (req: %ukHz). "
 683                         "Bus width=%d\n", ios->vdd,
 684                         rate / 1000, 0,
 685                         ios->clock / 1000, (int)ios->bus_width);
 686         } else {
 687                 dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
 688         }
 689
 690         /* set bus width */
 691         if (ios->bus_width == MMC_BUS_WIDTH_4)
 692                 bus_width = GLAMO_BASIC_MMC_EN_4BIT_DATA;
 693
 694         sd_drive = (rate * 4) / host->clk_rate;
 695         if (sd_drive > 3)
 696                 sd_drive = 3;
 697
 698         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
 699                                                GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xb0,
 700                                                    bus_width | sd_drive << 6);
 701 }
 702
 703
 704 /*
 705  * no physical write protect supported by us
 706  */
 707 static int glamo_mci_get_ro(struct mmc_host *mmc)
 708 {
 709         return 0;
 710 }
 711
 712 static struct mmc_host_ops glamo_mci_ops = {
 713         .request        = glamo_mci_send_request,
 714         .set_ios        = glamo_mci_set_ios,
 715         .get_ro         = glamo_mci_get_ro,
 716 };
 717
 718 static int glamo_mci_probe(struct platform_device *pdev)
 719 {
 720         struct mmc_host         *mmc;
 721         struct glamo_mci_host   *host;
 722         int ret;
 723
 724         dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
 725
 726         mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
 727         if (!mmc) {
 728                 ret = -ENOMEM;
 729                 goto probe_out;
 730         }
 731
 732         host = mmc_priv(mmc);
 733         host->mmc = mmc;
 734         host->pdev = pdev;
 735         host->pdata = pdev->dev.platform_data;
 736         host->power_mode = MMC_POWER_OFF;
 737         host->clk_enabled = 0;
 738
 739         INIT_WORK(&host->irq_work, glamo_mci_irq_worker);
 740         INIT_WORK(&host->read_work, glamo_mci_read_worker);
 741
 742         host->regulator = regulator_get(pdev->dev.parent, "SD_3V3");
 743         if (!host->regulator) {
 744                 dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
 745                 ret = -ENODEV;
 746                 goto probe_free_host;
 747         }
 748
 749         host->mmio_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 750         if (!host->mmio_mem) {
 751                 dev_err(&pdev->dev,
 752                         "failed to get io memory region resouce.\n");
 753                 ret = -ENOENT;
 754                 goto probe_regulator_put;
 755         }
 756
 757         host->mmio_mem = request_mem_region(host->mmio_mem->start,
 758                                             resource_size(host->mmio_mem),
 759                                             pdev->name);
 760
 761         if (!host->mmio_mem) {
 762                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 763                 ret = -ENOENT;
 764                 goto probe_regulator_put;
 765         }
 766
 767         host->mmio_base = ioremap(host->mmio_mem->start,
 768                                   resource_size(host->mmio_mem));
 769         if (!host->mmio_base) {
 770                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 771                 ret = -EINVAL;
 772                 goto probe_free_mem_region_mmio;
 773         }
 774
 775
 776         /* Get ahold of our data buffer we use for data in and out on MMC */
 777         host->data_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 778         if (!host->data_mem) {
 779                 dev_err(&pdev->dev,
 780                         "failed to get io memory region resource.\n");
 781                 ret = -ENOENT;
 782                 goto probe_iounmap_mmio;
 783         }
 784
 785         host->data_mem = request_mem_region(host->data_mem->start,
 786                                             resource_size(host->data_mem),
 787                                                                                 pdev->name);
 788
 789         if (!host->data_mem) {
 790                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 791                 ret = -ENOENT;
 792                 goto probe_iounmap_mmio;
 793         }
 794         host->data_base = ioremap(host->data_mem->start,
 795                                   resource_size(host->data_mem));
 796
 797         if (host->data_base == 0) {
 798                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 799                 ret = -EINVAL;
 800                 goto probe_free_mem_region_data;
 801         }
 802
 803         ret = request_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq, IRQF_SHARED,
 804                        pdev->name, host);
 805         if (ret) {
 806                 dev_err(&pdev->dev, "failed to register irq.\n");
 807                 goto probe_iounmap_data;
 808         }
 809
 810
 811         host->vdd = 0;
 812         host->clk_rate = glamo_pll_rate(host->pdata->core, GLAMO_PLL1);
 813
 814         /* explain our host controller capabilities */
 815         mmc->ops       = &glamo_mci_ops;
 816         mmc->ocr_avail = mmc_regulator_get_ocrmask(host->regulator);
 817         mmc->caps      = MMC_CAP_4_BIT_DATA |
 818                          MMC_CAP_MMC_HIGHSPEED |
 819                          MMC_CAP_SD_HIGHSPEED;
 820         mmc->f_min     = host->clk_rate / 256;
 821         mmc->f_max     = sd_max_clk;
 822
 823         mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
 824         mmc->max_blk_size  = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
 825         mmc->max_req_size  = resource_size(host->data_mem);
 826         mmc->max_seg_size  = mmc->max_req_size;
 827         mmc->max_phys_segs = 128;
 828         mmc->max_hw_segs   = 128;
 829
 830         if (mmc->ocr_avail < 0) {
 831                 dev_warn(&pdev->dev, "Failed to get ocr list for regulator: %d.\n",
 832                                 mmc->ocr_avail);
 833                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 834         }
 835
 836         platform_set_drvdata(pdev, mmc);
 837
 838         glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 839         glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 840
 841         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 842                         (u16)(host->data_mem->start));
 843         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 844                         (u16)(host->data_mem->start >> 16));
 845
 846         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 847                         (u16)(host->data_mem->start));
 848         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 849                         (u16)(host->data_mem->start >> 16));
 850
 851         setup_timer(&host->disable_timer, glamo_mci_disable_timer,
 852                                 (unsigned long)host);
 853
 854         if ((ret = mmc_add_host(mmc))) {
 855                 dev_err(&pdev->dev, "failed to add mmc host.\n");
 856                 goto probe_freeirq;
 857         }
 858
 859         dev_info(&pdev->dev,"initialisation done.\n");
 860         return 0;
 861
 862 probe_freeirq:
 863         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 864 probe_iounmap_data:
 865         iounmap(host->data_base);
 866 probe_free_mem_region_data:
 867         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 868 probe_iounmap_mmio:
 869         iounmap(host->mmio_base);
 870 probe_free_mem_region_mmio:
 871         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 872 probe_regulator_put:
 873         regulator_put(host->regulator);
 874 probe_free_host:
 875         mmc_free_host(mmc);
 876 probe_out:
 877         return ret;
 878 }
 879
 880 static int glamo_mci_remove(struct platform_device *pdev)
 881 {
 882         struct mmc_host *mmc = platform_get_drvdata(pdev);
 883         struct glamo_mci_host *host = mmc_priv(mmc);
 884
 885         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 886
 887         mmc_remove_host(mmc);
 888         iounmap(host->mmio_base);
 889         iounmap(host->data_base);
 890         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 891         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 892
 893         regulator_put(host->regulator);
 894
 895         mmc_free_host(mmc);
 896
 897         glamo_engine_disable(host->pdata->core, GLAMO_ENGINE_MMC);
 898         return 0;
 899 }
 900
 901
 902 #ifdef CONFIG_PM
 903
 904 static int glamo_mci_suspend(struct device *dev)
 905 {
 906         struct mmc_host *mmc = dev_get_drvdata(dev);
 907         struct glamo_mci_host *host = mmc_priv(mmc);
 908         int ret;
 909
 910         cancel_work_sync(&host->irq_work);
 911
 912         ret = mmc_suspend_host(mmc, PMSG_SUSPEND);
 913         glamo_mci_clock_enable(host);
 914
 915         return ret;
 916 }
 917
 918 static int glamo_mci_resume(struct device *dev)
 919 {
 920         struct mmc_host *mmc = dev_get_drvdata(dev);
 921         struct glamo_mci_host *host = mmc_priv(mmc);
 922         int ret;
 923
 924         glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 925         glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 926
 927         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 928                         (u16)(host->data_mem->start));
 929         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 930                         (u16)(host->data_mem->start >> 16));
 931
 932         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 933                         (u16)(host->data_mem->start));
 934         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 935                         (u16)(host->data_mem->start >> 16));
 936         mdelay(5);
 937
 938         ret = mmc_resume_host(host->mmc);
 939 /*      glamo_mci_clock_disable(host);*/
 940
 941         return 0;
 942 }
 943
 944 static struct dev_pm_ops glamo_mci_pm_ops = {
 945         .suspend = glamo_mci_suspend,
 946         .resume  = glamo_mci_resume,
 947 };
 948 #define GLAMO_MCI_PM_OPS (&glamo_mci_pm_ops)
 949
 950 #else /* CONFIG_PM */
 951 #define GLAMO_MCI_PM_OPS NULL
 952 #endif /* CONFIG_PM */
 953
 954
 955 static struct platform_driver glamo_mci_driver =
 956 {
 957         .probe  = glamo_mci_probe,
 958         .remove = glamo_mci_remove,
 959         .driver = {
 960                 .name  = "glamo-mci",
 961                 .owner = THIS_MODULE,
 962                 .pm    = GLAMO_MCI_PM_OPS,
 963         },
 964 };
 965
 966 static int __init glamo_mci_init(void)
 967 {
 968         platform_driver_register(&glamo_mci_driver);
 969         return 0;
 970 }
 971
 972 static void __exit glamo_mci_exit(void)
 973 {
 974         platform_driver_unregister(&glamo_mci_driver);
 975 }
 976
 977 module_init(glamo_mci_init);
 978 module_exit(glamo_mci_exit);
 979
 980 MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
 981 MODULE_LICENSE("GPL");
 982 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");