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[s3c24xx] glamo-mci: Cleanup mmc clock rate control.
[openwrt.git] / target / linux / s3c24xx / files-2.6.30 / drivers / mfd / glamo / glamo-core.c
1 /* Smedia Glamo 336x/337x driver
2 *
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/interrupt.h>
33 #include <linux/workqueue.h>
34 #include <linux/platform_device.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/spinlock.h>
37 #include <linux/mfd/core.h>
38 #include <linux/mfd/glamo.h>
39 #include <linux/spi/glamo.h>
40 #include <linux/glamo-gpio.h>
41 #include <linux/glamofb.h>
42 #include <linux/io.h>
43
44 #include <asm/div64.h>
45
46 #ifdef CONFIG_PM
47 #include <linux/pm.h>
48 #endif
49
50 #include "glamo-regs.h"
51 #include "glamo-core.h"
52
53 #define GLAMO_MEM_REFRESH_COUNT 0x100
54
55 /*
56 * Glamo internal settings
57 *
58 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
59 * above. Couple of GTA02 users report trouble with memory bus when they
60 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
61 * scheme if their Glamo chip needs it.
62 *
63 * you can override the faster default on kernel commandline using
64 *
65 * glamo3362.slow_memory=1
66 *
67 * for example
68 */
69
70 static int slow_memory = 0;
71 module_param(slow_memory, int, 0644);
72
73 struct reg_range {
74 int start;
75 int count;
76 char *name;
77 char dump;
78 };
79
80 struct reg_range reg_range[] = {
81 { 0x0000, 0x76, "General", 1 },
82 { 0x0200, 0x18, "Host Bus", 1 },
83 { 0x0300, 0x38, "Memory", 1 },
84 /* { 0x0400, 0x100, "Sensor", 0 }, */
85 /* { 0x0500, 0x300, "ISP", 0 }, */
86 /* { 0x0800, 0x400, "JPEG", 0 }, */
87 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
88 { 0x1100, 0xb2, "LCD 1", 1 },
89 { 0x1200, 0x64, "LCD 2", 1 },
90 { 0x1400, 0x42, "MMC", 1 },
91 /* { 0x1500, 0x080, "MPU 0", 0 },
92 { 0x1580, 0x080, "MPU 1", 0 },
93 { 0x1600, 0x080, "Cmd Queue", 0 },
94 { 0x1680, 0x080, "RISC CPU", 0 },
95 { 0x1700, 0x400, "2D Unit", 0 },
96 { 0x1b00, 0x900, "3D Unit", 0 }, */
97 };
98
99 static inline void __reg_write(struct glamo_core *glamo,
100 u_int16_t reg, u_int16_t val)
101 {
102 writew(val, glamo->base + reg);
103 }
104
105 static inline u_int16_t __reg_read(struct glamo_core *glamo,
106 u_int16_t reg)
107 {
108 return readw(glamo->base + reg);
109 }
110
111 static void __reg_set_bit_mask(struct glamo_core *glamo,
112 u_int16_t reg, u_int16_t mask,
113 u_int16_t val)
114 {
115 u_int16_t tmp;
116
117 val &= mask;
118
119 tmp = __reg_read(glamo, reg);
120 tmp &= ~mask;
121 tmp |= val;
122 __reg_write(glamo, reg, tmp);
123 }
124
125 static void reg_set_bit_mask(struct glamo_core *glamo,
126 u_int16_t reg, u_int16_t mask,
127 u_int16_t val)
128 {
129 spin_lock(&glamo->lock);
130 __reg_set_bit_mask(glamo, reg, mask, val);
131 spin_unlock(&glamo->lock);
132 }
133
134 static inline void __reg_set_bit(struct glamo_core *glamo,
135 u_int16_t reg, u_int16_t bit)
136 {
137 __reg_set_bit_mask(glamo, reg, bit, 0xffff);
138 }
139
140 static inline void __reg_clear_bit(struct glamo_core *glamo,
141 u_int16_t reg, u_int16_t bit)
142 {
143 __reg_set_bit_mask(glamo, reg, bit, 0);
144 }
145
146 /***********************************************************************
147 * resources of sibling devices
148 ***********************************************************************/
149
150 static struct resource glamo_fb_resources[] = {
151 {
152 .name = "glamo-fb-regs",
153 .start = GLAMO_REGOFS_LCD,
154 .end = GLAMO_REGOFS_MMC - 1,
155 .flags = IORESOURCE_MEM,
156 }, {
157 .name = "glamo-fb-mem",
158 .start = GLAMO_OFFSET_FB,
159 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 };
163
164 static struct resource glamo_mmc_resources[] = {
165 {
166 .start = GLAMO_REGOFS_MMC,
167 .end = GLAMO_REGOFS_MPROC0 - 1,
168 .flags = IORESOURCE_MEM
169 }, {
170 .start = IRQ_GLAMO_MMC,
171 .end = IRQ_GLAMO_MMC,
172 .flags = IORESOURCE_IRQ,
173 }, { /* our data buffer for MMC transfers */
174 .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
175 .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
176 GLAMO_MMC_BUFFER_SIZE - 1,
177 .flags = IORESOURCE_MEM
178 },
179 };
180
181 enum glamo_cells {
182 GLAMO_CELL_FB,
183 GLAMO_CELL_MMC,
184 GLAMO_CELL_SPI_GPIO
185 };
186
187 static struct mfd_cell glamo_cells[] = {
188 [GLAMO_CELL_FB] = {
189 .name = "glamo-fb",
190 .num_resources = ARRAY_SIZE(glamo_fb_resources),
191 .resources = glamo_fb_resources,
192 },
193 [GLAMO_CELL_MMC] = {
194 .name = "glamo-mci",
195 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
196 .resources = glamo_mmc_resources,
197 },
198 [GLAMO_CELL_SPI_GPIO] = {
199 .name = "glamo-spi-gpio",
200 },
201 };
202
203
204 /***********************************************************************
205 * IRQ demultiplexer
206 ***********************************************************************/
207 #define irq2glamo(x) (x - IRQ_GLAMO(0))
208
209 static void glamo_ack_irq(unsigned int irq)
210 {
211 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
212 /* clear interrupt source */
213 __reg_write(glamo, GLAMO_REG_IRQ_CLEAR,
214 1 << irq2glamo(irq));
215 }
216
217 static void glamo_mask_irq(unsigned int irq)
218 {
219 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
220 u_int16_t tmp;
221
222 /* clear bit in enable register */
223 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
224 tmp &= ~(1 << irq2glamo(irq));
225 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
226 }
227
228 static void glamo_unmask_irq(unsigned int irq)
229 {
230 struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
231 u_int16_t tmp;
232
233 /* set bit in enable register */
234 tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
235 tmp |= (1 << irq2glamo(irq));
236 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
237 }
238
239 static struct irq_chip glamo_irq_chip = {
240 .name = "glamo",
241 .ack = glamo_ack_irq,
242 .mask = glamo_mask_irq,
243 .unmask = glamo_unmask_irq,
244 };
245
246 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
247 {
248 struct glamo_core *glamo = get_irq_desc_chip_data(desc);
249 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
250
251 if (unlikely(desc->status & IRQ_INPROGRESS)) {
252 desc->status |= (IRQ_PENDING | IRQ_MASKED);
253 desc->chip->mask(irq);
254 desc->chip->ack(irq);
255 return;
256 }
257 kstat_incr_irqs_this_cpu(irq, desc);
258
259 desc->chip->ack(irq);
260 desc->status |= IRQ_INPROGRESS;
261
262 do {
263 u_int16_t irqstatus;
264 int i;
265
266 if (unlikely((desc->status &
267 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
268 (IRQ_PENDING | IRQ_MASKED))) {
269 /* dealing with pending IRQ, unmasking */
270 desc->chip->unmask(irq);
271 desc->status &= ~IRQ_MASKED;
272 }
273
274 desc->status &= ~IRQ_PENDING;
275
276 /* read IRQ status register */
277 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
278 for (i = 0; i < 9; i++)
279 if (irqstatus & (1 << i))
280 desc_handle_irq(IRQ_GLAMO(i),
281 irq_desc+IRQ_GLAMO(i));
282
283 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
284
285 desc->status &= ~IRQ_INPROGRESS;
286 }
287
288
289 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
290 const char *buf, size_t count)
291 {
292 unsigned long reg = simple_strtoul(buf, NULL, 10);
293 struct glamo_core *glamo = dev_get_drvdata(dev);
294
295 while (*buf && (*buf != ' '))
296 buf++;
297 if (*buf != ' ')
298 return -EINVAL;
299 while (*buf && (*buf == ' '))
300 buf++;
301 if (!*buf)
302 return -EINVAL;
303
304 printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
305 reg, simple_strtoul(buf, NULL, 10));
306
307 __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
308
309 return count;
310 }
311
312 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
313 char *buf)
314 {
315 struct glamo_core *glamo = dev_get_drvdata(dev);
316 int n, n1 = 0, r;
317 char * end = buf;
318
319 spin_lock(&glamo->lock);
320
321 for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
322 if (!reg_range[r].dump)
323 continue;
324 n1 = 0;
325 end += sprintf(end, "\n%s\n", reg_range[r].name);
326 for (n = reg_range[r].start;
327 n < reg_range[r].start + reg_range[r].count; n += 2) {
328 if (((n1++) & 7) == 0)
329 end += sprintf(end, "\n%04X: ", n);
330 end += sprintf(end, "%04x ", __reg_read(glamo, n));
331 }
332 end += sprintf(end, "\n");
333 if (!attr) {
334 printk("%s", buf);
335 end = buf;
336 }
337 }
338 spin_unlock(&glamo->lock);
339
340 return end - buf;
341 }
342
343 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
344 static struct attribute *glamo_sysfs_entries[] = {
345 &dev_attr_regs.attr,
346 NULL
347 };
348 static struct attribute_group glamo_attr_group = {
349 .name = NULL,
350 .attrs = glamo_sysfs_entries,
351 };
352
353
354
355 /***********************************************************************
356 * 'engine' support
357 ***********************************************************************/
358
359 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
360 {
361 switch (engine) {
362 case GLAMO_ENGINE_LCD:
363 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
364 GLAMO_HOSTBUS2_MMIO_EN_LCD,
365 GLAMO_HOSTBUS2_MMIO_EN_LCD);
366 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
367 GLAMO_CLOCK_LCD_EN_M5CLK |
368 GLAMO_CLOCK_LCD_EN_DHCLK |
369 GLAMO_CLOCK_LCD_EN_DMCLK |
370 GLAMO_CLOCK_LCD_EN_DCLK |
371 GLAMO_CLOCK_LCD_DG_M5CLK |
372 GLAMO_CLOCK_LCD_DG_DMCLK);
373 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
374 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
375 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
376 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
377 break;
378 case GLAMO_ENGINE_MMC:
379 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
380 GLAMO_HOSTBUS2_MMIO_EN_MMC,
381 GLAMO_HOSTBUS2_MMIO_EN_MMC);
382 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
383 GLAMO_CLOCK_MMC_EN_M9CLK |
384 GLAMO_CLOCK_MMC_EN_TCLK |
385 GLAMO_CLOCK_MMC_DG_M9CLK |
386 GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
387 /* enable the TCLK divider clk input */
388 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
389 GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
390 GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
391 break;
392 case GLAMO_ENGINE_2D:
393 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
394 GLAMO_CLOCK_2D_EN_M7CLK |
395 GLAMO_CLOCK_2D_EN_GCLK |
396 GLAMO_CLOCK_2D_DG_M7CLK |
397 GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
398 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
399 GLAMO_HOSTBUS2_MMIO_EN_2D,
400 GLAMO_HOSTBUS2_MMIO_EN_2D);
401 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
402 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
403 0xffff);
404 break;
405 case GLAMO_ENGINE_CMDQ:
406 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
407 GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
408 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
409 GLAMO_HOSTBUS2_MMIO_EN_CQ,
410 GLAMO_HOSTBUS2_MMIO_EN_CQ);
411 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
412 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
413 0xffff);
414 break;
415 /* FIXME: Implementation */
416 default:
417 return -EINVAL;
418 }
419
420 glamo->engine_enabled_bitfield |= 1 << engine;
421
422 return 0;
423 }
424
425 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
426 {
427 int ret;
428
429 spin_lock(&glamo->lock);
430
431 ret = __glamo_engine_enable(glamo, engine);
432
433 spin_unlock(&glamo->lock);
434
435 return ret;
436 }
437 EXPORT_SYMBOL_GPL(glamo_engine_enable);
438
439 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
440 {
441 switch (engine) {
442 case GLAMO_ENGINE_LCD:
443 /* remove pixel clock to LCM */
444 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
445 GLAMO_CLOCK_LCD_EN_DCLK, 0);
446 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
447 GLAMO_CLOCK_LCD_EN_DHCLK |
448 GLAMO_CLOCK_LCD_EN_DMCLK, 0);
449 /* kill memory clock */
450 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
451 GLAMO_CLOCK_LCD_EN_M5CLK, 0);
452 /* stop dividing the clocks */
453 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
454 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
455 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
456 GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
457 break;
458
459 case GLAMO_ENGINE_MMC:
460 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
461 GLAMO_CLOCK_MMC_EN_M9CLK |
462 GLAMO_CLOCK_MMC_EN_TCLK |
463 GLAMO_CLOCK_MMC_DG_M9CLK |
464 GLAMO_CLOCK_MMC_DG_TCLK, 0);
465 /* disable the TCLK divider clk input */
466 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
467 GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
468 break;
469 case GLAMO_ENGINE_CMDQ:
470 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
471 GLAMO_CLOCK_2D_EN_M6CLK,
472 0);
473 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
474 GLAMO_HOSTBUS2_MMIO_EN_CQ,
475 GLAMO_HOSTBUS2_MMIO_EN_CQ);
476 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
477 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
478 0);*/
479 break;
480 case GLAMO_ENGINE_2D:
481 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
482 GLAMO_CLOCK_2D_EN_M7CLK |
483 GLAMO_CLOCK_2D_EN_GCLK |
484 GLAMO_CLOCK_2D_DG_M7CLK |
485 GLAMO_CLOCK_2D_DG_GCLK,
486 0);
487 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
488 GLAMO_HOSTBUS2_MMIO_EN_2D,
489 GLAMO_HOSTBUS2_MMIO_EN_2D);
490 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
491 GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
492 0);
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 glamo->engine_enabled_bitfield &= ~(1 << engine);
499
500 return 0;
501 }
502 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
503 {
504 int ret;
505
506 spin_lock(&glamo->lock);
507
508 ret = __glamo_engine_disable(glamo, engine);
509
510 spin_unlock(&glamo->lock);
511
512 return ret;
513 }
514 EXPORT_SYMBOL_GPL(glamo_engine_disable);
515
516 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
517 [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD,
518 [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC,
519 [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP,
520 [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG,
521 [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D,
522 [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D,
523 [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
524 [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
525 };
526
527 void glamo_engine_clkreg_set(struct glamo_core *glamo,
528 enum glamo_engine engine,
529 u_int16_t mask, u_int16_t val)
530 {
531 reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
532 }
533 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
534
535 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
536 enum glamo_engine engine)
537 {
538 u_int16_t val;
539
540 spin_lock(&glamo->lock);
541 val = __reg_read(glamo, engine_clock_regs[engine]);
542 spin_unlock(&glamo->lock);
543
544 return val;
545 }
546 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
547
548 static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
549 [GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
550 [GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
551 [GLAMO_ENGINE_2D] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
552 };
553
554 void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
555 {
556 uint16_t reg = engine_div_regs[engine].reg;
557 uint16_t bit = engine_div_regs[engine].val;
558 uint16_t val;
559
560 spin_lock(&glamo->lock);
561 val = __reg_read(glamo, reg);
562 __reg_write(glamo, reg, val | bit);
563 spin_unlock(&glamo->lock);
564 mdelay(5);
565 }
566 EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
567
568 void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
569 {
570 uint16_t reg = engine_div_regs[engine].reg;
571 uint16_t bit = engine_div_regs[engine].val;
572 uint16_t val;
573
574 spin_lock(&glamo->lock);
575 val = __reg_read(glamo, reg);
576 __reg_write(glamo, reg, val & ~bit);
577 spin_unlock(&glamo->lock);
578 }
579 EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
580
581 static const struct glamo_script reset_regs[] = {
582 [GLAMO_ENGINE_LCD] = {
583 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
584 },
585 #if 0
586 [GLAMO_ENGINE_HOST] = {
587 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
588 },
589 [GLAMO_ENGINE_MEM] = {
590 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
591 },
592 #endif
593 [GLAMO_ENGINE_MMC] = {
594 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
595 },
596 [GLAMO_ENGINE_CMDQ] = {
597 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
598 },
599 [GLAMO_ENGINE_2D] = {
600 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
601 },
602 [GLAMO_ENGINE_JPEG] = {
603 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
604 },
605 };
606
607 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
608 {
609 uint16_t reg = reset_regs[engine].reg;
610 uint16_t val = reset_regs[engine].val;
611
612 if (engine >= ARRAY_SIZE(reset_regs)) {
613 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
614 return;
615 }
616
617
618 spin_lock(&glamo->lock);
619 __reg_set_bit(glamo, reg, val);
620 __reg_clear_bit(glamo, reg, val);
621 spin_unlock(&glamo->lock);
622 }
623 EXPORT_SYMBOL_GPL(glamo_engine_reset);
624
625 void glamo_lcm_reset(struct platform_device *pdev, int level)
626 {
627 struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
628 if (!glamo)
629 return;
630
631 glamo_gpio_setpin(glamo, GLAMO_GPIO4, level);
632 glamo_gpio_cfgpin(glamo, GLAMO_GPIO4_OUTPUT);
633 }
634 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
635
636 int glamo_pll_rate(struct glamo_core *glamo,
637 enum glamo_pll pll)
638 {
639 u_int16_t reg;
640 unsigned int osci = glamo->pdata->osci_clock_rate;
641
642 switch (pll) {
643 case GLAMO_PLL1:
644 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
645 break;
646 case GLAMO_PLL2:
647 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
648 break;
649 default:
650 return -EINVAL;
651 }
652 return osci*reg;
653 }
654 EXPORT_SYMBOL_GPL(glamo_pll_rate);
655
656 int glamo_engine_reclock(struct glamo_core *glamo,
657 enum glamo_engine engine,
658 int hz)
659 {
660 int pll;
661 u_int16_t reg, mask, div;
662
663 if (!hz)
664 return -EINVAL;
665
666 switch (engine) {
667 case GLAMO_ENGINE_LCD:
668 pll = GLAMO_PLL1;
669 reg = GLAMO_REG_CLOCK_GEN7;
670 mask = 0xff;
671 break;
672 case GLAMO_ENGINE_MMC:
673 pll = GLAMO_PLL1;
674 reg = GLAMO_REG_CLOCK_GEN8;
675 mask = 0xff;
676 break;
677 default:
678 dev_warn(&glamo->pdev->dev,
679 "reclock of engine 0x%x not supported\n", engine);
680 return -EINVAL;
681 break;
682 }
683
684 pll = glamo_pll_rate(glamo, pll);
685
686 div = pll / hz;
687
688 if (div != 0 && pll / div <= hz)
689 --div;
690
691 if (div > mask)
692 div = mask;
693
694 dev_dbg(&glamo->pdev->dev,
695 "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
696
697 reg_set_bit_mask(glamo, reg, mask, div);
698 mdelay(5); /* wait some time to stabilize */
699
700 return pll / (div + 1);
701 }
702 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
703
704 /***********************************************************************
705 * script support
706 ***********************************************************************/
707
708 int glamo_run_script(struct glamo_core *glamo, const struct glamo_script *script,
709 int len, int may_sleep)
710 {
711 int i;
712
713 for (i = 0; i < len; i++) {
714 struct glamo_script *line = &script[i];
715
716 switch (line->reg) {
717 case 0xffff:
718 return 0;
719 case 0xfffe:
720 if (may_sleep)
721 msleep(line->val);
722 else
723 mdelay(line->val * 4);
724 break;
725 case 0xfffd:
726 /* spin until PLLs lock */
727 while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
728 ;
729 break;
730
731 /*
732 * couple of people reported artefacts with 2.6.28 changes, this
733 * allows reversion to 2.6.24 settings
734 */
735
736 case 0x200:
737 switch (slow_memory) {
738 /* choice 1 is the most conservative */
739 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
740 __reg_write(glamo, script[i].reg, 0xef0);
741 break;
742 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
743 __reg_write(glamo, script[i].reg, 0xea0);
744 break;
745 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
746 __reg_write(glamo, script[i].reg, 0xe50);
747 break;
748 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
749 __reg_write(glamo, script[i].reg, 0xe00);
750 break;
751
752 /* using PLL2 for memory bus increases CPU bandwidth significantly */
753 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
754 __reg_write(glamo, script[i].reg, 0xef3);
755 break;
756 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
757 __reg_write(glamo, script[i].reg, 0xea3);
758 break;
759 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
760 __reg_write(glamo, script[i].reg, 0xe53);
761 break;
762 /* default of 0 or >7 is fastest */
763 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
764 __reg_write(glamo, script[i].reg, 0xe03);
765 break;
766 }
767 break;
768
769 default:
770 __reg_write(glamo, script[i].reg, script[i].val);
771 break;
772 }
773 }
774
775 return 0;
776 }
777 EXPORT_SYMBOL(glamo_run_script);
778
779 static const struct glamo_script glamo_init_script[] = {
780 { GLAMO_REG_CLOCK_HOST, 0x1000 },
781 { 0xfffe, 2 },
782 { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
783 { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
784 { GLAMO_REG_CLOCK_LCD, 0x1000 },
785 { GLAMO_REG_CLOCK_MMC, 0x1000 },
786 { GLAMO_REG_CLOCK_ISP, 0x1000 },
787 { GLAMO_REG_CLOCK_ISP, 0x3000 },
788 { GLAMO_REG_CLOCK_JPEG, 0x1000 },
789 { GLAMO_REG_CLOCK_3D, 0x1000 },
790 { GLAMO_REG_CLOCK_3D, 0x3000 },
791 { GLAMO_REG_CLOCK_2D, 0x1000 },
792 { GLAMO_REG_CLOCK_2D, 0x3000 },
793 { GLAMO_REG_CLOCK_RISC1, 0x1000 },
794 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
795 { GLAMO_REG_CLOCK_MPEG, 0x3000 },
796 { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
797 { 0xfffe, 2 },
798 { GLAMO_REG_CLOCK_HOST, 0x0000 },
799 { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
800 { GLAMO_REG_CLOCK_LCD, 0x0000 },
801 { GLAMO_REG_CLOCK_MMC, 0x0000 },
802 #if 0
803 /* unused engines must be left in reset to stop MMC block read "blackouts" */
804 { GLAMO_REG_CLOCK_ISP, 0x0000 },
805 { GLAMO_REG_CLOCK_ISP, 0x0000 },
806 { GLAMO_REG_CLOCK_JPEG, 0x0000 },
807 { GLAMO_REG_CLOCK_3D, 0x0000 },
808 { GLAMO_REG_CLOCK_3D, 0x0000 },
809 { GLAMO_REG_CLOCK_2D, 0x0000 },
810 { GLAMO_REG_CLOCK_2D, 0x0000 },
811 { GLAMO_REG_CLOCK_RISC1, 0x0000 },
812 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
813 { GLAMO_REG_CLOCK_MPEG, 0x0000 },
814 #endif
815 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
816 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
817 { 0xfffd, 0 },
818 /*
819 * b9 of this register MUST be zero to get any interrupts on INT#
820 * the other set bits enable all the engine interrupt sources
821 */
822 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
823 { GLAMO_REG_CLOCK_GEN6, 0x2000 },
824 { GLAMO_REG_CLOCK_GEN7, 0x0101 },
825 { GLAMO_REG_CLOCK_GEN8, 0x0100 },
826 { GLAMO_REG_CLOCK_HOST, 0x000d },
827 /*
828 * b7..b4 = 0 = no wait states on read or write
829 * b0 = 1 select PLL2 for Host interface, b1 = enable it
830 */
831 { 0x200, 0x0e03 /* this is replaced by script parser */ },
832 { 0x202, 0x07ff },
833 { 0x212, 0x0000 },
834 { 0x214, 0x4000 },
835 { 0x216, 0xf00e },
836
837 /* S-Media recommended "set tiling mode to 512 mode for memory access
838 * more efficiency when 640x480" */
839 { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
840 { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
841
842 { GLAMO_REGOFS_HOSTBUS + 2, 0xffff }, /* enable on MMIO*/
843
844 { GLAMO_REG_MEM_TIMING1, 0x0108 },
845 { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
846 { GLAMO_REG_MEM_TIMING3, 0x0000 },
847 { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
848 { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
849 { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
850 { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
851 { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
852 { GLAMO_REG_MEM_TIMING9, 0x6006 },
853 { GLAMO_REG_MEM_TIMING10, 0x00ff },
854 { GLAMO_REG_MEM_TIMING11, 0x0001 },
855 { GLAMO_REG_MEM_POWER1, 0x0020 },
856 { GLAMO_REG_MEM_POWER2, 0x0000 },
857 { GLAMO_REG_MEM_DRAM1, 0x0000 },
858 { 0xfffe, 1 },
859 { GLAMO_REG_MEM_DRAM1, 0xc100 },
860 { 0xfffe, 1 },
861 { GLAMO_REG_MEM_DRAM1, 0xe100 },
862 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
863 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
864 { GLAMO_REG_GPIO_GEN1, 0x000f },
865 { GLAMO_REG_GPIO_GEN2, 0x111e },
866 { GLAMO_REG_GPIO_GEN3, 0xccc3 },
867 { GLAMO_REG_GPIO_GEN4, 0x111e },
868 { GLAMO_REG_GPIO_GEN5, 0x000f },
869 };
870 #if 0
871 static struct glamo_script glamo_resume_script[] = {
872
873 { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
874 { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
875 { GLAMO_REG_DFT_GEN6, 1 },
876 { 0xfffe, 100 },
877 { 0xfffd, 0 },
878 { 0x200, 0x0e03 },
879
880 /*
881 * b9 of this register MUST be zero to get any interrupts on INT#
882 * the other set bits enable all the engine interrupt sources
883 */
884 { GLAMO_REG_IRQ_ENABLE, 0x01ff },
885 { GLAMO_REG_CLOCK_HOST, 0x0018 },
886 { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
887
888 { GLAMO_REG_MEM_DRAM1, 0x0000 },
889 { 0xfffe, 1 },
890 { GLAMO_REG_MEM_DRAM1, 0xc100 },
891 { 0xfffe, 1 },
892 { GLAMO_REG_MEM_DRAM1, 0xe100 },
893 { GLAMO_REG_MEM_DRAM2, 0x01d6 },
894 { GLAMO_REG_CLOCK_MEMORY, 0x000b },
895 };
896 #endif
897
898 enum glamo_power {
899 GLAMO_POWER_ON,
900 GLAMO_POWER_SUSPEND,
901 };
902
903 static void glamo_power(struct glamo_core *glamo,
904 enum glamo_power new_state)
905 {
906 int n;
907 unsigned long flags;
908
909 spin_lock_irqsave(&glamo->lock, flags);
910
911 dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
912
913 /*
914 Power management
915 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
916 {
917 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
918 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
919 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
920 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
921 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
922 };
923
924 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
925 {
926 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
927 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
928 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
929 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
930 };
931
932 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
933 {
934 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
935 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
936 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
937 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
938 };
939 */
940
941 switch (new_state) {
942 case GLAMO_POWER_ON:
943
944 /*
945 * glamo state on resume is nondeterministic in some
946 * fundamental way, it has also been observed that the
947 * Glamo reset pin can get asserted by, eg, touching it with
948 * a scope probe. So the only answer is to roll with it and
949 * force an external reset on the Glamo during resume.
950 */
951
952 (glamo->pdata->glamo_external_reset)(0);
953 udelay(10);
954 (glamo->pdata->glamo_external_reset)(1);
955 mdelay(5);
956
957 glamo_run_script(glamo, glamo_init_script,
958 ARRAY_SIZE(glamo_init_script), 0);
959
960 break;
961
962 case GLAMO_POWER_SUSPEND:
963
964 /* nuke interrupts */
965 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
966
967 /* stash a copy of which engines were running */
968 glamo->engine_enabled_bitfield_suspend =
969 glamo->engine_enabled_bitfield;
970
971 /* take down each engine before we kill mem and pll */
972 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
973 if (glamo->engine_enabled_bitfield & (1 << n))
974 __glamo_engine_disable(glamo, n);
975
976 /* enable self-refresh */
977
978 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
979 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
980 GLAMO_MEM_DRAM1_EN_GATE_CKE |
981 GLAMO_MEM_DRAM1_SELF_REFRESH |
982 GLAMO_MEM_REFRESH_COUNT);
983 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
984 GLAMO_MEM_DRAM1_EN_MODEREG_SET |
985 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
986 GLAMO_MEM_DRAM1_EN_GATE_CKE |
987 GLAMO_MEM_DRAM1_SELF_REFRESH |
988 GLAMO_MEM_REFRESH_COUNT);
989
990 /* force RAM into deep powerdown */
991
992 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
993 GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
994 (7 << 6) | /* tRC */
995 (1 << 4) | /* tRP */
996 (1 << 2) | /* tRCD */
997 2); /* CAS latency */
998
999 /* disable clocks to memory */
1000 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1001
1002 /* all dividers from OSCI */
1003 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1004
1005 /* PLL2 into bypass */
1006 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1007
1008 __reg_write(glamo, 0x200, 0x0e00);
1009
1010
1011 /* kill PLLS 1 then 2 */
1012 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1013 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1014
1015 break;
1016 }
1017
1018 spin_unlock_irqrestore(&glamo->lock, flags);
1019 }
1020
1021 #if 0
1022 #define MEMDETECT_RETRY 6
1023 static unsigned int detect_memsize(struct glamo_core *glamo)
1024 {
1025 int i;
1026
1027 /*static const u_int16_t pattern[] = {
1028 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1029 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1030 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1031 0x7777, 0x2a2a, 0x8888, 0x1a1a
1032 }; */
1033
1034 for (i = 0; i < MEMDETECT_RETRY; i++) {
1035 switch (glamo->type) {
1036 case 3600:
1037 __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1038 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1039 break;
1040 case 3650:
1041 switch (glamo->revision) {
1042 case GLAMO_CORE_REV_A0:
1043 if (i & 1)
1044 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1045 0x097a);
1046 else
1047 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1048 0x0173);
1049
1050 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1051 msleep(1);
1052 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1053 break;
1054 default:
1055 if (i & 1)
1056 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1057 0x0972);
1058 else
1059 __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1060 0x0872);
1061
1062 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1063 msleep(1);
1064 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1065 break;
1066 }
1067 break;
1068 case 3700:
1069 /* FIXME */
1070 default:
1071 break;
1072 }
1073
1074 #if 0
1075 /* FIXME: finish implementation */
1076 for (j = 0; j < 8; j++) {
1077 __
1078 #endif
1079 }
1080
1081 return 0;
1082 }
1083 #endif
1084
1085 /* Find out if we can support this version of the Glamo chip */
1086 static int glamo_supported(struct glamo_core *glamo)
1087 {
1088 u_int16_t dev_id, rev_id; /*, memsize; */
1089
1090 dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1091 rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1092
1093 switch (dev_id) {
1094 case 0x3650:
1095 switch (rev_id) {
1096 case GLAMO_CORE_REV_A2:
1097 break;
1098 case GLAMO_CORE_REV_A0:
1099 case GLAMO_CORE_REV_A1:
1100 case GLAMO_CORE_REV_A3:
1101 dev_warn(&glamo->pdev->dev, "untested core revision "
1102 "%04x, your mileage may vary\n", rev_id);
1103 break;
1104 default:
1105 dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1106 "%04x, your mileage may vary\n", rev_id);
1107 /* maybe should abort ? */
1108 }
1109 break;
1110 case 0x3600:
1111 case 0x3700:
1112 default:
1113 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1114 dev_id);
1115 return 0;
1116 }
1117
1118 dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1119 "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1120 glamo_pll_rate(glamo, GLAMO_PLL1),
1121 glamo_pll_rate(glamo, GLAMO_PLL2));
1122
1123 return 1;
1124 }
1125
1126 static int __init glamo_probe(struct platform_device *pdev)
1127 {
1128 int rc = 0, irq;
1129 struct glamo_core *glamo;
1130
1131 glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1132 if (!glamo)
1133 return -ENOMEM;
1134
1135 spin_lock_init(&glamo->lock);
1136 glamo->pdev = pdev;
1137 glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138 glamo->irq = platform_get_irq(pdev, 0);
1139 glamo->pdata = pdev->dev.platform_data;
1140 if (!glamo->mem || !glamo->pdata) {
1141 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1142 rc = -ENOENT;
1143 goto bail_free;
1144 }
1145
1146 /* register a number of sibling devices whoise IOMEM resources
1147 * are siblings of pdev's IOMEM resource */
1148
1149 /* only remap the generic, hostbus and memory controller registers */
1150 glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1151 if (!glamo->base) {
1152 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1153 goto bail_free;
1154 }
1155
1156 platform_set_drvdata(pdev, glamo);
1157
1158 (glamo->pdata->glamo_external_reset)(0);
1159 udelay(10);
1160 (glamo->pdata->glamo_external_reset)(1);
1161 mdelay(10);
1162
1163 /*
1164 * finally set the mfd interrupts up
1165 * can't do them earlier or sibling probes blow up
1166 */
1167
1168 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1169 set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
1170 set_irq_flags(irq, IRQF_VALID);
1171 set_irq_chip_data(irq, glamo);
1172 }
1173
1174 if (glamo->pdata->glamo_irq_is_wired &&
1175 !glamo->pdata->glamo_irq_is_wired()) {
1176 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1177 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1178 set_irq_chip_data(glamo->irq, glamo);
1179 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1180 glamo->irq_works = 1;
1181 } else {
1182 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1183 glamo->irq_works = 0;
1184 }
1185
1186 /* confirm it isn't insane version */
1187 if (!glamo_supported(glamo)) {
1188 dev_err(&pdev->dev, "This Glamo is not supported\n");
1189 goto bail_irq;
1190 }
1191
1192 /* sysfs */
1193 rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1194 if (rc < 0) {
1195 dev_err(&pdev->dev, "cannot create sysfs group\n");
1196 goto bail_irq;
1197 }
1198
1199 /* init the chip with canned register set */
1200
1201 dev_dbg(&glamo->pdev->dev, "running init script\n");
1202 glamo_run_script(glamo, glamo_init_script,
1203 ARRAY_SIZE(glamo_init_script), 1);
1204
1205 dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1206 glamo_pll_rate(glamo, GLAMO_PLL1),
1207 glamo_pll_rate(glamo, GLAMO_PLL2));
1208
1209 /* register siblings */
1210 glamo->pdata->mmc_data->core = glamo;
1211 glamo_cells[GLAMO_CELL_MMC].platform_data = glamo->pdata->mmc_data;
1212 glamo_cells[GLAMO_CELL_MMC].data_size =
1213 sizeof(struct glamo_mmc_platform_data);
1214
1215 glamo->pdata->fb_data->core = glamo;
1216 glamo_cells[GLAMO_CELL_FB].platform_data = glamo->pdata->fb_data;
1217 glamo_cells[GLAMO_CELL_FB].data_size = sizeof(struct glamo_fb_platform_data);
1218
1219 glamo->pdata->spigpio_data->core = glamo;
1220 glamo_cells[GLAMO_CELL_SPI_GPIO].platform_data =
1221 glamo->pdata->spigpio_data;
1222 glamo_cells[GLAMO_CELL_SPI_GPIO].data_size =
1223 sizeof(struct glamo_spigpio_platform_data);
1224
1225 mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1226 ARRAY_SIZE(glamo_cells),
1227 glamo->mem, 0);
1228
1229 /* only request the generic, hostbus and memory controller MMIO */
1230 glamo->mem = request_mem_region(glamo->mem->start,
1231 GLAMO_REGOFS_VIDCAP, "glamo-core");
1232 if (!glamo->mem) {
1233 dev_err(&pdev->dev, "failed to request memory region\n");
1234 goto bail_irq;
1235 }
1236
1237 return 0;
1238
1239 bail_irq:
1240 disable_irq(glamo->irq);
1241 set_irq_chained_handler(glamo->irq, NULL);
1242 set_irq_chip_data(glamo->irq, NULL);
1243
1244 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1245 set_irq_flags(irq, 0);
1246 set_irq_chip(irq, NULL);
1247 set_irq_chip_data(irq, NULL);
1248 }
1249
1250 iounmap(glamo->base);
1251 bail_free:
1252 platform_set_drvdata(pdev, NULL);
1253 kfree(glamo);
1254
1255 return rc;
1256 }
1257
1258 static int glamo_remove(struct platform_device *pdev)
1259 {
1260 struct glamo_core *glamo = platform_get_drvdata(pdev);
1261 int irq;
1262
1263 disable_irq(glamo->irq);
1264 set_irq_chained_handler(glamo->irq, NULL);
1265 set_irq_chip_data(glamo->irq, NULL);
1266
1267 for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1268 set_irq_flags(irq, 0);
1269 set_irq_chip(irq, NULL);
1270 set_irq_chip_data(irq, NULL);
1271 }
1272
1273 platform_set_drvdata(pdev, NULL);
1274 mfd_remove_devices(&pdev->dev);
1275 iounmap(glamo->base);
1276 release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1277 kfree(glamo);
1278
1279 return 0;
1280 }
1281
1282 #ifdef CONFIG_PM
1283
1284 static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
1285 {
1286 struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
1287 glamo->suspending = 1;
1288 glamo_power(glamo, GLAMO_POWER_SUSPEND);
1289
1290 return 0;
1291 }
1292
1293 static int glamo_resume(struct platform_device *pdev)
1294 {
1295 struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
1296 glamo_power(glamo, GLAMO_POWER_ON);
1297 glamo->suspending = 0;
1298
1299 return 0;
1300 }
1301
1302 #else
1303 #define glamo_suspend NULL
1304 #define glamo_resume NULL
1305 #endif
1306
1307 static struct platform_driver glamo_driver = {
1308 .probe = glamo_probe,
1309 .remove = glamo_remove,
1310 .suspend = glamo_suspend,
1311 .resume = glamo_resume,
1312 .driver = {
1313 .name = "glamo3362",
1314 .owner = THIS_MODULE,
1315 },
1316 };
1317
1318 static int __devinit glamo_init(void)
1319 {
1320 return platform_driver_register(&glamo_driver);
1321 }
1322
1323 static void __exit glamo_cleanup(void)
1324 {
1325 platform_driver_unregister(&glamo_driver);
1326 }
1327
1328 module_init(glamo_init);
1329 module_exit(glamo_cleanup);
1330
1331 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1332 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1333 MODULE_LICENSE("GPL");
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