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add another batch of ar7 cleanups and an ar7 watchdog timer (thx enrik!). also seems...
[openwrt.git] / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-10-21 16:43:16.316951500 +0200
3 +++ linux.dev/Makefile 2005-11-10 01:10:45.771570000 +0100
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
14 --- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
15 +++ linux.dev/arch/mips/Makefile 2005-11-10 01:10:45.775570250 +0100
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o
25 +SUBDIRS += arch/mips/ar7
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
34 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
35 +++ linux.dev/arch/mips/ar7/Makefile 2005-11-10 01:13:51.443173750 +0100
36 @@ -0,0 +1,14 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
44 +O_TARGET := ar7.o
45 +
46 +obj-y := tnetd73xx_misc.o misc.o
47 +export-objs := misc.o irq.o init.o
48 +obj-y += setup.o irq.o int-handler.o reset.o init.o psp_env.o memory.o promlib.o cmdline.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
52 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-11-10 01:14:16.372731750 +0100
54 @@ -0,0 +1,88 @@
55 +/*
56 + * Carsten Langgaard, carstenl@mips.com
57 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
58 + *
59 + * This program is free software; you can distribute it and/or modify it
60 + * under the terms of the GNU General Public License (Version 2) as
61 + * published by the Free Software Foundation.
62 + *
63 + * This program is distributed in the hope it will be useful, but WITHOUT
64 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
65 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
66 + * for more details.
67 + *
68 + * You should have received a copy of the GNU General Public License along
69 + * with this program; if not, write to the Free Software Foundation, Inc.,
70 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
71 + *
72 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
73 + */
74 +#include <linux/init.h>
75 +#include <linux/string.h>
76 +
77 +#include <asm/bootinfo.h>
78 +
79 +extern int prom_argc;
80 +extern int *_prom_argv;
81 +
82 +/*
83 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
84 + * This macro take care of sign extension.
85 + */
86 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
87 +
88 +char arcs_cmdline[CL_SIZE];
89 +#ifdef CONFIG_CMDLINE_BOOL
90 +char __initdata cfg_cmdline[] = CONFIG_CMDLINE;
91 +#endif
92 +
93 +char * __init prom_getcmdline(void)
94 +{
95 + return &(arcs_cmdline[0]);
96 +}
97 +
98 +
99 +void __init prom_init_cmdline(void)
100 +{
101 + char *cp, *end;
102 + int actr;
103 + char *env_cmdline = prom_getenv("kernel_args");
104 + size_t len;
105 +
106 + actr = 1; /* Always ignore argv[0] */
107 +
108 + cp = end = &(arcs_cmdline[0]);
109 + end += sizeof(arcs_cmdline);
110 +
111 + if (env_cmdline) {
112 + len = strlen(env_cmdline);
113 + if (len > end - cp - 1)
114 + len = end - cp - 1;
115 + strncpy(cp, env_cmdline, len);
116 + cp += len;
117 + *cp++ = ' ';
118 + }
119 +#ifdef CONFIG_CMDLINE_BOOL
120 + else {
121 + len = strlen(cfg_cmdline);
122 + if (len > end - cp - 1)
123 + len = end - cp - 1;
124 + strncpy(cp, cfg_cmdline, len);
125 + cp += len;
126 + *cp++ = ' ';
127 + }
128 +#endif
129 +
130 + while(actr < prom_argc) {
131 + len = strlen(prom_argv(actr));
132 + if (len > end - cp - 1)
133 + break;
134 + strncpy(cp, prom_argv(actr), len);
135 + cp += len;
136 + *cp++ = ' ';
137 + actr++;
138 + }
139 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
140 + --cp;
141 + *cp = '\0';
142 +}
143 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
144 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
145 +++ linux.dev/arch/mips/ar7/init.c 2005-11-10 01:10:45.795571500 +0100
146 @@ -0,0 +1,199 @@
147 +/*
148 + * Carsten Langgaard, carstenl@mips.com
149 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
150 + *
151 + * This program is free software; you can distribute it and/or modify it
152 + * under the terms of the GNU General Public License (Version 2) as
153 + * published by the Free Software Foundation.
154 + *
155 + * This program is distributed in the hope it will be useful, but WITHOUT
156 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
157 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
158 + * for more details.
159 + *
160 + * You should have received a copy of the GNU General Public License along
161 + * with this program; if not, write to the Free Software Foundation, Inc.,
162 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
163 + *
164 + * PROM library initialisation code.
165 + */
166 +#include <linux/config.h>
167 +#include <linux/init.h>
168 +#include <linux/string.h>
169 +#include <linux/kernel.h>
170 +#include <linux/module.h>
171 +
172 +#include <asm/io.h>
173 +#include <asm/mips-boards/prom.h>
174 +#include <asm/mips-boards/generic.h>
175 +
176 +#include <asm/ar7/adam2_env.h>
177 +
178 +int prom_argc;
179 +int *_prom_argv, *_prom_envp;
180 +
181 +/* max # of Adam2 environment variables */
182 +#define MAX_ENV_ENTRY 80
183 +
184 +static t_env_var local_envp[MAX_ENV_ENTRY];
185 +static int env_type = 0;
186 +int init_debug = 0;
187 +
188 +unsigned int max_env_entry;
189 +
190 +extern char *prom_psp_getenv(char *envname);
191 +
192 +static inline char *prom_adam2_getenv(char *envname)
193 +{
194 + /*
195 + * Return a pointer to the given environment variable.
196 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
197 + * in the PROM structures are only 32-bit, so we need some
198 + * workarounds, if we are running in 64-bit mode.
199 + */
200 + int i;
201 + t_env_var *env = (t_env_var *) local_envp;
202 +
203 + if (strcmp("bootloader", envname) == 0)
204 + return "Adam2";
205 +
206 + i = strlen(envname);
207 + while (env->name) {
208 + if(strncmp(envname, env->name, i) == 0) {
209 + return(env->val);
210 + }
211 + env++;
212 + }
213 +
214 + return NULL;
215 +}
216 +
217 +/* XXX "bootloader" won't be returned.
218 + * Better make it an element of local_envp */
219 +static inline t_env_var *
220 +prom_adam2_iterenv(t_env_var *env) {
221 + if (!env)
222 + env = local_envp;
223 + else
224 + env++;
225 + if (env - local_envp > MAX_ENV_ENTRY || !env->name)
226 + return 0;
227 + return env;
228 +}
229 +
230 +char *prom_getenv(char *envname)
231 +{
232 + if (env_type == 1)
233 + return prom_psp_getenv(envname);
234 + else
235 + return prom_adam2_getenv(envname);
236 +}
237 +
238 +t_env_var *
239 +prom_iterenv(t_env_var *last)
240 +{
241 + if (env_type == 1)
242 + return 0; /* not yet implemented */
243 + return prom_adam2_iterenv(last);
244 +}
245 +
246 +static inline unsigned char str2hexnum(unsigned char c)
247 +{
248 + if (c >= '0' && c <= '9')
249 + return c - '0';
250 + if (c >= 'a' && c <= 'f')
251 + return c - 'a' + 10;
252 + return 0; /* foo */
253 +}
254 +
255 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
256 +{
257 + int i;
258 +
259 + for (i = 0; i < 6; i++) {
260 + unsigned char num;
261 +
262 + if((*str == '.') || (*str == ':'))
263 + str++;
264 + num = str2hexnum(*str++) << 4;
265 + num |= (str2hexnum(*str++));
266 + ea[i] = num;
267 + }
268 +}
269 +
270 +int get_ethernet_addr(char *ethernet_addr)
271 +{
272 + char *ethaddr_str;
273 +
274 + ethaddr_str = prom_getenv("ethaddr");
275 + if (!ethaddr_str) {
276 + printk("ethaddr not set in boot prom\n");
277 + return -1;
278 + }
279 + str2eaddr(ethernet_addr, ethaddr_str);
280 +
281 + if (init_debug > 1) {
282 + int i;
283 + printk("get_ethernet_addr: ");
284 + for (i=0; i<5; i++)
285 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
286 + printk("%02x\n", *(ethernet_addr+i));
287 + }
288 +
289 + return 0;
290 +}
291 +
292 +struct psbl_rec {
293 + unsigned int psbl_size;
294 + unsigned int env_base;
295 + unsigned int env_size;
296 + unsigned int ffs_base;
297 + unsigned int ffs_size;
298 +};
299 +
300 +static const char psp_env_version[] = "TIENV0.8";
301 +
302 +int __init prom_init(int argc, char **argv, char **envp)
303 +{
304 + int i;
305 +
306 + t_env_var *env = (t_env_var *) envp;
307 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
308 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
309 +
310 + prom_argc = argc;
311 + _prom_argv = (int *)argv;
312 + _prom_envp = (int *)envp;
313 +
314 + if(strcmp(psp_env, psp_env_version) == 0) {
315 + /* PSPBOOT */
316 +
317 + env_type = 1;
318 + _prom_envp = psp_env;
319 + max_env_entry = (psbl->env_size / 16) - 1;
320 + } else {
321 + /* Copy what we need locally so we are not dependent on
322 + * bootloader RAM. In Adam2, the environment parameters
323 + * are in flash but the table that references them is in
324 + * RAM
325 + */
326 +
327 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
328 + if (env->name) {
329 + local_envp[i].name = env->name;
330 + local_envp[i].val = env->val;
331 + } else {
332 + local_envp[i].name = NULL;
333 + local_envp[i].val = NULL;
334 + }
335 + }
336 + }
337 +
338 + set_io_port_base(0);
339 +
340 + prom_printf("\nLINUX started...\n");
341 + prom_init_cmdline();
342 + prom_meminit();
343 +
344 + return 0;
345 +}
346 diff -urN linux.old/arch/mips/ar7/int-handler.S linux.dev/arch/mips/ar7/int-handler.S
347 --- linux.old/arch/mips/ar7/int-handler.S 1970-01-01 01:00:00.000000000 +0100
348 +++ linux.dev/arch/mips/ar7/int-handler.S 2005-11-10 01:12:43.938955000 +0100
349 @@ -0,0 +1,63 @@
350 +/*
351 + * Copyright 2004 PMC-Sierra Inc.
352 + * Author: Manish Lachwani (lachwani@pmc-sierra.com)
353 + * Adaption for AR7: Enrik Berkhan <enrik@akk.org>
354 + *
355 + * First-level interrupt dispatcher for the TI AR7
356 + *
357 + * This program is free software; you can redistribute it and/or modify it
358 + * under the terms of the GNU General Public License as published by the
359 + * Free Software Foundation; either version 2 of the License, or (at your
360 + * option) any later version.
361 + */
362 +#define __ASSEMBLY__
363 +#include <linux/config.h>
364 +#include <asm/asm.h>
365 +#include <asm/mipsregs.h>
366 +#include <asm/addrspace.h>
367 +#include <asm/regdef.h>
368 +#include <asm/stackframe.h>
369 +
370 +/*
371 + * First level interrupt dispatcher for TI AR7 based boards
372 + */
373 +
374 + .align 5
375 + NESTED(ar7IRQ, PT_SIZE, sp)
376 + SAVE_ALL
377 + CLI
378 + .set at
379 +
380 + mfc0 t0, CP0_CAUSE
381 + mfc0 t2, CP0_STATUS
382 +
383 + and t0, t2
384 +
385 + andi t1, t0, STATUSF_IP2 /* hw0 hardware interrupt */
386 + bnez t1, ll_hw0_irq
387 +
388 + andi t1, t0, STATUSF_IP7 /* R4k CPU timer */
389 + bnez t1, ll_timer_irq
390 +
391 + .set reorder
392 +
393 + /* wrong alarm or masked ... */
394 + j spurious_interrupt
395 + nop
396 + END(ar7IRQ)
397 +
398 + .align 5
399 +
400 +ll_hw0_irq:
401 + li a0, 2
402 + move a1, sp
403 + jal do_IRQ
404 + j ret_from_irq
405 +
406 +ll_timer_irq:
407 + li a0, 7
408 + move a1, sp
409 + jal do_IRQ
410 + j ret_from_irq
411 +
412 +
413 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
414 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
415 +++ linux.dev/arch/mips/ar7/irq.c 2005-11-10 01:12:43.938955000 +0100
416 @@ -0,0 +1,427 @@
417 +/*
418 + * Nitin Dhingra, iamnd@ti.com
419 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
420 + *
421 + * ########################################################################
422 + *
423 + * This program is free software; you can distribute it and/or modify it
424 + * under the terms of the GNU General Public License (Version 2) as
425 + * published by the Free Software Foundation.
426 + *
427 + * This program is distributed in the hope it will be useful, but WITHOUT
428 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
429 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
430 + * for more details.
431 + *
432 + * You should have received a copy of the GNU General Public License along
433 + * with this program; if not, write to the Free Software Foundation, Inc.,
434 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
435 + *
436 + * ########################################################################
437 + *
438 + * Routines for generic manipulation of the interrupts found on the Texas
439 + * Instruments avalanche board
440 + *
441 + */
442 +
443 +#include <linux/init.h>
444 +#include <linux/interrupt.h>
445 +
446 +#include <asm/irq.h>
447 +#include <asm/mipsregs.h>
448 +#include <asm/ar7/ar7.h>
449 +#include <asm/ar7/avalanche_intc.h>
450 +
451 +#define shutdown_avalanche_irq disable_avalanche_irq
452 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
453 +
454 +static unsigned int startup_avalanche_irq(unsigned int irq);
455 +static void end_avalanche_irq(unsigned int irq);
456 +void enable_avalanche_irq(unsigned int irq_nr);
457 +void disable_avalanche_irq(unsigned int irq_nr);
458 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs);
459 +
460 +static struct hw_interrupt_type avalanche_irq_type = {
461 + "AR7",
462 + startup_avalanche_irq,
463 + shutdown_avalanche_irq,
464 + enable_avalanche_irq,
465 + disable_avalanche_irq,
466 + mask_and_ack_avalanche_irq,
467 + end_avalanche_irq,
468 + NULL
469 +};
470 +
471 +static int ar7_irq_base;
472 +
473 +static struct irqaction ar7_hw0_action = {
474 + ar7_hw0_interrupt, 0, 0, "AR7 on hw0", NULL, NULL
475 +};
476 +
477 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
478 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
479 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
480 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
481 +
482 +/*
483 + This remaps interrupts to exist on other channels than the default
484 + channels. essentially we can use the line # as the index for this
485 + array
486 + */
487 +
488 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
489 +unsigned long uni_secondary_interrupt = 0;
490 +
491 +static void end_avalanche_irq(unsigned int irq)
492 +{
493 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
494 + enable_avalanche_irq(irq);
495 +}
496 +
497 +void disable_avalanche_irq(unsigned int irq_nr)
498 +{
499 + unsigned long flags;
500 + unsigned long chan_nr=0;
501 +
502 + save_and_cli(flags);
503 +
504 + /* irq_nr represents the line number for the interrupt. We must
505 + * disable the channel number associated with that line number.
506 + */
507 +
508 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
509 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
510 + else
511 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
512 +
513 + /* disable the interrupt channel bit */
514 +
515 + /* primary interrupt #'s 0-31 */
516 +
517 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
518 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
519 +
520 + /* primary interrupt #'s 32-39 */
521 +
522 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
523 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
524 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
525 +
526 + else /* secondary interrupt #'s 0-31 */
527 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
528 +
529 + restore_flags(flags);
530 +}
531 +
532 +void enable_avalanche_irq(unsigned int irq_nr)
533 +{
534 + unsigned long flags;
535 + unsigned long chan_nr=0;
536 +
537 + save_and_cli(flags);
538 +
539 + /* irq_nr represents the line number for the interrupt. We must
540 + * disable the channel number associated with that line number.
541 + */
542 +
543 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
544 + chan_nr = AVINTNUM(irq_nr);
545 + else
546 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
547 +
548 + /* enable the interrupt channel bit */
549 +
550 + /* primary interrupt #'s 0-31 */
551 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
552 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
553 +
554 + /* primary interrupt #'s 32 throuth 39 */
555 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
556 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
557 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
558 +
559 + else /* secondary interrupt #'s 0-31 */
560 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
561 +
562 + restore_flags(flags);
563 +}
564 +
565 +static unsigned int startup_avalanche_irq(unsigned int irq)
566 +{
567 + enable_avalanche_irq(irq);
568 + return 0; /* never anything pending */
569 +}
570 +
571 +void __init ar7_irq_init(int base)
572 +{
573 + int i;
574 +
575 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
576 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
577 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
578 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
579 +
580 + /* Disable interrupts and clear pending
581 + */
582 +
583 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
584 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
585 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
586 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
587 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
588 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
589 +
590 +
591 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
592 + /* hack for speeding up the pacing. */
593 + printk("the pacing pre-scalar has been set as 600.\n");
594 + avalanche_hw0_ipaceregs->ipacep = 600;
595 + /* Channel to line mapping, Line to Channel mapping */
596 +
597 + for(i = 0; i < 40; i++)
598 + avalanche_int_set(i,i);
599 +
600 + ar7_irq_base = base;
601 + for (i = base; i <= base+40; i++)
602 + {
603 + irq_desc[i].status = IRQ_DISABLED;
604 + irq_desc[i].action = 0;
605 + irq_desc[i].depth = 1;
606 + irq_desc[i].handler = &avalanche_irq_type;
607 + }
608 +
609 + setup_irq(2, &ar7_hw0_action);
610 + set_c0_status(IE_IRQ0);
611 +
612 + return;
613 +}
614 +
615 +void ar7_hw0_interrupt(int interrupt, void *dev, struct pt_regs *regs)
616 +{
617 + int irq;
618 + unsigned long int_line_number, status;
619 + int i, chan_nr = 0;
620 +
621 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
622 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
623 +
624 + if(chan_nr < 32) /* primary 0-31 */
625 + {
626 + if( chan_nr != uni_secondary_interrupt)
627 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
628 +
629 + }
630 +
631 + if((chan_nr < 40) && (chan_nr > 31)) /* primary 32-39 */
632 + {
633 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-32));
634 + }
635 +
636 +
637 + /* If the Priority Interrupt Index Register returns 40 then no
638 + * interrupts are pending
639 + */
640 +
641 + if(chan_nr == 40)
642 + return;
643 +
644 + if(chan_nr == uni_secondary_interrupt) /* secondary 0-31 */
645 + {
646 + status = avalanche_hw0_ecregs->exsr;
647 + for(i=0; i < 32; i++)
648 + {
649 + if (status & 1<<i)
650 + {
651 + /* clear secondary interrupt */
652 + avalanche_hw0_ecregs->excr = 1 << i;
653 + break;
654 + }
655 + }
656 + irq = i+40;
657 +
658 + /* clear the universal secondary interrupt */
659 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
660 +
661 + }
662 + else
663 + irq = chan_nr;
664 +
665 + do_IRQ(irq + ar7_irq_base, regs);
666 + return;
667 +}
668 +
669 +void avalanche_int_set(int channel, int line)
670 +{
671 + switch(channel)
672 + {
673 + case(0):
674 + avalanche_hw0_chregs->cintnr0 = line;
675 + break;
676 + case(1):
677 + avalanche_hw0_chregs->cintnr1 = line;
678 + break;
679 + case(2):
680 + avalanche_hw0_chregs->cintnr2 = line;
681 + break;
682 + case(3):
683 + avalanche_hw0_chregs->cintnr3 = line;
684 + break;
685 + case(4):
686 + avalanche_hw0_chregs->cintnr4 = line;
687 + break;
688 + case(5):
689 + avalanche_hw0_chregs->cintnr5 = line;
690 + break;
691 + case(6):
692 + avalanche_hw0_chregs->cintnr6 = line;
693 + break;
694 + case(7):
695 + avalanche_hw0_chregs->cintnr7 = line;
696 + break;
697 + case(8):
698 + avalanche_hw0_chregs->cintnr8 = line;
699 + break;
700 + case(9):
701 + avalanche_hw0_chregs->cintnr9 = line;
702 + break;
703 + case(10):
704 + avalanche_hw0_chregs->cintnr10 = line;
705 + break;
706 + case(11):
707 + avalanche_hw0_chregs->cintnr11 = line;
708 + break;
709 + case(12):
710 + avalanche_hw0_chregs->cintnr12 = line;
711 + break;
712 + case(13):
713 + avalanche_hw0_chregs->cintnr13 = line;
714 + break;
715 + case(14):
716 + avalanche_hw0_chregs->cintnr14 = line;
717 + break;
718 + case(15):
719 + avalanche_hw0_chregs->cintnr15 = line;
720 + break;
721 + case(16):
722 + avalanche_hw0_chregs->cintnr16 = line;
723 + break;
724 + case(17):
725 + avalanche_hw0_chregs->cintnr17 = line;
726 + break;
727 + case(18):
728 + avalanche_hw0_chregs->cintnr18 = line;
729 + break;
730 + case(19):
731 + avalanche_hw0_chregs->cintnr19 = line;
732 + break;
733 + case(20):
734 + avalanche_hw0_chregs->cintnr20 = line;
735 + break;
736 + case(21):
737 + avalanche_hw0_chregs->cintnr21 = line;
738 + break;
739 + case(22):
740 + avalanche_hw0_chregs->cintnr22 = line;
741 + break;
742 + case(23):
743 + avalanche_hw0_chregs->cintnr23 = line;
744 + break;
745 + case(24):
746 + avalanche_hw0_chregs->cintnr24 = line;
747 + break;
748 + case(25):
749 + avalanche_hw0_chregs->cintnr25 = line;
750 + break;
751 + case(26):
752 + avalanche_hw0_chregs->cintnr26 = line;
753 + break;
754 + case(27):
755 + avalanche_hw0_chregs->cintnr27 = line;
756 + break;
757 + case(28):
758 + avalanche_hw0_chregs->cintnr28 = line;
759 + break;
760 + case(29):
761 + avalanche_hw0_chregs->cintnr29 = line;
762 + break;
763 + case(30):
764 + avalanche_hw0_chregs->cintnr30 = line;
765 + break;
766 + case(31):
767 + avalanche_hw0_chregs->cintnr31 = line;
768 + break;
769 + case(32):
770 + avalanche_hw0_chregs->cintnr32 = line;
771 + break;
772 + case(33):
773 + avalanche_hw0_chregs->cintnr33 = line;
774 + break;
775 + case(34):
776 + avalanche_hw0_chregs->cintnr34 = line;
777 + break;
778 + case(35):
779 + avalanche_hw0_chregs->cintnr35 = line;
780 + break;
781 + case(36):
782 + avalanche_hw0_chregs->cintnr36 = line;
783 + break;
784 + case(37):
785 + avalanche_hw0_chregs->cintnr37 = line;
786 + break;
787 + case(38):
788 + avalanche_hw0_chregs->cintnr38 = line;
789 + break;
790 + case(39):
791 + avalanche_hw0_chregs->cintnr39 = line;
792 + break;
793 + default:
794 + printk("Error: Unknown Avalanche interrupt channel\n");
795 + }
796 +
797 + line_to_channel[line] = channel; /* Suraj check */
798 +
799 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
800 + uni_secondary_interrupt = line;
801 +
802 +}
803 +
804 +
805 +#define AVALANCHE_MAX_PACING_BLK 3
806 +#define AVALANCHE_PACING_LOW_VAL 2
807 +#define AVALANCHE_PACING_HIGH_VAL 63
808 +
809 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
810 + unsigned int pace_value)
811 +{
812 + unsigned int blk_offset;
813 + unsigned long flags;
814 +
815 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
816 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
817 + return (0);
818 +
819 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
820 + return(-1);
821 +
822 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
823 + pace_value < AVALANCHE_PACING_LOW_VAL)
824 + return(-1);
825 +
826 + blk_offset = blk_num*8;
827 +
828 + save_and_cli(flags);
829 +
830 + /* disable the interrupt pacing, if enabled previously */
831 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
832 +
833 + /* clear the pacing map */
834 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
835 +
836 + /* setup the new values */
837 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
838 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
839 +
840 + restore_flags(flags);
841 +
842 + return(0);
843 +}
844 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
845 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
846 +++ linux.dev/arch/mips/ar7/memory.c 2005-11-10 01:14:16.372731750 +0100
847 @@ -0,0 +1,103 @@
848 +/*
849 + * Carsten Langgaard, carstenl@mips.com
850 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
851 + *
852 + * ########################################################################
853 + *
854 + * This program is free software; you can distribute it and/or modify it
855 + * under the terms of the GNU General Public License (Version 2) as
856 + * published by the Free Software Foundation.
857 + *
858 + * This program is distributed in the hope it will be useful, but WITHOUT
859 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
860 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
861 + * for more details.
862 + *
863 + * You should have received a copy of the GNU General Public License along
864 + * with this program; if not, write to the Free Software Foundation, Inc.,
865 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
866 + *
867 + * ########################################################################
868 + *
869 + */
870 +
871 +#include <linux/config.h>
872 +#include <linux/init.h>
873 +#include <linux/mm.h>
874 +#include <linux/bootmem.h>
875 +
876 +#include <asm/bootinfo.h>
877 +#include <asm/page.h>
878 +#include <asm/mips-boards/prom.h>
879 +
880 +extern char _ftext;
881 +extern int preserve_adam2;
882 +
883 +void __init prom_meminit(void)
884 +{
885 + char *memsize_str;
886 + unsigned long memsize, adam2size;
887 +
888 + /* assume block before kernel is used by bootloader */
889 + adam2size = __pa(&_ftext) - PHYS_OFFSET;
890 +
891 + memsize_str = prom_getenv("memsize");
892 + if (!memsize_str) {
893 + memsize = 0x02000000;
894 + } else {
895 + memsize = simple_strtol(memsize_str, NULL, 0);
896 + }
897 +
898 +#if 0
899 + add_memory_region(0x00000000, PHYS_OFFSET, BOOT_MEM_RESERVED);
900 +#endif
901 + add_memory_region(PHYS_OFFSET, adam2size, BOOT_MEM_ROM_DATA);
902 + add_memory_region(PHYS_OFFSET+adam2size, memsize-adam2size,
903 + BOOT_MEM_RAM);
904 +}
905 +
906 +unsigned long __init prom_free_prom_memory (void)
907 +{
908 + int i;
909 + unsigned long freed = 0;
910 + unsigned long addr;
911 +
912 + if (preserve_adam2) {
913 + char *firstfree_str = prom_getenv("firstfreeaddress");
914 + unsigned long firstfree = 0;
915 +
916 + if (firstfree_str)
917 + firstfree = simple_strtol(firstfree_str, NULL, 0);
918 +
919 + if (firstfree && firstfree < (unsigned long)&_ftext) {
920 + printk("Preserving ADAM2 memory.\n");
921 + } else if (firstfree) {
922 + printk("Can't preserve ADAM2 memory, "
923 + "firstfreeaddress = %08lx.\n", firstfree);
924 + preserve_adam2 = 0;
925 + } else {
926 + printk("Can't preserve ADAM2 memory, "
927 + "firstfreeaddress unknown!\n");
928 + preserve_adam2 = 0;
929 + }
930 + }
931 +
932 + if (!preserve_adam2) {
933 + for (i = 0; i < boot_mem_map.nr_map; i++) {
934 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
935 + continue;
936 +
937 + addr = boot_mem_map.map[i].addr;
938 + while (addr < boot_mem_map.map[i].addr
939 + + boot_mem_map.map[i].size) {
940 + ClearPageReserved(virt_to_page(__va(addr)));
941 + set_page_count(virt_to_page(__va(addr)), 1);
942 + free_page((unsigned long)__va(addr));
943 + addr += PAGE_SIZE;
944 + freed += PAGE_SIZE;
945 + }
946 + }
947 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
948 + }
949 + return freed >> PAGE_SHIFT;
950 +}
951 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
952 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
953 +++ linux.dev/arch/mips/ar7/misc.c 2005-11-10 01:12:43.946955500 +0100
954 @@ -0,0 +1,322 @@
955 +#include <asm/ar7/sangam.h>
956 +#include <asm/ar7/avalanche_misc.h>
957 +#include <linux/module.h>
958 +#include <linux/spinlock.h>
959 +
960 +#define TRUE 1
961 +
962 +static unsigned int avalanche_vbus_freq;
963 +
964 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
965 +
966 +/*****************************************************************************
967 + * Reset Control Module.
968 + *****************************************************************************/
969 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
970 + AVALANCHE_RESET_CTRL_T reset_ctrl)
971 +{
972 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
973 +
974 + if(module_reset_bit >= 32 && module_reset_bit < 64)
975 + return;
976 +
977 + if(module_reset_bit >= 64)
978 + {
979 + if(p_remote_vlynq_dev_reset_ctrl) {
980 + p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl);
981 + return;
982 + }
983 + else
984 + return;
985 + }
986 +
987 + if(reset_ctrl == OUT_OF_RESET)
988 + *reset_reg |= 1 << module_reset_bit;
989 + else
990 + *reset_reg &= ~(1 << module_reset_bit);
991 + return;
992 +}
993 +
994 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
995 +{
996 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
997 +
998 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
999 +}
1000 +
1001 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
1002 +{
1003 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
1004 + *sw_reset_reg = mode;
1005 +}
1006 +
1007 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
1008 +
1009 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
1010 +{
1011 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1012 +
1013 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1014 +}
1015 +
1016 +
1017 +/*****************************************************************************
1018 + * Power Control Module
1019 + *****************************************************************************/
1020 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1021 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1022 +
1023 +
1024 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1025 +{
1026 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1027 +
1028 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1029 + /* power down the module */
1030 + *power_reg |= (1 << module_power_bit);
1031 + else
1032 + /* power on the module */
1033 + *power_reg &= (~(1 << module_power_bit));
1034 +}
1035 +
1036 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1037 +{
1038 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1039 +
1040 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1041 +}
1042 +
1043 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1044 +{
1045 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1046 +
1047 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1048 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1049 +}
1050 +
1051 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1052 +{
1053 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1054 +
1055 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1056 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1057 +}
1058 +
1059 +/*****************************************************************************
1060 + * GPIO Control
1061 + *****************************************************************************/
1062 +
1063 +/****************************************************************************
1064 + * FUNCTION: avalanche_gpio_init
1065 + ***************************************************************************/
1066 +void avalanche_gpio_init(void)
1067 +{
1068 + spinlock_t closeLock;
1069 + unsigned int closeFlag;
1070 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1071 + spin_lock_irqsave(&closeLock, closeFlag);
1072 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1073 + spin_unlock_irqrestore(&closeLock, closeFlag);
1074 +}
1075 +
1076 +/****************************************************************************
1077 + * FUNCTION: avalanche_gpio_ctrl
1078 + ***************************************************************************/
1079 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1080 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1081 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1082 +{
1083 + spinlock_t closeLock;
1084 + unsigned int closeFlag;
1085 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1086 +
1087 + if(gpio_pin >= 32)
1088 + return(-1);
1089 +
1090 + spin_lock_irqsave(&closeLock, closeFlag);
1091 +
1092 + if(pin_mode == GPIO_PIN)
1093 + {
1094 + *gpio_ctrl |= (1 << gpio_pin);
1095 +
1096 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1097 +
1098 + if(pin_direction == GPIO_INPUT_PIN)
1099 + *gpio_ctrl |= (1 << gpio_pin);
1100 + else
1101 + *gpio_ctrl &= ~(1 << gpio_pin);
1102 + }
1103 + else /* FUNCTIONAL PIN */
1104 + {
1105 + *gpio_ctrl &= ~(1 << gpio_pin);
1106 + }
1107 +
1108 + spin_unlock_irqrestore(&closeLock, closeFlag);
1109 +
1110 + return (0);
1111 +}
1112 +
1113 +/****************************************************************************
1114 + * FUNCTION: avalanche_gpio_out
1115 + ***************************************************************************/
1116 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1117 +{
1118 + spinlock_t closeLock;
1119 + unsigned int closeFlag;
1120 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1121 +
1122 + if(gpio_pin >= 32)
1123 + return(-1);
1124 +
1125 + spin_lock_irqsave(&closeLock, closeFlag);
1126 + if(value == TRUE)
1127 + *gpio_out |= 1 << gpio_pin;
1128 + else
1129 + *gpio_out &= ~(1 << gpio_pin);
1130 + spin_unlock_irqrestore(&closeLock, closeFlag);
1131 +
1132 + return(0);
1133 +}
1134 +
1135 +/****************************************************************************
1136 + * FUNCTION: avalanche_gpio_in
1137 + ***************************************************************************/
1138 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1139 +{
1140 + spinlock_t closeLock;
1141 + unsigned int closeFlag;
1142 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1143 + int ret_val = 0;
1144 +
1145 + if(gpio_pin >= 32)
1146 + return(-1);
1147 +
1148 + spin_lock_irqsave(&closeLock, closeFlag);
1149 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1150 + spin_unlock_irqrestore(&closeLock, closeFlag);
1151 +
1152 + return (ret_val);
1153 +}
1154 +
1155 +/****************************************************************************
1156 + * FUNCTION: avalanche_gpio_out_val
1157 + ***************************************************************************/
1158 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1159 + unsigned int reg_index)
1160 +{
1161 + spinlock_t closeLock;
1162 + unsigned int closeFlag;
1163 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1164 +
1165 + if(reg_index > 0)
1166 + return(-1);
1167 +
1168 + spin_lock_irqsave(&closeLock, closeFlag);
1169 + *gpio_out &= ~out_mask;
1170 + *gpio_out |= out_val;
1171 + spin_unlock_irqrestore(&closeLock, closeFlag);
1172 +
1173 + return(0);
1174 +}
1175 +
1176 +/****************************************************************************
1177 + * FUNCTION: avalanche_gpio_in_value
1178 + ***************************************************************************/
1179 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1180 +{
1181 + spinlock_t closeLock;
1182 + unsigned int closeFlag;
1183 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1184 +
1185 + if(reg_index > 0)
1186 + return(-1);
1187 +
1188 + spin_lock_irqsave(&closeLock, closeFlag);
1189 + *in_val = *gpio_in;
1190 + spin_unlock_irqrestore(&closeLock, closeFlag);
1191 +
1192 + return (0);
1193 +}
1194 +
1195 +/***********************************************************************
1196 + *
1197 + * Wakeup Control Module for TNETV1050 Communication Processor
1198 + *
1199 + ***********************************************************************/
1200 +
1201 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1202 +
1203 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1204 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1205 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1206 +{
1207 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1208 +
1209 + /* enable/disable */
1210 + if (wakeup_ctrl == WAKEUP_ENABLED)
1211 + /* enable wakeup */
1212 + *wakeup_status_reg |= wakeup_int;
1213 + else
1214 + /* disable wakeup */
1215 + *wakeup_status_reg &= (~wakeup_int);
1216 +
1217 + /* set polarity */
1218 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1219 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1220 + else
1221 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1222 +}
1223 +
1224 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1225 +{
1226 + avalanche_vbus_freq = new_vbus_freq;
1227 +}
1228 +
1229 +unsigned int avalanche_get_vbus_freq()
1230 +{
1231 + return(avalanche_vbus_freq);
1232 +}
1233 +
1234 +unsigned int avalanche_get_chip_version_info()
1235 +{
1236 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1237 +}
1238 +
1239 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1240 +
1241 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1242 +{
1243 + if(p_set_mdix_on_chip_fn)
1244 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1245 + else
1246 + return(-1);
1247 +}
1248 +
1249 +unsigned int avalanche_is_mdix_on_chip(void)
1250 +{
1251 + return(p_set_mdix_on_chip_fn ? 1:0);
1252 +}
1253 +
1254 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1255 +EXPORT_SYMBOL(avalanche_get_reset_status);
1256 +EXPORT_SYMBOL(avalanche_sys_reset);
1257 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1258 +EXPORT_SYMBOL(avalanche_power_ctrl);
1259 +EXPORT_SYMBOL(avalanche_get_power_status);
1260 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1261 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1262 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1263 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1264 +
1265 +EXPORT_SYMBOL(avalanche_gpio_init);
1266 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1267 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1268 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1269 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1270 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1271 +
1272 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1273 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1274 +
1275 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1276 +
1277 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1278 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1279 +++ linux.dev/arch/mips/ar7/platform.h 2005-11-10 01:10:45.799571750 +0100
1280 @@ -0,0 +1,65 @@
1281 +#ifndef _PLATFORM_H_
1282 +#define _PLATFORM_H_
1283 +
1284 +#include <linux/config.h>
1285 +
1286 +
1287 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1288 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1289 + */
1290 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1291 +#define ENV_SPACE_SIZE (10 * 1024)
1292 +#endif
1293 +
1294 +#ifdef CONFIG_MIPS_TNETV1050SDB
1295 +#define TNETV1050SDB
1296 +#define DUAL_FLASH
1297 +#endif
1298 +
1299 +#ifdef CONFIG_MIPS_AR7DB
1300 +#define TNETD73XX_BOARD
1301 +#define AR7DB
1302 +#endif
1303 +
1304 +#ifdef CONFIG_MIPS_AR7RD
1305 +#define TNETD73XX_BOARD
1306 +#define AR7RD
1307 +#endif
1308 +
1309 +#ifdef CONFIG_AR7WRD
1310 +#define TNETD73XX_BOARD
1311 +#define AR7WRD
1312 +#endif
1313 +
1314 +#ifdef CONFIG_MIPS_AR7VWI
1315 +#define TNETD73XX_BOARD
1316 +#define AR7VWi
1317 +#endif
1318 +
1319 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1320 +#ifdef CONFIG_MIPS_AR7VW
1321 +#define TNETD73XX_BOARD
1322 +#define AR7WRD
1323 +#endif
1324 +
1325 +#ifdef CONFIG_MIPS_AR7WI
1326 +#define TNETD73XX_BOARD
1327 +#define AR7Wi
1328 +#endif
1329 +
1330 +#ifdef CONFIG_MIPS_AR7V
1331 +#define TNETD73XX_BOARD
1332 +#define AR7V
1333 +#endif
1334 +
1335 +#ifdef CONFIG_MIPS_AR7V
1336 +#define TNETD73XX_BOARD
1337 +#define AR7V
1338 +#endif
1339 +
1340 +#ifdef CONFIG_MIPS_WA1130
1341 +#define AVALANCHE
1342 +#define WLAN
1343 +#endif
1344 +
1345 +#endif
1346 diff -urN linux.old/arch/mips/ar7/promlib.c linux.dev/arch/mips/ar7/promlib.c
1347 --- linux.old/arch/mips/ar7/promlib.c 1970-01-01 01:00:00.000000000 +0100
1348 +++ linux.dev/arch/mips/ar7/promlib.c 2005-11-10 01:14:16.372731750 +0100
1349 @@ -0,0 +1,48 @@
1350 +/*
1351 + * Carsten Langgaard, carstenl@mips.com
1352 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1353 + *
1354 + * This program is free software; you can distribute it and/or modify it
1355 + * under the terms of the GNU General Public License (Version 2) as
1356 + * published by the Free Software Foundation.
1357 + *
1358 + * This program is distributed in the hope it will be useful, but WITHOUT
1359 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1360 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1361 + * for more details.
1362 + *
1363 + * You should have received a copy of the GNU General Public License along
1364 + * with this program; if not, write to the Free Software Foundation, Inc.,
1365 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1366 + *
1367 + * Putting things on the screen/serial line using Adam2 facilities.
1368 + */
1369 +
1370 +#include <linux/types.h>
1371 +#include <asm/addrspace.h>
1372 +
1373 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1374 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR \
1375 + (AVALANCHE_YAMON_FUNCTION_BASE + 1 * 0x4)
1376 +#define AVALANCHE_YAMON_PROM_EXIT \
1377 + (AVALANCHE_YAMON_FUNCTION_BASE + 8 * 0x4)
1378 +
1379 +void prom_putchar(char c)
1380 +{
1381 + static char buf[1];
1382 + void (*prom_print_str)(unsigned int dummy, char *s, int len) =
1383 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR);
1384 +
1385 + buf[0] = c;
1386 + prom_print_str(1, buf, 1);
1387 + return;
1388 +}
1389 +
1390 +void adam2_exit(int retval)
1391 +{
1392 + void (*yamon_exit)(int retval) =
1393 + (void *)(*(uint32_t *)AVALANCHE_YAMON_PROM_EXIT);
1394 +
1395 + yamon_exit(retval);
1396 + return;
1397 +}
1398 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1399 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1400 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-11-10 01:10:45.799571750 +0100
1401 @@ -0,0 +1,350 @@
1402 +#include <linux/config.h>
1403 +#include <linux/init.h>
1404 +#include <linux/string.h>
1405 +#include <linux/kernel.h>
1406 +#include <linux/module.h>
1407 +#include <asm/io.h>
1408 +
1409 +#include "platform.h"
1410 +
1411 +#define ENV_CELL_SIZE 16
1412 +
1413 +/* control field decode */
1414 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1415 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1416 +
1417 +#define ENV_CTRL_MASK 0x03
1418 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1419 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1420 +
1421 +struct env_variable {
1422 + unsigned char varNum;
1423 + unsigned char ctrl;
1424 + unsigned short chksum;
1425 + unsigned char numCells;
1426 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1427 + * here, continues for
1428 + * numCells.
1429 + */
1430 +};
1431 +
1432 +extern unsigned int max_env_entry;
1433 +
1434 +/* Internal macros */
1435 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1436 +
1437 +typedef enum ENV_VARS {
1438 + env_vars_start = 0,
1439 + CPUFREQ,
1440 + MEMSZ,
1441 + FLASHSZ,
1442 + MODETTY0,
1443 + MODETTY1,
1444 + PROMPT,
1445 + BOOTCFG,
1446 + HWA_0,
1447 +#if !defined (AVALANCHE) || defined(TNETC401B)
1448 + HWA_1,
1449 +#endif
1450 +#if !defined(TNETV1020_BOARD)
1451 + HWA_RNDIS,
1452 +#endif
1453 +#if defined (TNETD73XX_BOARD)
1454 + HWA_3,
1455 +#endif
1456 + IPA,
1457 + IPA_SVR,
1458 + BLINE_MAC0,
1459 +#if !defined (AVALANCHE) || defined(TNETC401B)
1460 + BLINE_MAC1,
1461 +#endif
1462 +#if !defined(TNETV1020_BOARD)
1463 + BLINE_RNDIS,
1464 +#endif
1465 +#if defined (TNETD73XX_BOARD)
1466 + BLINE_ATM,
1467 +#endif
1468 +#if !defined(TNETV1020_BOARD)
1469 + USB_PID,
1470 + USB_VID,
1471 + USB_EPPOLLI,
1472 +#endif
1473 + IPA_GATEWAY,
1474 + SUBNET_MASK,
1475 +#if defined (TNETV1050_BOARD)
1476 + BLINE_ESWITCH,
1477 +#endif
1478 +#if !defined(TNETV1020_BOARD)
1479 + USB_SERIAL,
1480 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
1481 +#endif
1482 + REMOTE_USER,
1483 + REMOTE_PASS,
1484 + REMOTE_DIR,
1485 + SYSFREQ,
1486 + LINK_TIMEOUT,
1487 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1488 + MAC_PORT,
1489 +#endif
1490 + PATH,
1491 + HOSTNAME,
1492 +#ifdef WLAN
1493 + HW_REV_MAJOR,
1494 + HW_REV_MINOR,
1495 + HW_PATCH,
1496 + SW_PATCH,
1497 + SERIAL_NUMBER,
1498 +#endif
1499 + TFTPCFG,
1500 +#if defined (TNETV1050_BOARD)
1501 + HWA_ESWITCH,
1502 +#endif
1503 + /*
1504 + * Add new env variables here.
1505 + * NOTE: New environment variables should always be placed at the end, ie
1506 + * just before env_vars_end.
1507 + */
1508 +
1509 + env_vars_end
1510 +} ENV_VARS;
1511 +
1512 +
1513 +struct env_description {
1514 + ENV_VARS idx;
1515 + char *nm;
1516 + char *alias;
1517 +};
1518 +
1519 +#define ENVSTR(x) #x
1520 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1521 +
1522 +struct env_description env_ns[] = {
1523 + _ENV_ENTRY(env_vars_start), /* start. */
1524 + _ENV_ENTRY(CPUFREQ),
1525 + _ENV_ENTRY(MEMSZ),
1526 + _ENV_ENTRY(FLASHSZ),
1527 + _ENV_ENTRY(MODETTY0),
1528 + _ENV_ENTRY(MODETTY1),
1529 + _ENV_ENTRY(PROMPT),
1530 + _ENV_ENTRY(BOOTCFG),
1531 + _ENV_ENTRY(HWA_0),
1532 +#if !defined (AVALANCHE) || defined(TNETC401B)
1533 + _ENV_ENTRY(HWA_1),
1534 +#endif
1535 +#if !defined(TNETV1020_BOARD)
1536 + _ENV_ENTRY(HWA_RNDIS),
1537 +#endif
1538 +#if defined (TNETD73XX_BOARD)
1539 + _ENV_ENTRY(HWA_3),
1540 +#endif
1541 + _ENV_ENTRY(IPA),
1542 + _ENV_ENTRY(IPA_SVR),
1543 + _ENV_ENTRY(IPA_GATEWAY),
1544 + _ENV_ENTRY(SUBNET_MASK),
1545 + _ENV_ENTRY(BLINE_MAC0),
1546 +#if !defined (AVALANCHE) || defined(TNETC401B)
1547 + _ENV_ENTRY(BLINE_MAC1),
1548 +#endif
1549 +#if !defined(TNETV1020_BOARD)
1550 + _ENV_ENTRY(BLINE_RNDIS),
1551 +#endif
1552 +#if defined (TNETD73XX_BOARD)
1553 + _ENV_ENTRY(BLINE_ATM),
1554 +#endif
1555 +#if !defined(TNETV1020_BOARD)
1556 + _ENV_ENTRY(USB_PID),
1557 + _ENV_ENTRY(USB_VID),
1558 + _ENV_ENTRY(USB_EPPOLLI),
1559 +#endif
1560 +#if defined (TNETV1050_BOARD)
1561 + _ENV_ENTRY(BLINE_ESWITCH),
1562 +#endif
1563 +#if !defined(TNETV1020_BOARD)
1564 + _ENV_ENTRY(USB_SERIAL),
1565 + _ENV_ENTRY(HWA_HRNDIS),
1566 +#endif
1567 + _ENV_ENTRY(REMOTE_USER),
1568 + _ENV_ENTRY(REMOTE_PASS),
1569 + _ENV_ENTRY(REMOTE_DIR),
1570 + _ENV_ENTRY(SYSFREQ),
1571 + _ENV_ENTRY(LINK_TIMEOUT),
1572 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1573 + _ENV_ENTRY(MAC_PORT),
1574 +#endif
1575 + _ENV_ENTRY(PATH),
1576 + _ENV_ENTRY(HOSTNAME),
1577 +#ifdef WLAN
1578 + _ENV_ENTRY(HW_REV_MAJOR),
1579 + _ENV_ENTRY(HW_REV_MINOR),
1580 + _ENV_ENTRY(HW_PATCH),
1581 + _ENV_ENTRY(SW_PATCH),
1582 + _ENV_ENTRY(SERIAL_NUMBER),
1583 +#endif
1584 + _ENV_ENTRY(TFTPCFG),
1585 +#if defined (TNETV1050_BOARD)
1586 + _ENV_ENTRY(HWA_ESWITCH),
1587 +#endif
1588 + /*
1589 + * Add new entries below this.
1590 + */
1591 + /* Adam2 environment name alias. */
1592 + { .idx = IPA, .nm = "my_ipaddress" },
1593 + { .idx = CPUFREQ, .nm = "cpufrequency" },
1594 + { .idx = SYSFREQ, .nm = "sysfrequency" },
1595 + { .idx = HWA_0, .nm = "maca" },
1596 +#ifndef AVALANCHE
1597 + { .idx = HWA_1, .nm = "macb" },
1598 +#endif
1599 + { .idx = MODETTY0, .nm = "modetty0" },
1600 + { .idx = MODETTY1, .nm = "modetty1" },
1601 + { .idx = MEMSZ, .nm = "memsize" },
1602 +
1603 + _ENV_ENTRY(env_vars_end) /* delimiter. */
1604 +};
1605 +
1606 +static inline int var_to_idx(const char* var)
1607 +{
1608 + int ii;
1609 +
1610 + /* go over the list of pre-defined environment variables */
1611 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1612 + /* check if the env variable is listed */
1613 + if (strcmp(env_ns[ii].nm, var) == 0) {
1614 + return env_ns[ii].idx;
1615 + }
1616 +
1617 + /* if an alias is present, check if the alias matches
1618 + * the description
1619 + */
1620 + if (env_ns[ii].alias != NULL) {
1621 + if (strcmp(env_ns[ii].alias, var) == 0) {
1622 + return env_ns[ii].idx;
1623 + }
1624 + }
1625 + }
1626 + return 0;
1627 +}
1628 +
1629 +extern int *_prom_envp;
1630 +
1631 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1632 + * the next read some seconds later is ok. It looks like something is hidding or
1633 + * overlay the flash address at 0xb0000000. Is this possible?
1634 + *
1635 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
1636 + */
1637 +
1638 +static inline struct env_variable* get_var_by_number(int index)
1639 +{
1640 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1641 + volatile unsigned char nr;
1642 + int i;
1643 +
1644 + env_var++; /* skip signature */
1645 +
1646 + i = 0;
1647 + nr = readb(&(env_var->varNum));
1648 +
1649 + while (i < max_env_entry && nr != 0xFF) {
1650 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1651 + if (nr == index) {
1652 + return env_var;
1653 + }
1654 + }
1655 + i++;
1656 + env_var = get_next_block(env_var);
1657 + nr = readb(&(env_var->varNum));
1658 + }
1659 +
1660 + return NULL;
1661 +}
1662 +
1663 +static inline struct env_variable* get_var_by_name(char *var)
1664 +{
1665 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1666 + volatile unsigned char nr;
1667 + int i;
1668 +
1669 + env_var++; /* skip signature */
1670 +
1671 + nr = readb(&(env_var->varNum));
1672 + i = 0;
1673 +
1674 + while (i < max_env_entry && nr != 0xFF) {
1675 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1676 + if (strcmp(var, env_var->data) == 0)
1677 + return env_var;
1678 + }
1679 + i++;
1680 + env_var = get_next_block(env_var);
1681 + nr = readb(&(env_var->varNum));
1682 + }
1683 + return NULL;
1684 +}
1685 +
1686 +static inline struct env_variable* get_var(char *var)
1687 +{
1688 + int index = var_to_idx(var);
1689 +
1690 + if (index)
1691 + return get_var_by_number(index);
1692 + else
1693 + return get_var_by_name(var);
1694 +
1695 + return NULL;
1696 +}
1697 +
1698 +static inline char *get_value(struct env_variable* env_var)
1699 +{
1700 + unsigned char *name;
1701 + unsigned char *value;
1702 + unsigned short chksum;
1703 + int i;
1704 +
1705 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
1706 +
1707 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1708 + name = env_var->data;
1709 + value = env_var->data + strlen(name) + 1;
1710 +
1711 + for(i = 0; i < strlen(name); i++)
1712 + chksum += name[i];
1713 + } else
1714 + value = env_var->data;
1715 +
1716 + for (i = 0; i < strlen(value); i++)
1717 + chksum += value[i];
1718 +
1719 + chksum += env_var->chksum;
1720 + chksum = ~(chksum);
1721 +
1722 + if(chksum != 0) {
1723 + return NULL;
1724 + }
1725 +
1726 + return value;
1727 +}
1728 +
1729 +struct psbl_rec {
1730 + unsigned int psbl_size;
1731 + unsigned int env_base;
1732 + unsigned int env_size;
1733 + unsigned int ffs_base;
1734 + unsigned int ffs_size;
1735 +};
1736 +
1737 +char *prom_psp_getenv(char *envname)
1738 +{
1739 + struct env_variable* env_var;
1740 + char *value;
1741 +
1742 + if (strcmp("bootloader", envname) == 0)
1743 + return "PSPBoot";
1744 +
1745 + if (!(env_var = get_var(envname)))
1746 + return NULL;
1747 +
1748 + value = get_value(env_var);
1749 +
1750 + return value;
1751 +}
1752 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1753 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1754 +++ linux.dev/arch/mips/ar7/reset.c 2005-11-10 01:14:16.372731750 +0100
1755 @@ -0,0 +1,98 @@
1756 +/*
1757 + * Carsten Langgaard, carstenl@mips.com
1758 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1759 + *
1760 + * ########################################################################
1761 + *
1762 + * This program is free software; you can distribute it and/or modify it
1763 + * under the terms of the GNU General Public License (Version 2) as
1764 + * published by the Free Software Foundation.
1765 + *
1766 + * This program is distributed in the hope it will be useful, but WITHOUT
1767 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1768 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1769 + * for more details.
1770 + *
1771 + * You should have received a copy of the GNU General Public License along
1772 + * with this program; if not, write to the Free Software Foundation, Inc.,
1773 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1774 + *
1775 + * ########################################################################
1776 + *
1777 + * Reset the AR7 boards.
1778 + *
1779 + */
1780 +
1781 +#include <linux/init.h>
1782 +#include <linux/kernel.h>
1783 +#include <linux/string.h>
1784 +#include <linux/types.h>
1785 +
1786 +#include <asm/mipsregs.h>
1787 +#include <asm/reboot.h>
1788 +#include <asm/addrspace.h>
1789 +
1790 +int preserve_adam2 = 1;
1791 +
1792 +extern void adam2_exit(int retval);
1793 +
1794 +static void ar7_machine_restart(char *command);
1795 +static void ar7_machine_halt(void);
1796 +static void ar7_machine_power_off(void);
1797 +
1798 +static void ar7_machine_restart(char *command)
1799 +{
1800 + volatile uint32_t *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
1801 +
1802 + *softres_reg = 1;
1803 +}
1804 +
1805 +static void ar7_machine_halt(void)
1806 +{
1807 +
1808 + if (preserve_adam2) {
1809 + set_c0_status(ST0_BEV);
1810 + adam2_exit(0);
1811 + } else {
1812 + /* I'd like to have Alt-SysRq-b work in this state.
1813 + * What's missing here? The timer interrupt is still running.
1814 + * Why doesn't the UART work anymore? */
1815 + while(1) {
1816 + __asm__(".set\tmips3\n\t"
1817 + "wait\n\t"
1818 + ".set\tmips0");
1819 + }
1820 + }
1821 +}
1822 +
1823 +static void ar7_machine_power_off(void)
1824 +{
1825 + volatile uint32_t *power_reg = (void *)(KSEG1ADDR(0x08610A00));
1826 + uint32_t power_state = *power_reg;
1827 +
1828 + /* add something to turn LEDs off? */
1829 +
1830 + power_state &= ~(3 << 30);
1831 + power_state |= (3 << 30); /* power down */
1832 + *power_reg = power_state;
1833 +
1834 + printk("after power down?\n");
1835 +}
1836 +
1837 +void ar7_reboot_setup(void)
1838 +{
1839 + _machine_restart = ar7_machine_restart;
1840 + _machine_halt = ar7_machine_halt;
1841 + _machine_power_off = ar7_machine_power_off;
1842 +}
1843 +
1844 +static int __init ar7_do_preserve_adam2(char *s)
1845 +{
1846 + if (!strcmp(s, "no") || !strcmp(s, "0"))
1847 + preserve_adam2 = 0;
1848 + else
1849 + preserve_adam2 = 1;
1850 + return 1;
1851 +}
1852 +
1853 +__setup("adam2=", ar7_do_preserve_adam2);
1854 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
1855 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1856 +++ linux.dev/arch/mips/ar7/setup.c 2005-11-10 01:12:43.946955500 +0100
1857 @@ -0,0 +1,143 @@
1858 +/*
1859 + * Carsten Langgaard, carstenl@mips.com
1860 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1861 + *
1862 + * This program is free software; you can distribute it and/or modify it
1863 + * under the terms of the GNU General Public License (Version 2) as
1864 + * published by the Free Software Foundation.
1865 + *
1866 + * This program is distributed in the hope it will be useful, but WITHOUT
1867 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1868 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1869 + * for more details.
1870 + *
1871 + * You should have received a copy of the GNU General Public License along
1872 + * with this program; if not, write to the Free Software Foundation, Inc.,
1873 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1874 + */
1875 +
1876 +#include <linux/config.h>
1877 +#include <linux/init.h>
1878 +#include <linux/string.h>
1879 +#include <linux/irq.h>
1880 +
1881 +#include <asm/processor.h>
1882 +#include <asm/irq.h>
1883 +#include <asm/irq_cpu.h>
1884 +#include <asm/time.h>
1885 +#include <asm/mipsregs.h>
1886 +#include <asm/mips-boards/prom.h>
1887 +
1888 +#ifdef CONFIG_KGDB
1889 +extern void rs_kgdb_hook(int);
1890 +extern void breakpoint(void);
1891 +int remote_debug = 0;
1892 +#endif
1893 +
1894 +extern void ar7_reboot_setup(void);
1895 +extern void ar7_irq_init(int);
1896 +extern asmlinkage void ar7IRQ(void);
1897 +
1898 +void ar7_time_init(void)
1899 +{
1900 + /* XXX runtime */
1901 + mips_hpt_frequency = CONFIG_AR7_CPU * 500000;
1902 +}
1903 +
1904 +void ar7_timer_setup(struct irqaction *irq)
1905 +{
1906 + setup_irq(7, irq);
1907 + set_c0_status(IE_IRQ5);
1908 +}
1909 +
1910 +void __init init_IRQ(void)
1911 +{
1912 + init_generic_irq();
1913 + mips_cpu_irq_init(0);
1914 + ar7_irq_init(8);
1915 +
1916 + /* Now safe to set the exception vector. */
1917 + set_except_vector(0, ar7IRQ);
1918 +
1919 +#ifdef CONFIG_KGDB
1920 + if (remote_debug)
1921 + {
1922 + set_debug_traps();
1923 + breakpoint();
1924 + }
1925 +#endif
1926 +}
1927 +
1928 +const char *get_system_type(void)
1929 +{
1930 + return "Texas Instruments AR7";
1931 +}
1932 +
1933 +void __init ar7_setup(void)
1934 +{
1935 +#ifdef CONFIG_KGDB
1936 + int rs_putDebugChar(char);
1937 + char rs_getDebugChar(void);
1938 + extern int (*generic_putDebugChar)(char);
1939 + extern char (*generic_getDebugChar)(void);
1940 +#endif
1941 + char *argptr;
1942 +#ifdef CONFIG_SERIAL_CONSOLE
1943 + argptr = prom_getcmdline();
1944 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1945 + char console[20];
1946 + char *s;
1947 + int i = 0;
1948 +
1949 + s = prom_getenv("modetty0");
1950 + strcpy(console, "38400");
1951 +
1952 + if (s != NULL) {
1953 + while (s[i] >= '0' && s[i] <= '9')
1954 + i++;
1955 +
1956 + if (i > 0) {
1957 + strncpy(console, s, i);
1958 + console[i] = 0;
1959 + }
1960 + }
1961 +
1962 + argptr = prom_getcmdline();
1963 + strcat(argptr, " console=ttyS0,");
1964 + strcat(argptr, console);
1965 + }
1966 +#endif
1967 +
1968 +#ifdef CONFIG_KGDB
1969 + argptr = prom_getcmdline();
1970 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1971 + int line;
1972 + argptr += strlen("kgdb=ttyS");
1973 + if (*argptr != '0' && *argptr != '1')
1974 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1975 + "falling back to /dev/ttyS1\n", *argptr);
1976 + line = *argptr == '0' ? 0 : 1;
1977 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1978 + line ? 1 : 0);
1979 +
1980 + rs_kgdb_hook(line);
1981 + generic_putDebugChar = rs_putDebugChar;
1982 + generic_getDebugChar = rs_getDebugChar;
1983 +
1984 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1985 + "please connect your debugger\n", line ? 1 : 0);
1986 +
1987 + remote_debug = 1;
1988 + /* Breakpoints are in init_IRQ() */
1989 + }
1990 +#endif
1991 +
1992 + argptr = prom_getcmdline();
1993 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1994 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1995 +
1996 + ar7_reboot_setup();
1997 +
1998 + board_time_init = ar7_time_init;
1999 + board_timer_setup = ar7_timer_setup;
2000 +}
2001 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2002 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2003 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-11-10 01:12:43.946955500 +0100
2004 @@ -0,0 +1,921 @@
2005 +/******************************************************************************
2006 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2007 + ******************************************************************************
2008 + * FILE NAME: tnetd73xx_misc.c
2009 + *
2010 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2011 + * FSER Modules API
2012 + * As per TNETD73xx specifications
2013 + *
2014 + * REVISION HISTORY:
2015 + * 27 Nov 02 - Sharath Kumar PSP TII
2016 + * 14 Feb 03 - Anant Gole PSP TII
2017 + *
2018 + * (C) Copyright 2002, Texas Instruments, Inc
2019 + *******************************************************************************/
2020 +
2021 +#include <linux/types.h>
2022 +#include <asm/ar7/tnetd73xx.h>
2023 +#include <asm/ar7/tnetd73xx_misc.h>
2024 +
2025 +/* TNETD73XX Revision */
2026 +u32 tnetd73xx_get_revision(void)
2027 +{
2028 + /* Read Chip revision register - This register is from GPIO module */
2029 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2030 +}
2031 +
2032 +/*****************************************************************************
2033 + * Reset Control Module
2034 + *****************************************************************************/
2035 +
2036 +
2037 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2038 +{
2039 + u32 reset_status;
2040 +
2041 + /* read current reset register */
2042 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2043 +
2044 + if (reset_ctrl == OUT_OF_RESET)
2045 + {
2046 + /* bring module out of reset */
2047 + reset_status |= (1 << reset_module);
2048 + }
2049 + else
2050 + {
2051 + /* put module in reset */
2052 + reset_status &= (~(1 << reset_module));
2053 + }
2054 +
2055 + /* write to the reset register */
2056 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2057 +}
2058 +
2059 +
2060 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2061 +{
2062 + u32 reset_status;
2063 +
2064 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2065 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2066 +}
2067 +
2068 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2069 +{
2070 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2071 +}
2072 +
2073 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2074 +
2075 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2076 +{
2077 + u32 sys_reset_status;
2078 +
2079 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2080 +
2081 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2082 +}
2083 +
2084 +
2085 +/*****************************************************************************
2086 + * Power Control Module
2087 + *****************************************************************************/
2088 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2089 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2090 +
2091 +
2092 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2093 +{
2094 + u32 power_status;
2095 +
2096 + /* read current power down control register */
2097 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2098 +
2099 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2100 + {
2101 + /* power down the module */
2102 + power_status |= (1 << power_module);
2103 + }
2104 + else
2105 + {
2106 + /* power on the module */
2107 + power_status &= (~(1 << power_module));
2108 + }
2109 +
2110 + /* write to the reset register */
2111 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2112 +}
2113 +
2114 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2115 +{
2116 + u32 power_status;
2117 +
2118 + /* read current power down control register */
2119 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2120 +
2121 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2122 +}
2123 +
2124 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2125 +{
2126 + u32 power_status;
2127 +
2128 + /* read current power down control register */
2129 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2130 +
2131 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2132 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2133 +
2134 + /* write to power down control register */
2135 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2136 +}
2137 +
2138 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2139 +{
2140 + u32 power_status;
2141 +
2142 + /* read current power down control register */
2143 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2144 +
2145 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2146 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2147 +
2148 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2149 +}
2150 +
2151 +
2152 +/*****************************************************************************
2153 + * Wakeup Control
2154 + *****************************************************************************/
2155 +
2156 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2157 +
2158 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2159 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2160 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2161 +{
2162 + u32 wakeup_status;
2163 +
2164 + /* read the wakeup control register */
2165 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2166 +
2167 + /* enable/disable */
2168 + if (wakeup_ctrl == WAKEUP_ENABLED)
2169 + {
2170 + /* enable wakeup */
2171 + wakeup_status |= wakeup_int;
2172 + }
2173 + else
2174 + {
2175 + /* disable wakeup */
2176 + wakeup_status &= (~wakeup_int);
2177 + }
2178 +
2179 + /* set polarity */
2180 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2181 + {
2182 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2183 + }
2184 + else
2185 + {
2186 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2187 + }
2188 +
2189 + /* write the wakeup control register */
2190 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2191 +}
2192 +
2193 +
2194 +/*****************************************************************************
2195 + * FSER Control
2196 + *****************************************************************************/
2197 +
2198 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2199 +{
2200 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2201 +}
2202 +
2203 +/*****************************************************************************
2204 + * Clock Control
2205 + *****************************************************************************/
2206 +
2207 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2208 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2209 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2210 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2211 +
2212 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2213 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2214 +
2215 +#define CLKC_PRE_DIVIDER 0x0000001F
2216 +#define CLKC_POST_DIVIDER 0x001F0000
2217 +
2218 +#define CLKC_PLL_STATUS 0x1
2219 +#define CLKC_PLL_FACTOR 0x0000F000
2220 +
2221 +#define BOOTCR_PLL_BYPASS (1 << 5)
2222 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2223 +
2224 +#define MIPS_PLL_SELECT 0x00030000
2225 +#define SYSTEM_PLL_SELECT 0x0000C000
2226 +#define USB_PLL_SELECT 0x000C0000
2227 +#define ADSLSS_PLL_SELECT 0x00C00000
2228 +
2229 +#define MIPS_AFECLKI_SELECT 0x00000000
2230 +#define MIPS_REFCLKI_SELECT 0x00010000
2231 +#define MIPS_XTAL3IN_SELECT 0x00020000
2232 +
2233 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2234 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2235 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2236 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2237 +
2238 +#define USB_SYSPLL_SELECT 0x00000000
2239 +#define USB_REFCLKI_SELECT 0x00040000
2240 +#define USB_XTAL3IN_SELECT 0x00080000
2241 +#define USB_MIPSPLL_SELECT 0x000C0000
2242 +
2243 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2244 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2245 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2246 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2247 +
2248 +#define SYS_MAX CLK_MHZ(150)
2249 +#define SYS_MIN CLK_MHZ(1)
2250 +
2251 +#define MIPS_SYNC_MAX SYS_MAX
2252 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2253 +#define MIPS_MIN CLK_MHZ(1)
2254 +
2255 +#define USB_MAX CLK_MHZ(100)
2256 +#define USB_MIN CLK_MHZ(1)
2257 +
2258 +#define ADSL_MAX CLK_MHZ(180)
2259 +#define ADSL_MIN CLK_MHZ(1)
2260 +
2261 +#define PLL_MUL_MAXFACTOR 15
2262 +#define MAX_DIV_VALUE 32
2263 +#define MIN_DIV_VALUE 1
2264 +
2265 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2266 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2267 +
2268 +#define DIVIDER_LOCK_TIME 10100
2269 +#define PLL_LOCK_TIME 10100 * 75
2270 +
2271 +
2272 +
2273 + /****************************************************************************
2274 + * DATA PURPOSE: PRIVATE Variables
2275 + **************************************************************************/
2276 + static u32 *clk_src[4];
2277 + static u32 mips_pll_out;
2278 + static u32 sys_pll_out;
2279 + static u32 afeclk_inp;
2280 + static u32 refclk_inp;
2281 + static u32 xtal_inp;
2282 + static u32 present_min;
2283 + static u32 present_max;
2284 +
2285 + /* Forward References */
2286 + static u32 find_gcd(u32 min, u32 max);
2287 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2288 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2289 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2290 + static void find_approx(u32 *,u32 *,u32);
2291 +
2292 + /****************************************************************************
2293 + * FUNCTION: tnetd73xx_clkc_init
2294 + ****************************************************************************
2295 + * Description: The routine initializes the internal variables depending on
2296 + * on the sources selected for different clocks.
2297 + ***************************************************************************/
2298 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2299 +{
2300 +
2301 + u32 choice;
2302 +
2303 + afeclk_inp = afeclk;
2304 + refclk_inp = refclk;
2305 + xtal_inp = xtal3in;
2306 +
2307 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2308 + switch(choice)
2309 + {
2310 + case MIPS_AFECLKI_SELECT:
2311 + clk_src[CLKC_MIPS] = &afeclk_inp;
2312 + break;
2313 +
2314 + case MIPS_REFCLKI_SELECT:
2315 + clk_src[CLKC_MIPS] = &refclk_inp;
2316 + break;
2317 +
2318 + case MIPS_XTAL3IN_SELECT:
2319 + clk_src[CLKC_MIPS] = &xtal_inp;
2320 + break;
2321 +
2322 + default :
2323 + clk_src[CLKC_MIPS] = 0;
2324 +
2325 + }
2326 +
2327 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2328 + switch(choice)
2329 + {
2330 + case SYSTEM_AFECLKI_SELECT:
2331 + clk_src[CLKC_SYS] = &afeclk_inp;
2332 + break;
2333 +
2334 + case SYSTEM_REFCLKI_SELECT:
2335 + clk_src[CLKC_SYS] = &refclk_inp;
2336 + break;
2337 +
2338 + case SYSTEM_XTAL3IN_SELECT:
2339 + clk_src[CLKC_SYS] = &xtal_inp;
2340 + break;
2341 +
2342 + case SYSTEM_MIPSPLL_SELECT:
2343 + clk_src[CLKC_SYS] = &mips_pll_out;
2344 + break;
2345 +
2346 + default :
2347 + clk_src[CLKC_SYS] = 0;
2348 +
2349 + }
2350 +
2351 +
2352 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2353 + switch(choice)
2354 + {
2355 + case ADSLSS_AFECLKI_SELECT:
2356 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2357 + break;
2358 +
2359 + case ADSLSS_REFCLKI_SELECT:
2360 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2361 + break;
2362 +
2363 + case ADSLSS_XTAL3IN_SELECT:
2364 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2365 + break;
2366 +
2367 + case ADSLSS_MIPSPLL_SELECT:
2368 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2369 + break;
2370 +
2371 + default :
2372 + clk_src[CLKC_ADSLSS] = 0;
2373 +
2374 + }
2375 +
2376 +
2377 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2378 + switch(choice)
2379 + {
2380 + case USB_SYSPLL_SELECT:
2381 + clk_src[CLKC_USB] = &sys_pll_out ;
2382 + break;
2383 +
2384 + case USB_REFCLKI_SELECT:
2385 + clk_src[CLKC_USB] = &refclk_inp;
2386 + break;
2387 +
2388 + case USB_XTAL3IN_SELECT:
2389 + clk_src[CLKC_USB] = &xtal_inp;
2390 + break;
2391 +
2392 + case USB_MIPSPLL_SELECT:
2393 + clk_src[CLKC_USB] = &mips_pll_out;
2394 + break;
2395 +
2396 + default :
2397 + clk_src[CLKC_USB] = 0;
2398 +
2399 + }
2400 +}
2401 +
2402 +
2403 +
2404 +/****************************************************************************
2405 + * FUNCTION: tnetd73xx_clkc_set_freq
2406 + ****************************************************************************
2407 + * Description: The above routine is called to set the output_frequency of the
2408 + * selected clock(using clk_id) to the required value given
2409 + * by the variable output_freq.
2410 + ***************************************************************************/
2411 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2412 +(
2413 + TNETD73XX_CLKC_ID_T clk_id,
2414 + u32 output_freq
2415 + )
2416 +{
2417 + u32 base_freq;
2418 + u32 multiplier;
2419 + u32 divider;
2420 + u32 min_prediv;
2421 + u32 max_prediv;
2422 + u32 prediv;
2423 + u32 postdiv;
2424 + u32 temp;
2425 +
2426 + /* check if PLLs are bypassed*/
2427 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2428 + {
2429 + return TNETD73XX_ERR_ERROR;
2430 + }
2431 +
2432 + /*check if the requested output_frequency is in valid range*/
2433 + switch( clk_id )
2434 + {
2435 + case CLKC_SYS:
2436 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2437 + {
2438 + return TNETD73XX_ERR_ERROR;
2439 + }
2440 + present_min = SYS_MIN;
2441 + present_max = SYS_MAX;
2442 + break;
2443 +
2444 + case CLKC_MIPS:
2445 + if((output_freq < MIPS_MIN) ||
2446 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2447 + {
2448 + return TNETD73XX_ERR_ERROR;
2449 + }
2450 + present_min = MIPS_MIN;
2451 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2452 + break;
2453 +
2454 + case CLKC_USB:
2455 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2456 + {
2457 + return TNETD73XX_ERR_ERROR;
2458 + }
2459 + present_min = USB_MIN;
2460 + present_max = USB_MAX;
2461 + break;
2462 +
2463 + case CLKC_ADSLSS:
2464 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2465 + {
2466 + return TNETD73XX_ERR_ERROR;
2467 + }
2468 + present_min = ADSL_MIN;
2469 + present_max = ADSL_MAX;
2470 + break;
2471 + }
2472 +
2473 +
2474 + base_freq = get_base_frequency(clk_id);
2475 +
2476 +
2477 + /* check for minimum base frequency value */
2478 + if( base_freq < MIN_PLL_INP_FREQ)
2479 + {
2480 + return TNETD73XX_ERR_ERROR;
2481 + }
2482 +
2483 + get_val(output_freq, base_freq, &multiplier, &divider);
2484 +
2485 + /* check multiplier range */
2486 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2487 + {
2488 + return TNETD73XX_ERR_ERROR;
2489 + }
2490 +
2491 + /* check divider value */
2492 + if( divider == 0 )
2493 + {
2494 + return TNETD73XX_ERR_ERROR;
2495 + }
2496 +
2497 + /*compute minimum and maximum predivider values */
2498 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2499 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2500 +
2501 + /*adjust the value of divider so that it not less than minimum predivider value*/
2502 + if (divider < min_prediv)
2503 + {
2504 + temp = CEIL(min_prediv, divider);
2505 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2506 + {
2507 + return TNETD73XX_ERR_ERROR ;
2508 + }
2509 + else
2510 + {
2511 + multiplier = temp * multiplier;
2512 + divider = min_prediv;
2513 + }
2514 +
2515 + }
2516 +
2517 + /* compute predivider and postdivider values */
2518 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2519 + postdiv = CEIL(divider,prediv);
2520 +
2521 + /*return fail if postdivider value falls out of range */
2522 + if(postdiv > MAX_DIV_VALUE)
2523 + {
2524 + return TNETD73XX_ERR_ERROR;
2525 + }
2526 +
2527 +
2528 + /*write predivider and postdivider values*/
2529 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2530 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2531 +
2532 + /*wait for divider output to stabilise*/
2533 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2534 +
2535 + /*write to PLL clock register*/
2536 +
2537 + if(clk_id == CLKC_SYS)
2538 + {
2539 + /* but before writing put DRAM to hold mode */
2540 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2541 + }
2542 + /*Bring PLL into div mode */
2543 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2544 +
2545 + /*compute the word to be written to PLLCR
2546 + *corresponding to multiplier value
2547 + */
2548 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2549 +
2550 + /* wait till PLL enters div mode */
2551 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2552 + /*nothing*/;
2553 +
2554 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2555 +
2556 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2557 + /*nothing*/;
2558 +
2559 +
2560 + /*wait for External pll to lock*/
2561 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2562 +
2563 + if(clk_id == CLKC_SYS)
2564 + {
2565 + /* Bring DRAM out of hold */
2566 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2567 + }
2568 +
2569 + return TNETD73XX_ERR_OK ;
2570 +}
2571 +
2572 +/****************************************************************************
2573 + * FUNCTION: tnetd73xx_clkc_get_freq
2574 + ****************************************************************************
2575 + * Description: The above routine is called to get the output_frequency of the
2576 + * selected clock( clk_id)
2577 + ***************************************************************************/
2578 +u32 tnetd73xx_clkc_get_freq
2579 +(
2580 + TNETD73XX_CLKC_ID_T clk_id
2581 + )
2582 +{
2583 +
2584 + u32 clk_ctrl_register;
2585 + u32 clk_pll_setting;
2586 + u32 clk_predivider;
2587 + u32 clk_postdivider;
2588 + u16 pll_factor;
2589 + u32 base_freq;
2590 + u32 divider;
2591 +
2592 + base_freq = get_base_frequency(clk_id);
2593 +
2594 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2595 +
2596 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2597 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2598 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2599 +
2600 + divider = clk_predivider * clk_postdivider;
2601 +
2602 +
2603 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2604 + {
2605 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2606 + }
2607 +
2608 +
2609 + else
2610 + {
2611 + /* return the current clock speed based upon the PLL setting */
2612 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2613 +
2614 + /* Get the PLL multiplication factor */
2615 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2616 +
2617 + /* Check if we're in divide mode or multiply mode */
2618 + if((clk_pll_setting & 0x1) == 0)
2619 + {
2620 + /* We're in divide mode */
2621 + if(pll_factor < 0x10)
2622 + return (CEIL(base_freq >> 1, divider));
2623 + else
2624 + return (CEIL(base_freq >> 2, divider));
2625 + }
2626 +
2627 + else /* We're in PLL mode */
2628 + {
2629 + /* See if PLLNDIV & PLLDIV are set */
2630 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2631 + {
2632 + if(clk_pll_setting & 0x1000)
2633 + {
2634 + /* clk = base_freq * k/2 */
2635 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2636 + }
2637 + else
2638 + {
2639 + /* clk = base_freq * (k-1) / 4)*/
2640 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2641 + }
2642 + }
2643 + else
2644 + {
2645 + if(pll_factor < 0x10)
2646 + {
2647 + /* clk = base_freq * k */
2648 + return(CEIL(base_freq * pll_factor, divider));
2649 + }
2650 +
2651 + else
2652 + {
2653 + /* clk = base_freq */
2654 + return(CEIL(base_freq, divider));
2655 + }
2656 + }
2657 + }
2658 + return(0); /* Should never reach here */
2659 +
2660 + }
2661 +
2662 +}
2663 +
2664 +
2665 +/* local helper functions */
2666 +
2667 +/****************************************************************************
2668 + * FUNCTION: get_base_frequency
2669 + ****************************************************************************
2670 + * Description: The above routine is called to get base frequency of the clocks.
2671 + ***************************************************************************/
2672 +
2673 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2674 +{
2675 + /* update the current MIPs PLL output value, if the required
2676 + * source is MIPS PLL
2677 + */
2678 + if ( clk_src[clk_id] == &mips_pll_out)
2679 + {
2680 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2681 + }
2682 +
2683 +
2684 + /* update the current System PLL output value, if the required
2685 + * source is system PLL
2686 + */
2687 + if ( clk_src[clk_id] == &sys_pll_out)
2688 + {
2689 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2690 + }
2691 +
2692 + return (*clk_src[clk_id]);
2693 +
2694 +}
2695 +
2696 +
2697 +
2698 +/****************************************************************************
2699 + * FUNCTION: find_gcd
2700 + ****************************************************************************
2701 + * Description: The above routine is called to find gcd of 2 numbers.
2702 + ***************************************************************************/
2703 +static u32 find_gcd
2704 +(
2705 + u32 min,
2706 + u32 max
2707 + )
2708 +{
2709 + if (max % min == 0)
2710 + {
2711 + return min;
2712 + }
2713 + else
2714 + {
2715 + return find_gcd(max % min, min);
2716 + }
2717 +}
2718 +
2719 +/****************************************************************************
2720 + * FUNCTION: compute_prediv
2721 + ****************************************************************************
2722 + * Description: The above routine is called to compute predivider value
2723 + ***************************************************************************/
2724 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2725 +{
2726 + u16 prediv;
2727 +
2728 + /* return the divider itself it it falls within the range of predivider*/
2729 + if (min <= divider && divider <= max)
2730 + {
2731 + return divider;
2732 + }
2733 +
2734 + /* find a value for prediv such that it is a factor of divider */
2735 + for (prediv = max; prediv >= min ; prediv--)
2736 + {
2737 + if ( (divider % prediv) == 0 )
2738 + {
2739 + return prediv;
2740 + }
2741 + }
2742 +
2743 + /* No such factor exists, return min as prediv */
2744 + return min;
2745 +}
2746 +
2747 +/****************************************************************************
2748 + * FUNCTION: get_val
2749 + ****************************************************************************
2750 + * Description: This routine is called to get values of divider and multiplier.
2751 + ***************************************************************************/
2752 +
2753 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2754 +{
2755 + u32 temp_mul;
2756 + u32 temp_div;
2757 + u32 gcd;
2758 + u32 min_freq;
2759 + u32 max_freq;
2760 +
2761 + /* find gcd of base_freq, output_freq */
2762 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2763 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2764 + gcd = find_gcd(min_freq , max_freq);
2765 +
2766 + if(gcd == 0)
2767 + return; /* ERROR */
2768 +
2769 + /* compute values of multiplier and divider */
2770 + temp_mul = output_freq / gcd;
2771 + temp_div = base_freq / gcd;
2772 +
2773 +
2774 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2775 + if( temp_mul > PLL_MUL_MAXFACTOR )
2776 + {
2777 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2778 + return;
2779 +
2780 + find_approx(&temp_mul,&temp_div,base_freq);
2781 + }
2782 +
2783 + *multiplier = temp_mul;
2784 + *divider = temp_div;
2785 +}
2786 +
2787 +/****************************************************************************
2788 + * FUNCTION: find_approx
2789 + ****************************************************************************
2790 + * Description: This function gets the approx value of num/denom.
2791 + ***************************************************************************/
2792 +
2793 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2794 +{
2795 + u32 num1;
2796 + u32 denom1;
2797 + u32 num2;
2798 + u32 denom2;
2799 + int32_t closest;
2800 + int32_t prev_closest;
2801 + u32 temp_num;
2802 + u32 temp_denom;
2803 + u32 normalize;
2804 + u32 gcd;
2805 + u32 output_freq;
2806 +
2807 + num1 = *num;
2808 + denom1 = *denom;
2809 +
2810 + prev_closest = 0x7fffffff; /* maximum possible value */
2811 + num2 = num1;
2812 + denom2 = denom1;
2813 +
2814 + /* start with max */
2815 + for(temp_num = 15; temp_num >=1; temp_num--)
2816 + {
2817 +
2818 + temp_denom = CEIL(temp_num * denom1, num1);
2819 + output_freq = (temp_num * base_freq) / temp_denom;
2820 +
2821 + if(temp_denom < 1)
2822 + {
2823 + break;
2824 + }
2825 + else
2826 + {
2827 + normalize = CEIL(num1,temp_num);
2828 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2829 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2830 + {
2831 + prev_closest = closest;
2832 + num2 = temp_num;
2833 + denom2 = temp_denom;
2834 + }
2835 +
2836 + }
2837 +
2838 + }
2839 +
2840 + gcd = find_gcd(num2,denom2);
2841 + num2 = num2 / gcd;
2842 + denom2 = denom2 /gcd;
2843 +
2844 + *num = num2;
2845 + *denom = denom2;
2846 +}
2847 +
2848 +
2849 +/*****************************************************************************
2850 + * GPIO Control
2851 + *****************************************************************************/
2852 +
2853 +/****************************************************************************
2854 + * FUNCTION: tnetd73xx_gpio_init
2855 + ***************************************************************************/
2856 +void tnetd73xx_gpio_init()
2857 +{
2858 + /* Bring module out of reset */
2859 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2860 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2861 +}
2862 +
2863 +/****************************************************************************
2864 + * FUNCTION: tnetd73xx_gpio_ctrl
2865 + ***************************************************************************/
2866 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2867 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2868 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2869 +{
2870 + u32 pin_status;
2871 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2872 + if (pin_mode == GPIO_PIN)
2873 + {
2874 + pin_status |= (1 << gpio_pin);
2875 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2876 +
2877 + /* Set pin direction */
2878 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2879 + if (pin_direction == GPIO_INPUT_PIN)
2880 + {
2881 + pin_status |= (1 << gpio_pin);
2882 + }
2883 + else /* GPIO_OUTPUT_PIN */
2884 + {
2885 + pin_status &= (~(1 << gpio_pin));
2886 + }
2887 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2888 + }
2889 + else /* FUNCTIONAL PIN */
2890 + {
2891 + pin_status &= (~(1 << gpio_pin));
2892 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2893 + }
2894 +
2895 +}
2896 +
2897 +/****************************************************************************
2898 + * FUNCTION: tnetd73xx_gpio_out
2899 + ***************************************************************************/
2900 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2901 +{
2902 + u32 pin_value;
2903 +
2904 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2905 + if (value == 1)
2906 + {
2907 + pin_value |= (1 << gpio_pin);
2908 + }
2909 + else
2910 + {
2911 + pin_value &= (~(1 << gpio_pin));
2912 + }
2913 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2914 +}
2915 +
2916 +/****************************************************************************
2917 + * FUNCTION: tnetd73xx_gpio_in
2918 + ***************************************************************************/
2919 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2920 +{
2921 + u32 pin_value;
2922 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2923 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2924 +}
2925 +
2926 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
2927 --- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
2928 +++ linux.dev/arch/mips/config-shared.in 2005-11-10 01:12:43.950955750 +0100
2929 @@ -20,6 +20,16 @@
2930 mainmenu_option next_comment
2931 comment 'Machine selection'
2932 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2933 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2934 +if [ "$CONFIG_AR7" = "y" ]; then
2935 + choice 'Texas Instruments Reference Platform' \
2936 + "AR7DB CONFIG_AR7DB \
2937 + AR7RD CONFIG_AR7RD \
2938 + AR7WRD CONFIG_AR7WRD" AR7DB
2939 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
2940 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
2941 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2942 +fi
2943 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2944 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2945 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2946 @@ -239,6 +249,11 @@
2947 define_bool CONFIG_NONCOHERENT_IO y
2948 define_bool CONFIG_PC_KEYB y
2949 fi
2950 +if [ "$CONFIG_AR7" = "y" ]; then
2951 + define_bool CONFIG_IRQ_CPU y
2952 + define_bool CONFIG_NONCOHERENT_IO y
2953 + define_bool CONFIG_SWAP_IO_SPACE y
2954 +fi
2955 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2956 define_bool CONFIG_IRQ_CPU y
2957 define_bool CONFIG_NONCOHERENT_IO y
2958 @@ -736,6 +751,7 @@
2959 mainmenu_option next_comment
2960 comment 'General setup'
2961 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2962 + "$CONFIG_AR7" = "y" -o \
2963 "$CONFIG_CASIO_E55" = "y" -o \
2964 "$CONFIG_DDB5074" = "y" -o \
2965 "$CONFIG_DDB5476" = "y" -o \
2966 @@ -797,6 +813,7 @@
2967 bool 'Networking support' CONFIG_NET
2968
2969 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2970 + "$CONFIG_AR7" = "y" -o \
2971 "$CONFIG_CASIO_E55" = "y" -o \
2972 "$CONFIG_DECSTATION" = "y" -o \
2973 "$CONFIG_IBM_WORKPAD" = "y" -o \
2974 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
2975 --- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
2976 +++ linux.dev/arch/mips/kernel/head.S 2005-11-10 01:10:45.807572250 +0100
2977 @@ -75,11 +75,11 @@
2978 * size!
2979 */
2980 NESTED(except_vec4, 0, sp)
2981 - .set push
2982 - .set noreorder
2983 -1: j 1b /* Dummy, will be replaced */
2984 - nop
2985 - .set pop
2986 + .set mips2
2987 + lui k0, 0x9400
2988 + ori k0, 0x200
2989 + jr k0
2990 + nop
2991 END(except_vec4)
2992
2993 /*
2994 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
2995 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
2996 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-11-10 01:10:45.811572500 +0100
2997 @@ -40,6 +40,12 @@
2998 extern long __strnlen_user_nocheck_asm(const char *s);
2999 extern long __strnlen_user_asm(const char *s);
3000
3001 +#ifdef CONFIG_AR7
3002 +#include <asm/ar7/adam2_env.h>
3003 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3004 +#endif
3005 +
3006 +
3007 EXPORT_SYMBOL(mips_machtype);
3008 #ifdef CONFIG_EISA
3009 EXPORT_SYMBOL(EISA_bus);
3010 @@ -103,3 +109,10 @@
3011 #endif
3012
3013 EXPORT_SYMBOL(get_wchan);
3014 +
3015 +#ifdef CONFIG_AR7
3016 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3017 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3018 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3019 +#endif
3020 +
3021 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3022 --- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
3023 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-10 01:14:16.376732000 +0100
3024 @@ -38,6 +38,7 @@
3025 #include <asm/io.h>
3026 #include <asm/ptrace.h>
3027 #include <asm/system.h>
3028 +#include <asm/addrspace.h>
3029
3030 struct cpuinfo_mips cpu_data[NR_CPUS];
3031 EXPORT_SYMBOL(cpu_data);
3032 @@ -88,7 +89,7 @@
3033 struct boot_mem_map boot_mem_map;
3034
3035 unsigned char aux_device_present;
3036 -extern char _ftext, _etext, _fdata, _edata, _end;
3037 +extern char _ftext, _etext, _fdata, _edata, _fbss, _end;
3038
3039 static char command_line[CL_SIZE];
3040 char saved_command_line[CL_SIZE];
3041 @@ -116,6 +117,7 @@
3042
3043 static struct resource code_resource = { "Kernel code" };
3044 static struct resource data_resource = { "Kernel data" };
3045 +static struct resource bss_resource = { "Kernel bss" };
3046
3047 asmlinkage void __init
3048 init_arch(int argc, char **argv, char **envp, int *prom_vec)
3049 @@ -272,7 +274,7 @@
3050 for (i = 0; i < boot_mem_map.nr_map; i++) {
3051 unsigned long start, end;
3052
3053 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3054 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3055 continue;
3056
3057 start = PFN_UP(boot_mem_map.map[i].addr);
3058 @@ -320,7 +322,8 @@
3059 #endif
3060
3061 /* Initialize the boot-time allocator with low memory only. */
3062 - bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3063 + bootmap_size = init_bootmem_node(NODE_DATA(0), first_usable_pfn,
3064 + PFN_UP(PHYS_OFFSET), max_low_pfn);
3065
3066 /*
3067 * Register fully available low RAM pages with the bootmem allocator.
3068 @@ -371,11 +374,12 @@
3069 continue;
3070
3071 /* Register lowmem ranges */
3072 - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
3073 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
3074 + size<<PAGE_SHIFT);
3075 }
3076
3077 /* Reserve the bootmap memory. */
3078 - reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3079 + reserve_bootmem_node(NODE_DATA(0), PFN_PHYS(first_usable_pfn), bootmap_size);
3080
3081 #ifdef CONFIG_BLK_DEV_INITRD
3082 /* Board specific code should have set up initrd_start and initrd_end */
3083 @@ -409,6 +413,8 @@
3084 code_resource.end = virt_to_bus(&_etext) - 1;
3085 data_resource.start = virt_to_bus(&_fdata);
3086 data_resource.end = virt_to_bus(&_edata) - 1;
3087 + bss_resource.start = virt_to_bus(&_fbss);
3088 + bss_resource.end = virt_to_bus(&_end) - 1;
3089
3090 /*
3091 * Request address space for all standard RAM.
3092 @@ -448,6 +454,7 @@
3093 */
3094 request_resource(res, &code_resource);
3095 request_resource(res, &data_resource);
3096 + request_resource(res, &bss_resource);
3097 }
3098 }
3099
3100 @@ -494,6 +501,7 @@
3101 void hp_setup(void);
3102 void au1x00_setup(void);
3103 void frame_info_init(void);
3104 + void ar7_setup(void);
3105
3106 frame_info_init();
3107 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3108 @@ -691,6 +699,11 @@
3109 pmc_yosemite_setup();
3110 break;
3111 #endif
3112 +#ifdef CONFIG_AR7
3113 + case MACH_GROUP_UNKNOWN:
3114 + ar7_setup();
3115 + break;
3116 +#endif
3117 default:
3118 panic("Unsupported architecture");
3119 }
3120 diff -urN linux.old/arch/mips/kernel/time.c linux.dev/arch/mips/kernel/time.c
3121 --- linux.old/arch/mips/kernel/time.c 2005-01-19 15:09:29.000000000 +0100
3122 +++ linux.dev/arch/mips/kernel/time.c 2005-11-10 01:12:43.950955750 +0100
3123 @@ -143,7 +143,6 @@
3124 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
3125 write_c0_count(expirelo - cycles_per_jiffy);
3126 write_c0_compare(expirelo);
3127 - write_c0_count(count);
3128 }
3129
3130 int (*mips_timer_state)(void);
3131 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3132 --- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
3133 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-10 01:13:28.301727500 +0100
3134 @@ -869,9 +869,24 @@
3135
3136 exception_handlers[n] = handler;
3137 if (n == 0 && cpu_has_divec) {
3138 + printk(KERN_DEBUG "%s: using long jump via k0 to reach %08x\n",
3139 + __FUNCTION__, handler);
3140 + /* where does the 8 byte limit mentioned in head.S come from??? */
3141 + if (handler > 0x0fffffff) { /* maximum for single J instruction */
3142 + /* lui k0, 0x0000 */
3143 + *(volatile u32 *)(KSEG0+0x200) = 0x3c1a0000 | (handler >> 16);
3144 + /* ori k0, 0x0000 */
3145 + *(volatile u32 *)(KSEG0+0x204) = 0x375a0000 | (handler & 0xffff);
3146 + /* jr k0 */
3147 + *(volatile u32 *)(KSEG0+0x208) = 0x03400008;
3148 + /* nop */
3149 + *(volatile u32 *)(KSEG0+0x20C) = 0x00000000;
3150 + flush_icache_range(KSEG0+0x200, KSEG0+0x210);
3151 + } else {
3152 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3153 (0x03ffffff & (handler >> 2));
3154 - flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3155 + flush_icache_range(KSEG0+0x200, KSEG0+0x204);
3156 + }
3157 }
3158 return (void *)old_handler;
3159 }
3160 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3161 --- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3162 +++ linux.dev/arch/mips/mm/init.c 2005-11-10 01:14:16.376732000 +0100
3163 @@ -235,10 +235,13 @@
3164 #endif
3165 }
3166
3167 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3168 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3169 +
3170 void __init paging_init(void)
3171 {
3172 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3173 - unsigned long max_dma, high, low;
3174 + unsigned long max_dma, high, low, start;
3175
3176 pagetable_init();
3177
3178 @@ -247,7 +250,8 @@
3179 #endif
3180
3181 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3182 - low = max_low_pfn;
3183 + start = START_PFN;
3184 + low = MAX_LOW_PFN - start;
3185 high = highend_pfn;
3186
3187 #ifdef CONFIG_ISA
3188 @@ -270,7 +274,8 @@
3189 zones_size[ZONE_HIGHMEM] = high - low;
3190 #endif
3191
3192 - free_area_init(zones_size);
3193 + free_area_init_node(0, NODE_DATA(0), 0, zones_size,
3194 + start << PAGE_SHIFT, 0);
3195 }
3196
3197 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3198 @@ -283,7 +288,7 @@
3199 for (i = 0; i < boot_mem_map.nr_map; i++) {
3200 unsigned long addr, end;
3201
3202 - if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
3203 + if (boot_mem_map.map[i].type == BOOT_MEM_RESERVED)
3204 /* not usable memory */
3205 continue;
3206
3207 @@ -313,16 +318,17 @@
3208 max_mapnr = num_physpages = highend_pfn;
3209 num_mappedpages = max_low_pfn;
3210 #else
3211 - max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3212 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3213 #endif
3214 - high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3215 -
3216 - totalram_pages += free_all_bootmem();
3217 +
3218 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3219 +
3220 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3221 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3222
3223 reservedpages = ram = 0;
3224 - for (tmp = 0; tmp < max_low_pfn; tmp++)
3225 - if (page_is_ram(tmp)) {
3226 + for (tmp = 0; tmp < max_mapnr; tmp++)
3227 + if (page_is_ram(START_PFN + tmp)) {
3228 ram++;
3229 if (PageReserved(mem_map+tmp))
3230 reservedpages++;
3231 @@ -377,13 +383,13 @@
3232 #endif
3233
3234 extern char __init_begin, __init_end;
3235 -extern void prom_free_prom_memory(void) __init;
3236 +extern unsigned long prom_free_prom_memory(void) __init;
3237
3238 void free_initmem(void)
3239 {
3240 unsigned long addr;
3241
3242 - prom_free_prom_memory ();
3243 + totalram_pages += prom_free_prom_memory ();
3244
3245 addr = (unsigned long) &__init_begin;
3246 while (addr < (unsigned long) &__init_end) {
3247 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3248 --- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
3249 +++ linux.dev/drivers/char/Config.in 2005-11-10 01:10:45.843574500 +0100
3250 @@ -188,6 +188,14 @@
3251 tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3252 fi
3253
3254 +if [ "$CONFIG_AR7" = "y" ]; then
3255 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3256 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3257 +
3258 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3259 + tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3260 +fi
3261 +
3262 source drivers/i2c/Config.in
3263
3264 mainmenu_option next_comment
3265 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3266 --- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
3267 +++ linux.dev/drivers/char/Config.in.orig 2005-11-10 01:10:45.863575750 +0100
3268 @@ -0,0 +1,414 @@
3269 +#
3270 +# Character device configuration
3271 +#
3272 +mainmenu_option next_comment
3273 +comment 'Character devices'
3274 +
3275 +bool 'Virtual terminal' CONFIG_VT
3276 +if [ "$CONFIG_VT" = "y" ]; then
3277 + bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
3278 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3279 + bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3280 + fi
3281 +fi
3282 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3283 +if [ "$CONFIG_SERIAL" = "y" ]; then
3284 + bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
3285 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3286 + bool ' serial port on GSC support' CONFIG_SERIAL_GSC
3287 + fi
3288 + if [ "$CONFIG_IA64" = "y" ]; then
3289 + bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3290 + fi
3291 + if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3292 + tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3293 + tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
3294 + fi
3295 +fi
3296 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3297 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3298 + bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3299 + bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3300 + bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3301 + bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3302 + bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
3303 +fi
3304 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3305 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3306 + tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3307 + tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
3308 + tristate ' Cyclades async mux support' CONFIG_CYCLADES
3309 + if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3310 + bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3311 + fi
3312 + if [ "$CONFIG_X86_64" != "y" ]; then
3313 + tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3314 + if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3315 + tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
3316 + fi
3317 + fi
3318 + dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3319 + tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
3320 + tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3321 + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3322 + dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3323 + fi
3324 + tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
3325 + tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
3326 + tristate ' HDLC line discipline support' CONFIG_N_HDLC
3327 + tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
3328 + if [ "$CONFIG_X86_64" != "y" ]; then
3329 + tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
3330 + if [ "$CONFIG_SPECIALIX" != "n" ]; then
3331 + bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3332 + fi
3333 + tristate ' Specialix SX (and SI) card support' CONFIG_SX
3334 + tristate ' Specialix RIO system support' CONFIG_RIO
3335 + if [ "$CONFIG_RIO" != "n" ]; then
3336 + bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3337 + fi
3338 + fi
3339 + bool ' Stallion multiport serial support' CONFIG_STALDRV
3340 + if [ "$CONFIG_STALDRV" = "y" ]; then
3341 + tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3342 + tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3343 + fi
3344 + if [ "$CONFIG_PARISC" = "y" ]; then
3345 + if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3346 + bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3347 + fi
3348 + if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3349 + bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3350 + fi
3351 + fi
3352 + if [ "$CONFIG_MIPS" = "y" ]; then
3353 + bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3354 + dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3355 + bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3356 + dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3357 + if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3358 + bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3359 + if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3360 + bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3361 + fi
3362 + dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3363 + if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3364 + dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3365 + fi
3366 + if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3367 + "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3368 + define_bool CONFIG_AU1X00_USB_DEVICE y
3369 + fi
3370 + fi
3371 + bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
3372 + if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3373 + bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3374 + fi
3375 + if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3376 + bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3377 + if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3378 + bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3379 + if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3380 + define_bool CONFIG_SERIAL_CONSOLE y
3381 + fi
3382 + fi
3383 + fi
3384 + fi
3385 + if [ "$CONFIG_DECSTATION" = "y" ]; then
3386 + bool ' DECstation serial support' CONFIG_SERIAL_DEC
3387 + dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3388 + dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3389 + dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3390 + fi
3391 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3392 + bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
3393 + fi
3394 + if [ "$CONFIG_IA64" = "y" ]; then
3395 + bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
3396 + if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
3397 + bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
3398 + fi
3399 + if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
3400 + bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
3401 + fi
3402 + fi
3403 +fi
3404 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
3405 + tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
3406 +fi
3407 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3408 + bool 'DC21285 serial port support' CONFIG_SERIAL_21285
3409 + if [ "$CONFIG_SERIAL_21285" = "y" ]; then
3410 + if [ "$CONFIG_OBSOLETE" = "y" ]; then
3411 + bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
3412 + fi
3413 + bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
3414 + fi
3415 + if [ "$CONFIG_PARISC" = "y" ]; then
3416 + bool ' PDC software console support' CONFIG_PDC_CONSOLE
3417 + fi
3418 +fi
3419 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3420 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3421 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3422 + define_bool CONFIG_IT8172_CIR y
3423 + else
3424 + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
3425 + fi
3426 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3427 + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
3428 +fi
3429 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
3430 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
3431 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
3432 + define_bool CONFIG_IT8172_CIR y
3433 + fi
3434 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
3435 +fi
3436 +if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
3437 + bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
3438 +fi
3439 +bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
3440 +if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
3441 + int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
3442 +fi
3443 +if [ "$CONFIG_PARPORT" != "n" ]; then
3444 + dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
3445 + if [ "$CONFIG_PRINTER" != "n" ]; then
3446 + bool ' Support for console on line printer' CONFIG_LP_CONSOLE
3447 + fi
3448 + dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
3449 + dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
3450 +fi
3451 +
3452 +if [ "$CONFIG_PPC64" = "y" ] ; then
3453 + bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
3454 +fi
3455 +if [ "$CONFIG_ALL_PPC" = "y" ]; then
3456 + tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3457 +fi
3458 +
3459 +if [ "$CONFIG_AR7" = "y" ]; then
3460 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3461 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3462 +
3463 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3464 +fi
3465 +
3466 +source drivers/i2c/Config.in
3467 +
3468 +mainmenu_option next_comment
3469 +comment 'Mice'
3470 +tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
3471 +if [ "$CONFIG_BUSMOUSE" != "n" ]; then
3472 + dep_tristate ' ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
3473 + dep_tristate ' Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
3474 + dep_tristate ' Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
3475 + if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
3476 + dep_tristate ' Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
3477 + fi
3478 +# if [ "$CONFIG_DECSTATION" = "y" ]; then
3479 +# dep_bool ' MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
3480 +# fi
3481 +fi
3482 +
3483 +tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
3484 +if [ "$CONFIG_MOUSE" != "n" ]; then
3485 + bool ' PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
3486 + tristate ' C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
3487 + tristate ' PC110 digitizer pad support' CONFIG_PC110_PAD
3488 + tristate ' MK712 touch screen support' CONFIG_MK712_MOUSE
3489 +fi
3490 +endmenu
3491 +
3492 +source drivers/char/joystick/Config.in
3493 +
3494 +tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
3495 +if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
3496 + bool ' Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
3497 + if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
3498 + comment ' Edit configuration parameters in ./include/linux/tpqic02.h!'
3499 + else
3500 + comment ' Setting runtime QIC-02 configuration is done with qic02conf'
3501 + comment ' from the tpqic02-support package. It is available at'
3502 + comment ' metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
3503 + fi
3504 +fi
3505 +
3506 +tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
3507 +dep_mbool ' Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
3508 +dep_tristate ' Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
3509 +dep_tristate ' IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
3510 +dep_tristate ' IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
3511 +
3512 +mainmenu_option next_comment
3513 +comment 'Watchdog Cards'
3514 +bool 'Watchdog Timer Support' CONFIG_WATCHDOG
3515 +if [ "$CONFIG_WATCHDOG" != "n" ]; then
3516 + bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
3517 + tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
3518 + tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
3519 + tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
3520 + tristate ' ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
3521 + tristate ' AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
3522 + tristate ' Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
3523 + if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
3524 + tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG
3525 + if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3526 + tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
3527 + fi
3528 + fi
3529 + tristate ' Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
3530 + tristate ' IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
3531 + tristate ' ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
3532 + tristate ' Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
3533 + tristate ' Mixcom Watchdog' CONFIG_MIXCOMWD
3534 + tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
3535 + dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
3536 + tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
3537 + tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
3538 + tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
3539 + tristate ' WDT Watchdog timer' CONFIG_WDT
3540 + tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
3541 + if [ "$CONFIG_WDT" != "n" ]; then
3542 + bool ' WDT501 features' CONFIG_WDT_501
3543 + if [ "$CONFIG_WDT_501" = "y" ]; then
3544 + bool ' Fan Tachometer' CONFIG_WDT_501_FAN
3545 + fi
3546 + fi
3547 + tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
3548 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3549 + dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
3550 + fi
3551 + if [ "$CONFIG_8xx" = "y" ]; then
3552 + tristate ' MPC8xx Watchdog Timer' CONFIG_8xx_WDT
3553 + fi
3554 +fi
3555 +endmenu
3556 +
3557 +if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
3558 + tristate 'NetWinder thermometer support' CONFIG_DS1620
3559 + tristate 'NetWinder Button' CONFIG_NWBUTTON
3560 + if [ "$CONFIG_NWBUTTON" != "n" ]; then
3561 + bool ' Reboot Using Button' CONFIG_NWBUTTON_REBOOT
3562 + fi
3563 + tristate 'NetWinder flash support' CONFIG_NWFLASH
3564 +fi
3565 +tristate 'NatSemi SCx200 Support' CONFIG_SCx200
3566 +dep_tristate ' NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
3567 +
3568 +if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
3569 + bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
3570 +fi
3571 +
3572 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
3573 + dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
3574 +fi
3575 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
3576 + dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
3577 +fi
3578 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
3579 + "$CONFIG_X86_64" = "y" ]; then
3580 + dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
3581 +fi
3582 +dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
3583 +tristate '/dev/nvram support' CONFIG_NVRAM
3584 +tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
3585 +if [ "$CONFIG_IA64" = "y" ]; then
3586 + bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
3587 +fi
3588 +if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
3589 + bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8
3590 +fi
3591 +if [ "$CONFIG_SGI_IP22" = "y" ]; then
3592 + tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
3593 +fi
3594 +if [ "$CONFIG_SGI_IP27" = "y" ]; then
3595 + tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
3596 +fi
3597 +if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
3598 + tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
3599 +fi
3600 +
3601 +tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
3602 +tristate 'Siemens R3964 line discipline' CONFIG_R3964
3603 +tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
3604 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
3605 + dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
3606 +fi
3607 +
3608 +mainmenu_option next_comment
3609 +comment 'Ftape, the floppy tape device driver'
3610 +tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
3611 +if [ "$CONFIG_FTAPE" != "n" ]; then
3612 + source drivers/char/ftape/Config.in
3613 +fi
3614 +
3615 +endmenu
3616 +
3617 +if [ "$CONFIG_GART_IOMMU" = "y" ]; then
3618 + bool '/dev/agpgart (AGP Support)' CONFIG_AGP
3619 + define_bool CONFIG_AGP_AMD_K8 y
3620 +else
3621 + tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
3622 +fi
3623 +if [ "$CONFIG_AGP" != "n" ]; then
3624 + bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
3625 + bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
3626 + bool ' VIA chipset support' CONFIG_AGP_VIA
3627 + bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
3628 + if [ "$CONFIG_GART_IOMMU" != "y" ]; then
3629 + bool ' AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
3630 + fi
3631 + bool ' Generic SiS support' CONFIG_AGP_SIS
3632 + bool ' ALI chipset support' CONFIG_AGP_ALI
3633 + bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
3634 + if [ "$CONFIG_X86" = "y" ]; then
3635 + bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
3636 + fi
3637 + if [ "$CONFIG_IA64" = "y" ]; then
3638 + bool ' Intel 460GX support' CONFIG_AGP_I460
3639 + bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
3640 + fi
3641 + bool ' ATI IGP chipset support' CONFIG_AGP_ATI
3642 +fi
3643 +
3644 +mainmenu_option next_comment
3645 +comment 'Direct Rendering Manager (XFree86 DRI support)'
3646 +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
3647 +if [ "$CONFIG_DRM" = "y" ]; then
3648 + bool ' Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
3649 + if [ "$CONFIG_DRM_OLD" = "y" ]; then
3650 + comment 'DRM 4.0 drivers'
3651 + source drivers/char/drm-4.0/Config.in
3652 + else
3653 + comment 'DRM 4.1 drivers'
3654 + define_bool CONFIG_DRM_NEW y
3655 + source drivers/char/drm/Config.in
3656 + fi
3657 +fi
3658 +
3659 +if [ "$CONFIG_X86" = "y" ]; then
3660 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3661 +fi
3662 +
3663 +endmenu
3664 +
3665 +if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
3666 + source drivers/char/pcmcia/Config.in
3667 +fi
3668 +if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3669 + tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
3670 + tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
3671 + #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
3672 +fi
3673 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
3674 + tristate ' ITE GPIO' CONFIG_ITE_GPIO
3675 +fi
3676 +
3677 +if [ "$CONFIG_X86" = "y" ]; then
3678 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
3679 + dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
3680 +fi
3681 +
3682 +endmenu
3683 diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
3684 --- linux.old/drivers/char/Makefile 2005-10-21 16:43:16.460960500 +0200
3685 +++ linux.dev/drivers/char/Makefile 2005-11-10 01:10:45.871576250 +0100
3686 @@ -240,6 +240,13 @@
3687 obj-y += joystick/js.o
3688 endif
3689
3690 +#
3691 +# Texas Intruments VLYNQ driver
3692 +#
3693 +
3694 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3695 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3696 +
3697 obj-$(CONFIG_FETCHOP) += fetchop.o
3698 obj-$(CONFIG_BUSMOUSE) += busmouse.o
3699 obj-$(CONFIG_DTLK) += dtlk.o
3700 @@ -340,6 +347,11 @@
3701 obj-y += ipmi/ipmi.o
3702 endif
3703
3704 +subdir-$(CONFIG_AR7_ADAM2) += ticfg
3705 +ifeq ($(CONFIG_AR7_ADAM2),y)
3706 + obj-y += ticfg/ticfg.o
3707 +endif
3708 +
3709 include $(TOPDIR)/Rules.make
3710
3711 fastdep:
3712 diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
3713 --- linux.old/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
3714 +++ linux.dev/drivers/char/Makefile.orig 2005-11-10 01:10:45.871576250 +0100
3715 @@ -0,0 +1,374 @@
3716 +#
3717 +# Makefile for the kernel character device drivers.
3718 +#
3719 +# Note! Dependencies are done automagically by 'make dep', which also
3720 +# removes any old dependencies. DON'T put your own dependencies here
3721 +# unless it's something special (ie not a .c file).
3722 +#
3723 +# Note 2! The CFLAGS definitions are now inherited from the
3724 +# parent makes..
3725 +#
3726 +
3727 +#
3728 +# This file contains the font map for the default (hardware) font
3729 +#
3730 +FONTMAPFILE = cp437.uni
3731 +
3732 +O_TARGET := char.o
3733 +
3734 +obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
3735 +
3736 +# All of the (potential) objects that export symbols.
3737 +# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
3738 +
3739 +export-objs := busmouse.o console.o keyboard.o sysrq.o \
3740 + misc.o pty.o random.o selection.o serial.o \
3741 + sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
3742 + au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
3743 + scx200.o fetchop.o
3744 +
3745 +mod-subdirs := joystick ftape drm drm-4.0 pcmcia
3746 +
3747 +list-multi :=
3748 +
3749 +KEYMAP =defkeymap.o
3750 +KEYBD =pc_keyb.o
3751 +CONSOLE =console.o
3752 +SERIAL =serial.o
3753 +
3754 +ifeq ($(ARCH),s390)
3755 + KEYMAP =
3756 + KEYBD =
3757 + CONSOLE =
3758 + SERIAL =
3759 +endif
3760 +
3761 +ifeq ($(ARCH),mips)
3762 + ifneq ($(CONFIG_PC_KEYB),y)
3763 + KEYBD =
3764 + endif
3765 + ifeq ($(CONFIG_VR41XX_KIU),y)
3766 + ifeq ($(CONFIG_IBM_WORKPAD),y)
3767 + KEYMAP = ibm_workpad_keymap.o
3768 + endif
3769 + ifeq ($(CONFIG_VICTOR_MPC30X),y)
3770 + KEYMAP = victor_mpc30x_keymap.o
3771 + endif
3772 + KEYBD = vr41xx_keyb.o
3773 + endif
3774 +endif
3775 +
3776 +ifeq ($(ARCH),s390x)
3777 + KEYMAP =
3778 + KEYBD =
3779 + CONSOLE =
3780 + SERIAL =
3781 +endif
3782 +
3783 +ifeq ($(ARCH),m68k)
3784 + ifdef CONFIG_AMIGA
3785 + KEYBD = amikeyb.o
3786 + else
3787 + ifndef CONFIG_MAC
3788 + KEYBD =
3789 + endif
3790 + endif
3791 + SERIAL =
3792 +endif
3793 +
3794 +ifeq ($(ARCH),parisc)
3795 + ifdef CONFIG_GSC_PS2
3796 + KEYBD = hp_psaux.o hp_keyb.o
3797 + else
3798 + KEYBD =
3799 + endif
3800 + ifdef CONFIG_SERIAL_MUX
3801 + CONSOLE += mux.o
3802 + endif
3803 + ifdef CONFIG_PDC_CONSOLE
3804 + CONSOLE += pdc_console.o
3805 + endif
3806 +endif
3807 +
3808 +ifdef CONFIG_Q40
3809 + KEYBD += q40_keyb.o
3810 + SERIAL = serial.o
3811 +endif
3812 +
3813 +ifdef CONFIG_APOLLO
3814 + KEYBD += dn_keyb.o
3815 +endif
3816 +
3817 +ifeq ($(ARCH),parisc)
3818 + ifdef CONFIG_GSC_PS2
3819 + KEYBD = hp_psaux.o hp_keyb.o
3820 + else
3821 + KEYBD =
3822 + endif
3823 + ifdef CONFIG_PDC_CONSOLE
3824 + CONSOLE += pdc_console.o
3825 + endif
3826 +endif
3827 +
3828 +ifeq ($(ARCH),arm)
3829 + ifneq ($(CONFIG_PC_KEYMAP),y)
3830 + KEYMAP =
3831 + endif
3832 + ifneq ($(CONFIG_PC_KEYB),y)
3833 + KEYBD =
3834 + endif
3835 +endif
3836 +
3837 +ifeq ($(ARCH),sh)
3838 + KEYMAP =
3839 + KEYBD =
3840 + CONSOLE =
3841 + ifeq ($(CONFIG_SH_HP600),y)
3842 + KEYMAP = defkeymap.o
3843 + KEYBD = scan_keyb.o hp600_keyb.o
3844 + CONSOLE = console.o
3845 + endif
3846 + ifeq ($(CONFIG_SH_DMIDA),y)
3847 + # DMIDA does not connect the HD64465 PS/2 keyboard port
3848 + # but we allow for USB keyboards to be plugged in.
3849 + KEYMAP = defkeymap.o
3850 + KEYBD = # hd64465_keyb.o pc_keyb.o
3851 + CONSOLE = console.o
3852 + endif
3853 + ifeq ($(CONFIG_SH_EC3104),y)
3854 + KEYMAP = defkeymap.o
3855 + KEYBD = ec3104_keyb.o
3856 + CONSOLE = console.o
3857 + endif
3858 + ifeq ($(CONFIG_SH_DREAMCAST),y)
3859 + KEYMAP = defkeymap.o
3860 + KEYBD =
3861 + CONSOLE = console.o
3862 + endif
3863 +endif
3864 +
3865 +ifeq ($(CONFIG_DECSTATION),y)
3866 + KEYMAP =
3867 + KEYBD =
3868 +endif
3869 +
3870 +ifeq ($(CONFIG_BAGET_MIPS),y)
3871 + KEYBD =
3872 + SERIAL = vac-serial.o
3873 +endif
3874 +
3875 +ifeq ($(CONFIG_NINO),y)
3876 + SERIAL =
3877 +endif
3878 +
3879 +ifneq ($(CONFIG_SUN_SERIAL),)
3880 + SERIAL =
3881 +endif
3882 +
3883 +ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
3884 + KEYBD = qtronix.o
3885 + KEYMAP = qtronixmap.o
3886 +endif
3887 +
3888 +ifeq ($(CONFIG_DUMMY_KEYB),y)
3889 + KEYBD = dummy_keyb.o
3890 +endif
3891 +
3892 +obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
3893 +obj-$(CONFIG_SERIAL) += $(SERIAL)
3894 +obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
3895 +obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
3896 +obj-$(CONFIG_SERIAL_21285) += serial_21285.o
3897 +obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
3898 +obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
3899 +obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
3900 +obj-$(CONFIG_SERIAL_DEC) += decserial.o
3901 +
3902 +ifndef CONFIG_SUN_KEYBOARD
3903 + obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
3904 +else
3905 + obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
3906 +endif
3907 +
3908 +obj-$(CONFIG_HIL) += hp_keyb.o
3909 +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
3910 +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
3911 +obj-$(CONFIG_ROCKETPORT) += rocket.o
3912 +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
3913 +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
3914 +obj-$(CONFIG_DIGI) += pcxx.o
3915 +obj-$(CONFIG_DIGIEPCA) += epca.o
3916 +obj-$(CONFIG_CYCLADES) += cyclades.o
3917 +obj-$(CONFIG_STALLION) += stallion.o
3918 +obj-$(CONFIG_ISTALLION) += istallion.o
3919 +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
3920 +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
3921 +obj-$(CONFIG_RISCOM8) += riscom8.o
3922 +obj-$(CONFIG_ISI) += isicom.o
3923 +obj-$(CONFIG_ESPSERIAL) += esp.o
3924 +obj-$(CONFIG_SYNCLINK) += synclink.o
3925 +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
3926 +obj-$(CONFIG_N_HDLC) += n_hdlc.o
3927 +obj-$(CONFIG_SPECIALIX) += specialix.o
3928 +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
3929 +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
3930 +obj-$(CONFIG_SX) += sx.o generic_serial.o
3931 +obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
3932 +obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
3933 +obj-$(CONFIG_SERIAL167) += serial167.o
3934 +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
3935 +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
3936 +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
3937 +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
3938 +obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
3939 +obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
3940 +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
3941 +obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
3942 +obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
3943 +obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
3944 +
3945 +subdir-$(CONFIG_RIO) += rio
3946 +subdir-$(CONFIG_INPUT) += joystick
3947 +
3948 +obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
3949 +obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
3950 +obj-$(CONFIG_PRINTER) += lp.o
3951 +obj-$(CONFIG_TIPAR) += tipar.o
3952 +obj-$(CONFIG_OBMOUSE) += obmouse.o
3953 +
3954 +ifeq ($(CONFIG_INPUT),y)
3955 +obj-y += joystick/js.o
3956 +endif
3957 +
3958 +#
3959 +# Texas Intruments VLYNQ driver
3960 +#
3961 +
3962 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
3963 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
3964 +
3965 +obj-$(CONFIG_FETCHOP) += fetchop.o
3966 +obj-$(CONFIG_BUSMOUSE) += busmouse.o
3967 +obj-$(CONFIG_DTLK) += dtlk.o
3968 +obj-$(CONFIG_R3964) += n_r3964.o
3969 +obj-$(CONFIG_APPLICOM) += applicom.o
3970 +obj-$(CONFIG_SONYPI) += sonypi.o
3971 +obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
3972 +obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
3973 +obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
3974 +obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
3975 +obj-$(CONFIG_ADBMOUSE) += adbmouse.o
3976 +obj-$(CONFIG_PC110_PAD) += pc110pad.o
3977 +obj-$(CONFIG_MK712_MOUSE) += mk712.o
3978 +obj-$(CONFIG_RTC) += rtc.o
3979 +obj-$(CONFIG_GEN_RTC) += genrtc.o
3980 +obj-$(CONFIG_EFI_RTC) += efirtc.o
3981 +obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
3982 +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
3983 +ifeq ($(CONFIG_PPC),)
3984 + obj-$(CONFIG_NVRAM) += nvram.o
3985 +endif
3986 +obj-$(CONFIG_TOSHIBA) += toshiba.o
3987 +obj-$(CONFIG_I8K) += i8k.o
3988 +obj-$(CONFIG_DS1286) += ds1286.o
3989 +obj-$(CONFIG_DS1620) += ds1620.o
3990 +obj-$(CONFIG_DS1742) += ds1742.o
3991 +obj-$(CONFIG_INTEL_RNG) += i810_rng.o
3992 +obj-$(CONFIG_AMD_RNG) += amd768_rng.o
3993 +obj-$(CONFIG_HW_RANDOM) += hw_random.o
3994 +obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
3995 +obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
3996 +
3997 +obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
3998 +obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o
3999 +obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o
4000 +obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o
4001 +obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o
4002 +obj-$(CONFIG_COBALT_LCD) += lcd.o
4003 +
4004 +obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
4005 +
4006 +subdir-$(CONFIG_FTAPE) += ftape
4007 +subdir-$(CONFIG_DRM_OLD) += drm-4.0
4008 +subdir-$(CONFIG_DRM_NEW) += drm
4009 +subdir-$(CONFIG_PCMCIA) += pcmcia
4010 +subdir-$(CONFIG_AGP) += agp
4011 +
4012 +ifeq ($(CONFIG_FTAPE),y)
4013 +obj-y += ftape/ftape.o
4014 +endif
4015 +
4016 +obj-$(CONFIG_H8) += h8.o
4017 +obj-$(CONFIG_PPDEV) += ppdev.o
4018 +obj-$(CONFIG_DZ) += dz.o
4019 +obj-$(CONFIG_NWBUTTON) += nwbutton.o
4020 +obj-$(CONFIG_NWFLASH) += nwflash.o
4021 +obj-$(CONFIG_SCx200) += scx200.o
4022 +obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
4023 +
4024 +# Only one watchdog can succeed. We probe the hardware watchdog
4025 +# drivers first, then the softdog driver. This means if your hardware
4026 +# watchdog dies or is 'borrowed' for some reason the software watchdog
4027 +# still gives you some cover.
4028 +
4029 +obj-$(CONFIG_PCWATCHDOG) += pcwd.o
4030 +obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4031 +obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4032 +obj-$(CONFIG_IB700_WDT) += ib700wdt.o
4033 +obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
4034 +obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
4035 +obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
4036 +obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
4037 +obj-$(CONFIG_WDT) += wdt.o
4038 +obj-$(CONFIG_WDTPCI) += wdt_pci.o
4039 +obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
4040 +obj-$(CONFIG_977_WATCHDOG) += wdt977.o
4041 +obj-$(CONFIG_I810_TCO) += i810-tco.o
4042 +obj-$(CONFIG_MACHZ_WDT) += machzwd.o
4043 +obj-$(CONFIG_SH_WDT) += shwdt.o
4044 +obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
4045 +obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
4046 +obj-$(CONFIG_ALIM1535_WDT) += alim1535d_wdt.o
4047 +obj-$(CONFIG_INDYDOG) += indydog.o
4048 +obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
4049 +obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
4050 +obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
4051 +obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
4052 +obj-$(CONFIG_INDYDOG) += indydog.o
4053 +obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
4054 +
4055 +subdir-$(CONFIG_MWAVE) += mwave
4056 +ifeq ($(CONFIG_MWAVE),y)
4057 + obj-y += mwave/mwave.o
4058 +endif
4059 +
4060 +subdir-$(CONFIG_IPMI_HANDLER) += ipmi
4061 +ifeq ($(CONFIG_IPMI_HANDLER),y)
4062 + obj-y += ipmi/ipmi.o
4063 +endif
4064 +
4065 +include $(TOPDIR)/Rules.make
4066 +
4067 +fastdep:
4068 +
4069 +conmakehash: conmakehash.c
4070 + $(HOSTCC) $(HOSTCFLAGS) -o conmakehash conmakehash.c
4071 +
4072 +consolemap_deftbl.c: $(FONTMAPFILE) conmakehash
4073 + ./conmakehash $(FONTMAPFILE) > consolemap_deftbl.c
4074 +
4075 +consolemap_deftbl.o: consolemap_deftbl.c $(TOPDIR)/include/linux/types.h
4076 +
4077 +.DELETE_ON_ERROR:
4078 +
4079 +defkeymap.c: defkeymap.map
4080 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4081 +
4082 +qtronixmap.c: qtronixmap.map
4083 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4084 +
4085 +ibm_workpad_keymap.c: ibm_workpad_keymap.map
4086 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4087 +
4088 +victor_mpc30x_keymap.c: victor_mpc30x_keymap.map
4089 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4090 diff -urN linux.old/drivers/char/avalanche_vlynq/Makefile linux.dev/drivers/char/avalanche_vlynq/Makefile
4091 --- linux.old/drivers/char/avalanche_vlynq/Makefile 1970-01-01 01:00:00.000000000 +0100
4092 +++ linux.dev/drivers/char/avalanche_vlynq/Makefile 2005-11-10 01:10:45.871576250 +0100
4093 @@ -0,0 +1,16 @@
4094 +#
4095 +# Makefile for the linux kernel.
4096 +#
4097 +# Note! Dependencies are done automagically by 'make dep', which also
4098 +# removes any old dependencies. DON'T put your own dependencies here
4099 +# unless it's something special (ie not a .c file).
4100 +#
4101 +# Note 2! The CFLAGS definitions are now in the main makefile...
4102 +
4103 +O_TARGET := avalanche_vlynq.o
4104 +
4105 +export-objs := vlynq_board.o
4106 +
4107 +obj-y += vlynq_drv.o vlynq_hal.o vlynq_board.o
4108 +
4109 +include $(TOPDIR)/Rules.make
4110 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_board.c linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c
4111 --- linux.old/drivers/char/avalanche_vlynq/vlynq_board.c 1970-01-01 01:00:00.000000000 +0100
4112 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c 2005-11-10 01:10:45.871576250 +0100
4113 @@ -0,0 +1,184 @@
4114 +/*
4115 + * Jeff Harrell, jharrell@ti.com
4116 + * Copyright (C) 2001 Texas Instruments, Inc. All rights reserved.
4117 + *
4118 + * This program is free software; you can distribute it and/or modify it
4119 + * under the terms of the GNU General Public License (Version 2) as
4120 + * published by the Free Software Foundation.
4121 + *
4122 + * This program is distributed in the hope it will be useful, but WITHOUT
4123 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4124 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4125 + * for more details.
4126 + *
4127 + * You should have received a copy of the GNU General Public License along
4128 + * with this program; if not, write to the Free Software Foundation, Inc.,
4129 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4130 + *
4131 + * Texas Instruments Sangam specific setup.
4132 + */
4133 +#include <linux/config.h>
4134 +#include <linux/module.h>
4135 +#include <asm/ar7/sangam.h>
4136 +#include <asm/ar7/avalanche_misc.h>
4137 +#include <asm/ar7/vlynq.h>
4138 +
4139 +#define SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR 30 /* MSB - 1 bit */
4140 +#define SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR 31 /* MSB bit */
4141 +#define SYS_VLYNQ_OPTIONS 0x7F; /* all options*/
4142 +
4143 +/* These defines are board specific */
4144 +
4145 +
4146 +#define VLYNQ0_REMOTE_WINDOW1_OFFSET (0x0C000000)
4147 +#define VLYNQ0_REMOTE_WINDOW1_SIZE (0x500)
4148 +
4149 +
4150 +#define VLYNQ1_REMOTE_WINDOW1_OFFSET (0x0C000000)
4151 +#define VLYNQ1_REMOTE_WINDOW1_SIZE (0x500)
4152 +
4153 +
4154 +extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
4155 +int vlynq_init_status[2] = {0, 0};
4156 +EXPORT_SYMBOL(vlynq_init_status);
4157 +static int reset_hack = 1;
4158 +
4159 +void vlynq_ar7wrd_dev_init()
4160 +{
4161 + *(unsigned long*) AVALANCHE_GPIO_ENBL |= (1<<18);
4162 + vlynq_delay(20000);
4163 + *(unsigned long*) AVALANCHE_GPIO_DIR &= ~(1<<18);
4164 + vlynq_delay(20000);
4165 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT&= ~(1<<18);
4166 + vlynq_delay(50000);
4167 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT|= (1<<18);
4168 + vlynq_delay(50000);
4169 +
4170 + /* Initialize the MIPS host vlynq driver for a given vlynq interface */
4171 + vlynqDevice0.dev_idx = 0; /* first vlynq module - this parameter is for reference only */
4172 + vlynqDevice0.module_base = AVALANCHE_LOW_VLYNQ_CONTROL_BASE; /* vlynq0 module base address */
4173 +
4174 +#if defined(CONFIG_VLYNQ_CLK_LOCAL)
4175 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_LOCAL;
4176 +#else
4177 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_REMOTE;
4178 +#endif
4179 + vlynqDevice0.clk_div = 0x01; /* board/hardware specific */
4180 + vlynqDevice0.state = VLYNQ_DRV_STATE_UNINIT; /* uninitialized module */
4181 +
4182 + /* Populate vlynqDevice0.local_mem & Vlynq0.remote_mem based on system configuration */
4183 + /*Local memory configuration */
4184 +
4185 + /* Demiurg : not good !*/
4186 +#if 0
4187 + vlynqDevice0.local_mem.Txmap= AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE & ~(0xc0000000) ; /* physical address */
4188 + vlynqDevice0.remote_mem.RxOffset[0]= VLYNQ0_REMOTE_WINDOW1_OFFSET; /* This is specific to the board on the other end */
4189 + vlynqDevice0.remote_mem.RxSize[0]=VLYNQ0_REMOTE_WINDOW1_SIZE;
4190 +#endif
4191 +
4192 + /* Demiurg : This is how it should be ! */
4193 + vlynqDevice0.local_mem.Txmap = PHYSADDR(AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE);
4194 +#define VLYNQ_ACX111_MEM_OFFSET 0xC0000000 /* Physical address of ACX111 memory */
4195 +#define VLYNQ_ACX111_MEM_SIZE 0x00040000 /* Total size of the ACX111 memory */
4196 +#define VLYNQ_ACX111_REG_OFFSET 0xF0000000 /* PHYS_ADDR of ACX111 control registers */
4197 +#define VLYNQ_ACX111_REG_SIZE 0x00022000 /* Size of ACX111 registers area, MAC+PHY */
4198 +#define ACX111_VL1_REMOTE_SIZE 0x1000000
4199 + vlynqDevice0.remote_mem.RxOffset[0] = VLYNQ_ACX111_MEM_OFFSET;
4200 + vlynqDevice0.remote_mem.RxSize[0] = VLYNQ_ACX111_MEM_SIZE ;
4201 + vlynqDevice0.remote_mem.RxOffset[1] = VLYNQ_ACX111_REG_OFFSET;
4202 + vlynqDevice0.remote_mem.RxSize[1] = VLYNQ_ACX111_REG_SIZE ;
4203 + vlynqDevice0.remote_mem.Txmap = 0;
4204 + vlynqDevice0.local_mem.RxOffset[0] = AVALANCHE_SDRAM_BASE;
4205 + vlynqDevice0.local_mem.RxSize[0] = ACX111_VL1_REMOTE_SIZE;
4206 +
4207 +
4208 + /* Local interrupt configuration */
4209 + vlynqDevice0.local_irq.intLocal = VLYNQ_INT_LOCAL; /* Host handles vlynq interrupts*/
4210 + vlynqDevice0.local_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* vlynq root isr used */
4211 + vlynqDevice0.local_irq.map_vector = SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR;
4212 + vlynqDevice0.local_irq.intr_ptr = 0; /* Since remote interrupts part of vlynq root isr this is unused */
4213 +
4214 + /* Remote interrupt configuration */
4215 + vlynqDevice0.remote_irq.intLocal = VLYNQ_INT_REMOTE; /* MIPS handles interrupts */
4216 + vlynqDevice0.remote_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* Not significant since MIPS handles interrupts */
4217 + vlynqDevice0.remote_irq.map_vector = SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR;
4218 + vlynqDevice0. remote_irq.intr_ptr = AVALANCHE_INTC_BASE; /* Not significant since MIPS handles interrupts */
4219 +
4220 + if(reset_hack != 1)
4221 + printk("About to re-init the VLYNQ.\n");
4222 +
4223 + if(vlynq_init(&vlynqDevice0,VLYNQ_INIT_PERFORM_ALL)== 0)
4224 + {
4225 + /* Suraj added the following to keep the 1130 going. */
4226 + vlynq_interrupt_vector_set(&vlynqDevice0, 0 /* intr vector line running into 1130 vlynq */,
4227 + 0 /* intr mapped onto the interrupt register on remote vlynq and this vlynq */,
4228 + VLYNQ_REMOTE_DVC, 0 /* polarity active high */, 0 /* interrupt Level triggered */);
4229 +
4230 + /* System wide interrupt is 80 for 1130, please note. */
4231 + vlynq_init_status[0] = 1;
4232 + reset_hack = 2;
4233 + }
4234 + else
4235 + {
4236 + if(reset_hack == 1)
4237 + printk("VLYNQ INIT FAILED: Please try cold reboot. \n");
4238 + else
4239 + printk("Failed to initialize the VLYNQ interface at insmod.\n");
4240 +
4241 + }
4242 +}
4243 +
4244 +void vlynq_dev_init(void)
4245 +{
4246 + volatile unsigned int *reset_base = (unsigned int *) AVALANCHE_RESET_CONTROL_BASE;
4247 +
4248 + *reset_base &= ~((1 << AVALANCHE_LOW_VLYNQ_RESET_BIT)); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT)); */
4249 +
4250 + vlynq_delay(20000);
4251 +
4252 + /* Bring vlynq out of reset if not already done */
4253 + *reset_base |= (1 << AVALANCHE_LOW_VLYNQ_RESET_BIT); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT); */
4254 + vlynq_delay(20000); /* Allowing sufficient time to VLYNQ to settle down.*/
4255 +
4256 + vlynq_ar7wrd_dev_init( );
4257 +
4258 +}
4259 +
4260 +/* This function is board specific and should be ported for each board. */
4261 +void remote_vlynq_dev_reset_ctrl(unsigned int module_reset_bit,
4262 + AVALANCHE_RESET_CTRL_T reset_ctrl)
4263 +{
4264 + if(module_reset_bit >= 32)
4265 + return;
4266 +
4267 + switch(module_reset_bit)
4268 + {
4269 + case 0:
4270 + if(OUT_OF_RESET == reset_ctrl)
4271 + {
4272 + if(reset_hack) return;
4273 +
4274 + vlynq_delay(20000);
4275 + printk("Un-resetting the remote device.\n");
4276 + vlynq_dev_init();
4277 + printk("Re-initialized the VLYNQ.\n");
4278 + reset_hack = 2;
4279 + }
4280 + else if(IN_RESET == reset_ctrl)
4281 + {
4282 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT &= ~(1<<18);
4283 +
4284 + vlynq_delay(20000);
4285 + printk("Resetting the remote device.\n");
4286 + reset_hack = 0;
4287 + }
4288 + else
4289 + ;
4290 + break;
4291 +
4292 + default:
4293 + break;
4294 +
4295 + }
4296 +}
4297 +
4298 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c
4299 --- linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c 1970-01-01 01:00:00.000000000 +0100
4300 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c 2005-11-10 01:10:45.891577500 +0100
4301 @@ -0,0 +1,243 @@
4302 +/******************************************************************************
4303 + * FILE PURPOSE: Vlynq Linux Device Driver Source
4304 + ******************************************************************************
4305 + * FILE NAME: vlynq_drv.c
4306 + *
4307 + * DESCRIPTION: Vlynq Linux Device Driver Source
4308 + *
4309 + * REVISION HISTORY:
4310 + *
4311 + * Date Description Author
4312 + *-----------------------------------------------------------------------------
4313 + * 17 July 2003 Initial Creation Anant Gole
4314 + * 17 Dec 2003 Updates Sharath Kumar
4315 + *
4316 + * (C) Copyright 2003, Texas Instruments, Inc
4317 + *******************************************************************************/
4318 +
4319 +#include <linux/config.h>
4320 +#include <linux/init.h>
4321 +#include <linux/module.h>
4322 +#include <linux/sched.h>
4323 +#include <linux/miscdevice.h>
4324 +#include <linux/smp_lock.h>
4325 +#include <linux/delay.h>
4326 +#include <linux/proc_fs.h>
4327 +#include <linux/capability.h>
4328 +#include <asm/ar7/avalanche_intc.h>
4329 +#include <asm/ar7/sangam.h>
4330 +#include <asm/ar7/vlynq.h>
4331 +
4332 +
4333 +#define TI_VLYNQ_VERSION "0.2"
4334 +
4335 +/* debug on ? */
4336 +#define VLYNQ_DEBUG
4337 +
4338 +/* Macro for debug and error printf's */
4339 +#ifdef VLYNQ_DEBUG
4340 +#define DBGPRINT printk
4341 +#else
4342 +#define DBGPRINT(x)
4343 +#endif
4344 +
4345 +#define ERRPRINT printk
4346 +
4347 +/* Define the max vlynq ports this driver will support.
4348 + Device name strings are statically added here */
4349 +#define MAX_VLYNQ_PORTS 2
4350 +
4351 +
4352 +/* Type define for VLYNQ private structure */
4353 +typedef struct vlynqPriv{
4354 + int irq;
4355 + VLYNQ_DEV *vlynqDevice;
4356 +}VLYNQ_PRIV;
4357 +
4358 +extern int vlynq_init_status[2];
4359 +
4360 +/* Extern Global variable for vlynq devices used in initialization of the vlynq device
4361 + * These variables need to be populated/initialized by the system as part of initialization
4362 + * process. The vlynq enumerator can run at initialization and populate these globals
4363 + */
4364 +
4365 +VLYNQ_DEV vlynqDevice0;
4366 +VLYNQ_DEV vlynqDevice1;
4367 +
4368 +/* Defining dummy macro AVALANCHE_HIGH_VLYNQ_INT to take
4369 + * care of compilation in case of single vlynq device
4370 + */
4371 +
4372 +#ifndef AVALANCHE_HIGH_VLYNQ_INT
4373 +#define AVALANCHE_HIGH_VLYNQ_INT 0
4374 +#endif
4375 +
4376 +
4377 +
4378 +/* vlynq private object */
4379 +VLYNQ_PRIV vlynq_priv[CONFIG_AR7_VLYNQ_PORTS] = {
4380 + { LNXINTNUM(AVALANCHE_LOW_VLYNQ_INT),&vlynqDevice0},
4381 + { LNXINTNUM(AVALANCHE_HIGH_VLYNQ_INT),&vlynqDevice1},
4382 +};
4383 +
4384 +extern void vlynq_dev_init(void);
4385 +
4386 +
4387 +/* =================================== all the operations */
4388 +
4389 +static int
4390 +vlynq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4391 +{
4392 + return 0;
4393 +}
4394 +
4395 +static struct file_operations vlynq_fops = {
4396 + owner: THIS_MODULE,
4397 + ioctl: vlynq_ioctl,
4398 +};
4399 +
4400 +/* Vlynq device object */
4401 +static struct miscdevice vlynq_dev [MAX_VLYNQ_PORTS] = {
4402 + { MISC_DYNAMIC_MINOR , "vlynq0", &vlynq_fops },
4403 + { MISC_DYNAMIC_MINOR , "vlynq1", &vlynq_fops },
4404 +};
4405 +
4406 +
4407 +/* Proc read function */
4408 +static int
4409 +vlynq_read_link_proc(char *buf, char **start, off_t offset, int count, int *eof, void *unused)
4410 +{
4411 + int instance;
4412 + int len = 0;
4413 +
4414 + len += sprintf(buf +len,"VLYNQ Devices : %d\n",CONFIG_AR7_VLYNQ_PORTS);
4415 +
4416 + for(instance =0;instance < CONFIG_AR7_VLYNQ_PORTS;instance++)
4417 + {
4418 + int link_state;
4419 + char *link_msg[] = {" DOWN "," UP "};
4420 +
4421 + if(vlynq_init_status[instance] == 0)
4422 + link_state = 0;
4423 +
4424 + else if (vlynq_link_check(vlynq_priv[instance].vlynqDevice))
4425 + link_state = 1;
4426 +
4427 + else
4428 + link_state = 0;
4429 +
4430 + len += sprintf(buf + len, "VLYNQ %d: Link state: %s\n",instance,link_msg[link_state]);
4431 +
4432 + }
4433 + /* Print info about vlynq device 1 */
4434 +
4435 + return len;
4436 +}
4437 +
4438 +
4439 +/* Proc function to display driver version */
4440 +static int
4441 +vlynq_read_ver_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
4442 +{
4443 + int instance;
4444 + int len=0;
4445 +
4446 + len += sprintf(buf +len,"\nTI Linux VLYNQ Driver Version %s\n",TI_VLYNQ_VERSION);
4447 + return len;
4448 +}
4449 +
4450 +
4451 +
4452 +
4453 +/* Wrapper for vlynq ISR */
4454 +static void lnx_vlynq_root_isr(int irq, void * arg, struct pt_regs *regs)
4455 +{
4456 + vlynq_root_isr(arg);
4457 +}
4458 +
4459 +/* =================================== init and cleanup */
4460 +
4461 +int vlynq_init_module(void)
4462 +{
4463 + int ret;
4464 + int unit = 0;
4465 + int instance_count = CONFIG_AR7_VLYNQ_PORTS;
4466 + volatile int *ptr;
4467 +
4468 + vlynq_dev_init();
4469 +
4470 + DBGPRINT("Vlynq CONFIG_AR7_VLYNQ_PORTS=%d\n", CONFIG_AR7_VLYNQ_PORTS);
4471 + /* If num of configured vlynq ports > supported by driver return error */
4472 + if (instance_count > MAX_VLYNQ_PORTS)
4473 + {
4474 + ERRPRINT("ERROR: vlynq_init_module(): Max %d supported\n", MAX_VLYNQ_PORTS);
4475 + return (-1);
4476 + }
4477 +
4478 + /* register the misc device */
4479 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4480 + {
4481 + ret = misc_register(&vlynq_dev[unit]);
4482 +
4483 + if(ret < 0)
4484 + {
4485 + ERRPRINT("ERROR:Could not register vlynq device:%d\n",unit);
4486 + continue;
4487 + }
4488 + else
4489 + DBGPRINT("Vlynq Device %s registered with minor no %d as misc device. Result=%d\n",
4490 + vlynq_dev[unit].name, vlynq_dev[unit].minor, ret);
4491 +#if 0
4492 +
4493 + DBGPRINT("Calling vlynq init\n");
4494 +
4495 + /* Read the global variable for VLYNQ device structure and initialize vlynq driver */
4496 + ret = vlynq_init(vlynq_priv[unit].vlynqDevice,VLYNQ_INIT_PERFORM_ALL );
4497 +#endif
4498 +
4499 + if(vlynq_init_status[unit] == 0)
4500 + {
4501 + printk("VLYNQ %d : init failed\n",unit);
4502 + continue;
4503 + }
4504 +
4505 + /* Check link before proceeding */
4506 + if (!vlynq_link_check(vlynq_priv[unit].vlynqDevice))
4507 + {
4508 + DBGPRINT("\nError: Vlynq link not available.trying once before Exiting");
4509 + }
4510 + else
4511 + {
4512 + DBGPRINT("Vlynq instance:%d Link UP\n",unit);
4513 +
4514 + /* Install the vlynq local root ISR */
4515 + request_irq(vlynq_priv[unit].irq,lnx_vlynq_root_isr,0,vlynq_dev[unit].name,vlynq_priv[unit].vlynqDevice);
4516 + }
4517 + }
4518 +
4519 + proc_mkdir("avalanche", NULL);
4520 + /* Creating proc entry for the devices */
4521 + create_proc_read_entry("avalanche/vlynq_link", 0, NULL, vlynq_read_link_proc, NULL);
4522 + create_proc_read_entry("avalanche/vlynq_ver", 0, NULL, vlynq_read_ver_proc, NULL);
4523 +
4524 + return 0;
4525 +}
4526 +
4527 +void vlynq_cleanup_module(void)
4528 +{
4529 + int unit = 0;
4530 +
4531 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
4532 + {
4533 + DBGPRINT("vlynq_cleanup_module(): Unregistring misc device %s\n",vlynq_dev[unit].name);
4534 + misc_deregister(&vlynq_dev[unit]);
4535 + }
4536 +
4537 + remove_proc_entry("avalanche/vlynq_link", NULL);
4538 + remove_proc_entry("avalanche/vlynq_ver", NULL);
4539 +}
4540 +
4541 +
4542 +module_init(vlynq_init_module);
4543 +module_exit(vlynq_cleanup_module);
4544 +
4545 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c
4546 --- linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c 1970-01-01 01:00:00.000000000 +0100
4547 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c 2005-11-10 01:10:45.975582750 +0100
4548 @@ -0,0 +1,1214 @@
4549 +/***************************************************************************
4550 +**+----------------------------------------------------------------------+**
4551 +**| **** |**
4552 +**| **** |**
4553 +**| ******o*** |**
4554 +**| ********_///_**** |**
4555 +**| ***** /_//_/ **** |**
4556 +**| ** ** (__/ **** |**
4557 +**| ********* |**
4558 +**| **** |**
4559 +**| *** |**
4560 +**| |**
4561 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
4562 +**| ALL RIGHTS RESERVED |**
4563 +**| |**
4564 +**| Permission is hereby granted to licensees of Texas Instruments |**
4565 +**| Incorporated (TI) products to use this computer program for the sole |**
4566 +**| purpose of implementing a licensee product based on TI products. |**
4567 +**| No other rights to reproduce, use, or disseminate this computer |**
4568 +**| program, whether in part or in whole, are granted. |**
4569 +**| |**
4570 +**| TI makes no representation or warranties with respect to the |**
4571 +**| performance of this computer program, and specifically disclaims |**
4572 +**| any responsibility for any damages, special or consequential, |**
4573 +**| connected with the use of this program. |**
4574 +**| |**
4575 +**+----------------------------------------------------------------------+**
4576 +***************************************************************************/
4577 +
4578 +/***************************************************************************
4579 + * ------------------------------------------------------------------------------
4580 + * Module : vlynq_hal.c
4581 + * Description : This file implements VLYNQ HAL API.
4582 + * ------------------------------------------------------------------------------
4583 + ***************************************************************************/
4584 +
4585 +#include <linux/stddef.h>
4586 +#include <linux/types.h>
4587 +#include <asm/ar7/vlynq.h>
4588 +
4589 +/**** Local Function prototypes *******/
4590 +static int vlynqInterruptInit(VLYNQ_DEV *pdev);
4591 +static void vlynq_configClock(VLYNQ_DEV *pdev);
4592 +
4593 +/*** Second argument must be explicitly type casted to
4594 + * (VLYNQ_DEV*) inside the following functions */
4595 +static void vlynq_local_module_isr(void *arg1, void *arg2, void *arg3);
4596 +static void vlynq_remote_module_isr(void *arg1, void *arg2, void *arg3);
4597 +
4598 +
4599 +volatile int vlynq_delay_value = 0;
4600 +
4601 +/* Code adopted from original vlynq driver */
4602 +void vlynq_delay(unsigned int clktime)
4603 +{
4604 + int i = 0;
4605 + volatile int *ptr = &vlynq_delay_value;
4606 + *ptr = 0;
4607 +
4608 + /* We are assuming that the each cycle takes about
4609 + * 23 assembly instructions. */
4610 + for(i = 0; i < (clktime + 23)/23; i++)
4611 + {
4612 + *ptr = *ptr + 1;
4613 + }
4614 +}
4615 +
4616 +
4617 +/* ----------------------------------------------------------------------------
4618 + * Function : vlynq_configClock()
4619 + * Description: Configures clock settings based on input parameters
4620 + * Adapted from original vlyna driver from Cable
4621 + */
4622 +static void vlynq_configClock(VLYNQ_DEV * pdev)
4623 +{
4624 + unsigned int tmp;
4625 +
4626 + switch( pdev->clk_source)
4627 + {
4628 + case VLYNQ_CLK_SOURCE_LOCAL: /* we output the clock, clk_div in range [1..8]. */
4629 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
4630 + VLYNQ_CTRL_REG = tmp;
4631 + VLYNQ_R_CTRL_REG = 0ul;
4632 + break;
4633 + case VLYNQ_CLK_SOURCE_REMOTE: /* we need to set the clock pin as input */
4634 + VLYNQ_CTRL_REG = 0ul;
4635 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
4636 + VLYNQ_R_CTRL_REG = tmp;
4637 + break;
4638 + default: /* do nothing about the clock, but clear other bits. */
4639 + tmp = ~(VLYNQ_CTL_CLKDIR_MASK | VLYNQ_CTL_CLKDIV_MASK);
4640 + VLYNQ_CTRL_REG &= tmp;
4641 + break;
4642 + }
4643 +}
4644 +
4645 + /* ----------------------------------------------------------------------------
4646 + * Function : vlynq_link_check()
4647 + * Description: This function checks the current VLYNQ for a link.
4648 + * An arbitrary amount of time is allowed for the link to come up .
4649 + * Returns 0 for "no link / failure " and 1 for "link available".
4650 + * -----------------------------------------------------------------------------
4651 + */
4652 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev)
4653 +{
4654 + /*sleep for 64 cycles, allow link to come up*/
4655 + vlynq_delay(64);
4656 +
4657 + /* check status register return OK if link is found. */
4658 + if (VLYNQ_STATUS_REG & VLYNQ_STS_LINK_MASK)
4659 + {
4660 + return 1; /* Link Available */
4661 + }
4662 + else
4663 + {
4664 + return 0; /* Link Failure */
4665 + }
4666 +}
4667 +
4668 +/* ----------------------------------------------------------------------------
4669 + * Function : vlynq_init()
4670 + * Description: Initialization function accepting paramaters for VLYNQ module
4671 + * initialization. The Options bitmap decides what operations are performed
4672 + * as a part of initialization. The Input parameters are obtained through the
4673 + * sub fields of VLYNQ_DEV structure.
4674 + */
4675 +
4676 +int vlynq_init(VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options)
4677 +{
4678 + unsigned int map;
4679 + unsigned int val=0,cnt,tmp;
4680 + unsigned int counter=0;
4681 + VLYNQ_INTERRUPT_CNTRL *intSetting=NULL;
4682 +
4683 + /* validate arguments */
4684 + if( VLYNQ_OUTRANGE(pdev->clk_source, VLYNQ_CLK_SOURCE_REMOTE, VLYNQ_CLK_SOURCE_NONE) ||
4685 + VLYNQ_OUTRANGE(pdev->clk_div, 8, 1) )
4686 + {
4687 + return VLYNQ_INVALID_ARG;
4688 + }
4689 +
4690 + /** perform all sanity checks first **/
4691 + if(pdev->state != VLYNQ_DRV_STATE_UNINIT)
4692 + return VLYNQ_INVALID_DRV_STATE;
4693 +
4694 + /** Initialize local and remote register set addresses- additional
4695 + * provision to access the registers directly if need be */
4696 + pdev->local = (VLYNQ_REG_SET*)pdev->module_base;
4697 + pdev->remote = (VLYNQ_REG_SET*) (pdev->module_base + VLYNQ_REMOTE_REGS_OFFSET);
4698 +
4699 + /* Detect faulty int configuration that might induce int pkt looping */
4700 + if ( (options & VLYNQ_INIT_LOCAL_INTERRUPTS) && (options & VLYNQ_INIT_REMOTE_INTERRUPTS) )
4701 + {
4702 + /* case when both local and remote are configured */
4703 + if((pdev->local_irq.intLocal== VLYNQ_INT_REMOTE ) /* interrupts transfered to remote from local */
4704 + && (pdev->remote_irq.intLocal== VLYNQ_INT_REMOTE) /* interrupts transfered from remote to local */
4705 + && ((pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) || (pdev->remote_irq.intRemote == VLYNQ_INT_ROOT_ISR)) )
4706 + {
4707 + return (VLYNQ_INT_CONFIG_ERR);
4708 + }
4709 + }
4710 +
4711 + pdev->state = VLYNQ_DRV_STATE_ININIT;
4712 + pdev->intCount = 0;
4713 + pdev->isrCount = 0;
4714 +
4715 + /*** Its assumed that the vlynq module has been brought out of reset
4716 + * before invocation of vlynq_init. Since, this operation is board specific
4717 + * it must be handled outside this generic driver */
4718 +
4719 + /* Assert reset the remote device, call reset_cb,
4720 + * reset CB holds Reset according to the device needs. */
4721 + VLYNQ_RESETCB(VLYNQ_RESET_ASSERT);
4722 +
4723 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
4724 + * usually input for all the devices. */
4725 + if (options & VLYNQ_INIT_CONFIG_CLOCK)
4726 + {
4727 + vlynq_configClock(pdev);
4728 + }
4729 +
4730 + /* Call reset_cb again. It will release the remote device
4731 + * from reset, and wait for a while. */
4732 + VLYNQ_RESETCB(VLYNQ_RESET_DEASSERT);
4733 +
4734 + if(options & VLYNQ_INIT_CHECK_LINK )
4735 + {
4736 + /* Check for link up during initialization*/
4737 + while( counter < 25 )
4738 + {
4739 + /* loop around giving a chance for link status to settle down */
4740 + counter++;
4741 + if(vlynq_link_check(pdev))
4742 + {
4743 + /* Link is up exit loop*/
4744 + break;
4745 + }
4746 +
4747 + vlynq_delay(4000);
4748 + }/*end of while counter loop */
4749 +
4750 + if(!vlynq_link_check(pdev))
4751 + {
4752 + /* Handle this case as abort */
4753 + pdev->state = VLYNQ_DRV_STATE_ERROR;
4754 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4755 + return VLYNQ_LINK_DOWN;
4756 + }/* end of if not vlynq_link_check conditional block */
4757 +
4758 + }/*end of if options & VLYNQ_INIT_CHECK_LINK conditional block */
4759 +
4760 +
4761 + if (options & VLYNQ_INIT_LOCAL_MEM_REGIONS)
4762 + {
4763 + /* Initialise local memory regions . This initialization lets
4764 + * the local host access remote device memory regions*/
4765 + int i;
4766 +
4767 + /* configure the VLYNQ portal window to a PHYSICAL
4768 + * address of the local CPU */
4769 + VLYNQ_ALIGN4(pdev->local_mem.Txmap);
4770 + VLYNQ_TXMAP_REG = (pdev->local_mem.Txmap);
4771 +
4772 + /*This code assumes input parameter is itself a physical address */
4773 + for(i=0; i < VLYNQ_MAX_MEMORY_REGIONS ; i++)
4774 + {
4775 + /* Physical address on the remote */
4776 + map = i+1;
4777 + VLYNQ_R_RXMAP_SIZE_REG(map) = 0;
4778 + if( pdev->remote_mem.RxSize[i])
4779 + {
4780 + VLYNQ_ALIGN4(pdev->remote_mem.RxOffset[i]);
4781 + VLYNQ_ALIGN4(pdev->remote_mem.RxSize[i]);
4782 + VLYNQ_R_RXMAP_OFFSET_REG(map) = pdev->remote_mem.RxOffset[i];
4783 + VLYNQ_R_RXMAP_SIZE_REG(map) = pdev->remote_mem.RxSize[i];
4784 + }
4785 + }
4786 + }
4787 +
4788 + if(options & VLYNQ_INIT_REMOTE_MEM_REGIONS )
4789 + {
4790 + int i;
4791 +
4792 + /* Initialise remote memory regions. This initialization lets remote
4793 + * device access local host memory regions. It configures the VLYNQ portal
4794 + * window to a PHYSICAL address of the remote */
4795 + VLYNQ_ALIGN4(pdev->remote_mem.Txmap);
4796 + VLYNQ_R_TXMAP_REG = pdev->remote_mem.Txmap;
4797 +
4798 + for( i=0; i<VLYNQ_MAX_MEMORY_REGIONS; i++)
4799 + {
4800 + /* Physical address on the local */
4801 + map = i+1;
4802 + VLYNQ_RXMAP_SIZE_REG(map) = 0;
4803 + if( pdev->local_mem.RxSize[i])
4804 + {
4805 + VLYNQ_ALIGN4(pdev->local_mem.RxOffset[i]);
4806 + VLYNQ_ALIGN4(pdev->local_mem.RxSize[i]);
4807 + VLYNQ_RXMAP_OFFSET_REG(map) = (pdev->local_mem.RxOffset[i]);
4808 + VLYNQ_RXMAP_SIZE_REG(map) = (pdev->local_mem.RxSize[i]);
4809 + }
4810 + }
4811 + }
4812 +
4813 + /* Adapted from original vlynq driver from cable - Calculate VLYNQ bus width */
4814 + pdev->width = 3 + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_STATUS_REG)
4815 + + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_R_STATUS_REG);
4816 +
4817 + /* chance to initialize the device, e.g. to boost VLYNQ
4818 + * clock by modifying pdev->clk_div or and verify the width. */
4819 + VLYNQ_RESETCB(VLYNQ_RESET_LINKESTABLISH);
4820 +
4821 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
4822 + * usually input for all the devices. */
4823 + if(options & VLYNQ_INIT_CONFIG_CLOCK )
4824 + {
4825 + vlynq_configClock(pdev);
4826 + }
4827 +
4828 + /* last check for link*/
4829 + if(options & VLYNQ_INIT_CHECK_LINK )
4830 + {
4831 + /* Final Check for link during initialization*/
4832 + while( counter < 25 )
4833 + {
4834 + /* loop around giving a chance for link status to settle down */
4835 + counter++;
4836 + if(vlynq_link_check(pdev))
4837 + {
4838 + /* Link is up exit loop*/
4839 + break;
4840 + }
4841 +
4842 + vlynq_delay(4000);
4843 + }/*end of while counter loop */
4844 +
4845 + if(!vlynq_link_check(pdev))
4846 + {
4847 + /* Handle this case as abort */
4848 + pdev->state = VLYNQ_DRV_STATE_ERROR;
4849 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
4850 + return VLYNQ_LINK_DOWN;
4851 + }/* end of if not vlynq_link_check conditional block */
4852 +
4853 + } /* end of if options & VLYNQ_INIT_CHECK_LINK */
4854 +
4855 + if(options & VLYNQ_INIT_LOCAL_INTERRUPTS )
4856 + {
4857 + /* Configure local interrupt settings */
4858 + intSetting = &(pdev->local_irq);
4859 +
4860 + /* Map local module status interrupts to interrupt vector*/
4861 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4862 +
4863 + /* enable local module status interrupts */
4864 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4865 +
4866 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4867 + {
4868 + /*set the intLocal bit*/
4869 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4870 + }
4871 +
4872 + /* Irrespective of whether interrupts are handled locally, program
4873 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4874 + * i.e remote packets are set intPending register->which will result in
4875 + * same packet being sent out) has been done already
4876 + */
4877 +
4878 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4879 + {
4880 + /* Set the int2Cfg register, so that remote interrupt
4881 + * packets are written to intPending register */
4882 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4883 +
4884 + /* Set intPtr register to point to intPending register */
4885 + VLYNQ_INT_PTR_REG = VLYNQ_INT_PENDING_REG_PTR ;
4886 + }
4887 + else
4888 + {
4889 + /*set the interrupt pointer register*/
4890 + VLYNQ_INT_PTR_REG = intSetting->intr_ptr;
4891 + /* Dont bother to modify int2Cfg as it would be zero */
4892 + }
4893 +
4894 + /** Clear bits related to INT settings in control register **/
4895 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4896 +
4897 + /** Or the bits to be set with Control register **/
4898 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG | val;
4899 +
4900 + /* initialise local ICB */
4901 + if(vlynqInterruptInit(pdev)==VLYNQ_MEMALLOC_FAIL)
4902 + return VLYNQ_MEMALLOC_FAIL;
4903 +
4904 + /* Install handler for local module status interrupts. By default when
4905 + * local interrupt setting is initialised, the local module status are
4906 + * enabled and handler hooked up */
4907 + if(vlynq_install_isr(pdev, intSetting->map_vector, vlynq_local_module_isr,
4908 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4909 + return VLYNQ_INVALID_ARG;
4910 + } /* end of init local interrupts */
4911 +
4912 + if(options & VLYNQ_INIT_REMOTE_INTERRUPTS )
4913 + {
4914 + /* Configure remote interrupt settings from configuration */
4915 + intSetting = &(pdev->remote_irq);
4916 +
4917 + /* Map remote module status interrupts to remote interrupt vector*/
4918 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
4919 + /* enable remote module status interrupts */
4920 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
4921 +
4922 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
4923 + {
4924 + /*set the intLocal bit*/
4925 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
4926 + }
4927 +
4928 + /* Irrespective of whether interrupts are handled locally, program
4929 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
4930 + * i.e remote packets are set intPending register->which will result in
4931 + * same packet being sent out) has been done already
4932 + */
4933 +
4934 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
4935 + {
4936 + /* Set the int2Cfg register, so that remote interrupt
4937 + * packets are written to intPending register */
4938 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
4939 + /* Set intPtr register to point to intPending register */
4940 + VLYNQ_R_INT_PTR_REG = VLYNQ_R_INT_PENDING_REG_PTR ;
4941 + }
4942 + else
4943 + {
4944 + /*set the interrupt pointer register*/
4945 + VLYNQ_R_INT_PTR_REG = intSetting->intr_ptr;
4946 + /* Dont bother to modify int2Cfg as it would be zero */
4947 + }
4948 +
4949 + if( (intSetting->intLocal == VLYNQ_INT_REMOTE) &&
4950 + (options & VLYNQ_INIT_LOCAL_INTERRUPTS) &&
4951 + (pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) )
4952 + {
4953 + /* Install handler for remote module status interrupts. By default when
4954 + * remote interrupts are forwarded to local root_isr then remote_module_isr is
4955 + * enabled and handler hooked up */
4956 + if(vlynq_install_isr(pdev,intSetting->map_vector,vlynq_remote_module_isr,
4957 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
4958 + return VLYNQ_INVALID_ARG;
4959 + }
4960 +
4961 +
4962 + /** Clear bits related to INT settings in control register **/
4963 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
4964 +
4965 + /** Or the bits to be set with the remote Control register **/
4966 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG | val;
4967 +
4968 + } /* init remote interrupt settings*/
4969 +
4970 + if(options & VLYNQ_INIT_CLEAR_ERRORS )
4971 + {
4972 + /* Clear errors during initialization */
4973 + tmp = VLYNQ_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4974 + VLYNQ_STATUS_REG = tmp;
4975 + tmp = VLYNQ_R_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
4976 + VLYNQ_R_STATUS_REG = tmp;
4977 + }
4978 +
4979 + /* clear int status */
4980 + val = VLYNQ_INT_STAT_REG;
4981 + VLYNQ_INT_STAT_REG = val;
4982 +
4983 + /* finish initialization */
4984 + pdev->state = VLYNQ_DRV_STATE_RUN;
4985 + VLYNQ_RESETCB( VLYNQ_RESET_INITOK);
4986 + return VLYNQ_SUCCESS;
4987 +
4988 +}
4989 +
4990 +
4991 +/* ----------------------------------------------------------------------------
4992 + * Function : vlynqInterruptInit()
4993 + * Description: This local function is used to set up the ICB table for the
4994 + * VLYNQ_STATUS_REG vlynq module. The input parameter "pdev" points the vlynq
4995 + * device instance whose ICB is allocated.
4996 + * Return : returns VLYNQ_SUCCESS or vlynq error for failure
4997 + * -----------------------------------------------------------------------------
4998 + */
4999 +static int vlynqInterruptInit(VLYNQ_DEV *pdev)
5000 +{
5001 + int i, numslots;
5002 +
5003 + /* Memory allocated statically.
5004 + * Initialise ICB,free list.Indicate primary slot empty.
5005 + * Intialise intVector <==> map_vector translation table*/
5006 + for(i=0; i < VLYNQ_NUM_INT_BITS; i++)
5007 + {
5008 + pdev->pIntrCB[i].isr = NULL;
5009 + pdev->pIntrCB[i].next = NULL; /*nothing chained */
5010 + pdev->vector_map[i] = -1; /* indicates unmapped */
5011 + }
5012 +
5013 + /* In the ICB slots, [VLYNQ_NUM_INT_BITS i.e 32 to ICB array size) are expansion slots
5014 + * required only when interrupt chaining/sharing is supported. In case
5015 + * of chained interrupts the list starts from primary slot and the
5016 + * additional slots are obtained from the common free area */
5017 +
5018 + /* Initialise freelist */
5019 +
5020 + numslots = VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS;
5021 +
5022 + if (numslots > VLYNQ_NUM_INT_BITS)
5023 + {
5024 + pdev->freelist = &(pdev->pIntrCB[VLYNQ_NUM_INT_BITS]);
5025 +
5026 + for(i = VLYNQ_NUM_INT_BITS; i < (numslots-1) ; i++)
5027 + {
5028 + pdev->pIntrCB[i].next = &(pdev->pIntrCB[i+1]);
5029 + pdev->pIntrCB[i].isr = NULL;
5030 + }
5031 + pdev->pIntrCB[i].next=NULL; /* Indicate end of freelist*/
5032 + pdev->pIntrCB[i].isr=NULL;
5033 + }
5034 + else
5035 + {
5036 + pdev->freelist = NULL;
5037 + }
5038 +
5039 + /** Reset mapping for IV 0-7 **/
5040 + VLYNQ_IVR_03TO00_REG = 0;
5041 + VLYNQ_IVR_07TO04_REG = 0;
5042 +
5043 + return VLYNQ_SUCCESS;
5044 +}
5045 +
5046 +/** remember that hooking up of root ISR handler with the interrupt controller
5047 + * is not done as a part of this driver. Typically, it must be done after
5048 + * invoking vlynq_init*/
5049 +
5050 +
5051 + /* ----------------------------------------------------------------------------
5052 + * ISR with the SOC interrupt controller. This ISR typically scans
5053 + * the Int PENDING/SET register in the VLYNQ module and calls the
5054 + * appropriate ISR associated with the correponding vector number.
5055 + * -----------------------------------------------------------------------------
5056 + */
5057 +void vlynq_root_isr(void *arg)
5058 +{
5059 + int source; /* Bit position of pending interrupt, start from 0 */
5060 + unsigned int interrupts, clrInterrupts;
5061 + VLYNQ_DEV * pdev;
5062 + VLYNQ_INTR_CNTRL_ICB *entry;
5063 +
5064 + pdev=(VLYNQ_DEV*)(arg); /*obtain the vlynq device pointer*/
5065 +
5066 + interrupts = VLYNQ_INT_STAT_REG; /* Get the list of pending interrupts */
5067 + VLYNQ_INT_STAT_REG = interrupts; /* clear the int CR register */
5068 + clrInterrupts = interrupts; /* save them for further analysis */
5069 +
5070 + debugPrint("vlynq_root_isr: dev %u. INTCR = 0x%08lx\n", pdev->dev_idx, clrInterrupts,0,0,0,0);
5071 +
5072 + /* Scan interrupt bits */
5073 + source =0;
5074 + while( clrInterrupts != 0)
5075 + {
5076 + /* test if bit is set? */
5077 + if( 0x1ul & clrInterrupts)
5078 + {
5079 + entry = &(pdev->pIntrCB[source]); /* Get the ISR entry */
5080 + pdev->intCount++; /* update interrupt count */
5081 + if(entry->isr != NULL)
5082 + {
5083 + do
5084 + {
5085 + pdev->isrCount++; /* update isr invocation count */
5086 + /* Call the user ISR and update the count for ISR */
5087 + entry->isrCount++;
5088 + entry->isr(entry->arg1, entry->arg2, entry->arg3);
5089 + if (entry->next == NULL) break;
5090 + entry = entry->next;
5091 +
5092 + } while (entry->isr != NULL);
5093 + }
5094 + else
5095 + {
5096 + debugPrint(" ISR not installed for vlynq vector:%d\n",source,0,0,0,0,0);
5097 + }
5098 + }
5099 + clrInterrupts >>= 1; /* Next source bit */
5100 + ++source;
5101 + } /* endWhile clrInterrupts != 0 */
5102 +}
5103 +
5104 +
5105 + /* ----------------------------------------------------------------------------
5106 + * Function : vlynq_local__module_isr()
5107 + * Description: This ISR is attached to the local VLYNQ interrupt vector
5108 + * by the Vlynq Driver when local interrupts are being handled. i.e.
5109 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5110 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5111 + * is invoked.
5112 + * VLYNQ_DEV is passed as arg1. arg2 and arg3 are unused.
5113 + * -----------------------------------------------------------------------------
5114 + */
5115 +static void vlynq_local_module_isr(void *arg1,void *arg2, void *arg3)
5116 +{
5117 + VLYNQ_REPORT_CB func;
5118 + unsigned int dwStatRegVal;
5119 + VLYNQ_DEV * pdev;
5120 +
5121 + pdev = (VLYNQ_DEV*) arg1;
5122 + /* Callback function is read from the device pointer that is passed as an argument */
5123 + func = pdev->report_cb;
5124 +
5125 + /* read local status register */
5126 + dwStatRegVal = VLYNQ_STATUS_REG;
5127 +
5128 + /* clear pending events */
5129 + VLYNQ_STATUS_REG = dwStatRegVal;
5130 +
5131 + /* invoke user callback */
5132 + if( func != NULL)
5133 + func( pdev, VLYNQ_LOCAL_DVC, dwStatRegVal);
5134 +
5135 +}
5136 +
5137 + /* ----------------------------------------------------------------------------
5138 + * Function : vlynq_remote_module_isr()
5139 + * Description: This ISR is attached to the remote VLYNQ interrupt vector
5140 + * by the Vlynq Driver when remote interrupts are being handled locally. i.e.
5141 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5142 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5143 + * is invoked.
5144 + * The parameters irq,regs ar unused.
5145 + * -----------------------------------------------------------------------------
5146 + */
5147 +static void vlynq_remote_module_isr(void *arg1,void *arg2, void *arg3)
5148 +{
5149 + VLYNQ_REPORT_CB func;
5150 + unsigned int dwStatRegVal;
5151 + VLYNQ_DEV * pdev;
5152 +
5153 +
5154 + pdev = (VLYNQ_DEV*) arg1;
5155 +
5156 + /* Callback function is read from the device pointer that is passed as an argument */
5157 + func = pdev->report_cb;
5158 +
5159 + /* read local status register */
5160 + dwStatRegVal = VLYNQ_R_STATUS_REG;
5161 +
5162 + /* clear pending events */
5163 + VLYNQ_R_STATUS_REG = dwStatRegVal;
5164 +
5165 + /* invoke user callback */
5166 + if( func != NULL)
5167 + func( pdev, VLYNQ_REMOTE_DVC, dwStatRegVal);
5168 +
5169 +}
5170 +
5171 +/* ----------------------------------------------------------------------------
5172 + * Function : vlynq_interrupt_get_count()
5173 + * Description: This function returns the number of times a particular intr
5174 + * has been invoked.
5175 + *
5176 + * It returns 0, if erroneous map_vector is specified or if the corres isr
5177 + * has not been registered with VLYNQ.
5178 + */
5179 +unsigned int vlynq_interrupt_get_count(VLYNQ_DEV *pdev,
5180 + unsigned int map_vector)
5181 +{
5182 + VLYNQ_INTR_CNTRL_ICB *entry;
5183 + unsigned int count = 0;
5184 +
5185 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5186 + return count;
5187 +
5188 + entry = &(pdev->pIntrCB[map_vector]);
5189 +
5190 + if (entry)
5191 + count = entry->isrCount;
5192 +
5193 + return (count);
5194 +}
5195 +
5196 +
5197 +/* ----------------------------------------------------------------------------
5198 + * Function : vlynq_install_isr()
5199 + * Description: This function installs ISR for Vlynq interrupt vector
5200 + * bits(in IntPending register). This function should be used only when
5201 + * Vlynq interrupts are being handled locally(remote may be programmed to send
5202 + * interrupt packets).Also, the int2cfg should be 1 and the least significant
5203 + * 8 bits of the Interrupt Pointer Register must point to Interrupt
5204 + * Pending/Set Register).
5205 + * If host int2cfg=0 and the Interrupt Pointer register contains
5206 + * the address of the interrupt set register in the interrupt controller
5207 + * module of the local device , then the ISR for the remote interrupt must be
5208 + * directly registered with the Interrupt controller and must not use this API
5209 + * Note: this function simply installs the ISR in ICB It doesnt modify
5210 + * any register settings
5211 + */
5212 +int
5213 +vlynq_install_isr(VLYNQ_DEV *pdev,
5214 + unsigned int map_vector,
5215 + VLYNQ_INTR_CNTRL_ISR isr,
5216 + void *arg1, void *arg2, void *arg3)
5217 +{
5218 + VLYNQ_INTR_CNTRL_ICB *entry;
5219 +
5220 + if ( (map_vector > (VLYNQ_NUM_INT_BITS-1)) || (isr == NULL) )
5221 + return VLYNQ_INVALID_ARG;
5222 +
5223 + entry = &(pdev->pIntrCB[map_vector]);
5224 +
5225 + if(entry->isr == NULL)
5226 + {
5227 + entry->isr = isr;
5228 + entry->arg1 = arg1;
5229 + entry->arg2 = arg2;
5230 + entry->arg3 = arg3;
5231 + entry->next = NULL;
5232 + }
5233 + else
5234 + {
5235 + /** No more empty slots,return error */
5236 + if(pdev->freelist == NULL)
5237 + return VLYNQ_MEMALLOC_FAIL;
5238 +
5239 + while(entry->next != NULL)
5240 + {
5241 + entry = entry->next;
5242 + }
5243 +
5244 + /* Append new node to the chain */
5245 + entry->next = pdev->freelist;
5246 + /* Remove the appended node from freelist */
5247 + pdev->freelist = pdev->freelist->next;
5248 + entry= entry->next;
5249 +
5250 + /*** Set the ICB fields ***/
5251 + entry->isr = isr;
5252 + entry->arg1 = arg1;
5253 + entry->arg2 = arg2;
5254 + entry->arg3 = arg3;
5255 + entry->next = NULL;
5256 + }
5257 +
5258 + return VLYNQ_SUCCESS;
5259 +}
5260 +
5261 +
5262 +
5263 +/* ----------------------------------------------------------------------------
5264 + * Function : vlynq_uninstall_isr
5265 + * Description: This function is used to uninstall a previously
5266 + * registered ISR. In case of shared/chained interrupts, the
5267 + * void * arg parameter must uniquely identify the ISR to be
5268 + * uninstalled.
5269 + * Note: this function simply uninstalls the ISR in ICB
5270 + * It doesnt modify any register settings
5271 + */
5272 +int
5273 +vlynq_uninstall_isr(VLYNQ_DEV *pdev,
5274 + unsigned int map_vector,
5275 + void *arg1, void *arg2, void *arg3)
5276 +{
5277 + VLYNQ_INTR_CNTRL_ICB *entry,*temp;
5278 +
5279 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5280 + return VLYNQ_INVALID_ARG;
5281 +
5282 + entry = &(pdev->pIntrCB[map_vector]);
5283 +
5284 + if(entry->isr == NULL )
5285 + return VLYNQ_ISR_NON_EXISTENT;
5286 +
5287 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5288 + {
5289 + if(entry->next == NULL)
5290 + {
5291 + entry->isr=NULL;
5292 + return VLYNQ_SUCCESS;
5293 + }
5294 + else
5295 + {
5296 + temp = entry->next;
5297 + /* Copy next node in the chain to prim.slot */
5298 + entry->isr = temp->isr;
5299 + entry->arg1 = temp->arg1;
5300 + entry->arg2 = temp->arg2;
5301 + entry->arg3 = temp->arg3;
5302 + entry->next = temp->next;
5303 + /* Free the just copied node */
5304 + temp->isr = NULL;
5305 + temp->arg1 = NULL;
5306 + temp->arg2 = NULL;
5307 + temp->arg3 = NULL;
5308 + temp->next = pdev->freelist;
5309 + pdev->freelist = temp;
5310 + return VLYNQ_SUCCESS;
5311 + }
5312 + }
5313 + else
5314 + {
5315 + temp = entry;
5316 + while ( (entry = temp->next) != NULL)
5317 + {
5318 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5319 + {
5320 + /* remove node from chain */
5321 + temp->next = entry->next;
5322 + /* Add the removed node to freelist */
5323 + entry->isr = NULL;
5324 + entry->arg1 = NULL;
5325 + entry->arg2 = NULL;
5326 + entry->arg3 = NULL;
5327 + entry->next = pdev->freelist;
5328 + entry->isrCount = 0;
5329 + pdev->freelist = entry;
5330 + return VLYNQ_SUCCESS;
5331 + }
5332 + temp = entry;
5333 + }
5334 +
5335 + return VLYNQ_ISR_NON_EXISTENT;
5336 + }
5337 +}
5338 +
5339 +
5340 +
5341 +
5342 +/* ----------------------------------------------------------------------------
5343 + * function : vlynq_interrupt_vector_set()
5344 + * description:configures interrupt vector mapping,interrupt type
5345 + * polarity -all in one go.
5346 + */
5347 +int
5348 +vlynq_interrupt_vector_set(VLYNQ_DEV *pdev, /* vlynq device */
5349 + unsigned int int_vector, /* int vector on vlynq device */
5350 + unsigned int map_vector, /* bit for this interrupt */
5351 + VLYNQ_DEV_TYPE dev_type, /* local or remote device */
5352 + VLYNQ_INTR_POLARITY pol, /* polarity of interrupt */
5353 + VLYNQ_INTR_TYPE type) /* pulsed/level interrupt */
5354 +{
5355 + volatile unsigned int * vecreg;
5356 + unsigned int val=0;
5357 + unsigned int bytemask=0XFF;
5358 +
5359 + /* use the lower 8 bits of val to set the value , shift it to
5360 + * appropriate byte position in the ivr and write it to the
5361 + * corresponding register */
5362 +
5363 + /* validate the number of interrupts supported */
5364 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5365 + return VLYNQ_INVALID_ARG;
5366 +
5367 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5368 + return VLYNQ_INVALID_ARG;
5369 +
5370 + if (dev_type == VLYNQ_LOCAL_DVC)
5371 + {
5372 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5373 + }
5374 + else
5375 + {
5376 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5377 + }
5378 +
5379 + /* Update the intVector<==> bit position translation table */
5380 + pdev->vector_map[map_vector] = int_vector;
5381 +
5382 + /* val has been initialised to zero. we only have to turn on appropriate bits*/
5383 + if(type == VLYNQ_INTR_PULSED)
5384 + val |= VLYNQ_IVR_INTTYPE_MASK;
5385 +
5386 + if(pol == VLYNQ_INTR_ACTIVE_LOW)
5387 + val |= VLYNQ_IVR_INTPOL_MASK;
5388 +
5389 + val |= map_vector;
5390 +
5391 + /** clear the correct byte position and then or val **/
5392 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5393 +
5394 + /** write to correct byte position in vecreg*/
5395 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5396 +
5397 + /* Setting a interrupt vector, leaves the interrupt disabled
5398 + * which must be enabled subsequently */
5399 +
5400 + return VLYNQ_SUCCESS;
5401 +}
5402 +
5403 +
5404 +/* ----------------------------------------------------------------------------
5405 + * Function : vlynq_interrupt_vector_cntl()
5406 + * Description:enables/disable interrupt
5407 + */
5408 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
5409 + unsigned int int_vector,
5410 + VLYNQ_DEV_TYPE dev_type,
5411 + unsigned int enable)
5412 +{
5413 + volatile unsigned int *vecReg;
5414 + unsigned int val=0;
5415 + unsigned int intenMask=0x80;
5416 +
5417 + /* validate the number of interrupts supported */
5418 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5419 + return VLYNQ_INVALID_ARG;
5420 +
5421 + if (dev_type == VLYNQ_LOCAL_DVC)
5422 + {
5423 + vecReg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5424 + }
5425 + else
5426 + {
5427 + vecReg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5428 + }
5429 +
5430 + /** Clear the correct byte position and then or val **/
5431 + *vecReg = (*vecReg) & ( ~(intenMask << ( (int_vector %4)*8) ) );
5432 +
5433 + if(enable)
5434 + {
5435 + val |= VLYNQ_IVR_INTEN_MASK;
5436 + /** Write to correct byte position in vecReg*/
5437 + *vecReg = (*vecReg) | (val << ( (int_vector % 4)*8) ) ;
5438 + }
5439 +
5440 + return VLYNQ_SUCCESS;
5441 +
5442 +}/* end of function vlynq_interrupt_vector_cntl */
5443 +
5444 +
5445 +
5446 +/* ----------------------------------------------------------------------------
5447 + * Function : vlynq_interrupt_vector_map()
5448 + * Description:Configures interrupt vector mapping alone
5449 + */
5450 +int
5451 +vlynq_interrupt_vector_map( VLYNQ_DEV *pdev,
5452 + VLYNQ_DEV_TYPE dev_type,
5453 + unsigned int int_vector,
5454 + unsigned int map_vector)
5455 +{
5456 + volatile unsigned int * vecreg;
5457 + unsigned int val=0;
5458 + unsigned int bytemask=0x1f; /* mask to turn off bits corresponding to int vector */
5459 +
5460 + /* use the lower 8 bits of val to set the value , shift it to
5461 + * appropriate byte position in the ivr and write it to the
5462 + * corresponding register */
5463 +
5464 + /* validate the number of interrupts supported */
5465 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5466 + return VLYNQ_INVALID_ARG;
5467 +
5468 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5469 + return VLYNQ_INVALID_ARG;
5470 +
5471 + if (dev_type == VLYNQ_LOCAL_DVC)
5472 + {
5473 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5474 + }
5475 + else
5476 + {
5477 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5478 + }
5479 +
5480 + /* Update the intVector<==> bit position translation table */
5481 + pdev->vector_map[map_vector] = int_vector;
5482 +
5483 + /** val has been initialised to zero. we only have to turn on
5484 + * appropriate bits*/
5485 + val |= map_vector;
5486 +
5487 + /** clear the correct byte position and then or val **/
5488 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5489 +
5490 + /** write to correct byte position in vecreg*/
5491 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5492 +
5493 + return VLYNQ_SUCCESS;
5494 +}
5495 +
5496 +
5497 +/* ----------------------------------------------------------------------------
5498 + * function : vlynq_interrupt_set_polarity()
5499 + * description:configures interrupt polarity .
5500 + */
5501 +int
5502 +vlynq_interrupt_set_polarity( VLYNQ_DEV *pdev ,
5503 + VLYNQ_DEV_TYPE dev_type,
5504 + unsigned int map_vector,
5505 + VLYNQ_INTR_POLARITY pol)
5506 +{
5507 + volatile unsigned int * vecreg;
5508 + int int_vector;
5509 + unsigned int val=0;
5510 + unsigned int bytemask=0x20; /** mask to turn off bits corresponding to int polarity */
5511 +
5512 + /* get the int_vector from map_vector */
5513 + int_vector = pdev->vector_map[map_vector];
5514 +
5515 + if(int_vector == -1)
5516 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5517 +
5518 + /* use the lower 8 bits of val to set the value , shift it to
5519 + * appropriate byte position in the ivr and write it to the
5520 + * corresponding register */
5521 +
5522 + if (dev_type == VLYNQ_LOCAL_DVC)
5523 + {
5524 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5525 + }
5526 + else
5527 + {
5528 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5529 + }
5530 +
5531 + /* val has been initialised to zero. we only have to turn on
5532 + * appropriate bits, if need be*/
5533 +
5534 + /** clear the correct byte position and then or val **/
5535 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5536 +
5537 + if( pol == VLYNQ_INTR_ACTIVE_LOW)
5538 + {
5539 + val |= VLYNQ_IVR_INTPOL_MASK;
5540 + /** write to correct byte position in vecreg*/
5541 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5542 + }
5543 +
5544 + return VLYNQ_SUCCESS;
5545 +}
5546 +
5547 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
5548 + VLYNQ_DEV_TYPE dev_type,
5549 + unsigned int map_vector)
5550 +{
5551 + volatile unsigned int * vecreg;
5552 + int int_vector;
5553 + unsigned int val=0;
5554 +
5555 + /* get the int_vector from map_vector */
5556 + int_vector = pdev->vector_map[map_vector];
5557 +
5558 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5559 + return(-1);
5560 +
5561 + if(int_vector == -1)
5562 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5563 +
5564 + /* use the lower 8 bits of val to set the value , shift it to
5565 + * appropriate byte position in the ivr and write it to the
5566 + * corresponding register */
5567 +
5568 + if (dev_type == VLYNQ_LOCAL_DVC)
5569 + {
5570 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5571 + }
5572 + else
5573 + {
5574 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5575 + }
5576 +
5577 + /** read the information into val **/
5578 + val = (*vecreg) & ((VLYNQ_IVR_INTPOL_MASK << ( (int_vector %4)*8) ) );
5579 +
5580 + return (val ? (VLYNQ_INTR_ACTIVE_LOW) : (VLYNQ_INTR_ACTIVE_HIGH));
5581 +}
5582 +
5583 +
5584 +/* ----------------------------------------------------------------------------
5585 + * function : vlynq_interrupt_set_type()
5586 + * description:configures interrupt type .
5587 + */
5588 +int vlynq_interrupt_set_type( VLYNQ_DEV *pdev,
5589 + VLYNQ_DEV_TYPE dev_type,
5590 + unsigned int map_vector,
5591 + VLYNQ_INTR_TYPE type)
5592 +{
5593 + volatile unsigned int * vecreg;
5594 + unsigned int val=0;
5595 + int int_vector;
5596 +
5597 + /** mask to turn off bits corresponding to interrupt type */
5598 + unsigned int bytemask=0x40;
5599 +
5600 + /* get the int_vector from map_vector */
5601 + int_vector = pdev->vector_map[map_vector];
5602 + if(int_vector == -1)
5603 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5604 +
5605 + /* use the lower 8 bits of val to set the value , shift it to
5606 + * appropriate byte position in the ivr and write it to the
5607 + * corresponding register */
5608 + if (dev_type == VLYNQ_LOCAL_DVC)
5609 + {
5610 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5611 + }
5612 + else
5613 + {
5614 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5615 + }
5616 +
5617 + /** val has been initialised to zero. we only have to turn on
5618 + * appropriate bits if need be*/
5619 +
5620 + /** clear the correct byte position and then or val **/
5621 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5622 +
5623 + if( type == VLYNQ_INTR_PULSED)
5624 + {
5625 + val |= VLYNQ_IVR_INTTYPE_MASK;
5626 + /** write to correct byte position in vecreg*/
5627 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5628 + }
5629 +
5630 + return VLYNQ_SUCCESS;
5631 +}
5632 +
5633 +/* ----------------------------------------------------------------------------
5634 + * function : vlynq_interrupt_get_type()
5635 + * description:returns interrupt type .
5636 + */
5637 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev, VLYNQ_DEV_TYPE dev_type,
5638 + unsigned int map_vector)
5639 +{
5640 + volatile unsigned int * vecreg;
5641 + unsigned int val=0;
5642 + int int_vector;
5643 +
5644 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5645 + return(-1);
5646 +
5647 + /* get the int_vector from map_vector */
5648 + int_vector = pdev->vector_map[map_vector];
5649 + if(int_vector == -1)
5650 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5651 +
5652 + /* use the lower 8 bits of val to set the value , shift it to
5653 + * appropriate byte position in the ivr and write it to the
5654 + * corresponding register */
5655 + if (dev_type == VLYNQ_LOCAL_DVC)
5656 + {
5657 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5658 + }
5659 + else
5660 + {
5661 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5662 + }
5663 +
5664 + /** Read the correct bit position into val **/
5665 + val = (*vecreg) & ((VLYNQ_IVR_INTTYPE_MASK << ( (int_vector %4)*8) ) );
5666 +
5667 + return (val ? (VLYNQ_INTR_PULSED) : (VLYNQ_INTR_LEVEL));
5668 +}
5669 +
5670 +/* ----------------------------------------------------------------------------
5671 + * function : vlynq_interrupt_enable()
5672 + * description:Enable interrupt by writing to IVR register.
5673 + */
5674 +int vlynq_interrupt_enable( VLYNQ_DEV *pdev,
5675 + VLYNQ_DEV_TYPE dev_type,
5676 + unsigned int map_vector)
5677 +{
5678 + volatile unsigned int * vecreg;
5679 + unsigned int val=0;
5680 + int int_vector;
5681 +
5682 + /** mask to turn off bits corresponding to interrupt enable */
5683 + unsigned int bytemask=0x80;
5684 +
5685 + /* get the int_vector from map_vector */
5686 + int_vector = pdev->vector_map[map_vector];
5687 + if(int_vector == -1)
5688 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5689 +
5690 + /* use the lower 8 bits of val to set the value , shift it to
5691 + * appropriate byte position in the ivr and write it to the
5692 + * corresponding register */
5693 +
5694 + if (dev_type == VLYNQ_LOCAL_DVC)
5695 + {
5696 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5697 + }
5698 + else
5699 + {
5700 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5701 + }
5702 +
5703 + /** val has been initialised to zero. we only have to turn on
5704 + * bit corresponding to interrupt enable*/
5705 + val |= VLYNQ_IVR_INTEN_MASK;
5706 +
5707 + /** clear the correct byte position and then or val **/
5708 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5709 +
5710 + /** write to correct byte position in vecreg*/
5711 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
5712 +
5713 + return VLYNQ_SUCCESS;
5714 +}
5715 +
5716 +
5717 +/* ----------------------------------------------------------------------------
5718 + * function : vlynq_interrupt_disable()
5719 + * description:Disable interrupt by writing to IVR register.
5720 + */
5721 +int
5722 +vlynq_interrupt_disable( VLYNQ_DEV *pdev,
5723 + VLYNQ_DEV_TYPE dev_type,
5724 + unsigned int map_vector)
5725 +{
5726 + volatile unsigned int * vecreg;
5727 + int int_vector;
5728 +
5729 + /** mask to turn off bits corresponding to interrupt enable */
5730 + unsigned int bytemask=0x80;
5731 +
5732 + /* get the int_vector from map_vector */
5733 + int_vector = pdev->vector_map[map_vector];
5734 + if(int_vector == -1)
5735 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
5736 +
5737 + /* use the lower 8 bits of val to set the value , shift it to
5738 + * appropriate byte position in the ivr and write it to the
5739 + * corresponding register */
5740 + if (dev_type == VLYNQ_LOCAL_DVC)
5741 + {
5742 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5743 + }
5744 + else
5745 + {
5746 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5747 + }
5748 +
5749 + /* We disable the interrupt by simply turning off the bit
5750 + * corresponding to Interrupt enable.
5751 + * Clear the interrupt enable bit in the correct byte position **/
5752 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
5753 +
5754 + /* Dont have to set any bit positions */
5755 +
5756 + return VLYNQ_SUCCESS;
5757 +
5758 +}
5759 +
5760 +
5761 +
5762 +
5763 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
5764 --- linux.old/drivers/char/serial.c 2005-10-21 16:43:20.709226000 +0200
5765 +++ linux.dev/drivers/char/serial.c 2005-11-10 01:10:46.015585250 +0100
5766 @@ -419,7 +419,40 @@
5767 return 0;
5768 }
5769
5770 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5771 +#if defined(CONFIG_AR7)
5772 +
5773 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
5774 +{
5775 + return (inb(info->port + (offset * 4)) & 0xff);
5776 +}
5777 +
5778 +
5779 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
5780 +{
5781 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5782 + return (inb(info->port + (offset * 4)) & 0xff);
5783 +#else
5784 + return (inb_p(info->port + (offset * 4)) & 0xff);
5785 +#endif
5786 +}
5787 +
5788 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
5789 +{
5790 + outb(value, info->port + (offset * 4));
5791 +}
5792 +
5793 +
5794 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
5795 + int value)
5796 +{
5797 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
5798 + outb(value, info->port + (offset * 4));
5799 +#else
5800 + outb_p(value, info->port + (offset * 4));
5801 +#endif
5802 +}
5803 +
5804 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
5805
5806 #include <asm/mips-boards/atlas.h>
5807
5808 @@ -478,8 +511,10 @@
5809 * needed for certain old 386 machines, I've left these #define's
5810 * in....
5811 */
5812 +#ifndef CONFIG_AR7
5813 #define serial_inp(info, offset) serial_in(info, offset)
5814 #define serial_outp(info, offset, value) serial_out(info, offset, value)
5815 +#endif
5816
5817
5818 /*
5819 @@ -1728,7 +1763,15 @@
5820 /* Special case since 134 is really 134.5 */
5821 quot = (2*baud_base / 269);
5822 else if (baud)
5823 +#ifdef CONFIG_AR7
5824 + quot = (CONFIG_AR7_SYS*500000) / baud;
5825 +
5826 + if ((quot%16)>7)
5827 + quot += 8;
5828 + quot /=16;
5829 +#else
5830 quot = baud_base / baud;
5831 +#endif
5832 }
5833 /* If the quotient is zero refuse the change */
5834 if (!quot && old_termios) {
5835 @@ -5540,8 +5583,10 @@
5836 state->irq = irq_cannonicalize(state->irq);
5837 if (state->hub6)
5838 state->io_type = SERIAL_IO_HUB6;
5839 +#ifndef CONFIG_AR7
5840 if (state->port && check_region(state->port,8))
5841 continue;
5842 +#endif
5843 #ifdef CONFIG_MCA
5844 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
5845 continue;
5846 @@ -5997,7 +6042,15 @@
5847 info->io_type = state->io_type;
5848 info->iomem_base = state->iomem_base;
5849 info->iomem_reg_shift = state->iomem_reg_shift;
5850 +#ifdef CONFIG_AR7
5851 + quot = (CONFIG_AR7_SYS*500000) / baud;
5852 +
5853 + if ((quot%16)>7)
5854 + quot += 8;
5855 + quot /=16;
5856 +#else
5857 quot = state->baud_base / baud;
5858 +#endif
5859 cval = cflag & (CSIZE | CSTOPB);
5860 #if defined(__powerpc__) || defined(__alpha__)
5861 cval >>= 8;
5862 diff -urN linux.old/drivers/char/serial.c.orig linux.dev/drivers/char/serial.c.orig
5863 --- linux.old/drivers/char/serial.c.orig 1970-01-01 01:00:00.000000000 +0100
5864 +++ linux.dev/drivers/char/serial.c.orig 2005-11-10 01:10:46.051587500 +0100
5865 @@ -0,0 +1,6054 @@
5866 +/*
5867 + * linux/drivers/char/serial.c
5868 + *
5869 + * Copyright (C) 1991, 1992 Linus Torvalds
5870 + * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997,
5871 + * 1998, 1999 Theodore Ts'o
5872 + *
5873 + * Extensively rewritten by Theodore Ts'o, 8/16/92 -- 9/14/92. Now
5874 + * much more extensible to support other serial cards based on the
5875 + * 16450/16550A UART's. Added support for the AST FourPort and the
5876 + * Accent Async board.
5877 + *
5878 + * set_serial_info fixed to set the flags, custom divisor, and uart
5879 + * type fields. Fix suggested by Michael K. Johnson 12/12/92.
5880 + *
5881 + * 11/95: TIOCMIWAIT, TIOCGICOUNT by Angelo Haritsis <ah@doc.ic.ac.uk>
5882 + *
5883 + * 03/96: Modularised by Angelo Haritsis <ah@doc.ic.ac.uk>
5884 + *
5885 + * rs_set_termios fixed to look also for changes of the input
5886 + * flags INPCK, BRKINT, PARMRK, IGNPAR and IGNBRK.
5887 + * Bernd Anhäupl 05/17/96.
5888 + *
5889 + * 1/97: Extended dumb serial ports are a config option now.
5890 + * Saves 4k. Michael A. Griffith <grif@acm.org>
5891 + *
5892 + * 8/97: Fix bug in rs_set_termios with RTS
5893 + * Stanislav V. Voronyi <stas@uanet.kharkov.ua>
5894 + *
5895 + * 3/98: Change the IRQ detection, use of probe_irq_o*(),
5896 + * suppress TIOCSERGWILD and TIOCSERSWILD
5897 + * Etienne Lorrain <etienne.lorrain@ibm.net>
5898 + *
5899 + * 4/98: Added changes to support the ARM architecture proposed by
5900 + * Russell King
5901 + *
5902 + * 5/99: Updated to include support for the XR16C850 and ST16C654
5903 + * uarts. Stuart MacDonald <stuartm@connecttech.com>
5904 + *
5905 + * 8/99: Generalized PCI support added. Theodore Ts'o
5906 + *
5907 + * 3/00: Rid circular buffer of redundant xmit_cnt. Fix a
5908 + * few races on freeing buffers too.
5909 + * Alan Modra <alan@linuxcare.com>
5910 + *
5911 + * 5/00: Support for the RSA-DV II/S card added.
5912 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
5913 + *
5914 + * 6/00: Remove old-style timer, use timer_list
5915 + * Andrew Morton <andrewm@uow.edu.au>
5916 + *
5917 + * 7/00: Support Timedia/Sunix/Exsys PCI cards
5918 + *
5919 + * 7/00: fix some returns on failure not using MOD_DEC_USE_COUNT.
5920 + * Arnaldo Carvalho de Melo <acme@conectiva.com.br>
5921 + *
5922 + * 10/00: add in optional software flow control for serial console.
5923 + * Kanoj Sarcar <kanoj@sgi.com> (Modified by Theodore Ts'o)
5924 + *
5925 + * 02/02: Fix for AMD Elan bug in transmit irq routine, by
5926 + * Christer Weinigel <wingel@hog.ctrl-c.liu.se>,
5927 + * Robert Schwebel <robert@schwebel.de>,
5928 + * Juergen Beisert <jbeisert@eurodsn.de>,
5929 + * Theodore Ts'o <tytso@mit.edu>
5930 + *
5931 + * 10/00: Added suport for MIPS Atlas board.
5932 + * 11/00: Hooks for serial kernel debug port support added.
5933 + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard,
5934 + * carstenl@mips.com
5935 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5936 + */
5937 +
5938 +static char *serial_version = "5.05c";
5939 +static char *serial_revdate = "2001-07-08";
5940 +
5941 +/*
5942 + * Serial driver configuration section. Here are the various options:
5943 + *
5944 + * CONFIG_HUB6
5945 + * Enables support for the venerable Bell Technologies
5946 + * HUB6 card.
5947 + *
5948 + * CONFIG_SERIAL_MANY_PORTS
5949 + * Enables support for ports beyond the standard, stupid
5950 + * COM 1/2/3/4.
5951 + *
5952 + * CONFIG_SERIAL_MULTIPORT
5953 + * Enables support for special multiport board support.
5954 + *
5955 + * CONFIG_SERIAL_SHARE_IRQ
5956 + * Enables support for multiple serial ports on one IRQ
5957 + *
5958 + * CONFIG_SERIAL_DETECT_IRQ
5959 + * Enable the autodetection of IRQ on standart ports
5960 + *
5961 + * SERIAL_PARANOIA_CHECK
5962 + * Check the magic number for the async_structure where
5963 + * ever possible.
5964 + *
5965 + * CONFIG_SERIAL_ACPI
5966 + * Enable support for serial console port and serial
5967 + * debug port as defined by the SPCR and DBGP tables in
5968 + * ACPI 2.0.
5969 + */
5970 +
5971 +#include <linux/config.h>
5972 +#include <linux/version.h>
5973 +
5974 +#undef SERIAL_PARANOIA_CHECK
5975 +#define CONFIG_SERIAL_NOPAUSE_IO
5976 +#define SERIAL_DO_RESTART
5977 +
5978 +#if 0
5979 +/* These defines are normally controlled by the autoconf.h */
5980 +#define CONFIG_SERIAL_MANY_PORTS
5981 +#define CONFIG_SERIAL_SHARE_IRQ
5982 +#define CONFIG_SERIAL_DETECT_IRQ
5983 +#define CONFIG_SERIAL_MULTIPORT
5984 +#define CONFIG_HUB6
5985 +#endif
5986 +
5987 +#ifdef CONFIG_PCI
5988 +#define ENABLE_SERIAL_PCI
5989 +#ifndef CONFIG_SERIAL_SHARE_IRQ
5990 +#define CONFIG_SERIAL_SHARE_IRQ
5991 +#endif
5992 +#ifndef CONFIG_SERIAL_MANY_PORTS
5993 +#define CONFIG_SERIAL_MANY_PORTS
5994 +#endif
5995 +#endif
5996 +
5997 +#ifdef CONFIG_SERIAL_ACPI
5998 +#define ENABLE_SERIAL_ACPI
5999 +#endif
6000 +
6001 +#if defined(CONFIG_ISAPNP)|| (defined(CONFIG_ISAPNP_MODULE) && defined(MODULE))
6002 +#ifndef ENABLE_SERIAL_PNP
6003 +#define ENABLE_SERIAL_PNP
6004 +#endif
6005 +#endif
6006 +
6007 +/* Set of debugging defines */
6008 +
6009 +#undef SERIAL_DEBUG_INTR
6010 +#undef SERIAL_DEBUG_OPEN
6011 +#undef SERIAL_DEBUG_FLOW
6012 +#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
6013 +#undef SERIAL_DEBUG_PCI
6014 +#undef SERIAL_DEBUG_AUTOCONF
6015 +
6016 +/* Sanity checks */
6017 +
6018 +#ifdef CONFIG_SERIAL_MULTIPORT
6019 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6020 +#define CONFIG_SERIAL_SHARE_IRQ
6021 +#endif
6022 +#endif
6023 +
6024 +#ifdef CONFIG_HUB6
6025 +#ifndef CONFIG_SERIAL_MANY_PORTS
6026 +#define CONFIG_SERIAL_MANY_PORTS
6027 +#endif
6028 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6029 +#define CONFIG_SERIAL_SHARE_IRQ
6030 +#endif
6031 +#endif
6032 +
6033 +#ifdef MODULE
6034 +#undef CONFIG_SERIAL_CONSOLE
6035 +#endif
6036 +
6037 +#define CONFIG_SERIAL_RSA
6038 +
6039 +#define RS_STROBE_TIME (10*HZ)
6040 +#define RS_ISR_PASS_LIMIT 256
6041 +
6042 +#if defined(__i386__) && (defined(CONFIG_M386) || defined(CONFIG_M486))
6043 +#define SERIAL_INLINE
6044 +#endif
6045 +
6046 +/*
6047 + * End of serial driver configuration section.
6048 + */
6049 +
6050 +#include <linux/module.h>
6051 +
6052 +#include <linux/types.h>
6053 +#ifdef LOCAL_HEADERS
6054 +#include "serial_local.h"
6055 +#else
6056 +#include <linux/serial.h>
6057 +#include <linux/serialP.h>
6058 +#include <linux/serial_reg.h>
6059 +#include <asm/serial.h>
6060 +#define LOCAL_VERSTRING ""
6061 +#endif
6062 +
6063 +#include <linux/errno.h>
6064 +#include <linux/signal.h>
6065 +#include <linux/sched.h>
6066 +#include <linux/timer.h>
6067 +#include <linux/interrupt.h>
6068 +#include <linux/tty.h>
6069 +#include <linux/tty_flip.h>
6070 +#include <linux/major.h>
6071 +#include <linux/string.h>
6072 +#include <linux/fcntl.h>
6073 +#include <linux/ptrace.h>
6074 +#include <linux/ioport.h>
6075 +#include <linux/mm.h>
6076 +#include <linux/slab.h>
6077 +#if (LINUX_VERSION_CODE >= 131343)
6078 +#include <linux/init.h>
6079 +#endif
6080 +#if (LINUX_VERSION_CODE >= 131336)
6081 +#include <asm/uaccess.h>
6082 +#endif
6083 +#include <linux/delay.h>
6084 +#ifdef CONFIG_SERIAL_CONSOLE
6085 +#include <linux/console.h>
6086 +#endif
6087 +#ifdef ENABLE_SERIAL_PCI
6088 +#include <linux/pci.h>
6089 +#endif
6090 +#ifdef ENABLE_SERIAL_PNP
6091 +#include <linux/isapnp.h>
6092 +#endif
6093 +#ifdef CONFIG_MAGIC_SYSRQ
6094 +#include <linux/sysrq.h>
6095 +#endif
6096 +
6097 +/*
6098 + * All of the compatibilty code so we can compile serial.c against
6099 + * older kernels is hidden in serial_compat.h
6100 + */
6101 +#if defined(LOCAL_HEADERS) || (LINUX_VERSION_CODE < 0x020317) /* 2.3.23 */
6102 +#include "serial_compat.h"
6103 +#endif
6104 +
6105 +#include <asm/system.h>
6106 +#include <asm/io.h>
6107 +#include <asm/irq.h>
6108 +#include <asm/bitops.h>
6109 +
6110 +#if defined(CONFIG_MAC_SERIAL)
6111 +#define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2)
6112 +#else
6113 +#define SERIAL_DEV_OFFSET 0
6114 +#endif
6115 +
6116 +#ifdef SERIAL_INLINE
6117 +#define _INLINE_ inline
6118 +#else
6119 +#define _INLINE_
6120 +#endif
6121 +
6122 +static char *serial_name = "Serial driver";
6123 +
6124 +static DECLARE_TASK_QUEUE(tq_serial);
6125 +
6126 +static struct tty_driver serial_driver, callout_driver;
6127 +static int serial_refcount;
6128 +
6129 +static struct timer_list serial_timer;
6130 +
6131 +/* serial subtype definitions */
6132 +#ifndef SERIAL_TYPE_NORMAL
6133 +#define SERIAL_TYPE_NORMAL 1
6134 +#define SERIAL_TYPE_CALLOUT 2
6135 +#endif
6136 +
6137 +/* number of characters left in xmit buffer before we ask for more */
6138 +#define WAKEUP_CHARS 256
6139 +
6140 +/*
6141 + * IRQ_timeout - How long the timeout should be for each IRQ
6142 + * should be after the IRQ has been active.
6143 + */
6144 +
6145 +static struct async_struct *IRQ_ports[NR_IRQS];
6146 +#ifdef CONFIG_SERIAL_MULTIPORT
6147 +static struct rs_multiport_struct rs_multiport[NR_IRQS];
6148 +#endif
6149 +static int IRQ_timeout[NR_IRQS];
6150 +#ifdef CONFIG_SERIAL_CONSOLE
6151 +static struct console sercons;
6152 +static int lsr_break_flag;
6153 +#endif
6154 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6155 +static unsigned long break_pressed; /* break, really ... */
6156 +#endif
6157 +
6158 +static unsigned detect_uart_irq (struct serial_state * state);
6159 +static void autoconfig(struct serial_state * state);
6160 +static void change_speed(struct async_struct *info, struct termios *old);
6161 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
6162 +
6163 +/*
6164 + * Here we define the default xmit fifo size used for each type of
6165 + * UART
6166 + */
6167 +static struct serial_uart_config uart_config[] = {
6168 + { "unknown", 1, 0 },
6169 + { "8250", 1, 0 },
6170 + { "16450", 1, 0 },
6171 + { "16550", 1, 0 },
6172 + { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
6173 + { "cirrus", 1, 0 }, /* usurped by cyclades.c */
6174 + { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
6175 + { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO |
6176 + UART_STARTECH },
6177 + { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO},
6178 + { "Startech", 1, 0}, /* usurped by cyclades.c */
6179 + { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO},
6180 + { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO |
6181 + UART_STARTECH },
6182 + { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO |
6183 + UART_STARTECH },
6184 + { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO },
6185 + { 0, 0}
6186 +};
6187 +
6188 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
6189 +
6190 +#define PORT_RSA_MAX 4
6191 +static int probe_rsa[PORT_RSA_MAX];
6192 +static int force_rsa[PORT_RSA_MAX];
6193 +
6194 +MODULE_PARM(probe_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6195 +MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
6196 +MODULE_PARM(force_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6197 +MODULE_PARM_DESC(force_rsa, "Force I/O ports for RSA");
6198 +#endif /* CONFIG_SERIAL_RSA */
6199 +
6200 +struct serial_state rs_table[RS_TABLE_SIZE] = {
6201 + SERIAL_PORT_DFNS /* Defined in serial.h */
6202 +};
6203 +
6204 +#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state))
6205 +int serial_nr_ports = NR_PORTS;
6206 +
6207 +#if (defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP))
6208 +#define NR_PCI_BOARDS 8
6209 +
6210 +static struct pci_board_inst serial_pci_board[NR_PCI_BOARDS];
6211 +
6212 +#ifndef IS_PCI_REGION_IOPORT
6213 +#define IS_PCI_REGION_IOPORT(dev, r) (pci_resource_flags((dev), (r)) & \
6214 + IORESOURCE_IO)
6215 +#endif
6216 +#ifndef IS_PCI_REGION_IOMEM
6217 +#define IS_PCI_REGION_IOMEM(dev, r) (pci_resource_flags((dev), (r)) & \
6218 + IORESOURCE_MEM)
6219 +#endif
6220 +#ifndef PCI_IRQ_RESOURCE
6221 +#define PCI_IRQ_RESOURCE(dev, r) ((dev)->irq_resource[r].start)
6222 +#endif
6223 +#ifndef pci_get_subvendor
6224 +#define pci_get_subvendor(dev) ((dev)->subsystem_vendor)
6225 +#define pci_get_subdevice(dev) ((dev)->subsystem_device)
6226 +#endif
6227 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
6228 +
6229 +#ifndef PREPARE_FUNC
6230 +#define PREPARE_FUNC(dev) (dev->prepare)
6231 +#define ACTIVATE_FUNC(dev) (dev->activate)
6232 +#define DEACTIVATE_FUNC(dev) (dev->deactivate)
6233 +#endif
6234 +
6235 +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
6236 +
6237 +static struct tty_struct *serial_table[NR_PORTS];
6238 +static struct termios *serial_termios[NR_PORTS];
6239 +static struct termios *serial_termios_locked[NR_PORTS];
6240 +
6241 +
6242 +#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT)
6243 +#define DBG_CNT(s) printk("(%s): [%x] refc=%d, serc=%d, ttyc=%d -> %s\n", \
6244 + kdevname(tty->device), (info->flags), serial_refcount,info->count,tty->count,s)
6245 +#else
6246 +#define DBG_CNT(s)
6247 +#endif
6248 +
6249 +/*
6250 + * tmp_buf is used as a temporary buffer by serial_write. We need to
6251 + * lock it in case the copy_from_user blocks while swapping in a page,
6252 + * and some other program tries to do a serial write at the same time.
6253 + * Since the lock will only come under contention when the system is
6254 + * swapping and available memory is low, it makes sense to share one
6255 + * buffer across all the serial ports, since it significantly saves
6256 + * memory if large numbers of serial ports are open.
6257 + */
6258 +static unsigned char *tmp_buf;
6259 +#ifdef DECLARE_MUTEX
6260 +static DECLARE_MUTEX(tmp_buf_sem);
6261 +#else
6262 +static struct semaphore tmp_buf_sem = MUTEX;
6263 +#endif
6264 +
6265 +
6266 +static inline int serial_paranoia_check(struct async_struct *info,
6267 + kdev_t device, const char *routine)
6268 +{
6269 +#ifdef SERIAL_PARANOIA_CHECK
6270 + static const char *badmagic =
6271 + "Warning: bad magic number for serial struct (%s) in %s\n";
6272 + static const char *badinfo =
6273 + "Warning: null async_struct for (%s) in %s\n";
6274 +
6275 + if (!info) {
6276 + printk(badinfo, kdevname(device), routine);
6277 + return 1;
6278 + }
6279 + if (info->magic != SERIAL_MAGIC) {
6280 + printk(badmagic, kdevname(device), routine);
6281 + return 1;
6282 + }
6283 +#endif
6284 + return 0;
6285 +}
6286 +
6287 +#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
6288 +
6289 +#include <asm/mips-boards/atlas.h>
6290 +
6291 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6292 +{
6293 + return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff);
6294 +}
6295 +
6296 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
6297 +{
6298 + *(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value;
6299 +}
6300 +
6301 +#else
6302 +
6303 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6304 +{
6305 + switch (info->io_type) {
6306 +#ifdef CONFIG_HUB6
6307 + case SERIAL_IO_HUB6:
6308 + outb(info->hub6 - 1 + offset, info->port);
6309 + return inb(info->port+1);
6310 +#endif
6311 + case SERIAL_IO_MEM:
6312 + return readb((unsigned long) info->iomem_base +
6313 + (offset<<info->iomem_reg_shift));
6314 + default:
6315 + return inb(info->port + offset);
6316 + }
6317 +}
6318 +
6319 +static _INLINE_ void serial_out(struct async_struct *info, int offset,
6320 + int value)
6321 +{
6322 + switch (info->io_type) {
6323 +#ifdef CONFIG_HUB6
6324 + case SERIAL_IO_HUB6:
6325 + outb(info->hub6 - 1 + offset, info->port);
6326 + outb(value, info->port+1);
6327 + break;
6328 +#endif
6329 + case SERIAL_IO_MEM:
6330 + writeb(value, (unsigned long) info->iomem_base +
6331 + (offset<<info->iomem_reg_shift));
6332 + break;
6333 + default:
6334 + outb(value, info->port+offset);
6335 + }
6336 +}
6337 +#endif
6338 +
6339 +
6340 +/*
6341 + * We used to support using pause I/O for certain machines. We
6342 + * haven't supported this for a while, but just in case it's badly
6343 + * needed for certain old 386 machines, I've left these #define's
6344 + * in....
6345 + */
6346 +#define serial_inp(info, offset) serial_in(info, offset)
6347 +#define serial_outp(info, offset, value) serial_out(info, offset, value)
6348 +
6349 +
6350 +/*
6351 + * For the 16C950
6352 + */
6353 +void serial_icr_write(struct async_struct *info, int offset, int value)
6354 +{
6355 + serial_out(info, UART_SCR, offset);
6356 + serial_out(info, UART_ICR, value);
6357 +}
6358 +
6359 +unsigned int serial_icr_read(struct async_struct *info, int offset)
6360 +{
6361 + int value;
6362 +
6363 + serial_icr_write(info, UART_ACR, info->ACR | UART_ACR_ICRRD);
6364 + serial_out(info, UART_SCR, offset);
6365 + value = serial_in(info, UART_ICR);
6366 + serial_icr_write(info, UART_ACR, info->ACR);
6367 + return value;
6368 +}
6369 +
6370 +/*
6371 + * ------------------------------------------------------------
6372 + * rs_stop() and rs_start()
6373 + *
6374 + * This routines are called before setting or resetting tty->stopped.
6375 + * They enable or disable transmitter interrupts, as necessary.
6376 + * ------------------------------------------------------------
6377 + */
6378 +static void rs_stop(struct tty_struct *tty)
6379 +{
6380 + struct async_struct *info = (struct async_struct *)tty->driver_data;
6381 + unsigned long flags;
6382 +
6383 + if (serial_paranoia_check(info, tty->device, "rs_stop"))
6384 + return;
6385 +
6386 + save_flags(flags); cli();
6387 + if (info->IER & UART_IER_THRI) {
6388 + info->IER &= ~UART_IER_THRI;
6389 + serial_out(info, UART_IER, info->IER);
6390 + }
6391 + if (info->state->type == PORT_16C950) {
6392 + info->ACR |= UART_ACR_TXDIS;
6393 + serial_icr_write(info, UART_ACR, info->ACR);
6394 + }
6395 + restore_flags(flags);
6396 +}
6397 +
6398 +static void rs_start(struct tty_struct *tty)
6399 +{
6400 + struct async_struct *info = (struct async_struct *)tty->driver_data;
6401 + unsigned long flags;
6402 +
6403 + if (serial_paranoia_check(info, tty->device, "rs_start"))
6404 + return;
6405 +
6406 + save_flags(flags); cli();
6407 + if (info->xmit.head != info->xmit.tail
6408 + && info->xmit.buf
6409 + && !(info->IER & UART_IER_THRI)) {
6410 + info->IER |= UART_IER_THRI;
6411 + serial_out(info, UART_IER, info->IER);
6412 + }
6413 + if (info->state->type == PORT_16C950) {
6414 + info->ACR &= ~UART_ACR_TXDIS;
6415 + serial_icr_write(info, UART_ACR, info->ACR);
6416 + }
6417 + restore_flags(flags);
6418 +}
6419 +
6420 +/*
6421 + * ----------------------------------------------------------------------
6422 + *
6423 + * Here starts the interrupt handling routines. All of the following
6424 + * subroutines are declared as inline and are folded into
6425 + * rs_interrupt(). They were separated out for readability's sake.
6426 + *
6427 + * Note: rs_interrupt() is a "fast" interrupt, which means that it
6428 + * runs with interrupts turned off. People who may want to modify
6429 + * rs_interrupt() should try to keep the interrupt handler as fast as
6430 + * possible. After you are done making modifications, it is not a bad
6431 + * idea to do:
6432 + *
6433 + * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
6434 + *
6435 + * and look at the resulting assemble code in serial.s.
6436 + *
6437 + * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
6438 + * -----------------------------------------------------------------------
6439 + */
6440 +
6441 +/*
6442 + * This routine is used by the interrupt handler to schedule
6443 + * processing in the software interrupt portion of the driver.
6444 + */
6445 +static _INLINE_ void rs_sched_event(struct async_struct *info,
6446 + int event)
6447 +{
6448 + info->event |= 1 << event;
6449 + queue_task(&info->tqueue, &tq_serial);
6450 + mark_bh(SERIAL_BH);
6451 +}
6452 +
6453 +static _INLINE_ void receive_chars(struct async_struct *info,
6454 + int *status, struct pt_regs * regs)
6455 +{
6456 + struct tty_struct *tty = info->tty;
6457 + unsigned char ch;
6458 + struct async_icount *icount;
6459 + int max_count = 256;
6460 +
6461 + icount = &info->state->icount;
6462 + do {
6463 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
6464 + tty->flip.tqueue.routine((void *) tty);
6465 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
6466 + /* no room in flip buffer, discard rx FIFO contents to clear IRQ
6467 + * *FIXME* Hardware with auto flow control
6468 + * would benefit from leaving the data in the FIFO and
6469 + * disabling the rx IRQ until space becomes available.
6470 + */
6471 + do {
6472 + serial_inp(info, UART_RX);
6473 + icount->overrun++;
6474 + *status = serial_inp(info, UART_LSR);
6475 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
6476 + return; // if TTY_DONT_FLIP is set
6477 + }
6478 + }
6479 + ch = serial_inp(info, UART_RX);
6480 + *tty->flip.char_buf_ptr = ch;
6481 + icount->rx++;
6482 +
6483 +#ifdef SERIAL_DEBUG_INTR
6484 + printk("DR%02x:%02x...", ch, *status);
6485 +#endif
6486 + *tty->flip.flag_buf_ptr = 0;
6487 + if (*status & (UART_LSR_BI | UART_LSR_PE |
6488 + UART_LSR_FE | UART_LSR_OE)) {
6489 + /*
6490 + * For statistics only
6491 + */
6492 + if (*status & UART_LSR_BI) {
6493 + *status &= ~(UART_LSR_FE | UART_LSR_PE);
6494 + icount->brk++;
6495 + /*
6496 + * We do the SysRQ and SAK checking
6497 + * here because otherwise the break
6498 + * may get masked by ignore_status_mask
6499 + * or read_status_mask.
6500 + */
6501 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6502 + if (info->line == sercons.index) {
6503 + if (!break_pressed) {
6504 + break_pressed = jiffies;
6505 + goto ignore_char;
6506 + }
6507 + break_pressed = 0;
6508 + }
6509 +#endif
6510 + if (info->flags & ASYNC_SAK)
6511 + do_SAK(tty);
6512 + } else if (*status & UART_LSR_PE)
6513 + icount->parity++;
6514 + else if (*status & UART_LSR_FE)
6515 + icount->frame++;
6516 + if (*status & UART_LSR_OE)
6517 + icount->overrun++;
6518 +
6519 + /*
6520 + * Mask off conditions which should be ignored.
6521 + */
6522 + *status &= info->read_status_mask;
6523 +
6524 +#ifdef CONFIG_SERIAL_CONSOLE
6525 + if (info->line == sercons.index) {
6526 + /* Recover the break flag from console xmit */
6527 + *status |= lsr_break_flag;
6528 + lsr_break_flag = 0;
6529 + }
6530 +#endif
6531 + if (*status & (UART_LSR_BI)) {
6532 +#ifdef SERIAL_DEBUG_INTR
6533 + printk("handling break....");
6534 +#endif
6535 + *tty->flip.flag_buf_ptr = TTY_BREAK;
6536 + } else if (*status & UART_LSR_PE)
6537 + *tty->flip.flag_buf_ptr = TTY_PARITY;
6538 + else if (*status & UART_LSR_FE)
6539 + *tty->flip.flag_buf_ptr = TTY_FRAME;
6540 + }
6541 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6542 + if (break_pressed && info->line == sercons.index) {
6543 + if (ch != 0 &&
6544 + time_before(jiffies, break_pressed + HZ*5)) {
6545 + handle_sysrq(ch, regs, NULL, NULL);
6546 + break_pressed = 0;
6547 + goto ignore_char;
6548 + }
6549 + break_pressed = 0;
6550 + }
6551 +#endif
6552 + if ((*status & info->ignore_status_mask) == 0) {
6553 + tty->flip.flag_buf_ptr++;
6554 + tty->flip.char_buf_ptr++;
6555 + tty->flip.count++;
6556 + }
6557 + if ((*status & UART_LSR_OE) &&
6558 + (tty->flip.count < TTY_FLIPBUF_SIZE)) {
6559 + /*
6560 + * Overrun is special, since it's reported
6561 + * immediately, and doesn't affect the current
6562 + * character
6563 + */
6564 + *tty->flip.flag_buf_ptr = TTY_OVERRUN;
6565 + tty->flip.count++;
6566 + tty->flip.flag_buf_ptr++;
6567 + tty->flip.char_buf_ptr++;
6568 + }
6569 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6570 + ignore_char:
6571 +#endif
6572 + *status = serial_inp(info, UART_LSR);
6573 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
6574 +#if (LINUX_VERSION_CODE > 131394) /* 2.1.66 */
6575 + tty_flip_buffer_push(tty);
6576 +#else
6577 + queue_task_irq_off(&tty->flip.tqueue, &tq_timer);
6578 +#endif
6579 +}
6580 +
6581 +static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done)
6582 +{
6583 + int count;
6584 +
6585 + if (info->x_char) {
6586 + serial_outp(info, UART_TX, info->x_char);
6587 + info->state->icount.tx++;
6588 + info->x_char = 0;
6589 + if (intr_done)
6590 + *intr_done = 0;
6591 + return;
6592 + }
6593 + if (info->xmit.head == info->xmit.tail
6594 + || info->tty->stopped
6595 + || info->tty->hw_stopped) {
6596 + info->IER &= ~UART_IER_THRI;
6597 + serial_out(info, UART_IER, info->IER);
6598 + return;
6599 + }
6600 +
6601 + count = info->xmit_fifo_size;
6602 + do {
6603 + serial_out(info, UART_TX, info->xmit.buf[info->xmit.tail]);
6604 + info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
6605 + info->state->icount.tx++;
6606 + if (info->xmit.head == info->xmit.tail)
6607 + break;
6608 + } while (--count > 0);
6609 +
6610 + if (CIRC_CNT(info->xmit.head,
6611 + info->xmit.tail,
6612 + SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
6613 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
6614 +
6615 +#ifdef SERIAL_DEBUG_INTR
6616 + printk("THRE...");
6617 +#endif
6618 + if (intr_done)
6619 + *intr_done = 0;
6620 +
6621 + if (info->xmit.head == info->xmit.tail) {
6622 + info->IER &= ~UART_IER_THRI;
6623 + serial_out(info, UART_IER, info->IER);
6624 + }
6625 +}
6626 +
6627 +static _INLINE_ void check_modem_status(struct async_struct *info)
6628 +{
6629 + int status;
6630 + struct async_icount *icount;
6631 +
6632 + status = serial_in(info, UART_MSR);
6633 +
6634 + if (status & UART_MSR_ANY_DELTA) {
6635 + icount = &info->state->icount;
6636 + /* update input line counters */
6637 + if (status & UART_MSR_TERI)
6638 + icount->rng++;
6639 + if (status & UART_MSR_DDSR)
6640 + icount->dsr++;
6641 + if (status & UART_MSR_DDCD) {
6642 + icount->dcd++;
6643 +#ifdef CONFIG_HARD_PPS
6644 + if ((info->flags & ASYNC_HARDPPS_CD) &&
6645 + (status & UART_MSR_DCD))
6646 + hardpps();
6647 +#endif
6648 + }
6649 + if (status & UART_MSR_DCTS)
6650 + icount->cts++;
6651 + wake_up_interruptible(&info->delta_msr_wait);
6652 + }
6653 +
6654 + if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
6655 +#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
6656 + printk("ttys%d CD now %s...", info->line,
6657 + (status & UART_MSR_DCD) ? "on" : "off");
6658 +#endif
6659 + if (status & UART_MSR_DCD)
6660 + wake_up_interruptible(&info->open_wait);
6661 + else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
6662 + (info->flags & ASYNC_CALLOUT_NOHUP))) {
6663 +#ifdef SERIAL_DEBUG_OPEN
6664 + printk("doing serial hangup...");
6665 +#endif
6666 + if (info->tty)
6667 + tty_hangup(info->tty);
6668 + }
6669 + }
6670 + if (info->flags & ASYNC_CTS_FLOW) {
6671 + if (info->tty->hw_stopped) {
6672 + if (status & UART_MSR_CTS) {
6673 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
6674 + printk("CTS tx start...");
6675 +#endif
6676 + info->tty->hw_stopped = 0;
6677 + info->IER |= UART_IER_THRI;
6678 + serial_out(info, UART_IER, info->IER);
6679 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
6680 + return;
6681 + }
6682 + } else {
6683 + if (!(status & UART_MSR_CTS)) {
6684 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
6685 + printk("CTS tx stop...");
6686 +#endif
6687 + info->tty->hw_stopped = 1;
6688 + info->IER &= ~UART_IER_THRI;
6689 + serial_out(info, UART_IER, info->IER);
6690 + }
6691 + }
6692 + }
6693 +}
6694 +
6695 +#ifdef CONFIG_SERIAL_SHARE_IRQ
6696 +/*
6697 + * This is the serial driver's generic interrupt routine
6698 + */
6699 +static void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs)
6700 +{
6701 + int status, iir;
6702 + struct async_struct * info;
6703 + int pass_counter = 0;
6704 + struct async_struct *end_mark = 0;
6705 +#ifdef CONFIG_SERIAL_MULTIPORT
6706 + int first_multi = 0;
6707 + struct rs_multiport_struct *multi;
6708 +#endif
6709 +
6710 +#ifdef SERIAL_DEBUG_INTR
6711 + printk("rs_interrupt(%d)...", irq);
6712 +#endif
6713 +
6714 + info = IRQ_ports[irq];
6715 + if (!info)
6716 + return;
6717 +
6718 +#ifdef CONFIG_SERIAL_MULTIPORT
6719 + multi = &rs_multiport[irq];
6720 + if (multi->port_monitor)
6721 + first_multi = inb(multi->port_monitor);
6722 +#endif
6723 +
6724 + do {
6725 + if (!info->tty ||
6726 + ((iir=serial_in(info, UART_IIR)) & UART_IIR_NO_INT)) {
6727 + if (!end_mark)
6728 + end_mark = info;
6729 + goto next;
6730 + }
6731 +#ifdef SERIAL_DEBUG_INTR
6732 + printk("IIR = %x...", serial_in(info, UART_IIR));
6733 +#endif
6734 + end_mark = 0;
6735 +
6736 + info->last_active = jiffies;
6737 +
6738 + status = serial_inp(info, UART_LSR);
6739 +#ifdef SERIAL_DEBUG_INTR
6740 + printk("status = %x...", status);
6741 +#endif
6742 + if (status & UART_LSR_DR)
6743 + receive_chars(info, &status, regs);
6744 + check_modem_status(info);
6745 +#ifdef CONFIG_MELAN
6746 + if ((status & UART_LSR_THRE) ||
6747 + /* for buggy ELAN processors */
6748 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
6749 + transmit_chars(info, 0);
6750 +#else
6751 + if (status & UART_LSR_THRE)
6752 + transmit_chars(info, 0);
6753 +#endif
6754 +
6755 + next:
6756 + info = info->next_port;
6757 + if (!info) {
6758 + info = IRQ_ports[irq];
6759 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6760 +#if 0
6761 + printk("rs loop break\n");
6762 +#endif
6763 + break; /* Prevent infinite loops */
6764 + }
6765 + continue;
6766 + }
6767 + } while (end_mark != info);
6768 +#ifdef CONFIG_SERIAL_MULTIPORT
6769 + if (multi->port_monitor)
6770 + printk("rs port monitor (normal) irq %d: 0x%x, 0x%x\n",
6771 + info->state->irq, first_multi,
6772 + inb(multi->port_monitor));
6773 +#endif
6774 +#ifdef SERIAL_DEBUG_INTR
6775 + printk("end.\n");
6776 +#endif
6777 +}
6778 +#endif /* #ifdef CONFIG_SERIAL_SHARE_IRQ */
6779 +
6780 +
6781 +/*
6782 + * This is the serial driver's interrupt routine for a single port
6783 + */
6784 +static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs)
6785 +{
6786 + int status, iir;
6787 + int pass_counter = 0;
6788 + struct async_struct * info;
6789 +#ifdef CONFIG_SERIAL_MULTIPORT
6790 + int first_multi = 0;
6791 + struct rs_multiport_struct *multi;
6792 +#endif
6793 +
6794 +#ifdef SERIAL_DEBUG_INTR
6795 + printk("rs_interrupt_single(%d)...", irq);
6796 +#endif
6797 +
6798 + info = IRQ_ports[irq];
6799 + if (!info || !info->tty)
6800 + return;
6801 +
6802 +#ifdef CONFIG_SERIAL_MULTIPORT
6803 + multi = &rs_multiport[irq];
6804 + if (multi->port_monitor)
6805 + first_multi = inb(multi->port_monitor);
6806 +#endif
6807 +
6808 + iir = serial_in(info, UART_IIR);
6809 + do {
6810 + status = serial_inp(info, UART_LSR);
6811 +#ifdef SERIAL_DEBUG_INTR
6812 + printk("status = %x...", status);
6813 +#endif
6814 + if (status & UART_LSR_DR)
6815 + receive_chars(info, &status, regs);
6816 + check_modem_status(info);
6817 +#ifdef CONFIG_MELAN
6818 + if ((status & UART_LSR_THRE) ||
6819 + /* For buggy ELAN processors */
6820 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
6821 + transmit_chars(info, 0);
6822 +#else
6823 + if (status & UART_LSR_THRE)
6824 + transmit_chars(info, 0);
6825 +#endif
6826 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6827 +#if SERIAL_DEBUG_INTR
6828 + printk("rs_single loop break.\n");
6829 +#endif
6830 + break;
6831 + }
6832 + iir = serial_in(info, UART_IIR);
6833 +#ifdef SERIAL_DEBUG_INTR
6834 + printk("IIR = %x...", iir);
6835 +#endif
6836 + } while ((iir & UART_IIR_NO_INT) == 0);
6837 + info->last_active = jiffies;
6838 +#ifdef CONFIG_SERIAL_MULTIPORT
6839 + if (multi->port_monitor)
6840 + printk("rs port monitor (single) irq %d: 0x%x, 0x%x\n",
6841 + info->state->irq, first_multi,
6842 + inb(multi->port_monitor));
6843 +#endif
6844 +#ifdef SERIAL_DEBUG_INTR
6845 + printk("end.\n");
6846 +#endif
6847 +}
6848 +
6849 +#ifdef CONFIG_SERIAL_MULTIPORT
6850 +/*
6851 + * This is the serial driver's for multiport boards
6852 + */
6853 +static void rs_interrupt_multi(int irq, void *dev_id, struct pt_regs * regs)
6854 +{
6855 + int status;
6856 + struct async_struct * info;
6857 + int pass_counter = 0;
6858 + int first_multi= 0;
6859 + struct rs_multiport_struct *multi;
6860 +
6861 +#ifdef SERIAL_DEBUG_INTR
6862 + printk("rs_interrupt_multi(%d)...", irq);
6863 +#endif
6864 +
6865 + info = IRQ_ports[irq];
6866 + if (!info)
6867 + return;
6868 + multi = &rs_multiport[irq];
6869 + if (!multi->port1) {
6870 + /* Should never happen */
6871 + printk("rs_interrupt_multi: NULL port1!\n");
6872 + return;
6873 + }
6874 + if (multi->port_monitor)
6875 + first_multi = inb(multi->port_monitor);
6876 +
6877 + while (1) {
6878 + if (!info->tty ||
6879 + (serial_in(info, UART_IIR) & UART_IIR_NO_INT))
6880 + goto next;
6881 +
6882 + info->last_active = jiffies;
6883 +
6884 + status = serial_inp(info, UART_LSR);
6885 +#ifdef SERIAL_DEBUG_INTR
6886 + printk("status = %x...", status);
6887 +#endif
6888 + if (status & UART_LSR_DR)
6889 + receive_chars(info, &status, regs);
6890 + check_modem_status(info);
6891 + if (status & UART_LSR_THRE)
6892 + transmit_chars(info, 0);
6893 +
6894 + next:
6895 + info = info->next_port;
6896 + if (info)
6897 + continue;
6898 +
6899 + info = IRQ_ports[irq];
6900 + /*
6901 + * The user was a bonehead, and misconfigured their
6902 + * multiport info. Rather than lock up the kernel
6903 + * in an infinite loop, if we loop too many times,
6904 + * print a message and break out of the loop.
6905 + */
6906 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
6907 + printk("Misconfigured multiport serial info "
6908 + "for irq %d. Breaking out irq loop\n", irq);
6909 + break;
6910 + }
6911 + if (multi->port_monitor)
6912 + printk("rs port monitor irq %d: 0x%x, 0x%x\n",
6913 + info->state->irq, first_multi,
6914 + inb(multi->port_monitor));
6915 + if ((inb(multi->port1) & multi->mask1) != multi->match1)
6916 + continue;
6917 + if (!multi->port2)
6918 + break;
6919 + if ((inb(multi->port2) & multi->mask2) != multi->match2)
6920 + continue;
6921 + if (!multi->port3)
6922 + break;
6923 + if ((inb(multi->port3) & multi->mask3) != multi->match3)
6924 + continue;
6925 + if (!multi->port4)
6926 + break;
6927 + if ((inb(multi->port4) & multi->mask4) != multi->match4)
6928 + continue;
6929 + break;
6930 + }
6931 +#ifdef SERIAL_DEBUG_INTR
6932 + printk("end.\n");
6933 +#endif
6934 +}
6935 +#endif
6936 +
6937 +/*
6938 + * -------------------------------------------------------------------
6939 + * Here ends the serial interrupt routines.
6940 + * -------------------------------------------------------------------
6941 + */
6942 +
6943 +/*
6944 + * This routine is used to handle the "bottom half" processing for the
6945 + * serial driver, known also the "software interrupt" processing.
6946 + * This processing is done at the kernel interrupt level, after the
6947 + * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
6948 + * is where time-consuming activities which can not be done in the
6949 + * interrupt driver proper are done; the interrupt driver schedules
6950 + * them using rs_sched_event(), and they get done here.
6951 + */
6952 +static void do_serial_bh(void)
6953 +{
6954 + run_task_queue(&tq_serial);
6955 +}
6956 +
6957 +static void do_softint(void *private_)
6958 +{
6959 + struct async_struct *info = (struct async_struct *) private_;
6960 + struct tty_struct *tty;
6961 +
6962 + tty = info->tty;
6963 + if (!tty)
6964 + return;
6965 +
6966 + if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) {
6967 + tty_wakeup(tty);
6968 +
6969 +#ifdef SERIAL_HAVE_POLL_WAIT
6970 + wake_up_interruptible(&tty->poll_wait);
6971 +#endif
6972 + }
6973 +}
6974 +
6975 +/*
6976 + * This subroutine is called when the RS_TIMER goes off. It is used
6977 + * by the serial driver to handle ports that do not have an interrupt
6978 + * (irq=0). This doesn't work very well for 16450's, but gives barely
6979 + * passable results for a 16550A. (Although at the expense of much
6980 + * CPU overhead).
6981 + */
6982 +static void rs_timer(unsigned long dummy)
6983 +{
6984 + static unsigned long last_strobe;
6985 + struct async_struct *info;
6986 + unsigned int i;
6987 + unsigned long flags;
6988 +
6989 + if ((jiffies - last_strobe) >= RS_STROBE_TIME) {
6990 + for (i=0; i < NR_IRQS; i++) {
6991 + info = IRQ_ports[i];
6992 + if (!info)
6993 + continue;
6994 + save_flags(flags); cli();
6995 +#ifdef CONFIG_SERIAL_SHARE_IRQ
6996 + if (info->next_port) {
6997 + do {
6998 + serial_out(info, UART_IER, 0);
6999 + info->IER |= UART_IER_THRI;
7000 + serial_out(info, UART_IER, info->IER);
7001 + info = info->next_port;
7002 + } while (info);
7003 +#ifdef CONFIG_SERIAL_MULTIPORT
7004 + if (rs_multiport[i].port1)
7005 + rs_interrupt_multi(i, NULL, NULL);
7006 + else
7007 +#endif
7008 + rs_interrupt(i, NULL, NULL);
7009 + } else
7010 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
7011 + rs_interrupt_single(i, NULL, NULL);
7012 + restore_flags(flags);
7013 + }
7014 + }
7015 + last_strobe = jiffies;
7016 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
7017 +
7018 + if (IRQ_ports[0]) {
7019 + save_flags(flags); cli();
7020 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7021 + rs_interrupt(0, NULL, NULL);
7022 +#else
7023 + rs_interrupt_single(0, NULL, NULL);
7024 +#endif
7025 + restore_flags(flags);
7026 +
7027 + mod_timer(&serial_timer, jiffies + IRQ_timeout[0]);
7028 + }
7029 +}
7030 +
7031 +/*
7032 + * ---------------------------------------------------------------
7033 + * Low level utility subroutines for the serial driver: routines to
7034 + * figure out the appropriate timeout for an interrupt chain, routines
7035 + * to initialize and startup a serial port, and routines to shutdown a
7036 + * serial port. Useful stuff like that.
7037 + * ---------------------------------------------------------------
7038 + */
7039 +
7040 +/*
7041 + * This routine figures out the correct timeout for a particular IRQ.
7042 + * It uses the smallest timeout of all of the serial ports in a
7043 + * particular interrupt chain. Now only used for IRQ 0....
7044 + */
7045 +static void figure_IRQ_timeout(int irq)
7046 +{
7047 + struct async_struct *info;
7048 + int timeout = 60*HZ; /* 60 seconds === a long time :-) */
7049 +
7050 + info = IRQ_ports[irq];
7051 + if (!info) {
7052 + IRQ_timeout[irq] = 60*HZ;
7053 + return;
7054 + }
7055 + while (info) {
7056 + if (info->timeout < timeout)
7057 + timeout = info->timeout;
7058 + info = info->next_port;
7059 + }
7060 + if (!irq)
7061 + timeout = timeout / 2;
7062 + IRQ_timeout[irq] = (timeout > 3) ? timeout-2 : 1;
7063 +}
7064 +
7065 +#ifdef CONFIG_SERIAL_RSA
7066 +/* Attempts to turn on the RSA FIFO. Returns zero on failure */
7067 +static int enable_rsa(struct async_struct *info)
7068 +{
7069 + unsigned char mode;
7070 + int result;
7071 + unsigned long flags;
7072 +
7073 + save_flags(flags); cli();
7074 + mode = serial_inp(info, UART_RSA_MSR);
7075 + result = mode & UART_RSA_MSR_FIFO;
7076 +
7077 + if (!result) {
7078 + serial_outp(info, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
7079 + mode = serial_inp(info, UART_RSA_MSR);
7080 + result = mode & UART_RSA_MSR_FIFO;
7081 + }
7082 +
7083 + restore_flags(flags);
7084 + return result;
7085 +}
7086 +
7087 +/* Attempts to turn off the RSA FIFO. Returns zero on failure */
7088 +static int disable_rsa(struct async_struct *info)
7089 +{
7090 + unsigned char mode;
7091 + int result;
7092 + unsigned long flags;
7093 +
7094 + save_flags(flags); cli();
7095 + mode = serial_inp(info, UART_RSA_MSR);
7096 + result = !(mode & UART_RSA_MSR_FIFO);
7097 +
7098 + if (!result) {
7099 + serial_outp(info, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
7100 + mode = serial_inp(info, UART_RSA_MSR);
7101 + result = !(mode & UART_RSA_MSR_FIFO);
7102 + }
7103 +
7104 + restore_flags(flags);
7105 + return result;
7106 +}
7107 +#endif /* CONFIG_SERIAL_RSA */
7108 +
7109 +static int startup(struct async_struct * info)
7110 +{
7111 + unsigned long flags;
7112 + int retval=0;
7113 + void (*handler)(int, void *, struct pt_regs *);
7114 + struct serial_state *state= info->state;
7115 + unsigned long page;
7116 +#ifdef CONFIG_SERIAL_MANY_PORTS
7117 + unsigned short ICP;
7118 +#endif
7119 +
7120 + page = get_zeroed_page(GFP_KERNEL);
7121 + if (!page)
7122 + return -ENOMEM;
7123 +
7124 + save_flags(flags); cli();
7125 +
7126 + if (info->flags & ASYNC_INITIALIZED) {
7127 + free_page(page);
7128 + goto errout;
7129 + }
7130 +
7131 + if (!CONFIGURED_SERIAL_PORT(state) || !state->type) {
7132 + if (info->tty)
7133 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7134 + free_page(page);
7135 + goto errout;
7136 + }
7137 + if (info->xmit.buf)
7138 + free_page(page);
7139 + else
7140 + info->xmit.buf = (unsigned char *) page;
7141 +
7142 +#ifdef SERIAL_DEBUG_OPEN
7143 + printk("starting up ttys%d (irq %d)...", info->line, state->irq);
7144 +#endif
7145 +
7146 + if (uart_config[state->type].flags & UART_STARTECH) {
7147 + /* Wake up UART */
7148 + serial_outp(info, UART_LCR, 0xBF);
7149 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7150 + /*
7151 + * Turn off LCR == 0xBF so we actually set the IER
7152 + * register on the XR16C850
7153 + */
7154 + serial_outp(info, UART_LCR, 0);
7155 + serial_outp(info, UART_IER, 0);
7156 + /*
7157 + * Now reset LCR so we can turn off the ECB bit
7158 + */
7159 + serial_outp(info, UART_LCR, 0xBF);
7160 + serial_outp(info, UART_EFR, 0);
7161 + /*
7162 + * For a XR16C850, we need to set the trigger levels
7163 + */
7164 + if (state->type == PORT_16850) {
7165 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7166 + UART_FCTR_RX);
7167 + serial_outp(info, UART_TRG, UART_TRG_96);
7168 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7169 + UART_FCTR_TX);
7170 + serial_outp(info, UART_TRG, UART_TRG_96);
7171 + }
7172 + serial_outp(info, UART_LCR, 0);
7173 + }
7174 +
7175 + if (state->type == PORT_16750) {
7176 + /* Wake up UART */
7177 + serial_outp(info, UART_IER, 0);
7178 + }
7179 +
7180 + if (state->type == PORT_16C950) {
7181 + /* Wake up and initialize UART */
7182 + info->ACR = 0;
7183 + serial_outp(info, UART_LCR, 0xBF);
7184 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7185 + serial_outp(info, UART_IER, 0);
7186 + serial_outp(info, UART_LCR, 0);
7187 + serial_icr_write(info, UART_CSR, 0); /* Reset the UART */
7188 + serial_outp(info, UART_LCR, 0xBF);
7189 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7190 + serial_outp(info, UART_LCR, 0);
7191 + }
7192 +
7193 +#ifdef CONFIG_SERIAL_RSA
7194 + /*
7195 + * If this is an RSA port, see if we can kick it up to the
7196 + * higher speed clock.
7197 + */
7198 + if (state->type == PORT_RSA) {
7199 + if (state->baud_base != SERIAL_RSA_BAUD_BASE &&
7200 + enable_rsa(info))
7201 + state->baud_base = SERIAL_RSA_BAUD_BASE;
7202 + if (state->baud_base == SERIAL_RSA_BAUD_BASE)
7203 + serial_outp(info, UART_RSA_FRR, 0);
7204 + }
7205 +#endif
7206 +
7207 + /*
7208 + * Clear the FIFO buffers and disable them
7209 + * (they will be reenabled in change_speed())
7210 + */
7211 + if (uart_config[state->type].flags & UART_CLEAR_FIFO) {
7212 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
7213 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
7214 + UART_FCR_CLEAR_RCVR |
7215 + UART_FCR_CLEAR_XMIT));
7216 + serial_outp(info, UART_FCR, 0);
7217 + }
7218 +
7219 + /*
7220 + * Clear the interrupt registers.
7221 + */
7222 + (void) serial_inp(info, UART_LSR);
7223 + (void) serial_inp(info, UART_RX);
7224 + (void) serial_inp(info, UART_IIR);
7225 + (void) serial_inp(info, UART_MSR);
7226 +
7227 + /*
7228 + * At this point there's no way the LSR could still be 0xFF;
7229 + * if it is, then bail out, because there's likely no UART
7230 + * here.
7231 + */
7232 + if (!(info->flags & ASYNC_BUGGY_UART) &&
7233 + (serial_inp(info, UART_LSR) == 0xff)) {
7234 + printk("ttyS%d: LSR safety check engaged!\n", state->line);
7235 + if (capable(CAP_SYS_ADMIN)) {
7236 + if (info->tty)
7237 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7238 + } else
7239 + retval = -ENODEV;
7240 + goto errout;
7241 + }
7242 +
7243 + /*
7244 + * Allocate the IRQ if necessary
7245 + */
7246 + if (state->irq && (!IRQ_ports[state->irq] ||
7247 + !IRQ_ports[state->irq]->next_port)) {
7248 + if (IRQ_ports[state->irq]) {
7249 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7250 + free_irq(state->irq, &IRQ_ports[state->irq]);
7251 +#ifdef CONFIG_SERIAL_MULTIPORT
7252 + if (rs_multiport[state->irq].port1)
7253 + handler = rs_interrupt_multi;
7254 + else
7255 +#endif
7256 + handler = rs_interrupt;
7257 +#else
7258 + retval = -EBUSY;
7259 + goto errout;
7260 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
7261 + } else
7262 + handler = rs_interrupt_single;
7263 +
7264 + retval = request_irq(state->irq, handler, SA_SHIRQ,
7265 + "serial", &IRQ_ports[state->irq]);
7266 + if (retval) {
7267 + if (capable(CAP_SYS_ADMIN)) {
7268 + if (info->tty)
7269 + set_bit(TTY_IO_ERROR,
7270 + &info->tty->flags);
7271 + retval = 0;
7272 + }
7273 + goto errout;
7274 + }
7275 + }
7276 +
7277 + /*
7278 + * Insert serial port into IRQ chain.
7279 + */
7280 + info->prev_port = 0;
7281 + info->next_port = IRQ_ports[state->irq];
7282 + if (info->next_port)
7283 + info->next_port->prev_port = info;
7284 + IRQ_ports[state->irq] = info;
7285 + figure_IRQ_timeout(state->irq);
7286 +
7287 + /*
7288 + * Now, initialize the UART
7289 + */
7290 + serial_outp(info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
7291 +
7292 + info->MCR = 0;
7293 + if (info->tty->termios->c_cflag & CBAUD)
7294 + info->MCR = UART_MCR_DTR | UART_MCR_RTS;
7295 +#ifdef CONFIG_SERIAL_MANY_PORTS
7296 + if (info->flags & ASYNC_FOURPORT) {
7297 + if (state->irq == 0)
7298 + info->MCR |= UART_MCR_OUT1;
7299 + } else
7300 +#endif
7301 + {
7302 + if (state->irq != 0)
7303 + info->MCR |= UART_MCR_OUT2;
7304 + }
7305 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
7306 + serial_outp(info, UART_MCR, info->MCR);
7307 +
7308 + /*
7309 + * Finally, enable interrupts
7310 + */
7311 + info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
7312 + serial_outp(info, UART_IER, info->IER); /* enable interrupts */
7313 +
7314 +#ifdef CONFIG_SERIAL_MANY_PORTS
7315 + if (info->flags & ASYNC_FOURPORT) {
7316 + /* Enable interrupts on the AST Fourport board */
7317 + ICP = (info->port & 0xFE0) | 0x01F;
7318 + outb_p(0x80, ICP);
7319 + (void) inb_p(ICP);
7320 + }
7321 +#endif
7322 +
7323 + /*
7324 + * And clear the interrupt registers again for luck.
7325 + */
7326 + (void)serial_inp(info, UART_LSR);
7327 + (void)serial_inp(info, UART_RX);
7328 + (void)serial_inp(info, UART_IIR);
7329 + (void)serial_inp(info, UART_MSR);
7330 +
7331 + if (info->tty)
7332 + clear_bit(TTY_IO_ERROR, &info->tty->flags);
7333 + info->xmit.head = info->xmit.tail = 0;
7334 +
7335 + /*
7336 + * Set up serial timers...
7337 + */
7338 + mod_timer(&serial_timer, jiffies + 2*HZ/100);
7339 +
7340 + /*
7341 + * Set up the tty->alt_speed kludge
7342 + */
7343 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
7344 + if (info->tty) {
7345 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
7346 + info->tty->alt_speed = 57600;
7347 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
7348 + info->tty->alt_speed = 115200;
7349 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
7350 + info->tty->alt_speed = 230400;
7351 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
7352 + info->tty->alt_speed = 460800;
7353 + }
7354 +#endif
7355 +
7356 + /*
7357 + * and set the speed of the serial port
7358 + */
7359 + change_speed(info, 0);
7360 +
7361 + info->flags |= ASYNC_INITIALIZED;
7362 + restore_flags(flags);
7363 + return 0;
7364 +
7365 +errout:
7366 + restore_flags(flags);
7367 + return retval;
7368 +}
7369 +
7370 +/*
7371 + * This routine will shutdown a serial port; interrupts are disabled, and
7372 + * DTR is dropped if the hangup on close termio flag is on.
7373 + */
7374 +static void shutdown(struct async_struct * info)
7375 +{
7376 + unsigned long flags;
7377 + struct serial_state *state;
7378 + int retval;
7379 +
7380 + if (!(info->flags & ASYNC_INITIALIZED))
7381 + return;
7382 +
7383 + state = info->state;
7384 +
7385 +#ifdef SERIAL_DEBUG_OPEN
7386 + printk("Shutting down serial port %d (irq %d)....", info->line,
7387 + state->irq);
7388 +#endif
7389 +
7390 + save_flags(flags); cli(); /* Disable interrupts */
7391 +
7392 + /*
7393 + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
7394 + * here so the queue might never be waken up
7395 + */
7396 + wake_up_interruptible(&info->delta_msr_wait);
7397 +
7398 + /*
7399 + * First unlink the serial port from the IRQ chain...
7400 + */
7401 + if (info->next_port)
7402 + info->next_port->prev_port = info->prev_port;
7403 + if (info->prev_port)
7404 + info->prev_port->next_port = info->next_port;
7405 + else
7406 + IRQ_ports[state->irq] = info->next_port;
7407 + figure_IRQ_timeout(state->irq);
7408 +
7409 + /*
7410 + * Free the IRQ, if necessary
7411 + */
7412 + if (state->irq && (!IRQ_ports[state->irq] ||
7413 + !IRQ_ports[state->irq]->next_port)) {
7414 + if (IRQ_ports[state->irq]) {
7415 + free_irq(state->irq, &IRQ_ports[state->irq]);
7416 + retval = request_irq(state->irq, rs_interrupt_single,
7417 + SA_SHIRQ, "serial",
7418 + &IRQ_ports[state->irq]);
7419 +
7420 + if (retval)
7421 + printk("serial shutdown: request_irq: error %d"
7422 + " Couldn't reacquire IRQ.\n", retval);
7423 + } else
7424 + free_irq(state->irq, &IRQ_ports[state->irq]);
7425 + }
7426 +
7427 + if (info->xmit.buf) {
7428 + unsigned long pg = (unsigned long) info->xmit.buf;
7429 + info->xmit.buf = 0;
7430 + free_page(pg);
7431 + }
7432 +
7433 + info->IER = 0;
7434 + serial_outp(info, UART_IER, 0x00); /* disable all intrs */
7435 +#ifdef CONFIG_SERIAL_MANY_PORTS
7436 + if (info->flags & ASYNC_FOURPORT) {
7437 + /* reset interrupts on the AST Fourport board */
7438 + (void) inb((info->port & 0xFE0) | 0x01F);
7439 + info->MCR |= UART_MCR_OUT1;
7440 + } else
7441 +#endif
7442 + info->MCR &= ~UART_MCR_OUT2;
7443 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
7444 +
7445 + /* disable break condition */
7446 + serial_out(info, UART_LCR, serial_inp(info, UART_LCR) & ~UART_LCR_SBC);
7447 +
7448 + if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
7449 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
7450 + serial_outp(info, UART_MCR, info->MCR);
7451 +
7452 + /* disable FIFO's */
7453 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
7454 + UART_FCR_CLEAR_RCVR |
7455 + UART_FCR_CLEAR_XMIT));
7456 + serial_outp(info, UART_FCR, 0);
7457 +
7458 +#ifdef CONFIG_SERIAL_RSA
7459 + /*
7460 + * Reset the RSA board back to 115kbps compat mode.
7461 + */
7462 + if ((state->type == PORT_RSA) &&
7463 + (state->baud_base == SERIAL_RSA_BAUD_BASE &&
7464 + disable_rsa(info)))
7465 + state->baud_base = SERIAL_RSA_BAUD_BASE_LO;
7466 +#endif
7467 +
7468 +
7469 + (void)serial_in(info, UART_RX); /* read data port to reset things */
7470 +
7471 + if (info->tty)
7472 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7473 +
7474 + if (uart_config[info->state->type].flags & UART_STARTECH) {
7475 + /* Arrange to enter sleep mode */
7476 + serial_outp(info, UART_LCR, 0xBF);
7477 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7478 + serial_outp(info, UART_LCR, 0);
7479 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
7480 + serial_outp(info, UART_LCR, 0xBF);
7481 + serial_outp(info, UART_EFR, 0);
7482 + serial_outp(info, UART_LCR, 0);
7483 + }
7484 + if (info->state->type == PORT_16750) {
7485 + /* Arrange to enter sleep mode */
7486 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
7487 + }
7488 + info->flags &= ~ASYNC_INITIALIZED;
7489 + restore_flags(flags);
7490 +}
7491 +
7492 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
7493 +static int baud_table[] = {
7494 + 0, 50, 75, 110, 134, 150, 200, 300,
7495 + 600, 1200, 1800, 2400, 4800, 9600, 19200,
7496 + 38400, 57600, 115200, 230400, 460800, 0 };
7497 +
7498 +static int tty_get_baud_rate(struct tty_struct *tty)
7499 +{
7500 + struct async_struct * info = (struct async_struct *)tty->driver_data;
7501 + unsigned int cflag, i;
7502 +
7503 + cflag = tty->termios->c_cflag;
7504 +
7505 + i = cflag & CBAUD;
7506 + if (i & CBAUDEX) {
7507 + i &= ~CBAUDEX;
7508 + if (i < 1 || i > 2)
7509 + tty->termios->c_cflag &= ~CBAUDEX;
7510 + else
7511 + i += 15;
7512 + }
7513 + if (i == 15) {
7514 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
7515 + i += 1;
7516 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
7517 + i += 2;
7518 + }
7519 + return baud_table[i];
7520 +}
7521 +#endif
7522 +
7523 +/*
7524 + * This routine is called to set the UART divisor registers to match
7525 + * the specified baud rate for a serial port.
7526 + */
7527 +static void change_speed(struct async_struct *info,
7528 + struct termios *old_termios)
7529 +{
7530 + int quot = 0, baud_base, baud;
7531 + unsigned cflag, cval, fcr = 0;
7532 + int bits;
7533 + unsigned long flags;
7534 +
7535 + if (!info->tty || !info->tty->termios)
7536 + return;
7537 + cflag = info->tty->termios->c_cflag;
7538 + if (!CONFIGURED_SERIAL_PORT(info))
7539 + return;
7540 +
7541 + /* byte size and parity */
7542 + switch (cflag & CSIZE) {
7543 + case CS5: cval = 0x00; bits = 7; break;
7544 + case CS6: cval = 0x01; bits = 8; break;
7545 + case CS7: cval = 0x02; bits = 9; break;
7546 + case CS8: cval = 0x03; bits = 10; break;
7547 + /* Never happens, but GCC is too dumb to figure it out */
7548 + default: cval = 0x00; bits = 7; break;
7549 + }
7550 + if (cflag & CSTOPB) {
7551 + cval |= 0x04;
7552 + bits++;
7553 + }
7554 + if (cflag & PARENB) {
7555 + cval |= UART_LCR_PARITY;
7556 + bits++;
7557 + }
7558 + if (!(cflag & PARODD))
7559 + cval |= UART_LCR_EPAR;
7560 +#ifdef CMSPAR
7561 + if (cflag & CMSPAR)
7562 + cval |= UART_LCR_SPAR;
7563 +#endif
7564 +
7565 + /* Determine divisor based on baud rate */
7566 + baud = tty_get_baud_rate(info->tty);
7567 + if (!baud)
7568 + baud = 9600; /* B0 transition handled in rs_set_termios */
7569 +#ifdef CONFIG_SERIAL_RSA
7570 + if ((info->state->type == PORT_RSA) &&
7571 + (info->state->baud_base != SERIAL_RSA_BAUD_BASE) &&
7572 + enable_rsa(info))
7573 + info->state->baud_base = SERIAL_RSA_BAUD_BASE;
7574 +#endif
7575 + baud_base = info->state->baud_base;
7576 + if (info->state->type == PORT_16C950) {
7577 + if (baud <= baud_base)
7578 + serial_icr_write(info, UART_TCR, 0);
7579 + else if (baud <= 2*baud_base) {
7580 + serial_icr_write(info, UART_TCR, 0x8);
7581 + baud_base = baud_base * 2;
7582 + } else if (baud <= 4*baud_base) {
7583 + serial_icr_write(info, UART_TCR, 0x4);
7584 + baud_base = baud_base * 4;
7585 + } else
7586 + serial_icr_write(info, UART_TCR, 0);
7587 + }
7588 + if (baud == 38400 &&
7589 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
7590 + quot = info->state->custom_divisor;
7591 + else {
7592 + if (baud == 134)
7593 + /* Special case since 134 is really 134.5 */
7594 + quot = (2*baud_base / 269);
7595 + else if (baud)
7596 + quot = baud_base / baud;
7597 + }
7598 + /* If the quotient is zero refuse the change */
7599 + if (!quot && old_termios) {
7600 + info->tty->termios->c_cflag &= ~CBAUD;
7601 + info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD);
7602 + baud = tty_get_baud_rate(info->tty);
7603 + if (!baud)
7604 + baud = 9600;
7605 + if (baud == 38400 &&
7606 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
7607 + quot = info->state->custom_divisor;
7608 + else {
7609 + if (baud == 134)
7610 + /* Special case since 134 is really 134.5 */
7611 + quot = (2*baud_base / 269);
7612 + else if (baud)
7613 + quot = baud_base / baud;
7614 + }
7615 + }
7616 + /* As a last resort, if the quotient is zero, default to 9600 bps */
7617 + if (!quot)
7618 + quot = baud_base / 9600;
7619 + /*
7620 + * Work around a bug in the Oxford Semiconductor 952 rev B
7621 + * chip which causes it to seriously miscalculate baud rates
7622 + * when DLL is 0.
7623 + */
7624 + if (((quot & 0xFF) == 0) && (info->state->type == PORT_16C950) &&
7625 + (info->state->revision == 0x5201))
7626 + quot++;
7627 +
7628 + info->quot = quot;
7629 + info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base);
7630 + info->timeout += HZ/50; /* Add .02 seconds of slop */
7631 +
7632 + /* Set up FIFO's */
7633 + if (uart_config[info->state->type].flags & UART_USE_FIFO) {
7634 + if ((info->state->baud_base / quot) < 2400)
7635 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
7636 +#ifdef CONFIG_SERIAL_RSA
7637 + else if (info->state->type == PORT_RSA)
7638 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
7639 +#endif
7640 + else
7641 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
7642 + }
7643 + if (info->state->type == PORT_16750)
7644 + fcr |= UART_FCR7_64BYTE;
7645 +
7646 + /* CTS flow control flag and modem status interrupts */
7647 + info->IER &= ~UART_IER_MSI;
7648 + if (info->flags & ASYNC_HARDPPS_CD)
7649 + info->IER |= UART_IER_MSI;
7650 + if (cflag & CRTSCTS) {
7651 + info->flags |= ASYNC_CTS_FLOW;
7652 + info->IER |= UART_IER_MSI;
7653 + } else
7654 + info->flags &= ~ASYNC_CTS_FLOW;
7655 + if (cflag & CLOCAL)
7656 + info->flags &= ~ASYNC_CHECK_CD;
7657 + else {
7658 + info->flags |= ASYNC_CHECK_CD;
7659 + info->IER |= UART_IER_MSI;
7660 + }
7661 + serial_out(info, UART_IER, info->IER);
7662 +
7663 + /*
7664 + * Set up parity check flag
7665 + */
7666 +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
7667 +
7668 + info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
7669 + if (I_INPCK(info->tty))
7670 + info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
7671 + if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
7672 + info->read_status_mask |= UART_LSR_BI;
7673 +
7674 + /*
7675 + * Characters to ignore
7676 + */
7677 + info->ignore_status_mask = 0;
7678 + if (I_IGNPAR(info->tty))
7679 + info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
7680 + if (I_IGNBRK(info->tty)) {
7681 + info->ignore_status_mask |= UART_LSR_BI;
7682 + /*
7683 + * If we're ignore parity and break indicators, ignore
7684 + * overruns too. (For real raw support).
7685 + */
7686 + if (I_IGNPAR(info->tty))
7687 + info->ignore_status_mask |= UART_LSR_OE;
7688 + }
7689 + /*
7690 + * !!! ignore all characters if CREAD is not set
7691 + */
7692 + if ((cflag & CREAD) == 0)
7693 + info->ignore_status_mask |= UART_LSR_DR;
7694 + save_flags(flags); cli();
7695 + if (uart_config[info->state->type].flags & UART_STARTECH) {
7696 + serial_outp(info, UART_LCR, 0xBF);
7697 + serial_outp(info, UART_EFR,
7698 + (cflag & CRTSCTS) ? UART_EFR_CTS : 0);
7699 + }
7700 + serial_outp(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
7701 + serial_outp(info, UART_DLL, quot & 0xff); /* LS of divisor */
7702 + serial_outp(info, UART_DLM, quot >> 8); /* MS of divisor */
7703 + if (info->state->type == PORT_16750)
7704 + serial_outp(info, UART_FCR, fcr); /* set fcr */
7705 + serial_outp(info, UART_LCR, cval); /* reset DLAB */
7706 + info->LCR = cval; /* Save LCR */
7707 + if (info->state->type != PORT_16750) {
7708 + if (fcr & UART_FCR_ENABLE_FIFO) {
7709 + /* emulated UARTs (Lucent Venus 167x) need two steps */
7710 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
7711 + }
7712 + serial_outp(info, UART_FCR, fcr); /* set fcr */
7713 + }
7714 + restore_flags(flags);
7715 +}
7716 +
7717 +static void rs_put_char(struct tty_struct *tty, unsigned char ch)
7718 +{
7719 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7720 + unsigned long flags;
7721 +
7722 + if (serial_paranoia_check(info, tty->device, "rs_put_char"))
7723 + return;
7724 +
7725 + if (!tty || !info->xmit.buf)
7726 + return;
7727 +
7728 + save_flags(flags); cli();
7729 + if (CIRC_SPACE(info->xmit.head,
7730 + info->xmit.tail,
7731 + SERIAL_XMIT_SIZE) == 0) {
7732 + restore_flags(flags);
7733 + return;
7734 + }
7735 +
7736 + info->xmit.buf[info->xmit.head] = ch;
7737 + info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
7738 + restore_flags(flags);
7739 +}
7740 +
7741 +static void rs_flush_chars(struct tty_struct *tty)
7742 +{
7743 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7744 + unsigned long flags;
7745 +
7746 + if (serial_paranoia_check(info, tty->device, "rs_flush_chars"))
7747 + return;
7748 +
7749 + if (info->xmit.head == info->xmit.tail
7750 + || tty->stopped
7751 + || tty->hw_stopped
7752 + || !info->xmit.buf)
7753 + return;
7754 +
7755 + save_flags(flags); cli();
7756 + info->IER |= UART_IER_THRI;
7757 + serial_out(info, UART_IER, info->IER);
7758 + restore_flags(flags);
7759 +}
7760 +
7761 +static int rs_write(struct tty_struct * tty, int from_user,
7762 + const unsigned char *buf, int count)
7763 +{
7764 + int c, ret = 0;
7765 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7766 + unsigned long flags;
7767 +
7768 + if (serial_paranoia_check(info, tty->device, "rs_write"))
7769 + return 0;
7770 +
7771 + if (!tty || !info->xmit.buf || !tmp_buf)
7772 + return 0;
7773 +
7774 + save_flags(flags);
7775 + if (from_user) {
7776 + down(&tmp_buf_sem);
7777 + while (1) {
7778 + int c1;
7779 + c = CIRC_SPACE_TO_END(info->xmit.head,
7780 + info->xmit.tail,
7781 + SERIAL_XMIT_SIZE);
7782 + if (count < c)
7783 + c = count;
7784 + if (c <= 0)
7785 + break;
7786 +
7787 + c -= copy_from_user(tmp_buf, buf, c);
7788 + if (!c) {
7789 + if (!ret)
7790 + ret = -EFAULT;
7791 + break;
7792 + }
7793 + cli();
7794 + c1 = CIRC_SPACE_TO_END(info->xmit.head,
7795 + info->xmit.tail,
7796 + SERIAL_XMIT_SIZE);
7797 + if (c1 < c)
7798 + c = c1;
7799 + memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c);
7800 + info->xmit.head = ((info->xmit.head + c) &
7801 + (SERIAL_XMIT_SIZE-1));
7802 + restore_flags(flags);
7803 + buf += c;
7804 + count -= c;
7805 + ret += c;
7806 + }
7807 + up(&tmp_buf_sem);
7808 + } else {
7809 + cli();
7810 + while (1) {
7811 + c = CIRC_SPACE_TO_END(info->xmit.head,
7812 + info->xmit.tail,
7813 + SERIAL_XMIT_SIZE);
7814 + if (count < c)
7815 + c = count;
7816 + if (c <= 0) {
7817 + break;
7818 + }
7819 + memcpy(info->xmit.buf + info->xmit.head, buf, c);
7820 + info->xmit.head = ((info->xmit.head + c) &
7821 + (SERIAL_XMIT_SIZE-1));
7822 + buf += c;
7823 + count -= c;
7824 + ret += c;
7825 + }
7826 + restore_flags(flags);
7827 + }
7828 + if (info->xmit.head != info->xmit.tail
7829 + && !tty->stopped
7830 + && !tty->hw_stopped
7831 + && !(info->IER & UART_IER_THRI)) {
7832 + info->IER |= UART_IER_THRI;
7833 + serial_out(info, UART_IER, info->IER);
7834 + }
7835 + return ret;
7836 +}
7837 +
7838 +static int rs_write_room(struct tty_struct *tty)
7839 +{
7840 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7841 +
7842 + if (serial_paranoia_check(info, tty->device, "rs_write_room"))
7843 + return 0;
7844 + return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
7845 +}
7846 +
7847 +static int rs_chars_in_buffer(struct tty_struct *tty)
7848 +{
7849 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7850 +
7851 + if (serial_paranoia_check(info, tty->device, "rs_chars_in_buffer"))
7852 + return 0;
7853 + return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
7854 +}
7855 +
7856 +static void rs_flush_buffer(struct tty_struct *tty)
7857 +{
7858 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7859 + unsigned long flags;
7860 +
7861 + if (serial_paranoia_check(info, tty->device, "rs_flush_buffer"))
7862 + return;
7863 + save_flags(flags); cli();
7864 + info->xmit.head = info->xmit.tail = 0;
7865 + restore_flags(flags);
7866 +#ifdef SERIAL_HAVE_POLL_WAIT
7867 + wake_up_interruptible(&tty->poll_wait);
7868 +#endif
7869 + tty_wakeup(tty);
7870 +}
7871 +
7872 +/*
7873 + * This function is used to send a high-priority XON/XOFF character to
7874 + * the device
7875 + */
7876 +static void rs_send_xchar(struct tty_struct *tty, char ch)
7877 +{
7878 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7879 +
7880 + if (serial_paranoia_check(info, tty->device, "rs_send_char"))
7881 + return;
7882 +
7883 + info->x_char = ch;
7884 + if (ch) {
7885 + /* Make sure transmit interrupts are on */
7886 + info->IER |= UART_IER_THRI;
7887 + serial_out(info, UART_IER, info->IER);
7888 + }
7889 +}
7890 +
7891 +/*
7892 + * ------------------------------------------------------------
7893 + * rs_throttle()
7894 + *
7895 + * This routine is called by the upper-layer tty layer to signal that
7896 + * incoming characters should be throttled.
7897 + * ------------------------------------------------------------
7898 + */
7899 +static void rs_throttle(struct tty_struct * tty)
7900 +{
7901 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7902 + unsigned long flags;
7903 +#ifdef SERIAL_DEBUG_THROTTLE
7904 + char buf[64];
7905 +
7906 + printk("throttle %s: %d....\n", tty_name(tty, buf),
7907 + tty->ldisc.chars_in_buffer(tty));
7908 +#endif
7909 +
7910 + if (serial_paranoia_check(info, tty->device, "rs_throttle"))
7911 + return;
7912 +
7913 + if (I_IXOFF(tty))
7914 + rs_send_xchar(tty, STOP_CHAR(tty));
7915 +
7916 + if (tty->termios->c_cflag & CRTSCTS)
7917 + info->MCR &= ~UART_MCR_RTS;
7918 +
7919 + save_flags(flags); cli();
7920 + serial_out(info, UART_MCR, info->MCR);
7921 + restore_flags(flags);
7922 +}
7923 +
7924 +static void rs_unthrottle(struct tty_struct * tty)
7925 +{
7926 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7927 + unsigned long flags;
7928 +#ifdef SERIAL_DEBUG_THROTTLE
7929 + char buf[64];
7930 +
7931 + printk("unthrottle %s: %d....\n", tty_name(tty, buf),
7932 + tty->ldisc.chars_in_buffer(tty));
7933 +#endif
7934 +
7935 + if (serial_paranoia_check(info, tty->device, "rs_unthrottle"))
7936 + return;
7937 +
7938 + if (I_IXOFF(tty)) {
7939 + if (info->x_char)
7940 + info->x_char = 0;
7941 + else
7942 + rs_send_xchar(tty, START_CHAR(tty));
7943 + }
7944 + if (tty->termios->c_cflag & CRTSCTS)
7945 + info->MCR |= UART_MCR_RTS;
7946 + save_flags(flags); cli();
7947 + serial_out(info, UART_MCR, info->MCR);
7948 + restore_flags(flags);
7949 +}
7950 +
7951 +/*
7952 + * ------------------------------------------------------------
7953 + * rs_ioctl() and friends
7954 + * ------------------------------------------------------------
7955 + */
7956 +
7957 +static int get_serial_info(struct async_struct * info,
7958 + struct serial_struct * retinfo)
7959 +{
7960 + struct serial_struct tmp;
7961 + struct serial_state *state = info->state;
7962 +
7963 + if (!retinfo)
7964 + return -EFAULT;
7965 + memset(&tmp, 0, sizeof(tmp));
7966 + tmp.type = state->type;
7967 + tmp.line = state->line;
7968 + tmp.port = state->port;
7969 + if (HIGH_BITS_OFFSET)
7970 + tmp.port_high = state->port >> HIGH_BITS_OFFSET;
7971 + else
7972 + tmp.port_high = 0;
7973 + tmp.irq = state->irq;
7974 + tmp.flags = state->flags;
7975 + tmp.xmit_fifo_size = state->xmit_fifo_size;
7976 + tmp.baud_base = state->baud_base;
7977 + tmp.close_delay = state->close_delay;
7978 + tmp.closing_wait = state->closing_wait;
7979 + tmp.custom_divisor = state->custom_divisor;
7980 + tmp.hub6 = state->hub6;
7981 + tmp.io_type = state->io_type;
7982 + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
7983 + return -EFAULT;
7984 + return 0;
7985 +}
7986 +
7987 +static int set_serial_info(struct async_struct * info,
7988 + struct serial_struct * new_info)
7989 +{
7990 + struct serial_struct new_serial;
7991 + struct serial_state old_state, *state;
7992 + unsigned int i,change_irq,change_port;
7993 + int retval = 0;
7994 + unsigned long new_port;
7995 +
7996 + if (copy_from_user(&new_serial,new_info,sizeof(new_serial)))
7997 + return -EFAULT;
7998 + state = info->state;
7999 + old_state = *state;
8000 +
8001 + new_port = new_serial.port;
8002 + if (HIGH_BITS_OFFSET)
8003 + new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET;
8004 +
8005 + change_irq = new_serial.irq != state->irq;
8006 + change_port = (new_port != ((int) state->port)) ||
8007 + (new_serial.hub6 != state->hub6);
8008 +
8009 + if (!capable(CAP_SYS_ADMIN)) {
8010 + if (change_irq || change_port ||
8011 + (new_serial.baud_base != state->baud_base) ||
8012 + (new_serial.type != state->type) ||
8013 + (new_serial.close_delay != state->close_delay) ||
8014 + (new_serial.xmit_fifo_size != state->xmit_fifo_size) ||
8015 + ((new_serial.flags & ~ASYNC_USR_MASK) !=
8016 + (state->flags & ~ASYNC_USR_MASK)))
8017 + return -EPERM;
8018 + state->flags = ((state->flags & ~ASYNC_USR_MASK) |
8019 + (new_serial.flags & ASYNC_USR_MASK));
8020 + info->flags = ((info->flags & ~ASYNC_USR_MASK) |
8021 + (new_serial.flags & ASYNC_USR_MASK));
8022 + state->custom_divisor = new_serial.custom_divisor;
8023 + goto check_and_exit;
8024 + }
8025 +
8026 + new_serial.irq = irq_cannonicalize(new_serial.irq);
8027 +
8028 + if ((new_serial.irq >= NR_IRQS) || (new_serial.irq < 0) ||
8029 + (new_serial.baud_base < 9600)|| (new_serial.type < PORT_UNKNOWN) ||
8030 + (new_serial.type > PORT_MAX) || (new_serial.type == PORT_CIRRUS) ||
8031 + (new_serial.type == PORT_STARTECH)) {
8032 + return -EINVAL;
8033 + }
8034 +
8035 + if ((new_serial.type != state->type) ||
8036 + (new_serial.xmit_fifo_size <= 0))
8037 + new_serial.xmit_fifo_size =
8038 + uart_config[new_serial.type].dfl_xmit_fifo_size;
8039 +
8040 + /* Make sure address is not already in use */
8041 + if (new_serial.type) {
8042 + for (i = 0 ; i < NR_PORTS; i++)
8043 + if ((state != &rs_table[i]) &&
8044 + (rs_table[i].io_type == SERIAL_IO_PORT) &&
8045 + (rs_table[i].port == new_port) &&
8046 + rs_table[i].type)
8047 + return -EADDRINUSE;
8048 + }
8049 +
8050 + if ((change_port || change_irq) && (state->count > 1))
8051 + return -EBUSY;
8052 +
8053 + /*
8054 + * OK, past this point, all the error checking has been done.
8055 + * At this point, we start making changes.....
8056 + */
8057 +
8058 + state->baud_base = new_serial.baud_base;
8059 + state->flags = ((state->flags & ~ASYNC_FLAGS) |
8060 + (new_serial.flags & ASYNC_FLAGS));
8061 + info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) |
8062 + (info->flags & ASYNC_INTERNAL_FLAGS));
8063 + state->custom_divisor = new_serial.custom_divisor;
8064 + state->close_delay = new_serial.close_delay * HZ/100;
8065 + state->closing_wait = new_serial.closing_wait * HZ/100;
8066 +#if (LINUX_VERSION_CODE > 0x20100)
8067 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
8068 +#endif
8069 + info->xmit_fifo_size = state->xmit_fifo_size =
8070 + new_serial.xmit_fifo_size;
8071 +
8072 + if ((state->type != PORT_UNKNOWN) && state->port) {
8073 +#ifdef CONFIG_SERIAL_RSA
8074 + if (old_state.type == PORT_RSA)
8075 + release_region(state->port + UART_RSA_BASE, 16);
8076 + else
8077 +#endif
8078 + release_region(state->port,8);
8079 + }
8080 + state->type = new_serial.type;
8081 + if (change_port || change_irq) {
8082 + /*
8083 + * We need to shutdown the serial port at the old
8084 + * port/irq combination.
8085 + */
8086 + shutdown(info);
8087 + state->irq = new_serial.irq;
8088 + info->port = state->port = new_port;
8089 + info->hub6 = state->hub6 = new_serial.hub6;
8090 + if (info->hub6)
8091 + info->io_type = state->io_type = SERIAL_IO_HUB6;
8092 + else if (info->io_type == SERIAL_IO_HUB6)
8093 + info->io_type = state->io_type = SERIAL_IO_PORT;
8094 + }
8095 + if ((state->type != PORT_UNKNOWN) && state->port) {
8096 +#ifdef CONFIG_SERIAL_RSA
8097 + if (state->type == PORT_RSA)
8098 + request_region(state->port + UART_RSA_BASE,
8099 + 16, "serial_rsa(set)");
8100 + else
8101 +#endif
8102 + request_region(state->port,8,"serial(set)");
8103 + }
8104 +
8105 +
8106 +check_and_exit:
8107 + if ((!state->port && !state->iomem_base) || !state->type)
8108 + return 0;
8109 + if (info->flags & ASYNC_INITIALIZED) {
8110 + if (((old_state.flags & ASYNC_SPD_MASK) !=
8111 + (state->flags & ASYNC_SPD_MASK)) ||
8112 + (old_state.custom_divisor != state->custom_divisor)) {
8113 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
8114 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
8115 + info->tty->alt_speed = 57600;
8116 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
8117 + info->tty->alt_speed = 115200;
8118 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
8119 + info->tty->alt_speed = 230400;
8120 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
8121 + info->tty->alt_speed = 460800;
8122 +#endif
8123 + change_speed(info, 0);
8124 + }
8125 + } else
8126 + retval = startup(info);
8127 + return retval;
8128 +}
8129 +
8130 +
8131 +/*
8132 + * get_lsr_info - get line status register info
8133 + *
8134 + * Purpose: Let user call ioctl() to get info when the UART physically
8135 + * is emptied. On bus types like RS485, the transmitter must
8136 + * release the bus after transmitting. This must be done when
8137 + * the transmit shift register is empty, not be done when the
8138 + * transmit holding register is empty. This functionality
8139 + * allows an RS485 driver to be written in user space.
8140 + */
8141 +static int get_lsr_info(struct async_struct * info, unsigned int *value)
8142 +{
8143 + unsigned char status;
8144 + unsigned int result;
8145 + unsigned long flags;
8146 +
8147 + save_flags(flags); cli();
8148 + status = serial_in(info, UART_LSR);
8149 + restore_flags(flags);
8150 + result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
8151 +
8152 + /*
8153 + * If we're about to load something into the transmit
8154 + * register, we'll pretend the transmitter isn't empty to
8155 + * avoid a race condition (depending on when the transmit
8156 + * interrupt happens).
8157 + */
8158 + if (info->x_char ||
8159 + ((CIRC_CNT(info->xmit.head, info->xmit.tail,
8160 + SERIAL_XMIT_SIZE) > 0) &&
8161 + !info->tty->stopped && !info->tty->hw_stopped))
8162 + result &= ~TIOCSER_TEMT;
8163 +
8164 + if (copy_to_user(value, &result, sizeof(int)))
8165 + return -EFAULT;
8166 + return 0;
8167 +}
8168 +
8169 +
8170 +static int get_modem_info(struct async_struct * info, unsigned int *value)
8171 +{
8172 + unsigned char control, status;
8173 + unsigned int result;
8174 + unsigned long flags;
8175 +
8176 + control = info->MCR;
8177 + save_flags(flags); cli();
8178 + status = serial_in(info, UART_MSR);
8179 + restore_flags(flags);
8180 + result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
8181 + | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
8182 +#ifdef TIOCM_OUT1
8183 + | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
8184 + | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
8185 +#endif
8186 + | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0)
8187 + | ((status & UART_MSR_RI) ? TIOCM_RNG : 0)
8188 + | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0)
8189 + | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
8190 +
8191 + if (copy_to_user(value, &result, sizeof(int)))
8192 + return -EFAULT;
8193 + return 0;
8194 +}
8195 +
8196 +static int set_modem_info(struct async_struct * info, unsigned int cmd,
8197 + unsigned int *value)
8198 +{
8199 + unsigned int arg;
8200 + unsigned long flags;
8201 +
8202 + if (copy_from_user(&arg, value, sizeof(int)))
8203 + return -EFAULT;
8204 +
8205 + switch (cmd) {
8206 + case TIOCMBIS:
8207 + if (arg & TIOCM_RTS)
8208 + info->MCR |= UART_MCR_RTS;
8209 + if (arg & TIOCM_DTR)
8210 + info->MCR |= UART_MCR_DTR;
8211 +#ifdef TIOCM_OUT1
8212 + if (arg & TIOCM_OUT1)
8213 + info->MCR |= UART_MCR_OUT1;
8214 + if (arg & TIOCM_OUT2)
8215 + info->MCR |= UART_MCR_OUT2;
8216 +#endif
8217 + if (arg & TIOCM_LOOP)
8218 + info->MCR |= UART_MCR_LOOP;
8219 + break;
8220 + case TIOCMBIC:
8221 + if (arg & TIOCM_RTS)
8222 + info->MCR &= ~UART_MCR_RTS;
8223 + if (arg & TIOCM_DTR)
8224 + info->MCR &= ~UART_MCR_DTR;
8225 +#ifdef TIOCM_OUT1
8226 + if (arg & TIOCM_OUT1)
8227 + info->MCR &= ~UART_MCR_OUT1;
8228 + if (arg & TIOCM_OUT2)
8229 + info->MCR &= ~UART_MCR_OUT2;
8230 +#endif
8231 + if (arg & TIOCM_LOOP)
8232 + info->MCR &= ~UART_MCR_LOOP;
8233 + break;
8234 + case TIOCMSET:
8235 + info->MCR = ((info->MCR & ~(UART_MCR_RTS |
8236 +#ifdef TIOCM_OUT1
8237 + UART_MCR_OUT1 |
8238 + UART_MCR_OUT2 |
8239 +#endif
8240 + UART_MCR_LOOP |
8241 + UART_MCR_DTR))
8242 + | ((arg & TIOCM_RTS) ? UART_MCR_RTS : 0)
8243 +#ifdef TIOCM_OUT1
8244 + | ((arg & TIOCM_OUT1) ? UART_MCR_OUT1 : 0)
8245 + | ((arg & TIOCM_OUT2) ? UART_MCR_OUT2 : 0)
8246 +#endif
8247 + | ((arg & TIOCM_LOOP) ? UART_MCR_LOOP : 0)
8248 + | ((arg & TIOCM_DTR) ? UART_MCR_DTR : 0));
8249 + break;
8250 + default:
8251 + return -EINVAL;
8252 + }
8253 + save_flags(flags); cli();
8254 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
8255 + serial_out(info, UART_MCR, info->MCR);
8256 + restore_flags(flags);
8257 + return 0;
8258 +}
8259 +
8260 +static int do_autoconfig(struct async_struct * info)
8261 +{
8262 + int irq, retval;
8263 +
8264 + if (!capable(CAP_SYS_ADMIN))
8265 + return -EPERM;
8266 +
8267 + if (info->state->count > 1)
8268 + return -EBUSY;
8269 +
8270 + shutdown(info);
8271 +
8272 + autoconfig(info->state);
8273 + if ((info->state->flags & ASYNC_AUTO_IRQ) &&
8274 + (info->state->port != 0 || info->state->iomem_base != 0) &&
8275 + (info->state->type != PORT_UNKNOWN)) {
8276 + irq = detect_uart_irq(info->state);
8277 + if (irq > 0)
8278 + info->state->irq = irq;
8279 + }
8280 +
8281 + retval = startup(info);
8282 + if (retval)
8283 + return retval;
8284 + return 0;
8285 +}
8286 +
8287 +/*
8288 + * rs_break() --- routine which turns the break handling on or off
8289 + */
8290 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8291 +static void send_break( struct async_struct * info, int duration)
8292 +{
8293 + if (!CONFIGURED_SERIAL_PORT(info))
8294 + return;
8295 + current->state = TASK_INTERRUPTIBLE;
8296 + current->timeout = jiffies + duration;
8297 + cli();
8298 + info->LCR |= UART_LCR_SBC;
8299 + serial_out(info, UART_LCR, info->LCR);
8300 + schedule();
8301 + info->LCR &= ~UART_LCR_SBC;
8302 + serial_out(info, UART_LCR, info->LCR);
8303 + sti();
8304 +}
8305 +#else
8306 +static void rs_break(struct tty_struct *tty, int break_state)
8307 +{
8308 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8309 + unsigned long flags;
8310 +
8311 + if (serial_paranoia_check(info, tty->device, "rs_break"))
8312 + return;
8313 +
8314 + if (!CONFIGURED_SERIAL_PORT(info))
8315 + return;
8316 + save_flags(flags); cli();
8317 + if (break_state == -1)
8318 + info->LCR |= UART_LCR_SBC;
8319 + else
8320 + info->LCR &= ~UART_LCR_SBC;
8321 + serial_out(info, UART_LCR, info->LCR);
8322 + restore_flags(flags);
8323 +}
8324 +#endif
8325 +
8326 +#ifdef CONFIG_SERIAL_MULTIPORT
8327 +static int get_multiport_struct(struct async_struct * info,
8328 + struct serial_multiport_struct *retinfo)
8329 +{
8330 + struct serial_multiport_struct ret;
8331 + struct rs_multiport_struct *multi;
8332 +
8333 + multi = &rs_multiport[info->state->irq];
8334 +
8335 + ret.port_monitor = multi->port_monitor;
8336 +
8337 + ret.port1 = multi->port1;
8338 + ret.mask1 = multi->mask1;
8339 + ret.match1 = multi->match1;
8340 +
8341 + ret.port2 = multi->port2;
8342 + ret.mask2 = multi->mask2;
8343 + ret.match2 = multi->match2;
8344 +
8345 + ret.port3 = multi->port3;
8346 + ret.mask3 = multi->mask3;
8347 + ret.match3 = multi->match3;
8348 +
8349 + ret.port4 = multi->port4;
8350 + ret.mask4 = multi->mask4;
8351 + ret.match4 = multi->match4;
8352 +
8353 + ret.irq = info->state->irq;
8354 +
8355 + if (copy_to_user(retinfo,&ret,sizeof(*retinfo)))
8356 + return -EFAULT;
8357 + return 0;
8358 +}
8359 +
8360 +static int set_multiport_struct(struct async_struct * info,
8361 + struct serial_multiport_struct *in_multi)
8362 +{
8363 + struct serial_multiport_struct new_multi;
8364 + struct rs_multiport_struct *multi;
8365 + struct serial_state *state;
8366 + int was_multi, now_multi;
8367 + int retval;
8368 + void (*handler)(int, void *, struct pt_regs *);
8369 +
8370 + if (!capable(CAP_SYS_ADMIN))
8371 + return -EPERM;
8372 + state = info->state;
8373 +
8374 + if (copy_from_user(&new_multi, in_multi,
8375 + sizeof(struct serial_multiport_struct)))
8376 + return -EFAULT;
8377 +
8378 + if (new_multi.irq != state->irq || state->irq == 0 ||
8379 + !IRQ_ports[state->irq])
8380 + return -EINVAL;
8381 +
8382 + multi = &rs_multiport[state->irq];
8383 + was_multi = (multi->port1 != 0);
8384 +
8385 + multi->port_monitor = new_multi.port_monitor;
8386 +
8387 + if (multi->port1)
8388 + release_region(multi->port1,1);
8389 + multi->port1 = new_multi.port1;
8390 + multi->mask1 = new_multi.mask1;
8391 + multi->match1 = new_multi.match1;
8392 + if (multi->port1)
8393 + request_region(multi->port1,1,"serial(multiport1)");
8394 +
8395 + if (multi->port2)
8396 + release_region(multi->port2,1);
8397 + multi->port2 = new_multi.port2;
8398 + multi->mask2 = new_multi.mask2;
8399 + multi->match2 = new_multi.match2;
8400 + if (multi->port2)
8401 + request_region(multi->port2,1,"serial(multiport2)");
8402 +
8403 + if (multi->port3)
8404 + release_region(multi->port3,1);
8405 + multi->port3 = new_multi.port3;
8406 + multi->mask3 = new_multi.mask3;
8407 + multi->match3 = new_multi.match3;
8408 + if (multi->port3)
8409 + request_region(multi->port3,1,"serial(multiport3)");
8410 +
8411 + if (multi->port4)
8412 + release_region(multi->port4,1);
8413 + multi->port4 = new_multi.port4;
8414 + multi->mask4 = new_multi.mask4;
8415 + multi->match4 = new_multi.match4;
8416 + if (multi->port4)
8417 + request_region(multi->port4,1,"serial(multiport4)");
8418 +
8419 + now_multi = (multi->port1 != 0);
8420 +
8421 + if (IRQ_ports[state->irq]->next_port &&
8422 + (was_multi != now_multi)) {
8423 + free_irq(state->irq, &IRQ_ports[state->irq]);
8424 + if (now_multi)
8425 + handler = rs_interrupt_multi;
8426 + else
8427 + handler = rs_interrupt;
8428 +
8429 + retval = request_irq(state->irq, handler, SA_SHIRQ,
8430 + "serial", &IRQ_ports[state->irq]);
8431 + if (retval) {
8432 + printk("Couldn't reallocate serial interrupt "
8433 + "driver!!\n");
8434 + }
8435 + }
8436 + return 0;
8437 +}
8438 +#endif
8439 +
8440 +static int rs_ioctl(struct tty_struct *tty, struct file * file,
8441 + unsigned int cmd, unsigned long arg)
8442 +{
8443 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8444 + struct async_icount cprev, cnow; /* kernel counter temps */
8445 + struct serial_icounter_struct icount;
8446 + unsigned long flags;
8447 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8448 + int retval, tmp;
8449 +#endif
8450 +
8451 + if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
8452 + return -ENODEV;
8453 +
8454 + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
8455 + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) &&
8456 + (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
8457 + if (tty->flags & (1 << TTY_IO_ERROR))
8458 + return -EIO;
8459 + }
8460 +
8461 + switch (cmd) {
8462 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8463 + case TCSBRK: /* SVID version: non-zero arg --> no break */
8464 + retval = tty_check_change(tty);
8465 + if (retval)
8466 + return retval;
8467 + tty_wait_until_sent(tty, 0);
8468 + if (signal_pending(current))
8469 + return -EINTR;
8470 + if (!arg) {
8471 + send_break(info, HZ/4); /* 1/4 second */
8472 + if (signal_pending(current))
8473 + return -EINTR;
8474 + }
8475 + return 0;
8476 + case TCSBRKP: /* support for POSIX tcsendbreak() */
8477 + retval = tty_check_change(tty);
8478 + if (retval)
8479 + return retval;
8480 + tty_wait_until_sent(tty, 0);
8481 + if (signal_pending(current))
8482 + return -EINTR;
8483 + send_break(info, arg ? arg*(HZ/10) : HZ/4);
8484 + if (signal_pending(current))
8485 + return -EINTR;
8486 + return 0;
8487 + case TIOCGSOFTCAR:
8488 + tmp = C_CLOCAL(tty) ? 1 : 0;
8489 + if (copy_to_user((void *)arg, &tmp, sizeof(int)))
8490 + return -EFAULT;
8491 + return 0;
8492 + case TIOCSSOFTCAR:
8493 + if (copy_from_user(&tmp, (void *)arg, sizeof(int)))
8494 + return -EFAULT;
8495 +
8496 + tty->termios->c_cflag =
8497 + ((tty->termios->c_cflag & ~CLOCAL) |
8498 + (tmp ? CLOCAL : 0));
8499 + return 0;
8500 +#endif
8501 + case TIOCMGET:
8502 + return get_modem_info(info, (unsigned int *) arg);
8503 + case TIOCMBIS:
8504 + case TIOCMBIC:
8505 + case TIOCMSET:
8506 + return set_modem_info(info, cmd, (unsigned int *) arg);
8507 + case TIOCGSERIAL:
8508 + return get_serial_info(info,
8509 + (struct serial_struct *) arg);
8510 + case TIOCSSERIAL:
8511 + return set_serial_info(info,
8512 + (struct serial_struct *) arg);
8513 + case TIOCSERCONFIG:
8514 + return do_autoconfig(info);
8515 +
8516 + case TIOCSERGETLSR: /* Get line status register */
8517 + return get_lsr_info(info, (unsigned int *) arg);
8518 +
8519 + case TIOCSERGSTRUCT:
8520 + if (copy_to_user((struct async_struct *) arg,
8521 + info, sizeof(struct async_struct)))
8522 + return -EFAULT;
8523 + return 0;
8524 +
8525 +#ifdef CONFIG_SERIAL_MULTIPORT
8526 + case TIOCSERGETMULTI:
8527 + return get_multiport_struct(info,
8528 + (struct serial_multiport_struct *) arg);
8529 + case TIOCSERSETMULTI:
8530 + return set_multiport_struct(info,
8531 + (struct serial_multiport_struct *) arg);
8532 +#endif
8533 +
8534 + /*
8535 + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
8536 + * - mask passed in arg for lines of interest
8537 + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
8538 + * Caller should use TIOCGICOUNT to see which one it was
8539 + */
8540 + case TIOCMIWAIT:
8541 + save_flags(flags); cli();
8542 + /* note the counters on entry */
8543 + cprev = info->state->icount;
8544 + restore_flags(flags);
8545 + /* Force modem status interrupts on */
8546 + info->IER |= UART_IER_MSI;
8547 + serial_out(info, UART_IER, info->IER);
8548 + while (1) {
8549 + interruptible_sleep_on(&info->delta_msr_wait);
8550 + /* see if a signal did it */
8551 + if (signal_pending(current))
8552 + return -ERESTARTSYS;
8553 + save_flags(flags); cli();
8554 + cnow = info->state->icount; /* atomic copy */
8555 + restore_flags(flags);
8556 + if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
8557 + cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
8558 + return -EIO; /* no change => error */
8559 + if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
8560 + ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
8561 + ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
8562 + ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
8563 + return 0;
8564 + }
8565 + cprev = cnow;
8566 + }
8567 + /* NOTREACHED */
8568 +
8569 + /*
8570 + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
8571 + * Return: write counters to the user passed counter struct
8572 + * NB: both 1->0 and 0->1 transitions are counted except for
8573 + * RI where only 0->1 is counted.
8574 + */
8575 + case TIOCGICOUNT:
8576 + save_flags(flags); cli();
8577 + cnow = info->state->icount;
8578 + restore_flags(flags);
8579 + icount.cts = cnow.cts;
8580 + icount.dsr = cnow.dsr;
8581 + icount.rng = cnow.rng;
8582 + icount.dcd = cnow.dcd;
8583 + icount.rx = cnow.rx;
8584 + icount.tx = cnow.tx;
8585 + icount.frame = cnow.frame;
8586 + icount.overrun = cnow.overrun;
8587 + icount.parity = cnow.parity;
8588 + icount.brk = cnow.brk;
8589 + icount.buf_overrun = cnow.buf_overrun;
8590 +
8591 + if (copy_to_user((void *)arg, &icount, sizeof(icount)))
8592 + return -EFAULT;
8593 + return 0;
8594 + case TIOCSERGWILD:
8595 + case TIOCSERSWILD:
8596 + /* "setserial -W" is called in Debian boot */
8597 + printk ("TIOCSER?WILD ioctl obsolete, ignored.\n");
8598 + return 0;
8599 +
8600 + default:
8601 + return -ENOIOCTLCMD;
8602 + }
8603 + return 0;
8604 +}
8605 +
8606 +static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios)
8607 +{
8608 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8609 + unsigned long flags;
8610 + unsigned int cflag = tty->termios->c_cflag;
8611 +
8612 + if ( (cflag == old_termios->c_cflag)
8613 + && ( RELEVANT_IFLAG(tty->termios->c_iflag)
8614 + == RELEVANT_IFLAG(old_termios->c_iflag)))
8615 + return;
8616 +
8617 + change_speed(info, old_termios);
8618 +
8619 + /* Handle transition to B0 status */
8620 + if ((old_termios->c_cflag & CBAUD) &&
8621 + !(cflag & CBAUD)) {
8622 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
8623 + save_flags(flags); cli();
8624 + serial_out(info, UART_MCR, info->MCR);
8625 + restore_flags(flags);
8626 + }
8627 +
8628 + /* Handle transition away from B0 status */
8629 + if (!(old_termios->c_cflag & CBAUD) &&
8630 + (cflag & CBAUD)) {
8631 + info->MCR |= UART_MCR_DTR;
8632 + if (!(tty->termios->c_cflag & CRTSCTS) ||
8633 + !test_bit(TTY_THROTTLED, &tty->flags)) {
8634 + info->MCR |= UART_MCR_RTS;
8635 + }
8636 + save_flags(flags); cli();
8637 + serial_out(info, UART_MCR, info->MCR);
8638 + restore_flags(flags);
8639 + }
8640 +
8641 + /* Handle turning off CRTSCTS */
8642 + if ((old_termios->c_cflag & CRTSCTS) &&
8643 + !(tty->termios->c_cflag & CRTSCTS)) {
8644 + tty->hw_stopped = 0;
8645 + rs_start(tty);
8646 + }
8647 +
8648 +#if 0
8649 + /*
8650 + * No need to wake up processes in open wait, since they
8651 + * sample the CLOCAL flag once, and don't recheck it.
8652 + * XXX It's not clear whether the current behavior is correct
8653 + * or not. Hence, this may change.....
8654 + */
8655 + if (!(old_termios->c_cflag & CLOCAL) &&
8656 + (tty->termios->c_cflag & CLOCAL))
8657 + wake_up_interruptible(&info->open_wait);
8658 +#endif
8659 +}
8660 +
8661 +/*
8662 + * ------------------------------------------------------------
8663 + * rs_close()
8664 + *
8665 + * This routine is called when the serial port gets closed. First, we
8666 + * wait for the last remaining data to be sent. Then, we unlink its
8667 + * async structure from the interrupt chain if necessary, and we free
8668 + * that IRQ if nothing is left in the chain.
8669 + * ------------------------------------------------------------
8670 + */
8671 +static void rs_close(struct tty_struct *tty, struct file * filp)
8672 +{
8673 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8674 + struct serial_state *state;
8675 + unsigned long flags;
8676 +
8677 + if (!info || serial_paranoia_check(info, tty->device, "rs_close"))
8678 + return;
8679 +
8680 + state = info->state;
8681 +
8682 + save_flags(flags); cli();
8683 +
8684 + if (tty_hung_up_p(filp)) {
8685 + DBG_CNT("before DEC-hung");
8686 + MOD_DEC_USE_COUNT;
8687 + restore_flags(flags);
8688 + return;
8689 + }
8690 +
8691 +#ifdef SERIAL_DEBUG_OPEN
8692 + printk("rs_close ttys%d, count = %d\n", info->line, state->count);
8693 +#endif
8694 + if ((tty->count == 1) && (state->count != 1)) {
8695 + /*
8696 + * Uh, oh. tty->count is 1, which means that the tty
8697 + * structure will be freed. state->count should always
8698 + * be one in these conditions. If it's greater than
8699 + * one, we've got real problems, since it means the
8700 + * serial port won't be shutdown.
8701 + */
8702 + printk("rs_close: bad serial port count; tty->count is 1, "
8703 + "state->count is %d\n", state->count);
8704 + state->count = 1;
8705 + }
8706 + if (--state->count < 0) {
8707 + printk("rs_close: bad serial port count for ttys%d: %d\n",
8708 + info->line, state->count);
8709 + state->count = 0;
8710 + }
8711 + if (state->count) {
8712 + DBG_CNT("before DEC-2");
8713 + MOD_DEC_USE_COUNT;
8714 + restore_flags(flags);
8715 + return;
8716 + }
8717 + info->flags |= ASYNC_CLOSING;
8718 + restore_flags(flags);
8719 + /*
8720 + * Save the termios structure, since this port may have
8721 + * separate termios for callout and dialin.
8722 + */
8723 + if (info->flags & ASYNC_NORMAL_ACTIVE)
8724 + info->state->normal_termios = *tty->termios;
8725 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
8726 + info->state->callout_termios = *tty->termios;
8727 + /*
8728 + * Now we wait for the transmit buffer to clear; and we notify
8729 + * the line discipline to only process XON/XOFF characters.
8730 + */
8731 + tty->closing = 1;
8732 + if (state->closing_wait != ASYNC_CLOSING_WAIT_NONE)
8733 + tty_wait_until_sent(tty, state->closing_wait);
8734 + /*
8735 + * At this point we stop accepting input. To do this, we
8736 + * disable the receive line status interrupts, and tell the
8737 + * interrupt driver to stop checking the data ready bit in the
8738 + * line status register.
8739 + */
8740 + info->IER &= ~UART_IER_RLSI;
8741 + info->read_status_mask &= ~UART_LSR_DR;
8742 + if (info->flags & ASYNC_INITIALIZED) {
8743 + serial_out(info, UART_IER, info->IER);
8744 + /*
8745 + * Before we drop DTR, make sure the UART transmitter
8746 + * has completely drained; this is especially
8747 + * important if there is a transmit FIFO!
8748 + */
8749 + rs_wait_until_sent(tty, info->timeout);
8750 + }
8751 + shutdown(info);
8752 + if (tty->driver.flush_buffer)
8753 + tty->driver.flush_buffer(tty);
8754 + tty_ldisc_flush(tty);
8755 + tty->closing = 0;
8756 + info->event = 0;
8757 + info->tty = 0;
8758 + if (info->blocked_open) {
8759 + if (state->close_delay) {
8760 + set_current_state(TASK_INTERRUPTIBLE);
8761 + schedule_timeout(state->close_delay);
8762 + }
8763 + wake_up_interruptible(&info->open_wait);
8764 + }
8765 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
8766 + ASYNC_CLOSING);
8767 + wake_up_interruptible(&info->close_wait);
8768 + MOD_DEC_USE_COUNT;
8769 +}
8770 +
8771 +/*
8772 + * rs_wait_until_sent() --- wait until the transmitter is empty
8773 + */
8774 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
8775 +{
8776 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8777 + unsigned long orig_jiffies, char_time;
8778 + int lsr;
8779 +
8780 + if (serial_paranoia_check(info, tty->device, "rs_wait_until_sent"))
8781 + return;
8782 +
8783 + if (info->state->type == PORT_UNKNOWN)
8784 + return;
8785 +
8786 + if (info->xmit_fifo_size == 0)
8787 + return; /* Just in case.... */
8788 +
8789 + orig_jiffies = jiffies;
8790 + /*
8791 + * Set the check interval to be 1/5 of the estimated time to
8792 + * send a single character, and make it at least 1. The check
8793 + * interval should also be less than the timeout.
8794 + *
8795 + * Note: we have to use pretty tight timings here to satisfy
8796 + * the NIST-PCTS.
8797 + */
8798 + char_time = (info->timeout - HZ/50) / info->xmit_fifo_size;
8799 + char_time = char_time / 5;
8800 + if (char_time == 0)
8801 + char_time = 1;
8802 + if (timeout && timeout < char_time)
8803 + char_time = timeout;
8804 + /*
8805 + * If the transmitter hasn't cleared in twice the approximate
8806 + * amount of time to send the entire FIFO, it probably won't
8807 + * ever clear. This assumes the UART isn't doing flow
8808 + * control, which is currently the case. Hence, if it ever
8809 + * takes longer than info->timeout, this is probably due to a
8810 + * UART bug of some kind. So, we clamp the timeout parameter at
8811 + * 2*info->timeout.
8812 + */
8813 + if (!timeout || timeout > 2*info->timeout)
8814 + timeout = 2*info->timeout;
8815 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8816 + printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
8817 + printk("jiff=%lu...", jiffies);
8818 +#endif
8819 + while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
8820 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8821 + printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
8822 +#endif
8823 + set_current_state(TASK_INTERRUPTIBLE);
8824 + schedule_timeout(char_time);
8825 + if (signal_pending(current))
8826 + break;
8827 + if (timeout && time_after(jiffies, orig_jiffies + timeout))
8828 + break;
8829 + }
8830 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8831 + printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
8832 +#endif
8833 +}
8834 +
8835 +/*
8836 + * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
8837 + */
8838 +static void rs_hangup(struct tty_struct *tty)
8839 +{
8840 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8841 + struct serial_state *state = info->state;
8842 +
8843 + if (serial_paranoia_check(info, tty->device, "rs_hangup"))
8844 + return;
8845 +
8846 + state = info->state;
8847 +
8848 + rs_flush_buffer(tty);
8849 + if (info->flags & ASYNC_CLOSING)
8850 + return;
8851 + shutdown(info);
8852 + info->event = 0;
8853 + state->count = 0;
8854 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
8855 + info->tty = 0;
8856 + wake_up_interruptible(&info->open_wait);
8857 +}
8858 +
8859 +/*
8860 + * ------------------------------------------------------------
8861 + * rs_open() and friends
8862 + * ------------------------------------------------------------
8863 + */
8864 +static int block_til_ready(struct tty_struct *tty, struct file * filp,
8865 + struct async_struct *info)
8866 +{
8867 + DECLARE_WAITQUEUE(wait, current);
8868 + struct serial_state *state = info->state;
8869 + int retval;
8870 + int do_clocal = 0, extra_count = 0;
8871 + unsigned long flags;
8872 +
8873 + /*
8874 + * If the device is in the middle of being closed, then block
8875 + * until it's done, and then try again.
8876 + */
8877 + if (tty_hung_up_p(filp) ||
8878 + (info->flags & ASYNC_CLOSING)) {
8879 + if (info->flags & ASYNC_CLOSING)
8880 + interruptible_sleep_on(&info->close_wait);
8881 +#ifdef SERIAL_DO_RESTART
8882 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
8883 + -EAGAIN : -ERESTARTSYS);
8884 +#else
8885 + return -EAGAIN;
8886 +#endif
8887 + }
8888 +
8889 + /*
8890 + * If this is a callout device, then just make sure the normal
8891 + * device isn't being used.
8892 + */
8893 + if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
8894 + if (info->flags & ASYNC_NORMAL_ACTIVE)
8895 + return -EBUSY;
8896 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
8897 + (info->flags & ASYNC_SESSION_LOCKOUT) &&
8898 + (info->session != current->session))
8899 + return -EBUSY;
8900 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
8901 + (info->flags & ASYNC_PGRP_LOCKOUT) &&
8902 + (info->pgrp != current->pgrp))
8903 + return -EBUSY;
8904 + info->flags |= ASYNC_CALLOUT_ACTIVE;
8905 + return 0;
8906 + }
8907 +
8908 + /*
8909 + * If non-blocking mode is set, or the port is not enabled,
8910 + * then make the check up front and then exit.
8911 + */
8912 + if ((filp->f_flags & O_NONBLOCK) ||
8913 + (tty->flags & (1 << TTY_IO_ERROR))) {
8914 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
8915 + return -EBUSY;
8916 + info->flags |= ASYNC_NORMAL_ACTIVE;
8917 + return 0;
8918 + }
8919 +
8920 + if (info->flags & ASYNC_CALLOUT_ACTIVE) {
8921 + if (state->normal_termios.c_cflag & CLOCAL)
8922 + do_clocal = 1;
8923 + } else {
8924 + if (tty->termios->c_cflag & CLOCAL)
8925 + do_clocal = 1;
8926 + }
8927 +
8928 + /*
8929 + * Block waiting for the carrier detect and the line to become
8930 + * free (i.e., not in use by the callout). While we are in
8931 + * this loop, state->count is dropped by one, so that
8932 + * rs_close() knows when to free things. We restore it upon
8933 + * exit, either normal or abnormal.
8934 + */
8935 + retval = 0;
8936 + add_wait_queue(&info->open_wait, &wait);
8937 +#ifdef SERIAL_DEBUG_OPEN
8938 + printk("block_til_ready before block: ttys%d, count = %d\n",
8939 + state->line, state->count);
8940 +#endif
8941 + save_flags(flags); cli();
8942 + if (!tty_hung_up_p(filp)) {
8943 + extra_count = 1;
8944 + state->count--;
8945 + }
8946 + restore_flags(flags);
8947 + info->blocked_open++;
8948 + while (1) {
8949 + save_flags(flags); cli();
8950 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
8951 + (tty->termios->c_cflag & CBAUD))
8952 + serial_out(info, UART_MCR,
8953 + serial_inp(info, UART_MCR) |
8954 + (UART_MCR_DTR | UART_MCR_RTS));
8955 + restore_flags(flags);
8956 + set_current_state(TASK_INTERRUPTIBLE);
8957 + if (tty_hung_up_p(filp) ||
8958 + !(info->flags & ASYNC_INITIALIZED)) {
8959 +#ifdef SERIAL_DO_RESTART
8960 + if (info->flags & ASYNC_HUP_NOTIFY)
8961 + retval = -EAGAIN;
8962 + else
8963 + retval = -ERESTARTSYS;
8964 +#else
8965 + retval = -EAGAIN;
8966 +#endif
8967 + break;
8968 + }
8969 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
8970 + !(info->flags & ASYNC_CLOSING) &&
8971 + (do_clocal || (serial_in(info, UART_MSR) &
8972 + UART_MSR_DCD)))
8973 + break;
8974 + if (signal_pending(current)) {
8975 + retval = -ERESTARTSYS;
8976 + break;
8977 + }
8978 +#ifdef SERIAL_DEBUG_OPEN
8979 + printk("block_til_ready blocking: ttys%d, count = %d\n",
8980 + info->line, state->count);
8981 +#endif
8982 + schedule();
8983 + }
8984 + set_current_state(TASK_RUNNING);
8985 + remove_wait_queue(&info->open_wait, &wait);
8986 + if (extra_count)
8987 + state->count++;
8988 + info->blocked_open--;
8989 +#ifdef SERIAL_DEBUG_OPEN
8990 + printk("block_til_ready after blocking: ttys%d, count = %d\n",
8991 + info->line, state->count);
8992 +#endif
8993 + if (retval)
8994 + return retval;
8995 + info->flags |= ASYNC_NORMAL_ACTIVE;
8996 + return 0;
8997 +}
8998 +
8999 +static int get_async_struct(int line, struct async_struct **ret_info)
9000 +{
9001 + struct async_struct *info;
9002 + struct serial_state *sstate;
9003 +
9004 + sstate = rs_table + line;
9005 + sstate->count++;
9006 + if (sstate->info) {
9007 + *ret_info = sstate->info;
9008 + return 0;
9009 + }
9010 + info = kmalloc(sizeof(struct async_struct), GFP_KERNEL);
9011 + if (!info) {
9012 + sstate->count--;
9013 + return -ENOMEM;
9014 + }
9015 + memset(info, 0, sizeof(struct async_struct));
9016 + init_waitqueue_head(&info->open_wait);
9017 + init_waitqueue_head(&info->close_wait);
9018 + init_waitqueue_head(&info->delta_msr_wait);
9019 + info->magic = SERIAL_MAGIC;
9020 + info->port = sstate->port;
9021 + info->flags = sstate->flags;
9022 + info->io_type = sstate->io_type;
9023 + info->iomem_base = sstate->iomem_base;
9024 + info->iomem_reg_shift = sstate->iomem_reg_shift;
9025 + info->xmit_fifo_size = sstate->xmit_fifo_size;
9026 + info->line = line;
9027 + info->tqueue.routine = do_softint;
9028 + info->tqueue.data = info;
9029 + info->state = sstate;
9030 + if (sstate->info) {
9031 + kfree(info);
9032 + *ret_info = sstate->info;
9033 + return 0;
9034 + }
9035 + *ret_info = sstate->info = info;
9036 + return 0;
9037 +}
9038 +
9039 +/*
9040 + * This routine is called whenever a serial port is opened. It
9041 + * enables interrupts for a serial port, linking in its async structure into
9042 + * the IRQ chain. It also performs the serial-specific
9043 + * initialization for the tty structure.
9044 + *
9045 + * Note that on failure, we don't decrement the module use count - the tty
9046 + * later will call rs_close, which will decrement it for us as long as
9047 + * tty->driver_data is set non-NULL. --rmk
9048 + */
9049 +static int rs_open(struct tty_struct *tty, struct file * filp)
9050 +{
9051 + struct async_struct *info;
9052 + int retval, line;
9053 + unsigned long page;
9054 +
9055 + MOD_INC_USE_COUNT;
9056 + line = MINOR(tty->device) - tty->driver.minor_start;
9057 + if ((line < 0) || (line >= NR_PORTS)) {
9058 + MOD_DEC_USE_COUNT;
9059 + return -ENODEV;
9060 + }
9061 + retval = get_async_struct(line, &info);
9062 + if (retval) {
9063 + MOD_DEC_USE_COUNT;
9064 + return retval;
9065 + }
9066 + tty->driver_data = info;
9067 + info->tty = tty;
9068 + if (serial_paranoia_check(info, tty->device, "rs_open"))
9069 + return -ENODEV;
9070 +
9071 +#ifdef SERIAL_DEBUG_OPEN
9072 + printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line,
9073 + info->state->count);
9074 +#endif
9075 +#if (LINUX_VERSION_CODE > 0x20100)
9076 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
9077 +#endif
9078 +
9079 + /*
9080 + * This relies on lock_kernel() stuff so wants tidying for 2.5
9081 + */
9082 + if (!tmp_buf) {
9083 + page = get_zeroed_page(GFP_KERNEL);
9084 + if (!page)
9085 + return -ENOMEM;
9086 + if (tmp_buf)
9087 + free_page(page);
9088 + else
9089 + tmp_buf = (unsigned char *) page;
9090 + }
9091 +
9092 + /*
9093 + * If the port is the middle of closing, bail out now
9094 + */
9095 + if (tty_hung_up_p(filp) ||
9096 + (info->flags & ASYNC_CLOSING)) {
9097 + if (info->flags & ASYNC_CLOSING)
9098 + interruptible_sleep_on(&info->close_wait);
9099 +#ifdef SERIAL_DO_RESTART
9100 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
9101 + -EAGAIN : -ERESTARTSYS);
9102 +#else
9103 + return -EAGAIN;
9104 +#endif
9105 + }
9106 +
9107 + /*
9108 + * Start up serial port
9109 + */
9110 + retval = startup(info);
9111 + if (retval)
9112 + return retval;
9113 +
9114 + retval = block_til_ready(tty, filp, info);
9115 + if (retval) {
9116 +#ifdef SERIAL_DEBUG_OPEN
9117 + printk("rs_open returning after block_til_ready with %d\n",
9118 + retval);
9119 +#endif
9120 + return retval;
9121 + }
9122 +
9123 + if ((info->state->count == 1) &&
9124 + (info->flags & ASYNC_SPLIT_TERMIOS)) {
9125 + if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
9126 + *tty->termios = info->state->normal_termios;
9127 + else
9128 + *tty->termios = info->state->callout_termios;
9129 + change_speed(info, 0);
9130 + }
9131 +#ifdef CONFIG_SERIAL_CONSOLE
9132 + if (sercons.cflag && sercons.index == line) {
9133 + tty->termios->c_cflag = sercons.cflag;
9134 + sercons.cflag = 0;
9135 + change_speed(info, 0);
9136 + }
9137 +#endif
9138 + info->session = current->session;
9139 + info->pgrp = current->pgrp;
9140 +
9141 +#ifdef SERIAL_DEBUG_OPEN
9142 + printk("rs_open ttys%d successful...", info->line);
9143 +#endif
9144 + return 0;
9145 +}
9146 +
9147 +/*
9148 + * /proc fs routines....
9149 + */
9150 +
9151 +static inline int line_info(char *buf, struct serial_state *state)
9152 +{
9153 + struct async_struct *info = state->info, scr_info;
9154 + char stat_buf[30], control, status;
9155 + int ret;
9156 + unsigned long flags;
9157 +
9158 + /*
9159 + * Return zero characters for ports not claimed by driver.
9160 + */
9161 + if (state->type == PORT_UNKNOWN) {
9162 + return 0; /* ignore unused ports */
9163 + }
9164 +
9165 + ret = sprintf(buf, "%d: uart:%s port:%lX irq:%d",
9166 + state->line, uart_config[state->type].name,
9167 + (state->port ? state->port : (long)state->iomem_base),
9168 + state->irq);
9169 +
9170 + /*
9171 + * Figure out the current RS-232 lines
9172 + */
9173 + if (!info) {
9174 + info = &scr_info; /* This is just for serial_{in,out} */
9175 +
9176 + info->magic = SERIAL_MAGIC;
9177 + info->port = state->port;
9178 + info->flags = state->flags;
9179 + info->hub6 = state->hub6;
9180 + info->io_type = state->io_type;
9181 + info->iomem_base = state->iomem_base;
9182 + info->iomem_reg_shift = state->iomem_reg_shift;
9183 + info->quot = 0;
9184 + info->tty = 0;
9185 + }
9186 + save_flags(flags); cli();
9187 + status = serial_in(info, UART_MSR);
9188 + control = info != &scr_info ? info->MCR : serial_in(info, UART_MCR);
9189 + restore_flags(flags);
9190 +
9191 + stat_buf[0] = 0;
9192 + stat_buf[1] = 0;
9193 + if (control & UART_MCR_RTS)
9194 + strcat(stat_buf, "|RTS");
9195 + if (status & UART_MSR_CTS)
9196 + strcat(stat_buf, "|CTS");
9197 + if (control & UART_MCR_DTR)
9198 + strcat(stat_buf, "|DTR");
9199 + if (status & UART_MSR_DSR)
9200 + strcat(stat_buf, "|DSR");
9201 + if (status & UART_MSR_DCD)
9202 + strcat(stat_buf, "|CD");
9203 + if (status & UART_MSR_RI)
9204 + strcat(stat_buf, "|RI");
9205 +
9206 + if (info->quot) {
9207 + ret += sprintf(buf+ret, " baud:%d",
9208 + state->baud_base / info->quot);
9209 + }
9210 +
9211 + ret += sprintf(buf+ret, " tx:%d rx:%d",
9212 + state->icount.tx, state->icount.rx);
9213 +
9214 + if (state->icount.frame)
9215 + ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
9216 +
9217 + if (state->icount.parity)
9218 + ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
9219 +
9220 + if (state->icount.brk)
9221 + ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
9222 +
9223 + if (state->icount.overrun)
9224 + ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
9225 +
9226 + /*
9227 + * Last thing is the RS-232 status lines
9228 + */
9229 + ret += sprintf(buf+ret, " %s\n", stat_buf+1);
9230 + return ret;
9231 +}
9232 +
9233 +static int rs_read_proc(char *page, char **start, off_t off, int count,
9234 + int *eof, void *data)
9235 +{
9236 + int i, len = 0, l;
9237 + off_t begin = 0;
9238 +
9239 + len += sprintf(page, "serinfo:1.0 driver:%s%s revision:%s\n",
9240 + serial_version, LOCAL_VERSTRING, serial_revdate);
9241 + for (i = 0; i < NR_PORTS && len < 4000; i++) {
9242 + l = line_info(page + len, &rs_table[i]);
9243 + len += l;
9244 + if (len+begin > off+count)
9245 + goto done;
9246 + if (len+begin < off) {
9247 + begin += len;
9248 + len = 0;
9249 + }
9250 + }
9251 + *eof = 1;
9252 +done:
9253 + if (off >= len+begin)
9254 + return 0;
9255 + *start = page + (off-begin);
9256 + return ((count < begin+len-off) ? count : begin+len-off);
9257 +}
9258 +
9259 +/*
9260 + * ---------------------------------------------------------------------
9261 + * rs_init() and friends
9262 + *
9263 + * rs_init() is called at boot-time to initialize the serial driver.
9264 + * ---------------------------------------------------------------------
9265 + */
9266 +
9267 +/*
9268 + * This routine prints out the appropriate serial driver version
9269 + * number, and identifies which options were configured into this
9270 + * driver.
9271 + */
9272 +static char serial_options[] __initdata =
9273 +#ifdef CONFIG_HUB6
9274 + " HUB-6"
9275 +#define SERIAL_OPT
9276 +#endif
9277 +#ifdef CONFIG_SERIAL_MANY_PORTS
9278 + " MANY_PORTS"
9279 +#define SERIAL_OPT
9280 +#endif
9281 +#ifdef CONFIG_SERIAL_MULTIPORT
9282 + " MULTIPORT"
9283 +#define SERIAL_OPT
9284 +#endif
9285 +#ifdef CONFIG_SERIAL_SHARE_IRQ
9286 + " SHARE_IRQ"
9287 +#define SERIAL_OPT
9288 +#endif
9289 +#ifdef CONFIG_SERIAL_DETECT_IRQ
9290 + " DETECT_IRQ"
9291 +#define SERIAL_OPT
9292 +#endif
9293 +#ifdef ENABLE_SERIAL_PCI
9294 + " SERIAL_PCI"
9295 +#define SERIAL_OPT
9296 +#endif
9297 +#ifdef ENABLE_SERIAL_PNP
9298 + " ISAPNP"
9299 +#define SERIAL_OPT
9300 +#endif
9301 +#ifdef ENABLE_SERIAL_ACPI
9302 + " SERIAL_ACPI"
9303 +#define SERIAL_OPT
9304 +#endif
9305 +#ifdef SERIAL_OPT
9306 + " enabled\n";
9307 +#else
9308 + " no serial options enabled\n";
9309 +#endif
9310 +#undef SERIAL_OPT
9311 +
9312 +static _INLINE_ void show_serial_version(void)
9313 +{
9314 + printk(KERN_INFO "%s version %s%s (%s) with%s", serial_name,
9315 + serial_version, LOCAL_VERSTRING, serial_revdate,
9316 + serial_options);
9317 +}
9318 +
9319 +/*
9320 + * This routine detect the IRQ of a serial port by clearing OUT2 when
9321 + * no UART interrupt are requested (IER = 0) (*GPL*). This seems to work at
9322 + * each time, as long as no other device permanently request the IRQ.
9323 + * If no IRQ is detected, or multiple IRQ appear, this function returns 0.
9324 + * The variable "state" and the field "state->port" should not be null.
9325 + */
9326 +static unsigned detect_uart_irq (struct serial_state * state)
9327 +{
9328 + int irq;
9329 + unsigned long irqs;
9330 + unsigned char save_mcr, save_ier;
9331 + struct async_struct scr_info; /* serial_{in,out} because HUB6 */
9332 +
9333 +#ifdef CONFIG_SERIAL_MANY_PORTS
9334 + unsigned char save_ICP=0; /* no warning */
9335 + unsigned short ICP=0;
9336 +
9337 + if (state->flags & ASYNC_FOURPORT) {
9338 + ICP = (state->port & 0xFE0) | 0x01F;
9339 + save_ICP = inb_p(ICP);
9340 + outb_p(0x80, ICP);
9341 + (void) inb_p(ICP);
9342 + }
9343 +#endif
9344 + scr_info.magic = SERIAL_MAGIC;
9345 + scr_info.state = state;
9346 + scr_info.port = state->port;
9347 + scr_info.flags = state->flags;
9348 +#ifdef CONFIG_HUB6
9349 + scr_info.hub6 = state->hub6;
9350 +#endif
9351 + scr_info.io_type = state->io_type;
9352 + scr_info.iomem_base = state->iomem_base;
9353 + scr_info.iomem_reg_shift = state->iomem_reg_shift;
9354 +
9355 + /* forget possible initially masked and pending IRQ */
9356 + probe_irq_off(probe_irq_on());
9357 + save_mcr = serial_inp(&scr_info, UART_MCR);
9358 + save_ier = serial_inp(&scr_info, UART_IER);
9359 + serial_outp(&scr_info, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
9360 +
9361 + irqs = probe_irq_on();
9362 + serial_outp(&scr_info, UART_MCR, 0);
9363 + udelay (10);
9364 + if (state->flags & ASYNC_FOURPORT) {
9365 + serial_outp(&scr_info, UART_MCR,
9366 + UART_MCR_DTR | UART_MCR_RTS);
9367 + } else {
9368 + serial_outp(&scr_info, UART_MCR,
9369 + UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
9370 + }
9371 + serial_outp(&scr_info, UART_IER, 0x0f); /* enable all intrs */
9372 + (void)serial_inp(&scr_info, UART_LSR);
9373 + (void)serial_inp(&scr_info, UART_RX);
9374 + (void)serial_inp(&scr_info, UART_IIR);
9375 + (void)serial_inp(&scr_info, UART_MSR);
9376 + serial_outp(&scr_info, UART_TX, 0xFF);
9377 + udelay (20);
9378 + irq = probe_irq_off(irqs);
9379 +
9380 + serial_outp(&scr_info, UART_MCR, save_mcr);
9381 + serial_outp(&scr_info, UART_IER, save_ier);
9382 +#ifdef CONFIG_SERIAL_MANY_PORTS
9383 + if (state->flags & ASYNC_FOURPORT)
9384 + outb_p(save_ICP, ICP);
9385 +#endif
9386 + return (irq > 0)? irq : 0;
9387 +}
9388 +
9389 +/*
9390 + * This is a quickie test to see how big the FIFO is.
9391 + * It doesn't work at all the time, more's the pity.
9392 + */
9393 +static int size_fifo(struct async_struct *info)
9394 +{
9395 + unsigned char old_fcr, old_mcr, old_dll, old_dlm;
9396 + int count;
9397 +
9398 + old_fcr = serial_inp(info, UART_FCR);
9399 + old_mcr = serial_inp(info, UART_MCR);
9400 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO |
9401 + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
9402 + serial_outp(info, UART_MCR, UART_MCR_LOOP);
9403 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9404 + old_dll = serial_inp(info, UART_DLL);
9405 + old_dlm = serial_inp(info, UART_DLM);
9406 + serial_outp(info, UART_DLL, 0x01);
9407 + serial_outp(info, UART_DLM, 0x00);
9408 + serial_outp(info, UART_LCR, 0x03);
9409 + for (count = 0; count < 256; count++)
9410 + serial_outp(info, UART_TX, count);
9411 + mdelay(20);
9412 + for (count = 0; (serial_inp(info, UART_LSR) & UART_LSR_DR) &&
9413 + (count < 256); count++)
9414 + serial_inp(info, UART_RX);
9415 + serial_outp(info, UART_FCR, old_fcr);
9416 + serial_outp(info, UART_MCR, old_mcr);
9417 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9418 + serial_outp(info, UART_DLL, old_dll);
9419 + serial_outp(info, UART_DLM, old_dlm);
9420 +
9421 + return count;
9422 +}
9423 +
9424 +/*
9425 + * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
9426 + * When this function is called we know it is at least a StarTech
9427 + * 16650 V2, but it might be one of several StarTech UARTs, or one of
9428 + * its clones. (We treat the broken original StarTech 16650 V1 as a
9429 + * 16550, and why not? Startech doesn't seem to even acknowledge its
9430 + * existence.)
9431 + *
9432 + * What evil have men's minds wrought...
9433 + */
9434 +static void autoconfig_startech_uarts(struct async_struct *info,
9435 + struct serial_state *state,
9436 + unsigned long flags)
9437 +{
9438 + unsigned char scratch, scratch2, scratch3, scratch4;
9439 +
9440 + /*
9441 + * First we check to see if it's an Oxford Semiconductor UART.
9442 + *
9443 + * If we have to do this here because some non-National
9444 + * Semiconductor clone chips lock up if you try writing to the
9445 + * LSR register (which serial_icr_read does)
9446 + */
9447 + if (state->type == PORT_16550A) {
9448 + /*
9449 + * EFR [4] must be set else this test fails
9450 + *
9451 + * This shouldn't be necessary, but Mike Hudson
9452 + * (Exoray@isys.ca) claims that it's needed for 952
9453 + * dual UART's (which are not recommended for new designs).
9454 + */
9455 + info->ACR = 0;
9456 + serial_out(info, UART_LCR, 0xBF);
9457 + serial_out(info, UART_EFR, 0x10);
9458 + serial_out(info, UART_LCR, 0x00);
9459 + /* Check for Oxford Semiconductor 16C950 */
9460 + scratch = serial_icr_read(info, UART_ID1);
9461 + scratch2 = serial_icr_read(info, UART_ID2);
9462 + scratch3 = serial_icr_read(info, UART_ID3);
9463 +
9464 + if (scratch == 0x16 && scratch2 == 0xC9 &&
9465 + (scratch3 == 0x50 || scratch3 == 0x52 ||
9466 + scratch3 == 0x54)) {
9467 + state->type = PORT_16C950;
9468 + state->revision = serial_icr_read(info, UART_REV) |
9469 + (scratch3 << 8);
9470 + return;
9471 + }
9472 + }
9473 +
9474 + /*
9475 + * We check for a XR16C850 by setting DLL and DLM to 0, and
9476 + * then reading back DLL and DLM. If DLM reads back 0x10,
9477 + * then the UART is a XR16C850 and the DLL contains the chip
9478 + * revision. If DLM reads back 0x14, then the UART is a
9479 + * XR16C854.
9480 + *
9481 + */
9482 +
9483 + /* Save the DLL and DLM */
9484 +
9485 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9486 + scratch3 = serial_inp(info, UART_DLL);
9487 + scratch4 = serial_inp(info, UART_DLM);
9488 +
9489 + serial_outp(info, UART_DLL, 0);
9490 + serial_outp(info, UART_DLM, 0);
9491 + scratch2 = serial_inp(info, UART_DLL);
9492 + scratch = serial_inp(info, UART_DLM);
9493 + serial_outp(info, UART_LCR, 0);
9494 +
9495 + if (scratch == 0x10 || scratch == 0x14) {
9496 + if (scratch == 0x10)
9497 + state->revision = scratch2;
9498 + state->type = PORT_16850;
9499 + return;
9500 + }
9501 +
9502 + /* Restore the DLL and DLM */
9503 +
9504 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9505 + serial_outp(info, UART_DLL, scratch3);
9506 + serial_outp(info, UART_DLM, scratch4);
9507 + serial_outp(info, UART_LCR, 0);
9508 + /*
9509 + * We distinguish between the '654 and the '650 by counting
9510 + * how many bytes are in the FIFO. I'm using this for now,
9511 + * since that's the technique that was sent to me in the
9512 + * serial driver update, but I'm not convinced this works.
9513 + * I've had problems doing this in the past. -TYT
9514 + */
9515 + if (size_fifo(info) == 64)
9516 + state->type = PORT_16654;
9517 + else
9518 + state->type = PORT_16650V2;
9519 +}
9520 +
9521 +/*
9522 + * This routine is called by rs_init() to initialize a specific serial
9523 + * port. It determines what type of UART chip this serial port is
9524 + * using: 8250, 16450, 16550, 16550A. The important question is
9525 + * whether or not this UART is a 16550A or not, since this will
9526 + * determine whether or not we can use its FIFO features or not.
9527 + */
9528 +static void autoconfig(struct serial_state * state)
9529 +{
9530 + unsigned char status1, status2, scratch, scratch2, scratch3;
9531 + unsigned char save_lcr, save_mcr;
9532 + struct async_struct *info, scr_info;
9533 + unsigned long flags;
9534 +
9535 + state->type = PORT_UNKNOWN;
9536 +
9537 +#ifdef SERIAL_DEBUG_AUTOCONF
9538 + printk("Testing ttyS%d (0x%04lx, 0x%04x)...\n", state->line,
9539 + state->port, (unsigned) state->iomem_base);
9540 +#endif
9541 +
9542 + if (!CONFIGURED_SERIAL_PORT(state))
9543 + return;
9544 +
9545 + info = &scr_info; /* This is just for serial_{in,out} */
9546 +
9547 + info->magic = SERIAL_MAGIC;
9548 + info->state = state;
9549 + info->port = state->port;
9550 + info->flags = state->flags;
9551 +#ifdef CONFIG_HUB6
9552 + info->hub6 = state->hub6;
9553 +#endif
9554 + info->io_type = state->io_type;
9555 + info->iomem_base = state->iomem_base;
9556 + info->iomem_reg_shift = state->iomem_reg_shift;
9557 +
9558 + save_flags(flags); cli();
9559 +
9560 + if (!(state->flags & ASYNC_BUGGY_UART) &&
9561 + !state->iomem_base) {
9562 + /*
9563 + * Do a simple existence test first; if we fail this,
9564 + * there's no point trying anything else.
9565 + *
9566 + * 0x80 is used as a nonsense port to prevent against
9567 + * false positives due to ISA bus float. The
9568 + * assumption is that 0x80 is a non-existent port;
9569 + * which should be safe since include/asm/io.h also
9570 + * makes this assumption.
9571 + */
9572 + scratch = serial_inp(info, UART_IER);
9573 + serial_outp(info, UART_IER, 0);
9574 +#ifdef __i386__
9575 + outb(0xff, 0x080);
9576 +#endif
9577 + scratch2 = serial_inp(info, UART_IER);
9578 + serial_outp(info, UART_IER, 0x0F);
9579 +#ifdef __i386__
9580 + outb(0, 0x080);
9581 +#endif
9582 + scratch3 = serial_inp(info, UART_IER);
9583 + serial_outp(info, UART_IER, scratch);
9584 + if (scratch2 || scratch3 != 0x0F) {
9585 +#ifdef SERIAL_DEBUG_AUTOCONF
9586 + printk("serial: ttyS%d: simple autoconfig failed "
9587 + "(%02x, %02x)\n", state->line,
9588 + scratch2, scratch3);
9589 +#endif
9590 + restore_flags(flags);
9591 + return; /* We failed; there's nothing here */
9592 + }
9593 + }
9594 +
9595 + save_mcr = serial_in(info, UART_MCR);
9596 + save_lcr = serial_in(info, UART_LCR);
9597 +
9598 + /*
9599 + * Check to see if a UART is really there. Certain broken
9600 + * internal modems based on the Rockwell chipset fail this
9601 + * test, because they apparently don't implement the loopback
9602 + * test mode. So this test is skipped on the COM 1 through
9603 + * COM 4 ports. This *should* be safe, since no board
9604 + * manufacturer would be stupid enough to design a board
9605 + * that conflicts with COM 1-4 --- we hope!
9606 + */
9607 + if (!(state->flags & ASYNC_SKIP_TEST)) {
9608 + serial_outp(info, UART_MCR, UART_MCR_LOOP | 0x0A);
9609 + status1 = serial_inp(info, UART_MSR) & 0xF0;
9610 + serial_outp(info, UART_MCR, save_mcr);
9611 + if (status1 != 0x90) {
9612 +#ifdef SERIAL_DEBUG_AUTOCONF
9613 + printk("serial: ttyS%d: no UART loopback failed\n",
9614 + state->line);
9615 +#endif
9616 + restore_flags(flags);
9617 + return;
9618 + }
9619 + }
9620 + serial_outp(info, UART_LCR, 0xBF); /* set up for StarTech test */
9621 + serial_outp(info, UART_EFR, 0); /* EFR is the same as FCR */
9622 + serial_outp(info, UART_LCR, 0);
9623 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9624 + scratch = serial_in(info, UART_IIR) >> 6;
9625 + switch (scratch) {
9626 + case 0:
9627 + state->type = PORT_16450;
9628 + break;
9629 + case 1:
9630 + state->type = PORT_UNKNOWN;
9631 + break;
9632 + case 2:
9633 + state->type = PORT_16550;
9634 + break;
9635 + case 3:
9636 + state->type = PORT_16550A;
9637 + break;
9638 + }
9639 + if (state->type == PORT_16550A) {
9640 + /* Check for Startech UART's */
9641 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
9642 + if (serial_in(info, UART_EFR) == 0) {
9643 + serial_outp(info, UART_EFR, 0xA8);
9644 + if (serial_in(info, UART_EFR) == 0) {
9645 + /* We are a NS16552D/Motorola
9646 + * 8xxx DUART, stop. */
9647 + goto out;
9648 + }
9649 + state->type = PORT_16650;
9650 + serial_outp(info, UART_EFR, 0);
9651 + } else {
9652 + serial_outp(info, UART_LCR, 0xBF);
9653 + if (serial_in(info, UART_EFR) == 0)
9654 + autoconfig_startech_uarts(info, state, flags);
9655 + }
9656 + }
9657 + if (state->type == PORT_16550A) {
9658 + /* Check for TI 16750 */
9659 + serial_outp(info, UART_LCR, save_lcr | UART_LCR_DLAB);
9660 + serial_outp(info, UART_FCR,
9661 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
9662 + scratch = serial_in(info, UART_IIR) >> 5;
9663 + if (scratch == 7) {
9664 + /*
9665 + * If this is a 16750, and not a cheap UART
9666 + * clone, then it should only go into 64 byte
9667 + * mode if the UART_FCR7_64BYTE bit was set
9668 + * while UART_LCR_DLAB was latched.
9669 + */
9670 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9671 + serial_outp(info, UART_LCR, 0);
9672 + serial_outp(info, UART_FCR,
9673 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
9674 + scratch = serial_in(info, UART_IIR) >> 5;
9675 + if (scratch == 6)
9676 + state->type = PORT_16750;
9677 + }
9678 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
9679 + }
9680 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
9681 + if (state->type == PORT_16550A) {
9682 + int i;
9683 +
9684 + for (i = 0 ; i < PORT_RSA_MAX ; ++i) {
9685 + if (!probe_rsa[i] && !force_rsa[i])
9686 + break;
9687 + if (((probe_rsa[i] != state->port) ||
9688 + check_region(state->port + UART_RSA_BASE, 16)) &&
9689 + (force_rsa[i] != state->port))
9690 + continue;
9691 + if (!enable_rsa(info))
9692 + continue;
9693 + state->type = PORT_RSA;
9694 + state->baud_base = SERIAL_RSA_BAUD_BASE;
9695 + break;
9696 + }
9697 + }
9698 +#endif
9699 +out:
9700 + serial_outp(info, UART_LCR, save_lcr);
9701 + if (state->type == PORT_16450) {
9702 + scratch = serial_in(info, UART_SCR);
9703 + serial_outp(info, UART_SCR, 0xa5);
9704 + status1 = serial_in(info, UART_SCR);
9705 + serial_outp(info, UART_SCR, 0x5a);
9706 + status2 = serial_in(info, UART_SCR);
9707 + serial_outp(info, UART_SCR, scratch);
9708 +
9709 + if ((status1 != 0xa5) || (status2 != 0x5a))
9710 + state->type = PORT_8250;
9711 + }
9712 + state->xmit_fifo_size = uart_config[state->type].dfl_xmit_fifo_size;
9713 +
9714 + if (state->type == PORT_UNKNOWN) {
9715 + restore_flags(flags);
9716 + return;
9717 + }
9718 +
9719 + if (info->port) {
9720 +#ifdef CONFIG_SERIAL_RSA
9721 + if (state->type == PORT_RSA)
9722 + request_region(info->port + UART_RSA_BASE, 16,
9723 + "serial_rsa(auto)");
9724 + else
9725 +#endif
9726 + request_region(info->port,8,"serial(auto)");
9727 + }
9728 +
9729 + /*
9730 + * Reset the UART.
9731 + */
9732 +#ifdef CONFIG_SERIAL_RSA
9733 + if (state->type == PORT_RSA)
9734 + serial_outp(info, UART_RSA_FRR, 0);
9735 +#endif
9736 + serial_outp(info, UART_MCR, save_mcr);
9737 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
9738 + UART_FCR_CLEAR_RCVR |
9739 + UART_FCR_CLEAR_XMIT));
9740 + serial_outp(info, UART_FCR, 0);
9741 + (void)serial_in(info, UART_RX);
9742 + serial_outp(info, UART_IER, 0);
9743 +
9744 + restore_flags(flags);
9745 +}
9746 +
9747 +int register_serial(struct serial_struct *req);
9748 +void unregister_serial(int line);
9749 +
9750 +#if (LINUX_VERSION_CODE > 0x20100)
9751 +EXPORT_SYMBOL(register_serial);
9752 +EXPORT_SYMBOL(unregister_serial);
9753 +#else
9754 +static struct symbol_table serial_syms = {
9755 +#include <linux/symtab_begin.h>
9756 + X(register_serial),
9757 + X(unregister_serial),
9758 +#include <linux/symtab_end.h>
9759 +};
9760 +#endif
9761 +
9762 +
9763 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
9764 +
9765 +static void __devinit printk_pnp_dev_id(unsigned short vendor,
9766 + unsigned short device)
9767 +{
9768 + printk("%c%c%c%x%x%x%x",
9769 + 'A' + ((vendor >> 2) & 0x3f) - 1,
9770 + 'A' + (((vendor & 3) << 3) | ((vendor >> 13) & 7)) - 1,
9771 + 'A' + ((vendor >> 8) & 0x1f) - 1,
9772 + (device >> 4) & 0x0f,
9773 + device & 0x0f,
9774 + (device >> 12) & 0x0f,
9775 + (device >> 8) & 0x0f);
9776 +}
9777 +
9778 +static _INLINE_ int get_pci_port(struct pci_dev *dev,
9779 + struct pci_board *board,
9780 + struct serial_struct *req,
9781 + int idx)
9782 +{
9783 + unsigned long port;
9784 + int base_idx;
9785 + int max_port;
9786 + int offset;
9787 +
9788 + base_idx = SPCI_FL_GET_BASE(board->flags);
9789 + if (board->flags & SPCI_FL_BASE_TABLE)
9790 + base_idx += idx;
9791 +
9792 + if (board->flags & SPCI_FL_REGION_SZ_CAP) {
9793 + max_port = pci_resource_len(dev, base_idx) / 8;
9794 + if (idx >= max_port)
9795 + return 1;
9796 + }
9797 +
9798 + offset = board->first_uart_offset;
9799 +
9800 + /* Timedia/SUNIX uses a mixture of BARs and offsets */
9801 + /* Ugh, this is ugly as all hell --- TYT */
9802 + if(dev->vendor == PCI_VENDOR_ID_TIMEDIA ) /* 0x1409 */
9803 + switch(idx) {
9804 + case 0: base_idx=0;
9805 + break;
9806 + case 1: base_idx=0; offset=8;
9807 + break;
9808 + case 2: base_idx=1;
9809 + break;
9810 + case 3: base_idx=1; offset=8;
9811 + break;
9812 + case 4: /* BAR 2*/
9813 + case 5: /* BAR 3 */
9814 + case 6: /* BAR 4*/
9815 + case 7: base_idx=idx-2; /* BAR 5*/
9816 + }
9817 +
9818 + /* Some Titan cards are also a little weird */
9819 + if (dev->vendor == PCI_VENDOR_ID_TITAN &&
9820 + (dev->device == PCI_DEVICE_ID_TITAN_400L ||
9821 + dev->device == PCI_DEVICE_ID_TITAN_800L)) {
9822 + switch (idx) {
9823 + case 0: base_idx = 1;
9824 + break;
9825 + case 1: base_idx = 2;
9826 + break;
9827 + default:
9828 + base_idx = 4;
9829 + offset = 8 * (idx - 2);
9830 + }
9831 +
9832 + }
9833 +
9834 + /* HP's Diva chip puts the 4th/5th serial port further out, and
9835 + * some serial ports are supposed to be hidden on certain models.
9836 + */
9837 + if (dev->vendor == PCI_VENDOR_ID_HP &&
9838 + dev->device == PCI_DEVICE_ID_HP_SAS) {
9839 + switch (dev->subsystem_device) {
9840 + case 0x104B: /* Maestro */
9841 + if (idx == 3) idx++;
9842 + break;
9843 + case 0x1282: /* Everest / Longs Peak */
9844 + if (idx > 0) idx++;
9845 + if (idx > 2) idx++;
9846 + break;
9847 + }
9848 + if (idx > 2) {
9849 + offset = 0x18;
9850 + }
9851 + }
9852 +
9853 + port = pci_resource_start(dev, base_idx) + offset;
9854 +
9855 + if ((board->flags & SPCI_FL_BASE_TABLE) == 0)
9856 + port += idx * (board->uart_offset ? board->uart_offset : 8);
9857 +
9858 + if (IS_PCI_REGION_IOPORT(dev, base_idx)) {
9859 + req->port = port;
9860 + if (HIGH_BITS_OFFSET)
9861 + req->port_high = port >> HIGH_BITS_OFFSET;
9862 + else
9863 + req->port_high = 0;
9864 + return 0;
9865 + }
9866 + req->io_type = SERIAL_IO_MEM;
9867 + req->iomem_base = ioremap(port, board->uart_offset);
9868 + req->iomem_reg_shift = board->reg_shift;
9869 + req->port = 0;
9870 + return 0;
9871 +}
9872 +
9873 +static _INLINE_ int get_pci_irq(struct pci_dev *dev,
9874 + struct pci_board *board,
9875 + int idx)
9876 +{
9877 + int base_idx;
9878 +
9879 + if ((board->flags & SPCI_FL_IRQRESOURCE) == 0)
9880 + return dev->irq;
9881 +
9882 + base_idx = SPCI_FL_GET_IRQBASE(board->flags);
9883 + if (board->flags & SPCI_FL_IRQ_TABLE)
9884 + base_idx += idx;
9885 +
9886 + return PCI_IRQ_RESOURCE(dev, base_idx);
9887 +}
9888 +
9889 +/*
9890 + * Common enabler code shared by both PCI and ISAPNP probes
9891 + */
9892 +static void __devinit start_pci_pnp_board(struct pci_dev *dev,
9893 + struct pci_board *board)
9894 +{
9895 + int k, line;
9896 + struct serial_struct serial_req;
9897 + int base_baud;
9898 +
9899 + if (PREPARE_FUNC(dev) && (PREPARE_FUNC(dev))(dev) < 0) {
9900 + printk("serial: PNP device '");
9901 + printk_pnp_dev_id(dev->vendor, dev->device);
9902 + printk("' prepare failed\n");
9903 + return;
9904 + }
9905 +
9906 + if (ACTIVATE_FUNC(dev) && (ACTIVATE_FUNC(dev))(dev) < 0) {
9907 + printk("serial: PNP device '");
9908 + printk_pnp_dev_id(dev->vendor, dev->device);
9909 + printk("' activate failed\n");
9910 + return;
9911 + }
9912 +
9913 + /*
9914 + * Run the initialization function, if any
9915 + */
9916 + if (board->init_fn && ((board->init_fn)(dev, board, 1) != 0))
9917 + return;
9918 +
9919 + /*
9920 + * Register the serial board in the array if we need to
9921 + * shutdown the board on a module unload or card removal
9922 + */
9923 + if (DEACTIVATE_FUNC(dev) || board->init_fn) {
9924 + for (k=0; k < NR_PCI_BOARDS; k++)
9925 + if (serial_pci_board[k].dev == 0)
9926 + break;
9927 + if (k >= NR_PCI_BOARDS)
9928 + return;
9929 + serial_pci_board[k].board = *board;
9930 + serial_pci_board[k].dev = dev;
9931 + }
9932 +
9933 + base_baud = board->base_baud;
9934 + if (!base_baud)
9935 + base_baud = BASE_BAUD;
9936 + memset(&serial_req, 0, sizeof(serial_req));
9937 +
9938 + for (k=0; k < board->num_ports; k++) {
9939 + serial_req.irq = get_pci_irq(dev, board, k);
9940 + if (get_pci_port(dev, board, &serial_req, k))
9941 + break;
9942 + serial_req.flags = ASYNC_SKIP_TEST | ASYNC_AUTOPROBE;
9943 +#ifdef SERIAL_DEBUG_PCI
9944 + printk("Setup PCI/PNP port: port %x, irq %d, type %d\n",
9945 + serial_req.port, serial_req.irq, serial_req.io_type);
9946 +#endif
9947 + line = register_serial(&serial_req);
9948 + if (line < 0)
9949 + break;
9950 + rs_table[line].baud_base = base_baud;
9951 + rs_table[line].dev = dev;
9952 + }
9953 +}
9954 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
9955 +
9956 +#ifdef ENABLE_SERIAL_PCI
9957 +/*
9958 + * Some PCI serial cards using the PLX 9050 PCI interface chip require
9959 + * that the card interrupt be explicitly enabled or disabled. This
9960 + * seems to be mainly needed on card using the PLX which also use I/O
9961 + * mapped memory.
9962 + */
9963 +static int __devinit
9964 +pci_plx9050_fn(struct pci_dev *dev, struct pci_board *board, int enable)
9965 +{
9966 + u8 data, *p, irq_config;
9967 + int pci_config;
9968 +
9969 + irq_config = 0x41;
9970 + pci_config = PCI_COMMAND_MEMORY;
9971 + if (dev->vendor == PCI_VENDOR_ID_PANACOM)
9972 + irq_config = 0x43;
9973 + if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
9974 + (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
9975 + /*
9976 + * As the megawolf cards have the int pins active
9977 + * high, and have 2 UART chips, both ints must be
9978 + * enabled on the 9050. Also, the UARTS are set in
9979 + * 16450 mode by default, so we have to enable the
9980 + * 16C950 'enhanced' mode so that we can use the deep
9981 + * FIFOs
9982 + */
9983 + irq_config = 0x5b;
9984 + pci_config = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
9985 + }
9986 +
9987 + pci_read_config_byte(dev, PCI_COMMAND, &data);
9988 +
9989 + if (enable)
9990 + pci_write_config_byte(dev, PCI_COMMAND,
9991 + data | pci_config);
9992 +
9993 + /* enable/disable interrupts */
9994 + p = ioremap(pci_resource_start(dev, 0), 0x80);
9995 + writel(enable ? irq_config : 0x00, (unsigned long)p + 0x4c);
9996 + iounmap(p);
9997 +
9998 + if (!enable)
9999 + pci_write_config_byte(dev, PCI_COMMAND,
10000 + data & ~pci_config);
10001 + return 0;
10002 +}
10003 +
10004 +
10005 +/*
10006 + * SIIG serial cards have an PCI interface chip which also controls
10007 + * the UART clocking frequency. Each UART can be clocked independently
10008 + * (except cards equiped with 4 UARTs) and initial clocking settings
10009 + * are stored in the EEPROM chip. It can cause problems because this
10010 + * version of serial driver doesn't support differently clocked UART's
10011 + * on single PCI card. To prevent this, initialization functions set
10012 + * high frequency clocking for all UART's on given card. It is safe (I
10013 + * hope) because it doesn't touch EEPROM settings to prevent conflicts
10014 + * with other OSes (like M$ DOS).
10015 + *
10016 + * SIIG support added by Andrey Panin <pazke@mail.tp.ru>, 10/1999
10017 + *
10018 + * There is two family of SIIG serial cards with different PCI
10019 + * interface chip and different configuration methods:
10020 + * - 10x cards have control registers in IO and/or memory space;
10021 + * - 20x cards have control registers in standard PCI configuration space.
10022 + *
10023 + * SIIG initialization functions exported for use by parport_serial.c module.
10024 + */
10025 +
10026 +#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
10027 +#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
10028 +
10029 +int __devinit
10030 +pci_siig10x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10031 +{
10032 + u16 data, *p;
10033 +
10034 + if (!enable) return 0;
10035 +
10036 + p = ioremap(pci_resource_start(dev, 0), 0x80);
10037 +
10038 + switch (dev->device & 0xfff8) {
10039 + case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
10040 + data = 0xffdf;
10041 + break;
10042 + case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
10043 + data = 0xf7ff;
10044 + break;
10045 + default: /* 1S1P, 4S */
10046 + data = 0xfffb;
10047 + break;
10048 + }
10049 +
10050 + writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
10051 + iounmap(p);
10052 + return 0;
10053 +}
10054 +EXPORT_SYMBOL(pci_siig10x_fn);
10055 +
10056 +#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
10057 +#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
10058 +
10059 +int __devinit
10060 +pci_siig20x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10061 +{
10062 + u8 data;
10063 +
10064 + if (!enable) return 0;
10065 +
10066 + /* Change clock frequency for the first UART. */
10067 + pci_read_config_byte(dev, 0x6f, &data);
10068 + pci_write_config_byte(dev, 0x6f, data & 0xef);
10069 +
10070 + /* If this card has 2 UART, we have to do the same with second UART. */
10071 + if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
10072 + ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
10073 + pci_read_config_byte(dev, 0x73, &data);
10074 + pci_write_config_byte(dev, 0x73, data & 0xef);
10075 + }
10076 + return 0;
10077 +}
10078 +EXPORT_SYMBOL(pci_siig20x_fn);
10079 +
10080 +/* Added for EKF Intel i960 serial boards */
10081 +static int __devinit
10082 +pci_inteli960ni_fn(struct pci_dev *dev,
10083 + struct pci_board *board,
10084 + int enable)
10085 +{
10086 + unsigned long oldval;
10087 +
10088 + if (!(pci_get_subdevice(dev) & 0x1000))
10089 + return(-1);
10090 +
10091 + if (!enable) /* is there something to deinit? */
10092 + return(0);
10093 +
10094 +#ifdef SERIAL_DEBUG_PCI
10095 + printk(KERN_DEBUG " Subsystem ID %lx (intel 960)\n",
10096 + (unsigned long) board->subdevice);
10097 +#endif
10098 + /* is firmware started? */
10099 + pci_read_config_dword(dev, 0x44, (void*) &oldval);
10100 + if (oldval == 0x00001000L) { /* RESET value */
10101 + printk(KERN_DEBUG "Local i960 firmware missing");
10102 + return(-1);
10103 + }
10104 + return(0);
10105 +}
10106 +
10107 +/*
10108 + * Timedia has an explosion of boards, and to avoid the PCI table from
10109 + * growing *huge*, we use this function to collapse some 70 entries
10110 + * in the PCI table into one, for sanity's and compactness's sake.
10111 + */
10112 +static unsigned short timedia_single_port[] = {
10113 + 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 };
10114 +static unsigned short timedia_dual_port[] = {
10115 + 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
10116 + 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
10117 + 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
10118 + 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
10119 + 0xD079, 0 };
10120 +static unsigned short timedia_quad_port[] = {
10121 + 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
10122 + 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
10123 + 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
10124 + 0xB157, 0 };
10125 +static unsigned short timedia_eight_port[] = {
10126 + 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
10127 + 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 };
10128 +static struct timedia_struct {
10129 + int num;
10130 + unsigned short *ids;
10131 +} timedia_data[] = {
10132 + { 1, timedia_single_port },
10133 + { 2, timedia_dual_port },
10134 + { 4, timedia_quad_port },
10135 + { 8, timedia_eight_port },
10136 + { 0, 0 }
10137 +};
10138 +
10139 +static int __devinit
10140 +pci_timedia_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10141 +{
10142 + int i, j;
10143 + unsigned short *ids;
10144 +
10145 + if (!enable)
10146 + return 0;
10147 +
10148 + for (i=0; timedia_data[i].num; i++) {
10149 + ids = timedia_data[i].ids;
10150 + for (j=0; ids[j]; j++) {
10151 + if (pci_get_subdevice(dev) == ids[j]) {
10152 + board->num_ports = timedia_data[i].num;
10153 + return 0;
10154 + }
10155 + }
10156 + }
10157 + return 0;
10158 +}
10159 +
10160 +/*
10161 + * HP's Remote Management Console. The Diva chip came in several
10162 + * different versions. N-class, L2000 and A500 have two Diva chips, each
10163 + * with 3 UARTs (the third UART on the second chip is unused). Superdome
10164 + * and Keystone have one Diva chip with 3 UARTs. Some later machines have
10165 + * one Diva chip, but it has been expanded to 5 UARTs.
10166 + */
10167 +static int __devinit
10168 +pci_hp_diva(struct pci_dev *dev, struct pci_board *board, int enable)
10169 +{
10170 + if (!enable)
10171 + return 0;
10172 +
10173 + switch (dev->subsystem_device) {
10174 + case 0x1049: /* Prelude Diva 1 */
10175 + case 0x1223: /* Superdome */
10176 + case 0x1226: /* Keystone */
10177 + case 0x1282: /* Everest / Longs Peak */
10178 + board->num_ports = 3;
10179 + break;
10180 + case 0x104A: /* Prelude Diva 2 */
10181 + board->num_ports = 2;
10182 + break;
10183 + case 0x104B: /* Maestro */
10184 + board->num_ports = 4;
10185 + break;
10186 + case 0x1227: /* Powerbar */
10187 + board->num_ports = 1;
10188 + break;
10189 + }
10190 +
10191 + return 0;
10192 +}
10193 +
10194 +static int __devinit
10195 +pci_xircom_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10196 +{
10197 + __set_current_state(TASK_UNINTERRUPTIBLE);
10198 + schedule_timeout(HZ/10);
10199 + return 0;
10200 +}
10201 +
10202 +/*
10203 + * This is the configuration table for all of the PCI serial boards
10204 + * which we support. It is directly indexed by the pci_board_num_t enum
10205 + * value, which is encoded in the pci_device_id PCI probe table's
10206 + * driver_data member.
10207 + */
10208 +enum pci_board_num_t {
10209 + pbn_b0_1_115200,
10210 + pbn_default = 0,
10211 +
10212 + pbn_b0_2_115200,
10213 + pbn_b0_4_115200,
10214 +
10215 + pbn_b0_1_921600,
10216 + pbn_b0_2_921600,
10217 + pbn_b0_4_921600,
10218 +
10219 + pbn_b0_bt_1_115200,
10220 + pbn_b0_bt_2_115200,
10221 + pbn_b0_bt_1_460800,
10222 + pbn_b0_bt_2_460800,
10223 + pbn_b0_bt_2_921600,
10224 +
10225 + pbn_b1_1_115200,
10226 + pbn_b1_2_115200,
10227 + pbn_b1_4_115200,
10228 + pbn_b1_8_115200,
10229 +
10230 + pbn_b1_2_921600,
10231 + pbn_b1_4_921600,
10232 + pbn_b1_8_921600,
10233 +
10234 + pbn_b1_2_1382400,
10235 + pbn_b1_4_1382400,
10236 + pbn_b1_8_1382400,
10237 +
10238 + pbn_b2_1_115200,
10239 + pbn_b2_8_115200,
10240 + pbn_b2_4_460800,
10241 + pbn_b2_8_460800,
10242 + pbn_b2_16_460800,
10243 + pbn_b2_4_921600,
10244 + pbn_b2_8_921600,
10245 +
10246 + pbn_b2_bt_1_115200,
10247 + pbn_b2_bt_2_115200,
10248 + pbn_b2_bt_4_115200,
10249 + pbn_b2_bt_2_921600,
10250 +
10251 + pbn_panacom,
10252 + pbn_panacom2,
10253 + pbn_panacom4,
10254 + pbn_plx_romulus,
10255 + pbn_oxsemi,
10256 + pbn_timedia,
10257 + pbn_intel_i960,
10258 + pbn_sgi_ioc3,
10259 + pbn_hp_diva,
10260 +#ifdef CONFIG_DDB5074
10261 + pbn_nec_nile4,
10262 +#endif
10263 +
10264 + pbn_dci_pccom4,
10265 + pbn_dci_pccom8,
10266 +
10267 + pbn_xircom_combo,
10268 +
10269 + pbn_siig10x_0,
10270 + pbn_siig10x_1,
10271 + pbn_siig10x_2,
10272 + pbn_siig10x_4,
10273 + pbn_siig20x_0,
10274 + pbn_siig20x_2,
10275 + pbn_siig20x_4,
10276 +
10277 + pbn_computone_4,
10278 + pbn_computone_6,
10279 + pbn_computone_8,
10280 +};
10281 +
10282 +static struct pci_board pci_boards[] __devinitdata = {
10283 + /*
10284 + * PCI Flags, Number of Ports, Base (Maximum) Baud Rate,
10285 + * Offset to get to next UART's registers,
10286 + * Register shift to use for memory-mapped I/O,
10287 + * Initialization function, first UART offset
10288 + */
10289 +
10290 + /* Generic serial board, pbn_b0_1_115200, pbn_default */
10291 + { SPCI_FL_BASE0, 1, 115200 }, /* pbn_b0_1_115200,
10292 + pbn_default */
10293 +
10294 + { SPCI_FL_BASE0, 2, 115200 }, /* pbn_b0_2_115200 */
10295 + { SPCI_FL_BASE0, 4, 115200 }, /* pbn_b0_4_115200 */
10296 +
10297 + { SPCI_FL_BASE0, 1, 921600 }, /* pbn_b0_1_921600 */
10298 + { SPCI_FL_BASE0, 2, 921600 }, /* pbn_b0_2_921600 */
10299 + { SPCI_FL_BASE0, 4, 921600 }, /* pbn_b0_4_921600 */
10300 +
10301 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b0_bt_1_115200 */
10302 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b0_bt_2_115200 */
10303 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 460800 }, /* pbn_b0_bt_1_460800 */
10304 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 460800 }, /* pbn_b0_bt_2_460800 */
10305 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b0_bt_2_921600 */
10306 +
10307 + { SPCI_FL_BASE1, 1, 115200 }, /* pbn_b1_1_115200 */
10308 + { SPCI_FL_BASE1, 2, 115200 }, /* pbn_b1_2_115200 */
10309 + { SPCI_FL_BASE1, 4, 115200 }, /* pbn_b1_4_115200 */
10310 + { SPCI_FL_BASE1, 8, 115200 }, /* pbn_b1_8_115200 */
10311 +
10312 + { SPCI_FL_BASE1, 2, 921600 }, /* pbn_b1_2_921600 */
10313 + { SPCI_FL_BASE1, 4, 921600 }, /* pbn_b1_4_921600 */
10314 + { SPCI_FL_BASE1, 8, 921600 }, /* pbn_b1_8_921600 */
10315 +
10316 + { SPCI_FL_BASE1, 2, 1382400 }, /* pbn_b1_2_1382400 */
10317 + { SPCI_FL_BASE1, 4, 1382400 }, /* pbn_b1_4_1382400 */
10318 + { SPCI_FL_BASE1, 8, 1382400 }, /* pbn_b1_8_1382400 */
10319 +
10320 + { SPCI_FL_BASE2, 1, 115200 }, /* pbn_b2_1_115200 */
10321 + { SPCI_FL_BASE2, 8, 115200 }, /* pbn_b2_8_115200 */
10322 + { SPCI_FL_BASE2, 4, 460800 }, /* pbn_b2_4_460800 */
10323 + { SPCI_FL_BASE2, 8, 460800 }, /* pbn_b2_8_460800 */
10324 + { SPCI_FL_BASE2, 16, 460800 }, /* pbn_b2_16_460800 */
10325 + { SPCI_FL_BASE2, 4, 921600 }, /* pbn_b2_4_921600 */
10326 + { SPCI_FL_BASE2, 8, 921600 }, /* pbn_b2_8_921600 */
10327 +
10328 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b2_bt_1_115200 */
10329 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b2_bt_2_115200 */
10330 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 115200 }, /* pbn_b2_bt_4_115200 */
10331 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b2_bt_2_921600 */
10332 +
10333 + { SPCI_FL_BASE2, 2, 921600, /* IOMEM */ /* pbn_panacom */
10334 + 0x400, 7, pci_plx9050_fn },
10335 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_panacom2 */
10336 + 0x400, 7, pci_plx9050_fn },
10337 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_panacom4 */
10338 + 0x400, 7, pci_plx9050_fn },
10339 + { SPCI_FL_BASE2, 4, 921600, /* pbn_plx_romulus */
10340 + 0x20, 2, pci_plx9050_fn, 0x03 },
10341 + /* This board uses the size of PCI Base region 0 to
10342 + * signal now many ports are available */
10343 + { SPCI_FL_BASE0 | SPCI_FL_REGION_SZ_CAP, 32, 115200 }, /* pbn_oxsemi */
10344 + { SPCI_FL_BASE_TABLE, 1, 921600, /* pbn_timedia */
10345 + 0, 0, pci_timedia_fn },
10346 + /* EKF addition for i960 Boards form EKF with serial port */
10347 + { SPCI_FL_BASE0, 32, 921600, /* max 256 ports */ /* pbn_intel_i960 */
10348 + 8<<2, 2, pci_inteli960ni_fn, 0x10000},
10349 + { SPCI_FL_BASE0 | SPCI_FL_IRQRESOURCE, /* pbn_sgi_ioc3 */
10350 + 1, 458333, 0, 0, 0, 0x20178 },
10351 + { SPCI_FL_BASE0, 5, 115200, 8, 0, pci_hp_diva, 0}, /* pbn_hp_diva */
10352 +#ifdef CONFIG_DDB5074
10353 + /*
10354 + * NEC Vrc-5074 (Nile 4) builtin UART.
10355 + * Conditionally compiled in since this is a motherboard device.
10356 + */
10357 + { SPCI_FL_BASE0, 1, 520833, /* pbn_nec_nile4 */
10358 + 64, 3, NULL, 0x300 },
10359 +#endif
10360 +
10361 + {SPCI_FL_BASE3, 4, 115200, 8}, /* pbn_dci_pccom4 */
10362 + {SPCI_FL_BASE3, 8, 115200, 8}, /* pbn_dci_pccom8 */
10363 +
10364 + { SPCI_FL_BASE0, 1, 115200, /* pbn_xircom_combo */
10365 + 0, 0, pci_xircom_fn },
10366 +
10367 + { SPCI_FL_BASE2, 1, 460800, /* pbn_siig10x_0 */
10368 + 0, 0, pci_siig10x_fn },
10369 + { SPCI_FL_BASE2, 1, 921600, /* pbn_siig10x_1 */
10370 + 0, 0, pci_siig10x_fn },
10371 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siig10x_2 */
10372 + 0, 0, pci_siig10x_fn },
10373 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siig10x_4 */
10374 + 0, 0, pci_siig10x_fn },
10375 + { SPCI_FL_BASE0, 1, 921600, /* pbn_siix20x_0 */
10376 + 0, 0, pci_siig20x_fn },
10377 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siix20x_2 */
10378 + 0, 0, pci_siig20x_fn },
10379 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siix20x_4 */
10380 + 0, 0, pci_siig20x_fn },
10381 +
10382 + { SPCI_FL_BASE0, 4, 921600, /* IOMEM */ /* pbn_computone_4 */
10383 + 0x40, 2, NULL, 0x200 },
10384 + { SPCI_FL_BASE0, 6, 921600, /* IOMEM */ /* pbn_computone_6 */
10385 + 0x40, 2, NULL, 0x200 },
10386 + { SPCI_FL_BASE0, 8, 921600, /* IOMEM */ /* pbn_computone_8 */
10387 + 0x40, 2, NULL, 0x200 },
10388 +};
10389 +
10390 +/*
10391 + * Given a complete unknown PCI device, try to use some heuristics to
10392 + * guess what the configuration might be, based on the pitiful PCI
10393 + * serial specs. Returns 0 on success, 1 on failure.
10394 + */
10395 +static int __devinit serial_pci_guess_board(struct pci_dev *dev,
10396 + struct pci_board *board)
10397 +{
10398 + int num_iomem = 0, num_port = 0, first_port = -1;
10399 + int i;
10400 +
10401 + /*
10402 + * If it is not a communications device or the programming
10403 + * interface is greater than 6, give up.
10404 + *
10405 + * (Should we try to make guesses for multiport serial devices
10406 + * later?)
10407 + */
10408 + if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
10409 + ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
10410 + (dev->class & 0xff) > 6)
10411 + return 1;
10412 +
10413 + for (i=0; i < 6; i++) {
10414 + if (IS_PCI_REGION_IOPORT(dev, i)) {
10415 + num_port++;
10416 + if (first_port == -1)
10417 + first_port = i;
10418 + }
10419 + if (IS_PCI_REGION_IOMEM(dev, i))
10420 + num_iomem++;
10421 + }
10422 +
10423 + /*
10424 + * If there is 1 or 0 iomem regions, and exactly one port, use
10425 + * it.
10426 + */
10427 + if (num_iomem <= 1 && num_port == 1) {
10428 + board->flags = first_port;
10429 + return 0;
10430 + }
10431 + return 1;
10432 +}
10433 +
10434 +static int __devinit serial_init_one(struct pci_dev *dev,
10435 + const struct pci_device_id *ent)
10436 +{
10437 + struct pci_board *board, tmp;
10438 + int rc;
10439 +
10440 + board = &pci_boards[ent->driver_data];
10441 +
10442 + rc = pci_enable_device(dev);
10443 + if (rc) return rc;
10444 +
10445 + if (ent->driver_data == pbn_default &&
10446 + serial_pci_guess_board(dev, board))
10447 + return -ENODEV;
10448 + else if (serial_pci_guess_board(dev, &tmp) == 0) {
10449 + printk(KERN_INFO "Redundant entry in serial pci_table. "
10450 + "Please send the output of\n"
10451 + "lspci -vv, this message (%04x,%04x,%04x,%04x)\n"
10452 + "and the manufacturer and name of "
10453 + "serial board or modem board\n"
10454 + "to serial-pci-info@lists.sourceforge.net.\n",
10455 + dev->vendor, dev->device,
10456 + pci_get_subvendor(dev), pci_get_subdevice(dev));
10457 + }
10458 +
10459 + start_pci_pnp_board(dev, board);
10460 +
10461 + return 0;
10462 +}
10463 +
10464 +static void __devexit serial_remove_one(struct pci_dev *dev)
10465 +{
10466 + int i;
10467 +
10468 + /*
10469 + * Iterate through all of the ports finding those that belong
10470 + * to this PCI device.
10471 + */
10472 + for(i = 0; i < NR_PORTS; i++) {
10473 + if (rs_table[i].dev != dev)
10474 + continue;
10475 + unregister_serial(i);
10476 + rs_table[i].dev = 0;
10477 + }
10478 + /*
10479 + * Now execute any board-specific shutdown procedure
10480 + */
10481 + for (i=0; i < NR_PCI_BOARDS; i++) {
10482 + struct pci_board_inst *brd = &serial_pci_board[i];
10483 +
10484 + if (serial_pci_board[i].dev != dev)
10485 + continue;
10486 + if (brd->board.init_fn)
10487 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
10488 + if (DEACTIVATE_FUNC(brd->dev))
10489 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
10490 + serial_pci_board[i].dev = 0;
10491 + }
10492 +}
10493 +
10494 +
10495 +static struct pci_device_id serial_pci_tbl[] __devinitdata = {
10496 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10497 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10498 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
10499 + pbn_b1_8_1382400 },
10500 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10501 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10502 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
10503 + pbn_b1_4_1382400 },
10504 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
10505 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10506 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
10507 + pbn_b1_2_1382400 },
10508 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10509 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10510 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
10511 + pbn_b1_8_1382400 },
10512 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10513 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10514 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
10515 + pbn_b1_4_1382400 },
10516 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10517 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10518 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
10519 + pbn_b1_2_1382400 },
10520 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10521 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10522 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
10523 + pbn_b1_8_921600 },
10524 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10525 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10526 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
10527 + pbn_b1_8_921600 },
10528 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10529 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10530 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
10531 + pbn_b1_4_921600 },
10532 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10533 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10534 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
10535 + pbn_b1_4_921600 },
10536 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10537 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10538 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
10539 + pbn_b1_2_921600 },
10540 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10541 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10542 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
10543 + pbn_b1_8_921600 },
10544 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10545 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10546 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
10547 + pbn_b1_8_921600 },
10548 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
10549 + PCI_SUBVENDOR_ID_CONNECT_TECH,
10550 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
10551 + pbn_b1_4_921600 },
10552 +
10553 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
10554 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10555 + pbn_b2_bt_1_115200 },
10556 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
10557 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10558 + pbn_b2_bt_2_115200 },
10559 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
10560 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10561 + pbn_b2_bt_4_115200 },
10562 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
10563 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10564 + pbn_b2_bt_2_115200 },
10565 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
10566 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10567 + pbn_b2_bt_4_115200 },
10568 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
10569 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10570 + pbn_b2_8_115200 },
10571 +
10572 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
10573 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10574 + pbn_b2_bt_2_115200 },
10575 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
10576 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10577 + pbn_b2_bt_2_921600 },
10578 + /* VScom SPCOM800, from sl@s.pl */
10579 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
10580 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10581 + pbn_b2_8_921600 },
10582 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
10583 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10584 + pbn_b2_4_921600 },
10585 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10586 + PCI_SUBVENDOR_ID_KEYSPAN,
10587 + PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
10588 + pbn_panacom },
10589 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
10590 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10591 + pbn_panacom4 },
10592 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
10593 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10594 + pbn_panacom2 },
10595 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10596 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10597 + PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
10598 + pbn_b2_4_460800 },
10599 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10600 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10601 + PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
10602 + pbn_b2_8_460800 },
10603 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10604 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10605 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
10606 + pbn_b2_16_460800 },
10607 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10608 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
10609 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
10610 + pbn_b2_16_460800 },
10611 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10612 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
10613 + PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
10614 + pbn_b2_4_460800 },
10615 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
10616 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
10617 + PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
10618 + pbn_b2_8_460800 },
10619 + /* Megawolf Romulus PCI Serial Card, from Mike Hudson */
10620 + /* (Exoray@isys.ca) */
10621 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
10622 + 0x10b5, 0x106a, 0, 0,
10623 + pbn_plx_romulus },
10624 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
10625 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10626 + pbn_b1_4_115200 },
10627 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
10628 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10629 + pbn_b1_2_115200 },
10630 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
10631 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10632 + pbn_b1_8_115200 },
10633 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
10634 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10635 + pbn_b1_8_115200 },
10636 + { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
10637 + PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
10638 + pbn_b0_4_921600 },
10639 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
10640 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10641 + pbn_b0_4_115200 },
10642 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
10643 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10644 + pbn_b0_bt_2_921600 },
10645 +
10646 + /* Digitan DS560-558, from jimd@esoft.com */
10647 + { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
10648 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10649 + pbn_b1_1_115200 },
10650 +
10651 + /* 3Com US Robotics 56k Voice Internal PCI model 5610 */
10652 + { PCI_VENDOR_ID_USR, 0x1008,
10653 + PCI_ANY_ID, PCI_ANY_ID, },
10654 +
10655 + /* Titan Electronic cards */
10656 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
10657 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10658 + pbn_b0_1_921600 },
10659 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
10660 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10661 + pbn_b0_2_921600 },
10662 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
10663 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10664 + pbn_b0_4_921600 },
10665 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
10666 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10667 + pbn_b0_4_921600 },
10668 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
10669 + PCI_ANY_ID, PCI_ANY_ID,
10670 + SPCI_FL_BASE1, 1, 921600 },
10671 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
10672 + PCI_ANY_ID, PCI_ANY_ID,
10673 + SPCI_FL_BASE1 | SPCI_FL_BASE_TABLE, 2, 921600 },
10674 + /* The 400L and 800L have a custom hack in get_pci_port */
10675 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
10676 + PCI_ANY_ID, PCI_ANY_ID,
10677 + SPCI_FL_BASE_TABLE, 4, 921600 },
10678 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
10679 + PCI_ANY_ID, PCI_ANY_ID,
10680 + SPCI_FL_BASE_TABLE, 8, 921600 },
10681 +
10682 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
10683 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10684 + pbn_siig10x_0 },
10685 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
10686 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10687 + pbn_siig10x_0 },
10688 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
10689 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10690 + pbn_siig10x_0 },
10691 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
10692 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10693 + pbn_siig10x_2 },
10694 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
10695 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10696 + pbn_siig10x_2 },
10697 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
10698 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10699 + pbn_siig10x_2 },
10700 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
10701 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10702 + pbn_siig10x_4 },
10703 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
10704 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10705 + pbn_siig10x_4 },
10706 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
10707 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10708 + pbn_siig10x_4 },
10709 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
10710 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10711 + pbn_siig20x_0 },
10712 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
10713 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10714 + pbn_siig20x_0 },
10715 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
10716 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10717 + pbn_siig20x_0 },
10718 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
10719 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10720 + pbn_siig20x_2 },
10721 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
10722 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10723 + pbn_siig20x_2 },
10724 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
10725 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10726 + pbn_siig20x_2 },
10727 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
10728 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10729 + pbn_siig20x_4 },
10730 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
10731 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10732 + pbn_siig20x_4 },
10733 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
10734 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10735 + pbn_siig20x_4 },
10736 +
10737 + /* Computone devices submitted by Doug McNash dmcnash@computone.com */
10738 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10739 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
10740 + 0, 0, pbn_computone_4 },
10741 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10742 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
10743 + 0, 0, pbn_computone_8 },
10744 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
10745 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
10746 + 0, 0, pbn_computone_6 },
10747 +
10748 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
10749 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_oxsemi },
10750 + { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
10751 + PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, pbn_timedia },
10752 +
10753 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
10754 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10755 + pbn_b0_bt_2_115200 },
10756 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
10757 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10758 + pbn_b0_bt_2_115200 },
10759 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
10760 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10761 + pbn_b0_bt_2_115200 },
10762 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
10763 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10764 + pbn_b0_bt_2_460800 },
10765 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
10766 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10767 + pbn_b0_bt_2_460800 },
10768 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
10769 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10770 + pbn_b0_bt_2_460800 },
10771 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
10772 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10773 + pbn_b0_bt_1_115200 },
10774 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
10775 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10776 + pbn_b0_bt_1_460800 },
10777 +
10778 + /* RAStel 2 port modem, gerg@moreton.com.au */
10779 + { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
10780 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10781 + pbn_b2_bt_2_115200 },
10782 +
10783 + /* EKF addition for i960 Boards form EKF with serial port */
10784 + { PCI_VENDOR_ID_INTEL, 0x1960,
10785 + 0xE4BF, PCI_ANY_ID, 0, 0,
10786 + pbn_intel_i960 },
10787 +
10788 + /* Xircom Cardbus/Ethernet combos */
10789 + { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
10790 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10791 + pbn_xircom_combo },
10792 +
10793 + /*
10794 + * Untested PCI modems, sent in from various folks...
10795 + */
10796 +
10797 + /* Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> */
10798 + { PCI_VENDOR_ID_ROCKWELL, 0x1004,
10799 + 0x1048, 0x1500, 0, 0,
10800 + pbn_b1_1_115200 },
10801 +
10802 + { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
10803 + 0xFF00, 0, 0, 0,
10804 + pbn_sgi_ioc3 },
10805 +
10806 + /* HP Diva card */
10807 + { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_SAS,
10808 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10809 + pbn_hp_diva },
10810 + { PCI_VENDOR_ID_HP, 0x1290,
10811 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10812 + pbn_b2_1_115200 },
10813 +
10814 +#ifdef CONFIG_DDB5074
10815 + /*
10816 + * NEC Vrc-5074 (Nile 4) builtin UART.
10817 + * Conditionally compiled in since this is a motherboard device.
10818 + */
10819 + { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
10820 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10821 + pbn_nec_nile4 },
10822 +#endif
10823 +
10824 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
10825 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10826 + pbn_dci_pccom4 },
10827 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
10828 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
10829 + pbn_dci_pccom8 },
10830 +
10831 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
10832 + PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, },
10833 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
10834 + PCI_CLASS_COMMUNICATION_MODEM << 8, 0xffff00, },
10835 + { 0, }
10836 +};
10837 +
10838 +MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
10839 +
10840 +static struct pci_driver serial_pci_driver = {
10841 + name: "serial",
10842 + probe: serial_init_one,
10843 + remove: __devexit_p(serial_remove_one),
10844 + id_table: serial_pci_tbl,
10845 +};
10846 +
10847 +
10848 +/*
10849 + * Query PCI space for known serial boards
10850 + * If found, add them to the PCI device space in rs_table[]
10851 + *
10852 + * Accept a maximum of eight boards
10853 + *
10854 + */
10855 +static void __devinit probe_serial_pci(void)
10856 +{
10857 +#ifdef SERIAL_DEBUG_PCI
10858 + printk(KERN_DEBUG "Entered probe_serial_pci()\n");
10859 +#endif
10860 +
10861 + /* Register call PCI serial devices. Null out
10862 + * the driver name upon failure, as a signal
10863 + * not to attempt to unregister the driver later
10864 + */
10865 + if (pci_module_init (&serial_pci_driver) != 0)
10866 + serial_pci_driver.name = "";
10867 +
10868 +#ifdef SERIAL_DEBUG_PCI
10869 + printk(KERN_DEBUG "Leaving probe_serial_pci() (probe finished)\n");
10870 +#endif
10871 + return;
10872 +}
10873 +
10874 +#endif /* ENABLE_SERIAL_PCI */
10875 +
10876 +#ifdef ENABLE_SERIAL_PNP
10877 +
10878 +struct pnp_board {
10879 + unsigned short vendor;
10880 + unsigned short device;
10881 +};
10882 +
10883 +static struct pnp_board pnp_devices[] __devinitdata = {
10884 + /* Archtek America Corp. */
10885 + /* Archtek SmartLink Modem 3334BT Plug & Play */
10886 + { ISAPNP_VENDOR('A', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
10887 + /* Anchor Datacomm BV */
10888 + /* SXPro 144 External Data Fax Modem Plug & Play */
10889 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0001) },
10890 + /* SXPro 288 External Data Fax Modem Plug & Play */
10891 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0002) },
10892 + /* Rockwell 56K ACF II Fax+Data+Voice Modem */
10893 + { ISAPNP_VENDOR('A', 'K', 'Y'), ISAPNP_DEVICE(0x1021) },
10894 + /* AZT3005 PnP SOUND DEVICE */
10895 + { ISAPNP_VENDOR('A', 'Z', 'T'), ISAPNP_DEVICE(0x4001) },
10896 + /* Best Data Products Inc. Smart One 336F PnP Modem */
10897 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
10898 + /* Boca Research */
10899 + /* Boca Complete Ofc Communicator 14.4 Data-FAX */
10900 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
10901 + /* Boca Research 33,600 ACF Modem */
10902 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x1400) },
10903 + /* Boca 33.6 Kbps Internal FD34FSVD */
10904 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x3400) },
10905 + /* Boca 33.6 Kbps Internal FD34FSVD */
10906 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
10907 + /* Best Data Products Inc. Smart One 336F PnP Modem */
10908 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
10909 + /* Computer Peripherals Inc */
10910 + /* EuroViVa CommCenter-33.6 SP PnP */
10911 + { ISAPNP_VENDOR('C', 'P', 'I'), ISAPNP_DEVICE(0x4050) },
10912 + /* Creative Labs */
10913 + /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
10914 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3001) },
10915 + /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
10916 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3011) },
10917 + /* Creative */
10918 + /* Creative Modem Blaster Flash56 DI5601-1 */
10919 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x1032) },
10920 + /* Creative Modem Blaster V.90 DI5660 */
10921 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x2001) },
10922 + /* FUJITSU */
10923 + /* Fujitsu 33600 PnP-I2 R Plug & Play */
10924 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0202) },
10925 + /* Fujitsu FMV-FX431 Plug & Play */
10926 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0205) },
10927 + /* Fujitsu 33600 PnP-I4 R Plug & Play */
10928 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0206) },
10929 + /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
10930 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0209) },
10931 + /* Archtek America Corp. */
10932 + /* Archtek SmartLink Modem 3334BT Plug & Play */
10933 + { ISAPNP_VENDOR('G', 'V', 'C'), ISAPNP_DEVICE(0x000F) },
10934 + /* Hayes */
10935 + /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
10936 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x0001) },
10937 + /* Hayes Optima 336 V.34 + FAX + Voice PnP */
10938 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000C) },
10939 + /* Hayes Optima 336B V.34 + FAX + Voice PnP */
10940 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000D) },
10941 + /* Hayes Accura 56K Ext Fax Modem PnP */
10942 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5670) },
10943 + /* Hayes Accura 56K Ext Fax Modem PnP */
10944 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5674) },
10945 + /* Hayes Accura 56K Fax Modem PnP */
10946 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5675) },
10947 + /* Hayes 288, V.34 + FAX */
10948 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF000) },
10949 + /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
10950 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF001) },
10951 + /* IBM */
10952 + /* IBM Thinkpad 701 Internal Modem Voice */
10953 + { ISAPNP_VENDOR('I', 'B', 'M'), ISAPNP_DEVICE(0x0033) },
10954 + /* Intertex */
10955 + /* Intertex 28k8 33k6 Voice EXT PnP */
10956 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC801) },
10957 + /* Intertex 33k6 56k Voice EXT PnP */
10958 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC901) },
10959 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
10960 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD801) },
10961 + /* Intertex 33k6 56k Voice SP EXT PnP */
10962 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD901) },
10963 + /* Intertex 28k8 33k6 Voice SP INT PnP */
10964 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF401) },
10965 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
10966 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF801) },
10967 + /* Intertex 33k6 56k Voice SP EXT PnP */
10968 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF901) },
10969 + /* Kortex International */
10970 + /* KORTEX 28800 Externe PnP */
10971 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0x4522) },
10972 + /* KXPro 33.6 Vocal ASVD PnP */
10973 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0xF661) },
10974 + /* Lasat */
10975 + /* LASAT Internet 33600 PnP */
10976 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4040) },
10977 + /* Lasat Safire 560 PnP */
10978 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4540) },
10979 + /* Lasat Safire 336 PnP */
10980 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x5440) },
10981 + /* Microcom, Inc. */
10982 + /* Microcom TravelPorte FAST V.34 Plug & Play */
10983 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x281) },
10984 + /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
10985 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0336) },
10986 + /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
10987 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0339) },
10988 + /* Microcom DeskPorte 28.8P Plug & Play */
10989 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0342) },
10990 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
10991 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
10992 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
10993 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
10994 + /* Microcom DeskPorte 28.8S Internal Plug & Play */
10995 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0502) },
10996 + /* Motorola */
10997 + /* Motorola BitSURFR Plug & Play */
10998 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1105) },
10999 + /* Motorola TA210 Plug & Play */
11000 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1111) },
11001 + /* Motorola HMTA 200 (ISDN) Plug & Play */
11002 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1114) },
11003 + /* Motorola BitSURFR Plug & Play */
11004 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1115) },
11005 + /* Motorola Lifestyle 28.8 Internal */
11006 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1190) },
11007 + /* Motorola V.3400 Plug & Play */
11008 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1501) },
11009 + /* Motorola Lifestyle 28.8 V.34 Plug & Play */
11010 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1502) },
11011 + /* Motorola Power 28.8 V.34 Plug & Play */
11012 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1505) },
11013 + /* Motorola ModemSURFR External 28.8 Plug & Play */
11014 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1509) },
11015 + /* Motorola Premier 33.6 Desktop Plug & Play */
11016 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150A) },
11017 + /* Motorola VoiceSURFR 56K External PnP */
11018 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150F) },
11019 + /* Motorola ModemSURFR 56K External PnP */
11020 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1510) },
11021 + /* Motorola ModemSURFR 56K Internal PnP */
11022 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1550) },
11023 + /* Motorola ModemSURFR Internal 28.8 Plug & Play */
11024 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1560) },
11025 + /* Motorola Premier 33.6 Internal Plug & Play */
11026 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1580) },
11027 + /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
11028 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15B0) },
11029 + /* Motorola VoiceSURFR 56K Internal PnP */
11030 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15F0) },
11031 + /* Com 1 */
11032 + /* Deskline K56 Phone System PnP */
11033 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00A1) },
11034 + /* PC Rider K56 Phone System PnP */
11035 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00F2) },
11036 + /* Pace 56 Voice Internal Plug & Play Modem */
11037 + { ISAPNP_VENDOR('P', 'M', 'C'), ISAPNP_DEVICE(0x2430) },
11038 + /* Generic */
11039 + /* Generic standard PC COM port */
11040 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
11041 + /* Generic 16550A-compatible COM port */
11042 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
11043 + /* Compaq 14400 Modem */
11044 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC000) },
11045 + /* Compaq 2400/9600 Modem */
11046 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC001) },
11047 + /* Dial-Up Networking Serial Cable between 2 PCs */
11048 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC031) },
11049 + /* Dial-Up Networking Parallel Cable between 2 PCs */
11050 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC032) },
11051 + /* Standard 9600 bps Modem */
11052 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC100) },
11053 + /* Standard 14400 bps Modem */
11054 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC101) },
11055 + /* Standard 28800 bps Modem*/
11056 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC102) },
11057 + /* Standard Modem*/
11058 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC103) },
11059 + /* Standard 9600 bps Modem*/
11060 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC104) },
11061 + /* Standard 14400 bps Modem*/
11062 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC105) },
11063 + /* Standard 28800 bps Modem*/
11064 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC106) },
11065 + /* Standard Modem */
11066 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC107) },
11067 + /* Standard 9600 bps Modem */
11068 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC108) },
11069 + /* Standard 14400 bps Modem */
11070 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC109) },
11071 + /* Standard 28800 bps Modem */
11072 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10A) },
11073 + /* Standard Modem */
11074 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10B) },
11075 + /* Standard 9600 bps Modem */
11076 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10C) },
11077 + /* Standard 14400 bps Modem */
11078 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10D) },
11079 + /* Standard 28800 bps Modem */
11080 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10E) },
11081 + /* Standard Modem */
11082 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10F) },
11083 + /* Standard PCMCIA Card Modem */
11084 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x2000) },
11085 + /* Rockwell */
11086 + /* Modular Technology */
11087 + /* Rockwell 33.6 DPF Internal PnP */
11088 + /* Modular Technology 33.6 Internal PnP */
11089 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0030) },
11090 + /* Kortex International */
11091 + /* KORTEX 14400 Externe PnP */
11092 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0100) },
11093 + /* Viking Components, Inc */
11094 + /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
11095 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x4920) },
11096 + /* Rockwell */
11097 + /* British Telecom */
11098 + /* Modular Technology */
11099 + /* Rockwell 33.6 DPF External PnP */
11100 + /* BT Prologue 33.6 External PnP */
11101 + /* Modular Technology 33.6 External PnP */
11102 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x00A0) },
11103 + /* Viking 56K FAX INT */
11104 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x0262) },
11105 + /* SupraExpress 28.8 Data/Fax PnP modem */
11106 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1310) },
11107 + /* SupraExpress 33.6 Data/Fax PnP modem */
11108 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1421) },
11109 + /* SupraExpress 33.6 Data/Fax PnP modem */
11110 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1590) },
11111 + /* SupraExpress 33.6 Data/Fax PnP modem */
11112 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1760) },
11113 + /* Phoebe Micro */
11114 + /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
11115 + { ISAPNP_VENDOR('T', 'E', 'X'), ISAPNP_DEVICE(0x0011) },
11116 + /* Archtek America Corp. */
11117 + /* Archtek SmartLink Modem 3334BT Plug & Play */
11118 + { ISAPNP_VENDOR('U', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
11119 + /* 3Com Corp. */
11120 + /* Gateway Telepath IIvi 33.6 */
11121 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0000) },
11122 + /* Sportster Vi 14.4 PnP FAX Voicemail */
11123 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0004) },
11124 + /* U.S. Robotics 33.6K Voice INT PnP */
11125 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0006) },
11126 + /* U.S. Robotics 33.6K Voice EXT PnP */
11127 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0007) },
11128 + /* U.S. Robotics 33.6K Voice INT PnP */
11129 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2002) },
11130 + /* U.S. Robotics 56K Voice INT PnP */
11131 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2070) },
11132 + /* U.S. Robotics 56K Voice EXT PnP */
11133 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2080) },
11134 + /* U.S. Robotics 56K FAX INT */
11135 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3031) },
11136 + /* U.S. Robotics 56K Voice INT PnP */
11137 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3070) },
11138 + /* U.S. Robotics 56K Voice EXT PnP */
11139 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3080) },
11140 + /* U.S. Robotics 56K Voice INT PnP */
11141 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3090) },
11142 + /* U.S. Robotics 56K Message */
11143 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9100) },
11144 + /* U.S. Robotics 56K FAX EXT PnP*/
11145 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9160) },
11146 + /* U.S. Robotics 56K FAX INT PnP*/
11147 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9170) },
11148 + /* U.S. Robotics 56K Voice EXT PnP*/
11149 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9180) },
11150 + /* U.S. Robotics 56K Voice INT PnP*/
11151 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9190) },
11152 + { 0, }
11153 +};
11154 +
11155 +static inline void avoid_irq_share(struct pci_dev *dev)
11156 +{
11157 + int i, map = 0x1FF8;
11158 + struct serial_state *state = rs_table;
11159 + struct isapnp_irq *irq;
11160 + struct isapnp_resources *res = dev->sysdata;
11161 +
11162 + for (i = 0; i < NR_PORTS; i++) {
11163 + if (state->type != PORT_UNKNOWN)
11164 + clear_bit(state->irq, &map);
11165 + state++;
11166 + }
11167 +
11168 + for ( ; res; res = res->alt)
11169 + for(irq = res->irq; irq; irq = irq->next)
11170 + irq->map = map;
11171 +}
11172 +
11173 +static char *modem_names[] __devinitdata = {
11174 + "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
11175 + "56K", "56k", "K56", "33.6", "28.8", "14.4",
11176 + "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
11177 + "33600", "28800", "14400", "V.90", "V.34", "V.32", 0
11178 +};
11179 +
11180 +static int __devinit check_name(char *name)
11181 +{
11182 + char **tmp = modem_names;
11183 +
11184 + while (*tmp) {
11185 + if (strstr(name, *tmp))
11186 + return 1;
11187 + tmp++;
11188 + }
11189 + return 0;
11190 +}
11191 +
11192 +static inline int check_compatible_id(struct pci_dev *dev)
11193 +{
11194 + int i;
11195 + for (i = 0; i < DEVICE_COUNT_COMPATIBLE; i++)
11196 + if ((dev->vendor_compatible[i] ==
11197 + ISAPNP_VENDOR('P', 'N', 'P')) &&
11198 + (swab16(dev->device_compatible[i]) >= 0xc000) &&
11199 + (swab16(dev->device_compatible[i]) <= 0xdfff))
11200 + return 0;
11201 + return 1;
11202 +}
11203 +
11204 +/*
11205 + * Given a complete unknown ISA PnP device, try to use some heuristics to
11206 + * detect modems. Currently use such heuristic set:
11207 + * - dev->name or dev->bus->name must contain "modem" substring;
11208 + * - device must have only one IO region (8 byte long) with base adress
11209 + * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
11210 + *
11211 + * Such detection looks very ugly, but can detect at least some of numerous
11212 + * ISA PnP modems, alternatively we must hardcode all modems in pnp_devices[]
11213 + * table.
11214 + */
11215 +static int _INLINE_ serial_pnp_guess_board(struct pci_dev *dev,
11216 + struct pci_board *board)
11217 +{
11218 + struct isapnp_resources *res = (struct isapnp_resources *)dev->sysdata;
11219 + struct isapnp_resources *resa;
11220 +
11221 + if (!(check_name(dev->name) || check_name(dev->bus->name)) &&
11222 + !(check_compatible_id(dev)))
11223 + return 1;
11224 +
11225 + if (!res || res->next)
11226 + return 1;
11227 +
11228 + for (resa = res->alt; resa; resa = resa->alt) {
11229 + struct isapnp_port *port;
11230 + for (port = res->port; port; port = port->next)
11231 + if ((port->size == 8) &&
11232 + ((port->min == 0x2f8) ||
11233 + (port->min == 0x3f8) ||
11234 + (port->min == 0x2e8) ||
11235 + (port->min == 0x3e8)))
11236 + return 0;
11237 + }
11238 +
11239 + return 1;
11240 +}
11241 +
11242 +static void __devinit probe_serial_pnp(void)
11243 +{
11244 + struct pci_dev *dev = NULL;
11245 + struct pnp_board *pnp_board;
11246 + struct pci_board board;
11247 +
11248 +#ifdef SERIAL_DEBUG_PNP
11249 + printk("Entered probe_serial_pnp()\n");
11250 +#endif
11251 + if (!isapnp_present()) {
11252 +#ifdef SERIAL_DEBUG_PNP
11253 + printk("Leaving probe_serial_pnp() (no isapnp)\n");
11254 +#endif
11255 + return;
11256 + }
11257 +
11258 + isapnp_for_each_dev(dev) {
11259 + if (dev->active)
11260 + continue;
11261 +
11262 + memset(&board, 0, sizeof(board));
11263 + board.flags = SPCI_FL_BASE0 | SPCI_FL_PNPDEFAULT;
11264 + board.num_ports = 1;
11265 + board.base_baud = 115200;
11266 +
11267 + for (pnp_board = pnp_devices; pnp_board->vendor; pnp_board++)
11268 + if ((dev->vendor == pnp_board->vendor) &&
11269 + (dev->device == pnp_board->device))
11270 + break;
11271 +
11272 + if (pnp_board->vendor) {
11273 + /* Special case that's more efficient to hardcode */
11274 + if ((pnp_board->vendor == ISAPNP_VENDOR('A', 'K', 'Y') &&
11275 + pnp_board->device == ISAPNP_DEVICE(0x1021)))
11276 + board.flags |= SPCI_FL_NO_SHIRQ;
11277 + } else {
11278 + if (serial_pnp_guess_board(dev, &board))
11279 + continue;
11280 + }
11281 +
11282 + if (board.flags & SPCI_FL_NO_SHIRQ)
11283 + avoid_irq_share(dev);
11284 + start_pci_pnp_board(dev, &board);
11285 + }
11286 +
11287 +#ifdef SERIAL_DEBUG_PNP
11288 + printk("Leaving probe_serial_pnp() (probe finished)\n");
11289 +#endif
11290 + return;
11291 +}
11292 +
11293 +#endif /* ENABLE_SERIAL_PNP */
11294 +
11295 +/*
11296 + * The serial driver boot-time initialization code!
11297 + */
11298 +static int __init rs_init(void)
11299 +{
11300 + int i;
11301 + struct serial_state * state;
11302 +
11303 + init_bh(SERIAL_BH, do_serial_bh);
11304 + init_timer(&serial_timer);
11305 + serial_timer.function = rs_timer;
11306 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
11307 +
11308 + for (i = 0; i < NR_IRQS; i++) {
11309 + IRQ_ports[i] = 0;
11310 + IRQ_timeout[i] = 0;
11311 +#ifdef CONFIG_SERIAL_MULTIPORT
11312 + memset(&rs_multiport[i], 0,
11313 + sizeof(struct rs_multiport_struct));
11314 +#endif
11315 + }
11316 + show_serial_version();
11317 +
11318 + /* Initialize the tty_driver structure */
11319 +
11320 + memset(&serial_driver, 0, sizeof(struct tty_driver));
11321 + serial_driver.magic = TTY_DRIVER_MAGIC;
11322 +#if (LINUX_VERSION_CODE > 0x20100)
11323 + serial_driver.driver_name = "serial";
11324 +#endif
11325 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11326 + serial_driver.name = "tts/%d";
11327 +#else
11328 + serial_driver.name = "ttyS";
11329 +#endif
11330 + serial_driver.major = TTY_MAJOR;
11331 + serial_driver.minor_start = 64 + SERIAL_DEV_OFFSET;
11332 + serial_driver.name_base = SERIAL_DEV_OFFSET;
11333 + serial_driver.num = NR_PORTS;
11334 + serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
11335 + serial_driver.subtype = SERIAL_TYPE_NORMAL;
11336 + serial_driver.init_termios = tty_std_termios;
11337 + serial_driver.init_termios.c_cflag =
11338 + B9600 | CS8 | CREAD | HUPCL | CLOCAL;
11339 + serial_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
11340 + serial_driver.refcount = &serial_refcount;
11341 + serial_driver.table = serial_table;
11342 + serial_driver.termios = serial_termios;
11343 + serial_driver.termios_locked = serial_termios_locked;
11344 +
11345 + serial_driver.open = rs_open;
11346 + serial_driver.close = rs_close;
11347 + serial_driver.write = rs_write;
11348 + serial_driver.put_char = rs_put_char;
11349 + serial_driver.flush_chars = rs_flush_chars;
11350 + serial_driver.write_room = rs_write_room;
11351 + serial_driver.chars_in_buffer = rs_chars_in_buffer;
11352 + serial_driver.flush_buffer = rs_flush_buffer;
11353 + serial_driver.ioctl = rs_ioctl;
11354 + serial_driver.throttle = rs_throttle;
11355 + serial_driver.unthrottle = rs_unthrottle;
11356 + serial_driver.set_termios = rs_set_termios;
11357 + serial_driver.stop = rs_stop;
11358 + serial_driver.start = rs_start;
11359 + serial_driver.hangup = rs_hangup;
11360 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
11361 + serial_driver.break_ctl = rs_break;
11362 +#endif
11363 +#if (LINUX_VERSION_CODE >= 131343)
11364 + serial_driver.send_xchar = rs_send_xchar;
11365 + serial_driver.wait_until_sent = rs_wait_until_sent;
11366 + serial_driver.read_proc = rs_read_proc;
11367 +#endif
11368 +
11369 + /*
11370 + * The callout device is just like normal device except for
11371 + * major number and the subtype code.
11372 + */
11373 + callout_driver = serial_driver;
11374 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11375 + callout_driver.name = "cua/%d";
11376 +#else
11377 + callout_driver.name = "cua";
11378 +#endif
11379 + callout_driver.major = TTYAUX_MAJOR;
11380 + callout_driver.subtype = SERIAL_TYPE_CALLOUT;
11381 +#if (LINUX_VERSION_CODE >= 131343)
11382 + callout_driver.read_proc = 0;
11383 + callout_driver.proc_entry = 0;
11384 +#endif
11385 +
11386 + if (tty_register_driver(&serial_driver))
11387 + panic("Couldn't register serial driver\n");
11388 + if (tty_register_driver(&callout_driver))
11389 + panic("Couldn't register callout driver\n");
11390 +
11391 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
11392 + state->magic = SSTATE_MAGIC;
11393 + state->line = i;
11394 + state->type = PORT_UNKNOWN;
11395 + state->custom_divisor = 0;
11396 + state->close_delay = 5*HZ/10;
11397 + state->closing_wait = 30*HZ;
11398 + state->callout_termios = callout_driver.init_termios;
11399 + state->normal_termios = serial_driver.init_termios;
11400 + state->icount.cts = state->icount.dsr =
11401 + state->icount.rng = state->icount.dcd = 0;
11402 + state->icount.rx = state->icount.tx = 0;
11403 + state->icount.frame = state->icount.parity = 0;
11404 + state->icount.overrun = state->icount.brk = 0;
11405 + state->irq = irq_cannonicalize(state->irq);
11406 + if (state->hub6)
11407 + state->io_type = SERIAL_IO_HUB6;
11408 + if (state->port && check_region(state->port,8))
11409 + continue;
11410 +#ifdef CONFIG_MCA
11411 + if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
11412 + continue;
11413 +#endif
11414 + if (state->flags & ASYNC_BOOT_AUTOCONF)
11415 + autoconfig(state);
11416 + }
11417 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
11418 + if (state->type == PORT_UNKNOWN)
11419 + continue;
11420 + if ( (state->flags & ASYNC_BOOT_AUTOCONF)
11421 + && (state->flags & ASYNC_AUTO_IRQ)
11422 + && (state->port != 0 || state->iomem_base != 0))
11423 + state->irq = detect_uart_irq(state);
11424 + if (state->io_type == SERIAL_IO_MEM) {
11425 + printk(KERN_INFO"ttyS%02d%s at 0x%p (irq = %d) is a %s\n",
11426 + state->line + SERIAL_DEV_OFFSET,
11427 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
11428 + state->iomem_base, state->irq,
11429 + uart_config[state->type].name);
11430 + }
11431 + else {
11432 + printk(KERN_INFO "ttyS%02d%s at 0x%04lx (irq = %d) is a %s\n",
11433 + state->line + SERIAL_DEV_OFFSET,
11434 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
11435 + state->port, state->irq,
11436 + uart_config[state->type].name);
11437 + }
11438 + tty_register_devfs(&serial_driver, 0,
11439 + serial_driver.minor_start + state->line);
11440 + tty_register_devfs(&callout_driver, 0,
11441 + callout_driver.minor_start + state->line);
11442 + }
11443 +#ifdef ENABLE_SERIAL_PCI
11444 + probe_serial_pci();
11445 +#endif
11446 +#ifdef ENABLE_SERIAL_PNP
11447 + probe_serial_pnp();
11448 +#endif
11449 + return 0;
11450 +}
11451 +
11452 +/*
11453 + * This is for use by architectures that know their serial console
11454 + * attributes only at run time. Not to be invoked after rs_init().
11455 + */
11456 +int __init early_serial_setup(struct serial_struct *req)
11457 +{
11458 + int i = req->line;
11459 +
11460 + if (i >= NR_IRQS)
11461 + return(-ENOENT);
11462 + rs_table[i].magic = 0;
11463 + rs_table[i].baud_base = req->baud_base;
11464 + rs_table[i].port = req->port;
11465 + if (HIGH_BITS_OFFSET)
11466 + rs_table[i].port += (unsigned long) req->port_high <<
11467 + HIGH_BITS_OFFSET;
11468 + rs_table[i].irq = req->irq;
11469 + rs_table[i].flags = req->flags;
11470 + rs_table[i].close_delay = req->close_delay;
11471 + rs_table[i].io_type = req->io_type;
11472 + rs_table[i].hub6 = req->hub6;
11473 + rs_table[i].iomem_base = req->iomem_base;
11474 + rs_table[i].iomem_reg_shift = req->iomem_reg_shift;
11475 + rs_table[i].type = req->type;
11476 + rs_table[i].xmit_fifo_size = req->xmit_fifo_size;
11477 + rs_table[i].custom_divisor = req->custom_divisor;
11478 + rs_table[i].closing_wait = req->closing_wait;
11479 + return(0);
11480 +}
11481 +
11482 +/*
11483 + * register_serial and unregister_serial allows for 16x50 serial ports to be
11484 + * configured at run-time, to support PCMCIA modems.
11485 + */
11486 +
11487 +/**
11488 + * register_serial - configure a 16x50 serial port at runtime
11489 + * @req: request structure
11490 + *
11491 + * Configure the serial port specified by the request. If the
11492 + * port exists and is in use an error is returned. If the port
11493 + * is not currently in the table it is added.
11494 + *
11495 + * The port is then probed and if neccessary the IRQ is autodetected
11496 + * If this fails an error is returned.
11497 + *
11498 + * On success the port is ready to use and the line number is returned.
11499 + */
11500 +
11501 +int register_serial(struct serial_struct *req)
11502 +{
11503 + int i;
11504 + unsigned long flags;
11505 + struct serial_state *state;
11506 + struct async_struct *info;
11507 + unsigned long port;
11508 +
11509 + port = req->port;
11510 + if (HIGH_BITS_OFFSET)
11511 + port += (unsigned long) req->port_high << HIGH_BITS_OFFSET;
11512 +
11513 + save_flags(flags); cli();
11514 + for (i = 0; i < NR_PORTS; i++) {
11515 + if ((rs_table[i].port == port) &&
11516 + (rs_table[i].iomem_base == req->iomem_base))
11517 + break;
11518 + }
11519 +#ifdef __i386__
11520 + if (i == NR_PORTS) {
11521 + for (i = 4; i < NR_PORTS; i++)
11522 + if ((rs_table[i].type == PORT_UNKNOWN) &&
11523 + (rs_table[i].count == 0))
11524 + break;
11525 + }
11526 +#endif
11527 + if (i == NR_PORTS) {
11528 + for (i = 0; i < NR_PORTS; i++)
11529 + if ((rs_table[i].type == PORT_UNKNOWN) &&
11530 + (rs_table[i].count == 0))
11531 + break;
11532 + }
11533 + if (i == NR_PORTS) {
11534 + restore_flags(flags);
11535 + return -1;
11536 + }
11537 + state = &rs_table[i];
11538 + if (rs_table[i].count) {
11539 + restore_flags(flags);
11540 + printk("Couldn't configure serial #%d (port=%ld,irq=%d): "
11541 + "device already open\n", i, port, req->irq);
11542 + return -1;
11543 + }
11544 + state->irq = req->irq;
11545 + state->port = port;
11546 + state->flags = req->flags;
11547 + state->io_type = req->io_type;
11548 + state->iomem_base = req->iomem_base;
11549 + state->iomem_reg_shift = req->iomem_reg_shift;
11550 + if (req->baud_base)
11551 + state->baud_base = req->baud_base;
11552 + if ((info = state->info) != NULL) {
11553 + info->port = port;
11554 + info->flags = req->flags;
11555 + info->io_type = req->io_type;
11556 + info->iomem_base = req->iomem_base;
11557 + info->iomem_reg_shift = req->iomem_reg_shift;
11558 + }
11559 + autoconfig(state);
11560 + if (state->type == PORT_UNKNOWN) {
11561 + restore_flags(flags);
11562 + printk("register_serial(): autoconfig failed\n");
11563 + return -1;
11564 + }
11565 + restore_flags(flags);
11566 +
11567 + if ((state->flags & ASYNC_AUTO_IRQ) && CONFIGURED_SERIAL_PORT(state))
11568 + state->irq = detect_uart_irq(state);
11569 +
11570 + printk(KERN_INFO "ttyS%02d at %s 0x%04lx (irq = %d) is a %s\n",
11571 + state->line + SERIAL_DEV_OFFSET,
11572 + state->iomem_base ? "iomem" : "port",
11573 + state->iomem_base ? (unsigned long)state->iomem_base :
11574 + state->port, state->irq, uart_config[state->type].name);
11575 + tty_register_devfs(&serial_driver, 0,
11576 + serial_driver.minor_start + state->line);
11577 + tty_register_devfs(&callout_driver, 0,
11578 + callout_driver.minor_start + state->line);
11579 + return state->line + SERIAL_DEV_OFFSET;
11580 +}
11581 +
11582 +/**
11583 + * unregister_serial - deconfigure a 16x50 serial port
11584 + * @line: line to deconfigure
11585 + *
11586 + * The port specified is deconfigured and its resources are freed. Any
11587 + * user of the port is disconnected as if carrier was dropped. Line is
11588 + * the port number returned by register_serial().
11589 + */
11590 +
11591 +void unregister_serial(int line)
11592 +{
11593 + unsigned long flags;
11594 + struct serial_state *state = &rs_table[line];
11595 +
11596 + save_flags(flags); cli();
11597 + if (state->info && state->info->tty)
11598 + tty_hangup(state->info->tty);
11599 + state->type = PORT_UNKNOWN;
11600 + printk(KERN_INFO "ttyS%02d unloaded\n", state->line);
11601 + /* These will be hidden, because they are devices that will no longer
11602 + * be available to the system. (ie, PCMCIA modems, once ejected)
11603 + */
11604 + tty_unregister_devfs(&serial_driver,
11605 + serial_driver.minor_start + state->line);
11606 + tty_unregister_devfs(&callout_driver,
11607 + callout_driver.minor_start + state->line);
11608 + restore_flags(flags);
11609 +}
11610 +
11611 +static void __exit rs_fini(void)
11612 +{
11613 + unsigned long flags;
11614 + int e1, e2;
11615 + int i;
11616 + struct async_struct *info;
11617 +
11618 + /* printk("Unloading %s: version %s\n", serial_name, serial_version); */
11619 + del_timer_sync(&serial_timer);
11620 + save_flags(flags); cli();
11621 + remove_bh(SERIAL_BH);
11622 + if ((e1 = tty_unregister_driver(&serial_driver)))
11623 + printk("serial: failed to unregister serial driver (%d)\n",
11624 + e1);
11625 + if ((e2 = tty_unregister_driver(&callout_driver)))
11626 + printk("serial: failed to unregister callout driver (%d)\n",
11627 + e2);
11628 + restore_flags(flags);
11629 +
11630 + for (i = 0; i < NR_PORTS; i++) {
11631 + if ((info = rs_table[i].info)) {
11632 + rs_table[i].info = NULL;
11633 + kfree(info);
11634 + }
11635 + if ((rs_table[i].type != PORT_UNKNOWN) && rs_table[i].port) {
11636 +#ifdef CONFIG_SERIAL_RSA
11637 + if (rs_table[i].type == PORT_RSA)
11638 + release_region(rs_table[i].port +
11639 + UART_RSA_BASE, 16);
11640 + else
11641 +#endif
11642 + release_region(rs_table[i].port, 8);
11643 + }
11644 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
11645 + if (rs_table[i].iomem_base)
11646 + iounmap(rs_table[i].iomem_base);
11647 +#endif
11648 + }
11649 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
11650 + for (i=0; i < NR_PCI_BOARDS; i++) {
11651 + struct pci_board_inst *brd = &serial_pci_board[i];
11652 +
11653 + if (serial_pci_board[i].dev == 0)
11654 + continue;
11655 + if (brd->board.init_fn)
11656 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
11657 + if (DEACTIVATE_FUNC(brd->dev))
11658 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
11659 + }
11660 +#endif
11661 + if (tmp_buf) {
11662 + unsigned long pg = (unsigned long) tmp_buf;
11663 + tmp_buf = NULL;
11664 + free_page(pg);
11665 + }
11666 +
11667 +#ifdef ENABLE_SERIAL_PCI
11668 + if (serial_pci_driver.name[0])
11669 + pci_unregister_driver (&serial_pci_driver);
11670 +#endif
11671 +}
11672 +
11673 +module_init(rs_init);
11674 +module_exit(rs_fini);
11675 +MODULE_DESCRIPTION("Standard/generic (dumb) serial driver");
11676 +MODULE_AUTHOR("Theodore Ts'o <tytso@mit.edu>");
11677 +MODULE_LICENSE("GPL");
11678 +
11679 +
11680 +/*
11681 + * ------------------------------------------------------------
11682 + * Serial console driver
11683 + * ------------------------------------------------------------
11684 + */
11685 +#ifdef CONFIG_SERIAL_CONSOLE
11686 +
11687 +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
11688 +
11689 +static struct async_struct async_sercons;
11690 +
11691 +/*
11692 + * Wait for transmitter & holding register to empty
11693 + */
11694 +static inline void wait_for_xmitr(struct async_struct *info)
11695 +{
11696 + unsigned int status, tmout = 1000000;
11697 +
11698 + do {
11699 + status = serial_in(info, UART_LSR);
11700 +
11701 + if (status & UART_LSR_BI)
11702 + lsr_break_flag = UART_LSR_BI;
11703 +
11704 + if (--tmout == 0)
11705 + break;
11706 + } while((status & BOTH_EMPTY) != BOTH_EMPTY);
11707 +
11708 + /* Wait for flow control if necessary */
11709 + if (info->flags & ASYNC_CONS_FLOW) {
11710 + tmout = 1000000;
11711 + while (--tmout &&
11712 + ((serial_in(info, UART_MSR) & UART_MSR_CTS) == 0));
11713 + }
11714 +}
11715 +
11716 +
11717 +/*
11718 + * Print a string to the serial port trying not to disturb
11719 + * any possible real use of the port...
11720 + *
11721 + * The console must be locked when we get here.
11722 + */
11723 +static void serial_console_write(struct console *co, const char *s,
11724 + unsigned count)
11725 +{
11726 + static struct async_struct *info = &async_sercons;
11727 + int ier;
11728 + unsigned i;
11729 +
11730 + /*
11731 + * First save the IER then disable the interrupts
11732 + */
11733 + ier = serial_in(info, UART_IER);
11734 + serial_out(info, UART_IER, 0x00);
11735 +
11736 + /*
11737 + * Now, do each character
11738 + */
11739 + for (i = 0; i < count; i++, s++) {
11740 + wait_for_xmitr(info);
11741 +
11742 + /*
11743 + * Send the character out.
11744 + * If a LF, also do CR...
11745 + */
11746 + serial_out(info, UART_TX, *s);
11747 + if (*s == 10) {
11748 + wait_for_xmitr(info);
11749 + serial_out(info, UART_TX, 13);
11750 + }
11751 + }
11752 +
11753 + /*
11754 + * Finally, Wait for transmitter & holding register to empty
11755 + * and restore the IER
11756 + */
11757 + wait_for_xmitr(info);
11758 + serial_out(info, UART_IER, ier);
11759 +}
11760 +
11761 +static kdev_t serial_console_device(struct console *c)
11762 +{
11763 + return MKDEV(TTY_MAJOR, 64 + c->index);
11764 +}
11765 +
11766 +/*
11767 + * Setup initial baud/bits/parity/flow control. We do two things here:
11768 + * - construct a cflag setting for the first rs_open()
11769 + * - initialize the serial port
11770 + * Return non-zero if we didn't find a serial port.
11771 + */
11772 +static int __init serial_console_setup(struct console *co, char *options)
11773 +{
11774 + static struct async_struct *info;
11775 + struct serial_state *state;
11776 + unsigned cval;
11777 + int baud = 9600;
11778 + int bits = 8;
11779 + int parity = 'n';
11780 + int doflow = 0;
11781 + int cflag = CREAD | HUPCL | CLOCAL;
11782 + int quot = 0;
11783 + char *s;
11784 +
11785 + if (options) {
11786 + baud = simple_strtoul(options, NULL, 10);
11787 + s = options;
11788 + while(*s >= '0' && *s <= '9')
11789 + s++;
11790 + if (*s) parity = *s++;
11791 + if (*s) bits = *s++ - '0';
11792 + if (*s) doflow = (*s++ == 'r');
11793 + }
11794 +
11795 + /*
11796 + * Now construct a cflag setting.
11797 + */
11798 + switch(baud) {
11799 + case 1200:
11800 + cflag |= B1200;
11801 + break;
11802 + case 2400:
11803 + cflag |= B2400;
11804 + break;
11805 + case 4800:
11806 + cflag |= B4800;
11807 + break;
11808 + case 19200:
11809 + cflag |= B19200;
11810 + break;
11811 + case 38400:
11812 + cflag |= B38400;
11813 + break;
11814 + case 57600:
11815 + cflag |= B57600;
11816 + break;
11817 + case 115200:
11818 + cflag |= B115200;
11819 + break;
11820 + case 9600:
11821 + default:
11822 + cflag |= B9600;
11823 + /*
11824 + * Set this to a sane value to prevent a divide error
11825 + */
11826 + baud = 9600;
11827 + break;
11828 + }
11829 + switch(bits) {
11830 + case 7:
11831 + cflag |= CS7;
11832 + break;
11833 + default:
11834 + case 8:
11835 + cflag |= CS8;
11836 + break;
11837 + }
11838 + switch(parity) {
11839 + case 'o': case 'O':
11840 + cflag |= PARODD;
11841 + break;
11842 + case 'e': case 'E':
11843 + cflag |= PARENB;
11844 + break;
11845 + }
11846 + co->cflag = cflag;
11847 +
11848 + /*
11849 + * Divisor, bytesize and parity
11850 + */
11851 + state = rs_table + co->index;
11852 + if (doflow)
11853 + state->flags |= ASYNC_CONS_FLOW;
11854 + info = &async_sercons;
11855 + info->magic = SERIAL_MAGIC;
11856 + info->state = state;
11857 + info->port = state->port;
11858 + info->flags = state->flags;
11859 +#ifdef CONFIG_HUB6
11860 + info->hub6 = state->hub6;
11861 +#endif
11862 + info->io_type = state->io_type;
11863 + info->iomem_base = state->iomem_base;
11864 + info->iomem_reg_shift = state->iomem_reg_shift;
11865 + quot = state->baud_base / baud;
11866 + cval = cflag & (CSIZE | CSTOPB);
11867 +#if defined(__powerpc__) || defined(__alpha__)
11868 + cval >>= 8;
11869 +#else /* !__powerpc__ && !__alpha__ */
11870 + cval >>= 4;
11871 +#endif /* !__powerpc__ && !__alpha__ */
11872 + if (cflag & PARENB)
11873 + cval |= UART_LCR_PARITY;
11874 + if (!(cflag & PARODD))
11875 + cval |= UART_LCR_EPAR;
11876 +
11877 + /*
11878 + * Disable UART interrupts, set DTR and RTS high
11879 + * and set speed.
11880 + */
11881 + serial_out(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
11882 + serial_out(info, UART_DLL, quot & 0xff); /* LS of divisor */
11883 + serial_out(info, UART_DLM, quot >> 8); /* MS of divisor */
11884 + serial_out(info, UART_LCR, cval); /* reset DLAB */
11885 + serial_out(info, UART_IER, 0);
11886 + serial_out(info, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
11887 +
11888 + /*
11889 + * If we read 0xff from the LSR, there is no UART here.
11890 + */
11891 + if (serial_in(info, UART_LSR) == 0xff)
11892 + return -1;
11893 +
11894 + return 0;
11895 +}
11896 +
11897 +static struct console sercons = {
11898 + name: "ttyS",
11899 + write: serial_console_write,
11900 + device: serial_console_device,
11901 + setup: serial_console_setup,
11902 + flags: CON_PRINTBUFFER,
11903 + index: -1,
11904 +};
11905 +
11906 +/*
11907 + * Register console.
11908 + */
11909 +void __init serial_console_init(void)
11910 +{
11911 + register_console(&sercons);
11912 +}
11913 +#endif
11914 +
11915 +/*
11916 + Local variables:
11917 + compile-command: "gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing -pipe -fno-strength-reduce -march=i586 -DMODULE -DMODVERSIONS -include ../../include/linux/modversions.h -DEXPORT_SYMTAB -c serial.c"
11918 + End:
11919 +*/
11920 diff -urN linux.old/drivers/char/ticfg/Makefile linux.dev/drivers/char/ticfg/Makefile
11921 --- linux.old/drivers/char/ticfg/Makefile 1970-01-01 01:00:00.000000000 +0100
11922 +++ linux.dev/drivers/char/ticfg/Makefile 2005-11-10 01:10:46.051587500 +0100
11923 @@ -0,0 +1,6 @@
11924 +
11925 +O_TARGET := ticfg.o
11926 +
11927 +obj-$(CONFIG_AR7_ADAM2) := adam2_env.o
11928 +
11929 +include $(TOPDIR)/Rules.make
11930 diff -urN linux.old/drivers/char/ticfg/adam2_env.c linux.dev/drivers/char/ticfg/adam2_env.c
11931 --- linux.old/drivers/char/ticfg/adam2_env.c 1970-01-01 01:00:00.000000000 +0100
11932 +++ linux.dev/drivers/char/ticfg/adam2_env.c 2005-11-10 01:10:46.051587500 +0100
11933 @@ -0,0 +1,85 @@
11934 +#include <linux/types.h>
11935 +#include <linux/errno.h>
11936 +#include <linux/module.h>
11937 +#include <linux/kernel.h>
11938 +#include <linux/proc_fs.h>
11939 +#include <linux/fcntl.h>
11940 +#include <linux/init.h>
11941 +
11942 +#include <asm/ar7/adam2_env.h>
11943 +
11944 +#undef ADAM2_ENV_DEBUG
11945 +
11946 +#ifdef ADAM2_ENV_DEBUG
11947 +#define DPRINTK(args...) do { printk(args); } while(0);
11948 +#else
11949 +#define DPRINTK(args...) do { } while(0);
11950 +#endif
11951 +
11952 +#define ADAM2_ENV_DIR "ticfg"
11953 +#define ADAM2_ENV_NAME "env"
11954 +
11955 +static struct proc_dir_entry *adam2_env_proc_dir;
11956 +static struct proc_dir_entry *adam2_env_proc_ent;
11957 +
11958 +static int
11959 +adam2_proc_read_env(char *page, char **start, off_t pos, int count,
11960 + int *eof, void *data)
11961 +{
11962 + int len;
11963 + t_env_var *env;
11964 +
11965 + if (pos > 0)
11966 + return 0;
11967 +
11968 + len=0;
11969 + for (env = prom_iterenv(0); env; env = prom_iterenv(env)) {
11970 + if (env->val) {
11971 + /* XXX check for page len */
11972 + len += sprintf(page + len, "%s\t%s\n",
11973 + env->name, env->val);
11974 + }
11975 + }
11976 +
11977 + *eof=1;
11978 + return len;
11979 +}
11980 +
11981 +static int __init
11982 +adam2_env_init(void)
11983 +{
11984 +
11985 + DPRINTK("%s\n", __FUNCTION__);
11986 +
11987 + adam2_env_proc_dir = proc_mkdir(ADAM2_ENV_DIR, NULL);
11988 + if (!adam2_env_proc_dir) {
11989 + printk(KERN_ERR "%s: Unable to create /proc/%s entry\n",
11990 + __FUNCTION__, ADAM2_ENV_DIR);
11991 + return -ENOMEM;
11992 + }
11993 +
11994 + adam2_env_proc_ent =
11995 + create_proc_entry(ADAM2_ENV_NAME, 0444, adam2_env_proc_dir);
11996 + if (!adam2_env_proc_ent) {
11997 + printk(KERN_ERR "%s: Unable to create /proc/%s/%s entry\n",
11998 + __FUNCTION__, ADAM2_ENV_DIR, ADAM2_ENV_NAME);
11999 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
12000 + return -ENOMEM;
12001 + }
12002 + adam2_env_proc_ent->read_proc = adam2_proc_read_env;
12003 +
12004 + return 0;
12005 +}
12006 +
12007 +static
12008 +void __exit
12009 +adam2_env_cleanup(void)
12010 +{
12011 + remove_proc_entry(ADAM2_ENV_NAME, adam2_env_proc_dir);
12012 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
12013 +}
12014 +
12015 +module_init(adam2_env_init);
12016 +module_exit(adam2_env_cleanup);
12017 +
12018 +MODULE_LICENSE("GPL");
12019 diff -urN linux.old/include/asm-mips/addrspace.h linux.dev/include/asm-mips/addrspace.h
12020 --- linux.old/include/asm-mips/addrspace.h 2002-11-29 00:53:15.000000000 +0100
12021 +++ linux.dev/include/asm-mips/addrspace.h 2005-11-10 01:14:16.400733500 +0100
12022 @@ -11,6 +11,8 @@
12023 #ifndef __ASM_MIPS_ADDRSPACE_H
12024 #define __ASM_MIPS_ADDRSPACE_H
12025
12026 +#include <linux/config.h>
12027 +
12028 /*
12029 * Configure language
12030 */
12031 @@ -102,4 +104,11 @@
12032 #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
12033 #define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a))
12034
12035 +#ifdef CONFIG_AR7_MEMORY
12036 +#define PHYS_OFFSET ((unsigned long)(CONFIG_AR7_MEMORY))
12037 +#else
12038 +#define PHYS_OFFSET (0)
12039 +#endif
12040 +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
12041 +
12042 #endif /* __ASM_MIPS_ADDRSPACE_H */
12043 diff -urN linux.old/include/asm-mips/ar7/adam2_env.h linux.dev/include/asm-mips/ar7/adam2_env.h
12044 --- linux.old/include/asm-mips/ar7/adam2_env.h 1970-01-01 01:00:00.000000000 +0100
12045 +++ linux.dev/include/asm-mips/ar7/adam2_env.h 2005-11-10 01:10:46.067588500 +0100
12046 @@ -0,0 +1,13 @@
12047 +#ifndef _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12048 +#define _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12049 +
12050 +/* Environment variable */
12051 +typedef struct {
12052 + char *name;
12053 + char *val;
12054 +} t_env_var;
12055 +
12056 +char *prom_getenv(char *);
12057 +t_env_var *prom_iterenv(t_env_var *);
12058 +
12059 +#endif /* _INCLUDE_ASM_AR7_ADAM2_ENV_H_ */
12060 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
12061 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
12062 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-11-10 01:10:46.067588500 +0100
12063 @@ -0,0 +1,33 @@
12064 +/*
12065 + * $Id$
12066 + * Copyright (C) $Date$ $Author$
12067 + *
12068 + * This program is free software; you can redistribute it and/or modify
12069 + * it under the terms of the GNU General Public License as published by
12070 + * the Free Software Foundation; either version 2 of the License, or
12071 + * (at your option) any later version.
12072 + *
12073 + * This program is distributed in the hope that it will be useful,
12074 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12075 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12076 + * GNU General Public License for more details.
12077 + *
12078 + * You should have received a copy of the GNU General Public License
12079 + * along with this program; if not, write to the Free Software
12080 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
12081 + *
12082 + */
12083 +
12084 +#ifndef _AR7_H
12085 +#define _AR7_H
12086 +
12087 +#include <asm/addrspace.h>
12088 +#include <linux/config.h>
12089 +
12090 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
12091 +
12092 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
12093 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
12094 +#define AR7_BASE_BAUD ( 3686400 / 16 )
12095 +
12096 +#endif
12097 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
12098 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
12099 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-11-10 01:10:46.067588500 +0100
12100 @@ -0,0 +1,292 @@
12101 + /*
12102 + * Nitin Dhingra, iamnd@ti.com
12103 + * Copyright (C) 2000 Texas Instruments Inc.
12104 + *
12105 + *
12106 + * ########################################################################
12107 + *
12108 + * This program is free software; you can distribute it and/or modify it
12109 + * under the terms of the GNU General Public License (Version 2) as
12110 + * published by the Free Software Foundation.
12111 + *
12112 + * This program is distributed in the hope it will be useful, but WITHOUT
12113 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12114 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12115 + * for more details.
12116 + *
12117 + * You should have received a copy of the GNU General Public License along
12118 + * with this program; if not, write to the Free Software Foundation, Inc.,
12119 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
12120 + *
12121 + * ########################################################################
12122 + *
12123 + * Defines of the Sead board specific address-MAP, registers, etc.
12124 + *
12125 + */
12126 +#ifndef _AVALANCHE_INTC_H
12127 +#define _AVALANCHE_INTC_H
12128 +
12129 +#include <linux/config.h>
12130 +
12131 +/* ----- */
12132 +
12133 +#define KSEG1_BASE 0xA0000000
12134 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
12135 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
12136 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
12137 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
12138 +
12139 +/* ----- */
12140 +
12141 +#define MIPS_EXCEPTION_OFFSET 8
12142 +
12143 +/******************************************************************************
12144 + Avalanche Interrupt number
12145 +******************************************************************************/
12146 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
12147 +
12148 +/*******************************************************************************
12149 +*Linux Interrupt number
12150 +*******************************************************************************/
12151 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
12152 +
12153 +
12154 +
12155 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
12156 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
12157 +
12158 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
12159 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
12160 +
12161 +#define AVALANCHE_INTC_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
12162 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) + \
12163 + MIPS_EXCEPTION_OFFSET)
12164 +
12165 +#if defined(CONFIG_AR7_VLYNQ)
12166 +#define AVALANCHE_INT_END_LOW_VLYNQ (AVALANCHE_INTC_END + 32)
12167 +#define AVALANCHE_INT_END_VLYNQ (AVALANCHE_INTC_END + 32 * CONFIG_AR7_VLYNQ_PORTS)
12168 +#define AVALANCHE_INT_END AVALANCHE_INT_END_VLYNQ
12169 +#else
12170 +#define AVALANCHE_INT_END AVALANCHE_INTC_END
12171 +#endif
12172 +
12173 +
12174 +/*
12175 + * Avalanche interrupt controller register base (primary)
12176 + */
12177 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
12178 +
12179 +/******************************************************************************
12180 + * Avalanche exception controller register base (secondary)
12181 + ******************************************************************************/
12182 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
12183 +
12184 +
12185 +/******************************************************************************
12186 + * Avalanche Interrupt pacing register base (secondary)
12187 + ******************************************************************************/
12188 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
12189 +
12190 +
12191 +
12192 +/******************************************************************************
12193 + * Avalanche Interrupt Channel Control register base
12194 + *****************************************************************************/
12195 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
12196 +
12197 +
12198 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
12199 +{
12200 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
12201 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
12202 + volatile unsigned long unused1; /*0x08 */
12203 + volatile unsigned long unused2; /*0x0C */
12204 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
12205 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
12206 + volatile unsigned long unused3; /*0x18 */
12207 + volatile unsigned long unused4; /*0x1C */
12208 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
12209 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
12210 + volatile unsigned long unused5; /*0x28 */
12211 + volatile unsigned long unused6; /*0x2C */
12212 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
12213 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
12214 + volatile unsigned long unused7; /* 0x38 */
12215 + volatile unsigned long unused8; /* 0x3c */
12216 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
12217 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
12218 + volatile unsigned long unused9; /* 0x48 */
12219 + volatile unsigned long unused10; /* 0x4C */
12220 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
12221 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
12222 + volatile unsigned long unused11; /* 0x58 */
12223 + volatile unsigned long unused12; /*0x5C */
12224 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
12225 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
12226 +};
12227 +
12228 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
12229 +{
12230 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
12231 + volatile unsigned long reserved; /*0x84 */
12232 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
12233 + volatile unsigned long reserved1; /*0x8c */
12234 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
12235 + volatile unsigned long reserved2; /*0x94 */
12236 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
12237 +};
12238 +struct avalanche_ipace_regs
12239 +{
12240 +
12241 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
12242 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
12243 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
12244 +};
12245 +struct avalanche_channel_int_number
12246 +{
12247 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
12248 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
12249 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
12250 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
12251 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
12252 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
12253 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
12254 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
12255 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
12256 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
12257 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
12258 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
12259 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
12260 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
12261 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
12262 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
12263 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
12264 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
12265 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
12266 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
12267 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
12268 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
12269 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
12270 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
12271 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
12272 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
12273 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
12274 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
12275 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
12276 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
12277 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
12278 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
12279 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
12280 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
12281 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
12282 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
12283 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
12284 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
12285 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
12286 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
12287 +};
12288 +
12289 +struct avalanche_interrupt_line_to_channel
12290 +{
12291 + unsigned long int_line0; /* Start of primary interrupts */
12292 + unsigned long int_line1;
12293 + unsigned long int_line2;
12294 + unsigned long int_line3;
12295 + unsigned long int_line4;
12296 + unsigned long int_line5;
12297 + unsigned long int_line6;
12298 + unsigned long int_line7;
12299 + unsigned long int_line8;
12300 + unsigned long int_line9;
12301 + unsigned long int_line10;
12302 + unsigned long int_line11;
12303 + unsigned long int_line12;
12304 + unsigned long int_line13;
12305 + unsigned long int_line14;
12306 + unsigned long int_line15;
12307 + unsigned long int_line16;
12308 + unsigned long int_line17;
12309 + unsigned long int_line18;
12310 + unsigned long int_line19;
12311 + unsigned long int_line20;
12312 + unsigned long int_line21;
12313 + unsigned long int_line22;
12314 + unsigned long int_line23;
12315 + unsigned long int_line24;
12316 + unsigned long int_line25;
12317 + unsigned long int_line26;
12318 + unsigned long int_line27;
12319 + unsigned long int_line28;
12320 + unsigned long int_line29;
12321 + unsigned long int_line30;
12322 + unsigned long int_line31;
12323 + unsigned long int_line32;
12324 + unsigned long int_line33;
12325 + unsigned long int_line34;
12326 + unsigned long int_line35;
12327 + unsigned long int_line36;
12328 + unsigned long int_line37;
12329 + unsigned long int_line38;
12330 + unsigned long int_line39;
12331 +};
12332 +
12333 +
12334 +/* Interrupt Line #'s (Sangam peripherals) */
12335 +
12336 +/*------------------------------*/
12337 +/* Sangam primary interrupts */
12338 +/*------------------------------*/
12339 +
12340 +#define UNIFIED_SECONDARY_INTERRUPT 0
12341 +#define AVALANCHE_EXT_INT_0 1
12342 +#define AVALANCHE_EXT_INT_1 2
12343 +/* Line #3 Reserved */
12344 +/* Line #4 Reserved */
12345 +#define AVALANCHE_TIMER_0_INT 5
12346 +#define AVALANCHE_TIMER_1_INT 6
12347 +#define AVALANCHE_UART0_INT 7
12348 +#define AVALANCHE_UART1_INT 8
12349 +#define AVALANCHE_PDMA_INT0 9
12350 +#define AVALANCHE_PDMA_INT1 10
12351 +/* Line #11 Reserved */
12352 +/* Line #12 Reserved */
12353 +/* Line #13 Reserved */
12354 +/* Line #14 Reserved */
12355 +#define AVALANCHE_ATM_SAR_INT 15
12356 +/* Line #16 Reserved */
12357 +/* Line #17 Reserved */
12358 +/* Line #18 Reserved */
12359 +#define AVALANCHE_MAC0_INT 19
12360 +/* Line #20 Reserved */
12361 +#define AVALANCHE_VLYNQ0_INT 21
12362 +#define AVALANCHE_CODEC_WAKE_INT 22
12363 +/* Line #23 Reserved */
12364 +#define AVALANCHE_USB_INT 24
12365 +#define AVALANCHE_VLYNQ1_INT 25
12366 +/* Line #26 Reserved */
12367 +/* Line #27 Reserved */
12368 +#define AVALANCHE_MAC1_INT 28
12369 +#define AVALANCHE_I2CM_INT 29
12370 +#define AVALANCHE_PDMA_INT2 30
12371 +#define AVALANCHE_PDMA_INT3 31
12372 +/* Line #32 Reserved */
12373 +/* Line #33 Reserved */
12374 +/* Line #34 Reserved */
12375 +/* Line #35 Reserved */
12376 +/* Line #36 Reserved */
12377 +#define AVALANCHE_VDMA_VT_RX_INT 37
12378 +#define AVALANCHE_VDMA_VT_TX_INT 38
12379 +#define AVALANCHE_ADSLSS_INT 39
12380 +
12381 +/*-----------------------------------*/
12382 +/* Sangam Secondary Interrupts */
12383 +/*-----------------------------------*/
12384 +#define PRIMARY_INTS 40
12385 +
12386 +#define EMIF_INT (7 + PRIMARY_INTS)
12387 +
12388 +
12389 +extern void avalanche_int_set(int channel, int line);
12390 +
12391 +
12392 +#endif /* _AVALANCHE_INTC_H */
12393 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
12394 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
12395 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-11-10 01:10:46.067588500 +0100
12396 @@ -0,0 +1,174 @@
12397 +#ifndef _AVALANCHE_MISC_H_
12398 +#define _AVALANCHE_MISC_H_
12399 +
12400 +typedef enum AVALANCHE_ERR_t
12401 +{
12402 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
12403 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
12404 +
12405 + /* Pointers and args */
12406 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
12407 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
12408 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
12409 +
12410 + /* Memory issues */
12411 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
12412 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
12413 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
12414 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
12415 +
12416 + /* Device issues */
12417 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
12418 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
12419 +
12420 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
12421 +
12422 +} AVALANCHE_ERR;
12423 +
12424 +/*****************************************************************************
12425 + * Reset Control Module
12426 + *****************************************************************************/
12427 +
12428 +typedef enum AVALANCHE_RESET_MODULE_tag
12429 +{
12430 + RESET_MODULE_UART0 = 0,
12431 + RESET_MODULE_UART1 = 1,
12432 + RESET_MODULE_I2C = 2,
12433 + RESET_MODULE_TIMER0 = 3,
12434 + RESET_MODULE_TIMER1 = 4,
12435 + RESET_MODULE_GPIO = 6,
12436 + RESET_MODULE_ADSLSS = 7,
12437 + RESET_MODULE_USBS = 8,
12438 + RESET_MODULE_SAR = 9,
12439 + RESET_MODULE_VDMA_VT = 11,
12440 + RESET_MODULE_FSER = 12,
12441 + RESET_MODULE_VLYNQ1 = 16,
12442 + RESET_MODULE_EMAC0 = 17,
12443 + RESET_MODULE_DMA = 18,
12444 + RESET_MODULE_BIST = 19,
12445 + RESET_MODULE_VLYNQ0 = 20,
12446 + RESET_MODULE_EMAC1 = 21,
12447 + RESET_MODULE_MDIO = 22,
12448 + RESET_MODULE_ADSLSS_DSP = 23,
12449 + RESET_MODULE_EPHY = 26
12450 +} AVALANCHE_RESET_MODULE_T;
12451 +
12452 +typedef enum AVALANCHE_RESET_CTRL_tag
12453 +{
12454 + IN_RESET = 0,
12455 + OUT_OF_RESET
12456 +} AVALANCHE_RESET_CTRL_T;
12457 +
12458 +typedef enum AVALANCHE_SYS_RST_MODE_tag
12459 +{
12460 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
12461 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
12462 +} AVALANCHE_SYS_RST_MODE_T;
12463 +
12464 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
12465 +{
12466 + HARDWARE_RESET = 0,
12467 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
12468 + WATCHDOG_RESET,
12469 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
12470 +} AVALANCHE_SYS_RESET_STATUS_T;
12471 +
12472 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
12473 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
12474 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
12475 +
12476 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
12477 +
12478 +/*****************************************************************************
12479 + * Power Control Module
12480 + *****************************************************************************/
12481 +
12482 +typedef enum AVALANCHE_POWER_CTRL_tag
12483 +{
12484 + POWER_CTRL_POWER_UP = 0,
12485 + POWER_CTRL_POWER_DOWN
12486 +} AVALANCHE_POWER_CTRL_T;
12487 +
12488 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
12489 +{
12490 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
12491 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
12492 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
12493 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
12494 +} AVALANCHE_SYS_POWER_MODE_T;
12495 +
12496 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
12497 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
12498 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
12499 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
12500 +
12501 +/*****************************************************************************
12502 + * Wakeup Control
12503 + *****************************************************************************/
12504 +
12505 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
12506 +{
12507 + WAKEUP_INT0 = 1,
12508 + WAKEUP_INT1 = 2,
12509 + WAKEUP_INT2 = 4,
12510 + WAKEUP_INT3 = 8
12511 +} AVALANCHE_WAKEUP_INTERRUPT_T;
12512 +
12513 +typedef enum TNETV1050_WAKEUP_CTRL_tag
12514 +{
12515 + WAKEUP_DISABLED = 0,
12516 + WAKEUP_ENABLED
12517 +} AVALANCHE_WAKEUP_CTRL_T;
12518 +
12519 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
12520 +{
12521 + WAKEUP_ACTIVE_HIGH = 0,
12522 + WAKEUP_ACTIVE_LOW
12523 +} AVALANCHE_WAKEUP_POLARITY_T;
12524 +
12525 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
12526 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
12527 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
12528 +
12529 +/*****************************************************************************
12530 + * GPIO Control
12531 + *****************************************************************************/
12532 +
12533 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
12534 +{
12535 + FUNCTIONAL_PIN = 0,
12536 + GPIO_PIN = 1
12537 +} AVALANCHE_GPIO_PIN_MODE_T;
12538 +
12539 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
12540 +{
12541 + GPIO_OUTPUT_PIN = 0,
12542 + GPIO_INPUT_PIN = 1
12543 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
12544 +
12545 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
12546 +
12547 +void avalanche_gpio_init(void);
12548 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
12549 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
12550 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
12551 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
12552 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
12553 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
12554 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
12555 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
12556 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
12557 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
12558 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
12559 +
12560 +unsigned int avalanche_get_chip_version_info(void);
12561 +
12562 +unsigned int avalanche_get_vbus_freq(void);
12563 +void avalanche_set_vbus_freq(unsigned int);
12564 +
12565 +
12566 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
12567 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
12568 +unsigned int avalanche_is_mdix_on_chip(void);
12569 +
12570 +#endif
12571 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
12572 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
12573 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-11-10 01:10:46.071588750 +0100
12574 @@ -0,0 +1,567 @@
12575 +/*
12576 + * $Id$
12577 + * Avalanche Register Descriptions
12578 + *
12579 + * Jeff Harrell, jharrell@ti.com
12580 + * 2000 (c) Texas Instruments Inc.
12581 + */
12582 +
12583 +#ifndef __AVALANCHE_REGS_H
12584 +#define __AVALANCHE_REGS_H
12585 +
12586 +#include <asm/addrspace.h>
12587 +#include <linux/config.h>
12588 +
12589 +/*----------------------------------------*/
12590 +/* Base offsets within the Avalanche ASIC */
12591 +/*----------------------------------------*/
12592 +
12593 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
12594 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
12595 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
12596 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
12597 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
12598 +#define DES_BASE (KSEG1ADDR(0x08600000))
12599 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
12600 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
12601 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
12602 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
12603 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
12604 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
12605 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
12606 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
12607 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
12608 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
12609 +#define I2C_BASE (KSEG1ADDR(0x08611000))
12610 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
12611 +#define USB_BASE (KSEG1ADDR(0x08611200))
12612 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
12613 +#define DMA_BASE (KSEG1ADDR(0x08611400))
12614 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
12615 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
12616 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
12617 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
12618 +
12619 +/*---------------------------------*/
12620 +/* Device ID, chip version number */
12621 +/*---------------------------------*/
12622 +
12623 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
12624 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
12625 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
12626 +
12627 +/*----------------------------------*/
12628 +/* Reset Control VW changed to ptrs */
12629 +/*----------------------------------*/
12630 +
12631 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
12632 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
12633 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
12634 +
12635 +/* reset control bits */
12636 +
12637 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
12638 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
12639 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
12640 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
12641 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
12642 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
12643 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
12644 +/*
12645 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12646 + If you reset the GPIO interface all of the directions (i/o) of the UART B
12647 + interface pins are inputs and must be reconfigured so as not to lose the
12648 + serial console interface
12649 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12650 +*/
12651 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
12652 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
12653 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
12654 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
12655 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
12656 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
12657 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
12658 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
12659 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
12660 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
12661 +
12662 +/*----------------------*/
12663 +/* Physical interfaces */
12664 +/*----------------------*/
12665 +
12666 +/* Phy loopback */
12667 +#define PHY_LOOPBACK 1
12668 +
12669 +
12670 +/* Phy 0 */
12671 +#define PHY0BASE (PHY_BASE)
12672 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
12673 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
12674 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
12675 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
12676 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
12677 +
12678 +
12679 +/* Phy 1 */
12680 +
12681 +#define PHY1BASE (PHY_BASE + 0x100000)
12682 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
12683 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
12684 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
12685 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
12686 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
12687 +
12688 +/* Phy 2 */
12689 +
12690 +#define PHY2BASE (PHY_BASE + 0x200000)
12691 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
12692 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
12693 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
12694 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
12695 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
12696 +
12697 +/*-------------------*/
12698 +/* Avalanche ATM SAR */
12699 +/*-------------------*/
12700 +
12701 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
12702 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
12703 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
12704 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
12705 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
12706 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
12707 +
12708 +/* Transmit completion ring registers */
12709 +
12710 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
12711 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
12712 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
12713 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
12714 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
12715 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
12716 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
12717 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
12718 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
12719 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
12720 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
12721 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
12722 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
12723 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
12724 +
12725 +/* Transmit Queue Packet registers */
12726 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
12727 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
12728 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
12729 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
12730 +/* Receive completion ring registers */
12731 +
12732 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
12733 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
12734 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
12735 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
12736 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
12737 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
12738 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
12739 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
12740 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
12741 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
12742 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
12743 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
12744 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
12745 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
12746 +
12747 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
12748 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
12749 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
12750 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
12751 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
12752 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
12753 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
12754 +
12755 +
12756 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
12757 +
12758 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
12759 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
12760 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
12761 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
12762 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
12763 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
12764 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
12765 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
12766 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
12767 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
12768 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
12769 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
12770 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
12771 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
12772 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
12773 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
12774 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
12775 +
12776 +
12777 +/*
12778 +
12779 +#define OAM_CPID_ADD 0xa30104e0
12780 +
12781 +#define OAM_LLID_ADD 0xa30104f0
12782 +
12783 +#define OAM_LLID_VAL 0xffffffff
12784 +
12785 +#define OAM_CORR_TAG 0xa3010500
12786 +
12787 +#define OAM_FAR_COUNT_ADD 0xa3010520
12788 +
12789 +#define OAM_NEAR_COUNT_ADD 0xa3010540
12790 +
12791 +#define OAM_CONFIG_REG_ADD 0xa3000018
12792 +*/
12793 +
12794 +
12795 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
12796 +
12797 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
12798 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
12799 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
12800 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
12801 +
12802 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
12803 +
12804 +
12805 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
12806 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
12807 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
12808 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
12809 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
12810 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
12811 +
12812 +/*------------------------------------------*/
12813 +/* DSL Interface */
12814 +/*------------------------------------------*/
12815 +
12816 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
12817 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
12818 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
12819 +
12820 +/* Fast */
12821 +
12822 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
12823 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
12824 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
12825 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
12826 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
12827 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
12828 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
12829 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
12830 +
12831 +/* Interleaved */
12832 +
12833 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
12834 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
12835 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
12836 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
12837 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
12838 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
12839 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
12840 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
12841 +
12842 +/*------------------------------------------*/
12843 +/* Broadband I/F */
12844 +/*------------------------------------------*/
12845 +
12846 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
12847 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
12848 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
12849 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
12850 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
12851 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
12852 +
12853 +#define AVBBIF_DISABLED 0x0
12854 +#define AVBBIF_LBT4040_INT 0x1
12855 +#define AVBBIF_XBUS 0x2
12856 +#define AVBBIF_LBT4040_EXT 0x4
12857 +
12858 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
12859 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
12860 +#define AVBBIF_TRANS_MASK 0xff000000
12861 +/*------------------------------------------*/
12862 +/* GPIO I/F */
12863 +/*------------------------------------------*/
12864 +
12865 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
12866 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
12867 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
12868 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
12869 +
12870 +#define GPIO_0 (1<<21)
12871 +#define GPIO_1 (1<<22)
12872 +#define GPIO_2 (1<<23)
12873 +#define GPIO_3 (1<<24)
12874 +#define EINT_1 (1<<18)
12875 +
12876 +/*
12877 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12878 + If you reset the GPIO interface all of the directions (i/o) of the UART B
12879 + interface pins are inputs and must be reconfigured so as not to lose the
12880 + serial console interface
12881 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
12882 +*/
12883 +
12884 +/*------------------------------------------*/
12885 +/* CLK_CTRL */
12886 +/*------------------------------------------*/
12887 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
12888 +
12889 +#define PCLK_0_HALF_VBUS (0<<16)
12890 +#define PCLK_EQ_INPUT (1<<16)
12891 +#define BBIF_CLK_HALF_VBUS (0<<17)
12892 +#define BBIF_CLK_EQ_VBUS (1<<17)
12893 +#define BBIF_CLK_EQ_BBCLK (3<<17)
12894 +#define DSP_MODCLK_DSPCLKI (0<<20)
12895 +#define DSP_MODCLK_REFCLKI (1<<20)
12896 +#define USB_CLK_EQ_USBCLKI (0<<21)
12897 +#define USB_CLK_EQ_REFCLKI (1<<21)
12898 +
12899 +/*------------------------------------------*/
12900 +/* PCI Control Registers */
12901 +/*------------------------------------------*/
12902 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
12903 +#define PCIC_CONTROL_CFG_DONE (1<<0)
12904 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
12905 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
12906 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
12907 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
12908 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
12909 +#define PCIC_CONTROL_MEM_MASK (1<<6)
12910 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
12911 +#define PCIC_CONTROL_IO_MASK (1<<8)
12912 +/* PCIC_CONTROL_RESERVED (1<<9) */
12913 +#define PCIC_CONTROL_BASE0_EN (1<<10)
12914 +#define PCIC_CONTROL_BASE1_EN (1<<11)
12915 +#define PCIC_CONTROL_BASE2_EN (1<<12)
12916 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
12917 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
12918 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
12919 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
12920 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
12921 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
12922 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
12923 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
12924 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
12925 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
12926 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
12927 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
12928 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
12929 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
12930 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
12931 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
12932 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
12933 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
12934 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
12935 +#define PCIC_INT_CLEAR_PM (1<<0)
12936 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
12937 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
12938 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
12939 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
12940 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
12941 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
12942 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
12943 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
12944 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
12945 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
12946 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
12947 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
12948 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
12949 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
12950 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
12951 +#define PCIC_INT_EN_AVAL_PM (1<<0)
12952 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
12953 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
12954 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
12955 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
12956 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
12957 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
12958 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
12959 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
12960 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
12961 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
12962 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
12963 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
12964 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
12965 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
12966 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
12967 +#define PCIC_INT_EN_PCI_PM (1<<0)
12968 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
12969 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
12970 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
12971 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
12972 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
12973 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
12974 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
12975 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
12976 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
12977 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
12978 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
12979 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
12980 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
12981 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
12982 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
12983 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
12984 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
12985 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
12986 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
12987 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
12988 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
12989 +/* PCIC_PM_CTL_RESERVED (1<<2) */
12990 +/* PCIC_PM_CTL_RESERVED (1<<3) */
12991 +/* PCIC_PM_CTL_RESERVED (1<<4) */
12992 +/* PCIC_PM_CTL_RESERVED (1<<5) */
12993 +/* PCIC_PM_CTL_RESERVED (1<<6) */
12994 +/* PCIC_PM_CTL_RESERVED (1<<7) */
12995 +/* PCIC_PM_CTL_RESERVED (1<<8) */
12996 +/* PCIC_PM_CTL_RESERVED (1<<9) */
12997 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
12998 +#define PCIC_PM_CTL_PMEIN (1<<11)
12999 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
13000 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
13001 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
13002 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
13003 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
13004 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
13005 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
13006 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
13007 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
13008 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
13009 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
13010 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
13011 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
13012 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
13013 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
13014 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
13015 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
13016 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
13017 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
13018 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
13019 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
13020 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
13021 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
13022 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
13023 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
13024 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
13025 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
13026 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
13027 +
13028 +/*------------------------------------------*/
13029 +/* IIC_INTERFACE */
13030 +/*------------------------------------------*/
13031 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
13032 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
13033 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
13034 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
13035 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
13036 +
13037 +#define I2CWRITE 0x200
13038 +#define I2CREAD 0x300
13039 +#define I2C_END_BURST 0x400
13040 +
13041 +/* read bits */
13042 +#define I2C_READ_ERROR 0x8000
13043 +#define I2C_READ_COMPLETE 0x4000
13044 +#define I2C_READ_BUSY 0x2000
13045 +
13046 +/* device types */
13047 +#define I2C_IO_EXPANDER 0x2
13048 +#define I2C_RTC 0xd
13049 +
13050 +/* device Addresses on I2C bus (EVM3) */
13051 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
13052 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
13053 +#define EVM3_RTC_I2C_ADDR 0x0
13054 +
13055 +/*------------------------------------------*/
13056 +/* Ethernet MAC register offset definitions */
13057 +/*------------------------------------------*/
13058 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
13059 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
13060 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
13061 +
13062 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13063 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
13064 +
13065 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
13066 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
13067 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
13068 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
13069 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
13070 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
13071 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
13072 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
13073 +
13074 +
13075 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
13076 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
13077 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
13078 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
13079 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
13080 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
13081 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
13082 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
13083 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
13084 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
13085 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
13086 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
13087 +
13088 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
13089 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
13090 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
13091 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
13092 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
13093 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
13094 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
13095 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
13096 +
13097 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
13098 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
13099 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
13100 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
13101 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
13102 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
13103 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
13104 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
13105 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
13106 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
13107 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
13108 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
13109 +
13110 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
13111 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
13112 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
13113 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
13114 +
13115 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
13116 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
13117 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
13118 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
13119 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
13120 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
13121 +
13122 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13123 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
13124 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
13125 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
13126 +
13127 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
13128 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
13129 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
13130 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
13131 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
13132 +
13133 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
13134 +
13135 +#endif __AVALANCHE_REGS_H
13136 +
13137 +
13138 +
13139 +
13140 +
13141 +
13142 diff -urN linux.old/include/asm-mips/ar7/avalanche_types.h linux.dev/include/asm-mips/ar7/avalanche_types.h
13143 --- linux.old/include/asm-mips/ar7/avalanche_types.h 1970-01-01 01:00:00.000000000 +0100
13144 +++ linux.dev/include/asm-mips/ar7/avalanche_types.h 2005-11-10 01:10:46.071588750 +0100
13145 @@ -0,0 +1,126 @@
13146 +/*------------------------------------------------------------------------------------------*\
13147 +\*------------------------------------------------------------------------------------------*/
13148 +#ifndef _avalanche_types_h_
13149 +#define _avalanche_types_h_
13150 +
13151 +/*--- #include <asm/avalanche/generic/hal_modules/haltypes.h> ---*/
13152 +#ifndef TRUE
13153 +#define TRUE 1
13154 +#endif
13155 +#ifndef FALSE
13156 +#define FALSE 0
13157 +#endif
13158 +#ifndef NULL
13159 +#define NULL (void *)0
13160 +#endif
13161 +
13162 +/*------------------------------------------------------------------------------------------*\
13163 + * Typen für Texas GPL Module
13164 +\*------------------------------------------------------------------------------------------*/
13165 +#ifndef __UINT8_T__
13166 +typedef unsigned char UINT8;
13167 +#define __UINT8_T__
13168 +#endif
13169 +
13170 +#ifndef __UCHAR_T__
13171 +typedef unsigned char UCHAR;
13172 +#define __UCHAR_T__
13173 +#endif
13174 +
13175 +#ifndef __INT8_T__
13176 +typedef signed char INT8;
13177 +#define __INT8_T__
13178 +#endif
13179 +
13180 +#ifndef __UINT16_T__
13181 +typedef unsigned short UINT16;
13182 +#define __UINT16_T__
13183 +#endif
13184 +
13185 +#ifndef __USHORT_T__
13186 +typedef unsigned short USHORT;
13187 +#define __USHORT_T__
13188 +#endif
13189 +
13190 +#ifndef __INT16_T__
13191 +typedef signed short INT16;
13192 +#define __INT16_T__
13193 +#endif
13194 +
13195 +#ifndef __UINT32_T__
13196 +typedef unsigned int UINT32;
13197 +#define __UINT32_T__
13198 +#endif
13199 +
13200 +#ifndef __UINT_T__
13201 +typedef unsigned int UINT;
13202 +#define __UINT_T__
13203 +#endif
13204 +
13205 +#ifndef __INT32_T__
13206 +typedef signed int INT32;
13207 +#define __INT32_T__
13208 +#endif
13209 +
13210 +#ifndef __ULONG_T__
13211 +typedef unsigned long ULONG;
13212 +#define __ULONG_T__
13213 +#endif
13214 +
13215 +#ifndef __BOOL_T__
13216 +typedef int BOOL;
13217 +#define __BOOL_T__
13218 +#endif
13219 +
13220 +#ifndef __STATUS_T__
13221 +typedef int STATUS;
13222 +#define __STATUS_T__
13223 +#endif
13224 +
13225 +/*------------------------------------------------------------------------------------------*\
13226 +\*------------------------------------------------------------------------------------------*/
13227 +typedef void (*p_vlynq_intr_cntrl_isr_t)(void *,void *,void *);
13228 +typedef INT32 (*p_vlynq_interrupt_vector_set_t)(void *, UINT32, UINT32, INT32, INT32, INT32);
13229 +typedef INT32 (*p_vlynq_interrupt_vector_cntl_t)(void *, UINT32, INT32, UINT32);
13230 +typedef UINT32 (*p_vlynq_interrupt_get_count_t)(void *, UINT32);
13231 +typedef INT32 (*p_vlynq_install_isr_t)(void *, UINT32, p_vlynq_intr_cntrl_isr_t, void *, void *, void *);
13232 +typedef INT32 (*p_vlynq_uninstall_isr_t)(void *, UINT32, void *, void *, void *);
13233 +typedef void (*p_vlynq_root_isr_t)(void *);
13234 +typedef void (*p_vlynq_delay_t)(UINT32);
13235 +typedef INT32 (*p_vlynq_interrupt_vector_map_t)(void *, INT32, UINT32, UINT32);
13236 +typedef INT32 (*p_vlynq_interrupt_set_polarity_t)(void *, INT32, UINT32, INT32);
13237 +typedef INT32 (*p_vlynq_interrupt_get_polarity_t)(void *, INT32, UINT32);
13238 +typedef INT32 (*p_vlynq_interrupt_set_type_t)(void *, INT32, UINT32, INT32);
13239 +typedef INT32 (*p_vlynq_interrupt_get_type_t)(void *, INT32, UINT32);
13240 +typedef INT32 (*p_vlynq_interrupt_enable_t)(void *, INT32, UINT32);
13241 +typedef INT32 (*p_vlynq_interrupt_disable_t)(void *, INT32, UINT32);
13242 +
13243 +/*------------------------------------------------------------------------------------------*\
13244 +\*------------------------------------------------------------------------------------------*/
13245 +extern p_vlynq_interrupt_vector_set_t p_vlynq_interrupt_vector_set;
13246 +extern p_vlynq_interrupt_vector_cntl_t p_vlynq_interrupt_vector_cntl;
13247 +extern p_vlynq_interrupt_get_count_t p_vlynq_interrupt_get_count;
13248 +extern p_vlynq_install_isr_t p_vlynq_install_isr;
13249 +extern p_vlynq_uninstall_isr_t p_vlynq_uninstall_isr;
13250 +extern p_vlynq_root_isr_t p_vlynq_root_isr;
13251 +extern p_vlynq_delay_t p_vlynq_delay;
13252 +extern p_vlynq_interrupt_vector_map_t p_vlynq_interrupt_vector_map;
13253 +extern p_vlynq_interrupt_set_polarity_t p_vlynq_interrupt_set_polarity;
13254 +extern p_vlynq_interrupt_get_polarity_t p_vlynq_interrupt_get_polarity;
13255 +extern p_vlynq_interrupt_set_type_t p_vlynq_interrupt_set_type;
13256 +extern p_vlynq_interrupt_get_type_t p_vlynq_interrupt_get_type;
13257 +extern p_vlynq_interrupt_enable_t p_vlynq_interrupt_enable;
13258 +extern p_vlynq_interrupt_disable_t p_vlynq_interrupt_disable;
13259 +extern void *p_vlynqDevice0;
13260 +extern void *p_vlynqDevice1;
13261 +
13262 +/*------------------------------------------------------------------------------------------*\
13263 +\*------------------------------------------------------------------------------------------*/
13264 +enum _avalanche_need_ {
13265 + avalanche_need_vlynq,
13266 + avalanche_need_auto_mdix
13267 +};
13268 +
13269 +int avalanche_need(enum _avalanche_need_);
13270 +
13271 +#endif /*--- #ifndef _avalanche_types_h_ ---*/
13272 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
13273 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
13274 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-11-10 01:10:46.071588750 +0100
13275 @@ -0,0 +1,26 @@
13276 +/*******************************************************************************
13277 + * FILE PURPOSE: Interface port id Header file
13278 + *******************************************************************************
13279 + * FILE NAME: if_port.h
13280 + *
13281 + * DESCRIPTION: Header file carrying information about port ids of interfaces
13282 + *
13283 + *
13284 + * (C) Copyright 2003, Texas Instruments, Inc
13285 + ******************************************************************************/
13286 +#ifndef _IF_PORT_H_
13287 +#define _IF_PORT_H_
13288 +
13289 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
13290 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
13291 +#define AVALANCHE_USB_PORT_ID 2
13292 +#define AVALANCHE_WLAN_PORT_ID 3
13293 +
13294 +
13295 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
13296 +
13297 +/* The marvell ports occupy port ids from 4 to 8 */
13298 +/* so the next port id number should start at 9 */
13299 +
13300 +
13301 +#endif /* _IF_PORT_H_ */
13302 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
13303 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
13304 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-11-10 01:10:46.071588750 +0100
13305 @@ -0,0 +1,180 @@
13306 +#ifndef _SANGAM_H_
13307 +#define _SANGAM_H_
13308 +
13309 +#include <linux/config.h>
13310 +#include <asm/addrspace.h>
13311 +
13312 +/*----------------------------------------------------
13313 + * Sangam's Module Base Addresses
13314 + *--------------------------------------------------*/
13315 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
13316 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
13317 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
13318 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
13319 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
13320 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
13321 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
13322 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
13323 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
13324 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
13325 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
13326 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
13327 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
13328 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
13329 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
13330 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
13331 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
13332 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
13333 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
13334 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
13335 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
13336 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
13337 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
13338 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
13339 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
13340 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
13341 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
13342 +
13343 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
13344 +
13345 +
13346 +/*----------------------------------------------------
13347 + * Sangam Interrupt Map (Primary Interrupts)
13348 + *--------------------------------------------------*/
13349 +
13350 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
13351 +#define AVALANCHE_EXT_INT_0 1
13352 +#define AVALANCHE_EXT_INT_1 2
13353 +/* Line# 3 to 4 are reserved */
13354 +#define AVALANCHE_TIMER_0_INT 5
13355 +#define AVALANCHE_TIMER_1_INT 6
13356 +#define AVALANCHE_UART0_INT 7
13357 +#define AVALANCHE_UART1_INT 8
13358 +#define AVALANCHE_DMA_INT0 9
13359 +#define AVALANCHE_DMA_INT1 10
13360 +/* Line# 11 to 14 are reserved */
13361 +#define AVALANCHE_ATM_SAR_INT 15
13362 +/* Line# 16 to 18 are reserved */
13363 +#define AVALANCHE_LOW_CPMAC_INT 19
13364 +/* Line# 20 is reserved */
13365 +#define AVALANCHE_LOW_VLYNQ_INT 21
13366 +#define AVALANCHE_CODEC_WAKEUP_INT 22
13367 +/* Line# 23 is reserved */
13368 +#define AVALANCHE_USB_SLAVE_INT 24
13369 +#define AVALANCHE_HIGH_VLYNQ_INT 25
13370 +/* Line# 26 to 27 are reserved */
13371 +#define AVALANCHE_UNIFIED_PHY_INT 28
13372 +#define AVALANCHE_I2C_INT 29
13373 +#define AVALANCHE_DMA_INT2 30
13374 +#define AVALANCHE_DMA_INT3 31
13375 +/* Line# 32 is reserved */
13376 +#define AVALANCHE_HIGH_CPMAC_INT 33
13377 +/* Line# 34 to 36 is reserved */
13378 +#define AVALANCHE_VDMA_VT_RX_INT 37
13379 +#define AVALANCHE_VDMA_VT_TX_INT 38
13380 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
13381 +
13382 +
13383 +#define AVALANCHE_EMIF_INT 47
13384 +
13385 +
13386 +
13387 +/*-----------------------------------------------------------
13388 + * Sangam's Reset Bits
13389 + *---------------------------------------------------------*/
13390 +
13391 +#define AVALANCHE_UART0_RESET_BIT 0
13392 +#define AVALANCHE_UART1_RESET_BIT 1
13393 +#define AVALANCHE_I2C_RESET_BIT 2
13394 +#define AVALANCHE_TIMER0_RESET_BIT 3
13395 +#define AVALANCHE_TIMER1_RESET_BIT 4
13396 +/* Reset bit 5 is reserved. */
13397 +#define AVALANCHE_GPIO_RESET_BIT 6
13398 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
13399 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
13400 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
13401 +/* Reset bit 10 is reserved. */
13402 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
13403 +#define AVALANCHE_FSER_RESET_BIT 12
13404 +/* Reset bit 13 to 15 are reserved */
13405 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
13406 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
13407 +#define AVALANCHE_MCDMA_RESET_BIT 18
13408 +#define AVALANCHE_BIST_RESET_BIT 19
13409 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
13410 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
13411 +#define AVALANCHE_MDIO_RESET_BIT 22
13412 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
13413 +/* Reset bit 24 to 25 are reserved */
13414 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
13415 +/* Reset bit 27 to 31 are reserved */
13416 +
13417 +
13418 +#define AVALANCHE_POWER_MODULE_USBSP 0
13419 +#define AVALANCHE_POWER_MODULE_WDTP 1
13420 +#define AVALANCHE_POWER_MODULE_UT0P 2
13421 +#define AVALANCHE_POWER_MODULE_UT1P 3
13422 +#define AVALANCHE_POWER_MODULE_IICP 4
13423 +#define AVALANCHE_POWER_MODULE_VDMAP 5
13424 +#define AVALANCHE_POWER_MODULE_GPIOP 6
13425 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
13426 +#define AVALANCHE_POWER_MODULE_SARP 8
13427 +#define AVALANCHE_POWER_MODULE_ADSLP 9
13428 +#define AVALANCHE_POWER_MODULE_EMIFP 10
13429 +#define AVALANCHE_POWER_MODULE_ADSPP 12
13430 +#define AVALANCHE_POWER_MODULE_RAMP 13
13431 +#define AVALANCHE_POWER_MODULE_ROMP 14
13432 +#define AVALANCHE_POWER_MODULE_DMAP 15
13433 +#define AVALANCHE_POWER_MODULE_BISTP 16
13434 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
13435 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
13436 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
13437 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
13438 +#define AVALANCHE_POWER_MODULE_EPHYP 24
13439 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
13440 +
13441 +
13442 +
13443 +
13444 +
13445 +/*
13446 + * Sangam board vectors
13447 + */
13448 +
13449 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
13450 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
13451 +
13452 +/*-----------------------------------------------------------------------------
13453 + * Sangam's system register.
13454 + *
13455 + *---------------------------------------------------------------------------*/
13456 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
13457 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
13458 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
13459 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
13460 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
13461 +
13462 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
13463 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
13464 +
13465 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
13466 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
13467 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
13468 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
13469 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
13470 +
13471 +/*
13472 + * Yamon Prom print address.
13473 + */
13474 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
13475 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
13476 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
13477 +
13478 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
13479 +
13480 +#define AVALANCHE_GPIO_PIN_COUNT 32
13481 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
13482 +
13483 +#include "sangam_boards.h"
13484 +
13485 +#endif /*_SANGAM_H_ */
13486 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
13487 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
13488 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-11-10 01:10:46.071588750 +0100
13489 @@ -0,0 +1,77 @@
13490 +#ifndef _SANGAM_BOARDS_H
13491 +#define _SANGAM_BOARDS_H
13492 +
13493 +// Let us define board specific information here.
13494 +
13495 +
13496 +#if defined(CONFIG_AR7DB)
13497 +
13498 +#define AFECLK_FREQ 35328000
13499 +#define REFCLK_FREQ 25000000
13500 +#define OSC3_FREQ 24000000
13501 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13502 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
13503 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13504 +
13505 +#endif
13506 +
13507 +
13508 +#if defined(CONFIG_AR7RD)
13509 +#define AFECLK_FREQ 35328000
13510 +#define REFCLK_FREQ 25000000
13511 +#define OSC3_FREQ 24000000
13512 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13513 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13514 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13515 +#endif
13516 +
13517 +
13518 +#if defined(CONFIG_AR7WI)
13519 +#define AFECLK_FREQ 35328000
13520 +#define REFCLK_FREQ 25000000
13521 +#define OSC3_FREQ 24000000
13522 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13523 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13524 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13525 +#endif
13526 +
13527 +
13528 +#if defined(CONFIG_AR7V)
13529 +#define AFECLK_FREQ 35328000
13530 +#define REFCLK_FREQ 25000000
13531 +#define OSC3_FREQ 24000000
13532 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13533 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
13534 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13535 +#endif
13536 +
13537 +
13538 +#if defined(CONFIG_AR7WRD)
13539 +#define AFECLK_FREQ 35328000
13540 +#define REFCLK_FREQ 25000000
13541 +#define OSC3_FREQ 24000000
13542 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13543 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
13544 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13545 +#endif
13546 +
13547 +
13548 +#if defined(CONFIG_AR7VWI)
13549 +#define AFECLK_FREQ 35328000
13550 +#define REFCLK_FREQ 25000000
13551 +#define OSC3_FREQ 24000000
13552 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
13553 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
13554 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
13555 +#endif
13556 +
13557 +
13558 +#if defined CONFIG_SEAD2
13559 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
13560 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
13561 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
13562 +#include <asm/mips-boards/sead.h>
13563 +#endif
13564 +
13565 +
13566 +#endif
13567 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
13568 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
13569 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-11-10 01:10:46.075589000 +0100
13570 @@ -0,0 +1,338 @@
13571 +/******************************************************************************
13572 + * FILE PURPOSE: TNETD73xx Common Header File
13573 + ******************************************************************************
13574 + * FILE NAME: tnetd73xx.h
13575 + *
13576 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
13577 + *
13578 + * REVISION HISTORY:
13579 + * 27 Nov 02 - PSP TII
13580 + *
13581 + * (C) Copyright 2002, Texas Instruments, Inc
13582 + *******************************************************************************/
13583 +
13584 +/*
13585 + *
13586 + *
13587 + * These are const, typedef, and api definitions for tnetd73xx.
13588 + *
13589 + * NOTES:
13590 + * 1. This file may be included into both C and Assembly files.
13591 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
13592 + * avoid C data types (typedefs) below;
13593 + * - for .c files, you don't have to do anything special.
13594 + *
13595 + * 2. This file has a number of sections for each SOC subsystem. When adding
13596 + * a new constant, find the subsystem you are working on and follow the
13597 + * name pattern. If you are adding another typedef for your interface, please,
13598 + * place it with other typedefs and function prototypes.
13599 + *
13600 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
13601 + * cluttering. Include such items directly into the module's .c file or have a
13602 + * local .h file to pass data between smaller modules. This file defines only
13603 + * shared items.
13604 + */
13605 +
13606 +#ifndef __TNETD73XX_H__
13607 +#define __TNETD73XX_H__
13608 +
13609 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
13610 +
13611 +extern unsigned int tnetd73xx_mips_freq;
13612 +extern unsigned int tnetd73xx_vbus_freq;
13613 +
13614 +#include "tnetd73xx_err.h"
13615 +
13616 +#endif /* _ASMLANGUAGE */
13617 +
13618 +
13619 +/*******************************************************************************************
13620 +* Emerald core specific
13621 +******************************************************************************************** */
13622 +
13623 +#ifdef BIG_ENDIAN
13624 +#elif defined(LITTLE_ENDIAN)
13625 +#else
13626 +#error Need to define endianism
13627 +#endif
13628 +
13629 +#ifndef KSEG_MSK
13630 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
13631 +#endif
13632 +
13633 +#ifndef KSEG_INV_MASK
13634 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
13635 +#endif
13636 +
13637 +#ifndef KSEG0_BASE
13638 +#define KSEG0_BASE 0x80000000
13639 +#endif
13640 +
13641 +#ifndef KSEG1_BASE
13642 +#define KSEG1_BASE 0xA0000000
13643 +#endif
13644 +
13645 +#ifndef KSEG0
13646 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
13647 +#endif
13648 +
13649 +#ifndef KSEG1
13650 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
13651 +#endif
13652 +
13653 +#ifndef KUSEG
13654 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
13655 +#endif
13656 +
13657 +#ifndef PHYS_ADDR
13658 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
13659 +#endif
13660 +
13661 +#ifndef PHYS_TO_K0
13662 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
13663 +#endif
13664 +
13665 +#ifndef PHYS_TO_K1
13666 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
13667 +#endif
13668 +
13669 +#ifndef REG8_ADDR
13670 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
13671 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
13672 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
13673 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
13674 +#endif
13675 +
13676 +#ifndef REG16_ADDR
13677 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
13678 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
13679 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
13680 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
13681 +#endif
13682 +
13683 +#ifndef REG32_ADDR
13684 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
13685 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
13686 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
13687 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
13688 +#endif
13689 +
13690 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
13691 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
13692 +#endif
13693 +
13694 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
13695 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
13696 +#endif
13697 +
13698 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
13699 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
13700 +#endif
13701 +
13702 +/* TNETD73XX chip definations */
13703 +
13704 +#define FREQ_1MHZ 1000000
13705 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
13706 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
13707 +
13708 +#ifdef AR7SEAD2
13709 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
13710 +#else
13711 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
13712 +#endif
13713 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
13714 +
13715 +
13716 +
13717 +/* Module base addresses */
13718 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
13719 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
13720 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
13721 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
13722 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
13723 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
13724 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
13725 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
13726 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
13727 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
13728 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
13729 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
13730 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
13731 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
13732 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
13733 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
13734 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
13735 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
13736 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
13737 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
13738 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
13739 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
13740 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
13741 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
13742 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
13743 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
13744 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
13745 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
13746 +
13747 +/* BBIF Registers */
13748 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
13749 +
13750 +/* Device Configuration Latch Registers */
13751 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
13752 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
13753 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
13754 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
13755 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
13756 +
13757 +/* GPIO Control */
13758 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
13759 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
13760 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
13761 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
13762 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
13763 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
13764 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
13765 +
13766 +/* Reset Control */
13767 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
13768 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
13769 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
13770 +
13771 +/* Power Control */
13772 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
13773 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
13774 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
13775 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
13776 +
13777 +/* Clock Control */
13778 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
13779 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
13780 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
13781 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
13782 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
13783 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
13784 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
13785 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
13786 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
13787 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
13788 +
13789 +/* EMIF control */
13790 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
13791 +
13792 +/* UART */
13793 +#ifdef AR7SEAD2
13794 +#define TNETD73XX_UART_FREQ 3686400
13795 +#else
13796 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
13797 +#endif
13798 +
13799 +/* Interrupt Controller */
13800 +
13801 +/* Primary interrupts */
13802 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
13803 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
13804 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
13805 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
13806 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
13807 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
13808 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
13809 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
13810 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
13811 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
13812 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
13813 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
13814 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
13815 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
13816 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
13817 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
13818 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
13819 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
13820 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
13821 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
13822 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
13823 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
13824 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
13825 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
13826 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
13827 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
13828 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
13829 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
13830 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
13831 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
13832 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
13833 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
13834 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
13835 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
13836 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
13837 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
13838 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
13839 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
13840 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
13841 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
13842 +
13843 +/* Secondary interrupts */
13844 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
13845 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
13846 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
13847 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
13848 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
13849 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
13850 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
13851 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
13852 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
13853 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
13854 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
13855 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
13856 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
13857 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
13858 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
13859 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
13860 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
13861 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
13862 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
13863 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
13864 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
13865 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
13866 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
13867 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
13868 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
13869 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
13870 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
13871 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
13872 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
13873 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
13874 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
13875 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
13876 +
13877 +/* These ugly macros are to access the -1 registers, like config1 */
13878 +#define MFC0_SEL1_OPCODE(dst, src)\
13879 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
13880 + nop; \
13881 + nop; \
13882 + nop
13883 +
13884 +#define MTC0_SEL1_OPCODE(dst, src)\
13885 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
13886 + nop; \
13887 + nop; \
13888 + nop
13889 +
13890 +
13891 +/* Below are Jade core specific */
13892 +#define CFG0_4K_IL_MASK 0x00380000
13893 +#define CFG0_4K_IL_SHIFT 19
13894 +#define CFG0_4K_IA_MASK 0x00070000
13895 +#define CFG0_4K_IA_SHIFT 16
13896 +#define CFG0_4K_IS_MASK 0x01c00000
13897 +#define CFG0_4K_IS_SHIFT 22
13898 +
13899 +#define CFG0_4K_DL_MASK 0x00001c00
13900 +#define CFG0_4K_DL_SHIFT 10
13901 +#define CFG0_4K_DA_MASK 0x00000380
13902 +#define CFG0_4K_DA_SHIFT 7
13903 +#define CFG0_4K_DS_MASK 0x0000E000
13904 +#define CFG0_4K_DS_SHIFT 13
13905 +
13906 +
13907 +
13908 +#endif /* __TNETD73XX_H_ */
13909 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
13910 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
13911 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-11-10 01:10:46.075589000 +0100
13912 @@ -0,0 +1,42 @@
13913 +/******************************************************************************
13914 + * FILE PURPOSE: TNETD73xx Error Definations Header File
13915 + ******************************************************************************
13916 + * FILE NAME: tnetd73xx_err.h
13917 + *
13918 + * DESCRIPTION: Error definations for TNETD73XX
13919 + *
13920 + * REVISION HISTORY:
13921 + * 27 Nov 02 - PSP TII
13922 + *
13923 + * (C) Copyright 2002, Texas Instruments, Inc
13924 + *******************************************************************************/
13925 +
13926 +
13927 +#ifndef __TNETD73XX_ERR_H__
13928 +#define __TNETD73XX_ERR_H__
13929 +
13930 +typedef enum TNETD73XX_ERR_t
13931 +{
13932 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
13933 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
13934 +
13935 + /* Pointers and args */
13936 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
13937 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
13938 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
13939 +
13940 + /* Memory issues */
13941 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
13942 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
13943 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
13944 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
13945 +
13946 + /* Device issues */
13947 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
13948 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
13949 +
13950 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
13951 +
13952 +} TNETD73XX_ERR;
13953 +
13954 +#endif /* __TNETD73XX_ERR_H__ */
13955 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
13956 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
13957 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-11-10 01:10:46.075589000 +0100
13958 @@ -0,0 +1,239 @@
13959 +/******************************************************************************
13960 + * FILE PURPOSE: TNETD73xx Misc modules API Header
13961 + ******************************************************************************
13962 + * FILE NAME: tnetd73xx_misc.h
13963 + *
13964 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
13965 + * FSER Modules API
13966 + * As per TNETD73xx specifications
13967 + *
13968 + * REVISION HISTORY:
13969 + * 27 Nov 02 - Sharath Kumar PSP TII
13970 + * 14 Feb 03 - Anant Gole PSP TII
13971 + *
13972 + * (C) Copyright 2002, Texas Instruments, Inc
13973 + *******************************************************************************/
13974 +
13975 +#ifndef __TNETD73XX_MISC_H__
13976 +#define __TNETD73XX_MISC_H__
13977 +
13978 +/*****************************************************************************
13979 + * Reset Control Module
13980 + *****************************************************************************/
13981 +
13982 +typedef enum TNETD73XX_RESET_MODULE_tag
13983 +{
13984 + RESET_MODULE_UART0 = 0,
13985 + RESET_MODULE_UART1 = 1,
13986 + RESET_MODULE_I2C = 2,
13987 + RESET_MODULE_TIMER0 = 3,
13988 + RESET_MODULE_TIMER1 = 4,
13989 + RESET_MODULE_GPIO = 6,
13990 + RESET_MODULE_ADSLSS = 7,
13991 + RESET_MODULE_USBS = 8,
13992 + RESET_MODULE_SAR = 9,
13993 + RESET_MODULE_VDMA_VT = 11,
13994 + RESET_MODULE_FSER = 12,
13995 + RESET_MODULE_VLYNQ1 = 16,
13996 + RESET_MODULE_EMAC0 = 17,
13997 + RESET_MODULE_DMA = 18,
13998 + RESET_MODULE_BIST = 19,
13999 + RESET_MODULE_VLYNQ0 = 20,
14000 + RESET_MODULE_EMAC1 = 21,
14001 + RESET_MODULE_MDIO = 22,
14002 + RESET_MODULE_ADSLSS_DSP = 23,
14003 + RESET_MODULE_EPHY = 26
14004 +} TNETD73XX_RESET_MODULE_T;
14005 +
14006 +typedef enum TNETD73XX_RESET_CTRL_tag
14007 +{
14008 + IN_RESET = 0,
14009 + OUT_OF_RESET
14010 +} TNETD73XX_RESET_CTRL_T;
14011 +
14012 +typedef enum TNETD73XX_SYS_RST_MODE_tag
14013 +{
14014 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
14015 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
14016 +} TNETD73XX_SYS_RST_MODE_T;
14017 +
14018 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
14019 +{
14020 + HARDWARE_RESET = 0,
14021 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
14022 + WATCHDOG_RESET,
14023 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
14024 +} TNETD73XX_SYS_RESET_STATUS_T;
14025 +
14026 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
14027 + TNETD73XX_RESET_CTRL_T reset_ctrl);
14028 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
14029 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
14030 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
14031 +
14032 +/*****************************************************************************
14033 + * Power Control Module
14034 + *****************************************************************************/
14035 +
14036 +typedef enum TNETD73XX_POWER_MODULE_tag
14037 +{
14038 + POWER_MODULE_USBSP = 0,
14039 + POWER_MODULE_WDTP = 1,
14040 + POWER_MODULE_UT0P = 2,
14041 + POWER_MODULE_UT1P = 3,
14042 + POWER_MODULE_IICP = 4,
14043 + POWER_MODULE_VDMAP = 5,
14044 + POWER_MODULE_GPIOP = 6,
14045 + POWER_MODULE_VLYNQ1P = 7,
14046 + POWER_MODULE_SARP = 8,
14047 + POWER_MODULE_ADSLP = 9,
14048 + POWER_MODULE_EMIFP = 10,
14049 + POWER_MODULE_ADSPP = 12,
14050 + POWER_MODULE_RAMP = 13,
14051 + POWER_MODULE_ROMP = 14,
14052 + POWER_MODULE_DMAP = 15,
14053 + POWER_MODULE_BISTP = 16,
14054 + POWER_MODULE_TIMER0P = 18,
14055 + POWER_MODULE_TIMER1P = 19,
14056 + POWER_MODULE_EMAC0P = 20,
14057 + POWER_MODULE_EMAC1P = 22,
14058 + POWER_MODULE_EPHYP = 24,
14059 + POWER_MODULE_VLYNQ0P = 27,
14060 +} TNETD73XX_POWER_MODULE_T;
14061 +
14062 +typedef enum TNETD73XX_POWER_CTRL_tag
14063 +{
14064 + POWER_CTRL_POWER_UP = 0,
14065 + POWER_CTRL_POWER_DOWN
14066 +} TNETD73XX_POWER_CTRL_T;
14067 +
14068 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
14069 +{
14070 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
14071 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
14072 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
14073 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
14074 +} TNETD73XX_SYS_POWER_MODE_T;
14075 +
14076 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
14077 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
14078 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
14079 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
14080 +
14081 +/*****************************************************************************
14082 + * Wakeup Control
14083 + *****************************************************************************/
14084 +
14085 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
14086 +{
14087 + WAKEUP_INT0 = 1,
14088 + WAKEUP_INT1 = 2,
14089 + WAKEUP_INT2 = 4,
14090 + WAKEUP_INT3 = 8
14091 +} TNETD73XX_WAKEUP_INTERRUPT_T;
14092 +
14093 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
14094 +{
14095 + WAKEUP_DISABLED = 0,
14096 + WAKEUP_ENABLED
14097 +} TNETD73XX_WAKEUP_CTRL_T;
14098 +
14099 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
14100 +{
14101 + WAKEUP_ACTIVE_HIGH = 0,
14102 + WAKEUP_ACTIVE_LOW
14103 +} TNETD73XX_WAKEUP_POLARITY_T;
14104 +
14105 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
14106 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
14107 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
14108 +
14109 +/*****************************************************************************
14110 + * FSER Control
14111 + *****************************************************************************/
14112 +
14113 +typedef enum TNETD73XX_FSER_MODE_tag
14114 +{
14115 + FSER_I2C = 0,
14116 + FSER_UART = 1
14117 +} TNETD73XX_FSER_MODE_T;
14118 +
14119 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
14120 +
14121 +/*****************************************************************************
14122 + * Clock Control
14123 + *****************************************************************************/
14124 +
14125 +#define CLK_MHZ(x) ( (x) * 1000000 )
14126 +
14127 +typedef enum TNETD73XX_CLKC_ID_tag
14128 +{
14129 + CLKC_SYS = 0,
14130 + CLKC_MIPS,
14131 + CLKC_USB,
14132 + CLKC_ADSLSS
14133 +} TNETD73XX_CLKC_ID_T;
14134 +
14135 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
14136 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
14137 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
14138 +
14139 +/*****************************************************************************
14140 + * GPIO Control
14141 + *****************************************************************************/
14142 +
14143 +typedef enum TNETD73XX_GPIO_PIN_tag
14144 +{
14145 + GPIO_UART0_RD = 0,
14146 + GPIO_UART0_TD = 1,
14147 + GPIO_UART0_RTS = 2,
14148 + GPIO_UART0_CTS = 3,
14149 + GPIO_FSER_CLK = 4,
14150 + GPIO_FSER_D = 5,
14151 + GPIO_EXT_AFE_SCLK = 6,
14152 + GPIO_EXT_AFE_TX_FS = 7,
14153 + GPIO_EXT_AFE_TXD = 8,
14154 + GPIO_EXT_AFE_RS_FS = 9,
14155 + GPIO_EXT_AFE_RXD1 = 10,
14156 + GPIO_EXT_AFE_RXD0 = 11,
14157 + GPIO_EXT_AFE_CDIN = 12,
14158 + GPIO_EXT_AFE_CDOUT = 13,
14159 + GPIO_EPHY_SPEED100 = 14,
14160 + GPIO_EPHY_LINKON = 15,
14161 + GPIO_EPHY_ACTIVITY = 16,
14162 + GPIO_EPHY_FDUPLEX = 17,
14163 + GPIO_EINT0 = 18,
14164 + GPIO_EINT1 = 19,
14165 + GPIO_MBSP0_TCLK = 20,
14166 + GPIO_MBSP0_RCLK = 21,
14167 + GPIO_MBSP0_RD = 22,
14168 + GPIO_MBSP0_TD = 23,
14169 + GPIO_MBSP0_RFS = 24,
14170 + GPIO_MBSP0_TFS = 25,
14171 + GPIO_MII_DIO = 26,
14172 + GPIO_MII_DCLK = 27,
14173 +} TNETD73XX_GPIO_PIN_T;
14174 +
14175 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
14176 +{
14177 + FUNCTIONAL_PIN = 0,
14178 + GPIO_PIN = 1
14179 +} TNETD73XX_GPIO_PIN_MODE_T;
14180 +
14181 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
14182 +{
14183 + GPIO_OUTPUT_PIN = 0,
14184 + GPIO_INPUT_PIN = 1
14185 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
14186 +
14187 +void tnetd73xx_gpio_init(void);
14188 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
14189 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
14190 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
14191 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
14192 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
14193 +
14194 +/* TNETD73XX Revision */
14195 +__u32 tnetd73xx_get_revision(void);
14196 +
14197 +#endif /* __TNETD73XX_MISC_H__ */
14198 diff -urN linux.old/include/asm-mips/ar7/vlynq.h linux.dev/include/asm-mips/ar7/vlynq.h
14199 --- linux.old/include/asm-mips/ar7/vlynq.h 1970-01-01 01:00:00.000000000 +0100
14200 +++ linux.dev/include/asm-mips/ar7/vlynq.h 2005-11-10 01:10:46.095590250 +0100
14201 @@ -0,0 +1,610 @@
14202 +/***************************************************************************
14203 +**+----------------------------------------------------------------------+**
14204 +**| **** |**
14205 +**| **** |**
14206 +**| ******o*** |**
14207 +**| ********_///_**** |**
14208 +**| ***** /_//_/ **** |**
14209 +**| ** ** (__/ **** |**
14210 +**| ********* |**
14211 +**| **** |**
14212 +**| *** |**
14213 +**| |**
14214 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
14215 +**| ALL RIGHTS RESERVED |**
14216 +**| |**
14217 +**| Permission is hereby granted to licensees of Texas Instruments |**
14218 +**| Incorporated (TI) products to use this computer program for the sole |**
14219 +**| purpose of implementing a licensee product based on TI products. |**
14220 +**| No other rights to reproduce, use, or disseminate this computer |**
14221 +**| program, whether in part or in whole, are granted. |**
14222 +**| |**
14223 +**| TI makes no representation or warranties with respect to the |**
14224 +**| performance of this computer program, and specifically disclaims |**
14225 +**| any responsibility for any damages, special or consequential, |**
14226 +**| connected with the use of this program. |**
14227 +**| |**
14228 +**+----------------------------------------------------------------------+**
14229 +***************************************************************************/
14230 +
14231 +/*********************************************************************************
14232 + * ------------------------------------------------------------------------------
14233 + * Module : vlynq_hal.h
14234 + * Description :
14235 + * This header file provides the set of functions exported by the
14236 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
14237 + * ------------------------------------------------------------------------------
14238 + *********************************************************************************/
14239 +
14240 +#ifndef _VLYNQ_HAL_H_
14241 +#define _VLYNQ_HAL_H_
14242 +
14243 +/* Enable/Disable debug feature */
14244 +#undef VLYNQ_DEBUG
14245 +
14246 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
14247 +#define debugPrint(format,args...)
14248 +#else
14249 +#define debugPrint(format,args...)
14250 +#endif
14251 +
14252 + /* number of VLYNQ memory regions supported */
14253 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
14254 +
14255 + /* Max.number of external interrupt inputs supported by VLYNQ module */
14256 +#define VLYNQ_IVR_MAXIVR 0x08
14257 +
14258 +#define VLYNQ_CLK_DIV_MAX 0x08
14259 +#define VLYNQ_CLK_DIV_MIN 0x01
14260 +
14261 +
14262 +/*** the total number of entries allocated for ICB would be
14263 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
14264 +#define VLYNQ_IVR_CHAIN_SLOTS 10
14265 +
14266 +
14267 +/* Error defines */
14268 +#define VLYNQ_SUCCESS 0
14269 +
14270 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
14271 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
14272 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
14273 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
14274 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
14275 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
14276 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
14277 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
14278 +
14279 +/* Vlynq Defines and Macros */
14280 +
14281 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
14282 +
14283 +/* Base address of module */
14284 +#define VLYNQ_BASE (pdev->module_base)
14285 +
14286 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
14287 +
14288 +#define VLYNQ_REV_OFFSET 0x0000
14289 +#define VLYNQ_CTRL_OFFSET 0x0004
14290 +#define VLYNQ_STATUS_OFFSET 0x0008
14291 +#define VLYNQ_INT_STAT_OFFSET 0x0010
14292 +#define VLYNQ_INT_PEND_OFFSET 0x0014
14293 +#define VLYNQ_INT_PTR_OFFSET 0x0018
14294 +#define VLYNQ_TXMAP_OFFSET 0x001c
14295 +
14296 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
14297 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
14298 +
14299 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
14300 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
14301 +
14302 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
14303 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
14304 +
14305 +#define VLYNQ_REV_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
14306 +#define VLYNQ_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
14307 +#define VLYNQ_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
14308 +#define VLYNQ_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
14309 +#define VLYNQ_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
14310 +#define VLYNQ_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
14311 +#define VLYNQ_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
14312 +
14313 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14314 +#define VLYNQ_RXMAP_SIZE_REG(map) \
14315 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
14316 +
14317 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14318 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
14319 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
14320 +
14321 +#define VLYNQ_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
14322 +
14323 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
14324 +#define VLYNQ_IVR_OFFSET(ivr) \
14325 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
14326 +
14327 +#define VLYNQ_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(0)) )
14328 +#define VLYNQ_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(4)) )
14329 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14330 +
14331 +#define VLYNQ_IVR_INTEN(ivr) (((unsigned int)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
14332 +#define VLYNQ_IVR_INTTYPE(ivr) (((unsigned int)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
14333 +#define VLYNQ_IVR_INTPOL(ivr) (((unsigned int)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
14334 +#define VLYNQ_IVR_INTVEC(ivr) (((unsigned int)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
14335 +#define VLYNQ_IVR_INTALL(ivr) (((unsigned int)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
14336 +
14337 +
14338 +
14339 +/*********************************
14340 + * Remote VLYNQ register set *
14341 + *********************************/
14342 +
14343 +#define VLYNQ_R_REV_OFFSET 0x0080
14344 +#define VLYNQ_R_CTRL_OFFSET 0x0084
14345 +#define VLYNQ_R_STATUS_OFFSET 0x0088
14346 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
14347 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
14348 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
14349 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
14350 +
14351 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
14352 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
14353 +
14354 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
14355 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
14356 +
14357 +#define VLYNQ_R_REV_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
14358 +#define VLYNQ_R_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
14359 +#define VLYNQ_R_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
14360 +#define VLYNQ_R_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
14361 +#define VLYNQ_R_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
14362 +#define VLYNQ_R_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
14363 +#define VLYNQ_R_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
14364 +
14365 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14366 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
14367 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
14368 +
14369 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14370 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
14371 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
14372 +
14373 +#define VLYNQ_R_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
14374 +
14375 +#define VLYNQ_R_IVR_OFFSET(ivr) \
14376 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
14377 +
14378 +
14379 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14380 +#define VLYNQ_R_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(0)) )
14381 +#define VLYNQ_R_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(4)) )
14382 +
14383 +
14384 +/****End of remote register set definition******/
14385 +
14386 +
14387 +/*** Masks for individual register fields ***/
14388 +
14389 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
14390 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
14391 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
14392 +
14393 +
14394 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
14395 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
14396 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
14397 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
14398 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
14399 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
14400 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
14401 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
14402 +
14403 +
14404 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
14405 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
14406 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
14407 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
14408 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
14409 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
14410 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
14411 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
14412 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
14413 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
14414 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
14415 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
14416 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
14417 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
14418 +
14419 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
14420 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
14421 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
14422 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
14423 +
14424 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
14425 +
14426 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
14427 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
14428 +
14429 +#define VLYNQ_IVR_INTEN_MASK 0x80
14430 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
14431 +#define VLYNQ_IVR_INTPOL_MASK 0x20
14432 +
14433 +
14434 +/**** Helper macros ****/
14435 +
14436 +#define VLYNQ_RESETCB(arg) \
14437 + if( pdev->reset_cb != NULL) \
14438 + { \
14439 + (pdev->reset_cb)(pdev, (arg)); \
14440 + }
14441 +
14442 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
14443 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
14444 +
14445 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
14446 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
14447 +
14448 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
14449 +
14450 +
14451 +/*************************************
14452 + * Enums *
14453 + *************************************/
14454 +
14455 +/* Initialization options define what operations are
14456 + * undertaken during vlynq module initialization */
14457 +typedef enum
14458 +{
14459 + /* Init host local memory regions.This allows
14460 + * local host access remote memory regions */
14461 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
14462 + /* Init host remote memory regions.This allows
14463 + * remote device access local memory regions */
14464 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
14465 + /* Init local interrupt config*/
14466 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
14467 + /* Init remote interrupt config*/
14468 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
14469 + /* Check link during initialization*/
14470 + VLYNQ_INIT_CHECK_LINK =0x10,
14471 + /* configure clock during init */
14472 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
14473 + /* Clear errors during init */
14474 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
14475 + /* All options */
14476 + VLYNQ_INIT_PERFORM_ALL =0x7F
14477 +}VLYNQ_INIT_OPTIONS;
14478 +
14479 +
14480 +/* VLYNQ_DEV_TYPE identifies local or remote device */
14481 +typedef enum
14482 +{
14483 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
14484 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
14485 +}VLYNQ_DEV_TYPE;
14486 +
14487 +
14488 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
14489 +typedef enum
14490 +{
14491 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
14492 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
14493 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
14494 +}VLYNQ_CLK_SOURCE;
14495 +
14496 +
14497 +/* VLYNQ_DRV_STATE indicates the current driver state */
14498 +typedef enum
14499 +{
14500 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
14501 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
14502 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
14503 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
14504 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
14505 +}VLYNQ_DRV_STATE;
14506 +
14507 +
14508 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
14509 +typedef enum
14510 +{
14511 + VLYNQ_BUS_WIDTH_3 = 3,
14512 + VLYNQ_BUS_WIDTH_5 = 5,
14513 + VLYNQ_BUS_WIDTH_7 = 7,
14514 + VLYNQ_BUS_WIDTH_9 = 9
14515 +}VLYNQ_BUS_WIDTH;
14516 +
14517 +
14518 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
14519 + * interrupts are processed by the host or passed on to the
14520 + * remote device.
14521 + */
14522 +typedef enum
14523 +{
14524 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
14525 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
14526 +}VLYNQ_LOCAL_INT_CONFIG;
14527 +
14528 +
14529 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
14530 + * interrupts are to be handled by the SOC system ISR
14531 + * or via the vlynq root ISR
14532 + */
14533 +typedef enum
14534 +{
14535 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
14536 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
14537 +}VLYNQ_REMOTE_INT_CONFIG;
14538 +
14539 +
14540 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
14541 +typedef enum
14542 +{
14543 + VLYNQ_INTR_ACTIVE_HIGH = 0,
14544 + VLYNQ_INTR_ACTIVE_LOW = 1
14545 +}VLYNQ_INTR_POLARITY;
14546 +
14547 +
14548 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
14549 +typedef enum
14550 +{
14551 + VLYNQ_INTR_LEVEL = 0,
14552 + VLYNQ_INTR_PULSED = 1
14553 +}VLYNQ_INTR_TYPE;
14554 +
14555 +
14556 +/* VLYNQ_RESET_MODE - vlynq reset mode */
14557 +typedef enum
14558 +{
14559 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
14560 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
14561 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
14562 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
14563 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
14564 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
14565 +}VLYNQ_RESET_MODE;
14566 +
14567 +
14568 +
14569 +/*************************************
14570 + * Typedefs *
14571 + *************************************/
14572 +
14573 +struct VLYNQ_DEV_t; /*forward declaration*/
14574 +
14575 +/*--------Function Pointers defintions -----------*/
14576 +
14577 +/* prototype for interrupt handler definition */
14578 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
14579 +
14580 +typedef void
14581 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
14582 +
14583 +typedef void
14584 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
14585 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
14586 + unsigned int dwStatRegVal); /* Value of the relevant status register */
14587 +
14588 +
14589 +/*-------Structure Definitions------------*/
14590 +
14591 +typedef struct VLYNQ_MEMORY_MAP_t
14592 +{
14593 + unsigned int Txmap;
14594 + unsigned int RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
14595 + unsigned int RxSize[VLYNQ_MAX_MEMORY_REGIONS];
14596 +}VLYNQ_MEMORY_MAP;
14597 +
14598 +
14599 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
14600 + * settings in vlynq Control register */
14601 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
14602 +{
14603 + /* vlynq interrupts handled by host or remote - maps to
14604 + * intLocal bit in vlynq control register */
14605 + VLYNQ_LOCAL_INT_CONFIG intLocal;
14606 +
14607 + /* remote interrupts handled by vlynq isr or host system
14608 + * interrupt controller - maps to the int2Cfg in vlynq
14609 + * control register */
14610 + VLYNQ_REMOTE_INT_CONFIG intRemote;
14611 +
14612 + /* bit in pending/set register used for module interrupts*/
14613 + unsigned int map_vector;
14614 +
14615 + /* used only if remote interrupts are to be handled by system ISR*/
14616 + unsigned int intr_ptr;
14617 +
14618 +}VLYNQ_INTERRUPT_CNTRL;
14619 +
14620 +
14621 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
14622 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
14623 + * table to identify the ISR to be invoked
14624 + */
14625 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
14626 +{
14627 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
14628 + void *arg1 ; /* Arg 1 for the ISR */
14629 + void *arg2 ; /* Arg 2 for the ISR */
14630 + void *arg3 ; /* Arg 3 for the ISR */
14631 + unsigned int isrCount; /* number of ISR invocations so far */
14632 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
14633 +}VLYNQ_INTR_CNTRL_ICB;
14634 +
14635 +/* overlay of vlynq register set */
14636 +typedef struct VLYNQ_REG_SET_t
14637 +{
14638 + unsigned int revision; /*offset : 0x00 */
14639 + unsigned int control; /* 0x04*/
14640 + unsigned int status; /* 0x08*/
14641 + unsigned int pad1; /* 0x0c*/
14642 + unsigned int intStatus; /*0x10*/
14643 + unsigned int intPending; /*0x14*/
14644 + unsigned int intPtr; /*0x18*/
14645 + unsigned int txMap; /*0x1C*/
14646 + unsigned int rxSize1; /*0x20*/
14647 + unsigned int rxOffset1; /*0x24*/
14648 + unsigned int rxSize2; /*0x28*/
14649 + unsigned int rxOffset2; /*0x2C*/
14650 + unsigned int rxSize3; /*0x30*/
14651 + unsigned int rxOffset3; /*0x34*/
14652 + unsigned int rxSize4; /*0x38*/
14653 + unsigned int rxOffset4; /*0x3C*/
14654 + unsigned int chipVersion; /*0x40*/
14655 + unsigned int pad2[8];
14656 + unsigned int ivr30; /*0x60*/
14657 + unsigned int ivr74; /*0x64*/
14658 + unsigned int pad3[7];
14659 +}VLYNQ_REG_SET;
14660 +
14661 +
14662 +typedef struct VLYNQ_DEV_t
14663 +{
14664 + /** module index:1,2,3... used for debugging purposes */
14665 + unsigned int dev_idx;
14666 +
14667 + /*VLYNQ module base address */
14668 + unsigned int module_base;
14669 +
14670 + /* clock source selection */
14671 + VLYNQ_CLK_SOURCE clk_source;
14672 +
14673 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
14674 + unsigned int clk_div;
14675 +
14676 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
14677 + VLYNQ_DRV_STATE state;
14678 +
14679 + /* Valid VLYNQ bus width, filled by driver */
14680 + VLYNQ_BUS_WIDTH width;
14681 +
14682 + /* local memory mapping */
14683 + VLYNQ_MEMORY_MAP local_mem;
14684 +
14685 + /* remote memory mapping */
14686 + VLYNQ_MEMORY_MAP remote_mem;
14687 +
14688 + /* Local module interrupt params */
14689 + VLYNQ_INTERRUPT_CNTRL local_irq;
14690 +
14691 + /* remote module interrupt params */
14692 + VLYNQ_INTERRUPT_CNTRL remote_irq;
14693 +
14694 + /*** ICB related fields **/
14695 +
14696 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
14697 + * expansion slots for shared interrupts*/
14698 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
14699 + VLYNQ_INTR_CNTRL_ICB *freelist;
14700 +
14701 + /* table holding mapping between intVector and the bit position the interrupt
14702 + * is mapped to(mapVector)*/
14703 + char vector_map[32];
14704 +
14705 + /* user callback for vlynq events, NULL if unused */
14706 + VLYNQ_REPORT_CB report_cb;
14707 +
14708 + /* user callback for resetting/realeasing remote device */
14709 + VLYNQ_RESET_REMOTE reset_cb;
14710 +
14711 + /*** Handles provided for direct access to register set if need be
14712 + * Must be intialized to point to appropriate address during
14713 + * vlynq_init */
14714 + volatile VLYNQ_REG_SET * local;
14715 + volatile VLYNQ_REG_SET * remote;
14716 +
14717 + unsigned int intCount; /* number of interrupts generated so far */
14718 + unsigned int isrCount; /* number of ISR invocations so far */
14719 +}VLYNQ_DEV;
14720 +
14721 +
14722 +typedef struct VLYNQ_ISR_ARGS_t
14723 +{
14724 + int irq;
14725 + void * arg;
14726 + void * regset;
14727 +}VLYNQ_ISR_ARGS;
14728 +
14729 +
14730 +/****************************************
14731 + * Function Prototypes *
14732 + * API exported by generic vlynq driver *
14733 + ****************************************/
14734 +/* Initialization function */
14735 +int vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
14736 +
14737 +/* Check vlynq link */
14738 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev);
14739 +
14740 +/* Set interrupt vector in local or remote device */
14741 +int vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
14742 + unsigned int int_vector,
14743 + unsigned int map_vector,
14744 + VLYNQ_DEV_TYPE dev,
14745 + VLYNQ_INTR_POLARITY pol,
14746 + VLYNQ_INTR_TYPE type);
14747 +
14748 +
14749 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
14750 + unsigned int int_vector,
14751 + VLYNQ_DEV_TYPE dev,
14752 + unsigned int enable);
14753 +
14754 +unsigned int vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
14755 + unsigned int map_vector);
14756 +
14757 +int vlynq_install_isr( VLYNQ_DEV *pdev,
14758 + unsigned int map_vector,
14759 + VLYNQ_INTR_CNTRL_ISR isr,
14760 + void *arg1, void *arg2, void *arg3);
14761 +
14762 +int vlynq_uninstall_isr( VLYNQ_DEV *pdev,
14763 + unsigned int map_vector,
14764 + void *arg1, void *arg2, void *arg3);
14765 +
14766 +
14767 +void vlynq_root_isr(void *arg);
14768 +
14769 +void vlynq_delay(unsigned int clktime);
14770 +
14771 +/* The following functions, provide better granularity in setting
14772 + * interrupt parameters. (for better support of linux INT Controller)
14773 + * Note: The interrupt source is identified by "map_vector"- the bit
14774 + * position in interrupt status register*/
14775 +
14776 +int vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
14777 + VLYNQ_DEV_TYPE dev,
14778 + unsigned int int_vector,
14779 + unsigned int map_vector);
14780 +
14781 +int vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
14782 + VLYNQ_DEV_TYPE dev,
14783 + unsigned int map_vector,
14784 + VLYNQ_INTR_POLARITY pol);
14785 +
14786 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
14787 + VLYNQ_DEV_TYPE dev_type,
14788 + unsigned int map_vector);
14789 +
14790 +int vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
14791 + VLYNQ_DEV_TYPE dev,
14792 + unsigned int map_vector,
14793 + VLYNQ_INTR_TYPE type);
14794 +
14795 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
14796 + VLYNQ_DEV_TYPE dev_type,
14797 + unsigned int map_vector);
14798 +
14799 +int vlynq_interrupt_enable(VLYNQ_DEV* pdev,
14800 + VLYNQ_DEV_TYPE dev,
14801 + unsigned int map_vector);
14802 +
14803 +int vlynq_interrupt_disable(VLYNQ_DEV * pdev,
14804 + VLYNQ_DEV_TYPE dev,
14805 + unsigned int map_vector);
14806 +
14807 +
14808 +
14809 +
14810 +
14811 +#endif /* _VLYNQ_HAL_H_ */
14812 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal.h linux.dev/include/asm-mips/ar7/vlynq_hal.h
14813 --- linux.old/include/asm-mips/ar7/vlynq_hal.h 1970-01-01 01:00:00.000000000 +0100
14814 +++ linux.dev/include/asm-mips/ar7/vlynq_hal.h 2005-11-10 01:10:46.095590250 +0100
14815 @@ -0,0 +1,606 @@
14816 +/***************************************************************************
14817 +**+----------------------------------------------------------------------+**
14818 +**| **** |**
14819 +**| **** |**
14820 +**| ******o*** |**
14821 +**| ********_///_**** |**
14822 +**| ***** /_//_/ **** |**
14823 +**| ** ** (__/ **** |**
14824 +**| ********* |**
14825 +**| **** |**
14826 +**| *** |**
14827 +**| |**
14828 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
14829 +**| ALL RIGHTS RESERVED |**
14830 +**| |**
14831 +**| Permission is hereby granted to licensees of Texas Instruments |**
14832 +**| Incorporated (TI) products to use this computer program for the sole |**
14833 +**| purpose of implementing a licensee product based on TI products. |**
14834 +**| No other rights to reproduce, use, or disseminate this computer |**
14835 +**| program, whether in part or in whole, are granted. |**
14836 +**| |**
14837 +**| TI makes no representation or warranties with respect to the |**
14838 +**| performance of this computer program, and specifically disclaims |**
14839 +**| any responsibility for any damages, special or consequential, |**
14840 +**| connected with the use of this program. |**
14841 +**| |**
14842 +**+----------------------------------------------------------------------+**
14843 +***************************************************************************/
14844 +
14845 +/*********************************************************************************
14846 + * ------------------------------------------------------------------------------
14847 + * Module : vlynq_hal.h
14848 + * Description :
14849 + * This header file provides the set of functions exported by the
14850 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
14851 + * ------------------------------------------------------------------------------
14852 + *********************************************************************************/
14853 +
14854 +#ifndef _VLYNQ_HAL_H_
14855 +#define _VLYNQ_HAL_H_
14856 +
14857 +#include <asm/ar7/avalanche_types.h>
14858 +#include <asm/ar7/vlynq_hal_params.h>
14859 +
14860 +#ifndef PRIVATE
14861 +#define PRIVATE static
14862 +#endif
14863 +
14864 +#ifndef GLOBAL
14865 +#define GLOBAL
14866 +#endif
14867 +
14868 +/* Enable/Disable debug feature */
14869 +#undef VLYNQ_DEBUG
14870 +
14871 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
14872 +#define debugPrint(format,args...)
14873 +#else
14874 +#define debugPrint(format,args...)
14875 +#endif
14876 +
14877 +/* Error defines */
14878 +#define VLYNQ_SUCCESS 0
14879 +
14880 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
14881 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
14882 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
14883 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
14884 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
14885 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
14886 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
14887 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
14888 +
14889 +/* Vlynq Defines and Macros */
14890 +
14891 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
14892 +
14893 +/* Base address of module */
14894 +#define VLYNQ_BASE (pdev->module_base)
14895 +
14896 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
14897 +
14898 +#define VLYNQ_REV_OFFSET 0x0000
14899 +#define VLYNQ_CTRL_OFFSET 0x0004
14900 +#define VLYNQ_STATUS_OFFSET 0x0008
14901 +#define VLYNQ_INT_STAT_OFFSET 0x0010
14902 +#define VLYNQ_INT_PEND_OFFSET 0x0014
14903 +#define VLYNQ_INT_PTR_OFFSET 0x0018
14904 +#define VLYNQ_TXMAP_OFFSET 0x001c
14905 +
14906 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
14907 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
14908 +
14909 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
14910 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
14911 +
14912 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
14913 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
14914 +
14915 +#define VLYNQ_REV_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
14916 +#define VLYNQ_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
14917 +#define VLYNQ_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
14918 +#define VLYNQ_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
14919 +#define VLYNQ_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
14920 +#define VLYNQ_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
14921 +#define VLYNQ_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
14922 +
14923 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14924 +#define VLYNQ_RXMAP_SIZE_REG(map) \
14925 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
14926 +
14927 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14928 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
14929 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
14930 +
14931 +#define VLYNQ_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
14932 +
14933 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
14934 +#define VLYNQ_IVR_OFFSET(ivr) \
14935 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
14936 +
14937 +#define VLYNQ_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(0)) )
14938 +#define VLYNQ_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(4)) )
14939 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14940 +
14941 +#define VLYNQ_IVR_INTEN(ivr) (((UINT32)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
14942 +#define VLYNQ_IVR_INTTYPE(ivr) (((UINT32)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
14943 +#define VLYNQ_IVR_INTPOL(ivr) (((UINT32)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
14944 +#define VLYNQ_IVR_INTVEC(ivr) (((UINT32)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
14945 +#define VLYNQ_IVR_INTALL(ivr) (((UINT32)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
14946 +
14947 +
14948 +
14949 +/*********************************
14950 + * Remote VLYNQ register set *
14951 + *********************************/
14952 +
14953 +#define VLYNQ_R_REV_OFFSET 0x0080
14954 +#define VLYNQ_R_CTRL_OFFSET 0x0084
14955 +#define VLYNQ_R_STATUS_OFFSET 0x0088
14956 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
14957 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
14958 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
14959 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
14960 +
14961 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
14962 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
14963 +
14964 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
14965 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
14966 +
14967 +#define VLYNQ_R_REV_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
14968 +#define VLYNQ_R_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
14969 +#define VLYNQ_R_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
14970 +#define VLYNQ_R_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
14971 +#define VLYNQ_R_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
14972 +#define VLYNQ_R_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
14973 +#define VLYNQ_R_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
14974 +
14975 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14976 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
14977 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
14978 +
14979 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14980 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
14981 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
14982 +
14983 +#define VLYNQ_R_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
14984 +
14985 +#define VLYNQ_R_IVR_OFFSET(ivr) \
14986 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
14987 +
14988 +
14989 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14990 +#define VLYNQ_R_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(0)) )
14991 +#define VLYNQ_R_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(4)) )
14992 +
14993 +
14994 +/****End of remote register set definition******/
14995 +
14996 +
14997 +/*** Masks for individual register fields ***/
14998 +
14999 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
15000 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
15001 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
15002 +
15003 +
15004 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
15005 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
15006 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
15007 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
15008 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
15009 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
15010 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
15011 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
15012 +
15013 +
15014 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
15015 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
15016 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
15017 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
15018 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
15019 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
15020 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
15021 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
15022 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
15023 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
15024 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
15025 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
15026 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
15027 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
15028 +
15029 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
15030 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
15031 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
15032 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
15033 +
15034 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
15035 +
15036 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
15037 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
15038 +
15039 +#define VLYNQ_IVR_INTEN_MASK 0x80
15040 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
15041 +#define VLYNQ_IVR_INTPOL_MASK 0x20
15042 +
15043 +
15044 +/**** Helper macros ****/
15045 +
15046 +#define VLYNQ_RESETCB(arg) \
15047 + if( pdev->reset_cb != NULL) \
15048 + { \
15049 + (pdev->reset_cb)(pdev, (arg)); \
15050 + }
15051 +
15052 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
15053 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
15054 +
15055 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
15056 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
15057 +
15058 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
15059 +
15060 +
15061 +/*************************************
15062 + * Enums *
15063 + *************************************/
15064 +
15065 +/* Initialization options define what operations are
15066 + * undertaken during vlynq module initialization */
15067 +typedef enum
15068 +{
15069 + /* Init host local memory regions.This allows
15070 + * local host access remote memory regions */
15071 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
15072 + /* Init host remote memory regions.This allows
15073 + * remote device access local memory regions */
15074 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
15075 + /* Init local interrupt config*/
15076 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
15077 + /* Init remote interrupt config*/
15078 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
15079 + /* Check link during initialization*/
15080 + VLYNQ_INIT_CHECK_LINK =0x10,
15081 + /* configure clock during init */
15082 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
15083 + /* Clear errors during init */
15084 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
15085 + /* All options */
15086 + VLYNQ_INIT_PERFORM_ALL =0x7F
15087 +}VLYNQ_INIT_OPTIONS;
15088 +
15089 +
15090 +/* VLYNQ_DEV_TYPE identifies local or remote device */
15091 +typedef enum
15092 +{
15093 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
15094 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
15095 +}VLYNQ_DEV_TYPE;
15096 +
15097 +
15098 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
15099 +typedef enum
15100 +{
15101 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
15102 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
15103 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
15104 +}VLYNQ_CLK_SOURCE;
15105 +
15106 +
15107 +/* VLYNQ_DRV_STATE indicates the current driver state */
15108 +typedef enum
15109 +{
15110 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
15111 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
15112 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
15113 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
15114 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
15115 +}VLYNQ_DRV_STATE;
15116 +
15117 +
15118 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
15119 +typedef enum
15120 +{
15121 + VLYNQ_BUS_WIDTH_3 = 3,
15122 + VLYNQ_BUS_WIDTH_5 = 5,
15123 + VLYNQ_BUS_WIDTH_7 = 7,
15124 + VLYNQ_BUS_WIDTH_9 = 9
15125 +}VLYNQ_BUS_WIDTH;
15126 +
15127 +
15128 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
15129 + * interrupts are processed by the host or passed on to the
15130 + * remote device.
15131 + */
15132 +typedef enum
15133 +{
15134 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
15135 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
15136 +}VLYNQ_LOCAL_INT_CONFIG;
15137 +
15138 +
15139 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
15140 + * interrupts are to be handled by the SOC system ISR
15141 + * or via the vlynq root ISR
15142 + */
15143 +typedef enum
15144 +{
15145 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
15146 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
15147 +}VLYNQ_REMOTE_INT_CONFIG;
15148 +
15149 +
15150 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
15151 +typedef enum
15152 +{
15153 + VLYNQ_INTR_ACTIVE_HIGH = 0,
15154 + VLYNQ_INTR_ACTIVE_LOW = 1
15155 +}VLYNQ_INTR_POLARITY;
15156 +
15157 +
15158 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
15159 +typedef enum
15160 +{
15161 + VLYNQ_INTR_LEVEL = 0,
15162 + VLYNQ_INTR_PULSED = 1
15163 +}VLYNQ_INTR_TYPE;
15164 +
15165 +
15166 +/* VLYNQ_RESET_MODE - vlynq reset mode */
15167 +typedef enum
15168 +{
15169 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
15170 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
15171 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
15172 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
15173 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
15174 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
15175 +}VLYNQ_RESET_MODE;
15176 +
15177 +
15178 +
15179 +/*************************************
15180 + * Typedefs *
15181 + *************************************/
15182 +
15183 +struct VLYNQ_DEV_t; /*forward declaration*/
15184 +
15185 +/*--------Function Pointers defintions -----------*/
15186 +
15187 +/* prototype for interrupt handler definition */
15188 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
15189 +
15190 +typedef void
15191 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
15192 +
15193 +typedef void
15194 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
15195 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
15196 + UINT32 dwStatRegVal); /* Value of the relevant status register */
15197 +
15198 +
15199 +/*-------Structure Definitions------------*/
15200 +
15201 +typedef struct VLYNQ_MEMORY_MAP_t
15202 +{
15203 + UINT32 Txmap;
15204 + UINT32 RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
15205 + UINT32 RxSize[VLYNQ_MAX_MEMORY_REGIONS];
15206 +}VLYNQ_MEMORY_MAP;
15207 +
15208 +
15209 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
15210 + * settings in vlynq Control register */
15211 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
15212 +{
15213 + /* vlynq interrupts handled by host or remote - maps to
15214 + * intLocal bit in vlynq control register */
15215 + VLYNQ_LOCAL_INT_CONFIG intLocal;
15216 +
15217 + /* remote interrupts handled by vlynq isr or host system
15218 + * interrupt controller - maps to the int2Cfg in vlynq
15219 + * control register */
15220 + VLYNQ_REMOTE_INT_CONFIG intRemote;
15221 +
15222 + /* bit in pending/set register used for module interrupts*/
15223 + UINT32 map_vector;
15224 +
15225 + /* used only if remote interrupts are to be handled by system ISR*/
15226 + UINT32 intr_ptr;
15227 +
15228 +}VLYNQ_INTERRUPT_CNTRL;
15229 +
15230 +
15231 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
15232 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
15233 + * table to identify the ISR to be invoked
15234 + */
15235 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
15236 +{
15237 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
15238 + void *arg1 ; /* Arg 1 for the ISR */
15239 + void *arg2 ; /* Arg 2 for the ISR */
15240 + void *arg3 ; /* Arg 3 for the ISR */
15241 + UINT32 isrCount; /* number of ISR invocations so far */
15242 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
15243 +}VLYNQ_INTR_CNTRL_ICB;
15244 +
15245 +/* overlay of vlynq register set */
15246 +typedef struct VLYNQ_REG_SET_t
15247 +{
15248 + UINT32 revision; /*offset : 0x00 */
15249 + UINT32 control; /* 0x04*/
15250 + UINT32 status; /* 0x08*/
15251 + UINT32 pad1; /* 0x0c*/
15252 + UINT32 intStatus; /*0x10*/
15253 + UINT32 intPending; /*0x14*/
15254 + UINT32 intPtr; /*0x18*/
15255 + UINT32 txMap; /*0x1C*/
15256 + UINT32 rxSize1; /*0x20*/
15257 + UINT32 rxOffset1; /*0x24*/
15258 + UINT32 rxSize2; /*0x28*/
15259 + UINT32 rxOffset2; /*0x2C*/
15260 + UINT32 rxSize3; /*0x30*/
15261 + UINT32 rxOffset3; /*0x34*/
15262 + UINT32 rxSize4; /*0x38*/
15263 + UINT32 rxOffset4; /*0x3C*/
15264 + UINT32 chipVersion; /*0x40*/
15265 + UINT32 pad2[8];
15266 + UINT32 ivr30; /*0x60*/
15267 + UINT32 ivr74; /*0x64*/
15268 + UINT32 pad3[7];
15269 +}VLYNQ_REG_SET;
15270 +
15271 +
15272 +typedef struct VLYNQ_DEV_t
15273 +{
15274 + /** module index:1,2,3... used for debugging purposes */
15275 + UINT32 dev_idx;
15276 +
15277 + /*VLYNQ module base address */
15278 + UINT32 module_base;
15279 +
15280 + /* clock source selection */
15281 + VLYNQ_CLK_SOURCE clk_source;
15282 +
15283 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
15284 + UINT32 clk_div;
15285 +
15286 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
15287 + VLYNQ_DRV_STATE state;
15288 +
15289 + /* Valid VLYNQ bus width, filled by driver */
15290 + VLYNQ_BUS_WIDTH width;
15291 +
15292 + /* local memory mapping */
15293 + VLYNQ_MEMORY_MAP local_mem;
15294 +
15295 + /* remote memory mapping */
15296 + VLYNQ_MEMORY_MAP remote_mem;
15297 +
15298 + /* Local module interrupt params */
15299 + VLYNQ_INTERRUPT_CNTRL local_irq;
15300 +
15301 + /* remote module interrupt params */
15302 + VLYNQ_INTERRUPT_CNTRL remote_irq;
15303 +
15304 + /*** ICB related fields **/
15305 +
15306 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
15307 + * expansion slots for shared interrupts*/
15308 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
15309 + VLYNQ_INTR_CNTRL_ICB *freelist;
15310 +
15311 + /* table holding mapping between intVector and the bit position the interrupt
15312 + * is mapped to(mapVector)*/
15313 + INT8 vector_map[32];
15314 +
15315 + /* user callback for vlynq events, NULL if unused */
15316 + VLYNQ_REPORT_CB report_cb;
15317 +
15318 + /* user callback for resetting/realeasing remote device */
15319 + VLYNQ_RESET_REMOTE reset_cb;
15320 +
15321 + /*** Handles provided for direct access to register set if need be
15322 + * Must be intialized to point to appropriate address during
15323 + * vlynq_init */
15324 + volatile VLYNQ_REG_SET * local;
15325 + volatile VLYNQ_REG_SET * remote;
15326 +
15327 + UINT32 intCount; /* number of interrupts generated so far */
15328 + UINT32 isrCount; /* number of ISR invocations so far */
15329 +}VLYNQ_DEV;
15330 +
15331 +
15332 +typedef struct VLYNQ_ISR_ARGS_t
15333 +{
15334 + int irq;
15335 + void * arg;
15336 + void * regset;
15337 +}VLYNQ_ISR_ARGS;
15338 +
15339 +
15340 +/****************************************
15341 + * Function Prototypes *
15342 + * API exported by generic vlynq driver *
15343 + ****************************************/
15344 +/* Initialization function */
15345 +GLOBAL INT32 vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
15346 +
15347 +/* Check vlynq link */
15348 +GLOBAL UINT32 vlynq_link_check( VLYNQ_DEV * pdev);
15349 +
15350 +/* Set interrupt vector in local or remote device */
15351 +GLOBAL INT32 vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
15352 + UINT32 int_vector,
15353 + UINT32 map_vector,
15354 + VLYNQ_DEV_TYPE dev,
15355 + VLYNQ_INTR_POLARITY pol,
15356 + VLYNQ_INTR_TYPE type);
15357 +
15358 +
15359 +GLOBAL INT32 vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
15360 + UINT32 int_vector,
15361 + VLYNQ_DEV_TYPE dev,
15362 + UINT32 enable);
15363 +
15364 +GLOBAL UINT32 vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
15365 + UINT32 map_vector);
15366 +
15367 +GLOBAL INT32 vlynq_install_isr( VLYNQ_DEV *pdev,
15368 + UINT32 map_vector,
15369 + VLYNQ_INTR_CNTRL_ISR isr,
15370 + void *arg1, void *arg2, void *arg3);
15371 +
15372 +GLOBAL INT32 vlynq_uninstall_isr( VLYNQ_DEV *pdev,
15373 + UINT32 map_vector,
15374 + void *arg1, void *arg2, void *arg3);
15375 +
15376 +
15377 +GLOBAL void vlynq_root_isr(void *arg);
15378 +
15379 +GLOBAL void vlynq_delay(UINT32 clktime);
15380 +
15381 +/* The following functions, provide better granularity in setting
15382 + * interrupt parameters. (for better support of linux INT Controller)
15383 + * Note: The interrupt source is identified by "map_vector"- the bit
15384 + * position in interrupt status register*/
15385 +
15386 +GLOBAL INT32 vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
15387 + VLYNQ_DEV_TYPE dev,
15388 + UINT32 int_vector,
15389 + UINT32 map_vector);
15390 +
15391 +GLOBAL INT32 vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
15392 + VLYNQ_DEV_TYPE dev,
15393 + UINT32 map_vector,
15394 + VLYNQ_INTR_POLARITY pol);
15395 +
15396 +GLOBAL INT32 vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
15397 + VLYNQ_DEV_TYPE dev_type,
15398 + UINT32 map_vector);
15399 +
15400 +GLOBAL INT32 vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
15401 + VLYNQ_DEV_TYPE dev,
15402 + UINT32 map_vector,
15403 + VLYNQ_INTR_TYPE type);
15404 +
15405 +GLOBAL INT32 vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
15406 + VLYNQ_DEV_TYPE dev_type,
15407 + UINT32 map_vector);
15408 +
15409 +GLOBAL INT32 vlynq_interrupt_enable(VLYNQ_DEV* pdev,
15410 + VLYNQ_DEV_TYPE dev,
15411 + UINT32 map_vector);
15412 +
15413 +GLOBAL INT32 vlynq_interrupt_disable(VLYNQ_DEV * pdev,
15414 + VLYNQ_DEV_TYPE dev,
15415 + UINT32 map_vector);
15416 +
15417 +
15418 +
15419 +
15420 +
15421 +#endif /* _VLYNQ_HAL_H_ */
15422 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal_params.h linux.dev/include/asm-mips/ar7/vlynq_hal_params.h
15423 --- linux.old/include/asm-mips/ar7/vlynq_hal_params.h 1970-01-01 01:00:00.000000000 +0100
15424 +++ linux.dev/include/asm-mips/ar7/vlynq_hal_params.h 2005-11-10 01:10:46.095590250 +0100
15425 @@ -0,0 +1,50 @@
15426 +/***************************************************************************
15427 +**+----------------------------------------------------------------------+**
15428 +**| **** |**
15429 +**| **** |**
15430 +**| ******o*** |**
15431 +**| ********_///_**** |**
15432 +**| ***** /_//_/ **** |**
15433 +**| ** ** (__/ **** |**
15434 +**| ********* |**
15435 +**| **** |**
15436 +**| *** |**
15437 +**| |**
15438 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
15439 +**| ALL RIGHTS RESERVED |**
15440 +**| |**
15441 +**| Permission is hereby granted to licensees of Texas Instruments |**
15442 +**| Incorporated (TI) products to use this computer program for the sole |**
15443 +**| purpose of implementing a licensee product based on TI products. |**
15444 +**| No other rights to reproduce, use, or disseminate this computer |**
15445 +**| program, whether in part or in whole, are granted. |**
15446 +**| |**
15447 +**| TI makes no representation or warranties with respect to the |**
15448 +**| performance of this computer program, and specifically disclaims |**
15449 +**| any responsibility for any damages, special or consequential, |**
15450 +**| connected with the use of this program. |**
15451 +**| |**
15452 +**+----------------------------------------------------------------------+**
15453 +***************************************************************************/
15454 +
15455 +/* This file defines Vlynq module parameters*/
15456 +
15457 +#ifndef _VLYNQ_HAL_PARAMS_H
15458 +#define _VLYNQ_HAL_PARAMS_H
15459 +
15460 + /* number of VLYNQ memory regions supported */
15461 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
15462 +
15463 + /* Max.number of external interrupt inputs supported by VLYNQ module */
15464 +#define VLYNQ_IVR_MAXIVR 0x08
15465 +
15466 +#define VLYNQ_CLK_DIV_MAX 0x08
15467 +#define VLYNQ_CLK_DIV_MIN 0x01
15468 +
15469 +
15470 +/*** the total number of entries allocated for ICB would be
15471 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
15472 +#define VLYNQ_IVR_CHAIN_SLOTS 10
15473 +
15474 +
15475 +#endif /* _VLYNQ_HAL_PARAMS_H */
15476 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
15477 --- linux.old/include/asm-mips/io.h 2003-08-25 13:44:43.000000000 +0200
15478 +++ linux.dev/include/asm-mips/io.h 2005-11-10 01:14:16.400733500 +0100
15479 @@ -61,9 +61,9 @@
15480 * Change "struct page" to physical address.
15481 */
15482 #ifdef CONFIG_64BIT_PHYS_ADDR
15483 -#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
15484 +#define page_to_phys(page) (((u64)(page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
15485 #else
15486 -#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
15487 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + PHYS_OFFSET)
15488 #endif
15489
15490 #define IO_SPACE_LIMIT 0xffff
15491 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
15492 --- linux.old/include/asm-mips/irq.h 2003-08-25 13:44:43.000000000 +0200
15493 +++ linux.dev/include/asm-mips/irq.h 2005-11-10 01:12:43.950955750 +0100
15494 @@ -14,7 +14,20 @@
15495 #include <linux/config.h>
15496 #include <linux/linkage.h>
15497
15498 +#ifdef CONFIG_AR7
15499 +/* MIPS has 8 irqs
15500 + * AR7 has 40 primary and 32 secondary irqs
15501 + * vlynq0 has 32 irqs
15502 + * vlynq1 has 32 irqs
15503 + */
15504 +#ifdef CONFIG_AR7_VLYNQ
15505 +#define NR_IRQS (80 + 32 * CONFIG_AR7_VLYNQ_PORTS)
15506 +#else
15507 +#define NR_IRQS 80
15508 +#endif
15509 +#else
15510 #define NR_IRQS 128 /* Largest number of ints of all machines. */
15511 +#endif
15512
15513 #ifdef CONFIG_I8259
15514 static inline int irq_cannonicalize(int irq)
15515 diff -urN linux.old/include/asm-mips/mips-boards/prom.h linux.dev/include/asm-mips/mips-boards/prom.h
15516 --- linux.old/include/asm-mips/mips-boards/prom.h 2001-09-09 19:43:02.000000000 +0200
15517 +++ linux.dev/include/asm-mips/mips-boards/prom.h 2005-11-10 01:14:16.436735750 +0100
15518 @@ -33,7 +33,7 @@
15519 extern void prom_init_cmdline(void);
15520 extern void prom_meminit(void);
15521 extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
15522 -extern void prom_free_prom_memory (void);
15523 +extern unsigned long prom_free_prom_memory (void);
15524 extern void mips_display_message(const char *str);
15525 extern void mips_display_word(unsigned int num);
15526 extern int get_ethernet_addr(char *ethernet_addr);
15527 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
15528 --- linux.old/include/asm-mips/page.h 2004-02-18 14:36:32.000000000 +0100
15529 +++ linux.dev/include/asm-mips/page.h 2005-11-10 01:14:16.436735750 +0100
15530 @@ -12,6 +12,7 @@
15531
15532 #include <linux/config.h>
15533 #include <asm/break.h>
15534 +#include <asm/addrspace.h>
15535
15536 #ifdef __KERNEL__
15537
15538 @@ -129,7 +130,7 @@
15539
15540 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
15541 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
15542 -#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
15543 +#define virt_to_page(kaddr) (mem_map + ((__pa(kaddr)-PHYS_OFFSET) >> PAGE_SHIFT))
15544 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
15545
15546 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
15547 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
15548 --- linux.old/include/asm-mips/pgtable-32.h 2004-02-18 14:36:32.000000000 +0100
15549 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-11-10 01:14:16.436735750 +0100
15550 @@ -108,7 +108,7 @@
15551 * and a page entry and page directory to the page they refer to.
15552 */
15553
15554 -#ifdef CONFIG_CPU_VR41XX
15555 +#if defined(CONFIG_CPU_VR41XX)
15556 #define mk_pte(page, pgprot) \
15557 ({ \
15558 pte_t __pte; \
15559 @@ -123,13 +123,14 @@
15560 ({ \
15561 pte_t __pte; \
15562 \
15563 - pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \
15564 - pgprot_val(pgprot); \
15565 + pte_val(__pte) = (((phys_t)(page - mem_map) << PAGE_SHIFT) + \
15566 + PHYS_OFFSET) | pgprot_val(pgprot); \
15567 \
15568 __pte; \
15569 })
15570 #endif
15571
15572 +
15573 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
15574 {
15575 #ifdef CONFIG_CPU_VR41XX
15576 @@ -175,12 +176,12 @@
15577 set_pte(ptep, __pte(0));
15578 }
15579
15580 -#ifdef CONFIG_CPU_VR41XX
15581 +#if defined(CONFIG_CPU_VR41XX)
15582 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
15583 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
15584 #else
15585 -#define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> PAGE_SHIFT))))
15586 -#define __mk_pte(page_nr,pgprot) __pte(((page_nr) << PAGE_SHIFT) | pgprot_val(pgprot))
15587 +#define pte_page(x) (mem_map+((unsigned long)((((x).pte_low-PHYS_OFFSET) >> PAGE_SHIFT))))
15588 +#define __mk_pte(page_nr,pgprot) __pte((((page_nr) << PAGE_SHIFT)+PHYS_OFFSET)|pgprot_val(pgprot))
15589 #endif
15590
15591 #endif
15592 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
15593 --- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
15594 +++ linux.dev/include/asm-mips/serial.h 2005-11-10 01:14:16.436735750 +0100
15595 @@ -65,6 +65,16 @@
15596
15597 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
15598
15599 +#ifdef CONFIG_AR7
15600 +#include <asm/ar7/ar7.h>
15601 +#include <asm/ar7/avalanche_intc.h>
15602 +#define AR7_SERIAL_PORT_DEFNS \
15603 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
15604 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
15605 +#else
15606 +#define AR7_SERIAL_PORT_DEFNS
15607 +#endif
15608 +
15609 #ifdef CONFIG_MIPS_JAZZ
15610 #define _JAZZ_SERIAL_INIT(int, base) \
15611 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
15612 @@ -468,6 +478,7 @@
15613 #endif
15614
15615 #define SERIAL_PORT_DFNS \
15616 + AR7_SERIAL_PORT_DEFNS \
15617 ATLAS_SERIAL_PORT_DEFNS \
15618 AU1000_SERIAL_PORT_DEFNS \
15619 COBALT_SERIAL_PORT_DEFNS \
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